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b43: Handle B43_PHYTYPE_LP in RX path
[linux-2.6-block.git] / drivers / net / wireless / b43 / phy_lp.c
CommitLineData
e63e4363
MB		 1/*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11g LP-PHY driver
5
6c1bb927 6 Copyright (c) 2008-2009 Michael Buesch <mb@bu3sch.de>
e63e4363
MB		 7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING. If not, write to
20 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
21 Boston, MA 02110-1301, USA.
22
23*/
24
25#include "b43.h"
ce1a9ee3 26#include "main.h"
e63e4363
MB		 27#include "phy_lp.h"
28#include "phy_common.h"
6c1bb927 29#include "tables_lpphy.h"
e63e4363
MB		 30
31
588f8377
GS		 32static inline u16 channel2freq_lp(u8 channel)
33{
34 if (channel < 14)
35 return (2407 + 5 * channel);
36 else if (channel == 14)
37 return 2484;
38 else if (channel < 184)
39 return (5000 + 5 * channel);
40 else
41 return (4000 + 5 * channel);
42}
43
44static unsigned int b43_lpphy_op_get_default_chan(struct b43_wldev *dev)
45{
46 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
47 return 1;
48 return 36;
49}
50
e63e4363
MB		 51static int b43_lpphy_op_allocate(struct b43_wldev *dev)
52{
53 struct b43_phy_lp *lpphy;
54
55 lpphy = kzalloc(sizeof(*lpphy), GFP_KERNEL);
56 if (!lpphy)
57 return -ENOMEM;
58 dev->phy.lp = lpphy;
59
e63e4363
MB		 60 return 0;
61}
62
fb11137a 63static void b43_lpphy_op_prepare_structs(struct b43_wldev *dev)
e63e4363 64{
fb11137a
MB		 65 struct b43_phy *phy = &dev->phy;
66 struct b43_phy_lp *lpphy = phy->lp;
e63e4363 67
fb11137a 68 memset(lpphy, 0, sizeof(*lpphy));
e63e4363 69
fb11137a 70 //TODO
e63e4363
MB		 71}
72
fb11137a 73static void b43_lpphy_op_free(struct b43_wldev *dev)
e63e4363
MB		 74{
75 struct b43_phy_lp *lpphy = dev->phy.lp;
76
e63e4363
MB		 77 kfree(lpphy);
78 dev->phy.lp = NULL;
79}
80
84ec167d
GS		 81static void lpphy_read_band_sprom(struct b43_wldev *dev)
82{
83 struct b43_phy_lp *lpphy = dev->phy.lp;
84 struct ssb_bus *bus = dev->dev->bus;
85 u16 cckpo, maxpwr;
86 u32 ofdmpo;
87 int i;
88
89 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
90 lpphy->tx_isolation_med_band = bus->sprom.tri2g;
91 lpphy->bx_arch = bus->sprom.bxa2g;
92 lpphy->rx_pwr_offset = bus->sprom.rxpo2g;
93 lpphy->rssi_vf = bus->sprom.rssismf2g;
94 lpphy->rssi_vc = bus->sprom.rssismc2g;
95 lpphy->rssi_gs = bus->sprom.rssisav2g;
96 lpphy->txpa[0] = bus->sprom.pa0b0;
97 lpphy->txpa[1] = bus->sprom.pa0b1;
98 lpphy->txpa[2] = bus->sprom.pa0b2;
99 maxpwr = bus->sprom.maxpwr_bg;
100 lpphy->max_tx_pwr_med_band = maxpwr;
101 cckpo = bus->sprom.cck2gpo;
102 ofdmpo = bus->sprom.ofdm2gpo;
103 if (cckpo) {
104 for (i = 0; i < 4; i++) {
105 lpphy->tx_max_rate[i] =
106 maxpwr - (ofdmpo & 0xF) * 2;
107 ofdmpo >>= 4;
108 }
109 ofdmpo = bus->sprom.ofdm2gpo;
110 for (i = 4; i < 15; i++) {
111 lpphy->tx_max_rate[i] =
112 maxpwr - (ofdmpo & 0xF) * 2;
113 ofdmpo >>= 4;
114 }
115 } else {
116 ofdmpo &= 0xFF;
117 for (i = 0; i < 4; i++)
118 lpphy->tx_max_rate[i] = maxpwr;
119 for (i = 4; i < 15; i++)
120 lpphy->tx_max_rate[i] = maxpwr - ofdmpo;
121 }
122 } else { /* 5GHz */
123 lpphy->tx_isolation_low_band = bus->sprom.tri5gl;
124 lpphy->tx_isolation_med_band = bus->sprom.tri5g;
125 lpphy->tx_isolation_hi_band = bus->sprom.tri5gh;
126 lpphy->bx_arch = bus->sprom.bxa5g;
127 lpphy->rx_pwr_offset = bus->sprom.rxpo5g;
128 lpphy->rssi_vf = bus->sprom.rssismf5g;
129 lpphy->rssi_vc = bus->sprom.rssismc5g;
130 lpphy->rssi_gs = bus->sprom.rssisav5g;
131 lpphy->txpa[0] = bus->sprom.pa1b0;
132 lpphy->txpa[1] = bus->sprom.pa1b1;
133 lpphy->txpa[2] = bus->sprom.pa1b2;
134 lpphy->txpal[0] = bus->sprom.pa1lob0;
135 lpphy->txpal[1] = bus->sprom.pa1lob1;
136 lpphy->txpal[2] = bus->sprom.pa1lob2;
137 lpphy->txpah[0] = bus->sprom.pa1hib0;
138 lpphy->txpah[1] = bus->sprom.pa1hib1;
139 lpphy->txpah[2] = bus->sprom.pa1hib2;
140 maxpwr = bus->sprom.maxpwr_al;
141 ofdmpo = bus->sprom.ofdm5glpo;
142 lpphy->max_tx_pwr_low_band = maxpwr;
143 for (i = 4; i < 12; i++) {
144 lpphy->tx_max_ratel[i] = maxpwr - (ofdmpo & 0xF) * 2;
145 ofdmpo >>= 4;
146 }
147 maxpwr = bus->sprom.maxpwr_a;
148 ofdmpo = bus->sprom.ofdm5gpo;
149 lpphy->max_tx_pwr_med_band = maxpwr;
150 for (i = 4; i < 12; i++) {
151 lpphy->tx_max_rate[i] = maxpwr - (ofdmpo & 0xF) * 2;
152 ofdmpo >>= 4;
153 }
154 maxpwr = bus->sprom.maxpwr_ah;
155 ofdmpo = bus->sprom.ofdm5ghpo;
156 lpphy->max_tx_pwr_hi_band = maxpwr;
157 for (i = 4; i < 12; i++) {
158 lpphy->tx_max_rateh[i] = maxpwr - (ofdmpo & 0xF) * 2;
159 ofdmpo >>= 4;
160 }
161 }
162}
163
588f8377 164static void lpphy_adjust_gain_table(struct b43_wldev *dev, u32 freq)
c65d6fbf
GS		 165{
166 struct b43_phy_lp *lpphy = dev->phy.lp;
c65d6fbf
GS		 167 u16 temp[3];
168 u16 isolation;
169
170 B43_WARN_ON(dev->phy.rev >= 2);
171
172 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
173 isolation = lpphy->tx_isolation_med_band;
174 else if (freq <= 5320)
175 isolation = lpphy->tx_isolation_low_band;
176 else if (freq <= 5700)
177 isolation = lpphy->tx_isolation_med_band;
178 else
179 isolation = lpphy->tx_isolation_hi_band;
180
181 temp[0] = ((isolation - 26) / 12) << 12;
182 temp[1] = temp[0] + 0x1000;
183 temp[2] = temp[0] + 0x2000;
184
185 b43_lptab_write_bulk(dev, B43_LPTAB16(12, 0), 3, temp);
186 b43_lptab_write_bulk(dev, B43_LPTAB16(13, 0), 3, temp);
187}
188
a387cc7d
MB		 189static void lpphy_table_init(struct b43_wldev *dev)
190{
588f8377
GS		 191 u32 freq = channel2freq_lp(b43_lpphy_op_get_default_chan(dev));
192
c65d6fbf
GS		 193 if (dev->phy.rev < 2)
194 lpphy_rev0_1_table_init(dev);
195 else
196 lpphy_rev2plus_table_init(dev);
197
198 lpphy_init_tx_gain_table(dev);
199
200 if (dev->phy.rev < 2)
588f8377 201 lpphy_adjust_gain_table(dev, freq);
a387cc7d
MB		 202}
203
204static void lpphy_baseband_rev0_1_init(struct b43_wldev *dev)
205{
738f0f43
GS		 206 struct ssb_bus *bus = dev->dev->bus;
207 u16 tmp, tmp2;
208
209 if (dev->phy.rev == 1 &&
210 (bus->sprom.boardflags_hi & B43_BFH_FEM_BT)) {
211 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x000A);
212 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0x3F00, 0x0900);
213 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x000A);
214 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0B00);
215 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x000A);
216 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0400);
217 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x000A);
218 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0B00);
219 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_5, 0xFFC0, 0x000A);
220 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_5, 0xC0FF, 0x0900);
221 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_6, 0xFFC0, 0x000A);
222 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_6, 0xC0FF, 0x0B00);
223 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_7, 0xFFC0, 0x000A);
224 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_7, 0xC0FF, 0x0900);
225 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xFFC0, 0x000A);
226 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xC0FF, 0x0B00);
227 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ ||
228 (bus->boardinfo.type == 0x048A) || ((dev->phy.rev == 0) &&
229 (bus->sprom.boardflags_lo & B43_BFL_FEM))) {
230 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0001);
231 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0400);
232 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0001);
233 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0500);
234 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0002);
235 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0800);
236 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0002);
237 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0A00);
238 } else if (dev->phy.rev == 1 ||
239 (bus->sprom.boardflags_lo & B43_BFL_FEM)) {
240 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0004);
241 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0800);
242 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0004);
243 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0C00);
244 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0002);
245 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0100);
246 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0002);
247 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0300);
248 } else {
249 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x000A);
250 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0900);
251 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x000A);
252 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0B00);
253 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0006);
254 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0500);
255 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0006);
256 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0700);
257 }
258 if (dev->phy.rev == 1) {
259 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_5, B43_LPPHY_TR_LOOKUP_1);
260 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_6, B43_LPPHY_TR_LOOKUP_2);
261 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_7, B43_LPPHY_TR_LOOKUP_3);
262 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_8, B43_LPPHY_TR_LOOKUP_4);
263 }
264 if ((bus->sprom.boardflags_hi & B43_BFH_FEM_BT) &&
265 (bus->chip_id == 0x5354) &&
266 (bus->chip_package == SSB_CHIPPACK_BCM4712S)) {
267 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x0006);
268 b43_phy_write(dev, B43_LPPHY_GPIO_SELECT, 0x0005);
269 b43_phy_write(dev, B43_LPPHY_GPIO_OUTEN, 0xFFFF);
7c81e98a 270 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_PR45960W);
738f0f43
GS		 271 }
272 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
273 b43_phy_set(dev, B43_LPPHY_LP_PHY_CTL, 0x8000);
274 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x0040);
275 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0x00FF, 0xA400);
276 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xF0FF, 0x0B00);
277 b43_phy_maskset(dev, B43_LPPHY_SYNCPEAKCNT, 0xFFF8, 0x0007);
278 b43_phy_maskset(dev, B43_LPPHY_DSSS_CONFIRM_CNT, 0xFFF8, 0x0003);
279 b43_phy_maskset(dev, B43_LPPHY_DSSS_CONFIRM_CNT, 0xFFC7, 0x0020);
280 b43_phy_mask(dev, B43_LPPHY_IDLEAFTERPKTRXTO, 0x00FF);
281 } else { /* 5GHz */
282 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0x7FFF);
283 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFBF);
284 }
285 if (dev->phy.rev == 1) {
286 tmp = b43_phy_read(dev, B43_LPPHY_CLIPCTRTHRESH);
287 tmp2 = (tmp & 0x03E0) >> 5;
288 tmp2 |= tmp << 5;
289 b43_phy_write(dev, B43_LPPHY_4C3, tmp2);
290 tmp = b43_phy_read(dev, B43_LPPHY_OFDMSYNCTHRESH0);
291 tmp2 = (tmp & 0x1F00) >> 8;
292 tmp2 |= tmp << 5;
293 b43_phy_write(dev, B43_LPPHY_4C4, tmp2);
294 tmp = b43_phy_read(dev, B43_LPPHY_VERYLOWGAINDB);
295 tmp2 = tmp & 0x00FF;
296 tmp2 |= tmp << 8;
297 b43_phy_write(dev, B43_LPPHY_4C5, tmp2);
298 }
a387cc7d
MB		 299}
300
a3e14f3d
GS		 301static void lpphy_save_dig_flt_state(struct b43_wldev *dev)
302{
303 static const u16 addr[] = {
304 B43_PHY_OFDM(0xC1),
305 B43_PHY_OFDM(0xC2),
306 B43_PHY_OFDM(0xC3),
307 B43_PHY_OFDM(0xC4),
308 B43_PHY_OFDM(0xC5),
309 B43_PHY_OFDM(0xC6),
310 B43_PHY_OFDM(0xC7),
311 B43_PHY_OFDM(0xC8),
312 B43_PHY_OFDM(0xCF),
313 };
314
315 static const u16 coefs[] = {
316 0xDE5E, 0xE832, 0xE331, 0x4D26,
317 0x0026, 0x1420, 0x0020, 0xFE08,
318 0x0008,
319 };
320
321 struct b43_phy_lp *lpphy = dev->phy.lp;
322 int i;
323
324 for (i = 0; i < ARRAY_SIZE(addr); i++) {
325 lpphy->dig_flt_state[i] = b43_phy_read(dev, addr[i]);
326 b43_phy_write(dev, addr[i], coefs[i]);
327 }
328}
329
330static void lpphy_restore_dig_flt_state(struct b43_wldev *dev)
331{
332 static const u16 addr[] = {
333 B43_PHY_OFDM(0xC1),
334 B43_PHY_OFDM(0xC2),
335 B43_PHY_OFDM(0xC3),
336 B43_PHY_OFDM(0xC4),
337 B43_PHY_OFDM(0xC5),
338 B43_PHY_OFDM(0xC6),
339 B43_PHY_OFDM(0xC7),
340 B43_PHY_OFDM(0xC8),
341 B43_PHY_OFDM(0xCF),
342 };
343
344 struct b43_phy_lp *lpphy = dev->phy.lp;
345 int i;
346
347 for (i = 0; i < ARRAY_SIZE(addr); i++)
348 b43_phy_write(dev, addr[i], lpphy->dig_flt_state[i]);
349}
350
a387cc7d
MB		 351static void lpphy_baseband_rev2plus_init(struct b43_wldev *dev)
352{
686aa5f2 353 struct ssb_bus *bus = dev->dev->bus;
6c1bb927
MB		 354 struct b43_phy_lp *lpphy = dev->phy.lp;
355
356 b43_phy_write(dev, B43_LPPHY_AFE_DAC_CTL, 0x50);
357 b43_phy_write(dev, B43_LPPHY_AFE_CTL, 0x8800);
358 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, 0);
359 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0);
360 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, 0);
361 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0);
362 b43_phy_write(dev, B43_PHY_OFDM(0xF9), 0);
363 b43_phy_write(dev, B43_LPPHY_TR_LOOKUP_1, 0);
364 b43_phy_set(dev, B43_LPPHY_ADC_COMPENSATION_CTL, 0x10);
a3e14f3d 365 b43_phy_maskset(dev, B43_LPPHY_OFDMSYNCTHRESH0, 0xFF00, 0xB4);
6c1bb927
MB		 366 b43_phy_maskset(dev, B43_LPPHY_DCOFFSETTRANSIENT, 0xF8FF, 0x200);
367 b43_phy_maskset(dev, B43_LPPHY_DCOFFSETTRANSIENT, 0xFF00, 0x7F);
368 b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xFF0F, 0x40);
369 b43_phy_maskset(dev, B43_LPPHY_PREAMBLECONFIRMTO, 0xFF00, 0x2);
370 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x4000);
371 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x2000);
372 b43_phy_set(dev, B43_PHY_OFDM(0x10A), 0x1);
a3e14f3d
GS		 373 if (bus->boardinfo.rev >= 0x18) {
374 b43_lptab_write(dev, B43_LPTAB32(17, 65), 0xEC);
375 b43_phy_maskset(dev, B43_PHY_OFDM(0x10A), 0xFF01, 0x14);
376 } else {
377 b43_phy_maskset(dev, B43_PHY_OFDM(0x10A), 0xFF01, 0x10);
378 }
6c1bb927 379 b43_phy_maskset(dev, B43_PHY_OFDM(0xDF), 0xFF00, 0xF4);
24b5bcc6 380 b43_phy_maskset(dev, B43_PHY_OFDM(0xDF), 0x00FF, 0xF100);
6c1bb927
MB		 381 b43_phy_write(dev, B43_LPPHY_CLIPTHRESH, 0x48);
382 b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0xFF00, 0x46);
383 b43_phy_maskset(dev, B43_PHY_OFDM(0xE4), 0xFF00, 0x10);
384 b43_phy_maskset(dev, B43_LPPHY_PWR_THRESH1, 0xFFF0, 0x9);
385 b43_phy_mask(dev, B43_LPPHY_GAINDIRECTMISMATCH, ~0xF);
386 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0x00FF, 0x5500);
387 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xF81F, 0xA0);
388 b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xE0FF, 0x300);
389 b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0x00FF, 0x2A00);
686aa5f2
MB		 390 if ((bus->chip_id == 0x4325) && (bus->chip_rev == 0)) {
391 b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x2100);
392 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0xA);
393 } else {
394 b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x1E00);
395 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0xD);
396 }
6c1bb927
MB		 397 b43_phy_maskset(dev, B43_PHY_OFDM(0xFE), 0xFFE0, 0x1F);
398 b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0xFFE0, 0xC);
399 b43_phy_maskset(dev, B43_PHY_OFDM(0x100), 0xFF00, 0x19);
400 b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0x03FF, 0x3C00);
401 b43_phy_maskset(dev, B43_PHY_OFDM(0xFE), 0xFC1F, 0x3E0);
402 b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0xFFE0, 0xC);
403 b43_phy_maskset(dev, B43_PHY_OFDM(0x100), 0x00FF, 0x1900);
404 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0x83FF, 0x5800);
405 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFFE0, 0x12);
406 b43_phy_maskset(dev, B43_LPPHY_GAINMISMATCH, 0x0FFF, 0x9000);
407
a3e14f3d
GS		 408 if ((bus->chip_id == 0x4325) && (bus->chip_rev == 1)) {
409 b43_lptab_write(dev, B43_LPTAB16(0x08, 0x14), 0);
410 b43_lptab_write(dev, B43_LPTAB16(0x08, 0x12), 0x40);
411 }
6c1bb927
MB		 412
413 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
414 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x40);
415 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xF0FF, 0xB00);
416 b43_phy_maskset(dev, B43_LPPHY_SYNCPEAKCNT, 0xFFF8, 0x6);
417 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0x00FF, 0x9D00);
418 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0xFF00, 0xA1);
419 } else /* 5GHz */
420 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x40);
421
422 b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0xFF00, 0xB3);
423 b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0x00FF, 0xAD00);
424 b43_phy_maskset(dev, B43_LPPHY_INPUT_PWRDB, 0xFF00, lpphy->rx_pwr_offset);
425 b43_phy_set(dev, B43_LPPHY_RESET_CTL, 0x44);
426 b43_phy_write(dev, B43_LPPHY_RESET_CTL, 0x80);
427 b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_0, 0xA954);
428 b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_1,
429 0x2000 | ((u16)lpphy->rssi_gs << 10) |
430 ((u16)lpphy->rssi_vc << 4) | lpphy->rssi_vf);
a3e14f3d
GS		 431
432 if ((bus->chip_id == 0x4325) && (bus->chip_rev == 0)) {
433 b43_phy_set(dev, B43_LPPHY_AFE_ADC_CTL_0, 0x1C);
434 b43_phy_maskset(dev, B43_LPPHY_AFE_CTL, 0x00FF, 0x8800);
435 b43_phy_maskset(dev, B43_LPPHY_AFE_ADC_CTL_1, 0xFC3C, 0x0400);
436 }
437
438 lpphy_save_dig_flt_state(dev);
a387cc7d
MB		 439}
440
441static void lpphy_baseband_init(struct b43_wldev *dev)
442{
443 lpphy_table_init(dev);
444 if (dev->phy.rev >= 2)
445 lpphy_baseband_rev2plus_init(dev);
446 else
447 lpphy_baseband_rev0_1_init(dev);
448}
449
24b5bcc6
MB		 450struct b2062_freqdata {
451 u16 freq;
452 u8 data[6];
453};
454
455/* Initialize the 2062 radio. */
456static void lpphy_2062_init(struct b43_wldev *dev)
457{
1e711bee 458 struct b43_phy_lp *lpphy = dev->phy.lp;
99e0fca6 459 struct ssb_bus *bus = dev->dev->bus;
1e711bee 460 u32 crystalfreq, tmp, ref;
24b5bcc6
MB		 461 unsigned int i;
462 const struct b2062_freqdata *fd = NULL;
463
464 static const struct b2062_freqdata freqdata_tab[] = {
465 { .freq = 12000, .data[0] = 6, .data[1] = 6, .data[2] = 6,
466 .data[3] = 6, .data[4] = 10, .data[5] = 6, },
467 { .freq = 13000, .data[0] = 4, .data[1] = 4, .data[2] = 4,
468 .data[3] = 4, .data[4] = 11, .data[5] = 7, },
469 { .freq = 14400, .data[0] = 3, .data[1] = 3, .data[2] = 3,
470 .data[3] = 3, .data[4] = 12, .data[5] = 7, },
471 { .freq = 16200, .data[0] = 3, .data[1] = 3, .data[2] = 3,
472 .data[3] = 3, .data[4] = 13, .data[5] = 8, },
473 { .freq = 18000, .data[0] = 2, .data[1] = 2, .data[2] = 2,
474 .data[3] = 2, .data[4] = 14, .data[5] = 8, },
475 { .freq = 19200, .data[0] = 1, .data[1] = 1, .data[2] = 1,
476 .data[3] = 1, .data[4] = 14, .data[5] = 9, },
477 };
478
479 b2062_upload_init_table(dev);
480
481 b43_radio_write(dev, B2062_N_TX_CTL3, 0);
482 b43_radio_write(dev, B2062_N_TX_CTL4, 0);
483 b43_radio_write(dev, B2062_N_TX_CTL5, 0);
484 b43_radio_write(dev, B2062_N_PDN_CTL0, 0x40);
485 b43_radio_write(dev, B2062_N_PDN_CTL0, 0);
486 b43_radio_write(dev, B2062_N_CALIB_TS, 0x10);
487 b43_radio_write(dev, B2062_N_CALIB_TS, 0);
488 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
489 b43_radio_set(dev, B2062_N_TSSI_CTL0, 0x1);
490 else
491 b43_radio_mask(dev, B2062_N_TSSI_CTL0, ~0x1);
492
99e0fca6
MB		 493 /* Get the crystal freq, in Hz. */
494 crystalfreq = bus->chipco.pmu.crystalfreq * 1000;
495
496 B43_WARN_ON(!(bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU));
497 B43_WARN_ON(crystalfreq == 0);
24b5bcc6
MB		 498
499 if (crystalfreq >= 30000000) {
1e711bee 500 lpphy->pdiv = 1;
24b5bcc6
MB		 501 b43_radio_mask(dev, B2062_S_RFPLL_CTL1, 0xFFFB);
502 } else {
1e711bee 503 lpphy->pdiv = 2;
24b5bcc6
MB		 504 b43_radio_set(dev, B2062_S_RFPLL_CTL1, 0x4);
505 }
506
1e711bee
GS		 507 tmp = (800000000 * lpphy->pdiv + crystalfreq) /
508 (32000000 * lpphy->pdiv);
24b5bcc6
MB		 509 tmp = (tmp - 1) & 0xFF;
510 b43_radio_write(dev, B2062_S_RFPLL_CTL18, tmp);
511
1e711bee
GS		 512 tmp = (2 * crystalfreq + 1000000 * lpphy->pdiv) /
513 (2000000 * lpphy->pdiv);
24b5bcc6
MB		 514 tmp = ((tmp & 0xFF) - 1) & 0xFFFF;
515 b43_radio_write(dev, B2062_S_RFPLL_CTL19, tmp);
516
1e711bee 517 ref = (1000 * lpphy->pdiv + 2 * crystalfreq) / (2000 * lpphy->pdiv);
24b5bcc6
MB		 518 ref &= 0xFFFF;
519 for (i = 0; i < ARRAY_SIZE(freqdata_tab); i++) {
520 if (ref < freqdata_tab[i].freq) {
521 fd = &freqdata_tab[i];
522 break;
523 }
524 }
99e0fca6
MB		 525 if (!fd)
526 fd = &freqdata_tab[ARRAY_SIZE(freqdata_tab) - 1];
527 b43dbg(dev->wl, "b2062: Using crystal tab entry %u kHz.\n",
528 fd->freq); /* FIXME: Keep this printk until the code is fully debugged. */
24b5bcc6
MB		 529
530 b43_radio_write(dev, B2062_S_RFPLL_CTL8,
531 ((u16)(fd->data[1]) << 4) | fd->data[0]);
532 b43_radio_write(dev, B2062_S_RFPLL_CTL9,
99e0fca6 533 ((u16)(fd->data[3]) << 4) | fd->data[2]);
24b5bcc6
MB		 534 b43_radio_write(dev, B2062_S_RFPLL_CTL10, fd->data[4]);
535 b43_radio_write(dev, B2062_S_RFPLL_CTL11, fd->data[5]);
536}
537
538/* Initialize the 2063 radio. */
539static void lpphy_2063_init(struct b43_wldev *dev)
a387cc7d 540{
c10e47f4
GS		 541 b2063_upload_init_table(dev);
542 b43_radio_write(dev, B2063_LOGEN_SP5, 0);
543 b43_radio_set(dev, B2063_COMM8, 0x38);
544 b43_radio_write(dev, B2063_REG_SP1, 0x56);
545 b43_radio_mask(dev, B2063_RX_BB_CTL2, ~0x2);
546 b43_radio_write(dev, B2063_PA_SP7, 0);
547 b43_radio_write(dev, B2063_TX_RF_SP6, 0x20);
548 b43_radio_write(dev, B2063_TX_RF_SP9, 0x40);
549 b43_radio_write(dev, B2063_PA_SP3, 0xa0);
550 b43_radio_write(dev, B2063_PA_SP4, 0xa0);
551 b43_radio_write(dev, B2063_PA_SP2, 0x18);
a387cc7d
MB		 552}
553
3281d95d
GS		 554struct lpphy_stx_table_entry {
555 u16 phy_offset;
556 u16 phy_shift;
557 u16 rf_addr;
558 u16 rf_shift;
559 u16 mask;
560};
561
562static const struct lpphy_stx_table_entry lpphy_stx_table[] = {
563 { .phy_offset = 2, .phy_shift = 6, .rf_addr = 0x3d, .rf_shift = 3, .mask = 0x01, },
564 { .phy_offset = 1, .phy_shift = 12, .rf_addr = 0x4c, .rf_shift = 1, .mask = 0x01, },
565 { .phy_offset = 1, .phy_shift = 8, .rf_addr = 0x50, .rf_shift = 0, .mask = 0x7f, },
566 { .phy_offset = 0, .phy_shift = 8, .rf_addr = 0x44, .rf_shift = 0, .mask = 0xff, },
567 { .phy_offset = 1, .phy_shift = 0, .rf_addr = 0x4a, .rf_shift = 0, .mask = 0xff, },
568 { .phy_offset = 0, .phy_shift = 4, .rf_addr = 0x4d, .rf_shift = 0, .mask = 0xff, },
569 { .phy_offset = 1, .phy_shift = 4, .rf_addr = 0x4e, .rf_shift = 0, .mask = 0xff, },
570 { .phy_offset = 0, .phy_shift = 12, .rf_addr = 0x4f, .rf_shift = 0, .mask = 0x0f, },
571 { .phy_offset = 1, .phy_shift = 0, .rf_addr = 0x4f, .rf_shift = 4, .mask = 0x0f, },
572 { .phy_offset = 3, .phy_shift = 0, .rf_addr = 0x49, .rf_shift = 0, .mask = 0x0f, },
573 { .phy_offset = 4, .phy_shift = 3, .rf_addr = 0x46, .rf_shift = 4, .mask = 0x07, },
574 { .phy_offset = 3, .phy_shift = 15, .rf_addr = 0x46, .rf_shift = 0, .mask = 0x01, },
575 { .phy_offset = 4, .phy_shift = 0, .rf_addr = 0x46, .rf_shift = 1, .mask = 0x07, },
576 { .phy_offset = 3, .phy_shift = 8, .rf_addr = 0x48, .rf_shift = 4, .mask = 0x07, },
577 { .phy_offset = 3, .phy_shift = 11, .rf_addr = 0x48, .rf_shift = 0, .mask = 0x0f, },
578 { .phy_offset = 3, .phy_shift = 4, .rf_addr = 0x49, .rf_shift = 4, .mask = 0x0f, },
579 { .phy_offset = 2, .phy_shift = 15, .rf_addr = 0x45, .rf_shift = 0, .mask = 0x01, },
580 { .phy_offset = 5, .phy_shift = 13, .rf_addr = 0x52, .rf_shift = 4, .mask = 0x07, },
581 { .phy_offset = 6, .phy_shift = 0, .rf_addr = 0x52, .rf_shift = 7, .mask = 0x01, },
582 { .phy_offset = 5, .phy_shift = 3, .rf_addr = 0x41, .rf_shift = 5, .mask = 0x07, },
583 { .phy_offset = 5, .phy_shift = 6, .rf_addr = 0x41, .rf_shift = 0, .mask = 0x0f, },
584 { .phy_offset = 5, .phy_shift = 10, .rf_addr = 0x42, .rf_shift = 5, .mask = 0x07, },
585 { .phy_offset = 4, .phy_shift = 15, .rf_addr = 0x42, .rf_shift = 0, .mask = 0x01, },
586 { .phy_offset = 5, .phy_shift = 0, .rf_addr = 0x42, .rf_shift = 1, .mask = 0x07, },
587 { .phy_offset = 4, .phy_shift = 11, .rf_addr = 0x43, .rf_shift = 4, .mask = 0x0f, },
588 { .phy_offset = 4, .phy_shift = 7, .rf_addr = 0x43, .rf_shift = 0, .mask = 0x0f, },
589 { .phy_offset = 4, .phy_shift = 6, .rf_addr = 0x45, .rf_shift = 1, .mask = 0x01, },
590 { .phy_offset = 2, .phy_shift = 7, .rf_addr = 0x40, .rf_shift = 4, .mask = 0x0f, },
591 { .phy_offset = 2, .phy_shift = 11, .rf_addr = 0x40, .rf_shift = 0, .mask = 0x0f, },
592};
593
24b5bcc6
MB		 594static void lpphy_sync_stx(struct b43_wldev *dev)
595{
3281d95d
GS		 596 const struct lpphy_stx_table_entry *e;
597 unsigned int i;
598 u16 tmp;
599
600 for (i = 0; i < ARRAY_SIZE(lpphy_stx_table); i++) {
601 e = &lpphy_stx_table[i];
602 tmp = b43_radio_read(dev, e->rf_addr);
603 tmp >>= e->rf_shift;
604 tmp <<= e->phy_shift;
605 b43_phy_maskset(dev, B43_PHY_OFDM(0xF2 + e->phy_offset),
d44517f2 606 ~(e->mask << e->phy_shift), tmp);
3281d95d 607 }
24b5bcc6
MB		 608}
609
610static void lpphy_radio_init(struct b43_wldev *dev)
611{
612 /* The radio is attached through the 4wire bus. */
613 b43_phy_set(dev, B43_LPPHY_FOURWIRE_CTL, 0x2);
614 udelay(1);
615 b43_phy_mask(dev, B43_LPPHY_FOURWIRE_CTL, 0xFFFD);
616 udelay(1);
617
618 if (dev->phy.rev < 2) {
619 lpphy_2062_init(dev);
620 } else {
621 lpphy_2063_init(dev);
622 lpphy_sync_stx(dev);
623 b43_phy_write(dev, B43_PHY_OFDM(0xF0), 0x5F80);
624 b43_phy_write(dev, B43_PHY_OFDM(0xF1), 0);
3281d95d
GS		 625 if (dev->dev->bus->chip_id == 0x4325) {
626 // TODO SSB PMU recalibration
627 }
24b5bcc6
MB		 628 }
629}
630
560ad81b
GS		 631struct lpphy_iq_est { u32 iq_prod, i_pwr, q_pwr; };
632
d4de9532
GS		 633static void lpphy_set_rc_cap(struct b43_wldev *dev)
634{
635 u8 rc_cap = dev->phy.lp->rc_cap;
636
637 b43_radio_write(dev, B2062_N_RXBB_CALIB2, max_t(u8, rc_cap-4, 0x80));
638 b43_radio_write(dev, B2062_N_TX_CTL_A, ((rc_cap & 0x1F) >> 1) | 0x80);
639 b43_radio_write(dev, B2062_S_RXG_CNT16, ((rc_cap & 0x1F) >> 2) | 0x80);
640}
641
560ad81b 642static u8 lpphy_get_bb_mult(struct b43_wldev *dev)
d4de9532 643{
560ad81b 644 return (b43_lptab_read(dev, B43_LPTAB16(0, 87)) & 0xFF00) >> 8;
d4de9532
GS		 645}
646
560ad81b 647static void lpphy_set_bb_mult(struct b43_wldev *dev, u8 bb_mult)
d4de9532 648{
560ad81b
GS		 649 b43_lptab_write(dev, B43_LPTAB16(0, 87), (u16)bb_mult << 8);
650}
d4de9532 651
560ad81b
GS		 652static void lpphy_disable_crs(struct b43_wldev *dev)
653{
654 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFF1F, 0x80);
655 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFC, 0x1);
656 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x3);
657 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFB);
658 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x4);
659 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFF7);
660 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x8);
661 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x10);
662 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x10);
663 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFDF);
664 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x20);
665 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFBF);
666 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x40);
667 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0x7);
668 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0x38);
669 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFF3F);
670 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0x100);
671 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFDFF);
672 b43_phy_write(dev, B43_LPPHY_PS_CTL_OVERRIDE_VAL0, 0);
673 b43_phy_write(dev, B43_LPPHY_PS_CTL_OVERRIDE_VAL1, 1);
674 b43_phy_write(dev, B43_LPPHY_PS_CTL_OVERRIDE_VAL2, 0x20);
675 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFBFF);
676 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xF7FF);
677 b43_phy_write(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL, 0);
678 b43_phy_write(dev, B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL, 0x45AF);
679 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0x3FF);
680}
d4de9532 681
560ad81b
GS		 682static void lpphy_restore_crs(struct b43_wldev *dev)
683{
684 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
685 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFF1F, 0x60);
686 else
687 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFF1F, 0x20);
688 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFF80);
689 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFC00);
690}
691
692struct lpphy_tx_gains { u16 gm, pga, pad, dac; };
693
694static struct lpphy_tx_gains lpphy_get_tx_gains(struct b43_wldev *dev)
695{
696 struct lpphy_tx_gains gains;
697 u16 tmp;
698
699 gains.dac = (b43_phy_read(dev, B43_LPPHY_AFE_DAC_CTL) & 0x380) >> 7;
700 if (dev->phy.rev < 2) {
701 tmp = b43_phy_read(dev,
702 B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL) & 0x7FF;
703 gains.gm = tmp & 0x0007;
704 gains.pga = (tmp & 0x0078) >> 3;
705 gains.pad = (tmp & 0x780) >> 7;
706 } else {
707 tmp = b43_phy_read(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL);
708 gains.pad = b43_phy_read(dev, B43_PHY_OFDM(0xFB)) & 0xFF;
709 gains.gm = tmp & 0xFF;
710 gains.pga = (tmp >> 8) & 0xFF;
d4de9532
GS		 711 }
712
560ad81b
GS		 713 return gains;
714}
d4de9532 715
560ad81b
GS		 716static void lpphy_set_dac_gain(struct b43_wldev *dev, u16 dac)
717{
718 u16 ctl = b43_phy_read(dev, B43_LPPHY_AFE_DAC_CTL) & 0xC7F;
719 ctl |= dac << 7;
720 b43_phy_maskset(dev, B43_LPPHY_AFE_DAC_CTL, 0xF000, ctl);
721}
d4de9532 722
560ad81b
GS		 723static void lpphy_set_tx_gains(struct b43_wldev *dev,
724 struct lpphy_tx_gains gains)
725{
726 u16 rf_gain, pa_gain;
d4de9532 727
560ad81b
GS		 728 if (dev->phy.rev < 2) {
729 rf_gain = (gains.pad << 7) | (gains.pga << 3) | gains.gm;
730 b43_phy_maskset(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL,
731 0xF800, rf_gain);
d4de9532 732 } else {
560ad81b
GS		 733 pa_gain = b43_phy_read(dev, B43_PHY_OFDM(0xFB)) & 0x7F00;
734 b43_phy_write(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL,
735 (gains.pga << 8) | gains.gm);
736 b43_phy_maskset(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL,
737 0x8000, gains.pad | pa_gain);
738 b43_phy_write(dev, B43_PHY_OFDM(0xFC),
739 (gains.pga << 8) | gains.gm);
740 b43_phy_maskset(dev, B43_PHY_OFDM(0xFD),
741 0x8000, gains.pad | pa_gain);
d4de9532 742 }
560ad81b
GS		 743 lpphy_set_dac_gain(dev, gains.dac);
744 if (dev->phy.rev < 2) {
745 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF, 1 << 8);
746 } else {
747 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFF7F, 1 << 7);
748 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2, 0xBFFF, 1 << 14);
749 }
16373f65 750 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFFBF, 1 << 6);
560ad81b 751}
d4de9532 752
560ad81b
GS		 753static void lpphy_rev0_1_set_rx_gain(struct b43_wldev *dev, u32 gain)
754{
755 u16 trsw = gain & 0x1;
756 u16 lna = (gain & 0xFFFC) | ((gain & 0xC) >> 2);
757 u16 ext_lna = (gain & 2) >> 1;
758
759 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFE, trsw);
760 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
761 0xFBFF, ext_lna << 10);
762 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
763 0xF7FF, ext_lna << 11);
764 b43_phy_write(dev, B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL, lna);
765}
d4de9532 766
560ad81b
GS		 767static void lpphy_rev2plus_set_rx_gain(struct b43_wldev *dev, u32 gain)
768{
769 u16 low_gain = gain & 0xFFFF;
770 u16 high_gain = (gain >> 16) & 0xF;
771 u16 ext_lna = (gain >> 21) & 0x1;
772 u16 trsw = ~(gain >> 20) & 0x1;
773 u16 tmp;
774
775 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFE, trsw);
776 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
777 0xFDFF, ext_lna << 9);
778 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
779 0xFBFF, ext_lna << 10);
780 b43_phy_write(dev, B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL, low_gain);
781 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFFF0, high_gain);
782 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
783 tmp = (gain >> 2) & 0x3;
784 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
785 0xE7FF, tmp<<11);
786 b43_phy_maskset(dev, B43_PHY_OFDM(0xE6), 0xFFE7, tmp << 3);
787 }
788}
789
790static void lpphy_enable_rx_gain_override(struct b43_wldev *dev)
791{
792 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFFE);
793 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFEF);
794 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFBF);
795 if (dev->phy.rev >= 2) {
796 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF);
797 if (b43_current_band(dev->wl) != IEEE80211_BAND_2GHZ)
798 return;
799 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFBFF);
800 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFFF7);
801 } else {
802 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFDFF);
803 }
804}
805
806static void lpphy_disable_rx_gain_override(struct b43_wldev *dev)
807{
808 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x1);
809 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x10);
810 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x40);
811 if (dev->phy.rev >= 2) {
812 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x100);
813 if (b43_current_band(dev->wl) != IEEE80211_BAND_2GHZ)
814 return;
815 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x400);
816 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x8);
817 } else {
818 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x200);
819 }
820}
821
822static void lpphy_set_rx_gain(struct b43_wldev *dev, u32 gain)
823{
824 if (dev->phy.rev < 2)
825 lpphy_rev0_1_set_rx_gain(dev, gain);
826 else
827 lpphy_rev2plus_set_rx_gain(dev, gain);
828 lpphy_enable_rx_gain_override(dev);
829}
830
831static void lpphy_set_rx_gain_by_index(struct b43_wldev *dev, u16 idx)
832{
833 u32 gain = b43_lptab_read(dev, B43_LPTAB16(12, idx));
834 lpphy_set_rx_gain(dev, gain);
835}
836
837static void lpphy_stop_ddfs(struct b43_wldev *dev)
838{
839 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS, 0xFFFD);
840 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0xFFDF);
841}
842
843static void lpphy_run_ddfs(struct b43_wldev *dev, int i_on, int q_on,
844 int incr1, int incr2, int scale_idx)
845{
846 lpphy_stop_ddfs(dev);
847 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS_POINTER_INIT, 0xFF80);
848 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS_POINTER_INIT, 0x80FF);
849 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS_INCR_INIT, 0xFF80, incr1);
850 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS_INCR_INIT, 0x80FF, incr2 << 8);
851 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFFF7, i_on << 3);
852 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFFEF, q_on << 4);
853 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFF9F, scale_idx << 5);
854 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS, 0xFFFB);
855 b43_phy_set(dev, B43_LPPHY_AFE_DDFS, 0x2);
856 b43_phy_set(dev, B43_LPPHY_AFE_DDFS, 0x20);
857}
858
859static bool lpphy_rx_iq_est(struct b43_wldev *dev, u16 samples, u8 time,
860 struct lpphy_iq_est *iq_est)
861{
862 int i;
863
864 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFF7);
865 b43_phy_write(dev, B43_LPPHY_IQ_NUM_SMPLS_ADDR, samples);
866 b43_phy_maskset(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0xFF00, time);
867 b43_phy_mask(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0xFEFF);
868 b43_phy_set(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0xFDFF);
869
870 for (i = 0; i < 500; i++) {
871 if (!(b43_phy_read(dev,
872 B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR) & 0x200))
d4de9532
GS		 873 break;
874 msleep(1);
875 }
876
560ad81b
GS		 877 if ((b43_phy_read(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR) & 0x200)) {
878 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x8);
879 return false;
880 }
d4de9532 881
560ad81b
GS		 882 iq_est->iq_prod = b43_phy_read(dev, B43_LPPHY_IQ_ACC_HI_ADDR);
883 iq_est->iq_prod <<= 16;
884 iq_est->iq_prod |= b43_phy_read(dev, B43_LPPHY_IQ_ACC_LO_ADDR);
885
886 iq_est->i_pwr = b43_phy_read(dev, B43_LPPHY_IQ_I_PWR_ACC_HI_ADDR);
887 iq_est->i_pwr <<= 16;
888 iq_est->i_pwr |= b43_phy_read(dev, B43_LPPHY_IQ_I_PWR_ACC_LO_ADDR);
889
890 iq_est->q_pwr = b43_phy_read(dev, B43_LPPHY_IQ_Q_PWR_ACC_HI_ADDR);
891 iq_est->q_pwr <<= 16;
892 iq_est->q_pwr |= b43_phy_read(dev, B43_LPPHY_IQ_Q_PWR_ACC_LO_ADDR);
893
894 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x8);
895 return true;
d4de9532
GS		 896}
897
560ad81b 898static int lpphy_loopback(struct b43_wldev *dev)
d4de9532 899{
560ad81b
GS		 900 struct lpphy_iq_est iq_est;
901 int i, index = -1;
902 u32 tmp;
903
904 memset(&iq_est, 0, sizeof(iq_est));
905
906 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFC, 0x3);
907 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x3);
908 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xFFFE);
909 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x800);
910 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x800);
911 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x8);
912 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x8);
913 b43_radio_write(dev, B2062_N_TX_CTL_A, 0x80);
914 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x80);
915 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x80);
916 for (i = 0; i < 32; i++) {
917 lpphy_set_rx_gain_by_index(dev, i);
918 lpphy_run_ddfs(dev, 1, 1, 5, 5, 0);
919 if (!(lpphy_rx_iq_est(dev, 1000, 32, &iq_est)))
920 continue;
921 tmp = (iq_est.i_pwr + iq_est.q_pwr) / 1000;
922 if ((tmp > 4000) && (tmp < 10000)) {
923 index = i;
924 break;
925 }
926 }
927 lpphy_stop_ddfs(dev);
928 return index;
929}
d4de9532 930
560ad81b
GS		 931static u32 lpphy_qdiv_roundup(u32 dividend, u32 divisor, u8 precision)
932{
933 u32 quotient, remainder, rbit, roundup, tmp;
934
935 if (divisor == 0) {
936 quotient = 0;
937 remainder = 0;
d4de9532 938 } else {
560ad81b
GS		 939 quotient = dividend / divisor;
940 remainder = dividend % divisor;
d4de9532 941 }
560ad81b
GS		 942
943 rbit = divisor & 0x1;
944 roundup = (divisor >> 1) + rbit;
945 precision--;
946
947 while (precision != 0xFF) {
948 tmp = remainder - roundup;
949 quotient <<= 1;
950 remainder <<= 1;
951 if (remainder >= roundup) {
952 remainder = (tmp << 1) + rbit;
953 quotient--;
954 }
955 precision--;
956 }
957
958 if (remainder >= roundup)
959 quotient++;
960
961 return quotient;
d4de9532
GS		 962}
963
ce1a9ee3
MB		 964/* Read the TX power control mode from hardware. */
965static void lpphy_read_tx_pctl_mode_from_hardware(struct b43_wldev *dev)
966{
967 struct b43_phy_lp *lpphy = dev->phy.lp;
968 u16 ctl;
969
970 ctl = b43_phy_read(dev, B43_LPPHY_TX_PWR_CTL_CMD);
971 switch (ctl & B43_LPPHY_TX_PWR_CTL_CMD_MODE) {
972 case B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF:
973 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_OFF;
974 break;
975 case B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW:
976 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_SW;
977 break;
978 case B43_LPPHY_TX_PWR_CTL_CMD_MODE_HW:
979 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_HW;
980 break;
981 default:
982 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_UNKNOWN;
983 B43_WARN_ON(1);
984 break;
985 }
986}
987
988/* Set the TX power control mode in hardware. */
989static void lpphy_write_tx_pctl_mode_to_hardware(struct b43_wldev *dev)
990{
991 struct b43_phy_lp *lpphy = dev->phy.lp;
992 u16 ctl;
993
994 switch (lpphy->txpctl_mode) {
995 case B43_LPPHY_TXPCTL_OFF:
996 ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF;
997 break;
998 case B43_LPPHY_TXPCTL_HW:
999 ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_HW;
1000 break;
1001 case B43_LPPHY_TXPCTL_SW:
1002 ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW;
1003 break;
1004 default:
1005 ctl = 0;
1006 B43_WARN_ON(1);
1007 }
1008 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
1009 (u16)~B43_LPPHY_TX_PWR_CTL_CMD_MODE, ctl);
1010}
1011
1012static void lpphy_set_tx_power_control(struct b43_wldev *dev,
1013 enum b43_lpphy_txpctl_mode mode)
1014{
1015 struct b43_phy_lp *lpphy = dev->phy.lp;
1016 enum b43_lpphy_txpctl_mode oldmode;
1017
1018 oldmode = lpphy->txpctl_mode;
1019 lpphy_read_tx_pctl_mode_from_hardware(dev);
1020 if (lpphy->txpctl_mode == mode)
1021 return;
1022 lpphy->txpctl_mode = mode;
1023
1024 if (oldmode == B43_LPPHY_TXPCTL_HW) {
1025 //TODO Update TX Power NPT
1026 //TODO Clear all TX Power offsets
1027 } else {
1028 if (mode == B43_LPPHY_TXPCTL_HW) {
1029 //TODO Recalculate target TX power
1030 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
1031 0xFF80, lpphy->tssi_idx);
1032 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_NNUM,
1033 0x8FFF, ((u16)lpphy->tssi_npt << 16));
1034 //TODO Set "TSSI Transmit Count" variable to total transmitted frame count
1035 //TODO Disable TX gain override
1036 lpphy->tx_pwr_idx_over = -1;
1037 }
1038 }
1039 if (dev->phy.rev >= 2) {
1040 if (mode == B43_LPPHY_TXPCTL_HW)
1041 b43_phy_maskset(dev, B43_PHY_OFDM(0xD0), 0xFD, 0x2);
1042 else
1043 b43_phy_maskset(dev, B43_PHY_OFDM(0xD0), 0xFD, 0);
1044 }
1045 lpphy_write_tx_pctl_mode_to_hardware(dev);
1046}
1047
560ad81b
GS		 1048static void lpphy_rev0_1_rc_calib(struct b43_wldev *dev)
1049{
1050 struct b43_phy_lp *lpphy = dev->phy.lp;
1051 struct lpphy_iq_est iq_est;
1052 struct lpphy_tx_gains tx_gains;
1053 static const u32 ideal_pwr_table[22] = {
1054 0x10000, 0x10557, 0x10e2d, 0x113e0, 0x10f22, 0x0ff64,
1055 0x0eda2, 0x0e5d4, 0x0efd1, 0x0fbe8, 0x0b7b8, 0x04b35,
1056 0x01a5e, 0x00a0b, 0x00444, 0x001fd, 0x000ff, 0x00088,
1057 0x0004c, 0x0002c, 0x0001a, 0xc0006,
1058 };
1059 bool old_txg_ovr;
1060 u8 old_bbmult;
1061 u16 old_rf_ovr, old_rf_ovrval, old_afe_ovr, old_afe_ovrval,
1245684c
GS		 1062 old_rf2_ovr, old_rf2_ovrval, old_phy_ctl;
1063 enum b43_lpphy_txpctl_mode old_txpctl;
560ad81b
GS		 1064 u32 normal_pwr, ideal_pwr, mean_sq_pwr, tmp = 0, mean_sq_pwr_min = 0;
1065 int loopback, i, j, inner_sum;
1066
1067 memset(&iq_est, 0, sizeof(iq_est));
1068
1069 b43_switch_channel(dev, 7);
1070 old_txg_ovr = (b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVR) >> 6) & 1;
1071 old_bbmult = lpphy_get_bb_mult(dev);
1072 if (old_txg_ovr)
1073 tx_gains = lpphy_get_tx_gains(dev);
1074 old_rf_ovr = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_0);
1075 old_rf_ovrval = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_VAL_0);
1076 old_afe_ovr = b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVR);
1077 old_afe_ovrval = b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVRVAL);
1078 old_rf2_ovr = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_2);
1079 old_rf2_ovrval = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_2_VAL);
1080 old_phy_ctl = b43_phy_read(dev, B43_LPPHY_LP_PHY_CTL);
1245684c
GS		 1081 lpphy_read_tx_pctl_mode_from_hardware(dev);
1082 old_txpctl = lpphy->txpctl_mode;
560ad81b
GS		 1083
1084 lpphy_set_tx_power_control(dev, B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF);
1085 lpphy_disable_crs(dev);
1086 loopback = lpphy_loopback(dev);
1087 if (loopback == -1)
1088 goto finish;
1089 lpphy_set_rx_gain_by_index(dev, loopback);
1090 b43_phy_maskset(dev, B43_LPPHY_LP_PHY_CTL, 0xFFBF, 0x40);
1091 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFFF8, 0x1);
1092 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFFC7, 0x8);
1093 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFF3F, 0xC0);
1094 for (i = 128; i <= 159; i++) {
1095 b43_radio_write(dev, B2062_N_RXBB_CALIB2, i);
1096 inner_sum = 0;
1097 for (j = 5; j <= 25; j++) {
1098 lpphy_run_ddfs(dev, 1, 1, j, j, 0);
1099 if (!(lpphy_rx_iq_est(dev, 1000, 32, &iq_est)))
1100 goto finish;
1101 mean_sq_pwr = iq_est.i_pwr + iq_est.q_pwr;
1102 if (j == 5)
1103 tmp = mean_sq_pwr;
1104 ideal_pwr = ((ideal_pwr_table[j-5] >> 3) + 1) >> 1;
1105 normal_pwr = lpphy_qdiv_roundup(mean_sq_pwr, tmp, 12);
1106 mean_sq_pwr = ideal_pwr - normal_pwr;
1107 mean_sq_pwr *= mean_sq_pwr;
1108 inner_sum += mean_sq_pwr;
1109 if ((i = 128) || (inner_sum < mean_sq_pwr_min)) {
1110 lpphy->rc_cap = i;
1111 mean_sq_pwr_min = inner_sum;
1112 }
1113 }
1114 }
1115 lpphy_stop_ddfs(dev);
1116
1117finish:
1118 lpphy_restore_crs(dev);
1119 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, old_rf_ovrval);
1120 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, old_rf_ovr);
1121 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVRVAL, old_afe_ovrval);
1122 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, old_afe_ovr);
1123 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, old_rf2_ovrval);
1124 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, old_rf2_ovr);
1125 b43_phy_write(dev, B43_LPPHY_LP_PHY_CTL, old_phy_ctl);
1126
1127 lpphy_set_bb_mult(dev, old_bbmult);
1128 if (old_txg_ovr) {
1129 /*
1130 * SPEC FIXME: The specs say "get_tx_gains" here, which is
1131 * illogical. According to lwfinger, vendor driver v4.150.10.5
1132 * has a Set here, while v4.174.64.19 has a Get - regression in
1133 * the vendor driver? This should be tested this once the code
1134 * is testable.
1135 */
1136 lpphy_set_tx_gains(dev, tx_gains);
1137 }
1138 lpphy_set_tx_power_control(dev, old_txpctl);
1139 if (lpphy->rc_cap)
1140 lpphy_set_rc_cap(dev);
1141}
1142
1143static void lpphy_rev2plus_rc_calib(struct b43_wldev *dev)
1144{
1145 struct ssb_bus *bus = dev->dev->bus;
1146 u32 crystal_freq = bus->chipco.pmu.crystalfreq * 1000;
1147 u8 tmp = b43_radio_read(dev, B2063_RX_BB_SP8) & 0xFF;
1148 int i;
1149
1150 b43_radio_write(dev, B2063_RX_BB_SP8, 0x0);
1151 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7E);
1152 b43_radio_mask(dev, B2063_PLL_SP1, 0xF7);
1153 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7C);
1154 b43_radio_write(dev, B2063_RC_CALIB_CTL2, 0x15);
1155 b43_radio_write(dev, B2063_RC_CALIB_CTL3, 0x70);
1156 b43_radio_write(dev, B2063_RC_CALIB_CTL4, 0x52);
1157 b43_radio_write(dev, B2063_RC_CALIB_CTL5, 0x1);
1158 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7D);
1159
1160 for (i = 0; i < 10000; i++) {
1161 if (b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2)
1162 break;
1163 msleep(1);
1164 }
1165
1166 if (!(b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2))
1167 b43_radio_write(dev, B2063_RX_BB_SP8, tmp);
1168
1169 tmp = b43_radio_read(dev, B2063_TX_BB_SP3) & 0xFF;
1170
1171 b43_radio_write(dev, B2063_TX_BB_SP3, 0x0);
1172 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7E);
1173 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7C);
1174 b43_radio_write(dev, B2063_RC_CALIB_CTL2, 0x55);
1175 b43_radio_write(dev, B2063_RC_CALIB_CTL3, 0x76);
1176
1177 if (crystal_freq == 24000000) {
1178 b43_radio_write(dev, B2063_RC_CALIB_CTL4, 0xFC);
1179 b43_radio_write(dev, B2063_RC_CALIB_CTL5, 0x0);
1180 } else {
1181 b43_radio_write(dev, B2063_RC_CALIB_CTL4, 0x13);
1182 b43_radio_write(dev, B2063_RC_CALIB_CTL5, 0x1);
1183 }
1184
1185 b43_radio_write(dev, B2063_PA_SP7, 0x7D);
1186
1187 for (i = 0; i < 10000; i++) {
1188 if (b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2)
1189 break;
1190 msleep(1);
1191 }
1192
1193 if (!(b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2))
1194 b43_radio_write(dev, B2063_TX_BB_SP3, tmp);
1195
1196 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7E);
1197}
1198
1199static void lpphy_calibrate_rc(struct b43_wldev *dev)
1200{
1201 struct b43_phy_lp *lpphy = dev->phy.lp;
1202
1203 if (dev->phy.rev >= 2) {
1204 lpphy_rev2plus_rc_calib(dev);
1205 } else if (!lpphy->rc_cap) {
1206 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1207 lpphy_rev0_1_rc_calib(dev);
1208 } else {
1209 lpphy_set_rc_cap(dev);
1210 }
1211}
1212
ce1a9ee3
MB		 1213static void lpphy_set_tx_power_by_index(struct b43_wldev *dev, u8 index)
1214{
1215 struct b43_phy_lp *lpphy = dev->phy.lp;
1216
1217 lpphy->tx_pwr_idx_over = index;
1218 if (lpphy->txpctl_mode != B43_LPPHY_TXPCTL_OFF)
1219 lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_SW);
1220
1221 //TODO
1222}
1223
1224static void lpphy_btcoex_override(struct b43_wldev *dev)
1225{
1226 b43_write16(dev, B43_MMIO_BTCOEX_CTL, 0x3);
1227 b43_write16(dev, B43_MMIO_BTCOEX_TXCTL, 0xFF);
1228}
1229
1230static void lpphy_pr41573_workaround(struct b43_wldev *dev)
1231{
1232 struct b43_phy_lp *lpphy = dev->phy.lp;
1233 u32 *saved_tab;
1234 const unsigned int saved_tab_size = 256;
1235 enum b43_lpphy_txpctl_mode txpctl_mode;
1236 s8 tx_pwr_idx_over;
1237 u16 tssi_npt, tssi_idx;
1238
1239 saved_tab = kcalloc(saved_tab_size, sizeof(saved_tab[0]), GFP_KERNEL);
1240 if (!saved_tab) {
1241 b43err(dev->wl, "PR41573 failed. Out of memory!\n");
1242 return;
1243 }
1244
1245 lpphy_read_tx_pctl_mode_from_hardware(dev);
1246 txpctl_mode = lpphy->txpctl_mode;
1247 tx_pwr_idx_over = lpphy->tx_pwr_idx_over;
1248 tssi_npt = lpphy->tssi_npt;
1249 tssi_idx = lpphy->tssi_idx;
1250
1251 if (dev->phy.rev < 2) {
1252 b43_lptab_read_bulk(dev, B43_LPTAB32(10, 0x140),
1253 saved_tab_size, saved_tab);
1254 } else {
1255 b43_lptab_read_bulk(dev, B43_LPTAB32(7, 0x140),
1256 saved_tab_size, saved_tab);
1257 }
1258 //TODO
1259
1260 kfree(saved_tab);
1261}
1262
1263static void lpphy_calibration(struct b43_wldev *dev)
1264{
1265 struct b43_phy_lp *lpphy = dev->phy.lp;
1266 enum b43_lpphy_txpctl_mode saved_pctl_mode;
1267
1268 b43_mac_suspend(dev);
1269
1270 lpphy_btcoex_override(dev);
1271 lpphy_read_tx_pctl_mode_from_hardware(dev);
1272 saved_pctl_mode = lpphy->txpctl_mode;
1273 lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF);
1274 //TODO Perform transmit power table I/Q LO calibration
1275 if ((dev->phy.rev == 0) && (saved_pctl_mode != B43_LPPHY_TXPCTL_OFF))
1276 lpphy_pr41573_workaround(dev);
1277 //TODO If a full calibration has not been performed on this channel yet, perform PAPD TX-power calibration
1278 lpphy_set_tx_power_control(dev, saved_pctl_mode);
1279 //TODO Perform I/Q calibration with a single control value set
1280
1281 b43_mac_enable(dev);
1282}
1283
7021f62a
GS		 1284static void lpphy_set_tssi_mux(struct b43_wldev *dev, enum tssi_mux_mode mode)
1285{
1286 if (mode != TSSI_MUX_EXT) {
1287 b43_radio_set(dev, B2063_PA_SP1, 0x2);
1288 b43_phy_set(dev, B43_PHY_OFDM(0xF3), 0x1000);
1289 b43_radio_write(dev, B2063_PA_CTL10, 0x51);
1290 if (mode == TSSI_MUX_POSTPA) {
1291 b43_radio_mask(dev, B2063_PA_SP1, 0xFFFE);
1292 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xFFC7);
1293 } else {
1294 b43_radio_maskset(dev, B2063_PA_SP1, 0xFFFE, 0x1);
1295 b43_phy_maskset(dev, B43_LPPHY_AFE_CTL_OVRVAL,
1296 0xFFC7, 0x20);
1297 }
1298 } else {
1299 B43_WARN_ON(1);
1300 }
1301}
1302
1303static void lpphy_tx_pctl_init_hw(struct b43_wldev *dev)
1304{
1305 u16 tmp;
1306 int i;
1307
1308 //SPEC TODO Call LP PHY Clear TX Power offsets
1309 for (i = 0; i < 64; i++) {
1310 if (dev->phy.rev >= 2)
1311 b43_lptab_write(dev, B43_LPTAB32(7, i + 1), i);
1312 else
1313 b43_lptab_write(dev, B43_LPTAB32(10, i + 1), i);
1314 }
1315
1316 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_NNUM, 0xFF00, 0xFF);
1317 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_NNUM, 0x8FFF, 0x5000);
1318 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_IDLETSSI, 0xFFC0, 0x1F);
1319 if (dev->phy.rev < 2) {
1320 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0xEFFF);
1321 b43_phy_maskset(dev, B43_LPPHY_LP_PHY_CTL, 0xDFFF, 0x2000);
1322 } else {
1323 b43_phy_mask(dev, B43_PHY_OFDM(0x103), 0xFFFE);
1324 b43_phy_maskset(dev, B43_PHY_OFDM(0x103), 0xFFFB, 0x4);
1325 b43_phy_maskset(dev, B43_PHY_OFDM(0x103), 0xFFEF, 0x10);
1326 b43_radio_maskset(dev, B2063_IQ_CALIB_CTL2, 0xF3, 0x1);
1327 lpphy_set_tssi_mux(dev, TSSI_MUX_POSTPA);
1328 }
1329 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_IDLETSSI, 0x7FFF, 0x8000);
1330 b43_phy_mask(dev, B43_LPPHY_TX_PWR_CTL_DELTAPWR_LIMIT, 0xFF);
1331 b43_phy_write(dev, B43_LPPHY_TX_PWR_CTL_DELTAPWR_LIMIT, 0xA);
1332 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
1333 (u16)~B43_LPPHY_TX_PWR_CTL_CMD_MODE,
1334 B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF);
1335 b43_phy_mask(dev, B43_LPPHY_TX_PWR_CTL_NNUM, 0xF8FF);
1336 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
1337 (u16)~B43_LPPHY_TX_PWR_CTL_CMD_MODE,
1338 B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW);
1339
1340 if (dev->phy.rev < 2) {
1341 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_0, 0xEFFF, 0x1000);
1342 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xEFFF);
1343 } else {
1344 lpphy_set_tx_power_by_index(dev, 0x7F);
1345 }
1346
1347 b43_dummy_transmission(dev, true, true);
1348
1349 tmp = b43_phy_read(dev, B43_LPPHY_TX_PWR_CTL_STAT);
1350 if (tmp & 0x8000) {
1351 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_IDLETSSI,
1352 0xFFC0, (tmp & 0xFF) - 32);
1353 }
1354
1355 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xEFFF);
1356
1357 // (SPEC?) TODO Set "Target TX frequency" variable to 0
1358 // SPEC FIXME "Set BB Multiplier to 0xE000" impossible - bb_mult is u8!
1359}
1360
1361static void lpphy_tx_pctl_init_sw(struct b43_wldev *dev)
1362{
1363 struct lpphy_tx_gains gains;
1364
1365 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1366 gains.gm = 4;
1367 gains.pad = 12;
1368 gains.pga = 12;
1369 gains.dac = 0;
1370 } else {
1371 gains.gm = 7;
1372 gains.pad = 14;
1373 gains.pga = 15;
1374 gains.dac = 0;
1375 }
1376 lpphy_set_tx_gains(dev, gains);
1377 lpphy_set_bb_mult(dev, 150);
1378}
1379
ce1a9ee3
MB		 1380/* Initialize TX power control */
1381static void lpphy_tx_pctl_init(struct b43_wldev *dev)
1382{
1383 if (0/*FIXME HWPCTL capable */) {
7021f62a 1384 lpphy_tx_pctl_init_hw(dev);
ce1a9ee3 1385 } else { /* This device is only software TX power control capable. */
7021f62a 1386 lpphy_tx_pctl_init_sw(dev);
ce1a9ee3
MB		 1387 }
1388}
1389
e63e4363
MB		 1390static u16 b43_lpphy_op_read(struct b43_wldev *dev, u16 reg)
1391{
0888707f
MB		 1392 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
1393 return b43_read16(dev, B43_MMIO_PHY_DATA);
e63e4363
MB		 1394}
1395
1396static void b43_lpphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
1397{
0888707f
MB		 1398 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
1399 b43_write16(dev, B43_MMIO_PHY_DATA, value);
e63e4363
MB		 1400}
1401
1402static u16 b43_lpphy_op_radio_read(struct b43_wldev *dev, u16 reg)
1403{
0888707f
MB		 1404 /* Register 1 is a 32-bit register. */
1405 B43_WARN_ON(reg == 1);
1406 /* LP-PHY needs a special bit set for read access */
1407 if (dev->phy.rev < 2) {
1408 if (reg != 0x4001)
1409 reg |= 0x100;
1410 } else
1411 reg |= 0x200;
1412
1413 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
1414 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
e63e4363
MB		 1415}
1416
1417static void b43_lpphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
1418{
1419 /* Register 1 is a 32-bit register. */
1420 B43_WARN_ON(reg == 1);
1421
0888707f
MB		 1422 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
1423 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
e63e4363
MB		 1424}
1425
1426static void b43_lpphy_op_software_rfkill(struct b43_wldev *dev,
19d337df 1427 bool blocked)
e63e4363
MB		 1428{
1429 //TODO
1430}
1431
588f8377
GS		 1432struct b206x_channel {
1433 u8 channel;
1434 u16 freq;
1435 u8 data[12];
1436};
1437
1e711bee
GS		 1438static const struct b206x_channel b2062_chantbl[] = {
1439 { .channel = 1, .freq = 2412, .data[0] = 0xFF, .data[1] = 0xFF,
1440 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1441 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1442 { .channel = 2, .freq = 2417, .data[0] = 0xFF, .data[1] = 0xFF,
1443 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1444 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1445 { .channel = 3, .freq = 2422, .data[0] = 0xFF, .data[1] = 0xFF,
1446 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1447 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1448 { .channel = 4, .freq = 2427, .data[0] = 0xFF, .data[1] = 0xFF,
1449 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1450 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1451 { .channel = 5, .freq = 2432, .data[0] = 0xFF, .data[1] = 0xFF,
1452 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1453 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1454 { .channel = 6, .freq = 2437, .data[0] = 0xFF, .data[1] = 0xFF,
1455 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1456 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1457 { .channel = 7, .freq = 2442, .data[0] = 0xFF, .data[1] = 0xFF,
1458 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1459 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1460 { .channel = 8, .freq = 2447, .data[0] = 0xFF, .data[1] = 0xFF,
1461 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1462 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1463 { .channel = 9, .freq = 2452, .data[0] = 0xFF, .data[1] = 0xFF,
1464 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1465 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1466 { .channel = 10, .freq = 2457, .data[0] = 0xFF, .data[1] = 0xFF,
1467 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1468 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1469 { .channel = 11, .freq = 2462, .data[0] = 0xFF, .data[1] = 0xFF,
1470 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1471 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1472 { .channel = 12, .freq = 2467, .data[0] = 0xFF, .data[1] = 0xFF,
1473 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1474 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1475 { .channel = 13, .freq = 2472, .data[0] = 0xFF, .data[1] = 0xFF,
1476 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1477 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1478 { .channel = 14, .freq = 2484, .data[0] = 0xFF, .data[1] = 0xFF,
1479 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1480 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1481 { .channel = 34, .freq = 5170, .data[0] = 0x00, .data[1] = 0x22,
1482 .data[2] = 0x20, .data[3] = 0x84, .data[4] = 0x3C, .data[5] = 0x77,
1483 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1484 { .channel = 38, .freq = 5190, .data[0] = 0x00, .data[1] = 0x11,
1485 .data[2] = 0x10, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1486 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1487 { .channel = 42, .freq = 5210, .data[0] = 0x00, .data[1] = 0x11,
1488 .data[2] = 0x10, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1489 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1490 { .channel = 46, .freq = 5230, .data[0] = 0x00, .data[1] = 0x00,
1491 .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1492 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1493 { .channel = 36, .freq = 5180, .data[0] = 0x00, .data[1] = 0x11,
1494 .data[2] = 0x20, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1495 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1496 { .channel = 40, .freq = 5200, .data[0] = 0x00, .data[1] = 0x11,
1497 .data[2] = 0x10, .data[3] = 0x84, .data[4] = 0x3C, .data[5] = 0x77,
1498 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1499 { .channel = 44, .freq = 5220, .data[0] = 0x00, .data[1] = 0x11,
1500 .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1501 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1502 { .channel = 48, .freq = 5240, .data[0] = 0x00, .data[1] = 0x00,
1503 .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1504 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1505 { .channel = 52, .freq = 5260, .data[0] = 0x00, .data[1] = 0x00,
1506 .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1507 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1508 { .channel = 56, .freq = 5280, .data[0] = 0x00, .data[1] = 0x00,
1509 .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1510 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1511 { .channel = 60, .freq = 5300, .data[0] = 0x00, .data[1] = 0x00,
1512 .data[2] = 0x00, .data[3] = 0x63, .data[4] = 0x3C, .data[5] = 0x77,
1513 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1514 { .channel = 64, .freq = 5320, .data[0] = 0x00, .data[1] = 0x00,
1515 .data[2] = 0x00, .data[3] = 0x62, .data[4] = 0x3C, .data[5] = 0x77,
1516 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1517 { .channel = 100, .freq = 5500, .data[0] = 0x00, .data[1] = 0x00,
1518 .data[2] = 0x00, .data[3] = 0x30, .data[4] = 0x3C, .data[5] = 0x77,
1519 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1520 { .channel = 104, .freq = 5520, .data[0] = 0x00, .data[1] = 0x00,
1521 .data[2] = 0x00, .data[3] = 0x20, .data[4] = 0x3C, .data[5] = 0x77,
1522 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1523 { .channel = 108, .freq = 5540, .data[0] = 0x00, .data[1] = 0x00,
1524 .data[2] = 0x00, .data[3] = 0x20, .data[4] = 0x3C, .data[5] = 0x77,
1525 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1526 { .channel = 112, .freq = 5560, .data[0] = 0x00, .data[1] = 0x00,
1527 .data[2] = 0x00, .data[3] = 0x20, .data[4] = 0x3C, .data[5] = 0x77,
1528 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1529 { .channel = 116, .freq = 5580, .data[0] = 0x00, .data[1] = 0x00,
1530 .data[2] = 0x00, .data[3] = 0x10, .data[4] = 0x3C, .data[5] = 0x77,
1531 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1532 { .channel = 120, .freq = 5600, .data[0] = 0x00, .data[1] = 0x00,
1533 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1534 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1535 { .channel = 124, .freq = 5620, .data[0] = 0x00, .data[1] = 0x00,
1536 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1537 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1538 { .channel = 128, .freq = 5640, .data[0] = 0x00, .data[1] = 0x00,
1539 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1540 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1541 { .channel = 132, .freq = 5660, .data[0] = 0x00, .data[1] = 0x00,
1542 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1543 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1544 { .channel = 136, .freq = 5680, .data[0] = 0x00, .data[1] = 0x00,
1545 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1546 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1547 { .channel = 140, .freq = 5700, .data[0] = 0x00, .data[1] = 0x00,
1548 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1549 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1550 { .channel = 149, .freq = 5745, .data[0] = 0x00, .data[1] = 0x00,
1551 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1552 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1553 { .channel = 153, .freq = 5765, .data[0] = 0x00, .data[1] = 0x00,
1554 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1555 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1556 { .channel = 157, .freq = 5785, .data[0] = 0x00, .data[1] = 0x00,
1557 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1558 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1559 { .channel = 161, .freq = 5805, .data[0] = 0x00, .data[1] = 0x00,
1560 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1561 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1562 { .channel = 165, .freq = 5825, .data[0] = 0x00, .data[1] = 0x00,
1563 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1564 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1565 { .channel = 184, .freq = 4920, .data[0] = 0x55, .data[1] = 0x77,
1566 .data[2] = 0x90, .data[3] = 0xF7, .data[4] = 0x3C, .data[5] = 0x77,
1567 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1568 { .channel = 188, .freq = 4940, .data[0] = 0x44, .data[1] = 0x77,
1569 .data[2] = 0x80, .data[3] = 0xE7, .data[4] = 0x3C, .data[5] = 0x77,
1570 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1571 { .channel = 192, .freq = 4960, .data[0] = 0x44, .data[1] = 0x66,
1572 .data[2] = 0x80, .data[3] = 0xE7, .data[4] = 0x3C, .data[5] = 0x77,
1573 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1574 { .channel = 196, .freq = 4980, .data[0] = 0x33, .data[1] = 0x66,
1575 .data[2] = 0x70, .data[3] = 0xC7, .data[4] = 0x3C, .data[5] = 0x77,
1576 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1577 { .channel = 200, .freq = 5000, .data[0] = 0x22, .data[1] = 0x55,
1578 .data[2] = 0x60, .data[3] = 0xD7, .data[4] = 0x3C, .data[5] = 0x77,
1579 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1580 { .channel = 204, .freq = 5020, .data[0] = 0x22, .data[1] = 0x55,
1581 .data[2] = 0x60, .data[3] = 0xC7, .data[4] = 0x3C, .data[5] = 0x77,
1582 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1583 { .channel = 208, .freq = 5040, .data[0] = 0x22, .data[1] = 0x44,
1584 .data[2] = 0x50, .data[3] = 0xC7, .data[4] = 0x3C, .data[5] = 0x77,
1585 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1586 { .channel = 212, .freq = 5060, .data[0] = 0x11, .data[1] = 0x44,
1587 .data[2] = 0x50, .data[3] = 0xA5, .data[4] = 0x3C, .data[5] = 0x77,
1588 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1589 { .channel = 216, .freq = 5080, .data[0] = 0x00, .data[1] = 0x44,
1590 .data[2] = 0x40, .data[3] = 0xB6, .data[4] = 0x3C, .data[5] = 0x77,
1591 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1592};
1593
588f8377
GS		 1594static const struct b206x_channel b2063_chantbl[] = {
1595 { .channel = 1, .freq = 2412, .data[0] = 0x6F, .data[1] = 0x3C,
1596 .data[2] = 0x3C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1597 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1598 .data[10] = 0x80, .data[11] = 0x70, },
1599 { .channel = 2, .freq = 2417, .data[0] = 0x6F, .data[1] = 0x3C,
1600 .data[2] = 0x3C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1601 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1602 .data[10] = 0x80, .data[11] = 0x70, },
1603 { .channel = 3, .freq = 2422, .data[0] = 0x6F, .data[1] = 0x3C,
1604 .data[2] = 0x3C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1605 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1606 .data[10] = 0x80, .data[11] = 0x70, },
1607 { .channel = 4, .freq = 2427, .data[0] = 0x6F, .data[1] = 0x2C,
1608 .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1609 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1610 .data[10] = 0x80, .data[11] = 0x70, },
1611 { .channel = 5, .freq = 2432, .data[0] = 0x6F, .data[1] = 0x2C,
1612 .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1613 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1614 .data[10] = 0x80, .data[11] = 0x70, },
1615 { .channel = 6, .freq = 2437, .data[0] = 0x6F, .data[1] = 0x2C,
1616 .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1617 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1618 .data[10] = 0x80, .data[11] = 0x70, },
1619 { .channel = 7, .freq = 2442, .data[0] = 0x6F, .data[1] = 0x2C,
1620 .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1621 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1622 .data[10] = 0x80, .data[11] = 0x70, },
1623 { .channel = 8, .freq = 2447, .data[0] = 0x6F, .data[1] = 0x2C,
1624 .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1625 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1626 .data[10] = 0x80, .data[11] = 0x70, },
1627 { .channel = 9, .freq = 2452, .data[0] = 0x6F, .data[1] = 0x1C,
1628 .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1629 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1630 .data[10] = 0x80, .data[11] = 0x70, },
1631 { .channel = 10, .freq = 2457, .data[0] = 0x6F, .data[1] = 0x1C,
1632 .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1633 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1634 .data[10] = 0x80, .data[11] = 0x70, },
1635 { .channel = 11, .freq = 2462, .data[0] = 0x6E, .data[1] = 0x1C,
1636 .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1637 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1638 .data[10] = 0x80, .data[11] = 0x70, },
1639 { .channel = 12, .freq = 2467, .data[0] = 0x6E, .data[1] = 0x1C,
1640 .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1641 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1642 .data[10] = 0x80, .data[11] = 0x70, },
1643 { .channel = 13, .freq = 2472, .data[0] = 0x6E, .data[1] = 0x1C,
1644 .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1645 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1646 .data[10] = 0x80, .data[11] = 0x70, },
1647 { .channel = 14, .freq = 2484, .data[0] = 0x6E, .data[1] = 0x0C,
1648 .data[2] = 0x0C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1649 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1650 .data[10] = 0x80, .data[11] = 0x70, },
1651 { .channel = 34, .freq = 5170, .data[0] = 0x6A, .data[1] = 0x0C,
1652 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x02, .data[5] = 0x05,
1653 .data[6] = 0x0D, .data[7] = 0x0D, .data[8] = 0x77, .data[9] = 0x80,
1654 .data[10] = 0x20, .data[11] = 0x00, },
1655 { .channel = 36, .freq = 5180, .data[0] = 0x6A, .data[1] = 0x0C,
1656 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x01, .data[5] = 0x05,
1657 .data[6] = 0x0D, .data[7] = 0x0C, .data[8] = 0x77, .data[9] = 0x80,
1658 .data[10] = 0x20, .data[11] = 0x00, },
1659 { .channel = 38, .freq = 5190, .data[0] = 0x6A, .data[1] = 0x0C,
1660 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x01, .data[5] = 0x04,
1661 .data[6] = 0x0C, .data[7] = 0x0C, .data[8] = 0x77, .data[9] = 0x80,
1662 .data[10] = 0x20, .data[11] = 0x00, },
1663 { .channel = 40, .freq = 5200, .data[0] = 0x69, .data[1] = 0x0C,
1664 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x01, .data[5] = 0x04,
1665 .data[6] = 0x0C, .data[7] = 0x0C, .data[8] = 0x77, .data[9] = 0x70,
1666 .data[10] = 0x20, .data[11] = 0x00, },
1667 { .channel = 42, .freq = 5210, .data[0] = 0x69, .data[1] = 0x0C,
1668 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x01, .data[5] = 0x04,
1669 .data[6] = 0x0B, .data[7] = 0x0C, .data[8] = 0x77, .data[9] = 0x70,
1670 .data[10] = 0x20, .data[11] = 0x00, },
1671 { .channel = 44, .freq = 5220, .data[0] = 0x69, .data[1] = 0x0C,
1672 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x04,
1673 .data[6] = 0x0B, .data[7] = 0x0B, .data[8] = 0x77, .data[9] = 0x60,
1674 .data[10] = 0x20, .data[11] = 0x00, },
1675 { .channel = 46, .freq = 5230, .data[0] = 0x69, .data[1] = 0x0C,
1676 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x03,
1677 .data[6] = 0x0A, .data[7] = 0x0B, .data[8] = 0x77, .data[9] = 0x60,
1678 .data[10] = 0x20, .data[11] = 0x00, },
1679 { .channel = 48, .freq = 5240, .data[0] = 0x69, .data[1] = 0x0C,
1680 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x03,
1681 .data[6] = 0x0A, .data[7] = 0x0A, .data[8] = 0x77, .data[9] = 0x60,
1682 .data[10] = 0x20, .data[11] = 0x00, },
1683 { .channel = 52, .freq = 5260, .data[0] = 0x68, .data[1] = 0x0C,
1684 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x02,
1685 .data[6] = 0x09, .data[7] = 0x09, .data[8] = 0x77, .data[9] = 0x60,
1686 .data[10] = 0x20, .data[11] = 0x00, },
1687 { .channel = 56, .freq = 5280, .data[0] = 0x68, .data[1] = 0x0C,
1688 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x01,
1689 .data[6] = 0x08, .data[7] = 0x08, .data[8] = 0x77, .data[9] = 0x50,
1690 .data[10] = 0x10, .data[11] = 0x00, },
1691 { .channel = 60, .freq = 5300, .data[0] = 0x68, .data[1] = 0x0C,
1692 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x01,
1693 .data[6] = 0x08, .data[7] = 0x08, .data[8] = 0x77, .data[9] = 0x50,
1694 .data[10] = 0x10, .data[11] = 0x00, },
1695 { .channel = 64, .freq = 5320, .data[0] = 0x67, .data[1] = 0x0C,
1696 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1697 .data[6] = 0x08, .data[7] = 0x08, .data[8] = 0x77, .data[9] = 0x50,
1698 .data[10] = 0x10, .data[11] = 0x00, },
1699 { .channel = 100, .freq = 5500, .data[0] = 0x64, .data[1] = 0x0C,
1700 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1701 .data[6] = 0x02, .data[7] = 0x01, .data[8] = 0x77, .data[9] = 0x20,
1702 .data[10] = 0x00, .data[11] = 0x00, },
1703 { .channel = 104, .freq = 5520, .data[0] = 0x64, .data[1] = 0x0C,
1704 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1705 .data[6] = 0x01, .data[7] = 0x01, .data[8] = 0x77, .data[9] = 0x20,
1706 .data[10] = 0x00, .data[11] = 0x00, },
1707 { .channel = 108, .freq = 5540, .data[0] = 0x63, .data[1] = 0x0C,
1708 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1709 .data[6] = 0x01, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x10,
1710 .data[10] = 0x00, .data[11] = 0x00, },
1711 { .channel = 112, .freq = 5560, .data[0] = 0x63, .data[1] = 0x0C,
1712 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1713 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x10,
1714 .data[10] = 0x00, .data[11] = 0x00, },
1715 { .channel = 116, .freq = 5580, .data[0] = 0x62, .data[1] = 0x0C,
1716 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1717 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x10,
1718 .data[10] = 0x00, .data[11] = 0x00, },
1719 { .channel = 120, .freq = 5600, .data[0] = 0x62, .data[1] = 0x0C,
1720 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1721 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1722 .data[10] = 0x00, .data[11] = 0x00, },
1723 { .channel = 124, .freq = 5620, .data[0] = 0x62, .data[1] = 0x0C,
1724 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1725 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1726 .data[10] = 0x00, .data[11] = 0x00, },
1727 { .channel = 128, .freq = 5640, .data[0] = 0x61, .data[1] = 0x0C,
1728 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1729 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1730 .data[10] = 0x00, .data[11] = 0x00, },
1731 { .channel = 132, .freq = 5660, .data[0] = 0x61, .data[1] = 0x0C,
1732 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1733 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1734 .data[10] = 0x00, .data[11] = 0x00, },
1735 { .channel = 136, .freq = 5680, .data[0] = 0x61, .data[1] = 0x0C,
1736 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1737 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1738 .data[10] = 0x00, .data[11] = 0x00, },
1739 { .channel = 140, .freq = 5700, .data[0] = 0x60, .data[1] = 0x0C,
1740 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1741 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1742 .data[10] = 0x00, .data[11] = 0x00, },
1743 { .channel = 149, .freq = 5745, .data[0] = 0x60, .data[1] = 0x0C,
1744 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1745 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1746 .data[10] = 0x00, .data[11] = 0x00, },
1747 { .channel = 153, .freq = 5765, .data[0] = 0x60, .data[1] = 0x0C,
1748 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1749 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1750 .data[10] = 0x00, .data[11] = 0x00, },
1751 { .channel = 157, .freq = 5785, .data[0] = 0x60, .data[1] = 0x0C,
1752 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1753 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1754 .data[10] = 0x00, .data[11] = 0x00, },
1755 { .channel = 161, .freq = 5805, .data[0] = 0x60, .data[1] = 0x0C,
1756 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1757 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1758 .data[10] = 0x00, .data[11] = 0x00, },
1759 { .channel = 165, .freq = 5825, .data[0] = 0x60, .data[1] = 0x0C,
1760 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1761 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1762 .data[10] = 0x00, .data[11] = 0x00, },
1763 { .channel = 184, .freq = 4920, .data[0] = 0x6E, .data[1] = 0x0C,
1764 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x09, .data[5] = 0x0E,
1765 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xC0,
1766 .data[10] = 0x50, .data[11] = 0x00, },
1767 { .channel = 188, .freq = 4940, .data[0] = 0x6E, .data[1] = 0x0C,
1768 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x09, .data[5] = 0x0D,
1769 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xB0,
1770 .data[10] = 0x50, .data[11] = 0x00, },
1771 { .channel = 192, .freq = 4960, .data[0] = 0x6E, .data[1] = 0x0C,
1772 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x08, .data[5] = 0x0C,
1773 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xB0,
1774 .data[10] = 0x50, .data[11] = 0x00, },
1775 { .channel = 196, .freq = 4980, .data[0] = 0x6D, .data[1] = 0x0C,
1776 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x08, .data[5] = 0x0C,
1777 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xA0,
1778 .data[10] = 0x40, .data[11] = 0x00, },
1779 { .channel = 200, .freq = 5000, .data[0] = 0x6D, .data[1] = 0x0C,
1780 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x08, .data[5] = 0x0B,
1781 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xA0,
1782 .data[10] = 0x40, .data[11] = 0x00, },
1783 { .channel = 204, .freq = 5020, .data[0] = 0x6D, .data[1] = 0x0C,
1784 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x08, .data[5] = 0x0A,
1785 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xA0,
1786 .data[10] = 0x40, .data[11] = 0x00, },
1787 { .channel = 208, .freq = 5040, .data[0] = 0x6C, .data[1] = 0x0C,
1788 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x07, .data[5] = 0x09,
1789 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0x90,
1790 .data[10] = 0x40, .data[11] = 0x00, },
1791 { .channel = 212, .freq = 5060, .data[0] = 0x6C, .data[1] = 0x0C,
1792 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x06, .data[5] = 0x08,
1793 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0x90,
1794 .data[10] = 0x40, .data[11] = 0x00, },
1795 { .channel = 216, .freq = 5080, .data[0] = 0x6C, .data[1] = 0x0C,
1796 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x05, .data[5] = 0x08,
1797 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0x90,
1798 .data[10] = 0x40, .data[11] = 0x00, },
1799};
1800
1e711bee 1801static void lpphy_b2062_reset_pll_bias(struct b43_wldev *dev)
588f8377 1802{
1e711bee
GS		 1803 struct ssb_bus *bus = dev->dev->bus;
1804
1805 b43_radio_write(dev, B2062_S_RFPLL_CTL2, 0xFF);
1806 udelay(20);
1807 if (bus->chip_id == 0x5354) {
1808 b43_radio_write(dev, B2062_N_COMM1, 4);
1809 b43_radio_write(dev, B2062_S_RFPLL_CTL2, 4);
1810 } else {
1811 b43_radio_write(dev, B2062_S_RFPLL_CTL2, 0);
1812 }
1813 udelay(5);
1814}
1815
1816static void lpphy_b2062_vco_calib(struct b43_wldev *dev)
1817{
1818 b43_phy_write(dev, B2062_S_RFPLL_CTL21, 0x42);
1819 b43_phy_write(dev, B2062_S_RFPLL_CTL21, 0x62);
1820 udelay(200);
1821}
1822
1823static int lpphy_b2062_tune(struct b43_wldev *dev,
1824 unsigned int channel)
1825{
1826 struct b43_phy_lp *lpphy = dev->phy.lp;
1827 struct ssb_bus *bus = dev->dev->bus;
1828 static const struct b206x_channel *chandata = NULL;
1829 u32 crystal_freq = bus->chipco.pmu.crystalfreq * 1000;
1830 u32 tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7, tmp8, tmp9;
1831 int i, err = 0;
1832
1833 for (i = 0; i < ARRAY_SIZE(b2063_chantbl); i++) {
1834 if (b2063_chantbl[i].channel == channel) {
1835 chandata = &b2063_chantbl[i];
1836 break;
1837 }
1838 }
1839
1840 if (B43_WARN_ON(!chandata))
1841 return -EINVAL;
1842
1843 b43_radio_set(dev, B2062_S_RFPLL_CTL14, 0x04);
1844 b43_radio_write(dev, B2062_N_LGENA_TUNE0, chandata->data[0]);
1845 b43_radio_write(dev, B2062_N_LGENA_TUNE2, chandata->data[1]);
1846 b43_radio_write(dev, B2062_N_LGENA_TUNE3, chandata->data[2]);
1847 b43_radio_write(dev, B2062_N_TX_TUNE, chandata->data[3]);
1848 b43_radio_write(dev, B2062_S_LGENG_CTL1, chandata->data[4]);
1849 b43_radio_write(dev, B2062_N_LGENA_CTL5, chandata->data[5]);
1850 b43_radio_write(dev, B2062_N_LGENA_CTL6, chandata->data[6]);
1851 b43_radio_write(dev, B2062_N_TX_PGA, chandata->data[7]);
1852 b43_radio_write(dev, B2062_N_TX_PAD, chandata->data[8]);
1853
1854 tmp1 = crystal_freq / 1000;
1855 tmp2 = lpphy->pdiv * 1000;
1856 b43_radio_write(dev, B2062_S_RFPLL_CTL33, 0xCC);
1857 b43_radio_write(dev, B2062_S_RFPLL_CTL34, 0x07);
1858 lpphy_b2062_reset_pll_bias(dev);
1859 tmp3 = tmp2 * channel2freq_lp(channel);
1860 if (channel2freq_lp(channel) < 4000)
1861 tmp3 *= 2;
1862 tmp4 = 48 * tmp1;
1863 tmp6 = tmp3 / tmp4;
1864 tmp7 = tmp3 % tmp4;
1865 b43_radio_write(dev, B2062_S_RFPLL_CTL26, tmp6);
1866 tmp5 = tmp7 * 0x100;
1867 tmp6 = tmp5 / tmp4;
1868 tmp7 = tmp5 % tmp4;
1869 b43_radio_write(dev, B2062_S_RFPLL_CTL28, tmp6);
1870 tmp5 = tmp7 * 0x100;
1871 tmp6 = tmp5 / tmp4;
1872 tmp7 = tmp5 % tmp4;
1873 b43_radio_write(dev, B2062_S_RFPLL_CTL29, tmp6 + ((2 * tmp7) / tmp4));
1874 tmp8 = b43_phy_read(dev, B2062_S_RFPLL_CTL19);
1875 tmp9 = ((2 * tmp3 * (tmp8 + 1)) + (3 * tmp1)) / (6 * tmp1);
1876 b43_radio_write(dev, B2062_S_RFPLL_CTL23, tmp9 >> 8);
1877 b43_radio_write(dev, B2062_S_RFPLL_CTL24, tmp9 & 0xFF);
1878
1879 lpphy_b2062_vco_calib(dev);
1880 if (b43_radio_read(dev, B2062_S_RFPLL_CTL3) & 0x10) {
1881 b43_radio_write(dev, B2062_S_RFPLL_CTL33, 0xFC);
1882 b43_radio_write(dev, B2062_S_RFPLL_CTL34, 0);
1883 lpphy_b2062_reset_pll_bias(dev);
1884 lpphy_b2062_vco_calib(dev);
1885 if (b43_radio_read(dev, B2062_S_RFPLL_CTL3) & 0x10)
1886 err = -EINVAL;
1887 }
1888
1889 b43_radio_mask(dev, B2062_S_RFPLL_CTL14, ~0x04);
1890 return err;
1891}
1892
1893static void lpphy_japan_filter(struct b43_wldev *dev, int channel)
1894{
1895 struct b43_phy_lp *lpphy = dev->phy.lp;
1896 u16 tmp = (channel == 14); //SPEC FIXME check japanwidefilter!
1897
1898 if (dev->phy.rev < 2) { //SPEC FIXME Isn't this rev0/1-specific?
1899 b43_phy_maskset(dev, B43_LPPHY_LP_PHY_CTL, 0xFCFF, tmp << 9);
1900 if ((dev->phy.rev == 1) && (lpphy->rc_cap))
1901 lpphy_set_rc_cap(dev);
1902 } else {
1903 b43_radio_write(dev, B2063_TX_BB_SP3, 0x3F);
1904 }
588f8377
GS		 1905}
1906
1907static void lpphy_b2063_vco_calib(struct b43_wldev *dev)
1908{
1909 u16 tmp;
1910
1911 b43_phy_mask(dev, B2063_PLL_SP1, ~0x40);
1912 tmp = b43_phy_read(dev, B2063_PLL_JTAG_CALNRST) & 0xF8;
1913 b43_phy_write(dev, B2063_PLL_JTAG_CALNRST, tmp);
1914 udelay(1);
1915 b43_phy_write(dev, B2063_PLL_JTAG_CALNRST, tmp | 0x4);
1916 udelay(1);
1917 b43_phy_write(dev, B2063_PLL_JTAG_CALNRST, tmp | 0x6);
1918 udelay(1);
1919 b43_phy_write(dev, B2063_PLL_JTAG_CALNRST, tmp | 0x7);
1920 udelay(300);
1921 b43_phy_set(dev, B2063_PLL_SP1, 0x40);
1922}
1923
1e711bee
GS		 1924static int lpphy_b2063_tune(struct b43_wldev *dev,
1925 unsigned int channel)
588f8377
GS		 1926{
1927 struct ssb_bus *bus = dev->dev->bus;
1928
1929 static const struct b206x_channel *chandata = NULL;
1930 u32 crystal_freq = bus->chipco.pmu.crystalfreq * 1000;
1931 u32 freqref, vco_freq, val1, val2, val3, timeout, timeoutref, count;
1932 u16 old_comm15, scale;
1933 u32 tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
1934 int i, div = (crystal_freq <= 26000000 ? 1 : 2);
1935
1936 for (i = 0; i < ARRAY_SIZE(b2063_chantbl); i++) {
1937 if (b2063_chantbl[i].channel == channel) {
1938 chandata = &b2063_chantbl[i];
1939 break;
1940 }
1941 }
1942
1943 if (B43_WARN_ON(!chandata))
1e711bee 1944 return -EINVAL;
588f8377
GS		 1945
1946 b43_radio_write(dev, B2063_LOGEN_VCOBUF1, chandata->data[0]);
1947 b43_radio_write(dev, B2063_LOGEN_MIXER2, chandata->data[1]);
1948 b43_radio_write(dev, B2063_LOGEN_BUF2, chandata->data[2]);
1949 b43_radio_write(dev, B2063_LOGEN_RCCR1, chandata->data[3]);
1950 b43_radio_write(dev, B2063_A_RX_1ST3, chandata->data[4]);
1951 b43_radio_write(dev, B2063_A_RX_2ND1, chandata->data[5]);
1952 b43_radio_write(dev, B2063_A_RX_2ND4, chandata->data[6]);
1953 b43_radio_write(dev, B2063_A_RX_2ND7, chandata->data[7]);
1954 b43_radio_write(dev, B2063_A_RX_PS6, chandata->data[8]);
1955 b43_radio_write(dev, B2063_TX_RF_CTL2, chandata->data[9]);
1956 b43_radio_write(dev, B2063_TX_RF_CTL5, chandata->data[10]);
1957 b43_radio_write(dev, B2063_PA_CTL11, chandata->data[11]);
1958
1959 old_comm15 = b43_radio_read(dev, B2063_COMM15);
1960 b43_radio_set(dev, B2063_COMM15, 0x1E);
1961
1962 if (chandata->freq > 4000) /* spec says 2484, but 4000 is safer */
1963 vco_freq = chandata->freq << 1;
1964 else
1965 vco_freq = chandata->freq << 2;
1966
1967 freqref = crystal_freq * 3;
1968 val1 = lpphy_qdiv_roundup(crystal_freq, 1000000, 16);
1969 val2 = lpphy_qdiv_roundup(crystal_freq, 1000000 * div, 16);
1970 val3 = lpphy_qdiv_roundup(vco_freq, 3, 16);
1971 timeout = ((((8 * crystal_freq) / (div * 5000000)) + 1) >> 1) - 1;
1972 b43_radio_write(dev, B2063_PLL_JTAG_PLL_VCO_CALIB3, 0x2);
1973 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_VCO_CALIB6,
1974 0xFFF8, timeout >> 2);
1975 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_VCO_CALIB7,
1976 0xFF9F,timeout << 5);
1977
1978 timeoutref = ((((8 * crystal_freq) / (div * (timeout + 1))) +
1979 999999) / 1000000) + 1;
1980 b43_radio_write(dev, B2063_PLL_JTAG_PLL_VCO_CALIB5, timeoutref);
1981
1982 count = lpphy_qdiv_roundup(val3, val2 + 16, 16);
1983 count *= (timeout + 1) * (timeoutref + 1);
1984 count--;
1985 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_VCO_CALIB7,
1986 0xF0, count >> 8);
1987 b43_radio_write(dev, B2063_PLL_JTAG_PLL_VCO_CALIB8, count & 0xFF);
1988
1989 tmp1 = ((val3 * 62500) / freqref) << 4;
1990 tmp2 = ((val3 * 62500) % freqref) << 4;
1991 while (tmp2 >= freqref) {
1992 tmp1++;
1993 tmp2 -= freqref;
1994 }
1995 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_SG1, 0xFFE0, tmp1 >> 4);
1996 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_SG2, 0xFE0F, tmp1 << 4);
1997 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_SG2, 0xFFF0, tmp1 >> 16);
1998 b43_radio_write(dev, B2063_PLL_JTAG_PLL_SG3, (tmp2 >> 8) & 0xFF);
1999 b43_radio_write(dev, B2063_PLL_JTAG_PLL_SG4, tmp2 & 0xFF);
2000
2001 b43_radio_write(dev, B2063_PLL_JTAG_PLL_LF1, 0xB9);
2002 b43_radio_write(dev, B2063_PLL_JTAG_PLL_LF2, 0x88);
2003 b43_radio_write(dev, B2063_PLL_JTAG_PLL_LF3, 0x28);
2004 b43_radio_write(dev, B2063_PLL_JTAG_PLL_LF4, 0x63);
2005
2006 tmp3 = ((41 * (val3 - 3000)) /1200) + 27;
2007 tmp4 = lpphy_qdiv_roundup(132000 * tmp1, 8451, 16);
2008
2009 if ((tmp4 + tmp3 - 1) / tmp3 > 60) {
2010 scale = 1;
2011 tmp5 = ((tmp4 + tmp3) / (tmp3 << 1)) - 8;
2012 } else {
2013 scale = 0;
2014 tmp5 = ((tmp4 + (tmp3 >> 1)) / tmp3) - 8;
2015 }
2016 b43_phy_maskset(dev, B2063_PLL_JTAG_PLL_CP2, 0xFFC0, tmp5);
2017 b43_phy_maskset(dev, B2063_PLL_JTAG_PLL_CP2, 0xFFBF, scale << 6);
2018
2019 tmp6 = lpphy_qdiv_roundup(100 * val1, val3, 16);
2020 tmp6 *= (tmp5 * 8) * (scale + 1);
2021 if (tmp6 > 150)
2022 tmp6 = 0;
2023
2024 b43_phy_maskset(dev, B2063_PLL_JTAG_PLL_CP3, 0xFFE0, tmp6);
2025 b43_phy_maskset(dev, B2063_PLL_JTAG_PLL_CP3, 0xFFDF, scale << 5);
2026
2027 b43_phy_maskset(dev, B2063_PLL_JTAG_PLL_XTAL_12, 0xFFFB, 0x4);
2028 if (crystal_freq > 26000000)
2029 b43_phy_set(dev, B2063_PLL_JTAG_PLL_XTAL_12, 0x2);
2030 else
2031 b43_phy_mask(dev, B2063_PLL_JTAG_PLL_XTAL_12, 0xFD);
2032
2033 if (val1 == 45)
2034 b43_phy_set(dev, B2063_PLL_JTAG_PLL_VCO1, 0x2);
2035 else
2036 b43_phy_mask(dev, B2063_PLL_JTAG_PLL_VCO1, 0xFD);
2037
2038 b43_phy_set(dev, B2063_PLL_SP2, 0x3);
2039 udelay(1);
2040 b43_phy_mask(dev, B2063_PLL_SP2, 0xFFFC);
2041 lpphy_b2063_vco_calib(dev);
2042 b43_radio_write(dev, B2063_COMM15, old_comm15);
1e711bee
GS		 2043
2044 return 0;
588f8377
GS		 2045}
2046
e63e4363
MB		 2047static int b43_lpphy_op_switch_channel(struct b43_wldev *dev,
2048 unsigned int new_channel)
2049{
1e711bee
GS		 2050 int err;
2051
588f8377
GS		 2052 b43_write16(dev, B43_MMIO_CHANNEL, new_channel);
2053
2054 if (dev->phy.radio_ver == 0x2063) {
1e711bee
GS		 2055 err = lpphy_b2063_tune(dev, new_channel);
2056 if (err)
2057 return err;
588f8377 2058 } else {
1e711bee
GS		 2059 err = lpphy_b2062_tune(dev, new_channel);
2060 if (err)
2061 return err;
2062 lpphy_japan_filter(dev, new_channel);
0c61bb9a 2063 lpphy_adjust_gain_table(dev, channel2freq_lp(new_channel));
588f8377
GS		 2064 }
2065
e63e4363
MB		 2066 return 0;
2067}
2068
588f8377 2069static int b43_lpphy_op_init(struct b43_wldev *dev)
e63e4363 2070{
588f8377
GS		 2071 lpphy_read_band_sprom(dev); //FIXME should this be in prepare_structs?
2072 lpphy_baseband_init(dev);
2073 lpphy_radio_init(dev);
2074 lpphy_calibrate_rc(dev);
2075 b43_lpphy_op_switch_channel(dev, b43_lpphy_op_get_default_chan(dev));
2076 lpphy_tx_pctl_init(dev);
2077 lpphy_calibration(dev);
2078 //TODO ACI init
2079
2080 return 0;
e63e4363
MB		 2081}
2082
2083static void b43_lpphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna)
2084{
2085 //TODO
2086}
2087
2088static void b43_lpphy_op_adjust_txpower(struct b43_wldev *dev)
2089{
2090 //TODO
2091}
2092
2093static enum b43_txpwr_result b43_lpphy_op_recalc_txpower(struct b43_wldev *dev,
2094 bool ignore_tssi)
2095{
2096 //TODO
2097 return B43_TXPWR_RES_DONE;
2098}
2099
e63e4363
MB		 2100const struct b43_phy_operations b43_phyops_lp = {
2101 .allocate = b43_lpphy_op_allocate,
fb11137a
MB		 2102 .free = b43_lpphy_op_free,
2103 .prepare_structs = b43_lpphy_op_prepare_structs,
e63e4363 2104 .init = b43_lpphy_op_init,
e63e4363
MB		 2105 .phy_read = b43_lpphy_op_read,
2106 .phy_write = b43_lpphy_op_write,
2107 .radio_read = b43_lpphy_op_radio_read,
2108 .radio_write = b43_lpphy_op_radio_write,
2109 .software_rfkill = b43_lpphy_op_software_rfkill,
cb24f57f 2110 .switch_analog = b43_phyop_switch_analog_generic,
e63e4363
MB		 2111 .switch_channel = b43_lpphy_op_switch_channel,
2112 .get_default_chan = b43_lpphy_op_get_default_chan,
2113 .set_rx_antenna = b43_lpphy_op_set_rx_antenna,
2114 .recalc_txpower = b43_lpphy_op_recalc_txpower,
2115 .adjust_txpower = b43_lpphy_op_adjust_txpower,
2116};
Linux 6.x block layer and io_uring tree(s)