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b43: Update dummy transmission to match V4 specs
[linux-2.6-block.git] / drivers / net / wireless / b43 / phy_lp.c
CommitLineData
e63e4363
MB		 1/*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11g LP-PHY driver
5
6c1bb927 6 Copyright (c) 2008-2009 Michael Buesch <mb@bu3sch.de>
e63e4363
MB		 7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING. If not, write to
20 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
21 Boston, MA 02110-1301, USA.
22
23*/
24
25#include "b43.h"
ce1a9ee3 26#include "main.h"
e63e4363
MB		 27#include "phy_lp.h"
28#include "phy_common.h"
6c1bb927 29#include "tables_lpphy.h"
e63e4363
MB		 30
31
32static int b43_lpphy_op_allocate(struct b43_wldev *dev)
33{
34 struct b43_phy_lp *lpphy;
35
36 lpphy = kzalloc(sizeof(*lpphy), GFP_KERNEL);
37 if (!lpphy)
38 return -ENOMEM;
39 dev->phy.lp = lpphy;
40
e63e4363
MB		 41 return 0;
42}
43
fb11137a 44static void b43_lpphy_op_prepare_structs(struct b43_wldev *dev)
e63e4363 45{
fb11137a
MB		 46 struct b43_phy *phy = &dev->phy;
47 struct b43_phy_lp *lpphy = phy->lp;
e63e4363 48
fb11137a 49 memset(lpphy, 0, sizeof(*lpphy));
e63e4363 50
fb11137a 51 //TODO
e63e4363
MB		 52}
53
fb11137a 54static void b43_lpphy_op_free(struct b43_wldev *dev)
e63e4363
MB		 55{
56 struct b43_phy_lp *lpphy = dev->phy.lp;
57
e63e4363
MB		 58 kfree(lpphy);
59 dev->phy.lp = NULL;
60}
61
84ec167d
GS		 62static void lpphy_read_band_sprom(struct b43_wldev *dev)
63{
64 struct b43_phy_lp *lpphy = dev->phy.lp;
65 struct ssb_bus *bus = dev->dev->bus;
66 u16 cckpo, maxpwr;
67 u32 ofdmpo;
68 int i;
69
70 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
71 lpphy->tx_isolation_med_band = bus->sprom.tri2g;
72 lpphy->bx_arch = bus->sprom.bxa2g;
73 lpphy->rx_pwr_offset = bus->sprom.rxpo2g;
74 lpphy->rssi_vf = bus->sprom.rssismf2g;
75 lpphy->rssi_vc = bus->sprom.rssismc2g;
76 lpphy->rssi_gs = bus->sprom.rssisav2g;
77 lpphy->txpa[0] = bus->sprom.pa0b0;
78 lpphy->txpa[1] = bus->sprom.pa0b1;
79 lpphy->txpa[2] = bus->sprom.pa0b2;
80 maxpwr = bus->sprom.maxpwr_bg;
81 lpphy->max_tx_pwr_med_band = maxpwr;
82 cckpo = bus->sprom.cck2gpo;
83 ofdmpo = bus->sprom.ofdm2gpo;
84 if (cckpo) {
85 for (i = 0; i < 4; i++) {
86 lpphy->tx_max_rate[i] =
87 maxpwr - (ofdmpo & 0xF) * 2;
88 ofdmpo >>= 4;
89 }
90 ofdmpo = bus->sprom.ofdm2gpo;
91 for (i = 4; i < 15; i++) {
92 lpphy->tx_max_rate[i] =
93 maxpwr - (ofdmpo & 0xF) * 2;
94 ofdmpo >>= 4;
95 }
96 } else {
97 ofdmpo &= 0xFF;
98 for (i = 0; i < 4; i++)
99 lpphy->tx_max_rate[i] = maxpwr;
100 for (i = 4; i < 15; i++)
101 lpphy->tx_max_rate[i] = maxpwr - ofdmpo;
102 }
103 } else { /* 5GHz */
104 lpphy->tx_isolation_low_band = bus->sprom.tri5gl;
105 lpphy->tx_isolation_med_band = bus->sprom.tri5g;
106 lpphy->tx_isolation_hi_band = bus->sprom.tri5gh;
107 lpphy->bx_arch = bus->sprom.bxa5g;
108 lpphy->rx_pwr_offset = bus->sprom.rxpo5g;
109 lpphy->rssi_vf = bus->sprom.rssismf5g;
110 lpphy->rssi_vc = bus->sprom.rssismc5g;
111 lpphy->rssi_gs = bus->sprom.rssisav5g;
112 lpphy->txpa[0] = bus->sprom.pa1b0;
113 lpphy->txpa[1] = bus->sprom.pa1b1;
114 lpphy->txpa[2] = bus->sprom.pa1b2;
115 lpphy->txpal[0] = bus->sprom.pa1lob0;
116 lpphy->txpal[1] = bus->sprom.pa1lob1;
117 lpphy->txpal[2] = bus->sprom.pa1lob2;
118 lpphy->txpah[0] = bus->sprom.pa1hib0;
119 lpphy->txpah[1] = bus->sprom.pa1hib1;
120 lpphy->txpah[2] = bus->sprom.pa1hib2;
121 maxpwr = bus->sprom.maxpwr_al;
122 ofdmpo = bus->sprom.ofdm5glpo;
123 lpphy->max_tx_pwr_low_band = maxpwr;
124 for (i = 4; i < 12; i++) {
125 lpphy->tx_max_ratel[i] = maxpwr - (ofdmpo & 0xF) * 2;
126 ofdmpo >>= 4;
127 }
128 maxpwr = bus->sprom.maxpwr_a;
129 ofdmpo = bus->sprom.ofdm5gpo;
130 lpphy->max_tx_pwr_med_band = maxpwr;
131 for (i = 4; i < 12; i++) {
132 lpphy->tx_max_rate[i] = maxpwr - (ofdmpo & 0xF) * 2;
133 ofdmpo >>= 4;
134 }
135 maxpwr = bus->sprom.maxpwr_ah;
136 ofdmpo = bus->sprom.ofdm5ghpo;
137 lpphy->max_tx_pwr_hi_band = maxpwr;
138 for (i = 4; i < 12; i++) {
139 lpphy->tx_max_rateh[i] = maxpwr - (ofdmpo & 0xF) * 2;
140 ofdmpo >>= 4;
141 }
142 }
143}
144
c65d6fbf
GS		 145static void lpphy_adjust_gain_table(struct b43_wldev *dev)
146{
147 struct b43_phy_lp *lpphy = dev->phy.lp;
148 u32 freq = dev->wl->hw->conf.channel->center_freq;
149 u16 temp[3];
150 u16 isolation;
151
152 B43_WARN_ON(dev->phy.rev >= 2);
153
154 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
155 isolation = lpphy->tx_isolation_med_band;
156 else if (freq <= 5320)
157 isolation = lpphy->tx_isolation_low_band;
158 else if (freq <= 5700)
159 isolation = lpphy->tx_isolation_med_band;
160 else
161 isolation = lpphy->tx_isolation_hi_band;
162
163 temp[0] = ((isolation - 26) / 12) << 12;
164 temp[1] = temp[0] + 0x1000;
165 temp[2] = temp[0] + 0x2000;
166
167 b43_lptab_write_bulk(dev, B43_LPTAB16(12, 0), 3, temp);
168 b43_lptab_write_bulk(dev, B43_LPTAB16(13, 0), 3, temp);
169}
170
a387cc7d
MB		 171static void lpphy_table_init(struct b43_wldev *dev)
172{
c65d6fbf
GS		 173 if (dev->phy.rev < 2)
174 lpphy_rev0_1_table_init(dev);
175 else
176 lpphy_rev2plus_table_init(dev);
177
178 lpphy_init_tx_gain_table(dev);
179
180 if (dev->phy.rev < 2)
181 lpphy_adjust_gain_table(dev);
a387cc7d
MB		 182}
183
184static void lpphy_baseband_rev0_1_init(struct b43_wldev *dev)
185{
738f0f43
GS		 186 struct ssb_bus *bus = dev->dev->bus;
187 u16 tmp, tmp2;
188
189 if (dev->phy.rev == 1 &&
190 (bus->sprom.boardflags_hi & B43_BFH_FEM_BT)) {
191 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x000A);
192 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0x3F00, 0x0900);
193 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x000A);
194 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0B00);
195 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x000A);
196 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0400);
197 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x000A);
198 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0B00);
199 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_5, 0xFFC0, 0x000A);
200 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_5, 0xC0FF, 0x0900);
201 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_6, 0xFFC0, 0x000A);
202 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_6, 0xC0FF, 0x0B00);
203 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_7, 0xFFC0, 0x000A);
204 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_7, 0xC0FF, 0x0900);
205 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xFFC0, 0x000A);
206 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xC0FF, 0x0B00);
207 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ ||
208 (bus->boardinfo.type == 0x048A) || ((dev->phy.rev == 0) &&
209 (bus->sprom.boardflags_lo & B43_BFL_FEM))) {
210 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0001);
211 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0400);
212 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0001);
213 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0500);
214 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0002);
215 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0800);
216 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0002);
217 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0A00);
218 } else if (dev->phy.rev == 1 ||
219 (bus->sprom.boardflags_lo & B43_BFL_FEM)) {
220 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0004);
221 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0800);
222 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0004);
223 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0C00);
224 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0002);
225 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0100);
226 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0002);
227 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0300);
228 } else {
229 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x000A);
230 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0900);
231 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x000A);
232 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0B00);
233 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0006);
234 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0500);
235 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0006);
236 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0700);
237 }
238 if (dev->phy.rev == 1) {
239 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_5, B43_LPPHY_TR_LOOKUP_1);
240 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_6, B43_LPPHY_TR_LOOKUP_2);
241 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_7, B43_LPPHY_TR_LOOKUP_3);
242 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_8, B43_LPPHY_TR_LOOKUP_4);
243 }
244 if ((bus->sprom.boardflags_hi & B43_BFH_FEM_BT) &&
245 (bus->chip_id == 0x5354) &&
246 (bus->chip_package == SSB_CHIPPACK_BCM4712S)) {
247 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x0006);
248 b43_phy_write(dev, B43_LPPHY_GPIO_SELECT, 0x0005);
249 b43_phy_write(dev, B43_LPPHY_GPIO_OUTEN, 0xFFFF);
7c81e98a 250 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_PR45960W);
738f0f43
GS		 251 }
252 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
253 b43_phy_set(dev, B43_LPPHY_LP_PHY_CTL, 0x8000);
254 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x0040);
255 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0x00FF, 0xA400);
256 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xF0FF, 0x0B00);
257 b43_phy_maskset(dev, B43_LPPHY_SYNCPEAKCNT, 0xFFF8, 0x0007);
258 b43_phy_maskset(dev, B43_LPPHY_DSSS_CONFIRM_CNT, 0xFFF8, 0x0003);
259 b43_phy_maskset(dev, B43_LPPHY_DSSS_CONFIRM_CNT, 0xFFC7, 0x0020);
260 b43_phy_mask(dev, B43_LPPHY_IDLEAFTERPKTRXTO, 0x00FF);
261 } else { /* 5GHz */
262 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0x7FFF);
263 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFBF);
264 }
265 if (dev->phy.rev == 1) {
266 tmp = b43_phy_read(dev, B43_LPPHY_CLIPCTRTHRESH);
267 tmp2 = (tmp & 0x03E0) >> 5;
268 tmp2 |= tmp << 5;
269 b43_phy_write(dev, B43_LPPHY_4C3, tmp2);
270 tmp = b43_phy_read(dev, B43_LPPHY_OFDMSYNCTHRESH0);
271 tmp2 = (tmp & 0x1F00) >> 8;
272 tmp2 |= tmp << 5;
273 b43_phy_write(dev, B43_LPPHY_4C4, tmp2);
274 tmp = b43_phy_read(dev, B43_LPPHY_VERYLOWGAINDB);
275 tmp2 = tmp & 0x00FF;
276 tmp2 |= tmp << 8;
277 b43_phy_write(dev, B43_LPPHY_4C5, tmp2);
278 }
a387cc7d
MB		 279}
280
a3e14f3d
GS		 281static void lpphy_save_dig_flt_state(struct b43_wldev *dev)
282{
283 static const u16 addr[] = {
284 B43_PHY_OFDM(0xC1),
285 B43_PHY_OFDM(0xC2),
286 B43_PHY_OFDM(0xC3),
287 B43_PHY_OFDM(0xC4),
288 B43_PHY_OFDM(0xC5),
289 B43_PHY_OFDM(0xC6),
290 B43_PHY_OFDM(0xC7),
291 B43_PHY_OFDM(0xC8),
292 B43_PHY_OFDM(0xCF),
293 };
294
295 static const u16 coefs[] = {
296 0xDE5E, 0xE832, 0xE331, 0x4D26,
297 0x0026, 0x1420, 0x0020, 0xFE08,
298 0x0008,
299 };
300
301 struct b43_phy_lp *lpphy = dev->phy.lp;
302 int i;
303
304 for (i = 0; i < ARRAY_SIZE(addr); i++) {
305 lpphy->dig_flt_state[i] = b43_phy_read(dev, addr[i]);
306 b43_phy_write(dev, addr[i], coefs[i]);
307 }
308}
309
310static void lpphy_restore_dig_flt_state(struct b43_wldev *dev)
311{
312 static const u16 addr[] = {
313 B43_PHY_OFDM(0xC1),
314 B43_PHY_OFDM(0xC2),
315 B43_PHY_OFDM(0xC3),
316 B43_PHY_OFDM(0xC4),
317 B43_PHY_OFDM(0xC5),
318 B43_PHY_OFDM(0xC6),
319 B43_PHY_OFDM(0xC7),
320 B43_PHY_OFDM(0xC8),
321 B43_PHY_OFDM(0xCF),
322 };
323
324 struct b43_phy_lp *lpphy = dev->phy.lp;
325 int i;
326
327 for (i = 0; i < ARRAY_SIZE(addr); i++)
328 b43_phy_write(dev, addr[i], lpphy->dig_flt_state[i]);
329}
330
a387cc7d
MB		 331static void lpphy_baseband_rev2plus_init(struct b43_wldev *dev)
332{
686aa5f2 333 struct ssb_bus *bus = dev->dev->bus;
6c1bb927
MB		 334 struct b43_phy_lp *lpphy = dev->phy.lp;
335
336 b43_phy_write(dev, B43_LPPHY_AFE_DAC_CTL, 0x50);
337 b43_phy_write(dev, B43_LPPHY_AFE_CTL, 0x8800);
338 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, 0);
339 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0);
340 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, 0);
341 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0);
342 b43_phy_write(dev, B43_PHY_OFDM(0xF9), 0);
343 b43_phy_write(dev, B43_LPPHY_TR_LOOKUP_1, 0);
344 b43_phy_set(dev, B43_LPPHY_ADC_COMPENSATION_CTL, 0x10);
a3e14f3d 345 b43_phy_maskset(dev, B43_LPPHY_OFDMSYNCTHRESH0, 0xFF00, 0xB4);
6c1bb927
MB		 346 b43_phy_maskset(dev, B43_LPPHY_DCOFFSETTRANSIENT, 0xF8FF, 0x200);
347 b43_phy_maskset(dev, B43_LPPHY_DCOFFSETTRANSIENT, 0xFF00, 0x7F);
348 b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xFF0F, 0x40);
349 b43_phy_maskset(dev, B43_LPPHY_PREAMBLECONFIRMTO, 0xFF00, 0x2);
350 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x4000);
351 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x2000);
352 b43_phy_set(dev, B43_PHY_OFDM(0x10A), 0x1);
a3e14f3d
GS		 353 if (bus->boardinfo.rev >= 0x18) {
354 b43_lptab_write(dev, B43_LPTAB32(17, 65), 0xEC);
355 b43_phy_maskset(dev, B43_PHY_OFDM(0x10A), 0xFF01, 0x14);
356 } else {
357 b43_phy_maskset(dev, B43_PHY_OFDM(0x10A), 0xFF01, 0x10);
358 }
6c1bb927 359 b43_phy_maskset(dev, B43_PHY_OFDM(0xDF), 0xFF00, 0xF4);
24b5bcc6 360 b43_phy_maskset(dev, B43_PHY_OFDM(0xDF), 0x00FF, 0xF100);
6c1bb927
MB		 361 b43_phy_write(dev, B43_LPPHY_CLIPTHRESH, 0x48);
362 b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0xFF00, 0x46);
363 b43_phy_maskset(dev, B43_PHY_OFDM(0xE4), 0xFF00, 0x10);
364 b43_phy_maskset(dev, B43_LPPHY_PWR_THRESH1, 0xFFF0, 0x9);
365 b43_phy_mask(dev, B43_LPPHY_GAINDIRECTMISMATCH, ~0xF);
366 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0x00FF, 0x5500);
367 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xF81F, 0xA0);
368 b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xE0FF, 0x300);
369 b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0x00FF, 0x2A00);
686aa5f2
MB		 370 if ((bus->chip_id == 0x4325) && (bus->chip_rev == 0)) {
371 b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x2100);
372 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0xA);
373 } else {
374 b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x1E00);
375 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0xD);
376 }
6c1bb927
MB		 377 b43_phy_maskset(dev, B43_PHY_OFDM(0xFE), 0xFFE0, 0x1F);
378 b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0xFFE0, 0xC);
379 b43_phy_maskset(dev, B43_PHY_OFDM(0x100), 0xFF00, 0x19);
380 b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0x03FF, 0x3C00);
381 b43_phy_maskset(dev, B43_PHY_OFDM(0xFE), 0xFC1F, 0x3E0);
382 b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0xFFE0, 0xC);
383 b43_phy_maskset(dev, B43_PHY_OFDM(0x100), 0x00FF, 0x1900);
384 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0x83FF, 0x5800);
385 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFFE0, 0x12);
386 b43_phy_maskset(dev, B43_LPPHY_GAINMISMATCH, 0x0FFF, 0x9000);
387
a3e14f3d
GS		 388 if ((bus->chip_id == 0x4325) && (bus->chip_rev == 1)) {
389 b43_lptab_write(dev, B43_LPTAB16(0x08, 0x14), 0);
390 b43_lptab_write(dev, B43_LPTAB16(0x08, 0x12), 0x40);
391 }
6c1bb927
MB		 392
393 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
394 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x40);
395 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xF0FF, 0xB00);
396 b43_phy_maskset(dev, B43_LPPHY_SYNCPEAKCNT, 0xFFF8, 0x6);
397 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0x00FF, 0x9D00);
398 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0xFF00, 0xA1);
399 } else /* 5GHz */
400 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x40);
401
402 b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0xFF00, 0xB3);
403 b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0x00FF, 0xAD00);
404 b43_phy_maskset(dev, B43_LPPHY_INPUT_PWRDB, 0xFF00, lpphy->rx_pwr_offset);
405 b43_phy_set(dev, B43_LPPHY_RESET_CTL, 0x44);
406 b43_phy_write(dev, B43_LPPHY_RESET_CTL, 0x80);
407 b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_0, 0xA954);
408 b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_1,
409 0x2000 | ((u16)lpphy->rssi_gs << 10) |
410 ((u16)lpphy->rssi_vc << 4) | lpphy->rssi_vf);
a3e14f3d
GS		 411
412 if ((bus->chip_id == 0x4325) && (bus->chip_rev == 0)) {
413 b43_phy_set(dev, B43_LPPHY_AFE_ADC_CTL_0, 0x1C);
414 b43_phy_maskset(dev, B43_LPPHY_AFE_CTL, 0x00FF, 0x8800);
415 b43_phy_maskset(dev, B43_LPPHY_AFE_ADC_CTL_1, 0xFC3C, 0x0400);
416 }
417
418 lpphy_save_dig_flt_state(dev);
a387cc7d
MB		 419}
420
421static void lpphy_baseband_init(struct b43_wldev *dev)
422{
423 lpphy_table_init(dev);
424 if (dev->phy.rev >= 2)
425 lpphy_baseband_rev2plus_init(dev);
426 else
427 lpphy_baseband_rev0_1_init(dev);
428}
429
24b5bcc6
MB		 430struct b2062_freqdata {
431 u16 freq;
432 u8 data[6];
433};
434
435/* Initialize the 2062 radio. */
436static void lpphy_2062_init(struct b43_wldev *dev)
437{
99e0fca6 438 struct ssb_bus *bus = dev->dev->bus;
24b5bcc6
MB		 439 u32 crystalfreq, pdiv, tmp, ref;
440 unsigned int i;
441 const struct b2062_freqdata *fd = NULL;
442
443 static const struct b2062_freqdata freqdata_tab[] = {
444 { .freq = 12000, .data[0] = 6, .data[1] = 6, .data[2] = 6,
445 .data[3] = 6, .data[4] = 10, .data[5] = 6, },
446 { .freq = 13000, .data[0] = 4, .data[1] = 4, .data[2] = 4,
447 .data[3] = 4, .data[4] = 11, .data[5] = 7, },
448 { .freq = 14400, .data[0] = 3, .data[1] = 3, .data[2] = 3,
449 .data[3] = 3, .data[4] = 12, .data[5] = 7, },
450 { .freq = 16200, .data[0] = 3, .data[1] = 3, .data[2] = 3,
451 .data[3] = 3, .data[4] = 13, .data[5] = 8, },
452 { .freq = 18000, .data[0] = 2, .data[1] = 2, .data[2] = 2,
453 .data[3] = 2, .data[4] = 14, .data[5] = 8, },
454 { .freq = 19200, .data[0] = 1, .data[1] = 1, .data[2] = 1,
455 .data[3] = 1, .data[4] = 14, .data[5] = 9, },
456 };
457
458 b2062_upload_init_table(dev);
459
460 b43_radio_write(dev, B2062_N_TX_CTL3, 0);
461 b43_radio_write(dev, B2062_N_TX_CTL4, 0);
462 b43_radio_write(dev, B2062_N_TX_CTL5, 0);
463 b43_radio_write(dev, B2062_N_PDN_CTL0, 0x40);
464 b43_radio_write(dev, B2062_N_PDN_CTL0, 0);
465 b43_radio_write(dev, B2062_N_CALIB_TS, 0x10);
466 b43_radio_write(dev, B2062_N_CALIB_TS, 0);
467 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
468 b43_radio_set(dev, B2062_N_TSSI_CTL0, 0x1);
469 else
470 b43_radio_mask(dev, B2062_N_TSSI_CTL0, ~0x1);
471
99e0fca6
MB		 472 /* Get the crystal freq, in Hz. */
473 crystalfreq = bus->chipco.pmu.crystalfreq * 1000;
474
475 B43_WARN_ON(!(bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU));
476 B43_WARN_ON(crystalfreq == 0);
24b5bcc6
MB		 477
478 if (crystalfreq >= 30000000) {
479 pdiv = 1;
480 b43_radio_mask(dev, B2062_S_RFPLL_CTL1, 0xFFFB);
481 } else {
482 pdiv = 2;
483 b43_radio_set(dev, B2062_S_RFPLL_CTL1, 0x4);
484 }
485
486 tmp = (800000000 * pdiv + crystalfreq) / (32000000 * pdiv);
487 tmp = (tmp - 1) & 0xFF;
488 b43_radio_write(dev, B2062_S_RFPLL_CTL18, tmp);
489
490 tmp = (2 * crystalfreq + 1000000 * pdiv) / (2000000 * pdiv);
491 tmp = ((tmp & 0xFF) - 1) & 0xFFFF;
492 b43_radio_write(dev, B2062_S_RFPLL_CTL19, tmp);
493
494 ref = (1000 * pdiv + 2 * crystalfreq) / (2000 * pdiv);
495 ref &= 0xFFFF;
496 for (i = 0; i < ARRAY_SIZE(freqdata_tab); i++) {
497 if (ref < freqdata_tab[i].freq) {
498 fd = &freqdata_tab[i];
499 break;
500 }
501 }
99e0fca6
MB		 502 if (!fd)
503 fd = &freqdata_tab[ARRAY_SIZE(freqdata_tab) - 1];
504 b43dbg(dev->wl, "b2062: Using crystal tab entry %u kHz.\n",
505 fd->freq); /* FIXME: Keep this printk until the code is fully debugged. */
24b5bcc6
MB		 506
507 b43_radio_write(dev, B2062_S_RFPLL_CTL8,
508 ((u16)(fd->data[1]) << 4) | fd->data[0]);
509 b43_radio_write(dev, B2062_S_RFPLL_CTL9,
99e0fca6 510 ((u16)(fd->data[3]) << 4) | fd->data[2]);
24b5bcc6
MB		 511 b43_radio_write(dev, B2062_S_RFPLL_CTL10, fd->data[4]);
512 b43_radio_write(dev, B2062_S_RFPLL_CTL11, fd->data[5]);
513}
514
515/* Initialize the 2063 radio. */
516static void lpphy_2063_init(struct b43_wldev *dev)
a387cc7d 517{
c10e47f4
GS		 518 b2063_upload_init_table(dev);
519 b43_radio_write(dev, B2063_LOGEN_SP5, 0);
520 b43_radio_set(dev, B2063_COMM8, 0x38);
521 b43_radio_write(dev, B2063_REG_SP1, 0x56);
522 b43_radio_mask(dev, B2063_RX_BB_CTL2, ~0x2);
523 b43_radio_write(dev, B2063_PA_SP7, 0);
524 b43_radio_write(dev, B2063_TX_RF_SP6, 0x20);
525 b43_radio_write(dev, B2063_TX_RF_SP9, 0x40);
526 b43_radio_write(dev, B2063_PA_SP3, 0xa0);
527 b43_radio_write(dev, B2063_PA_SP4, 0xa0);
528 b43_radio_write(dev, B2063_PA_SP2, 0x18);
a387cc7d
MB		 529}
530
3281d95d
GS		 531struct lpphy_stx_table_entry {
532 u16 phy_offset;
533 u16 phy_shift;
534 u16 rf_addr;
535 u16 rf_shift;
536 u16 mask;
537};
538
539static const struct lpphy_stx_table_entry lpphy_stx_table[] = {
540 { .phy_offset = 2, .phy_shift = 6, .rf_addr = 0x3d, .rf_shift = 3, .mask = 0x01, },
541 { .phy_offset = 1, .phy_shift = 12, .rf_addr = 0x4c, .rf_shift = 1, .mask = 0x01, },
542 { .phy_offset = 1, .phy_shift = 8, .rf_addr = 0x50, .rf_shift = 0, .mask = 0x7f, },
543 { .phy_offset = 0, .phy_shift = 8, .rf_addr = 0x44, .rf_shift = 0, .mask = 0xff, },
544 { .phy_offset = 1, .phy_shift = 0, .rf_addr = 0x4a, .rf_shift = 0, .mask = 0xff, },
545 { .phy_offset = 0, .phy_shift = 4, .rf_addr = 0x4d, .rf_shift = 0, .mask = 0xff, },
546 { .phy_offset = 1, .phy_shift = 4, .rf_addr = 0x4e, .rf_shift = 0, .mask = 0xff, },
547 { .phy_offset = 0, .phy_shift = 12, .rf_addr = 0x4f, .rf_shift = 0, .mask = 0x0f, },
548 { .phy_offset = 1, .phy_shift = 0, .rf_addr = 0x4f, .rf_shift = 4, .mask = 0x0f, },
549 { .phy_offset = 3, .phy_shift = 0, .rf_addr = 0x49, .rf_shift = 0, .mask = 0x0f, },
550 { .phy_offset = 4, .phy_shift = 3, .rf_addr = 0x46, .rf_shift = 4, .mask = 0x07, },
551 { .phy_offset = 3, .phy_shift = 15, .rf_addr = 0x46, .rf_shift = 0, .mask = 0x01, },
552 { .phy_offset = 4, .phy_shift = 0, .rf_addr = 0x46, .rf_shift = 1, .mask = 0x07, },
553 { .phy_offset = 3, .phy_shift = 8, .rf_addr = 0x48, .rf_shift = 4, .mask = 0x07, },
554 { .phy_offset = 3, .phy_shift = 11, .rf_addr = 0x48, .rf_shift = 0, .mask = 0x0f, },
555 { .phy_offset = 3, .phy_shift = 4, .rf_addr = 0x49, .rf_shift = 4, .mask = 0x0f, },
556 { .phy_offset = 2, .phy_shift = 15, .rf_addr = 0x45, .rf_shift = 0, .mask = 0x01, },
557 { .phy_offset = 5, .phy_shift = 13, .rf_addr = 0x52, .rf_shift = 4, .mask = 0x07, },
558 { .phy_offset = 6, .phy_shift = 0, .rf_addr = 0x52, .rf_shift = 7, .mask = 0x01, },
559 { .phy_offset = 5, .phy_shift = 3, .rf_addr = 0x41, .rf_shift = 5, .mask = 0x07, },
560 { .phy_offset = 5, .phy_shift = 6, .rf_addr = 0x41, .rf_shift = 0, .mask = 0x0f, },
561 { .phy_offset = 5, .phy_shift = 10, .rf_addr = 0x42, .rf_shift = 5, .mask = 0x07, },
562 { .phy_offset = 4, .phy_shift = 15, .rf_addr = 0x42, .rf_shift = 0, .mask = 0x01, },
563 { .phy_offset = 5, .phy_shift = 0, .rf_addr = 0x42, .rf_shift = 1, .mask = 0x07, },
564 { .phy_offset = 4, .phy_shift = 11, .rf_addr = 0x43, .rf_shift = 4, .mask = 0x0f, },
565 { .phy_offset = 4, .phy_shift = 7, .rf_addr = 0x43, .rf_shift = 0, .mask = 0x0f, },
566 { .phy_offset = 4, .phy_shift = 6, .rf_addr = 0x45, .rf_shift = 1, .mask = 0x01, },
567 { .phy_offset = 2, .phy_shift = 7, .rf_addr = 0x40, .rf_shift = 4, .mask = 0x0f, },
568 { .phy_offset = 2, .phy_shift = 11, .rf_addr = 0x40, .rf_shift = 0, .mask = 0x0f, },
569};
570
24b5bcc6
MB		 571static void lpphy_sync_stx(struct b43_wldev *dev)
572{
3281d95d
GS		 573 const struct lpphy_stx_table_entry *e;
574 unsigned int i;
575 u16 tmp;
576
577 for (i = 0; i < ARRAY_SIZE(lpphy_stx_table); i++) {
578 e = &lpphy_stx_table[i];
579 tmp = b43_radio_read(dev, e->rf_addr);
580 tmp >>= e->rf_shift;
581 tmp <<= e->phy_shift;
582 b43_phy_maskset(dev, B43_PHY_OFDM(0xF2 + e->phy_offset),
d44517f2 583 ~(e->mask << e->phy_shift), tmp);
3281d95d 584 }
24b5bcc6
MB		 585}
586
587static void lpphy_radio_init(struct b43_wldev *dev)
588{
589 /* The radio is attached through the 4wire bus. */
590 b43_phy_set(dev, B43_LPPHY_FOURWIRE_CTL, 0x2);
591 udelay(1);
592 b43_phy_mask(dev, B43_LPPHY_FOURWIRE_CTL, 0xFFFD);
593 udelay(1);
594
595 if (dev->phy.rev < 2) {
596 lpphy_2062_init(dev);
597 } else {
598 lpphy_2063_init(dev);
599 lpphy_sync_stx(dev);
600 b43_phy_write(dev, B43_PHY_OFDM(0xF0), 0x5F80);
601 b43_phy_write(dev, B43_PHY_OFDM(0xF1), 0);
3281d95d
GS		 602 if (dev->dev->bus->chip_id == 0x4325) {
603 // TODO SSB PMU recalibration
604 }
24b5bcc6
MB		 605 }
606}
607
560ad81b
GS		 608struct lpphy_iq_est { u32 iq_prod, i_pwr, q_pwr; };
609
d4de9532
GS		 610static void lpphy_set_rc_cap(struct b43_wldev *dev)
611{
612 u8 rc_cap = dev->phy.lp->rc_cap;
613
614 b43_radio_write(dev, B2062_N_RXBB_CALIB2, max_t(u8, rc_cap-4, 0x80));
615 b43_radio_write(dev, B2062_N_TX_CTL_A, ((rc_cap & 0x1F) >> 1) | 0x80);
616 b43_radio_write(dev, B2062_S_RXG_CNT16, ((rc_cap & 0x1F) >> 2) | 0x80);
617}
618
560ad81b 619static u8 lpphy_get_bb_mult(struct b43_wldev *dev)
d4de9532 620{
560ad81b 621 return (b43_lptab_read(dev, B43_LPTAB16(0, 87)) & 0xFF00) >> 8;
d4de9532
GS		 622}
623
560ad81b 624static void lpphy_set_bb_mult(struct b43_wldev *dev, u8 bb_mult)
d4de9532 625{
560ad81b
GS		 626 b43_lptab_write(dev, B43_LPTAB16(0, 87), (u16)bb_mult << 8);
627}
d4de9532 628
560ad81b
GS		 629static void lpphy_disable_crs(struct b43_wldev *dev)
630{
631 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFF1F, 0x80);
632 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFC, 0x1);
633 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x3);
634 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFB);
635 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x4);
636 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFF7);
637 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x8);
638 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x10);
639 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x10);
640 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFDF);
641 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x20);
642 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFBF);
643 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x40);
644 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0x7);
645 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0x38);
646 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFF3F);
647 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0x100);
648 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFDFF);
649 b43_phy_write(dev, B43_LPPHY_PS_CTL_OVERRIDE_VAL0, 0);
650 b43_phy_write(dev, B43_LPPHY_PS_CTL_OVERRIDE_VAL1, 1);
651 b43_phy_write(dev, B43_LPPHY_PS_CTL_OVERRIDE_VAL2, 0x20);
652 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFBFF);
653 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xF7FF);
654 b43_phy_write(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL, 0);
655 b43_phy_write(dev, B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL, 0x45AF);
656 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0x3FF);
657}
d4de9532 658
560ad81b
GS		 659static void lpphy_restore_crs(struct b43_wldev *dev)
660{
661 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
662 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFF1F, 0x60);
663 else
664 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFF1F, 0x20);
665 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFF80);
666 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFC00);
667}
668
669struct lpphy_tx_gains { u16 gm, pga, pad, dac; };
670
671static struct lpphy_tx_gains lpphy_get_tx_gains(struct b43_wldev *dev)
672{
673 struct lpphy_tx_gains gains;
674 u16 tmp;
675
676 gains.dac = (b43_phy_read(dev, B43_LPPHY_AFE_DAC_CTL) & 0x380) >> 7;
677 if (dev->phy.rev < 2) {
678 tmp = b43_phy_read(dev,
679 B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL) & 0x7FF;
680 gains.gm = tmp & 0x0007;
681 gains.pga = (tmp & 0x0078) >> 3;
682 gains.pad = (tmp & 0x780) >> 7;
683 } else {
684 tmp = b43_phy_read(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL);
685 gains.pad = b43_phy_read(dev, B43_PHY_OFDM(0xFB)) & 0xFF;
686 gains.gm = tmp & 0xFF;
687 gains.pga = (tmp >> 8) & 0xFF;
d4de9532
GS		 688 }
689
560ad81b
GS		 690 return gains;
691}
d4de9532 692
560ad81b
GS		 693static void lpphy_set_dac_gain(struct b43_wldev *dev, u16 dac)
694{
695 u16 ctl = b43_phy_read(dev, B43_LPPHY_AFE_DAC_CTL) & 0xC7F;
696 ctl |= dac << 7;
697 b43_phy_maskset(dev, B43_LPPHY_AFE_DAC_CTL, 0xF000, ctl);
698}
d4de9532 699
560ad81b
GS		 700static void lpphy_set_tx_gains(struct b43_wldev *dev,
701 struct lpphy_tx_gains gains)
702{
703 u16 rf_gain, pa_gain;
d4de9532 704
560ad81b
GS		 705 if (dev->phy.rev < 2) {
706 rf_gain = (gains.pad << 7) | (gains.pga << 3) | gains.gm;
707 b43_phy_maskset(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL,
708 0xF800, rf_gain);
d4de9532 709 } else {
560ad81b
GS		 710 pa_gain = b43_phy_read(dev, B43_PHY_OFDM(0xFB)) & 0x7F00;
711 b43_phy_write(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL,
712 (gains.pga << 8) | gains.gm);
713 b43_phy_maskset(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL,
714 0x8000, gains.pad | pa_gain);
715 b43_phy_write(dev, B43_PHY_OFDM(0xFC),
716 (gains.pga << 8) | gains.gm);
717 b43_phy_maskset(dev, B43_PHY_OFDM(0xFD),
718 0x8000, gains.pad | pa_gain);
d4de9532 719 }
560ad81b
GS		 720 lpphy_set_dac_gain(dev, gains.dac);
721 if (dev->phy.rev < 2) {
722 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF, 1 << 8);
723 } else {
724 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFF7F, 1 << 7);
725 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2, 0xBFFF, 1 << 14);
726 }
727 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFFBF, 1 << 4);
728}
d4de9532 729
560ad81b
GS		 730static void lpphy_rev0_1_set_rx_gain(struct b43_wldev *dev, u32 gain)
731{
732 u16 trsw = gain & 0x1;
733 u16 lna = (gain & 0xFFFC) | ((gain & 0xC) >> 2);
734 u16 ext_lna = (gain & 2) >> 1;
735
736 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFE, trsw);
737 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
738 0xFBFF, ext_lna << 10);
739 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
740 0xF7FF, ext_lna << 11);
741 b43_phy_write(dev, B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL, lna);
742}
d4de9532 743
560ad81b
GS		 744static void lpphy_rev2plus_set_rx_gain(struct b43_wldev *dev, u32 gain)
745{
746 u16 low_gain = gain & 0xFFFF;
747 u16 high_gain = (gain >> 16) & 0xF;
748 u16 ext_lna = (gain >> 21) & 0x1;
749 u16 trsw = ~(gain >> 20) & 0x1;
750 u16 tmp;
751
752 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFE, trsw);
753 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
754 0xFDFF, ext_lna << 9);
755 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
756 0xFBFF, ext_lna << 10);
757 b43_phy_write(dev, B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL, low_gain);
758 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFFF0, high_gain);
759 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
760 tmp = (gain >> 2) & 0x3;
761 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
762 0xE7FF, tmp<<11);
763 b43_phy_maskset(dev, B43_PHY_OFDM(0xE6), 0xFFE7, tmp << 3);
764 }
765}
766
767static void lpphy_enable_rx_gain_override(struct b43_wldev *dev)
768{
769 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFFE);
770 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFEF);
771 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFBF);
772 if (dev->phy.rev >= 2) {
773 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF);
774 if (b43_current_band(dev->wl) != IEEE80211_BAND_2GHZ)
775 return;
776 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFBFF);
777 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFFF7);
778 } else {
779 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFDFF);
780 }
781}
782
783static void lpphy_disable_rx_gain_override(struct b43_wldev *dev)
784{
785 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x1);
786 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x10);
787 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x40);
788 if (dev->phy.rev >= 2) {
789 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x100);
790 if (b43_current_band(dev->wl) != IEEE80211_BAND_2GHZ)
791 return;
792 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x400);
793 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x8);
794 } else {
795 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x200);
796 }
797}
798
799static void lpphy_set_rx_gain(struct b43_wldev *dev, u32 gain)
800{
801 if (dev->phy.rev < 2)
802 lpphy_rev0_1_set_rx_gain(dev, gain);
803 else
804 lpphy_rev2plus_set_rx_gain(dev, gain);
805 lpphy_enable_rx_gain_override(dev);
806}
807
808static void lpphy_set_rx_gain_by_index(struct b43_wldev *dev, u16 idx)
809{
810 u32 gain = b43_lptab_read(dev, B43_LPTAB16(12, idx));
811 lpphy_set_rx_gain(dev, gain);
812}
813
814static void lpphy_stop_ddfs(struct b43_wldev *dev)
815{
816 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS, 0xFFFD);
817 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0xFFDF);
818}
819
820static void lpphy_run_ddfs(struct b43_wldev *dev, int i_on, int q_on,
821 int incr1, int incr2, int scale_idx)
822{
823 lpphy_stop_ddfs(dev);
824 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS_POINTER_INIT, 0xFF80);
825 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS_POINTER_INIT, 0x80FF);
826 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS_INCR_INIT, 0xFF80, incr1);
827 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS_INCR_INIT, 0x80FF, incr2 << 8);
828 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFFF7, i_on << 3);
829 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFFEF, q_on << 4);
830 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFF9F, scale_idx << 5);
831 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS, 0xFFFB);
832 b43_phy_set(dev, B43_LPPHY_AFE_DDFS, 0x2);
833 b43_phy_set(dev, B43_LPPHY_AFE_DDFS, 0x20);
834}
835
836static bool lpphy_rx_iq_est(struct b43_wldev *dev, u16 samples, u8 time,
837 struct lpphy_iq_est *iq_est)
838{
839 int i;
840
841 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFF7);
842 b43_phy_write(dev, B43_LPPHY_IQ_NUM_SMPLS_ADDR, samples);
843 b43_phy_maskset(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0xFF00, time);
844 b43_phy_mask(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0xFEFF);
845 b43_phy_set(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0xFDFF);
846
847 for (i = 0; i < 500; i++) {
848 if (!(b43_phy_read(dev,
849 B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR) & 0x200))
d4de9532
GS		 850 break;
851 msleep(1);
852 }
853
560ad81b
GS		 854 if ((b43_phy_read(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR) & 0x200)) {
855 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x8);
856 return false;
857 }
d4de9532 858
560ad81b
GS		 859 iq_est->iq_prod = b43_phy_read(dev, B43_LPPHY_IQ_ACC_HI_ADDR);
860 iq_est->iq_prod <<= 16;
861 iq_est->iq_prod |= b43_phy_read(dev, B43_LPPHY_IQ_ACC_LO_ADDR);
862
863 iq_est->i_pwr = b43_phy_read(dev, B43_LPPHY_IQ_I_PWR_ACC_HI_ADDR);
864 iq_est->i_pwr <<= 16;
865 iq_est->i_pwr |= b43_phy_read(dev, B43_LPPHY_IQ_I_PWR_ACC_LO_ADDR);
866
867 iq_est->q_pwr = b43_phy_read(dev, B43_LPPHY_IQ_Q_PWR_ACC_HI_ADDR);
868 iq_est->q_pwr <<= 16;
869 iq_est->q_pwr |= b43_phy_read(dev, B43_LPPHY_IQ_Q_PWR_ACC_LO_ADDR);
870
871 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x8);
872 return true;
d4de9532
GS		 873}
874
560ad81b 875static int lpphy_loopback(struct b43_wldev *dev)
d4de9532 876{
560ad81b
GS		 877 struct lpphy_iq_est iq_est;
878 int i, index = -1;
879 u32 tmp;
880
881 memset(&iq_est, 0, sizeof(iq_est));
882
883 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFC, 0x3);
884 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x3);
885 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xFFFE);
886 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x800);
887 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x800);
888 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x8);
889 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x8);
890 b43_radio_write(dev, B2062_N_TX_CTL_A, 0x80);
891 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x80);
892 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x80);
893 for (i = 0; i < 32; i++) {
894 lpphy_set_rx_gain_by_index(dev, i);
895 lpphy_run_ddfs(dev, 1, 1, 5, 5, 0);
896 if (!(lpphy_rx_iq_est(dev, 1000, 32, &iq_est)))
897 continue;
898 tmp = (iq_est.i_pwr + iq_est.q_pwr) / 1000;
899 if ((tmp > 4000) && (tmp < 10000)) {
900 index = i;
901 break;
902 }
903 }
904 lpphy_stop_ddfs(dev);
905 return index;
906}
d4de9532 907
560ad81b
GS		 908static u32 lpphy_qdiv_roundup(u32 dividend, u32 divisor, u8 precision)
909{
910 u32 quotient, remainder, rbit, roundup, tmp;
911
912 if (divisor == 0) {
913 quotient = 0;
914 remainder = 0;
d4de9532 915 } else {
560ad81b
GS		 916 quotient = dividend / divisor;
917 remainder = dividend % divisor;
d4de9532 918 }
560ad81b
GS		 919
920 rbit = divisor & 0x1;
921 roundup = (divisor >> 1) + rbit;
922 precision--;
923
924 while (precision != 0xFF) {
925 tmp = remainder - roundup;
926 quotient <<= 1;
927 remainder <<= 1;
928 if (remainder >= roundup) {
929 remainder = (tmp << 1) + rbit;
930 quotient--;
931 }
932 precision--;
933 }
934
935 if (remainder >= roundup)
936 quotient++;
937
938 return quotient;
d4de9532
GS		 939}
940
ce1a9ee3
MB		 941/* Read the TX power control mode from hardware. */
942static void lpphy_read_tx_pctl_mode_from_hardware(struct b43_wldev *dev)
943{
944 struct b43_phy_lp *lpphy = dev->phy.lp;
945 u16 ctl;
946
947 ctl = b43_phy_read(dev, B43_LPPHY_TX_PWR_CTL_CMD);
948 switch (ctl & B43_LPPHY_TX_PWR_CTL_CMD_MODE) {
949 case B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF:
950 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_OFF;
951 break;
952 case B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW:
953 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_SW;
954 break;
955 case B43_LPPHY_TX_PWR_CTL_CMD_MODE_HW:
956 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_HW;
957 break;
958 default:
959 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_UNKNOWN;
960 B43_WARN_ON(1);
961 break;
962 }
963}
964
965/* Set the TX power control mode in hardware. */
966static void lpphy_write_tx_pctl_mode_to_hardware(struct b43_wldev *dev)
967{
968 struct b43_phy_lp *lpphy = dev->phy.lp;
969 u16 ctl;
970
971 switch (lpphy->txpctl_mode) {
972 case B43_LPPHY_TXPCTL_OFF:
973 ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF;
974 break;
975 case B43_LPPHY_TXPCTL_HW:
976 ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_HW;
977 break;
978 case B43_LPPHY_TXPCTL_SW:
979 ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW;
980 break;
981 default:
982 ctl = 0;
983 B43_WARN_ON(1);
984 }
985 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
986 (u16)~B43_LPPHY_TX_PWR_CTL_CMD_MODE, ctl);
987}
988
989static void lpphy_set_tx_power_control(struct b43_wldev *dev,
990 enum b43_lpphy_txpctl_mode mode)
991{
992 struct b43_phy_lp *lpphy = dev->phy.lp;
993 enum b43_lpphy_txpctl_mode oldmode;
994
995 oldmode = lpphy->txpctl_mode;
996 lpphy_read_tx_pctl_mode_from_hardware(dev);
997 if (lpphy->txpctl_mode == mode)
998 return;
999 lpphy->txpctl_mode = mode;
1000
1001 if (oldmode == B43_LPPHY_TXPCTL_HW) {
1002 //TODO Update TX Power NPT
1003 //TODO Clear all TX Power offsets
1004 } else {
1005 if (mode == B43_LPPHY_TXPCTL_HW) {
1006 //TODO Recalculate target TX power
1007 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
1008 0xFF80, lpphy->tssi_idx);
1009 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_NNUM,
1010 0x8FFF, ((u16)lpphy->tssi_npt << 16));
1011 //TODO Set "TSSI Transmit Count" variable to total transmitted frame count
1012 //TODO Disable TX gain override
1013 lpphy->tx_pwr_idx_over = -1;
1014 }
1015 }
1016 if (dev->phy.rev >= 2) {
1017 if (mode == B43_LPPHY_TXPCTL_HW)
1018 b43_phy_maskset(dev, B43_PHY_OFDM(0xD0), 0xFD, 0x2);
1019 else
1020 b43_phy_maskset(dev, B43_PHY_OFDM(0xD0), 0xFD, 0);
1021 }
1022 lpphy_write_tx_pctl_mode_to_hardware(dev);
1023}
1024
560ad81b
GS		 1025static void lpphy_rev0_1_rc_calib(struct b43_wldev *dev)
1026{
1027 struct b43_phy_lp *lpphy = dev->phy.lp;
1028 struct lpphy_iq_est iq_est;
1029 struct lpphy_tx_gains tx_gains;
1030 static const u32 ideal_pwr_table[22] = {
1031 0x10000, 0x10557, 0x10e2d, 0x113e0, 0x10f22, 0x0ff64,
1032 0x0eda2, 0x0e5d4, 0x0efd1, 0x0fbe8, 0x0b7b8, 0x04b35,
1033 0x01a5e, 0x00a0b, 0x00444, 0x001fd, 0x000ff, 0x00088,
1034 0x0004c, 0x0002c, 0x0001a, 0xc0006,
1035 };
1036 bool old_txg_ovr;
1037 u8 old_bbmult;
1038 u16 old_rf_ovr, old_rf_ovrval, old_afe_ovr, old_afe_ovrval,
1039 old_rf2_ovr, old_rf2_ovrval, old_phy_ctl, old_txpctl;
1040 u32 normal_pwr, ideal_pwr, mean_sq_pwr, tmp = 0, mean_sq_pwr_min = 0;
1041 int loopback, i, j, inner_sum;
1042
1043 memset(&iq_est, 0, sizeof(iq_est));
1044
1045 b43_switch_channel(dev, 7);
1046 old_txg_ovr = (b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVR) >> 6) & 1;
1047 old_bbmult = lpphy_get_bb_mult(dev);
1048 if (old_txg_ovr)
1049 tx_gains = lpphy_get_tx_gains(dev);
1050 old_rf_ovr = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_0);
1051 old_rf_ovrval = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_VAL_0);
1052 old_afe_ovr = b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVR);
1053 old_afe_ovrval = b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVRVAL);
1054 old_rf2_ovr = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_2);
1055 old_rf2_ovrval = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_2_VAL);
1056 old_phy_ctl = b43_phy_read(dev, B43_LPPHY_LP_PHY_CTL);
1057 old_txpctl = b43_phy_read(dev, B43_LPPHY_TX_PWR_CTL_CMD) &
1058 B43_LPPHY_TX_PWR_CTL_CMD_MODE;
1059
1060 lpphy_set_tx_power_control(dev, B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF);
1061 lpphy_disable_crs(dev);
1062 loopback = lpphy_loopback(dev);
1063 if (loopback == -1)
1064 goto finish;
1065 lpphy_set_rx_gain_by_index(dev, loopback);
1066 b43_phy_maskset(dev, B43_LPPHY_LP_PHY_CTL, 0xFFBF, 0x40);
1067 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFFF8, 0x1);
1068 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFFC7, 0x8);
1069 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFF3F, 0xC0);
1070 for (i = 128; i <= 159; i++) {
1071 b43_radio_write(dev, B2062_N_RXBB_CALIB2, i);
1072 inner_sum = 0;
1073 for (j = 5; j <= 25; j++) {
1074 lpphy_run_ddfs(dev, 1, 1, j, j, 0);
1075 if (!(lpphy_rx_iq_est(dev, 1000, 32, &iq_est)))
1076 goto finish;
1077 mean_sq_pwr = iq_est.i_pwr + iq_est.q_pwr;
1078 if (j == 5)
1079 tmp = mean_sq_pwr;
1080 ideal_pwr = ((ideal_pwr_table[j-5] >> 3) + 1) >> 1;
1081 normal_pwr = lpphy_qdiv_roundup(mean_sq_pwr, tmp, 12);
1082 mean_sq_pwr = ideal_pwr - normal_pwr;
1083 mean_sq_pwr *= mean_sq_pwr;
1084 inner_sum += mean_sq_pwr;
1085 if ((i = 128) || (inner_sum < mean_sq_pwr_min)) {
1086 lpphy->rc_cap = i;
1087 mean_sq_pwr_min = inner_sum;
1088 }
1089 }
1090 }
1091 lpphy_stop_ddfs(dev);
1092
1093finish:
1094 lpphy_restore_crs(dev);
1095 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, old_rf_ovrval);
1096 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, old_rf_ovr);
1097 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVRVAL, old_afe_ovrval);
1098 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, old_afe_ovr);
1099 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, old_rf2_ovrval);
1100 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, old_rf2_ovr);
1101 b43_phy_write(dev, B43_LPPHY_LP_PHY_CTL, old_phy_ctl);
1102
1103 lpphy_set_bb_mult(dev, old_bbmult);
1104 if (old_txg_ovr) {
1105 /*
1106 * SPEC FIXME: The specs say "get_tx_gains" here, which is
1107 * illogical. According to lwfinger, vendor driver v4.150.10.5
1108 * has a Set here, while v4.174.64.19 has a Get - regression in
1109 * the vendor driver? This should be tested this once the code
1110 * is testable.
1111 */
1112 lpphy_set_tx_gains(dev, tx_gains);
1113 }
1114 lpphy_set_tx_power_control(dev, old_txpctl);
1115 if (lpphy->rc_cap)
1116 lpphy_set_rc_cap(dev);
1117}
1118
1119static void lpphy_rev2plus_rc_calib(struct b43_wldev *dev)
1120{
1121 struct ssb_bus *bus = dev->dev->bus;
1122 u32 crystal_freq = bus->chipco.pmu.crystalfreq * 1000;
1123 u8 tmp = b43_radio_read(dev, B2063_RX_BB_SP8) & 0xFF;
1124 int i;
1125
1126 b43_radio_write(dev, B2063_RX_BB_SP8, 0x0);
1127 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7E);
1128 b43_radio_mask(dev, B2063_PLL_SP1, 0xF7);
1129 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7C);
1130 b43_radio_write(dev, B2063_RC_CALIB_CTL2, 0x15);
1131 b43_radio_write(dev, B2063_RC_CALIB_CTL3, 0x70);
1132 b43_radio_write(dev, B2063_RC_CALIB_CTL4, 0x52);
1133 b43_radio_write(dev, B2063_RC_CALIB_CTL5, 0x1);
1134 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7D);
1135
1136 for (i = 0; i < 10000; i++) {
1137 if (b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2)
1138 break;
1139 msleep(1);
1140 }
1141
1142 if (!(b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2))
1143 b43_radio_write(dev, B2063_RX_BB_SP8, tmp);
1144
1145 tmp = b43_radio_read(dev, B2063_TX_BB_SP3) & 0xFF;
1146
1147 b43_radio_write(dev, B2063_TX_BB_SP3, 0x0);
1148 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7E);
1149 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7C);
1150 b43_radio_write(dev, B2063_RC_CALIB_CTL2, 0x55);
1151 b43_radio_write(dev, B2063_RC_CALIB_CTL3, 0x76);
1152
1153 if (crystal_freq == 24000000) {
1154 b43_radio_write(dev, B2063_RC_CALIB_CTL4, 0xFC);
1155 b43_radio_write(dev, B2063_RC_CALIB_CTL5, 0x0);
1156 } else {
1157 b43_radio_write(dev, B2063_RC_CALIB_CTL4, 0x13);
1158 b43_radio_write(dev, B2063_RC_CALIB_CTL5, 0x1);
1159 }
1160
1161 b43_radio_write(dev, B2063_PA_SP7, 0x7D);
1162
1163 for (i = 0; i < 10000; i++) {
1164 if (b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2)
1165 break;
1166 msleep(1);
1167 }
1168
1169 if (!(b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2))
1170 b43_radio_write(dev, B2063_TX_BB_SP3, tmp);
1171
1172 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7E);
1173}
1174
1175static void lpphy_calibrate_rc(struct b43_wldev *dev)
1176{
1177 struct b43_phy_lp *lpphy = dev->phy.lp;
1178
1179 if (dev->phy.rev >= 2) {
1180 lpphy_rev2plus_rc_calib(dev);
1181 } else if (!lpphy->rc_cap) {
1182 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1183 lpphy_rev0_1_rc_calib(dev);
1184 } else {
1185 lpphy_set_rc_cap(dev);
1186 }
1187}
1188
ce1a9ee3
MB		 1189static void lpphy_set_tx_power_by_index(struct b43_wldev *dev, u8 index)
1190{
1191 struct b43_phy_lp *lpphy = dev->phy.lp;
1192
1193 lpphy->tx_pwr_idx_over = index;
1194 if (lpphy->txpctl_mode != B43_LPPHY_TXPCTL_OFF)
1195 lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_SW);
1196
1197 //TODO
1198}
1199
1200static void lpphy_btcoex_override(struct b43_wldev *dev)
1201{
1202 b43_write16(dev, B43_MMIO_BTCOEX_CTL, 0x3);
1203 b43_write16(dev, B43_MMIO_BTCOEX_TXCTL, 0xFF);
1204}
1205
1206static void lpphy_pr41573_workaround(struct b43_wldev *dev)
1207{
1208 struct b43_phy_lp *lpphy = dev->phy.lp;
1209 u32 *saved_tab;
1210 const unsigned int saved_tab_size = 256;
1211 enum b43_lpphy_txpctl_mode txpctl_mode;
1212 s8 tx_pwr_idx_over;
1213 u16 tssi_npt, tssi_idx;
1214
1215 saved_tab = kcalloc(saved_tab_size, sizeof(saved_tab[0]), GFP_KERNEL);
1216 if (!saved_tab) {
1217 b43err(dev->wl, "PR41573 failed. Out of memory!\n");
1218 return;
1219 }
1220
1221 lpphy_read_tx_pctl_mode_from_hardware(dev);
1222 txpctl_mode = lpphy->txpctl_mode;
1223 tx_pwr_idx_over = lpphy->tx_pwr_idx_over;
1224 tssi_npt = lpphy->tssi_npt;
1225 tssi_idx = lpphy->tssi_idx;
1226
1227 if (dev->phy.rev < 2) {
1228 b43_lptab_read_bulk(dev, B43_LPTAB32(10, 0x140),
1229 saved_tab_size, saved_tab);
1230 } else {
1231 b43_lptab_read_bulk(dev, B43_LPTAB32(7, 0x140),
1232 saved_tab_size, saved_tab);
1233 }
1234 //TODO
1235
1236 kfree(saved_tab);
1237}
1238
1239static void lpphy_calibration(struct b43_wldev *dev)
1240{
1241 struct b43_phy_lp *lpphy = dev->phy.lp;
1242 enum b43_lpphy_txpctl_mode saved_pctl_mode;
1243
1244 b43_mac_suspend(dev);
1245
1246 lpphy_btcoex_override(dev);
1247 lpphy_read_tx_pctl_mode_from_hardware(dev);
1248 saved_pctl_mode = lpphy->txpctl_mode;
1249 lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF);
1250 //TODO Perform transmit power table I/Q LO calibration
1251 if ((dev->phy.rev == 0) && (saved_pctl_mode != B43_LPPHY_TXPCTL_OFF))
1252 lpphy_pr41573_workaround(dev);
1253 //TODO If a full calibration has not been performed on this channel yet, perform PAPD TX-power calibration
1254 lpphy_set_tx_power_control(dev, saved_pctl_mode);
1255 //TODO Perform I/Q calibration with a single control value set
1256
1257 b43_mac_enable(dev);
1258}
1259
1260/* Initialize TX power control */
1261static void lpphy_tx_pctl_init(struct b43_wldev *dev)
1262{
1263 if (0/*FIXME HWPCTL capable */) {
1264 //TODO
1265 } else { /* This device is only software TX power control capable. */
1266 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1267 //TODO
1268 } else {
1269 //TODO
1270 }
1271 //TODO set BB multiplier to 0x0096
1272 }
1273}
1274
fb11137a
MB		 1275static int b43_lpphy_op_init(struct b43_wldev *dev)
1276{
84ec167d 1277 lpphy_read_band_sprom(dev); //FIXME should this be in prepare_structs?
a387cc7d
MB		 1278 lpphy_baseband_init(dev);
1279 lpphy_radio_init(dev);
d4de9532 1280 lpphy_calibrate_rc(dev);
ce1a9ee3
MB		 1281 //TODO set channel
1282 lpphy_tx_pctl_init(dev);
c65d6fbf
GS		 1283 lpphy_calibration(dev);
1284 //TODO ACI init
fb11137a
MB		 1285
1286 return 0;
1287}
1288
e63e4363
MB		 1289static u16 b43_lpphy_op_read(struct b43_wldev *dev, u16 reg)
1290{
0888707f
MB		 1291 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
1292 return b43_read16(dev, B43_MMIO_PHY_DATA);
e63e4363
MB		 1293}
1294
1295static void b43_lpphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
1296{
0888707f
MB		 1297 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
1298 b43_write16(dev, B43_MMIO_PHY_DATA, value);
e63e4363
MB		 1299}
1300
1301static u16 b43_lpphy_op_radio_read(struct b43_wldev *dev, u16 reg)
1302{
0888707f
MB		 1303 /* Register 1 is a 32-bit register. */
1304 B43_WARN_ON(reg == 1);
1305 /* LP-PHY needs a special bit set for read access */
1306 if (dev->phy.rev < 2) {
1307 if (reg != 0x4001)
1308 reg |= 0x100;
1309 } else
1310 reg |= 0x200;
1311
1312 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
1313 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
e63e4363
MB		 1314}
1315
1316static void b43_lpphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
1317{
1318 /* Register 1 is a 32-bit register. */
1319 B43_WARN_ON(reg == 1);
1320
0888707f
MB		 1321 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
1322 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
e63e4363
MB		 1323}
1324
1325static void b43_lpphy_op_software_rfkill(struct b43_wldev *dev,
19d337df 1326 bool blocked)
e63e4363
MB		 1327{
1328 //TODO
1329}
1330
1331static int b43_lpphy_op_switch_channel(struct b43_wldev *dev,
1332 unsigned int new_channel)
1333{
1334 //TODO
1335 return 0;
1336}
1337
1338static unsigned int b43_lpphy_op_get_default_chan(struct b43_wldev *dev)
1339{
24b5bcc6
MB		 1340 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1341 return 1;
1342 return 36;
e63e4363
MB		 1343}
1344
1345static void b43_lpphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna)
1346{
1347 //TODO
1348}
1349
1350static void b43_lpphy_op_adjust_txpower(struct b43_wldev *dev)
1351{
1352 //TODO
1353}
1354
1355static enum b43_txpwr_result b43_lpphy_op_recalc_txpower(struct b43_wldev *dev,
1356 bool ignore_tssi)
1357{
1358 //TODO
1359 return B43_TXPWR_RES_DONE;
1360}
1361
e63e4363
MB		 1362const struct b43_phy_operations b43_phyops_lp = {
1363 .allocate = b43_lpphy_op_allocate,
fb11137a
MB		 1364 .free = b43_lpphy_op_free,
1365 .prepare_structs = b43_lpphy_op_prepare_structs,
e63e4363 1366 .init = b43_lpphy_op_init,
e63e4363
MB		 1367 .phy_read = b43_lpphy_op_read,
1368 .phy_write = b43_lpphy_op_write,
1369 .radio_read = b43_lpphy_op_radio_read,
1370 .radio_write = b43_lpphy_op_radio_write,
1371 .software_rfkill = b43_lpphy_op_software_rfkill,
cb24f57f 1372 .switch_analog = b43_phyop_switch_analog_generic,
e63e4363
MB		 1373 .switch_channel = b43_lpphy_op_switch_channel,
1374 .get_default_chan = b43_lpphy_op_get_default_chan,
1375 .set_rx_antenna = b43_lpphy_op_set_rx_antenna,
1376 .recalc_txpower = b43_lpphy_op_recalc_txpower,
1377 .adjust_txpower = b43_lpphy_op_adjust_txpower,
1378};
Linux 6.x block layer and io_uring tree(s)