Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
cfe8cba9 | 17 | #include "hw.h" |
8fe65368 LR |
18 | #include "hw-ops.h" |
19 | #include "../regd.h" | |
20 | #include "ar9002_phy.h" | |
a043dfb9 | 21 | #include "ar5008_initvals.h" |
e16393bb | 22 | |
e36b27af LR |
23 | /* All code below is for AR5008, AR9001, AR9002 */ |
24 | ||
25 | static const int firstep_table[] = | |
26 | /* level: 0 1 2 3 4 5 6 7 8 */ | |
27 | { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */ | |
28 | ||
29 | static const int cycpwrThr1_table[] = | |
30 | /* level: 0 1 2 3 4 5 6 7 8 */ | |
31 | { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */ | |
32 | ||
33 | /* | |
34 | * register values to turn OFDM weak signal detection OFF | |
35 | */ | |
36 | static const int m1ThreshLow_off = 127; | |
37 | static const int m2ThreshLow_off = 127; | |
38 | static const int m1Thresh_off = 127; | |
39 | static const int m2Thresh_off = 127; | |
40 | static const int m2CountThr_off = 31; | |
41 | static const int m2CountThrLow_off = 63; | |
42 | static const int m1ThreshLowExt_off = 127; | |
43 | static const int m2ThreshLowExt_off = 127; | |
44 | static const int m1ThreshExt_off = 127; | |
45 | static const int m2ThreshExt_off = 127; | |
46 | ||
a043dfb9 FF |
47 | static const struct ar5416IniArray bank0 = STATIC_INI_ARRAY(ar5416Bank0); |
48 | static const struct ar5416IniArray bank1 = STATIC_INI_ARRAY(ar5416Bank1); | |
49 | static const struct ar5416IniArray bank2 = STATIC_INI_ARRAY(ar5416Bank2); | |
50 | static const struct ar5416IniArray bank3 = STATIC_INI_ARRAY(ar5416Bank3); | |
51 | static const struct ar5416IniArray bank7 = STATIC_INI_ARRAY(ar5416Bank7); | |
e16393bb | 52 | |
a043dfb9 | 53 | static void ar5008_write_bank6(struct ath_hw *ah, unsigned int *writecnt) |
a9b6b256 | 54 | { |
a043dfb9 FF |
55 | struct ar5416IniArray *array = &ah->iniBank6; |
56 | u32 *data = ah->analogBank6Data; | |
a9b6b256 FF |
57 | int r; |
58 | ||
59 | ENABLE_REGWRITE_BUFFER(ah); | |
60 | ||
61 | for (r = 0; r < array->ia_rows; r++) { | |
62 | REG_WRITE(ah, INI_RA(array, r, 0), data[r]); | |
63 | DO_DELAY(*writecnt); | |
64 | } | |
65 | ||
66 | REGWRITE_BUFFER_FLUSH(ah); | |
67 | } | |
68 | ||
ddcd4c08 | 69 | /** |
8fe65368 | 70 | * ar5008_hw_phy_modify_rx_buffer() - perform analog swizzling of parameters |
ddcd4c08 LR |
71 | * @rfbuf: |
72 | * @reg32: | |
73 | * @numBits: | |
74 | * @firstBit: | |
75 | * @column: | |
76 | * | |
77 | * Performs analog "swizzling" of parameters into their location. | |
78 | * Used on external AR2133/AR5133 radios. | |
79 | */ | |
8fe65368 LR |
80 | static void ar5008_hw_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32, |
81 | u32 numBits, u32 firstBit, | |
82 | u32 column) | |
ddcd4c08 LR |
83 | { |
84 | u32 tmp32, mask, arrayEntry, lastBit; | |
85 | int32_t bitPosition, bitsLeft; | |
86 | ||
87 | tmp32 = ath9k_hw_reverse_bits(reg32, numBits); | |
88 | arrayEntry = (firstBit - 1) / 8; | |
89 | bitPosition = (firstBit - 1) % 8; | |
90 | bitsLeft = numBits; | |
91 | while (bitsLeft > 0) { | |
92 | lastBit = (bitPosition + bitsLeft > 8) ? | |
93 | 8 : bitPosition + bitsLeft; | |
94 | mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) << | |
95 | (column * 8); | |
96 | rfBuf[arrayEntry] &= ~mask; | |
97 | rfBuf[arrayEntry] |= ((tmp32 << bitPosition) << | |
98 | (column * 8)) & mask; | |
99 | bitsLeft -= 8 - bitPosition; | |
100 | tmp32 = tmp32 >> (8 - bitPosition); | |
101 | bitPosition = 0; | |
102 | arrayEntry++; | |
103 | } | |
104 | } | |
105 | ||
a7765828 LR |
106 | /* |
107 | * Fix on 2.4 GHz band for orientation sensitivity issue by increasing | |
108 | * rf_pwd_icsyndiv. | |
109 | * | |
110 | * Theoretical Rules: | |
111 | * if 2 GHz band | |
112 | * if forceBiasAuto | |
113 | * if synth_freq < 2412 | |
114 | * bias = 0 | |
115 | * else if 2412 <= synth_freq <= 2422 | |
116 | * bias = 1 | |
117 | * else // synth_freq > 2422 | |
118 | * bias = 2 | |
119 | * else if forceBias > 0 | |
120 | * bias = forceBias & 7 | |
121 | * else | |
122 | * no change, use value from ini file | |
123 | * else | |
124 | * no change, invalid band | |
125 | * | |
126 | * 1st Mod: | |
127 | * 2422 also uses value of 2 | |
128 | * <approved> | |
129 | * | |
130 | * 2nd Mod: | |
131 | * Less than 2412 uses value of 0, 2412 and above uses value of 2 | |
132 | */ | |
8fe65368 | 133 | static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq) |
a7765828 LR |
134 | { |
135 | struct ath_common *common = ath9k_hw_common(ah); | |
136 | u32 tmp_reg; | |
137 | int reg_writes = 0; | |
138 | u32 new_bias = 0; | |
139 | ||
8fe65368 | 140 | if (!AR_SREV_5416(ah) || synth_freq >= 3000) |
a7765828 | 141 | return; |
a7765828 | 142 | |
7a37081e | 143 | BUG_ON(AR_SREV_9280_20_OR_LATER(ah)); |
a7765828 LR |
144 | |
145 | if (synth_freq < 2412) | |
146 | new_bias = 0; | |
147 | else if (synth_freq < 2422) | |
148 | new_bias = 1; | |
149 | else | |
150 | new_bias = 2; | |
151 | ||
152 | /* pre-reverse this field */ | |
153 | tmp_reg = ath9k_hw_reverse_bits(new_bias, 3); | |
154 | ||
d2182b69 | 155 | ath_dbg(common, CONFIG, "Force rf_pwd_icsyndiv to %1d on %4d\n", |
226afe68 | 156 | new_bias, synth_freq); |
a7765828 LR |
157 | |
158 | /* swizzle rf_pwd_icsyndiv */ | |
8fe65368 | 159 | ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3); |
a7765828 LR |
160 | |
161 | /* write Bank 6 with new params */ | |
a043dfb9 | 162 | ar5008_write_bank6(ah, ®_writes); |
a7765828 LR |
163 | } |
164 | ||
e16393bb | 165 | /** |
8fe65368 | 166 | * ar5008_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios |
25985edc | 167 | * @ah: atheros hardware structure |
e16393bb LR |
168 | * @chan: |
169 | * | |
170 | * For the external AR2133/AR5133 radios, takes the MHz channel value and set | |
171 | * the channel value. Assumes writes enabled to analog bus and bank6 register | |
172 | * cache in ah->analogBank6Data. | |
173 | */ | |
8fe65368 | 174 | static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) |
e16393bb LR |
175 | { |
176 | struct ath_common *common = ath9k_hw_common(ah); | |
177 | u32 channelSel = 0; | |
178 | u32 bModeSynth = 0; | |
179 | u32 aModeRefSel = 0; | |
180 | u32 reg32 = 0; | |
181 | u16 freq; | |
182 | struct chan_centers centers; | |
183 | ||
184 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); | |
185 | freq = centers.synth_center; | |
186 | ||
187 | if (freq < 4800) { | |
188 | u32 txctl; | |
189 | ||
190 | if (((freq - 2192) % 5) == 0) { | |
191 | channelSel = ((freq - 672) * 2 - 3040) / 10; | |
192 | bModeSynth = 0; | |
193 | } else if (((freq - 2224) % 5) == 0) { | |
194 | channelSel = ((freq - 704) * 2 - 3040) / 10; | |
195 | bModeSynth = 1; | |
196 | } else { | |
3800276a | 197 | ath_err(common, "Invalid channel %u MHz\n", freq); |
e16393bb LR |
198 | return -EINVAL; |
199 | } | |
200 | ||
201 | channelSel = (channelSel << 2) & 0xff; | |
202 | channelSel = ath9k_hw_reverse_bits(channelSel, 8); | |
203 | ||
204 | txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL); | |
205 | if (freq == 2484) { | |
206 | ||
207 | REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, | |
208 | txctl | AR_PHY_CCK_TX_CTRL_JAPAN); | |
209 | } else { | |
210 | REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, | |
211 | txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN); | |
212 | } | |
213 | ||
214 | } else if ((freq % 20) == 0 && freq >= 5120) { | |
215 | channelSel = | |
216 | ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8); | |
217 | aModeRefSel = ath9k_hw_reverse_bits(1, 2); | |
218 | } else if ((freq % 10) == 0) { | |
219 | channelSel = | |
220 | ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8); | |
221 | if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) | |
222 | aModeRefSel = ath9k_hw_reverse_bits(2, 2); | |
223 | else | |
224 | aModeRefSel = ath9k_hw_reverse_bits(1, 2); | |
225 | } else if ((freq % 5) == 0) { | |
226 | channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8); | |
227 | aModeRefSel = ath9k_hw_reverse_bits(1, 2); | |
228 | } else { | |
3800276a | 229 | ath_err(common, "Invalid channel %u MHz\n", freq); |
e16393bb LR |
230 | return -EINVAL; |
231 | } | |
232 | ||
8fe65368 | 233 | ar5008_hw_force_bias(ah, freq); |
a7765828 | 234 | |
e16393bb LR |
235 | reg32 = |
236 | (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) | | |
237 | (1 << 5) | 0x1; | |
238 | ||
239 | REG_WRITE(ah, AR_PHY(0x37), reg32); | |
240 | ||
241 | ah->curchan = chan; | |
e16393bb LR |
242 | |
243 | return 0; | |
244 | } | |
245 | ||
246 | /** | |
8fe65368 | 247 | * ar5008_hw_spur_mitigate - convert baseband spur frequency for external radios |
e16393bb LR |
248 | * @ah: atheros hardware structure |
249 | * @chan: | |
250 | * | |
251 | * For non single-chip solutions. Converts to baseband spur frequency given the | |
252 | * input channel frequency and compute register settings below. | |
253 | */ | |
8fe65368 LR |
254 | static void ar5008_hw_spur_mitigate(struct ath_hw *ah, |
255 | struct ath9k_channel *chan) | |
e16393bb LR |
256 | { |
257 | int bb_spur = AR_NO_SPUR; | |
258 | int bin, cur_bin; | |
259 | int spur_freq_sd; | |
260 | int spur_delta_phase; | |
261 | int denominator; | |
262 | int upper, lower, cur_vit_mask; | |
263 | int tmp, new; | |
264 | int i; | |
07b2fa5a JP |
265 | static int pilot_mask_reg[4] = { |
266 | AR_PHY_TIMING7, AR_PHY_TIMING8, | |
267 | AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 | |
e16393bb | 268 | }; |
07b2fa5a JP |
269 | static int chan_mask_reg[4] = { |
270 | AR_PHY_TIMING9, AR_PHY_TIMING10, | |
271 | AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 | |
e16393bb | 272 | }; |
07b2fa5a | 273 | static int inc[4] = { 0, 100, 0, 0 }; |
e16393bb LR |
274 | |
275 | int8_t mask_m[123]; | |
276 | int8_t mask_p[123]; | |
277 | int8_t mask_amt; | |
278 | int tmp_mask; | |
279 | int cur_bb_spur; | |
280 | bool is2GHz = IS_CHAN_2GHZ(chan); | |
281 | ||
282 | memset(&mask_m, 0, sizeof(int8_t) * 123); | |
283 | memset(&mask_p, 0, sizeof(int8_t) * 123); | |
284 | ||
285 | for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { | |
286 | cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz); | |
287 | if (AR_NO_SPUR == cur_bb_spur) | |
288 | break; | |
289 | cur_bb_spur = cur_bb_spur - (chan->channel * 10); | |
290 | if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) { | |
291 | bb_spur = cur_bb_spur; | |
292 | break; | |
293 | } | |
294 | } | |
295 | ||
296 | if (AR_NO_SPUR == bb_spur) | |
297 | return; | |
298 | ||
299 | bin = bb_spur * 32; | |
300 | ||
301 | tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); | |
302 | new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | | |
303 | AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | | |
304 | AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | | |
305 | AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); | |
306 | ||
307 | REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new); | |
308 | ||
309 | new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | | |
310 | AR_PHY_SPUR_REG_ENABLE_MASK_PPM | | |
311 | AR_PHY_SPUR_REG_MASK_RATE_SELECT | | |
312 | AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | | |
313 | SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); | |
314 | REG_WRITE(ah, AR_PHY_SPUR_REG, new); | |
315 | ||
316 | spur_delta_phase = ((bb_spur * 524288) / 100) & | |
317 | AR_PHY_TIMING11_SPUR_DELTA_PHASE; | |
318 | ||
319 | denominator = IS_CHAN_2GHZ(chan) ? 440 : 400; | |
320 | spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff; | |
321 | ||
322 | new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | | |
323 | SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | | |
324 | SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); | |
325 | REG_WRITE(ah, AR_PHY_TIMING11, new); | |
326 | ||
327 | cur_bin = -6000; | |
328 | upper = bin + 100; | |
329 | lower = bin - 100; | |
330 | ||
331 | for (i = 0; i < 4; i++) { | |
332 | int pilot_mask = 0; | |
333 | int chan_mask = 0; | |
334 | int bp = 0; | |
335 | for (bp = 0; bp < 30; bp++) { | |
336 | if ((cur_bin > lower) && (cur_bin < upper)) { | |
337 | pilot_mask = pilot_mask | 0x1 << bp; | |
338 | chan_mask = chan_mask | 0x1 << bp; | |
339 | } | |
340 | cur_bin += 100; | |
341 | } | |
342 | cur_bin += inc[i]; | |
343 | REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); | |
344 | REG_WRITE(ah, chan_mask_reg[i], chan_mask); | |
345 | } | |
346 | ||
347 | cur_vit_mask = 6100; | |
348 | upper = bin + 120; | |
349 | lower = bin - 120; | |
350 | ||
351 | for (i = 0; i < 123; i++) { | |
352 | if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { | |
353 | ||
354 | /* workaround for gcc bug #37014 */ | |
355 | volatile int tmp_v = abs(cur_vit_mask - bin); | |
356 | ||
357 | if (tmp_v < 75) | |
358 | mask_amt = 1; | |
359 | else | |
360 | mask_amt = 0; | |
361 | if (cur_vit_mask < 0) | |
362 | mask_m[abs(cur_vit_mask / 100)] = mask_amt; | |
363 | else | |
364 | mask_p[cur_vit_mask / 100] = mask_amt; | |
365 | } | |
366 | cur_vit_mask -= 100; | |
367 | } | |
368 | ||
369 | tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) | |
370 | | (mask_m[48] << 26) | (mask_m[49] << 24) | |
371 | | (mask_m[50] << 22) | (mask_m[51] << 20) | |
372 | | (mask_m[52] << 18) | (mask_m[53] << 16) | |
373 | | (mask_m[54] << 14) | (mask_m[55] << 12) | |
374 | | (mask_m[56] << 10) | (mask_m[57] << 8) | |
375 | | (mask_m[58] << 6) | (mask_m[59] << 4) | |
376 | | (mask_m[60] << 2) | (mask_m[61] << 0); | |
377 | REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); | |
378 | REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); | |
379 | ||
380 | tmp_mask = (mask_m[31] << 28) | |
381 | | (mask_m[32] << 26) | (mask_m[33] << 24) | |
382 | | (mask_m[34] << 22) | (mask_m[35] << 20) | |
383 | | (mask_m[36] << 18) | (mask_m[37] << 16) | |
384 | | (mask_m[48] << 14) | (mask_m[39] << 12) | |
385 | | (mask_m[40] << 10) | (mask_m[41] << 8) | |
386 | | (mask_m[42] << 6) | (mask_m[43] << 4) | |
387 | | (mask_m[44] << 2) | (mask_m[45] << 0); | |
388 | REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); | |
389 | REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); | |
390 | ||
391 | tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) | |
392 | | (mask_m[18] << 26) | (mask_m[18] << 24) | |
393 | | (mask_m[20] << 22) | (mask_m[20] << 20) | |
394 | | (mask_m[22] << 18) | (mask_m[22] << 16) | |
395 | | (mask_m[24] << 14) | (mask_m[24] << 12) | |
396 | | (mask_m[25] << 10) | (mask_m[26] << 8) | |
397 | | (mask_m[27] << 6) | (mask_m[28] << 4) | |
398 | | (mask_m[29] << 2) | (mask_m[30] << 0); | |
399 | REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); | |
400 | REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); | |
401 | ||
402 | tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28) | |
403 | | (mask_m[2] << 26) | (mask_m[3] << 24) | |
404 | | (mask_m[4] << 22) | (mask_m[5] << 20) | |
405 | | (mask_m[6] << 18) | (mask_m[7] << 16) | |
406 | | (mask_m[8] << 14) | (mask_m[9] << 12) | |
407 | | (mask_m[10] << 10) | (mask_m[11] << 8) | |
408 | | (mask_m[12] << 6) | (mask_m[13] << 4) | |
409 | | (mask_m[14] << 2) | (mask_m[15] << 0); | |
410 | REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); | |
411 | REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); | |
412 | ||
413 | tmp_mask = (mask_p[15] << 28) | |
414 | | (mask_p[14] << 26) | (mask_p[13] << 24) | |
415 | | (mask_p[12] << 22) | (mask_p[11] << 20) | |
416 | | (mask_p[10] << 18) | (mask_p[9] << 16) | |
417 | | (mask_p[8] << 14) | (mask_p[7] << 12) | |
418 | | (mask_p[6] << 10) | (mask_p[5] << 8) | |
419 | | (mask_p[4] << 6) | (mask_p[3] << 4) | |
420 | | (mask_p[2] << 2) | (mask_p[1] << 0); | |
421 | REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); | |
422 | REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); | |
423 | ||
424 | tmp_mask = (mask_p[30] << 28) | |
425 | | (mask_p[29] << 26) | (mask_p[28] << 24) | |
426 | | (mask_p[27] << 22) | (mask_p[26] << 20) | |
427 | | (mask_p[25] << 18) | (mask_p[24] << 16) | |
428 | | (mask_p[23] << 14) | (mask_p[22] << 12) | |
429 | | (mask_p[21] << 10) | (mask_p[20] << 8) | |
430 | | (mask_p[19] << 6) | (mask_p[18] << 4) | |
431 | | (mask_p[17] << 2) | (mask_p[16] << 0); | |
432 | REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); | |
433 | REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); | |
434 | ||
435 | tmp_mask = (mask_p[45] << 28) | |
436 | | (mask_p[44] << 26) | (mask_p[43] << 24) | |
437 | | (mask_p[42] << 22) | (mask_p[41] << 20) | |
438 | | (mask_p[40] << 18) | (mask_p[39] << 16) | |
439 | | (mask_p[38] << 14) | (mask_p[37] << 12) | |
440 | | (mask_p[36] << 10) | (mask_p[35] << 8) | |
441 | | (mask_p[34] << 6) | (mask_p[33] << 4) | |
442 | | (mask_p[32] << 2) | (mask_p[31] << 0); | |
443 | REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); | |
444 | REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); | |
445 | ||
446 | tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) | |
447 | | (mask_p[59] << 26) | (mask_p[58] << 24) | |
448 | | (mask_p[57] << 22) | (mask_p[56] << 20) | |
449 | | (mask_p[55] << 18) | (mask_p[54] << 16) | |
450 | | (mask_p[53] << 14) | (mask_p[52] << 12) | |
451 | | (mask_p[51] << 10) | (mask_p[50] << 8) | |
452 | | (mask_p[49] << 6) | (mask_p[48] << 4) | |
453 | | (mask_p[47] << 2) | (mask_p[46] << 0); | |
454 | REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); | |
455 | REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); | |
456 | } | |
457 | ||
458 | /** | |
8fe65368 | 459 | * ar5008_hw_rf_alloc_ext_banks - allocates banks for external radio programming |
e16393bb LR |
460 | * @ah: atheros hardware structure |
461 | * | |
462 | * Only required for older devices with external AR2133/AR5133 radios. | |
463 | */ | |
8fe65368 | 464 | static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah) |
e16393bb | 465 | { |
a043dfb9 | 466 | int size = ah->iniBank6.ia_rows * sizeof(u32); |
e16393bb | 467 | |
c1b976d2 FF |
468 | if (AR_SREV_9280_20_OR_LATER(ah)) |
469 | return 0; | |
e16393bb | 470 | |
a043dfb9 FF |
471 | ah->analogBank6Data = devm_kzalloc(ah->dev, size, GFP_KERNEL); |
472 | if (!ah->analogBank6Data) | |
473 | return -ENOMEM; | |
e16393bb LR |
474 | |
475 | return 0; | |
e16393bb LR |
476 | } |
477 | ||
478 | ||
131d1d03 | 479 | /* * |
8fe65368 | 480 | * ar5008_hw_set_rf_regs - programs rf registers based on EEPROM |
131d1d03 LR |
481 | * @ah: atheros hardware structure |
482 | * @chan: | |
483 | * @modesIndex: | |
484 | * | |
485 | * Used for the external AR2133/AR5133 radios. | |
486 | * | |
487 | * Reads the EEPROM header info from the device structure and programs | |
488 | * all rf registers. This routine requires access to the analog | |
489 | * rf device. This is not required for single-chip devices. | |
490 | */ | |
8fe65368 LR |
491 | static bool ar5008_hw_set_rf_regs(struct ath_hw *ah, |
492 | struct ath9k_channel *chan, | |
493 | u16 modesIndex) | |
f078f209 | 494 | { |
f078f209 LR |
495 | u32 eepMinorRev; |
496 | u32 ob5GHz = 0, db5GHz = 0; | |
497 | u32 ob2GHz = 0, db2GHz = 0; | |
498 | int regWrites = 0; | |
37c62fec | 499 | int i; |
f078f209 | 500 | |
131d1d03 LR |
501 | /* |
502 | * Software does not need to program bank data | |
503 | * for single chip devices, that is AR9280 or anything | |
504 | * after that. | |
505 | */ | |
7a37081e | 506 | if (AR_SREV_9280_20_OR_LATER(ah)) |
f078f209 LR |
507 | return true; |
508 | ||
131d1d03 | 509 | /* Setup rf parameters */ |
f74df6fb | 510 | eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV); |
f078f209 | 511 | |
37c62fec FF |
512 | for (i = 0; i < ah->iniBank6.ia_rows; i++) |
513 | ah->analogBank6Data[i] = INI_RA(&ah->iniBank6, i, modesIndex); | |
f078f209 | 514 | |
131d1d03 | 515 | /* Only the 5 or 2 GHz OB/DB need to be set for a mode */ |
f078f209 LR |
516 | if (eepMinorRev >= 2) { |
517 | if (IS_CHAN_2GHZ(chan)) { | |
f74df6fb S |
518 | ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2); |
519 | db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2); | |
8fe65368 LR |
520 | ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, |
521 | ob2GHz, 3, 197, 0); | |
522 | ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, | |
523 | db2GHz, 3, 194, 0); | |
f078f209 | 524 | } else { |
f74df6fb S |
525 | ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5); |
526 | db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5); | |
8fe65368 LR |
527 | ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, |
528 | ob5GHz, 3, 203, 0); | |
529 | ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, | |
530 | db5GHz, 3, 200, 0); | |
f078f209 LR |
531 | } |
532 | } | |
533 | ||
131d1d03 | 534 | /* Write Analog registers */ |
a043dfb9 FF |
535 | REG_WRITE_ARRAY(&bank0, 1, regWrites); |
536 | REG_WRITE_ARRAY(&bank1, 1, regWrites); | |
537 | REG_WRITE_ARRAY(&bank2, 1, regWrites); | |
538 | REG_WRITE_ARRAY(&bank3, modesIndex, regWrites); | |
539 | ar5008_write_bank6(ah, ®Writes); | |
540 | REG_WRITE_ARRAY(&bank7, 1, regWrites); | |
f078f209 LR |
541 | |
542 | return true; | |
543 | } | |
8fe65368 LR |
544 | |
545 | static void ar5008_hw_init_bb(struct ath_hw *ah, | |
546 | struct ath9k_channel *chan) | |
547 | { | |
548 | u32 synthDelay; | |
549 | ||
550 | synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; | |
7d865c70 | 551 | |
8fe65368 LR |
552 | REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); |
553 | ||
7c5adc8d | 554 | ath9k_hw_synth_delay(ah, chan, synthDelay); |
8fe65368 LR |
555 | } |
556 | ||
557 | static void ar5008_hw_init_chain_masks(struct ath_hw *ah) | |
558 | { | |
559 | int rx_chainmask, tx_chainmask; | |
560 | ||
561 | rx_chainmask = ah->rxchainmask; | |
562 | tx_chainmask = ah->txchainmask; | |
563 | ||
7d0d0df0 | 564 | |
8fe65368 LR |
565 | switch (rx_chainmask) { |
566 | case 0x5: | |
567 | REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, | |
568 | AR_PHY_SWAP_ALT_CHAIN); | |
569 | case 0x3: | |
570 | if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) { | |
571 | REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7); | |
572 | REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7); | |
573 | break; | |
574 | } | |
575 | case 0x1: | |
576 | case 0x2: | |
577 | case 0x7: | |
435c1610 | 578 | ENABLE_REGWRITE_BUFFER(ah); |
8fe65368 LR |
579 | REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); |
580 | REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); | |
581 | break; | |
582 | default: | |
435c1610 | 583 | ENABLE_REGWRITE_BUFFER(ah); |
8fe65368 LR |
584 | break; |
585 | } | |
586 | ||
587 | REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask); | |
7d0d0df0 S |
588 | |
589 | REGWRITE_BUFFER_FLUSH(ah); | |
7d0d0df0 | 590 | |
8fe65368 LR |
591 | if (tx_chainmask == 0x5) { |
592 | REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, | |
593 | AR_PHY_SWAP_ALT_CHAIN); | |
594 | } | |
595 | if (AR_SREV_9100(ah)) | |
596 | REG_WRITE(ah, AR_PHY_ANALOG_SWAP, | |
597 | REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001); | |
598 | } | |
599 | ||
600 | static void ar5008_hw_override_ini(struct ath_hw *ah, | |
601 | struct ath9k_channel *chan) | |
602 | { | |
603 | u32 val; | |
604 | ||
605 | /* | |
606 | * Set the RX_ABORT and RX_DIS and clear if off only after | |
607 | * RXE is set for MAC. This prevents frames with corrupted | |
608 | * descriptor status. | |
609 | */ | |
610 | REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); | |
611 | ||
7a37081e | 612 | if (AR_SREV_9280_20_OR_LATER(ah)) { |
64b6f46f SM |
613 | /* |
614 | * For AR9280 and above, there is a new feature that allows | |
615 | * Multicast search based on both MAC Address and Key ID. | |
616 | * By default, this feature is enabled. But since the driver | |
617 | * is not using this feature, we switch it off; otherwise | |
618 | * multicast search based on MAC addr only will fail. | |
619 | */ | |
620 | val = REG_READ(ah, AR_PCU_MISC_MODE2) & | |
621 | (~AR_ADHOC_MCAST_KEYID_ENABLE); | |
8fe65368 LR |
622 | |
623 | if (!AR_SREV_9271(ah)) | |
624 | val &= ~AR_PCU_MISC_MODE2_HWWAR1; | |
625 | ||
a42acef0 | 626 | if (AR_SREV_9287_11_OR_LATER(ah)) |
8fe65368 LR |
627 | val = val & (~AR_PCU_MISC_MODE2_HWWAR2); |
628 | ||
9ef48932 SM |
629 | val |= AR_PCU_MISC_MODE2_CFP_IGNORE; |
630 | ||
8fe65368 LR |
631 | REG_WRITE(ah, AR_PCU_MISC_MODE2, val); |
632 | } | |
633 | ||
1b8714f7 | 634 | if (AR_SREV_9280_20_OR_LATER(ah)) |
8fe65368 LR |
635 | return; |
636 | /* | |
637 | * Disable BB clock gating | |
638 | * Necessary to avoid issues on AR5416 2.0 | |
639 | */ | |
640 | REG_WRITE(ah, 0x9800 + (651 << 2), 0x11); | |
641 | ||
642 | /* | |
643 | * Disable RIFS search on some chips to avoid baseband | |
644 | * hang issues. | |
645 | */ | |
646 | if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) { | |
647 | val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS); | |
648 | val &= ~AR_PHY_RIFS_INIT_DELAY; | |
649 | REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val); | |
650 | } | |
651 | } | |
652 | ||
653 | static void ar5008_hw_set_channel_regs(struct ath_hw *ah, | |
654 | struct ath9k_channel *chan) | |
655 | { | |
656 | u32 phymode; | |
657 | u32 enableDacFifo = 0; | |
658 | ||
e17f83ea | 659 | if (AR_SREV_9285_12_OR_LATER(ah)) |
8fe65368 LR |
660 | enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) & |
661 | AR_PHY_FC_ENABLE_DAC_FIFO); | |
662 | ||
663 | phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40 | |
664 | | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo; | |
665 | ||
666 | if (IS_CHAN_HT40(chan)) { | |
667 | phymode |= AR_PHY_FC_DYN2040_EN; | |
668 | ||
8896934c | 669 | if (IS_CHAN_HT40PLUS(chan)) |
8fe65368 LR |
670 | phymode |= AR_PHY_FC_DYN2040_PRI_CH; |
671 | ||
672 | } | |
673 | REG_WRITE(ah, AR_PHY_TURBO, phymode); | |
674 | ||
675 | ath9k_hw_set11nmac2040(ah); | |
676 | ||
7d0d0df0 S |
677 | ENABLE_REGWRITE_BUFFER(ah); |
678 | ||
8fe65368 LR |
679 | REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S); |
680 | REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); | |
7d0d0df0 S |
681 | |
682 | REGWRITE_BUFFER_FLUSH(ah); | |
8fe65368 LR |
683 | } |
684 | ||
685 | ||
686 | static int ar5008_hw_process_ini(struct ath_hw *ah, | |
687 | struct ath9k_channel *chan) | |
688 | { | |
e7fc6338 | 689 | struct ath_common *common = ath9k_hw_common(ah); |
8fe65368 | 690 | int i, regWrites = 0; |
8fe65368 LR |
691 | u32 modesIndex, freqIndex; |
692 | ||
8896934c | 693 | if (IS_CHAN_5GHZ(chan)) { |
8fe65368 | 694 | freqIndex = 1; |
8896934c FF |
695 | modesIndex = IS_CHAN_HT40(chan) ? 2 : 1; |
696 | } else { | |
8fe65368 | 697 | freqIndex = 2; |
8896934c | 698 | modesIndex = IS_CHAN_HT40(chan) ? 3 : 4; |
8fe65368 LR |
699 | } |
700 | ||
8fe65368 LR |
701 | /* |
702 | * Set correct baseband to analog shift setting to | |
703 | * access analog chips. | |
704 | */ | |
705 | REG_WRITE(ah, AR_PHY(0), 0x00000007); | |
706 | ||
707 | /* Write ADDAC shifts */ | |
708 | REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); | |
d7084da0 FF |
709 | if (ah->eep_ops->set_addac) |
710 | ah->eep_ops->set_addac(ah, chan); | |
8fe65368 | 711 | |
9bbb8168 | 712 | REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites); |
8fe65368 LR |
713 | REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); |
714 | ||
7d0d0df0 S |
715 | ENABLE_REGWRITE_BUFFER(ah); |
716 | ||
8fe65368 LR |
717 | for (i = 0; i < ah->iniModes.ia_rows; i++) { |
718 | u32 reg = INI_RA(&ah->iniModes, i, 0); | |
719 | u32 val = INI_RA(&ah->iniModes, i, modesIndex); | |
720 | ||
721 | if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup) | |
722 | val &= ~AR_AN_TOP2_PWDCLKIND; | |
723 | ||
724 | REG_WRITE(ah, reg, val); | |
725 | ||
726 | if (reg >= 0x7800 && reg < 0x78a0 | |
e7fc6338 RM |
727 | && ah->config.analog_shiftreg |
728 | && (common->bus_ops->ath_bus_type != ATH_USB)) { | |
8fe65368 LR |
729 | udelay(100); |
730 | } | |
731 | ||
732 | DO_DELAY(regWrites); | |
733 | } | |
734 | ||
7d0d0df0 | 735 | REGWRITE_BUFFER_FLUSH(ah); |
7d0d0df0 | 736 | |
a42acef0 | 737 | if (AR_SREV_9280(ah) || AR_SREV_9287_11_OR_LATER(ah)) |
8fe65368 LR |
738 | REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites); |
739 | ||
740 | if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) || | |
a42acef0 | 741 | AR_SREV_9287_11_OR_LATER(ah)) |
8fe65368 LR |
742 | REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites); |
743 | ||
c7effd35 FF |
744 | if (AR_SREV_9271_10(ah)) { |
745 | REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENA); | |
746 | REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_ADC_ON, 0xa); | |
747 | } | |
8fe65368 | 748 | |
7d0d0df0 S |
749 | ENABLE_REGWRITE_BUFFER(ah); |
750 | ||
8fe65368 LR |
751 | /* Write common array parameters */ |
752 | for (i = 0; i < ah->iniCommon.ia_rows; i++) { | |
753 | u32 reg = INI_RA(&ah->iniCommon, i, 0); | |
754 | u32 val = INI_RA(&ah->iniCommon, i, 1); | |
755 | ||
756 | REG_WRITE(ah, reg, val); | |
757 | ||
758 | if (reg >= 0x7800 && reg < 0x78a0 | |
e7fc6338 RM |
759 | && ah->config.analog_shiftreg |
760 | && (common->bus_ops->ath_bus_type != ATH_USB)) { | |
8fe65368 LR |
761 | udelay(100); |
762 | } | |
763 | ||
764 | DO_DELAY(regWrites); | |
765 | } | |
766 | ||
7d0d0df0 | 767 | REGWRITE_BUFFER_FLUSH(ah); |
7d0d0df0 | 768 | |
8fe65368 LR |
769 | REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites); |
770 | ||
c7d36f9f FF |
771 | if (IS_CHAN_A_FAST_CLOCK(ah, chan)) |
772 | REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, | |
8fe65368 | 773 | regWrites); |
8fe65368 LR |
774 | |
775 | ar5008_hw_override_ini(ah, chan); | |
776 | ar5008_hw_set_channel_regs(ah, chan); | |
777 | ar5008_hw_init_chain_masks(ah); | |
778 | ath9k_olc_init(ah); | |
64ea57d0 | 779 | ath9k_hw_apply_txpower(ah, chan, false); |
8fe65368 LR |
780 | |
781 | /* Write analog registers */ | |
782 | if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) { | |
3800276a | 783 | ath_err(ath9k_hw_common(ah), "ar5416SetRfRegs failed\n"); |
8fe65368 LR |
784 | return -EIO; |
785 | } | |
786 | ||
787 | return 0; | |
788 | } | |
789 | ||
790 | static void ar5008_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan) | |
791 | { | |
792 | u32 rfMode = 0; | |
793 | ||
794 | if (chan == NULL) | |
795 | return; | |
796 | ||
1a5e6326 FF |
797 | if (IS_CHAN_2GHZ(chan)) |
798 | rfMode |= AR_PHY_MODE_DYNAMIC; | |
799 | else | |
800 | rfMode |= AR_PHY_MODE_OFDM; | |
8fe65368 | 801 | |
7a37081e | 802 | if (!AR_SREV_9280_20_OR_LATER(ah)) |
8fe65368 LR |
803 | rfMode |= (IS_CHAN_5GHZ(chan)) ? |
804 | AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ; | |
805 | ||
6b42e8d0 | 806 | if (IS_CHAN_A_FAST_CLOCK(ah, chan)) |
8fe65368 LR |
807 | rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE); |
808 | ||
809 | REG_WRITE(ah, AR_PHY_MODE, rfMode); | |
810 | } | |
811 | ||
812 | static void ar5008_hw_mark_phy_inactive(struct ath_hw *ah) | |
813 | { | |
814 | REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); | |
815 | } | |
816 | ||
817 | static void ar5008_hw_set_delta_slope(struct ath_hw *ah, | |
818 | struct ath9k_channel *chan) | |
819 | { | |
820 | u32 coef_scaled, ds_coef_exp, ds_coef_man; | |
821 | u32 clockMhzScaled = 0x64000000; | |
822 | struct chan_centers centers; | |
823 | ||
824 | if (IS_CHAN_HALF_RATE(chan)) | |
825 | clockMhzScaled = clockMhzScaled >> 1; | |
826 | else if (IS_CHAN_QUARTER_RATE(chan)) | |
827 | clockMhzScaled = clockMhzScaled >> 2; | |
828 | ||
829 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); | |
830 | coef_scaled = clockMhzScaled / centers.synth_center; | |
831 | ||
832 | ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, | |
833 | &ds_coef_exp); | |
834 | ||
835 | REG_RMW_FIELD(ah, AR_PHY_TIMING3, | |
836 | AR_PHY_TIMING3_DSC_MAN, ds_coef_man); | |
837 | REG_RMW_FIELD(ah, AR_PHY_TIMING3, | |
838 | AR_PHY_TIMING3_DSC_EXP, ds_coef_exp); | |
839 | ||
840 | coef_scaled = (9 * coef_scaled) / 10; | |
841 | ||
842 | ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, | |
843 | &ds_coef_exp); | |
844 | ||
845 | REG_RMW_FIELD(ah, AR_PHY_HALFGI, | |
846 | AR_PHY_HALFGI_DSC_MAN, ds_coef_man); | |
847 | REG_RMW_FIELD(ah, AR_PHY_HALFGI, | |
848 | AR_PHY_HALFGI_DSC_EXP, ds_coef_exp); | |
849 | } | |
850 | ||
851 | static bool ar5008_hw_rfbus_req(struct ath_hw *ah) | |
852 | { | |
853 | REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); | |
854 | return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN, | |
855 | AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT); | |
856 | } | |
857 | ||
858 | static void ar5008_hw_rfbus_done(struct ath_hw *ah) | |
859 | { | |
860 | u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; | |
8fe65368 | 861 | |
7c5adc8d | 862 | ath9k_hw_synth_delay(ah, ah->curchan, synthDelay); |
8fe65368 LR |
863 | |
864 | REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); | |
865 | } | |
866 | ||
8fe65368 LR |
867 | static void ar5008_restore_chainmask(struct ath_hw *ah) |
868 | { | |
869 | int rx_chainmask = ah->rxchainmask; | |
870 | ||
871 | if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) { | |
872 | REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); | |
873 | REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); | |
874 | } | |
875 | } | |
876 | ||
64773964 LR |
877 | static u32 ar9160_hw_compute_pll_control(struct ath_hw *ah, |
878 | struct ath9k_channel *chan) | |
879 | { | |
880 | u32 pll; | |
881 | ||
882 | pll = SM(0x5, AR_RTC_9160_PLL_REFDIV); | |
883 | ||
884 | if (chan && IS_CHAN_HALF_RATE(chan)) | |
885 | pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); | |
886 | else if (chan && IS_CHAN_QUARTER_RATE(chan)) | |
887 | pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); | |
888 | ||
889 | if (chan && IS_CHAN_5GHZ(chan)) | |
890 | pll |= SM(0x50, AR_RTC_9160_PLL_DIV); | |
891 | else | |
892 | pll |= SM(0x58, AR_RTC_9160_PLL_DIV); | |
893 | ||
894 | return pll; | |
895 | } | |
896 | ||
897 | static u32 ar5008_hw_compute_pll_control(struct ath_hw *ah, | |
898 | struct ath9k_channel *chan) | |
899 | { | |
900 | u32 pll; | |
901 | ||
902 | pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2; | |
903 | ||
904 | if (chan && IS_CHAN_HALF_RATE(chan)) | |
905 | pll |= SM(0x1, AR_RTC_PLL_CLKSEL); | |
906 | else if (chan && IS_CHAN_QUARTER_RATE(chan)) | |
907 | pll |= SM(0x2, AR_RTC_PLL_CLKSEL); | |
908 | ||
909 | if (chan && IS_CHAN_5GHZ(chan)) | |
910 | pll |= SM(0xa, AR_RTC_PLL_DIV); | |
911 | else | |
912 | pll |= SM(0xb, AR_RTC_PLL_DIV); | |
913 | ||
914 | return pll; | |
915 | } | |
916 | ||
e36b27af LR |
917 | static bool ar5008_hw_ani_control_new(struct ath_hw *ah, |
918 | enum ath9k_ani_cmd cmd, | |
919 | int param) | |
920 | { | |
e36b27af LR |
921 | struct ath_common *common = ath9k_hw_common(ah); |
922 | struct ath9k_channel *chan = ah->curchan; | |
c24bd362 | 923 | struct ar5416AniState *aniState = &ah->ani; |
e36b27af LR |
924 | s32 value, value2; |
925 | ||
926 | switch (cmd & ah->ani_function) { | |
927 | case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{ | |
928 | /* | |
929 | * on == 1 means ofdm weak signal detection is ON | |
930 | * on == 1 is the default, for less noise immunity | |
931 | * | |
932 | * on == 0 means ofdm weak signal detection is OFF | |
933 | * on == 0 means more noise imm | |
934 | */ | |
935 | u32 on = param ? 1 : 0; | |
936 | /* | |
937 | * make register setting for default | |
938 | * (weak sig detect ON) come from INI file | |
939 | */ | |
940 | int m1ThreshLow = on ? | |
941 | aniState->iniDef.m1ThreshLow : m1ThreshLow_off; | |
942 | int m2ThreshLow = on ? | |
943 | aniState->iniDef.m2ThreshLow : m2ThreshLow_off; | |
944 | int m1Thresh = on ? | |
945 | aniState->iniDef.m1Thresh : m1Thresh_off; | |
946 | int m2Thresh = on ? | |
947 | aniState->iniDef.m2Thresh : m2Thresh_off; | |
948 | int m2CountThr = on ? | |
949 | aniState->iniDef.m2CountThr : m2CountThr_off; | |
950 | int m2CountThrLow = on ? | |
951 | aniState->iniDef.m2CountThrLow : m2CountThrLow_off; | |
952 | int m1ThreshLowExt = on ? | |
953 | aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off; | |
954 | int m2ThreshLowExt = on ? | |
955 | aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off; | |
956 | int m1ThreshExt = on ? | |
957 | aniState->iniDef.m1ThreshExt : m1ThreshExt_off; | |
958 | int m2ThreshExt = on ? | |
959 | aniState->iniDef.m2ThreshExt : m2ThreshExt_off; | |
960 | ||
961 | REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, | |
962 | AR_PHY_SFCORR_LOW_M1_THRESH_LOW, | |
963 | m1ThreshLow); | |
964 | REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, | |
965 | AR_PHY_SFCORR_LOW_M2_THRESH_LOW, | |
966 | m2ThreshLow); | |
967 | REG_RMW_FIELD(ah, AR_PHY_SFCORR, | |
968 | AR_PHY_SFCORR_M1_THRESH, m1Thresh); | |
969 | REG_RMW_FIELD(ah, AR_PHY_SFCORR, | |
970 | AR_PHY_SFCORR_M2_THRESH, m2Thresh); | |
971 | REG_RMW_FIELD(ah, AR_PHY_SFCORR, | |
972 | AR_PHY_SFCORR_M2COUNT_THR, m2CountThr); | |
973 | REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, | |
974 | AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, | |
975 | m2CountThrLow); | |
976 | ||
977 | REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, | |
978 | AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt); | |
979 | REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, | |
980 | AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt); | |
981 | REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, | |
982 | AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt); | |
983 | REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, | |
984 | AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt); | |
985 | ||
986 | if (on) | |
987 | REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, | |
988 | AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); | |
989 | else | |
990 | REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, | |
991 | AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); | |
992 | ||
7067e701 | 993 | if (on != aniState->ofdmWeakSigDetect) { |
d2182b69 | 994 | ath_dbg(common, ANI, |
226afe68 JP |
995 | "** ch %d: ofdm weak signal: %s=>%s\n", |
996 | chan->channel, | |
7067e701 | 997 | aniState->ofdmWeakSigDetect ? |
226afe68 JP |
998 | "on" : "off", |
999 | on ? "on" : "off"); | |
e36b27af LR |
1000 | if (on) |
1001 | ah->stats.ast_ani_ofdmon++; | |
1002 | else | |
1003 | ah->stats.ast_ani_ofdmoff++; | |
7067e701 | 1004 | aniState->ofdmWeakSigDetect = on; |
e36b27af LR |
1005 | } |
1006 | break; | |
1007 | } | |
1008 | case ATH9K_ANI_FIRSTEP_LEVEL:{ | |
1009 | u32 level = param; | |
1010 | ||
1011 | if (level >= ARRAY_SIZE(firstep_table)) { | |
d2182b69 | 1012 | ath_dbg(common, ANI, |
226afe68 JP |
1013 | "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n", |
1014 | level, ARRAY_SIZE(firstep_table)); | |
e36b27af LR |
1015 | return false; |
1016 | } | |
1017 | ||
1018 | /* | |
1019 | * make register setting relative to default | |
1020 | * from INI file & cap value | |
1021 | */ | |
1022 | value = firstep_table[level] - | |
465dce62 | 1023 | firstep_table[ATH9K_ANI_FIRSTEP_LVL] + |
e36b27af LR |
1024 | aniState->iniDef.firstep; |
1025 | if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN) | |
1026 | value = ATH9K_SIG_FIRSTEP_SETTING_MIN; | |
1027 | if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX) | |
1028 | value = ATH9K_SIG_FIRSTEP_SETTING_MAX; | |
1029 | REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, | |
1030 | AR_PHY_FIND_SIG_FIRSTEP, | |
1031 | value); | |
1032 | /* | |
1033 | * we need to set first step low register too | |
1034 | * make register setting relative to default | |
1035 | * from INI file & cap value | |
1036 | */ | |
1037 | value2 = firstep_table[level] - | |
465dce62 | 1038 | firstep_table[ATH9K_ANI_FIRSTEP_LVL] + |
e36b27af LR |
1039 | aniState->iniDef.firstepLow; |
1040 | if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN) | |
1041 | value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN; | |
1042 | if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX) | |
1043 | value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX; | |
1044 | ||
1045 | REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW, | |
1046 | AR_PHY_FIND_SIG_FIRSTEP_LOW, value2); | |
1047 | ||
1048 | if (level != aniState->firstepLevel) { | |
d2182b69 | 1049 | ath_dbg(common, ANI, |
226afe68 JP |
1050 | "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n", |
1051 | chan->channel, | |
1052 | aniState->firstepLevel, | |
1053 | level, | |
465dce62 | 1054 | ATH9K_ANI_FIRSTEP_LVL, |
226afe68 JP |
1055 | value, |
1056 | aniState->iniDef.firstep); | |
d2182b69 | 1057 | ath_dbg(common, ANI, |
226afe68 JP |
1058 | "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n", |
1059 | chan->channel, | |
1060 | aniState->firstepLevel, | |
1061 | level, | |
465dce62 | 1062 | ATH9K_ANI_FIRSTEP_LVL, |
226afe68 JP |
1063 | value2, |
1064 | aniState->iniDef.firstepLow); | |
e36b27af LR |
1065 | if (level > aniState->firstepLevel) |
1066 | ah->stats.ast_ani_stepup++; | |
1067 | else if (level < aniState->firstepLevel) | |
1068 | ah->stats.ast_ani_stepdown++; | |
1069 | aniState->firstepLevel = level; | |
1070 | } | |
1071 | break; | |
1072 | } | |
1073 | case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{ | |
1074 | u32 level = param; | |
1075 | ||
1076 | if (level >= ARRAY_SIZE(cycpwrThr1_table)) { | |
d2182b69 | 1077 | ath_dbg(common, ANI, |
226afe68 JP |
1078 | "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n", |
1079 | level, ARRAY_SIZE(cycpwrThr1_table)); | |
e36b27af LR |
1080 | return false; |
1081 | } | |
1082 | /* | |
1083 | * make register setting relative to default | |
1084 | * from INI file & cap value | |
1085 | */ | |
1086 | value = cycpwrThr1_table[level] - | |
465dce62 | 1087 | cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] + |
e36b27af LR |
1088 | aniState->iniDef.cycpwrThr1; |
1089 | if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN) | |
1090 | value = ATH9K_SIG_SPUR_IMM_SETTING_MIN; | |
1091 | if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX) | |
1092 | value = ATH9K_SIG_SPUR_IMM_SETTING_MAX; | |
1093 | REG_RMW_FIELD(ah, AR_PHY_TIMING5, | |
1094 | AR_PHY_TIMING5_CYCPWR_THR1, | |
1095 | value); | |
1096 | ||
1097 | /* | |
1098 | * set AR_PHY_EXT_CCA for extension channel | |
1099 | * make register setting relative to default | |
1100 | * from INI file & cap value | |
1101 | */ | |
1102 | value2 = cycpwrThr1_table[level] - | |
465dce62 | 1103 | cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] + |
e36b27af LR |
1104 | aniState->iniDef.cycpwrThr1Ext; |
1105 | if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN) | |
1106 | value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN; | |
1107 | if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX) | |
1108 | value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX; | |
1109 | REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, | |
1110 | AR_PHY_EXT_TIMING5_CYCPWR_THR1, value2); | |
1111 | ||
1112 | if (level != aniState->spurImmunityLevel) { | |
d2182b69 | 1113 | ath_dbg(common, ANI, |
226afe68 JP |
1114 | "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n", |
1115 | chan->channel, | |
1116 | aniState->spurImmunityLevel, | |
1117 | level, | |
465dce62 | 1118 | ATH9K_ANI_SPUR_IMMUNE_LVL, |
226afe68 JP |
1119 | value, |
1120 | aniState->iniDef.cycpwrThr1); | |
d2182b69 | 1121 | ath_dbg(common, ANI, |
226afe68 JP |
1122 | "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n", |
1123 | chan->channel, | |
1124 | aniState->spurImmunityLevel, | |
1125 | level, | |
465dce62 | 1126 | ATH9K_ANI_SPUR_IMMUNE_LVL, |
226afe68 JP |
1127 | value2, |
1128 | aniState->iniDef.cycpwrThr1Ext); | |
e36b27af LR |
1129 | if (level > aniState->spurImmunityLevel) |
1130 | ah->stats.ast_ani_spurup++; | |
1131 | else if (level < aniState->spurImmunityLevel) | |
1132 | ah->stats.ast_ani_spurdown++; | |
1133 | aniState->spurImmunityLevel = level; | |
1134 | } | |
1135 | break; | |
1136 | } | |
1137 | case ATH9K_ANI_MRC_CCK: | |
1138 | /* | |
1139 | * You should not see this as AR5008, AR9001, AR9002 | |
1140 | * does not have hardware support for MRC CCK. | |
1141 | */ | |
1142 | WARN_ON(1); | |
1143 | break; | |
e36b27af | 1144 | default: |
d2182b69 | 1145 | ath_dbg(common, ANI, "invalid cmd %u\n", cmd); |
e36b27af LR |
1146 | return false; |
1147 | } | |
1148 | ||
d2182b69 | 1149 | ath_dbg(common, ANI, |
226afe68 JP |
1150 | "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n", |
1151 | aniState->spurImmunityLevel, | |
7067e701 | 1152 | aniState->ofdmWeakSigDetect ? "on" : "off", |
226afe68 | 1153 | aniState->firstepLevel, |
81b67fd6 | 1154 | aniState->mrcCCK ? "on" : "off", |
226afe68 JP |
1155 | aniState->listenTime, |
1156 | aniState->ofdmPhyErrCount, | |
1157 | aniState->cckPhyErrCount); | |
e36b27af LR |
1158 | return true; |
1159 | } | |
1160 | ||
641d9921 FF |
1161 | static void ar5008_hw_do_getnf(struct ath_hw *ah, |
1162 | int16_t nfarray[NUM_NF_READINGS]) | |
1163 | { | |
641d9921 FF |
1164 | int16_t nf; |
1165 | ||
1166 | nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR); | |
7919a57b | 1167 | nfarray[0] = sign_extend32(nf, 8); |
641d9921 FF |
1168 | |
1169 | nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR); | |
7919a57b | 1170 | nfarray[1] = sign_extend32(nf, 8); |
641d9921 FF |
1171 | |
1172 | nf = MS(REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR); | |
7919a57b | 1173 | nfarray[2] = sign_extend32(nf, 8); |
641d9921 | 1174 | |
866b7780 FF |
1175 | if (!IS_CHAN_HT40(ah->curchan)) |
1176 | return; | |
1177 | ||
641d9921 | 1178 | nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR); |
7919a57b | 1179 | nfarray[3] = sign_extend32(nf, 8); |
641d9921 FF |
1180 | |
1181 | nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR); | |
7919a57b | 1182 | nfarray[4] = sign_extend32(nf, 8); |
641d9921 FF |
1183 | |
1184 | nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR); | |
7919a57b | 1185 | nfarray[5] = sign_extend32(nf, 8); |
641d9921 FF |
1186 | } |
1187 | ||
e36b27af LR |
1188 | /* |
1189 | * Initialize the ANI register values with default (ini) values. | |
1190 | * This routine is called during a (full) hardware reset after | |
1191 | * all the registers are initialised from the INI. | |
1192 | */ | |
1193 | static void ar5008_hw_ani_cache_ini_regs(struct ath_hw *ah) | |
1194 | { | |
e36b27af LR |
1195 | struct ath_common *common = ath9k_hw_common(ah); |
1196 | struct ath9k_channel *chan = ah->curchan; | |
c24bd362 | 1197 | struct ar5416AniState *aniState = &ah->ani; |
e36b27af | 1198 | struct ath9k_ani_default *iniDef; |
e36b27af LR |
1199 | u32 val; |
1200 | ||
e36b27af LR |
1201 | iniDef = &aniState->iniDef; |
1202 | ||
8896934c | 1203 | ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz\n", |
226afe68 JP |
1204 | ah->hw_version.macVersion, |
1205 | ah->hw_version.macRev, | |
1206 | ah->opmode, | |
8896934c | 1207 | chan->channel); |
e36b27af LR |
1208 | |
1209 | val = REG_READ(ah, AR_PHY_SFCORR); | |
1210 | iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH); | |
1211 | iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH); | |
1212 | iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR); | |
1213 | ||
1214 | val = REG_READ(ah, AR_PHY_SFCORR_LOW); | |
1215 | iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW); | |
1216 | iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW); | |
1217 | iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW); | |
1218 | ||
1219 | val = REG_READ(ah, AR_PHY_SFCORR_EXT); | |
1220 | iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH); | |
1221 | iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH); | |
1222 | iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW); | |
1223 | iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW); | |
1224 | iniDef->firstep = REG_READ_FIELD(ah, | |
1225 | AR_PHY_FIND_SIG, | |
1226 | AR_PHY_FIND_SIG_FIRSTEP); | |
1227 | iniDef->firstepLow = REG_READ_FIELD(ah, | |
1228 | AR_PHY_FIND_SIG_LOW, | |
1229 | AR_PHY_FIND_SIG_FIRSTEP_LOW); | |
1230 | iniDef->cycpwrThr1 = REG_READ_FIELD(ah, | |
1231 | AR_PHY_TIMING5, | |
1232 | AR_PHY_TIMING5_CYCPWR_THR1); | |
1233 | iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah, | |
1234 | AR_PHY_EXT_CCA, | |
1235 | AR_PHY_EXT_TIMING5_CYCPWR_THR1); | |
1236 | ||
1237 | /* these levels just got reset to defaults by the INI */ | |
465dce62 FF |
1238 | aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL; |
1239 | aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL; | |
4f4395c6 | 1240 | aniState->ofdmWeakSigDetect = true; |
81b67fd6 | 1241 | aniState->mrcCCK = false; /* not available on pre AR9003 */ |
e36b27af LR |
1242 | } |
1243 | ||
f2552e28 FF |
1244 | static void ar5008_hw_set_nf_limits(struct ath_hw *ah) |
1245 | { | |
1246 | ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ; | |
1247 | ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ; | |
1248 | ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ; | |
1249 | ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ; | |
1250 | ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ; | |
1251 | ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ; | |
1252 | } | |
e36b27af | 1253 | |
4e8c14e9 FF |
1254 | static void ar5008_hw_set_radar_params(struct ath_hw *ah, |
1255 | struct ath_hw_radar_conf *conf) | |
1256 | { | |
1257 | u32 radar_0 = 0, radar_1 = 0; | |
1258 | ||
1259 | if (!conf) { | |
1260 | REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA); | |
1261 | return; | |
1262 | } | |
1263 | ||
1264 | radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA; | |
1265 | radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR); | |
1266 | radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI); | |
1267 | radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT); | |
1268 | radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI); | |
1269 | radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND); | |
1270 | ||
1271 | radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI; | |
1272 | radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK; | |
1273 | radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN); | |
1274 | radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH); | |
1275 | radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH); | |
1276 | ||
1277 | REG_WRITE(ah, AR_PHY_RADAR_0, radar_0); | |
1278 | REG_WRITE(ah, AR_PHY_RADAR_1, radar_1); | |
1279 | if (conf->ext_channel) | |
1280 | REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); | |
1281 | else | |
1282 | REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); | |
1283 | } | |
1284 | ||
c5d0855a FF |
1285 | static void ar5008_hw_set_radar_conf(struct ath_hw *ah) |
1286 | { | |
1287 | struct ath_hw_radar_conf *conf = &ah->radar_conf; | |
1288 | ||
1289 | conf->fir_power = -33; | |
1290 | conf->radar_rssi = 20; | |
1291 | conf->pulse_height = 10; | |
1292 | conf->pulse_rssi = 24; | |
1293 | conf->pulse_inband = 15; | |
1294 | conf->pulse_maxlen = 255; | |
1295 | conf->pulse_inband_step = 12; | |
1296 | conf->radar_inband = 8; | |
1297 | } | |
1298 | ||
c1b976d2 | 1299 | int ar5008_hw_attach_phy_ops(struct ath_hw *ah) |
8fe65368 LR |
1300 | { |
1301 | struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); | |
07b2fa5a | 1302 | static const u32 ar5416_cca_regs[6] = { |
bbacee13 FF |
1303 | AR_PHY_CCA, |
1304 | AR_PHY_CH1_CCA, | |
1305 | AR_PHY_CH2_CCA, | |
1306 | AR_PHY_EXT_CCA, | |
1307 | AR_PHY_CH1_EXT_CCA, | |
1308 | AR_PHY_CH2_EXT_CCA | |
1309 | }; | |
c1b976d2 FF |
1310 | int ret; |
1311 | ||
1312 | ret = ar5008_hw_rf_alloc_ext_banks(ah); | |
1313 | if (ret) | |
1314 | return ret; | |
8fe65368 LR |
1315 | |
1316 | priv_ops->rf_set_freq = ar5008_hw_set_channel; | |
1317 | priv_ops->spur_mitigate_freq = ar5008_hw_spur_mitigate; | |
1318 | ||
8fe65368 LR |
1319 | priv_ops->set_rf_regs = ar5008_hw_set_rf_regs; |
1320 | priv_ops->set_channel_regs = ar5008_hw_set_channel_regs; | |
1321 | priv_ops->init_bb = ar5008_hw_init_bb; | |
1322 | priv_ops->process_ini = ar5008_hw_process_ini; | |
1323 | priv_ops->set_rfmode = ar5008_hw_set_rfmode; | |
1324 | priv_ops->mark_phy_inactive = ar5008_hw_mark_phy_inactive; | |
1325 | priv_ops->set_delta_slope = ar5008_hw_set_delta_slope; | |
1326 | priv_ops->rfbus_req = ar5008_hw_rfbus_req; | |
1327 | priv_ops->rfbus_done = ar5008_hw_rfbus_done; | |
8fe65368 | 1328 | priv_ops->restore_chainmask = ar5008_restore_chainmask; |
641d9921 | 1329 | priv_ops->do_getnf = ar5008_hw_do_getnf; |
4e8c14e9 | 1330 | priv_ops->set_radar_params = ar5008_hw_set_radar_params; |
64773964 | 1331 | |
6790ae7a FF |
1332 | priv_ops->ani_control = ar5008_hw_ani_control_new; |
1333 | priv_ops->ani_cache_ini_regs = ar5008_hw_ani_cache_ini_regs; | |
e36b27af | 1334 | |
491b209d | 1335 | if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) |
64773964 LR |
1336 | priv_ops->compute_pll_control = ar9160_hw_compute_pll_control; |
1337 | else | |
1338 | priv_ops->compute_pll_control = ar5008_hw_compute_pll_control; | |
f2552e28 FF |
1339 | |
1340 | ar5008_hw_set_nf_limits(ah); | |
c5d0855a | 1341 | ar5008_hw_set_radar_conf(ah); |
bbacee13 | 1342 | memcpy(ah->nf_regs, ar5416_cca_regs, sizeof(ah->nf_regs)); |
c1b976d2 | 1343 | return 0; |
8fe65368 | 1344 | } |