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ath9k_hw: increase symbol overlap window for half/quarter channels
[linux-2.6-block.git] / drivers / net / wireless / ath / ath9k / ar5008_phy.c
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
cfe8cba9 17#include "hw.h"
8fe65368
LR		 18#include "hw-ops.h"
19#include "../regd.h"
20#include "ar9002_phy.h"
e16393bb 21
e36b27af
LR		 22/* All code below is for AR5008, AR9001, AR9002 */
23
24static const int firstep_table[] =
25/* level: 0 1 2 3 4 5 6 7 8 */
26 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */
27
28static const int cycpwrThr1_table[] =
29/* level: 0 1 2 3 4 5 6 7 8 */
30 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */
31
32/*
33 * register values to turn OFDM weak signal detection OFF
34 */
35static const int m1ThreshLow_off = 127;
36static const int m2ThreshLow_off = 127;
37static const int m1Thresh_off = 127;
38static const int m2Thresh_off = 127;
39static const int m2CountThr_off = 31;
40static const int m2CountThrLow_off = 63;
41static const int m1ThreshLowExt_off = 127;
42static const int m2ThreshLowExt_off = 127;
43static const int m1ThreshExt_off = 127;
44static const int m2ThreshExt_off = 127;
45
e16393bb 46
a9b6b256
FF		 47static void ar5008_rf_bank_setup(u32 *bank, struct ar5416IniArray *array,
48 int col)
49{
50 int i;
51
52 for (i = 0; i < array->ia_rows; i++)
53 bank[i] = INI_RA(array, i, col);
54}
55
56
57#define REG_WRITE_RF_ARRAY(iniarray, regData, regWr) \
58 ar5008_write_rf_array(ah, iniarray, regData, &(regWr))
59
60static void ar5008_write_rf_array(struct ath_hw *ah, struct ar5416IniArray *array,
61 u32 *data, unsigned int *writecnt)
62{
63 int r;
64
65 ENABLE_REGWRITE_BUFFER(ah);
66
67 for (r = 0; r < array->ia_rows; r++) {
68 REG_WRITE(ah, INI_RA(array, r, 0), data[r]);
69 DO_DELAY(*writecnt);
70 }
71
72 REGWRITE_BUFFER_FLUSH(ah);
73}
74
ddcd4c08 75/**
8fe65368 76 * ar5008_hw_phy_modify_rx_buffer() - perform analog swizzling of parameters
ddcd4c08
LR		 77 * @rfbuf:
78 * @reg32:
79 * @numBits:
80 * @firstBit:
81 * @column:
82 *
83 * Performs analog "swizzling" of parameters into their location.
84 * Used on external AR2133/AR5133 radios.
85 */
8fe65368
LR		 86static void ar5008_hw_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
87 u32 numBits, u32 firstBit,
88 u32 column)
ddcd4c08
LR		 89{
90 u32 tmp32, mask, arrayEntry, lastBit;
91 int32_t bitPosition, bitsLeft;
92
93 tmp32 = ath9k_hw_reverse_bits(reg32, numBits);
94 arrayEntry = (firstBit - 1) / 8;
95 bitPosition = (firstBit - 1) % 8;
96 bitsLeft = numBits;
97 while (bitsLeft > 0) {
98 lastBit = (bitPosition + bitsLeft > 8) ?
99 8 : bitPosition + bitsLeft;
100 mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) <<
101 (column * 8);
102 rfBuf[arrayEntry] &= ~mask;
103 rfBuf[arrayEntry] |= ((tmp32 << bitPosition) <<
104 (column * 8)) & mask;
105 bitsLeft -= 8 - bitPosition;
106 tmp32 = tmp32 >> (8 - bitPosition);
107 bitPosition = 0;
108 arrayEntry++;
109 }
110}
111
a7765828
LR		 112/*
113 * Fix on 2.4 GHz band for orientation sensitivity issue by increasing
114 * rf_pwd_icsyndiv.
115 *
116 * Theoretical Rules:
117 * if 2 GHz band
118 * if forceBiasAuto
119 * if synth_freq < 2412
120 * bias = 0
121 * else if 2412 <= synth_freq <= 2422
122 * bias = 1
123 * else // synth_freq > 2422
124 * bias = 2
125 * else if forceBias > 0
126 * bias = forceBias & 7
127 * else
128 * no change, use value from ini file
129 * else
130 * no change, invalid band
131 *
132 * 1st Mod:
133 * 2422 also uses value of 2
134 * <approved>
135 *
136 * 2nd Mod:
137 * Less than 2412 uses value of 0, 2412 and above uses value of 2
138 */
8fe65368 139static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq)
a7765828
LR		 140{
141 struct ath_common *common = ath9k_hw_common(ah);
142 u32 tmp_reg;
143 int reg_writes = 0;
144 u32 new_bias = 0;
145
8fe65368 146 if (!AR_SREV_5416(ah) || synth_freq >= 3000)
a7765828 147 return;
a7765828 148
7a37081e 149 BUG_ON(AR_SREV_9280_20_OR_LATER(ah));
a7765828
LR		 150
151 if (synth_freq < 2412)
152 new_bias = 0;
153 else if (synth_freq < 2422)
154 new_bias = 1;
155 else
156 new_bias = 2;
157
158 /* pre-reverse this field */
159 tmp_reg = ath9k_hw_reverse_bits(new_bias, 3);
160
d2182b69 161 ath_dbg(common, CONFIG, "Force rf_pwd_icsyndiv to %1d on %4d\n",
226afe68 162 new_bias, synth_freq);
a7765828
LR		 163
164 /* swizzle rf_pwd_icsyndiv */
8fe65368 165 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3);
a7765828
LR		 166
167 /* write Bank 6 with new params */
168 REG_WRITE_RF_ARRAY(&ah->iniBank6, ah->analogBank6Data, reg_writes);
169}
170
e16393bb 171/**
8fe65368 172 * ar5008_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios
25985edc 173 * @ah: atheros hardware structure
e16393bb
LR		 174 * @chan:
175 *
176 * For the external AR2133/AR5133 radios, takes the MHz channel value and set
177 * the channel value. Assumes writes enabled to analog bus and bank6 register
178 * cache in ah->analogBank6Data.
179 */
8fe65368 180static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
e16393bb
LR		 181{
182 struct ath_common *common = ath9k_hw_common(ah);
183 u32 channelSel = 0;
184 u32 bModeSynth = 0;
185 u32 aModeRefSel = 0;
186 u32 reg32 = 0;
187 u16 freq;
188 struct chan_centers centers;
189
190 ath9k_hw_get_channel_centers(ah, chan, &centers);
191 freq = centers.synth_center;
192
193 if (freq < 4800) {
194 u32 txctl;
195
196 if (((freq - 2192) % 5) == 0) {
197 channelSel = ((freq - 672) * 2 - 3040) / 10;
198 bModeSynth = 0;
199 } else if (((freq - 2224) % 5) == 0) {
200 channelSel = ((freq - 704) * 2 - 3040) / 10;
201 bModeSynth = 1;
202 } else {
3800276a 203 ath_err(common, "Invalid channel %u MHz\n", freq);
e16393bb
LR		 204 return -EINVAL;
205 }
206
207 channelSel = (channelSel << 2) & 0xff;
208 channelSel = ath9k_hw_reverse_bits(channelSel, 8);
209
210 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
211 if (freq == 2484) {
212
213 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
214 txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
215 } else {
216 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
217 txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
218 }
219
220 } else if ((freq % 20) == 0 && freq >= 5120) {
221 channelSel =
222 ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8);
223 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
224 } else if ((freq % 10) == 0) {
225 channelSel =
226 ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8);
227 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
228 aModeRefSel = ath9k_hw_reverse_bits(2, 2);
229 else
230 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
231 } else if ((freq % 5) == 0) {
232 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
233 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
234 } else {
3800276a 235 ath_err(common, "Invalid channel %u MHz\n", freq);
e16393bb
LR		 236 return -EINVAL;
237 }
238
8fe65368 239 ar5008_hw_force_bias(ah, freq);
a7765828 240
e16393bb
LR		 241 reg32 =
242 (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
243 (1 << 5) | 0x1;
244
245 REG_WRITE(ah, AR_PHY(0x37), reg32);
246
247 ah->curchan = chan;
e16393bb
LR		 248
249 return 0;
250}
251
252/**
8fe65368 253 * ar5008_hw_spur_mitigate - convert baseband spur frequency for external radios
e16393bb
LR		 254 * @ah: atheros hardware structure
255 * @chan:
256 *
257 * For non single-chip solutions. Converts to baseband spur frequency given the
258 * input channel frequency and compute register settings below.
259 */
8fe65368
LR		 260static void ar5008_hw_spur_mitigate(struct ath_hw *ah,
261 struct ath9k_channel *chan)
e16393bb
LR		 262{
263 int bb_spur = AR_NO_SPUR;
264 int bin, cur_bin;
265 int spur_freq_sd;
266 int spur_delta_phase;
267 int denominator;
268 int upper, lower, cur_vit_mask;
269 int tmp, new;
270 int i;
07b2fa5a
JP		 271 static int pilot_mask_reg[4] = {
272 AR_PHY_TIMING7, AR_PHY_TIMING8,
273 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
e16393bb 274 };
07b2fa5a
JP		 275 static int chan_mask_reg[4] = {
276 AR_PHY_TIMING9, AR_PHY_TIMING10,
277 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
e16393bb 278 };
07b2fa5a 279 static int inc[4] = { 0, 100, 0, 0 };
e16393bb
LR		 280
281 int8_t mask_m[123];
282 int8_t mask_p[123];
283 int8_t mask_amt;
284 int tmp_mask;
285 int cur_bb_spur;
286 bool is2GHz = IS_CHAN_2GHZ(chan);
287
288 memset(&mask_m, 0, sizeof(int8_t) * 123);
289 memset(&mask_p, 0, sizeof(int8_t) * 123);
290
291 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
292 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
293 if (AR_NO_SPUR == cur_bb_spur)
294 break;
295 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
296 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
297 bb_spur = cur_bb_spur;
298 break;
299 }
300 }
301
302 if (AR_NO_SPUR == bb_spur)
303 return;
304
305 bin = bb_spur * 32;
306
307 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
308 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
309 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
310 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
311 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
312
313 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
314
315 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
316 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
317 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
318 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
319 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
320 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
321
322 spur_delta_phase = ((bb_spur * 524288) / 100) &
323 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
324
325 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
326 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
327
328 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
329 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
330 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
331 REG_WRITE(ah, AR_PHY_TIMING11, new);
332
333 cur_bin = -6000;
334 upper = bin + 100;
335 lower = bin - 100;
336
337 for (i = 0; i < 4; i++) {
338 int pilot_mask = 0;
339 int chan_mask = 0;
340 int bp = 0;
341 for (bp = 0; bp < 30; bp++) {
342 if ((cur_bin > lower) && (cur_bin < upper)) {
343 pilot_mask = pilot_mask | 0x1 << bp;
344 chan_mask = chan_mask | 0x1 << bp;
345 }
346 cur_bin += 100;
347 }
348 cur_bin += inc[i];
349 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
350 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
351 }
352
353 cur_vit_mask = 6100;
354 upper = bin + 120;
355 lower = bin - 120;
356
357 for (i = 0; i < 123; i++) {
358 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
359
360 /* workaround for gcc bug #37014 */
361 volatile int tmp_v = abs(cur_vit_mask - bin);
362
363 if (tmp_v < 75)
364 mask_amt = 1;
365 else
366 mask_amt = 0;
367 if (cur_vit_mask < 0)
368 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
369 else
370 mask_p[cur_vit_mask / 100] = mask_amt;
371 }
372 cur_vit_mask -= 100;
373 }
374
375 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
376 | (mask_m[48] << 26) | (mask_m[49] << 24)
377 | (mask_m[50] << 22) | (mask_m[51] << 20)
378 | (mask_m[52] << 18) | (mask_m[53] << 16)
379 | (mask_m[54] << 14) | (mask_m[55] << 12)
380 | (mask_m[56] << 10) | (mask_m[57] << 8)
381 | (mask_m[58] << 6) | (mask_m[59] << 4)
382 | (mask_m[60] << 2) | (mask_m[61] << 0);
383 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
384 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
385
386 tmp_mask = (mask_m[31] << 28)
387 | (mask_m[32] << 26) | (mask_m[33] << 24)
388 | (mask_m[34] << 22) | (mask_m[35] << 20)
389 | (mask_m[36] << 18) | (mask_m[37] << 16)
390 | (mask_m[48] << 14) | (mask_m[39] << 12)
391 | (mask_m[40] << 10) | (mask_m[41] << 8)
392 | (mask_m[42] << 6) | (mask_m[43] << 4)
393 | (mask_m[44] << 2) | (mask_m[45] << 0);
394 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
395 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
396
397 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
398 | (mask_m[18] << 26) | (mask_m[18] << 24)
399 | (mask_m[20] << 22) | (mask_m[20] << 20)
400 | (mask_m[22] << 18) | (mask_m[22] << 16)
401 | (mask_m[24] << 14) | (mask_m[24] << 12)
402 | (mask_m[25] << 10) | (mask_m[26] << 8)
403 | (mask_m[27] << 6) | (mask_m[28] << 4)
404 | (mask_m[29] << 2) | (mask_m[30] << 0);
405 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
406 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
407
408 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
409 | (mask_m[2] << 26) | (mask_m[3] << 24)
410 | (mask_m[4] << 22) | (mask_m[5] << 20)
411 | (mask_m[6] << 18) | (mask_m[7] << 16)
412 | (mask_m[8] << 14) | (mask_m[9] << 12)
413 | (mask_m[10] << 10) | (mask_m[11] << 8)
414 | (mask_m[12] << 6) | (mask_m[13] << 4)
415 | (mask_m[14] << 2) | (mask_m[15] << 0);
416 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
417 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
418
419 tmp_mask = (mask_p[15] << 28)
420 | (mask_p[14] << 26) | (mask_p[13] << 24)
421 | (mask_p[12] << 22) | (mask_p[11] << 20)
422 | (mask_p[10] << 18) | (mask_p[9] << 16)
423 | (mask_p[8] << 14) | (mask_p[7] << 12)
424 | (mask_p[6] << 10) | (mask_p[5] << 8)
425 | (mask_p[4] << 6) | (mask_p[3] << 4)
426 | (mask_p[2] << 2) | (mask_p[1] << 0);
427 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
428 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
429
430 tmp_mask = (mask_p[30] << 28)
431 | (mask_p[29] << 26) | (mask_p[28] << 24)
432 | (mask_p[27] << 22) | (mask_p[26] << 20)
433 | (mask_p[25] << 18) | (mask_p[24] << 16)
434 | (mask_p[23] << 14) | (mask_p[22] << 12)
435 | (mask_p[21] << 10) | (mask_p[20] << 8)
436 | (mask_p[19] << 6) | (mask_p[18] << 4)
437 | (mask_p[17] << 2) | (mask_p[16] << 0);
438 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
439 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
440
441 tmp_mask = (mask_p[45] << 28)
442 | (mask_p[44] << 26) | (mask_p[43] << 24)
443 | (mask_p[42] << 22) | (mask_p[41] << 20)
444 | (mask_p[40] << 18) | (mask_p[39] << 16)
445 | (mask_p[38] << 14) | (mask_p[37] << 12)
446 | (mask_p[36] << 10) | (mask_p[35] << 8)
447 | (mask_p[34] << 6) | (mask_p[33] << 4)
448 | (mask_p[32] << 2) | (mask_p[31] << 0);
449 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
450 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
451
452 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
453 | (mask_p[59] << 26) | (mask_p[58] << 24)
454 | (mask_p[57] << 22) | (mask_p[56] << 20)
455 | (mask_p[55] << 18) | (mask_p[54] << 16)
456 | (mask_p[53] << 14) | (mask_p[52] << 12)
457 | (mask_p[51] << 10) | (mask_p[50] << 8)
458 | (mask_p[49] << 6) | (mask_p[48] << 4)
459 | (mask_p[47] << 2) | (mask_p[46] << 0);
460 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
461 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
462}
463
464/**
8fe65368 465 * ar5008_hw_rf_alloc_ext_banks - allocates banks for external radio programming
e16393bb
LR		 466 * @ah: atheros hardware structure
467 *
468 * Only required for older devices with external AR2133/AR5133 radios.
469 */
8fe65368 470static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah)
e16393bb
LR		 471{
472#define ATH_ALLOC_BANK(bank, size) do { \
473 bank = kzalloc((sizeof(u32) * size), GFP_KERNEL); \
474 if (!bank) { \
3800276a 475 ath_err(common, "Cannot allocate RF banks\n"); \
e16393bb
LR		 476 return -ENOMEM; \
477 } \
478 } while (0);
479
480 struct ath_common *common = ath9k_hw_common(ah);
481
7a37081e 482 BUG_ON(AR_SREV_9280_20_OR_LATER(ah));
e16393bb
LR		 483
484 ATH_ALLOC_BANK(ah->analogBank0Data, ah->iniBank0.ia_rows);
485 ATH_ALLOC_BANK(ah->analogBank1Data, ah->iniBank1.ia_rows);
486 ATH_ALLOC_BANK(ah->analogBank2Data, ah->iniBank2.ia_rows);
487 ATH_ALLOC_BANK(ah->analogBank3Data, ah->iniBank3.ia_rows);
488 ATH_ALLOC_BANK(ah->analogBank6Data, ah->iniBank6.ia_rows);
489 ATH_ALLOC_BANK(ah->analogBank6TPCData, ah->iniBank6TPC.ia_rows);
490 ATH_ALLOC_BANK(ah->analogBank7Data, ah->iniBank7.ia_rows);
e16393bb
LR		 491 ATH_ALLOC_BANK(ah->bank6Temp, ah->iniBank6.ia_rows);
492
493 return 0;
494#undef ATH_ALLOC_BANK
495}
496
497
498/**
8fe65368 499 * ar5008_hw_rf_free_ext_banks - Free memory for analog bank scratch buffers
e16393bb
LR		 500 * @ah: atheros hardware struture
501 * For the external AR2133/AR5133 radios banks.
502 */
8fe65368 503static void ar5008_hw_rf_free_ext_banks(struct ath_hw *ah)
e16393bb
LR		 504{
505#define ATH_FREE_BANK(bank) do { \
506 kfree(bank); \
507 bank = NULL; \
508 } while (0);
509
7a37081e 510 BUG_ON(AR_SREV_9280_20_OR_LATER(ah));
e16393bb
LR		 511
512 ATH_FREE_BANK(ah->analogBank0Data);
513 ATH_FREE_BANK(ah->analogBank1Data);
514 ATH_FREE_BANK(ah->analogBank2Data);
515 ATH_FREE_BANK(ah->analogBank3Data);
516 ATH_FREE_BANK(ah->analogBank6Data);
517 ATH_FREE_BANK(ah->analogBank6TPCData);
518 ATH_FREE_BANK(ah->analogBank7Data);
e16393bb
LR		 519 ATH_FREE_BANK(ah->bank6Temp);
520
521#undef ATH_FREE_BANK
522}
523
131d1d03 524/* *
8fe65368 525 * ar5008_hw_set_rf_regs - programs rf registers based on EEPROM
131d1d03
LR		 526 * @ah: atheros hardware structure
527 * @chan:
528 * @modesIndex:
529 *
530 * Used for the external AR2133/AR5133 radios.
531 *
532 * Reads the EEPROM header info from the device structure and programs
533 * all rf registers. This routine requires access to the analog
534 * rf device. This is not required for single-chip devices.
535 */
8fe65368
LR		 536static bool ar5008_hw_set_rf_regs(struct ath_hw *ah,
537 struct ath9k_channel *chan,
538 u16 modesIndex)
f078f209 539{
f078f209
LR		 540 u32 eepMinorRev;
541 u32 ob5GHz = 0, db5GHz = 0;
542 u32 ob2GHz = 0, db2GHz = 0;
543 int regWrites = 0;
544
131d1d03
LR		 545 /*
546 * Software does not need to program bank data
547 * for single chip devices, that is AR9280 or anything
548 * after that.
549 */
7a37081e 550 if (AR_SREV_9280_20_OR_LATER(ah))
f078f209
LR		 551 return true;
552
131d1d03 553 /* Setup rf parameters */
f74df6fb 554 eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV);
f078f209 555
131d1d03 556 /* Setup Bank 0 Write */
a9b6b256 557 ar5008_rf_bank_setup(ah->analogBank0Data, &ah->iniBank0, 1);
f078f209 558
131d1d03 559 /* Setup Bank 1 Write */
a9b6b256 560 ar5008_rf_bank_setup(ah->analogBank1Data, &ah->iniBank1, 1);
f078f209 561
131d1d03 562 /* Setup Bank 2 Write */
a9b6b256 563 ar5008_rf_bank_setup(ah->analogBank2Data, &ah->iniBank2, 1);
f078f209 564
131d1d03 565 /* Setup Bank 6 Write */
a9b6b256 566 ar5008_rf_bank_setup(ah->analogBank3Data, &ah->iniBank3,
f078f209
LR		 567 modesIndex);
568 {
569 int i;
2660b81a
S		 570 for (i = 0; i < ah->iniBank6TPC.ia_rows; i++) {
571 ah->analogBank6Data[i] =
572 INI_RA(&ah->iniBank6TPC, i, modesIndex);
f078f209
LR		 573 }
574 }
575
131d1d03 576 /* Only the 5 or 2 GHz OB/DB need to be set for a mode */
f078f209
LR		 577 if (eepMinorRev >= 2) {
578 if (IS_CHAN_2GHZ(chan)) {
f74df6fb
S		 579 ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2);
580 db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2);
8fe65368
LR		 581 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
582 ob2GHz, 3, 197, 0);
583 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
584 db2GHz, 3, 194, 0);
f078f209 585 } else {
f74df6fb
S		 586 ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5);
587 db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5);
8fe65368
LR		 588 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
589 ob5GHz, 3, 203, 0);
590 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
591 db5GHz, 3, 200, 0);
f078f209
LR		 592 }
593 }
594
131d1d03 595 /* Setup Bank 7 Setup */
a9b6b256 596 ar5008_rf_bank_setup(ah->analogBank7Data, &ah->iniBank7, 1);
f078f209 597
131d1d03 598 /* Write Analog registers */
2660b81a 599 REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data,
f078f209 600 regWrites);
2660b81a 601 REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data,
f078f209 602 regWrites);
2660b81a 603 REG_WRITE_RF_ARRAY(&ah->iniBank2, ah->analogBank2Data,
f078f209 604 regWrites);
2660b81a 605 REG_WRITE_RF_ARRAY(&ah->iniBank3, ah->analogBank3Data,
f078f209 606 regWrites);
2660b81a 607 REG_WRITE_RF_ARRAY(&ah->iniBank6TPC, ah->analogBank6Data,
f078f209 608 regWrites);
2660b81a 609 REG_WRITE_RF_ARRAY(&ah->iniBank7, ah->analogBank7Data,
f078f209
LR		 610 regWrites);
611
612 return true;
613}
8fe65368
LR		 614
615static void ar5008_hw_init_bb(struct ath_hw *ah,
616 struct ath9k_channel *chan)
617{
618 u32 synthDelay;
619
620 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
621 if (IS_CHAN_B(chan))
622 synthDelay = (4 * synthDelay) / 22;
623 else
624 synthDelay /= 10;
625
7d865c70
FF		 626 if (IS_CHAN_HALF_RATE(chan))
627 synthDelay *= 2;
628 else if (IS_CHAN_QUARTER_RATE(chan))
629 synthDelay *= 4;
630
8fe65368
LR		 631 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
632
633 udelay(synthDelay + BASE_ACTIVATE_DELAY);
634}
635
636static void ar5008_hw_init_chain_masks(struct ath_hw *ah)
637{
638 int rx_chainmask, tx_chainmask;
639
640 rx_chainmask = ah->rxchainmask;
641 tx_chainmask = ah->txchainmask;
642
7d0d0df0 643
8fe65368
LR		 644 switch (rx_chainmask) {
645 case 0x5:
646 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
647 AR_PHY_SWAP_ALT_CHAIN);
648 case 0x3:
649 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
650 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
651 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
652 break;
653 }
654 case 0x1:
655 case 0x2:
656 case 0x7:
435c1610 657 ENABLE_REGWRITE_BUFFER(ah);
8fe65368
LR		 658 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
659 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
660 break;
661 default:
435c1610 662 ENABLE_REGWRITE_BUFFER(ah);
8fe65368
LR		 663 break;
664 }
665
666 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
7d0d0df0
S		 667
668 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 669
8fe65368
LR		 670 if (tx_chainmask == 0x5) {
671 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
672 AR_PHY_SWAP_ALT_CHAIN);
673 }
674 if (AR_SREV_9100(ah))
675 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
676 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
677}
678
679static void ar5008_hw_override_ini(struct ath_hw *ah,
680 struct ath9k_channel *chan)
681{
682 u32 val;
683
684 /*
685 * Set the RX_ABORT and RX_DIS and clear if off only after
686 * RXE is set for MAC. This prevents frames with corrupted
687 * descriptor status.
688 */
689 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
690
7a37081e 691 if (AR_SREV_9280_20_OR_LATER(ah)) {
8fe65368
LR		 692 val = REG_READ(ah, AR_PCU_MISC_MODE2);
693
694 if (!AR_SREV_9271(ah))
695 val &= ~AR_PCU_MISC_MODE2_HWWAR1;
696
a42acef0 697 if (AR_SREV_9287_11_OR_LATER(ah))
8fe65368
LR		 698 val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
699
700 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
701 }
702
bf3f204b
FF		 703 REG_SET_BIT(ah, AR_PHY_CCK_DETECT,
704 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
705
1b8714f7 706 if (AR_SREV_9280_20_OR_LATER(ah))
8fe65368
LR		 707 return;
708 /*
709 * Disable BB clock gating
710 * Necessary to avoid issues on AR5416 2.0
711 */
712 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
713
714 /*
715 * Disable RIFS search on some chips to avoid baseband
716 * hang issues.
717 */
718 if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) {
719 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
720 val &= ~AR_PHY_RIFS_INIT_DELAY;
721 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
722 }
723}
724
725static void ar5008_hw_set_channel_regs(struct ath_hw *ah,
726 struct ath9k_channel *chan)
727{
728 u32 phymode;
729 u32 enableDacFifo = 0;
730
e17f83ea 731 if (AR_SREV_9285_12_OR_LATER(ah))
8fe65368
LR		 732 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
733 AR_PHY_FC_ENABLE_DAC_FIFO);
734
735 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
736 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
737
738 if (IS_CHAN_HT40(chan)) {
739 phymode |= AR_PHY_FC_DYN2040_EN;
740
741 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
742 (chan->chanmode == CHANNEL_G_HT40PLUS))
743 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
744
745 }
746 REG_WRITE(ah, AR_PHY_TURBO, phymode);
747
748 ath9k_hw_set11nmac2040(ah);
749
7d0d0df0
S		 750 ENABLE_REGWRITE_BUFFER(ah);
751
8fe65368
LR		 752 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
753 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
7d0d0df0
S		 754
755 REGWRITE_BUFFER_FLUSH(ah);
8fe65368
LR		 756}
757
758
759static int ar5008_hw_process_ini(struct ath_hw *ah,
760 struct ath9k_channel *chan)
761{
e7fc6338 762 struct ath_common *common = ath9k_hw_common(ah);
8fe65368 763 int i, regWrites = 0;
8fe65368
LR		 764 u32 modesIndex, freqIndex;
765
766 switch (chan->chanmode) {
767 case CHANNEL_A:
768 case CHANNEL_A_HT20:
769 modesIndex = 1;
770 freqIndex = 1;
771 break;
772 case CHANNEL_A_HT40PLUS:
773 case CHANNEL_A_HT40MINUS:
774 modesIndex = 2;
775 freqIndex = 1;
776 break;
777 case CHANNEL_G:
778 case CHANNEL_G_HT20:
779 case CHANNEL_B:
780 modesIndex = 4;
781 freqIndex = 2;
782 break;
783 case CHANNEL_G_HT40PLUS:
784 case CHANNEL_G_HT40MINUS:
785 modesIndex = 3;
786 freqIndex = 2;
787 break;
788
789 default:
790 return -EINVAL;
791 }
792
8fe65368
LR		 793 /*
794 * Set correct baseband to analog shift setting to
795 * access analog chips.
796 */
797 REG_WRITE(ah, AR_PHY(0), 0x00000007);
798
799 /* Write ADDAC shifts */
800 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
d7084da0
FF		 801 if (ah->eep_ops->set_addac)
802 ah->eep_ops->set_addac(ah, chan);
8fe65368 803
9bbb8168 804 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
8fe65368
LR		 805 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
806
7d0d0df0
S		 807 ENABLE_REGWRITE_BUFFER(ah);
808
8fe65368
LR		 809 for (i = 0; i < ah->iniModes.ia_rows; i++) {
810 u32 reg = INI_RA(&ah->iniModes, i, 0);
811 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
812
813 if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup)
814 val &= ~AR_AN_TOP2_PWDCLKIND;
815
816 REG_WRITE(ah, reg, val);
817
818 if (reg >= 0x7800 && reg < 0x78a0
e7fc6338
RM		 819 && ah->config.analog_shiftreg
820 && (common->bus_ops->ath_bus_type != ATH_USB)) {
8fe65368
LR		 821 udelay(100);
822 }
823
824 DO_DELAY(regWrites);
825 }
826
7d0d0df0 827 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 828
a42acef0 829 if (AR_SREV_9280(ah) || AR_SREV_9287_11_OR_LATER(ah))
8fe65368
LR		 830 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
831
832 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
a42acef0 833 AR_SREV_9287_11_OR_LATER(ah))
8fe65368
LR		 834 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
835
c7effd35
FF		 836 if (AR_SREV_9271_10(ah)) {
837 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENA);
838 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_ADC_ON, 0xa);
839 }
8fe65368 840
7d0d0df0
S		 841 ENABLE_REGWRITE_BUFFER(ah);
842
8fe65368
LR		 843 /* Write common array parameters */
844 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
845 u32 reg = INI_RA(&ah->iniCommon, i, 0);
846 u32 val = INI_RA(&ah->iniCommon, i, 1);
847
848 REG_WRITE(ah, reg, val);
849
850 if (reg >= 0x7800 && reg < 0x78a0
e7fc6338
RM		 851 && ah->config.analog_shiftreg
852 && (common->bus_ops->ath_bus_type != ATH_USB)) {
8fe65368
LR		 853 udelay(100);
854 }
855
856 DO_DELAY(regWrites);
857 }
858
7d0d0df0 859 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 860
8fe65368
LR		 861 REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites);
862
c7d36f9f
FF		 863 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
864 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex,
8fe65368 865 regWrites);
8fe65368
LR		 866
867 ar5008_hw_override_ini(ah, chan);
868 ar5008_hw_set_channel_regs(ah, chan);
869 ar5008_hw_init_chain_masks(ah);
870 ath9k_olc_init(ah);
ca2c68cc 871 ath9k_hw_apply_txpower(ah, chan);
8fe65368
LR		 872
873 /* Write analog registers */
874 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
3800276a 875 ath_err(ath9k_hw_common(ah), "ar5416SetRfRegs failed\n");
8fe65368
LR		 876 return -EIO;
877 }
878
879 return 0;
880}
881
882static void ar5008_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
883{
884 u32 rfMode = 0;
885
886 if (chan == NULL)
887 return;
888
889 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
890 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
891
7a37081e 892 if (!AR_SREV_9280_20_OR_LATER(ah))
8fe65368
LR		 893 rfMode |= (IS_CHAN_5GHZ(chan)) ?
894 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
895
6b42e8d0 896 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
8fe65368
LR		 897 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
898
899 REG_WRITE(ah, AR_PHY_MODE, rfMode);
900}
901
902static void ar5008_hw_mark_phy_inactive(struct ath_hw *ah)
903{
904 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
905}
906
907static void ar5008_hw_set_delta_slope(struct ath_hw *ah,
908 struct ath9k_channel *chan)
909{
910 u32 coef_scaled, ds_coef_exp, ds_coef_man;
911 u32 clockMhzScaled = 0x64000000;
912 struct chan_centers centers;
913
914 if (IS_CHAN_HALF_RATE(chan))
915 clockMhzScaled = clockMhzScaled >> 1;
916 else if (IS_CHAN_QUARTER_RATE(chan))
917 clockMhzScaled = clockMhzScaled >> 2;
918
919 ath9k_hw_get_channel_centers(ah, chan, &centers);
920 coef_scaled = clockMhzScaled / centers.synth_center;
921
922 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
923 &ds_coef_exp);
924
925 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
926 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
927 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
928 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
929
930 coef_scaled = (9 * coef_scaled) / 10;
931
932 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
933 &ds_coef_exp);
934
935 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
936 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
937 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
938 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
939}
940
941static bool ar5008_hw_rfbus_req(struct ath_hw *ah)
942{
943 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
944 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
945 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
946}
947
948static void ar5008_hw_rfbus_done(struct ath_hw *ah)
949{
950 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
951 if (IS_CHAN_B(ah->curchan))
952 synthDelay = (4 * synthDelay) / 22;
953 else
954 synthDelay /= 10;
955
956 udelay(synthDelay + BASE_ACTIVATE_DELAY);
957
958 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
959}
960
8fe65368
LR		 961static void ar5008_restore_chainmask(struct ath_hw *ah)
962{
963 int rx_chainmask = ah->rxchainmask;
964
965 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
966 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
967 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
968 }
969}
970
64773964
LR		 971static u32 ar9160_hw_compute_pll_control(struct ath_hw *ah,
972 struct ath9k_channel *chan)
973{
974 u32 pll;
975
976 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
977
978 if (chan && IS_CHAN_HALF_RATE(chan))
979 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
980 else if (chan && IS_CHAN_QUARTER_RATE(chan))
981 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
982
983 if (chan && IS_CHAN_5GHZ(chan))
984 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
985 else
986 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
987
988 return pll;
989}
990
991static u32 ar5008_hw_compute_pll_control(struct ath_hw *ah,
992 struct ath9k_channel *chan)
993{
994 u32 pll;
995
996 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
997
998 if (chan && IS_CHAN_HALF_RATE(chan))
999 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1000 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1001 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1002
1003 if (chan && IS_CHAN_5GHZ(chan))
1004 pll |= SM(0xa, AR_RTC_PLL_DIV);
1005 else
1006 pll |= SM(0xb, AR_RTC_PLL_DIV);
1007
1008 return pll;
1009}
1010
e36b27af
LR		 1011static bool ar5008_hw_ani_control_old(struct ath_hw *ah,
1012 enum ath9k_ani_cmd cmd,
1013 int param)
c16fcb49 1014{
093115b7 1015 struct ar5416AniState *aniState = &ah->curchan->ani;
c16fcb49
FF		 1016 struct ath_common *common = ath9k_hw_common(ah);
1017
1018 switch (cmd & ah->ani_function) {
1019 case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
1020 u32 level = param;
1021
1022 if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {
d2182b69 1023 ath_dbg(common, ANI, "level out of range (%u > %zu)\n",
226afe68 1024 level, ARRAY_SIZE(ah->totalSizeDesired));
c16fcb49
FF		 1025 return false;
1026 }
1027
1028 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
1029 AR_PHY_DESIRED_SZ_TOT_DES,
1030 ah->totalSizeDesired[level]);
1031 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
1032 AR_PHY_AGC_CTL1_COARSE_LOW,
1033 ah->coarse_low[level]);
1034 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
1035 AR_PHY_AGC_CTL1_COARSE_HIGH,
1036 ah->coarse_high[level]);
1037 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1038 AR_PHY_FIND_SIG_FIRPWR,
1039 ah->firpwr[level]);
1040
1041 if (level > aniState->noiseImmunityLevel)
1042 ah->stats.ast_ani_niup++;
1043 else if (level < aniState->noiseImmunityLevel)
1044 ah->stats.ast_ani_nidown++;
1045 aniState->noiseImmunityLevel = level;
1046 break;
1047 }
1048 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
c16fcb49
FF		 1049 u32 on = param ? 1 : 0;
1050
c16fcb49
FF		 1051 if (on)
1052 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
1053 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1054 else
1055 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
1056 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1057
1058 if (!on != aniState->ofdmWeakSigDetectOff) {
1059 if (on)
1060 ah->stats.ast_ani_ofdmon++;
1061 else
1062 ah->stats.ast_ani_ofdmoff++;
1063 aniState->ofdmWeakSigDetectOff = !on;
1064 }
1065 break;
1066 }
1067 case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
07b2fa5a 1068 static const int weakSigThrCck[] = { 8, 6 };
c16fcb49
FF		 1069 u32 high = param ? 1 : 0;
1070
1071 REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
1072 AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
1073 weakSigThrCck[high]);
1074 if (high != aniState->cckWeakSigThreshold) {
1075 if (high)
1076 ah->stats.ast_ani_cckhigh++;
1077 else
1078 ah->stats.ast_ani_ccklow++;
1079 aniState->cckWeakSigThreshold = high;
1080 }
1081 break;
1082 }
1083 case ATH9K_ANI_FIRSTEP_LEVEL:{
07b2fa5a 1084 static const int firstep[] = { 0, 4, 8 };
c16fcb49
FF		 1085 u32 level = param;
1086
1087 if (level >= ARRAY_SIZE(firstep)) {
d2182b69 1088 ath_dbg(common, ANI, "level out of range (%u > %zu)\n",
226afe68 1089 level, ARRAY_SIZE(firstep));
c16fcb49
FF		 1090 return false;
1091 }
1092 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1093 AR_PHY_FIND_SIG_FIRSTEP,
1094 firstep[level]);
1095 if (level > aniState->firstepLevel)
1096 ah->stats.ast_ani_stepup++;
1097 else if (level < aniState->firstepLevel)
1098 ah->stats.ast_ani_stepdown++;
1099 aniState->firstepLevel = level;
1100 break;
1101 }
1102 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
07b2fa5a 1103 static const int cycpwrThr1[] = { 2, 4, 6, 8, 10, 12, 14, 16 };
c16fcb49
FF		 1104 u32 level = param;
1105
1106 if (level >= ARRAY_SIZE(cycpwrThr1)) {
d2182b69 1107 ath_dbg(common, ANI, "level out of range (%u > %zu)\n",
226afe68 1108 level, ARRAY_SIZE(cycpwrThr1));
c16fcb49
FF		 1109 return false;
1110 }
1111 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
1112 AR_PHY_TIMING5_CYCPWR_THR1,
1113 cycpwrThr1[level]);
1114 if (level > aniState->spurImmunityLevel)
1115 ah->stats.ast_ani_spurup++;
1116 else if (level < aniState->spurImmunityLevel)
1117 ah->stats.ast_ani_spurdown++;
1118 aniState->spurImmunityLevel = level;
1119 break;
1120 }
1121 case ATH9K_ANI_PRESENT:
1122 break;
1123 default:
d2182b69 1124 ath_dbg(common, ANI, "invalid cmd %u\n", cmd);
c16fcb49
FF		 1125 return false;
1126 }
1127
d2182b69
JP		 1128 ath_dbg(common, ANI, "ANI parameters:\n");
1129 ath_dbg(common, ANI,
226afe68
JP		 1130 "noiseImmunityLevel=%d, spurImmunityLevel=%d, ofdmWeakSigDetectOff=%d\n",
1131 aniState->noiseImmunityLevel,
1132 aniState->spurImmunityLevel,
1133 !aniState->ofdmWeakSigDetectOff);
d2182b69 1134 ath_dbg(common, ANI,
226afe68
JP		 1135 "cckWeakSigThreshold=%d, firstepLevel=%d, listenTime=%d\n",
1136 aniState->cckWeakSigThreshold,
1137 aniState->firstepLevel,
1138 aniState->listenTime);
d2182b69 1139 ath_dbg(common, ANI, "ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
c16fcb49
FF		 1140 aniState->ofdmPhyErrCount,
1141 aniState->cckPhyErrCount);
1142
1143 return true;
1144}
1145
e36b27af
LR		 1146static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
1147 enum ath9k_ani_cmd cmd,
1148 int param)
1149{
e36b27af
LR		 1150 struct ath_common *common = ath9k_hw_common(ah);
1151 struct ath9k_channel *chan = ah->curchan;
093115b7 1152 struct ar5416AniState *aniState = &chan->ani;
e36b27af
LR		 1153 s32 value, value2;
1154
1155 switch (cmd & ah->ani_function) {
1156 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
1157 /*
1158 * on == 1 means ofdm weak signal detection is ON
1159 * on == 1 is the default, for less noise immunity
1160 *
1161 * on == 0 means ofdm weak signal detection is OFF
1162 * on == 0 means more noise imm
1163 */
1164 u32 on = param ? 1 : 0;
1165 /*
1166 * make register setting for default
1167 * (weak sig detect ON) come from INI file
1168 */
1169 int m1ThreshLow = on ?
1170 aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
1171 int m2ThreshLow = on ?
1172 aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
1173 int m1Thresh = on ?
1174 aniState->iniDef.m1Thresh : m1Thresh_off;
1175 int m2Thresh = on ?
1176 aniState->iniDef.m2Thresh : m2Thresh_off;
1177 int m2CountThr = on ?
1178 aniState->iniDef.m2CountThr : m2CountThr_off;
1179 int m2CountThrLow = on ?
1180 aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
1181 int m1ThreshLowExt = on ?
1182 aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
1183 int m2ThreshLowExt = on ?
1184 aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
1185 int m1ThreshExt = on ?
1186 aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
1187 int m2ThreshExt = on ?
1188 aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
1189
1190 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1191 AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
1192 m1ThreshLow);
1193 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1194 AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
1195 m2ThreshLow);
1196 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1197 AR_PHY_SFCORR_M1_THRESH, m1Thresh);
1198 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1199 AR_PHY_SFCORR_M2_THRESH, m2Thresh);
1200 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1201 AR_PHY_SFCORR_M2COUNT_THR, m2CountThr);
1202 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1203 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
1204 m2CountThrLow);
1205
1206 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1207 AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt);
1208 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1209 AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt);
1210 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1211 AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt);
1212 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1213 AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt);
1214
1215 if (on)
1216 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
1217 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1218 else
1219 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
1220 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1221
1222 if (!on != aniState->ofdmWeakSigDetectOff) {
d2182b69 1223 ath_dbg(common, ANI,
226afe68
JP		 1224 "** ch %d: ofdm weak signal: %s=>%s\n",
1225 chan->channel,
1226 !aniState->ofdmWeakSigDetectOff ?
1227 "on" : "off",
1228 on ? "on" : "off");
e36b27af
LR		 1229 if (on)
1230 ah->stats.ast_ani_ofdmon++;
1231 else
1232 ah->stats.ast_ani_ofdmoff++;
1233 aniState->ofdmWeakSigDetectOff = !on;
1234 }
1235 break;
1236 }
1237 case ATH9K_ANI_FIRSTEP_LEVEL:{
1238 u32 level = param;
1239
1240 if (level >= ARRAY_SIZE(firstep_table)) {
d2182b69 1241 ath_dbg(common, ANI,
226afe68
JP		 1242 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
1243 level, ARRAY_SIZE(firstep_table));
e36b27af
LR		 1244 return false;
1245 }
1246
1247 /*
1248 * make register setting relative to default
1249 * from INI file & cap value
1250 */
1251 value = firstep_table[level] -
1252 firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
1253 aniState->iniDef.firstep;
1254 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1255 value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1256 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1257 value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1258 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1259 AR_PHY_FIND_SIG_FIRSTEP,
1260 value);
1261 /*
1262 * we need to set first step low register too
1263 * make register setting relative to default
1264 * from INI file & cap value
1265 */
1266 value2 = firstep_table[level] -
1267 firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
1268 aniState->iniDef.firstepLow;
1269 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1270 value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1271 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1272 value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1273
1274 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
1275 AR_PHY_FIND_SIG_FIRSTEP_LOW, value2);
1276
1277 if (level != aniState->firstepLevel) {
d2182b69 1278 ath_dbg(common, ANI,
226afe68
JP		 1279 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
1280 chan->channel,
1281 aniState->firstepLevel,
1282 level,
1283 ATH9K_ANI_FIRSTEP_LVL_NEW,
1284 value,
1285 aniState->iniDef.firstep);
d2182b69 1286 ath_dbg(common, ANI,
226afe68
JP		 1287 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
1288 chan->channel,
1289 aniState->firstepLevel,
1290 level,
1291 ATH9K_ANI_FIRSTEP_LVL_NEW,
1292 value2,
1293 aniState->iniDef.firstepLow);
e36b27af
LR		 1294 if (level > aniState->firstepLevel)
1295 ah->stats.ast_ani_stepup++;
1296 else if (level < aniState->firstepLevel)
1297 ah->stats.ast_ani_stepdown++;
1298 aniState->firstepLevel = level;
1299 }
1300 break;
1301 }
1302 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
1303 u32 level = param;
1304
1305 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
d2182b69 1306 ath_dbg(common, ANI,
226afe68
JP		 1307 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
1308 level, ARRAY_SIZE(cycpwrThr1_table));
e36b27af
LR		 1309 return false;
1310 }
1311 /*
1312 * make register setting relative to default
1313 * from INI file & cap value
1314 */
1315 value = cycpwrThr1_table[level] -
1316 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
1317 aniState->iniDef.cycpwrThr1;
1318 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1319 value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1320 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1321 value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1322 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
1323 AR_PHY_TIMING5_CYCPWR_THR1,
1324 value);
1325
1326 /*
1327 * set AR_PHY_EXT_CCA for extension channel
1328 * make register setting relative to default
1329 * from INI file & cap value
1330 */
1331 value2 = cycpwrThr1_table[level] -
1332 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
1333 aniState->iniDef.cycpwrThr1Ext;
1334 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1335 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1336 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1337 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1338 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
1339 AR_PHY_EXT_TIMING5_CYCPWR_THR1, value2);
1340
1341 if (level != aniState->spurImmunityLevel) {
d2182b69 1342 ath_dbg(common, ANI,
226afe68
JP		 1343 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
1344 chan->channel,
1345 aniState->spurImmunityLevel,
1346 level,
1347 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
1348 value,
1349 aniState->iniDef.cycpwrThr1);
d2182b69 1350 ath_dbg(common, ANI,
226afe68
JP		 1351 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
1352 chan->channel,
1353 aniState->spurImmunityLevel,
1354 level,
1355 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
1356 value2,
1357 aniState->iniDef.cycpwrThr1Ext);
e36b27af
LR		 1358 if (level > aniState->spurImmunityLevel)
1359 ah->stats.ast_ani_spurup++;
1360 else if (level < aniState->spurImmunityLevel)
1361 ah->stats.ast_ani_spurdown++;
1362 aniState->spurImmunityLevel = level;
1363 }
1364 break;
1365 }
1366 case ATH9K_ANI_MRC_CCK:
1367 /*
1368 * You should not see this as AR5008, AR9001, AR9002
1369 * does not have hardware support for MRC CCK.
1370 */
1371 WARN_ON(1);
1372 break;
1373 case ATH9K_ANI_PRESENT:
1374 break;
1375 default:
d2182b69 1376 ath_dbg(common, ANI, "invalid cmd %u\n", cmd);
e36b27af
LR		 1377 return false;
1378 }
1379
d2182b69 1380 ath_dbg(common, ANI,
226afe68
JP		 1381 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1382 aniState->spurImmunityLevel,
1383 !aniState->ofdmWeakSigDetectOff ? "on" : "off",
1384 aniState->firstepLevel,
1385 !aniState->mrcCCKOff ? "on" : "off",
1386 aniState->listenTime,
1387 aniState->ofdmPhyErrCount,
1388 aniState->cckPhyErrCount);
e36b27af
LR		 1389 return true;
1390}
1391
641d9921
FF		 1392static void ar5008_hw_do_getnf(struct ath_hw *ah,
1393 int16_t nfarray[NUM_NF_READINGS])
1394{
641d9921
FF		 1395 int16_t nf;
1396
1397 nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
7919a57b 1398 nfarray[0] = sign_extend32(nf, 8);
641d9921
FF		 1399
1400 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR);
7919a57b 1401 nfarray[1] = sign_extend32(nf, 8);
641d9921
FF		 1402
1403 nf = MS(REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR);
7919a57b 1404 nfarray[2] = sign_extend32(nf, 8);
641d9921 1405
866b7780
FF		 1406 if (!IS_CHAN_HT40(ah->curchan))
1407 return;
1408
641d9921 1409 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);
7919a57b 1410 nfarray[3] = sign_extend32(nf, 8);
641d9921
FF		 1411
1412 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR);
7919a57b 1413 nfarray[4] = sign_extend32(nf, 8);
641d9921
FF		 1414
1415 nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR);
7919a57b 1416 nfarray[5] = sign_extend32(nf, 8);
641d9921
FF		 1417}
1418
e36b27af
LR		 1419/*
1420 * Initialize the ANI register values with default (ini) values.
1421 * This routine is called during a (full) hardware reset after
1422 * all the registers are initialised from the INI.
1423 */
1424static void ar5008_hw_ani_cache_ini_regs(struct ath_hw *ah)
1425{
e36b27af
LR		 1426 struct ath_common *common = ath9k_hw_common(ah);
1427 struct ath9k_channel *chan = ah->curchan;
093115b7 1428 struct ar5416AniState *aniState = &chan->ani;
e36b27af 1429 struct ath9k_ani_default *iniDef;
e36b27af
LR		 1430 u32 val;
1431
e36b27af
LR		 1432 iniDef = &aniState->iniDef;
1433
d2182b69 1434 ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
226afe68
JP		 1435 ah->hw_version.macVersion,
1436 ah->hw_version.macRev,
1437 ah->opmode,
1438 chan->channel,
1439 chan->channelFlags);
e36b27af
LR		 1440
1441 val = REG_READ(ah, AR_PHY_SFCORR);
1442 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1443 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1444 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1445
1446 val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1447 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1448 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1449 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1450
1451 val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1452 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1453 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1454 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1455 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1456 iniDef->firstep = REG_READ_FIELD(ah,
1457 AR_PHY_FIND_SIG,
1458 AR_PHY_FIND_SIG_FIRSTEP);
1459 iniDef->firstepLow = REG_READ_FIELD(ah,
1460 AR_PHY_FIND_SIG_LOW,
1461 AR_PHY_FIND_SIG_FIRSTEP_LOW);
1462 iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1463 AR_PHY_TIMING5,
1464 AR_PHY_TIMING5_CYCPWR_THR1);
1465 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1466 AR_PHY_EXT_CCA,
1467 AR_PHY_EXT_TIMING5_CYCPWR_THR1);
1468
1469 /* these levels just got reset to defaults by the INI */
1470 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL_NEW;
1471 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW;
1472 aniState->ofdmWeakSigDetectOff = !ATH9K_ANI_USE_OFDM_WEAK_SIG;
1473 aniState->mrcCCKOff = true; /* not available on pre AR9003 */
e36b27af
LR		 1474}
1475
f2552e28
FF		 1476static void ar5008_hw_set_nf_limits(struct ath_hw *ah)
1477{
1478 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ;
1479 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ;
1480 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ;
1481 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ;
1482 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ;
1483 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ;
1484}
e36b27af 1485
4e8c14e9
FF		 1486static void ar5008_hw_set_radar_params(struct ath_hw *ah,
1487 struct ath_hw_radar_conf *conf)
1488{
1489 u32 radar_0 = 0, radar_1 = 0;
1490
1491 if (!conf) {
1492 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1493 return;
1494 }
1495
1496 radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
1497 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1498 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1499 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1500 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1501 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1502
1503 radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1504 radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1505 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1506 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
1507 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1508
1509 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1510 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1511 if (conf->ext_channel)
1512 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1513 else
1514 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1515}
1516
c5d0855a
FF		 1517static void ar5008_hw_set_radar_conf(struct ath_hw *ah)
1518{
1519 struct ath_hw_radar_conf *conf = &ah->radar_conf;
1520
1521 conf->fir_power = -33;
1522 conf->radar_rssi = 20;
1523 conf->pulse_height = 10;
1524 conf->pulse_rssi = 24;
1525 conf->pulse_inband = 15;
1526 conf->pulse_maxlen = 255;
1527 conf->pulse_inband_step = 12;
1528 conf->radar_inband = 8;
1529}
1530
8fe65368
LR		 1531void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
1532{
1533 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
07b2fa5a 1534 static const u32 ar5416_cca_regs[6] = {
bbacee13
FF		 1535 AR_PHY_CCA,
1536 AR_PHY_CH1_CCA,
1537 AR_PHY_CH2_CCA,
1538 AR_PHY_EXT_CCA,
1539 AR_PHY_CH1_EXT_CCA,
1540 AR_PHY_CH2_EXT_CCA
1541 };
8fe65368
LR		 1542
1543 priv_ops->rf_set_freq = ar5008_hw_set_channel;
1544 priv_ops->spur_mitigate_freq = ar5008_hw_spur_mitigate;
1545
1546 priv_ops->rf_alloc_ext_banks = ar5008_hw_rf_alloc_ext_banks;
1547 priv_ops->rf_free_ext_banks = ar5008_hw_rf_free_ext_banks;
1548 priv_ops->set_rf_regs = ar5008_hw_set_rf_regs;
1549 priv_ops->set_channel_regs = ar5008_hw_set_channel_regs;
1550 priv_ops->init_bb = ar5008_hw_init_bb;
1551 priv_ops->process_ini = ar5008_hw_process_ini;
1552 priv_ops->set_rfmode = ar5008_hw_set_rfmode;
1553 priv_ops->mark_phy_inactive = ar5008_hw_mark_phy_inactive;
1554 priv_ops->set_delta_slope = ar5008_hw_set_delta_slope;
1555 priv_ops->rfbus_req = ar5008_hw_rfbus_req;
1556 priv_ops->rfbus_done = ar5008_hw_rfbus_done;
8fe65368 1557 priv_ops->restore_chainmask = ar5008_restore_chainmask;
641d9921 1558 priv_ops->do_getnf = ar5008_hw_do_getnf;
4e8c14e9 1559 priv_ops->set_radar_params = ar5008_hw_set_radar_params;
64773964 1560
e36b27af
LR		 1561 if (modparam_force_new_ani) {
1562 priv_ops->ani_control = ar5008_hw_ani_control_new;
1563 priv_ops->ani_cache_ini_regs = ar5008_hw_ani_cache_ini_regs;
1564 } else
1565 priv_ops->ani_control = ar5008_hw_ani_control_old;
1566
491b209d 1567 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
64773964
LR		 1568 priv_ops->compute_pll_control = ar9160_hw_compute_pll_control;
1569 else
1570 priv_ops->compute_pll_control = ar5008_hw_compute_pll_control;
f2552e28
FF		 1571
1572 ar5008_hw_set_nf_limits(ah);
c5d0855a 1573 ar5008_hw_set_radar_conf(ah);
bbacee13 1574 memcpy(ah->nf_regs, ar5416_cca_regs, sizeof(ah->nf_regs));
8fe65368 1575}
Linux 6.x block layer and io_uring tree(s)