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ath9k_hw: set 5 GHz half/quarter channels on AR9002 using fractional mode
[linux-2.6-block.git] / drivers / net / wireless / ath / ath9k / ar5008_phy.c
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
cfe8cba9 17#include "hw.h"
8fe65368
LR		 18#include "hw-ops.h"
19#include "../regd.h"
20#include "ar9002_phy.h"
e16393bb 21
e36b27af
LR		 22/* All code below is for AR5008, AR9001, AR9002 */
23
24static const int firstep_table[] =
25/* level: 0 1 2 3 4 5 6 7 8 */
26 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */
27
28static const int cycpwrThr1_table[] =
29/* level: 0 1 2 3 4 5 6 7 8 */
30 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */
31
32/*
33 * register values to turn OFDM weak signal detection OFF
34 */
35static const int m1ThreshLow_off = 127;
36static const int m2ThreshLow_off = 127;
37static const int m1Thresh_off = 127;
38static const int m2Thresh_off = 127;
39static const int m2CountThr_off = 31;
40static const int m2CountThrLow_off = 63;
41static const int m1ThreshLowExt_off = 127;
42static const int m2ThreshLowExt_off = 127;
43static const int m1ThreshExt_off = 127;
44static const int m2ThreshExt_off = 127;
45
e16393bb 46
a9b6b256
FF		 47static void ar5008_rf_bank_setup(u32 *bank, struct ar5416IniArray *array,
48 int col)
49{
50 int i;
51
52 for (i = 0; i < array->ia_rows; i++)
53 bank[i] = INI_RA(array, i, col);
54}
55
56
57#define REG_WRITE_RF_ARRAY(iniarray, regData, regWr) \
58 ar5008_write_rf_array(ah, iniarray, regData, &(regWr))
59
60static void ar5008_write_rf_array(struct ath_hw *ah, struct ar5416IniArray *array,
61 u32 *data, unsigned int *writecnt)
62{
63 int r;
64
65 ENABLE_REGWRITE_BUFFER(ah);
66
67 for (r = 0; r < array->ia_rows; r++) {
68 REG_WRITE(ah, INI_RA(array, r, 0), data[r]);
69 DO_DELAY(*writecnt);
70 }
71
72 REGWRITE_BUFFER_FLUSH(ah);
73}
74
ddcd4c08 75/**
8fe65368 76 * ar5008_hw_phy_modify_rx_buffer() - perform analog swizzling of parameters
ddcd4c08
LR		 77 * @rfbuf:
78 * @reg32:
79 * @numBits:
80 * @firstBit:
81 * @column:
82 *
83 * Performs analog "swizzling" of parameters into their location.
84 * Used on external AR2133/AR5133 radios.
85 */
8fe65368
LR		 86static void ar5008_hw_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
87 u32 numBits, u32 firstBit,
88 u32 column)
ddcd4c08
LR		 89{
90 u32 tmp32, mask, arrayEntry, lastBit;
91 int32_t bitPosition, bitsLeft;
92
93 tmp32 = ath9k_hw_reverse_bits(reg32, numBits);
94 arrayEntry = (firstBit - 1) / 8;
95 bitPosition = (firstBit - 1) % 8;
96 bitsLeft = numBits;
97 while (bitsLeft > 0) {
98 lastBit = (bitPosition + bitsLeft > 8) ?
99 8 : bitPosition + bitsLeft;
100 mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) <<
101 (column * 8);
102 rfBuf[arrayEntry] &= ~mask;
103 rfBuf[arrayEntry] |= ((tmp32 << bitPosition) <<
104 (column * 8)) & mask;
105 bitsLeft -= 8 - bitPosition;
106 tmp32 = tmp32 >> (8 - bitPosition);
107 bitPosition = 0;
108 arrayEntry++;
109 }
110}
111
a7765828
LR		 112/*
113 * Fix on 2.4 GHz band for orientation sensitivity issue by increasing
114 * rf_pwd_icsyndiv.
115 *
116 * Theoretical Rules:
117 * if 2 GHz band
118 * if forceBiasAuto
119 * if synth_freq < 2412
120 * bias = 0
121 * else if 2412 <= synth_freq <= 2422
122 * bias = 1
123 * else // synth_freq > 2422
124 * bias = 2
125 * else if forceBias > 0
126 * bias = forceBias & 7
127 * else
128 * no change, use value from ini file
129 * else
130 * no change, invalid band
131 *
132 * 1st Mod:
133 * 2422 also uses value of 2
134 * <approved>
135 *
136 * 2nd Mod:
137 * Less than 2412 uses value of 0, 2412 and above uses value of 2
138 */
8fe65368 139static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq)
a7765828
LR		 140{
141 struct ath_common *common = ath9k_hw_common(ah);
142 u32 tmp_reg;
143 int reg_writes = 0;
144 u32 new_bias = 0;
145
8fe65368 146 if (!AR_SREV_5416(ah) || synth_freq >= 3000)
a7765828 147 return;
a7765828 148
7a37081e 149 BUG_ON(AR_SREV_9280_20_OR_LATER(ah));
a7765828
LR		 150
151 if (synth_freq < 2412)
152 new_bias = 0;
153 else if (synth_freq < 2422)
154 new_bias = 1;
155 else
156 new_bias = 2;
157
158 /* pre-reverse this field */
159 tmp_reg = ath9k_hw_reverse_bits(new_bias, 3);
160
226afe68
JP		 161 ath_dbg(common, ATH_DBG_CONFIG, "Force rf_pwd_icsyndiv to %1d on %4d\n",
162 new_bias, synth_freq);
a7765828
LR		 163
164 /* swizzle rf_pwd_icsyndiv */
8fe65368 165 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3);
a7765828
LR		 166
167 /* write Bank 6 with new params */
168 REG_WRITE_RF_ARRAY(&ah->iniBank6, ah->analogBank6Data, reg_writes);
169}
170
e16393bb 171/**
8fe65368 172 * ar5008_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios
25985edc 173 * @ah: atheros hardware structure
e16393bb
LR		 174 * @chan:
175 *
176 * For the external AR2133/AR5133 radios, takes the MHz channel value and set
177 * the channel value. Assumes writes enabled to analog bus and bank6 register
178 * cache in ah->analogBank6Data.
179 */
8fe65368 180static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
e16393bb
LR		 181{
182 struct ath_common *common = ath9k_hw_common(ah);
183 u32 channelSel = 0;
184 u32 bModeSynth = 0;
185 u32 aModeRefSel = 0;
186 u32 reg32 = 0;
187 u16 freq;
188 struct chan_centers centers;
189
190 ath9k_hw_get_channel_centers(ah, chan, &centers);
191 freq = centers.synth_center;
192
193 if (freq < 4800) {
194 u32 txctl;
195
196 if (((freq - 2192) % 5) == 0) {
197 channelSel = ((freq - 672) * 2 - 3040) / 10;
198 bModeSynth = 0;
199 } else if (((freq - 2224) % 5) == 0) {
200 channelSel = ((freq - 704) * 2 - 3040) / 10;
201 bModeSynth = 1;
202 } else {
3800276a 203 ath_err(common, "Invalid channel %u MHz\n", freq);
e16393bb
LR		 204 return -EINVAL;
205 }
206
207 channelSel = (channelSel << 2) & 0xff;
208 channelSel = ath9k_hw_reverse_bits(channelSel, 8);
209
210 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
211 if (freq == 2484) {
212
213 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
214 txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
215 } else {
216 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
217 txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
218 }
219
220 } else if ((freq % 20) == 0 && freq >= 5120) {
221 channelSel =
222 ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8);
223 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
224 } else if ((freq % 10) == 0) {
225 channelSel =
226 ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8);
227 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
228 aModeRefSel = ath9k_hw_reverse_bits(2, 2);
229 else
230 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
231 } else if ((freq % 5) == 0) {
232 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
233 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
234 } else {
3800276a 235 ath_err(common, "Invalid channel %u MHz\n", freq);
e16393bb
LR		 236 return -EINVAL;
237 }
238
8fe65368 239 ar5008_hw_force_bias(ah, freq);
a7765828 240
e16393bb
LR		 241 reg32 =
242 (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
243 (1 << 5) | 0x1;
244
245 REG_WRITE(ah, AR_PHY(0x37), reg32);
246
247 ah->curchan = chan;
248 ah->curchan_rad_index = -1;
249
250 return 0;
251}
252
253/**
8fe65368 254 * ar5008_hw_spur_mitigate - convert baseband spur frequency for external radios
e16393bb
LR		 255 * @ah: atheros hardware structure
256 * @chan:
257 *
258 * For non single-chip solutions. Converts to baseband spur frequency given the
259 * input channel frequency and compute register settings below.
260 */
8fe65368
LR		 261static void ar5008_hw_spur_mitigate(struct ath_hw *ah,
262 struct ath9k_channel *chan)
e16393bb
LR		 263{
264 int bb_spur = AR_NO_SPUR;
265 int bin, cur_bin;
266 int spur_freq_sd;
267 int spur_delta_phase;
268 int denominator;
269 int upper, lower, cur_vit_mask;
270 int tmp, new;
271 int i;
07b2fa5a
JP		 272 static int pilot_mask_reg[4] = {
273 AR_PHY_TIMING7, AR_PHY_TIMING8,
274 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
e16393bb 275 };
07b2fa5a
JP		 276 static int chan_mask_reg[4] = {
277 AR_PHY_TIMING9, AR_PHY_TIMING10,
278 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
e16393bb 279 };
07b2fa5a 280 static int inc[4] = { 0, 100, 0, 0 };
e16393bb
LR		 281
282 int8_t mask_m[123];
283 int8_t mask_p[123];
284 int8_t mask_amt;
285 int tmp_mask;
286 int cur_bb_spur;
287 bool is2GHz = IS_CHAN_2GHZ(chan);
288
289 memset(&mask_m, 0, sizeof(int8_t) * 123);
290 memset(&mask_p, 0, sizeof(int8_t) * 123);
291
292 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
293 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
294 if (AR_NO_SPUR == cur_bb_spur)
295 break;
296 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
297 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
298 bb_spur = cur_bb_spur;
299 break;
300 }
301 }
302
303 if (AR_NO_SPUR == bb_spur)
304 return;
305
306 bin = bb_spur * 32;
307
308 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
309 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
310 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
311 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
312 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
313
314 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
315
316 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
317 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
318 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
319 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
320 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
321 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
322
323 spur_delta_phase = ((bb_spur * 524288) / 100) &
324 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
325
326 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
327 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
328
329 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
330 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
331 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
332 REG_WRITE(ah, AR_PHY_TIMING11, new);
333
334 cur_bin = -6000;
335 upper = bin + 100;
336 lower = bin - 100;
337
338 for (i = 0; i < 4; i++) {
339 int pilot_mask = 0;
340 int chan_mask = 0;
341 int bp = 0;
342 for (bp = 0; bp < 30; bp++) {
343 if ((cur_bin > lower) && (cur_bin < upper)) {
344 pilot_mask = pilot_mask | 0x1 << bp;
345 chan_mask = chan_mask | 0x1 << bp;
346 }
347 cur_bin += 100;
348 }
349 cur_bin += inc[i];
350 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
351 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
352 }
353
354 cur_vit_mask = 6100;
355 upper = bin + 120;
356 lower = bin - 120;
357
358 for (i = 0; i < 123; i++) {
359 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
360
361 /* workaround for gcc bug #37014 */
362 volatile int tmp_v = abs(cur_vit_mask - bin);
363
364 if (tmp_v < 75)
365 mask_amt = 1;
366 else
367 mask_amt = 0;
368 if (cur_vit_mask < 0)
369 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
370 else
371 mask_p[cur_vit_mask / 100] = mask_amt;
372 }
373 cur_vit_mask -= 100;
374 }
375
376 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
377 | (mask_m[48] << 26) | (mask_m[49] << 24)
378 | (mask_m[50] << 22) | (mask_m[51] << 20)
379 | (mask_m[52] << 18) | (mask_m[53] << 16)
380 | (mask_m[54] << 14) | (mask_m[55] << 12)
381 | (mask_m[56] << 10) | (mask_m[57] << 8)
382 | (mask_m[58] << 6) | (mask_m[59] << 4)
383 | (mask_m[60] << 2) | (mask_m[61] << 0);
384 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
385 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
386
387 tmp_mask = (mask_m[31] << 28)
388 | (mask_m[32] << 26) | (mask_m[33] << 24)
389 | (mask_m[34] << 22) | (mask_m[35] << 20)
390 | (mask_m[36] << 18) | (mask_m[37] << 16)
391 | (mask_m[48] << 14) | (mask_m[39] << 12)
392 | (mask_m[40] << 10) | (mask_m[41] << 8)
393 | (mask_m[42] << 6) | (mask_m[43] << 4)
394 | (mask_m[44] << 2) | (mask_m[45] << 0);
395 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
396 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
397
398 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
399 | (mask_m[18] << 26) | (mask_m[18] << 24)
400 | (mask_m[20] << 22) | (mask_m[20] << 20)
401 | (mask_m[22] << 18) | (mask_m[22] << 16)
402 | (mask_m[24] << 14) | (mask_m[24] << 12)
403 | (mask_m[25] << 10) | (mask_m[26] << 8)
404 | (mask_m[27] << 6) | (mask_m[28] << 4)
405 | (mask_m[29] << 2) | (mask_m[30] << 0);
406 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
407 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
408
409 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
410 | (mask_m[2] << 26) | (mask_m[3] << 24)
411 | (mask_m[4] << 22) | (mask_m[5] << 20)
412 | (mask_m[6] << 18) | (mask_m[7] << 16)
413 | (mask_m[8] << 14) | (mask_m[9] << 12)
414 | (mask_m[10] << 10) | (mask_m[11] << 8)
415 | (mask_m[12] << 6) | (mask_m[13] << 4)
416 | (mask_m[14] << 2) | (mask_m[15] << 0);
417 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
418 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
419
420 tmp_mask = (mask_p[15] << 28)
421 | (mask_p[14] << 26) | (mask_p[13] << 24)
422 | (mask_p[12] << 22) | (mask_p[11] << 20)
423 | (mask_p[10] << 18) | (mask_p[9] << 16)
424 | (mask_p[8] << 14) | (mask_p[7] << 12)
425 | (mask_p[6] << 10) | (mask_p[5] << 8)
426 | (mask_p[4] << 6) | (mask_p[3] << 4)
427 | (mask_p[2] << 2) | (mask_p[1] << 0);
428 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
429 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
430
431 tmp_mask = (mask_p[30] << 28)
432 | (mask_p[29] << 26) | (mask_p[28] << 24)
433 | (mask_p[27] << 22) | (mask_p[26] << 20)
434 | (mask_p[25] << 18) | (mask_p[24] << 16)
435 | (mask_p[23] << 14) | (mask_p[22] << 12)
436 | (mask_p[21] << 10) | (mask_p[20] << 8)
437 | (mask_p[19] << 6) | (mask_p[18] << 4)
438 | (mask_p[17] << 2) | (mask_p[16] << 0);
439 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
440 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
441
442 tmp_mask = (mask_p[45] << 28)
443 | (mask_p[44] << 26) | (mask_p[43] << 24)
444 | (mask_p[42] << 22) | (mask_p[41] << 20)
445 | (mask_p[40] << 18) | (mask_p[39] << 16)
446 | (mask_p[38] << 14) | (mask_p[37] << 12)
447 | (mask_p[36] << 10) | (mask_p[35] << 8)
448 | (mask_p[34] << 6) | (mask_p[33] << 4)
449 | (mask_p[32] << 2) | (mask_p[31] << 0);
450 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
451 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
452
453 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
454 | (mask_p[59] << 26) | (mask_p[58] << 24)
455 | (mask_p[57] << 22) | (mask_p[56] << 20)
456 | (mask_p[55] << 18) | (mask_p[54] << 16)
457 | (mask_p[53] << 14) | (mask_p[52] << 12)
458 | (mask_p[51] << 10) | (mask_p[50] << 8)
459 | (mask_p[49] << 6) | (mask_p[48] << 4)
460 | (mask_p[47] << 2) | (mask_p[46] << 0);
461 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
462 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
463}
464
465/**
8fe65368 466 * ar5008_hw_rf_alloc_ext_banks - allocates banks for external radio programming
e16393bb
LR		 467 * @ah: atheros hardware structure
468 *
469 * Only required for older devices with external AR2133/AR5133 radios.
470 */
8fe65368 471static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah)
e16393bb
LR		 472{
473#define ATH_ALLOC_BANK(bank, size) do { \
474 bank = kzalloc((sizeof(u32) * size), GFP_KERNEL); \
475 if (!bank) { \
3800276a 476 ath_err(common, "Cannot allocate RF banks\n"); \
e16393bb
LR		 477 return -ENOMEM; \
478 } \
479 } while (0);
480
481 struct ath_common *common = ath9k_hw_common(ah);
482
7a37081e 483 BUG_ON(AR_SREV_9280_20_OR_LATER(ah));
e16393bb
LR		 484
485 ATH_ALLOC_BANK(ah->analogBank0Data, ah->iniBank0.ia_rows);
486 ATH_ALLOC_BANK(ah->analogBank1Data, ah->iniBank1.ia_rows);
487 ATH_ALLOC_BANK(ah->analogBank2Data, ah->iniBank2.ia_rows);
488 ATH_ALLOC_BANK(ah->analogBank3Data, ah->iniBank3.ia_rows);
489 ATH_ALLOC_BANK(ah->analogBank6Data, ah->iniBank6.ia_rows);
490 ATH_ALLOC_BANK(ah->analogBank6TPCData, ah->iniBank6TPC.ia_rows);
491 ATH_ALLOC_BANK(ah->analogBank7Data, ah->iniBank7.ia_rows);
492 ATH_ALLOC_BANK(ah->addac5416_21,
493 ah->iniAddac.ia_rows * ah->iniAddac.ia_columns);
494 ATH_ALLOC_BANK(ah->bank6Temp, ah->iniBank6.ia_rows);
495
496 return 0;
497#undef ATH_ALLOC_BANK
498}
499
500
501/**
8fe65368 502 * ar5008_hw_rf_free_ext_banks - Free memory for analog bank scratch buffers
e16393bb
LR		 503 * @ah: atheros hardware struture
504 * For the external AR2133/AR5133 radios banks.
505 */
8fe65368 506static void ar5008_hw_rf_free_ext_banks(struct ath_hw *ah)
e16393bb
LR		 507{
508#define ATH_FREE_BANK(bank) do { \
509 kfree(bank); \
510 bank = NULL; \
511 } while (0);
512
7a37081e 513 BUG_ON(AR_SREV_9280_20_OR_LATER(ah));
e16393bb
LR		 514
515 ATH_FREE_BANK(ah->analogBank0Data);
516 ATH_FREE_BANK(ah->analogBank1Data);
517 ATH_FREE_BANK(ah->analogBank2Data);
518 ATH_FREE_BANK(ah->analogBank3Data);
519 ATH_FREE_BANK(ah->analogBank6Data);
520 ATH_FREE_BANK(ah->analogBank6TPCData);
521 ATH_FREE_BANK(ah->analogBank7Data);
522 ATH_FREE_BANK(ah->addac5416_21);
523 ATH_FREE_BANK(ah->bank6Temp);
524
525#undef ATH_FREE_BANK
526}
527
131d1d03 528/* *
8fe65368 529 * ar5008_hw_set_rf_regs - programs rf registers based on EEPROM
131d1d03
LR		 530 * @ah: atheros hardware structure
531 * @chan:
532 * @modesIndex:
533 *
534 * Used for the external AR2133/AR5133 radios.
535 *
536 * Reads the EEPROM header info from the device structure and programs
537 * all rf registers. This routine requires access to the analog
538 * rf device. This is not required for single-chip devices.
539 */
8fe65368
LR		 540static bool ar5008_hw_set_rf_regs(struct ath_hw *ah,
541 struct ath9k_channel *chan,
542 u16 modesIndex)
f078f209 543{
f078f209
LR		 544 u32 eepMinorRev;
545 u32 ob5GHz = 0, db5GHz = 0;
546 u32 ob2GHz = 0, db2GHz = 0;
547 int regWrites = 0;
548
131d1d03
LR		 549 /*
550 * Software does not need to program bank data
551 * for single chip devices, that is AR9280 or anything
552 * after that.
553 */
7a37081e 554 if (AR_SREV_9280_20_OR_LATER(ah))
f078f209
LR		 555 return true;
556
131d1d03 557 /* Setup rf parameters */
f74df6fb 558 eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV);
f078f209 559
131d1d03 560 /* Setup Bank 0 Write */
a9b6b256 561 ar5008_rf_bank_setup(ah->analogBank0Data, &ah->iniBank0, 1);
f078f209 562
131d1d03 563 /* Setup Bank 1 Write */
a9b6b256 564 ar5008_rf_bank_setup(ah->analogBank1Data, &ah->iniBank1, 1);
f078f209 565
131d1d03 566 /* Setup Bank 2 Write */
a9b6b256 567 ar5008_rf_bank_setup(ah->analogBank2Data, &ah->iniBank2, 1);
f078f209 568
131d1d03 569 /* Setup Bank 6 Write */
a9b6b256 570 ar5008_rf_bank_setup(ah->analogBank3Data, &ah->iniBank3,
f078f209
LR		 571 modesIndex);
572 {
573 int i;
2660b81a
S		 574 for (i = 0; i < ah->iniBank6TPC.ia_rows; i++) {
575 ah->analogBank6Data[i] =
576 INI_RA(&ah->iniBank6TPC, i, modesIndex);
f078f209
LR		 577 }
578 }
579
131d1d03 580 /* Only the 5 or 2 GHz OB/DB need to be set for a mode */
f078f209
LR		 581 if (eepMinorRev >= 2) {
582 if (IS_CHAN_2GHZ(chan)) {
f74df6fb
S		 583 ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2);
584 db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2);
8fe65368
LR		 585 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
586 ob2GHz, 3, 197, 0);
587 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
588 db2GHz, 3, 194, 0);
f078f209 589 } else {
f74df6fb
S		 590 ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5);
591 db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5);
8fe65368
LR		 592 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
593 ob5GHz, 3, 203, 0);
594 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
595 db5GHz, 3, 200, 0);
f078f209
LR		 596 }
597 }
598
131d1d03 599 /* Setup Bank 7 Setup */
a9b6b256 600 ar5008_rf_bank_setup(ah->analogBank7Data, &ah->iniBank7, 1);
f078f209 601
131d1d03 602 /* Write Analog registers */
2660b81a 603 REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data,
f078f209 604 regWrites);
2660b81a 605 REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data,
f078f209 606 regWrites);
2660b81a 607 REG_WRITE_RF_ARRAY(&ah->iniBank2, ah->analogBank2Data,
f078f209 608 regWrites);
2660b81a 609 REG_WRITE_RF_ARRAY(&ah->iniBank3, ah->analogBank3Data,
f078f209 610 regWrites);
2660b81a 611 REG_WRITE_RF_ARRAY(&ah->iniBank6TPC, ah->analogBank6Data,
f078f209 612 regWrites);
2660b81a 613 REG_WRITE_RF_ARRAY(&ah->iniBank7, ah->analogBank7Data,
f078f209
LR		 614 regWrites);
615
616 return true;
617}
8fe65368
LR		 618
619static void ar5008_hw_init_bb(struct ath_hw *ah,
620 struct ath9k_channel *chan)
621{
622 u32 synthDelay;
623
624 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
625 if (IS_CHAN_B(chan))
626 synthDelay = (4 * synthDelay) / 22;
627 else
628 synthDelay /= 10;
629
630 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
631
632 udelay(synthDelay + BASE_ACTIVATE_DELAY);
633}
634
635static void ar5008_hw_init_chain_masks(struct ath_hw *ah)
636{
637 int rx_chainmask, tx_chainmask;
638
639 rx_chainmask = ah->rxchainmask;
640 tx_chainmask = ah->txchainmask;
641
7d0d0df0 642
8fe65368
LR		 643 switch (rx_chainmask) {
644 case 0x5:
645 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
646 AR_PHY_SWAP_ALT_CHAIN);
647 case 0x3:
648 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
649 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
650 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
651 break;
652 }
653 case 0x1:
654 case 0x2:
655 case 0x7:
435c1610 656 ENABLE_REGWRITE_BUFFER(ah);
8fe65368
LR		 657 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
658 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
659 break;
660 default:
435c1610 661 ENABLE_REGWRITE_BUFFER(ah);
8fe65368
LR		 662 break;
663 }
664
665 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
7d0d0df0
S		 666
667 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 668
8fe65368
LR		 669 if (tx_chainmask == 0x5) {
670 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
671 AR_PHY_SWAP_ALT_CHAIN);
672 }
673 if (AR_SREV_9100(ah))
674 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
675 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
676}
677
678static void ar5008_hw_override_ini(struct ath_hw *ah,
679 struct ath9k_channel *chan)
680{
681 u32 val;
682
683 /*
684 * Set the RX_ABORT and RX_DIS and clear if off only after
685 * RXE is set for MAC. This prevents frames with corrupted
686 * descriptor status.
687 */
688 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
689
7a37081e 690 if (AR_SREV_9280_20_OR_LATER(ah)) {
8fe65368
LR		 691 val = REG_READ(ah, AR_PCU_MISC_MODE2);
692
693 if (!AR_SREV_9271(ah))
694 val &= ~AR_PCU_MISC_MODE2_HWWAR1;
695
a42acef0 696 if (AR_SREV_9287_11_OR_LATER(ah))
8fe65368
LR		 697 val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
698
699 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
700 }
701
702 if (!AR_SREV_5416_20_OR_LATER(ah) ||
7a37081e 703 AR_SREV_9280_20_OR_LATER(ah))
8fe65368
LR		 704 return;
705 /*
706 * Disable BB clock gating
707 * Necessary to avoid issues on AR5416 2.0
708 */
709 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
710
711 /*
712 * Disable RIFS search on some chips to avoid baseband
713 * hang issues.
714 */
715 if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) {
716 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
717 val &= ~AR_PHY_RIFS_INIT_DELAY;
718 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
719 }
720}
721
722static void ar5008_hw_set_channel_regs(struct ath_hw *ah,
723 struct ath9k_channel *chan)
724{
725 u32 phymode;
726 u32 enableDacFifo = 0;
727
e17f83ea 728 if (AR_SREV_9285_12_OR_LATER(ah))
8fe65368
LR		 729 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
730 AR_PHY_FC_ENABLE_DAC_FIFO);
731
732 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
733 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
734
735 if (IS_CHAN_HT40(chan)) {
736 phymode |= AR_PHY_FC_DYN2040_EN;
737
738 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
739 (chan->chanmode == CHANNEL_G_HT40PLUS))
740 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
741
742 }
743 REG_WRITE(ah, AR_PHY_TURBO, phymode);
744
745 ath9k_hw_set11nmac2040(ah);
746
7d0d0df0
S		 747 ENABLE_REGWRITE_BUFFER(ah);
748
8fe65368
LR		 749 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
750 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
7d0d0df0
S		 751
752 REGWRITE_BUFFER_FLUSH(ah);
8fe65368
LR		 753}
754
755
756static int ar5008_hw_process_ini(struct ath_hw *ah,
757 struct ath9k_channel *chan)
758{
759 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
e7fc6338 760 struct ath_common *common = ath9k_hw_common(ah);
8fe65368
LR		 761 int i, regWrites = 0;
762 struct ieee80211_channel *channel = chan->chan;
763 u32 modesIndex, freqIndex;
764
765 switch (chan->chanmode) {
766 case CHANNEL_A:
767 case CHANNEL_A_HT20:
768 modesIndex = 1;
769 freqIndex = 1;
770 break;
771 case CHANNEL_A_HT40PLUS:
772 case CHANNEL_A_HT40MINUS:
773 modesIndex = 2;
774 freqIndex = 1;
775 break;
776 case CHANNEL_G:
777 case CHANNEL_G_HT20:
778 case CHANNEL_B:
779 modesIndex = 4;
780 freqIndex = 2;
781 break;
782 case CHANNEL_G_HT40PLUS:
783 case CHANNEL_G_HT40MINUS:
784 modesIndex = 3;
785 freqIndex = 2;
786 break;
787
788 default:
789 return -EINVAL;
790 }
791
8fe65368
LR		 792 /*
793 * Set correct baseband to analog shift setting to
794 * access analog chips.
795 */
796 REG_WRITE(ah, AR_PHY(0), 0x00000007);
797
798 /* Write ADDAC shifts */
799 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
800 ah->eep_ops->set_addac(ah, chan);
801
802 if (AR_SREV_5416_22_OR_LATER(ah)) {
803 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
804 } else {
805 struct ar5416IniArray temp;
806 u32 addacSize =
807 sizeof(u32) * ah->iniAddac.ia_rows *
808 ah->iniAddac.ia_columns;
809
810 /* For AR5416 2.0/2.1 */
811 memcpy(ah->addac5416_21,
812 ah->iniAddac.ia_array, addacSize);
813
814 /* override CLKDRV value at [row, column] = [31, 1] */
815 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
816
817 temp.ia_array = ah->addac5416_21;
818 temp.ia_columns = ah->iniAddac.ia_columns;
819 temp.ia_rows = ah->iniAddac.ia_rows;
820 REG_WRITE_ARRAY(&temp, 1, regWrites);
821 }
822
823 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
824
7d0d0df0
S		 825 ENABLE_REGWRITE_BUFFER(ah);
826
8fe65368
LR		 827 for (i = 0; i < ah->iniModes.ia_rows; i++) {
828 u32 reg = INI_RA(&ah->iniModes, i, 0);
829 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
830
831 if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup)
832 val &= ~AR_AN_TOP2_PWDCLKIND;
833
834 REG_WRITE(ah, reg, val);
835
836 if (reg >= 0x7800 && reg < 0x78a0
e7fc6338
RM		 837 && ah->config.analog_shiftreg
838 && (common->bus_ops->ath_bus_type != ATH_USB)) {
8fe65368
LR		 839 udelay(100);
840 }
841
842 DO_DELAY(regWrites);
843 }
844
7d0d0df0 845 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 846
a42acef0 847 if (AR_SREV_9280(ah) || AR_SREV_9287_11_OR_LATER(ah))
8fe65368
LR		 848 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
849
850 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
a42acef0 851 AR_SREV_9287_11_OR_LATER(ah))
8fe65368
LR		 852 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
853
854 if (AR_SREV_9271_10(ah))
855 REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
856 modesIndex, regWrites);
857
7d0d0df0
S		 858 ENABLE_REGWRITE_BUFFER(ah);
859
8fe65368
LR		 860 /* Write common array parameters */
861 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
862 u32 reg = INI_RA(&ah->iniCommon, i, 0);
863 u32 val = INI_RA(&ah->iniCommon, i, 1);
864
865 REG_WRITE(ah, reg, val);
866
867 if (reg >= 0x7800 && reg < 0x78a0
e7fc6338
RM		 868 && ah->config.analog_shiftreg
869 && (common->bus_ops->ath_bus_type != ATH_USB)) {
8fe65368
LR		 870 udelay(100);
871 }
872
873 DO_DELAY(regWrites);
874 }
875
7d0d0df0 876 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 877
8fe65368
LR		 878 if (AR_SREV_9271(ah)) {
879 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 1)
880 REG_WRITE_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
881 modesIndex, regWrites);
882 else
883 REG_WRITE_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
884 modesIndex, regWrites);
885 }
886
887 REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites);
888
6b42e8d0 889 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) {
8fe65368
LR		 890 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
891 regWrites);
892 }
893
894 ar5008_hw_override_ini(ah, chan);
895 ar5008_hw_set_channel_regs(ah, chan);
896 ar5008_hw_init_chain_masks(ah);
897 ath9k_olc_init(ah);
898
899 /* Set TX power */
900 ah->eep_ops->set_txpower(ah, chan,
901 ath9k_regd_get_ctl(regulatory, chan),
902 channel->max_antenna_gain * 2,
903 channel->max_power * 2,
904 min((u32) MAX_RATE_POWER,
de40f316 905 (u32) regulatory->power_limit), false);
8fe65368
LR		 906
907 /* Write analog registers */
908 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
3800276a 909 ath_err(ath9k_hw_common(ah), "ar5416SetRfRegs failed\n");
8fe65368
LR		 910 return -EIO;
911 }
912
913 return 0;
914}
915
916static void ar5008_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
917{
918 u32 rfMode = 0;
919
920 if (chan == NULL)
921 return;
922
923 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
924 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
925
7a37081e 926 if (!AR_SREV_9280_20_OR_LATER(ah))
8fe65368
LR		 927 rfMode |= (IS_CHAN_5GHZ(chan)) ?
928 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
929
6b42e8d0 930 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
8fe65368
LR		 931 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
932
933 REG_WRITE(ah, AR_PHY_MODE, rfMode);
934}
935
936static void ar5008_hw_mark_phy_inactive(struct ath_hw *ah)
937{
938 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
939}
940
941static void ar5008_hw_set_delta_slope(struct ath_hw *ah,
942 struct ath9k_channel *chan)
943{
944 u32 coef_scaled, ds_coef_exp, ds_coef_man;
945 u32 clockMhzScaled = 0x64000000;
946 struct chan_centers centers;
947
948 if (IS_CHAN_HALF_RATE(chan))
949 clockMhzScaled = clockMhzScaled >> 1;
950 else if (IS_CHAN_QUARTER_RATE(chan))
951 clockMhzScaled = clockMhzScaled >> 2;
952
953 ath9k_hw_get_channel_centers(ah, chan, &centers);
954 coef_scaled = clockMhzScaled / centers.synth_center;
955
956 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
957 &ds_coef_exp);
958
959 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
960 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
961 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
962 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
963
964 coef_scaled = (9 * coef_scaled) / 10;
965
966 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
967 &ds_coef_exp);
968
969 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
970 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
971 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
972 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
973}
974
975static bool ar5008_hw_rfbus_req(struct ath_hw *ah)
976{
977 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
978 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
979 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
980}
981
982static void ar5008_hw_rfbus_done(struct ath_hw *ah)
983{
984 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
985 if (IS_CHAN_B(ah->curchan))
986 synthDelay = (4 * synthDelay) / 22;
987 else
988 synthDelay /= 10;
989
990 udelay(synthDelay + BASE_ACTIVATE_DELAY);
991
992 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
993}
994
8fe65368
LR		 995static void ar5008_restore_chainmask(struct ath_hw *ah)
996{
997 int rx_chainmask = ah->rxchainmask;
998
999 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
1000 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1001 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1002 }
1003}
1004
1005static void ar5008_set_diversity(struct ath_hw *ah, bool value)
1006{
1007 u32 v = REG_READ(ah, AR_PHY_CCK_DETECT);
1008 if (value)
1009 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
1010 else
1011 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
1012 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
1013}
1014
64773964
LR		 1015static u32 ar9100_hw_compute_pll_control(struct ath_hw *ah,
1016 struct ath9k_channel *chan)
1017{
1018 if (chan && IS_CHAN_5GHZ(chan))
1019 return 0x1450;
1020 return 0x1458;
1021}
1022
1023static u32 ar9160_hw_compute_pll_control(struct ath_hw *ah,
1024 struct ath9k_channel *chan)
1025{
1026 u32 pll;
1027
1028 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1029
1030 if (chan && IS_CHAN_HALF_RATE(chan))
1031 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1032 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1033 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1034
1035 if (chan && IS_CHAN_5GHZ(chan))
1036 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1037 else
1038 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1039
1040 return pll;
1041}
1042
1043static u32 ar5008_hw_compute_pll_control(struct ath_hw *ah,
1044 struct ath9k_channel *chan)
1045{
1046 u32 pll;
1047
1048 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1049
1050 if (chan && IS_CHAN_HALF_RATE(chan))
1051 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1052 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1053 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1054
1055 if (chan && IS_CHAN_5GHZ(chan))
1056 pll |= SM(0xa, AR_RTC_PLL_DIV);
1057 else
1058 pll |= SM(0xb, AR_RTC_PLL_DIV);
1059
1060 return pll;
1061}
1062
e36b27af
LR		 1063static bool ar5008_hw_ani_control_old(struct ath_hw *ah,
1064 enum ath9k_ani_cmd cmd,
1065 int param)
c16fcb49 1066{
093115b7 1067 struct ar5416AniState *aniState = &ah->curchan->ani;
c16fcb49
FF		 1068 struct ath_common *common = ath9k_hw_common(ah);
1069
1070 switch (cmd & ah->ani_function) {
1071 case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
1072 u32 level = param;
1073
1074 if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {
226afe68
JP		 1075 ath_dbg(common, ATH_DBG_ANI,
1076 "level out of range (%u > %zu)\n",
1077 level, ARRAY_SIZE(ah->totalSizeDesired));
c16fcb49
FF		 1078 return false;
1079 }
1080
1081 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
1082 AR_PHY_DESIRED_SZ_TOT_DES,
1083 ah->totalSizeDesired[level]);
1084 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
1085 AR_PHY_AGC_CTL1_COARSE_LOW,
1086 ah->coarse_low[level]);
1087 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
1088 AR_PHY_AGC_CTL1_COARSE_HIGH,
1089 ah->coarse_high[level]);
1090 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1091 AR_PHY_FIND_SIG_FIRPWR,
1092 ah->firpwr[level]);
1093
1094 if (level > aniState->noiseImmunityLevel)
1095 ah->stats.ast_ani_niup++;
1096 else if (level < aniState->noiseImmunityLevel)
1097 ah->stats.ast_ani_nidown++;
1098 aniState->noiseImmunityLevel = level;
1099 break;
1100 }
1101 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
07b2fa5a
JP		 1102 static const int m1ThreshLow[] = { 127, 50 };
1103 static const int m2ThreshLow[] = { 127, 40 };
1104 static const int m1Thresh[] = { 127, 0x4d };
1105 static const int m2Thresh[] = { 127, 0x40 };
1106 static const int m2CountThr[] = { 31, 16 };
1107 static const int m2CountThrLow[] = { 63, 48 };
c16fcb49
FF		 1108 u32 on = param ? 1 : 0;
1109
1110 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1111 AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
1112 m1ThreshLow[on]);
1113 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1114 AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
1115 m2ThreshLow[on]);
1116 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1117 AR_PHY_SFCORR_M1_THRESH,
1118 m1Thresh[on]);
1119 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1120 AR_PHY_SFCORR_M2_THRESH,
1121 m2Thresh[on]);
1122 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1123 AR_PHY_SFCORR_M2COUNT_THR,
1124 m2CountThr[on]);
1125 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1126 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
1127 m2CountThrLow[on]);
1128
1129 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1130 AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
1131 m1ThreshLow[on]);
1132 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1133 AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
1134 m2ThreshLow[on]);
1135 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1136 AR_PHY_SFCORR_EXT_M1_THRESH,
1137 m1Thresh[on]);
1138 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1139 AR_PHY_SFCORR_EXT_M2_THRESH,
1140 m2Thresh[on]);
1141
1142 if (on)
1143 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
1144 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1145 else
1146 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
1147 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1148
1149 if (!on != aniState->ofdmWeakSigDetectOff) {
1150 if (on)
1151 ah->stats.ast_ani_ofdmon++;
1152 else
1153 ah->stats.ast_ani_ofdmoff++;
1154 aniState->ofdmWeakSigDetectOff = !on;
1155 }
1156 break;
1157 }
1158 case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
07b2fa5a 1159 static const int weakSigThrCck[] = { 8, 6 };
c16fcb49
FF		 1160 u32 high = param ? 1 : 0;
1161
1162 REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
1163 AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
1164 weakSigThrCck[high]);
1165 if (high != aniState->cckWeakSigThreshold) {
1166 if (high)
1167 ah->stats.ast_ani_cckhigh++;
1168 else
1169 ah->stats.ast_ani_ccklow++;
1170 aniState->cckWeakSigThreshold = high;
1171 }
1172 break;
1173 }
1174 case ATH9K_ANI_FIRSTEP_LEVEL:{
07b2fa5a 1175 static const int firstep[] = { 0, 4, 8 };
c16fcb49
FF		 1176 u32 level = param;
1177
1178 if (level >= ARRAY_SIZE(firstep)) {
226afe68
JP		 1179 ath_dbg(common, ATH_DBG_ANI,
1180 "level out of range (%u > %zu)\n",
1181 level, ARRAY_SIZE(firstep));
c16fcb49
FF		 1182 return false;
1183 }
1184 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1185 AR_PHY_FIND_SIG_FIRSTEP,
1186 firstep[level]);
1187 if (level > aniState->firstepLevel)
1188 ah->stats.ast_ani_stepup++;
1189 else if (level < aniState->firstepLevel)
1190 ah->stats.ast_ani_stepdown++;
1191 aniState->firstepLevel = level;
1192 break;
1193 }
1194 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
07b2fa5a 1195 static const int cycpwrThr1[] = { 2, 4, 6, 8, 10, 12, 14, 16 };
c16fcb49
FF		 1196 u32 level = param;
1197
1198 if (level >= ARRAY_SIZE(cycpwrThr1)) {
226afe68
JP		 1199 ath_dbg(common, ATH_DBG_ANI,
1200 "level out of range (%u > %zu)\n",
1201 level, ARRAY_SIZE(cycpwrThr1));
c16fcb49
FF		 1202 return false;
1203 }
1204 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
1205 AR_PHY_TIMING5_CYCPWR_THR1,
1206 cycpwrThr1[level]);
1207 if (level > aniState->spurImmunityLevel)
1208 ah->stats.ast_ani_spurup++;
1209 else if (level < aniState->spurImmunityLevel)
1210 ah->stats.ast_ani_spurdown++;
1211 aniState->spurImmunityLevel = level;
1212 break;
1213 }
1214 case ATH9K_ANI_PRESENT:
1215 break;
1216 default:
226afe68 1217 ath_dbg(common, ATH_DBG_ANI, "invalid cmd %u\n", cmd);
c16fcb49
FF		 1218 return false;
1219 }
1220
226afe68
JP		 1221 ath_dbg(common, ATH_DBG_ANI, "ANI parameters:\n");
1222 ath_dbg(common, ATH_DBG_ANI,
1223 "noiseImmunityLevel=%d, spurImmunityLevel=%d, ofdmWeakSigDetectOff=%d\n",
1224 aniState->noiseImmunityLevel,
1225 aniState->spurImmunityLevel,
1226 !aniState->ofdmWeakSigDetectOff);
1227 ath_dbg(common, ATH_DBG_ANI,
1228 "cckWeakSigThreshold=%d, firstepLevel=%d, listenTime=%d\n",
1229 aniState->cckWeakSigThreshold,
1230 aniState->firstepLevel,
1231 aniState->listenTime);
1232 ath_dbg(common, ATH_DBG_ANI,
9dbebc7f 1233 "ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
c16fcb49
FF		 1234 aniState->ofdmPhyErrCount,
1235 aniState->cckPhyErrCount);
1236
1237 return true;
1238}
1239
e36b27af
LR		 1240static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
1241 enum ath9k_ani_cmd cmd,
1242 int param)
1243{
e36b27af
LR		 1244 struct ath_common *common = ath9k_hw_common(ah);
1245 struct ath9k_channel *chan = ah->curchan;
093115b7 1246 struct ar5416AniState *aniState = &chan->ani;
e36b27af
LR		 1247 s32 value, value2;
1248
1249 switch (cmd & ah->ani_function) {
1250 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
1251 /*
1252 * on == 1 means ofdm weak signal detection is ON
1253 * on == 1 is the default, for less noise immunity
1254 *
1255 * on == 0 means ofdm weak signal detection is OFF
1256 * on == 0 means more noise imm
1257 */
1258 u32 on = param ? 1 : 0;
1259 /*
1260 * make register setting for default
1261 * (weak sig detect ON) come from INI file
1262 */
1263 int m1ThreshLow = on ?
1264 aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
1265 int m2ThreshLow = on ?
1266 aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
1267 int m1Thresh = on ?
1268 aniState->iniDef.m1Thresh : m1Thresh_off;
1269 int m2Thresh = on ?
1270 aniState->iniDef.m2Thresh : m2Thresh_off;
1271 int m2CountThr = on ?
1272 aniState->iniDef.m2CountThr : m2CountThr_off;
1273 int m2CountThrLow = on ?
1274 aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
1275 int m1ThreshLowExt = on ?
1276 aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
1277 int m2ThreshLowExt = on ?
1278 aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
1279 int m1ThreshExt = on ?
1280 aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
1281 int m2ThreshExt = on ?
1282 aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
1283
1284 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1285 AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
1286 m1ThreshLow);
1287 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1288 AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
1289 m2ThreshLow);
1290 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1291 AR_PHY_SFCORR_M1_THRESH, m1Thresh);
1292 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1293 AR_PHY_SFCORR_M2_THRESH, m2Thresh);
1294 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1295 AR_PHY_SFCORR_M2COUNT_THR, m2CountThr);
1296 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1297 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
1298 m2CountThrLow);
1299
1300 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1301 AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt);
1302 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1303 AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt);
1304 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1305 AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt);
1306 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1307 AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt);
1308
1309 if (on)
1310 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
1311 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1312 else
1313 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
1314 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1315
1316 if (!on != aniState->ofdmWeakSigDetectOff) {
226afe68
JP		 1317 ath_dbg(common, ATH_DBG_ANI,
1318 "** ch %d: ofdm weak signal: %s=>%s\n",
1319 chan->channel,
1320 !aniState->ofdmWeakSigDetectOff ?
1321 "on" : "off",
1322 on ? "on" : "off");
e36b27af
LR		 1323 if (on)
1324 ah->stats.ast_ani_ofdmon++;
1325 else
1326 ah->stats.ast_ani_ofdmoff++;
1327 aniState->ofdmWeakSigDetectOff = !on;
1328 }
1329 break;
1330 }
1331 case ATH9K_ANI_FIRSTEP_LEVEL:{
1332 u32 level = param;
1333
1334 if (level >= ARRAY_SIZE(firstep_table)) {
226afe68
JP		 1335 ath_dbg(common, ATH_DBG_ANI,
1336 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
1337 level, ARRAY_SIZE(firstep_table));
e36b27af
LR		 1338 return false;
1339 }
1340
1341 /*
1342 * make register setting relative to default
1343 * from INI file & cap value
1344 */
1345 value = firstep_table[level] -
1346 firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
1347 aniState->iniDef.firstep;
1348 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1349 value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1350 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1351 value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1352 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1353 AR_PHY_FIND_SIG_FIRSTEP,
1354 value);
1355 /*
1356 * we need to set first step low register too
1357 * make register setting relative to default
1358 * from INI file & cap value
1359 */
1360 value2 = firstep_table[level] -
1361 firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
1362 aniState->iniDef.firstepLow;
1363 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1364 value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1365 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1366 value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1367
1368 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
1369 AR_PHY_FIND_SIG_FIRSTEP_LOW, value2);
1370
1371 if (level != aniState->firstepLevel) {
226afe68
JP		 1372 ath_dbg(common, ATH_DBG_ANI,
1373 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
1374 chan->channel,
1375 aniState->firstepLevel,
1376 level,
1377 ATH9K_ANI_FIRSTEP_LVL_NEW,
1378 value,
1379 aniState->iniDef.firstep);
1380 ath_dbg(common, ATH_DBG_ANI,
1381 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
1382 chan->channel,
1383 aniState->firstepLevel,
1384 level,
1385 ATH9K_ANI_FIRSTEP_LVL_NEW,
1386 value2,
1387 aniState->iniDef.firstepLow);
e36b27af
LR		 1388 if (level > aniState->firstepLevel)
1389 ah->stats.ast_ani_stepup++;
1390 else if (level < aniState->firstepLevel)
1391 ah->stats.ast_ani_stepdown++;
1392 aniState->firstepLevel = level;
1393 }
1394 break;
1395 }
1396 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
1397 u32 level = param;
1398
1399 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
226afe68
JP		 1400 ath_dbg(common, ATH_DBG_ANI,
1401 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
1402 level, ARRAY_SIZE(cycpwrThr1_table));
e36b27af
LR		 1403 return false;
1404 }
1405 /*
1406 * make register setting relative to default
1407 * from INI file & cap value
1408 */
1409 value = cycpwrThr1_table[level] -
1410 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
1411 aniState->iniDef.cycpwrThr1;
1412 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1413 value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1414 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1415 value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1416 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
1417 AR_PHY_TIMING5_CYCPWR_THR1,
1418 value);
1419
1420 /*
1421 * set AR_PHY_EXT_CCA for extension channel
1422 * make register setting relative to default
1423 * from INI file & cap value
1424 */
1425 value2 = cycpwrThr1_table[level] -
1426 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
1427 aniState->iniDef.cycpwrThr1Ext;
1428 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1429 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1430 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1431 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1432 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
1433 AR_PHY_EXT_TIMING5_CYCPWR_THR1, value2);
1434
1435 if (level != aniState->spurImmunityLevel) {
226afe68
JP		 1436 ath_dbg(common, ATH_DBG_ANI,
1437 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
1438 chan->channel,
1439 aniState->spurImmunityLevel,
1440 level,
1441 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
1442 value,
1443 aniState->iniDef.cycpwrThr1);
1444 ath_dbg(common, ATH_DBG_ANI,
1445 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
1446 chan->channel,
1447 aniState->spurImmunityLevel,
1448 level,
1449 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
1450 value2,
1451 aniState->iniDef.cycpwrThr1Ext);
e36b27af
LR		 1452 if (level > aniState->spurImmunityLevel)
1453 ah->stats.ast_ani_spurup++;
1454 else if (level < aniState->spurImmunityLevel)
1455 ah->stats.ast_ani_spurdown++;
1456 aniState->spurImmunityLevel = level;
1457 }
1458 break;
1459 }
1460 case ATH9K_ANI_MRC_CCK:
1461 /*
1462 * You should not see this as AR5008, AR9001, AR9002
1463 * does not have hardware support for MRC CCK.
1464 */
1465 WARN_ON(1);
1466 break;
1467 case ATH9K_ANI_PRESENT:
1468 break;
1469 default:
226afe68 1470 ath_dbg(common, ATH_DBG_ANI, "invalid cmd %u\n", cmd);
e36b27af
LR		 1471 return false;
1472 }
1473
226afe68
JP		 1474 ath_dbg(common, ATH_DBG_ANI,
1475 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1476 aniState->spurImmunityLevel,
1477 !aniState->ofdmWeakSigDetectOff ? "on" : "off",
1478 aniState->firstepLevel,
1479 !aniState->mrcCCKOff ? "on" : "off",
1480 aniState->listenTime,
1481 aniState->ofdmPhyErrCount,
1482 aniState->cckPhyErrCount);
e36b27af
LR		 1483 return true;
1484}
1485
641d9921
FF		 1486static void ar5008_hw_do_getnf(struct ath_hw *ah,
1487 int16_t nfarray[NUM_NF_READINGS])
1488{
641d9921
FF		 1489 int16_t nf;
1490
1491 nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
7919a57b 1492 nfarray[0] = sign_extend32(nf, 8);
641d9921
FF		 1493
1494 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR);
7919a57b 1495 nfarray[1] = sign_extend32(nf, 8);
641d9921
FF		 1496
1497 nf = MS(REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR);
7919a57b 1498 nfarray[2] = sign_extend32(nf, 8);
641d9921 1499
866b7780
FF		 1500 if (!IS_CHAN_HT40(ah->curchan))
1501 return;
1502
641d9921 1503 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);
7919a57b 1504 nfarray[3] = sign_extend32(nf, 8);
641d9921
FF		 1505
1506 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR);
7919a57b 1507 nfarray[4] = sign_extend32(nf, 8);
641d9921
FF		 1508
1509 nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR);
7919a57b 1510 nfarray[5] = sign_extend32(nf, 8);
641d9921
FF		 1511}
1512
e36b27af
LR		 1513/*
1514 * Initialize the ANI register values with default (ini) values.
1515 * This routine is called during a (full) hardware reset after
1516 * all the registers are initialised from the INI.
1517 */
1518static void ar5008_hw_ani_cache_ini_regs(struct ath_hw *ah)
1519{
e36b27af
LR		 1520 struct ath_common *common = ath9k_hw_common(ah);
1521 struct ath9k_channel *chan = ah->curchan;
093115b7 1522 struct ar5416AniState *aniState = &chan->ani;
e36b27af 1523 struct ath9k_ani_default *iniDef;
e36b27af
LR		 1524 u32 val;
1525
e36b27af
LR		 1526 iniDef = &aniState->iniDef;
1527
226afe68
JP		 1528 ath_dbg(common, ATH_DBG_ANI, "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
1529 ah->hw_version.macVersion,
1530 ah->hw_version.macRev,
1531 ah->opmode,
1532 chan->channel,
1533 chan->channelFlags);
e36b27af
LR		 1534
1535 val = REG_READ(ah, AR_PHY_SFCORR);
1536 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1537 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1538 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1539
1540 val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1541 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1542 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1543 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1544
1545 val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1546 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1547 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1548 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1549 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1550 iniDef->firstep = REG_READ_FIELD(ah,
1551 AR_PHY_FIND_SIG,
1552 AR_PHY_FIND_SIG_FIRSTEP);
1553 iniDef->firstepLow = REG_READ_FIELD(ah,
1554 AR_PHY_FIND_SIG_LOW,
1555 AR_PHY_FIND_SIG_FIRSTEP_LOW);
1556 iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1557 AR_PHY_TIMING5,
1558 AR_PHY_TIMING5_CYCPWR_THR1);
1559 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1560 AR_PHY_EXT_CCA,
1561 AR_PHY_EXT_TIMING5_CYCPWR_THR1);
1562
1563 /* these levels just got reset to defaults by the INI */
1564 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL_NEW;
1565 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW;
1566 aniState->ofdmWeakSigDetectOff = !ATH9K_ANI_USE_OFDM_WEAK_SIG;
1567 aniState->mrcCCKOff = true; /* not available on pre AR9003 */
e36b27af
LR		 1568}
1569
f2552e28
FF		 1570static void ar5008_hw_set_nf_limits(struct ath_hw *ah)
1571{
1572 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ;
1573 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ;
1574 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ;
1575 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ;
1576 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ;
1577 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ;
1578}
e36b27af 1579
4e8c14e9
FF		 1580static void ar5008_hw_set_radar_params(struct ath_hw *ah,
1581 struct ath_hw_radar_conf *conf)
1582{
1583 u32 radar_0 = 0, radar_1 = 0;
1584
1585 if (!conf) {
1586 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1587 return;
1588 }
1589
1590 radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
1591 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1592 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1593 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1594 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1595 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1596
1597 radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1598 radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1599 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1600 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
1601 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1602
1603 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1604 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1605 if (conf->ext_channel)
1606 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1607 else
1608 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1609}
1610
c5d0855a
FF		 1611static void ar5008_hw_set_radar_conf(struct ath_hw *ah)
1612{
1613 struct ath_hw_radar_conf *conf = &ah->radar_conf;
1614
1615 conf->fir_power = -33;
1616 conf->radar_rssi = 20;
1617 conf->pulse_height = 10;
1618 conf->pulse_rssi = 24;
1619 conf->pulse_inband = 15;
1620 conf->pulse_maxlen = 255;
1621 conf->pulse_inband_step = 12;
1622 conf->radar_inband = 8;
1623}
1624
8fe65368
LR		 1625void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
1626{
1627 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
07b2fa5a 1628 static const u32 ar5416_cca_regs[6] = {
bbacee13
FF		 1629 AR_PHY_CCA,
1630 AR_PHY_CH1_CCA,
1631 AR_PHY_CH2_CCA,
1632 AR_PHY_EXT_CCA,
1633 AR_PHY_CH1_EXT_CCA,
1634 AR_PHY_CH2_EXT_CCA
1635 };
8fe65368
LR		 1636
1637 priv_ops->rf_set_freq = ar5008_hw_set_channel;
1638 priv_ops->spur_mitigate_freq = ar5008_hw_spur_mitigate;
1639
1640 priv_ops->rf_alloc_ext_banks = ar5008_hw_rf_alloc_ext_banks;
1641 priv_ops->rf_free_ext_banks = ar5008_hw_rf_free_ext_banks;
1642 priv_ops->set_rf_regs = ar5008_hw_set_rf_regs;
1643 priv_ops->set_channel_regs = ar5008_hw_set_channel_regs;
1644 priv_ops->init_bb = ar5008_hw_init_bb;
1645 priv_ops->process_ini = ar5008_hw_process_ini;
1646 priv_ops->set_rfmode = ar5008_hw_set_rfmode;
1647 priv_ops->mark_phy_inactive = ar5008_hw_mark_phy_inactive;
1648 priv_ops->set_delta_slope = ar5008_hw_set_delta_slope;
1649 priv_ops->rfbus_req = ar5008_hw_rfbus_req;
1650 priv_ops->rfbus_done = ar5008_hw_rfbus_done;
8fe65368
LR		 1651 priv_ops->restore_chainmask = ar5008_restore_chainmask;
1652 priv_ops->set_diversity = ar5008_set_diversity;
641d9921 1653 priv_ops->do_getnf = ar5008_hw_do_getnf;
4e8c14e9 1654 priv_ops->set_radar_params = ar5008_hw_set_radar_params;
64773964 1655
e36b27af
LR		 1656 if (modparam_force_new_ani) {
1657 priv_ops->ani_control = ar5008_hw_ani_control_new;
1658 priv_ops->ani_cache_ini_regs = ar5008_hw_ani_cache_ini_regs;
1659 } else
1660 priv_ops->ani_control = ar5008_hw_ani_control_old;
1661
64773964
LR		 1662 if (AR_SREV_9100(ah))
1663 priv_ops->compute_pll_control = ar9100_hw_compute_pll_control;
1664 else if (AR_SREV_9160_10_OR_LATER(ah))
1665 priv_ops->compute_pll_control = ar9160_hw_compute_pll_control;
1666 else
1667 priv_ops->compute_pll_control = ar5008_hw_compute_pll_control;
f2552e28
FF		 1668
1669 ar5008_hw_set_nf_limits(ah);
c5d0855a 1670 ar5008_hw_set_radar_conf(ah);
bbacee13 1671 memcpy(ah->nf_regs, ar5416_cca_regs, sizeof(ah->nf_regs));
8fe65368 1672}
Linux 6.x block layer and io_uring tree(s)