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r8152: replace void * with struct r8152 *
[linux-2.6-block.git] / drivers / net / usb / r8152.c
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ac718b69 1/*
2 * Copyright (c) 2013 Realtek Semiconductor Corp. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * version 2 as published by the Free Software Foundation.
7 *
8 */
9
10#include <linux/init.h>
11#include <linux/signal.h>
12#include <linux/slab.h>
13#include <linux/module.h>
ac718b69 14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/mii.h>
17#include <linux/ethtool.h>
18#include <linux/usb.h>
19#include <linux/crc32.h>
20#include <linux/if_vlan.h>
21#include <linux/uaccess.h>
ebc2ec48 22#include <linux/list.h>
5bd23881 23#include <linux/ip.h>
24#include <linux/ipv6.h>
ac718b69 25
26/* Version Information */
ebc2ec48 27#define DRIVER_VERSION "v1.01.0 (2013/08/12)"
ac718b69 28#define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
29#define DRIVER_DESC "Realtek RTL8152 Based USB 2.0 Ethernet Adapters"
30#define MODULENAME "r8152"
31
32#define R8152_PHY_ID 32
33
34#define PLA_IDR 0xc000
35#define PLA_RCR 0xc010
36#define PLA_RMS 0xc016
37#define PLA_RXFIFO_CTRL0 0xc0a0
38#define PLA_RXFIFO_CTRL1 0xc0a4
39#define PLA_RXFIFO_CTRL2 0xc0a8
40#define PLA_FMC 0xc0b4
41#define PLA_CFG_WOL 0xc0b6
42#define PLA_MAR 0xcd00
43#define PAL_BDC_CR 0xd1a0
44#define PLA_LEDSEL 0xdd90
45#define PLA_LED_FEATURE 0xdd92
46#define PLA_PHYAR 0xde00
47#define PLA_GPHY_INTR_IMR 0xe022
48#define PLA_EEE_CR 0xe040
49#define PLA_EEEP_CR 0xe080
50#define PLA_MAC_PWR_CTRL 0xe0c0
51#define PLA_TCR0 0xe610
52#define PLA_TCR1 0xe612
53#define PLA_TXFIFO_CTRL 0xe618
54#define PLA_RSTTELLY 0xe800
55#define PLA_CR 0xe813
56#define PLA_CRWECR 0xe81c
57#define PLA_CONFIG5 0xe822
58#define PLA_PHY_PWR 0xe84c
59#define PLA_OOB_CTRL 0xe84f
60#define PLA_CPCR 0xe854
61#define PLA_MISC_0 0xe858
62#define PLA_MISC_1 0xe85a
63#define PLA_OCP_GPHY_BASE 0xe86c
64#define PLA_TELLYCNT 0xe890
65#define PLA_SFF_STS_7 0xe8de
66#define PLA_PHYSTATUS 0xe908
67#define PLA_BP_BA 0xfc26
68#define PLA_BP_0 0xfc28
69#define PLA_BP_1 0xfc2a
70#define PLA_BP_2 0xfc2c
71#define PLA_BP_3 0xfc2e
72#define PLA_BP_4 0xfc30
73#define PLA_BP_5 0xfc32
74#define PLA_BP_6 0xfc34
75#define PLA_BP_7 0xfc36
76
77#define USB_DEV_STAT 0xb808
78#define USB_USB_CTRL 0xd406
79#define USB_PHY_CTRL 0xd408
80#define USB_TX_AGG 0xd40a
81#define USB_RX_BUF_TH 0xd40c
82#define USB_USB_TIMER 0xd428
83#define USB_PM_CTRL_STATUS 0xd432
84#define USB_TX_DMA 0xd434
85#define USB_UPS_CTRL 0xd800
86#define USB_BP_BA 0xfc26
87#define USB_BP_0 0xfc28
88#define USB_BP_1 0xfc2a
89#define USB_BP_2 0xfc2c
90#define USB_BP_3 0xfc2e
91#define USB_BP_4 0xfc30
92#define USB_BP_5 0xfc32
93#define USB_BP_6 0xfc34
94#define USB_BP_7 0xfc36
95
96/* OCP Registers */
97#define OCP_ALDPS_CONFIG 0x2010
98#define OCP_EEE_CONFIG1 0x2080
99#define OCP_EEE_CONFIG2 0x2092
100#define OCP_EEE_CONFIG3 0x2094
101#define OCP_EEE_AR 0xa41a
102#define OCP_EEE_DATA 0xa41c
103
104/* PLA_RCR */
105#define RCR_AAP 0x00000001
106#define RCR_APM 0x00000002
107#define RCR_AM 0x00000004
108#define RCR_AB 0x00000008
109#define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
110
111/* PLA_RXFIFO_CTRL0 */
112#define RXFIFO_THR1_NORMAL 0x00080002
113#define RXFIFO_THR1_OOB 0x01800003
114
115/* PLA_RXFIFO_CTRL1 */
116#define RXFIFO_THR2_FULL 0x00000060
117#define RXFIFO_THR2_HIGH 0x00000038
118#define RXFIFO_THR2_OOB 0x0000004a
119
120/* PLA_RXFIFO_CTRL2 */
121#define RXFIFO_THR3_FULL 0x00000078
122#define RXFIFO_THR3_HIGH 0x00000048
123#define RXFIFO_THR3_OOB 0x0000005a
124
125/* PLA_TXFIFO_CTRL */
126#define TXFIFO_THR_NORMAL 0x00400008
127
128/* PLA_FMC */
129#define FMC_FCR_MCU_EN 0x0001
130
131/* PLA_EEEP_CR */
132#define EEEP_CR_EEEP_TX 0x0002
133
134/* PLA_TCR0 */
135#define TCR0_TX_EMPTY 0x0800
136#define TCR0_AUTO_FIFO 0x0080
137
138/* PLA_TCR1 */
139#define VERSION_MASK 0x7cf0
140
141/* PLA_CR */
142#define CR_RST 0x10
143#define CR_RE 0x08
144#define CR_TE 0x04
145
146/* PLA_CRWECR */
147#define CRWECR_NORAML 0x00
148#define CRWECR_CONFIG 0xc0
149
150/* PLA_OOB_CTRL */
151#define NOW_IS_OOB 0x80
152#define TXFIFO_EMPTY 0x20
153#define RXFIFO_EMPTY 0x10
154#define LINK_LIST_READY 0x02
155#define DIS_MCU_CLROOB 0x01
156#define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
157
158/* PLA_MISC_1 */
159#define RXDY_GATED_EN 0x0008
160
161/* PLA_SFF_STS_7 */
162#define RE_INIT_LL 0x8000
163#define MCU_BORW_EN 0x4000
164
165/* PLA_CPCR */
166#define CPCR_RX_VLAN 0x0040
167
168/* PLA_CFG_WOL */
169#define MAGIC_EN 0x0001
170
171/* PAL_BDC_CR */
172#define ALDPS_PROXY_MODE 0x0001
173
174/* PLA_CONFIG5 */
175#define LAN_WAKE_EN 0x0002
176
177/* PLA_LED_FEATURE */
178#define LED_MODE_MASK 0x0700
179
180/* PLA_PHY_PWR */
181#define TX_10M_IDLE_EN 0x0080
182#define PFM_PWM_SWITCH 0x0040
183
184/* PLA_MAC_PWR_CTRL */
185#define D3_CLK_GATED_EN 0x00004000
186#define MCU_CLK_RATIO 0x07010f07
187#define MCU_CLK_RATIO_MASK 0x0f0f0f0f
188
189/* PLA_GPHY_INTR_IMR */
190#define GPHY_STS_MSK 0x0001
191#define SPEED_DOWN_MSK 0x0002
192#define SPDWN_RXDV_MSK 0x0004
193#define SPDWN_LINKCHG_MSK 0x0008
194
195/* PLA_PHYAR */
196#define PHYAR_FLAG 0x80000000
197
198/* PLA_EEE_CR */
199#define EEE_RX_EN 0x0001
200#define EEE_TX_EN 0x0002
201
202/* USB_DEV_STAT */
203#define STAT_SPEED_MASK 0x0006
204#define STAT_SPEED_HIGH 0x0000
205#define STAT_SPEED_FULL 0x0001
206
207/* USB_TX_AGG */
208#define TX_AGG_MAX_THRESHOLD 0x03
209
210/* USB_RX_BUF_TH */
211#define RX_BUF_THR 0x7a120180
212
213/* USB_TX_DMA */
214#define TEST_MODE_DISABLE 0x00000001
215#define TX_SIZE_ADJUST1 0x00000100
216
217/* USB_UPS_CTRL */
218#define POWER_CUT 0x0100
219
220/* USB_PM_CTRL_STATUS */
221#define RWSUME_INDICATE 0x0001
222
223/* USB_USB_CTRL */
224#define RX_AGG_DISABLE 0x0010
225
226/* OCP_ALDPS_CONFIG */
227#define ENPWRSAVE 0x8000
228#define ENPDNPS 0x0200
229#define LINKENA 0x0100
230#define DIS_SDSAVE 0x0010
231
232/* OCP_EEE_CONFIG1 */
233#define RG_TXLPI_MSK_HFDUP 0x8000
234#define RG_MATCLR_EN 0x4000
235#define EEE_10_CAP 0x2000
236#define EEE_NWAY_EN 0x1000
237#define TX_QUIET_EN 0x0200
238#define RX_QUIET_EN 0x0100
239#define SDRISETIME 0x0010 /* bit 4 ~ 6 */
240#define RG_RXLPI_MSK_HFDUP 0x0008
241#define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
242
243/* OCP_EEE_CONFIG2 */
244#define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
245#define RG_DACQUIET_EN 0x0400
246#define RG_LDVQUIET_EN 0x0200
247#define RG_CKRSEL 0x0020
248#define RG_EEEPRG_EN 0x0010
249
250/* OCP_EEE_CONFIG3 */
251#define FST_SNR_EYE_R 0x1500 /* bit 7 ~ 15 */
252#define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
253#define MSK_PH 0x0006 /* bit 0 ~ 3 */
254
255/* OCP_EEE_AR */
256/* bit[15:14] function */
257#define FUN_ADDR 0x0000
258#define FUN_DATA 0x4000
259/* bit[4:0] device addr */
260#define DEVICE_ADDR 0x0007
261
262/* OCP_EEE_DATA */
263#define EEE_ADDR 0x003C
264#define EEE_DATA 0x0002
265
266enum rtl_register_content {
267 _100bps = 0x08,
268 _10bps = 0x04,
269 LINK_STATUS = 0x02,
270 FULL_DUP = 0x01,
271};
272
ebc2ec48 273#define RTL8152_MAX_TX 10
274#define RTL8152_MAX_RX 10
40a82917 275#define INTBUFSIZE 2
276
277#define INTR_LINK 0x0004
ebc2ec48 278
ac718b69 279#define RTL8152_REQT_READ 0xc0
280#define RTL8152_REQT_WRITE 0x40
281#define RTL8152_REQ_GET_REGS 0x05
282#define RTL8152_REQ_SET_REGS 0x05
283
284#define BYTE_EN_DWORD 0xff
285#define BYTE_EN_WORD 0x33
286#define BYTE_EN_BYTE 0x11
287#define BYTE_EN_SIX_BYTES 0x3f
288#define BYTE_EN_START_MASK 0x0f
289#define BYTE_EN_END_MASK 0xf0
290
291#define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
292#define RTL8152_TX_TIMEOUT (HZ)
293
294/* rtl8152 flags */
295enum rtl8152_flags {
296 RTL8152_UNPLUG = 0,
ac718b69 297 RTL8152_SET_RX_MODE,
40a82917 298 WORK_ENABLE,
299 RTL8152_LINK_CHG,
ac718b69 300};
301
302/* Define these values to match your device */
303#define VENDOR_ID_REALTEK 0x0bda
304#define PRODUCT_ID_RTL8152 0x8152
305
306#define MCU_TYPE_PLA 0x0100
307#define MCU_TYPE_USB 0x0000
308
309struct rx_desc {
310 u32 opts1;
311#define RX_LEN_MASK 0x7fff
312 u32 opts2;
313 u32 opts3;
314 u32 opts4;
315 u32 opts5;
316 u32 opts6;
317};
318
319struct tx_desc {
320 u32 opts1;
321#define TX_FS (1 << 31) /* First segment of a packet */
322#define TX_LS (1 << 30) /* Final segment of a packet */
5bd23881 323#define TX_LEN_MASK 0x3ffff
324
ac718b69 325 u32 opts2;
5bd23881 326#define UDP_CS (1 << 31) /* Calculate UDP/IP checksum */
327#define TCP_CS (1 << 30) /* Calculate TCP/IP checksum */
328#define IPV4_CS (1 << 29) /* Calculate IPv4 checksum */
329#define IPV6_CS (1 << 28) /* Calculate IPv6 checksum */
ac718b69 330};
331
dff4e8ad 332struct r8152;
333
ebc2ec48 334struct rx_agg {
335 struct list_head list;
336 struct urb *urb;
dff4e8ad 337 struct r8152 *context;
ebc2ec48 338 void *buffer;
339 void *head;
340};
341
342struct tx_agg {
343 struct list_head list;
344 struct urb *urb;
dff4e8ad 345 struct r8152 *context;
ebc2ec48 346 void *buffer;
347 void *head;
348 u32 skb_num;
349 u32 skb_len;
350};
351
ac718b69 352struct r8152 {
353 unsigned long flags;
354 struct usb_device *udev;
355 struct tasklet_struct tl;
40a82917 356 struct usb_interface *intf;
ac718b69 357 struct net_device *netdev;
40a82917 358 struct urb *intr_urb;
ebc2ec48 359 struct tx_agg tx_info[RTL8152_MAX_TX];
360 struct rx_agg rx_info[RTL8152_MAX_RX];
361 struct list_head rx_done, tx_free;
362 struct sk_buff_head tx_queue;
363 spinlock_t rx_lock, tx_lock;
ac718b69 364 struct delayed_work schedule;
365 struct mii_if_info mii;
40a82917 366 int intr_interval;
ac718b69 367 u32 msg_enable;
368 u16 ocp_base;
40a82917 369 u8 *intr_buff;
ac718b69 370 u8 version;
371 u8 speed;
372};
373
374enum rtl_version {
375 RTL_VER_UNKNOWN = 0,
376 RTL_VER_01,
377 RTL_VER_02
378};
379
380/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
381 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
382 */
383static const int multicast_filter_limit = 32;
ebc2ec48 384static unsigned int rx_buf_sz = 16384;
ac718b69 385
386static
387int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
388{
31787f53 389 int ret;
390 void *tmp;
391
392 tmp = kmalloc(size, GFP_KERNEL);
393 if (!tmp)
394 return -ENOMEM;
395
396 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
ac718b69 397 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
31787f53 398 value, index, tmp, size, 500);
399
400 memcpy(data, tmp, size);
401 kfree(tmp);
402
403 return ret;
ac718b69 404}
405
406static
407int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
408{
31787f53 409 int ret;
410 void *tmp;
411
412 tmp = kmalloc(size, GFP_KERNEL);
413 if (!tmp)
414 return -ENOMEM;
415
416 memcpy(tmp, data, size);
417
418 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
ac718b69 419 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
31787f53 420 value, index, tmp, size, 500);
421
422 kfree(tmp);
423 return ret;
ac718b69 424}
425
426static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
427 void *data, u16 type)
428{
429 u16 limit = 64;
430 int ret = 0;
431
432 if (test_bit(RTL8152_UNPLUG, &tp->flags))
433 return -ENODEV;
434
435 /* both size and indix must be 4 bytes align */
436 if ((size & 3) || !size || (index & 3) || !data)
437 return -EPERM;
438
439 if ((u32)index + (u32)size > 0xffff)
440 return -EPERM;
441
442 while (size) {
443 if (size > limit) {
444 ret = get_registers(tp, index, type, limit, data);
445 if (ret < 0)
446 break;
447
448 index += limit;
449 data += limit;
450 size -= limit;
451 } else {
452 ret = get_registers(tp, index, type, size, data);
453 if (ret < 0)
454 break;
455
456 index += size;
457 data += size;
458 size = 0;
459 break;
460 }
461 }
462
463 return ret;
464}
465
466static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
467 u16 size, void *data, u16 type)
468{
469 int ret;
470 u16 byteen_start, byteen_end, byen;
471 u16 limit = 512;
472
473 if (test_bit(RTL8152_UNPLUG, &tp->flags))
474 return -ENODEV;
475
476 /* both size and indix must be 4 bytes align */
477 if ((size & 3) || !size || (index & 3) || !data)
478 return -EPERM;
479
480 if ((u32)index + (u32)size > 0xffff)
481 return -EPERM;
482
483 byteen_start = byteen & BYTE_EN_START_MASK;
484 byteen_end = byteen & BYTE_EN_END_MASK;
485
486 byen = byteen_start | (byteen_start << 4);
487 ret = set_registers(tp, index, type | byen, 4, data);
488 if (ret < 0)
489 goto error1;
490
491 index += 4;
492 data += 4;
493 size -= 4;
494
495 if (size) {
496 size -= 4;
497
498 while (size) {
499 if (size > limit) {
500 ret = set_registers(tp, index,
501 type | BYTE_EN_DWORD,
502 limit, data);
503 if (ret < 0)
504 goto error1;
505
506 index += limit;
507 data += limit;
508 size -= limit;
509 } else {
510 ret = set_registers(tp, index,
511 type | BYTE_EN_DWORD,
512 size, data);
513 if (ret < 0)
514 goto error1;
515
516 index += size;
517 data += size;
518 size = 0;
519 break;
520 }
521 }
522
523 byen = byteen_end | (byteen_end >> 4);
524 ret = set_registers(tp, index, type | byen, 4, data);
525 if (ret < 0)
526 goto error1;
527 }
528
529error1:
530 return ret;
531}
532
533static inline
534int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
535{
536 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
537}
538
539static inline
540int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
541{
542 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
543}
544
545static inline
546int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
547{
548 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
549}
550
551static inline
552int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
553{
554 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
555}
556
557static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
558{
c8826de8 559 __le32 data;
ac718b69 560
c8826de8 561 generic_ocp_read(tp, index, sizeof(data), &data, type);
ac718b69 562
563 return __le32_to_cpu(data);
564}
565
566static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
567{
c8826de8 568 __le32 tmp = __cpu_to_le32(data);
569
570 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
ac718b69 571}
572
573static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
574{
575 u32 data;
c8826de8 576 __le32 tmp;
ac718b69 577 u8 shift = index & 2;
578
579 index &= ~3;
580
c8826de8 581 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
ac718b69 582
c8826de8 583 data = __le32_to_cpu(tmp);
ac718b69 584 data >>= (shift * 8);
585 data &= 0xffff;
586
587 return (u16)data;
588}
589
590static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
591{
c8826de8 592 u32 mask = 0xffff;
593 __le32 tmp;
ac718b69 594 u16 byen = BYTE_EN_WORD;
595 u8 shift = index & 2;
596
597 data &= mask;
598
599 if (index & 2) {
600 byen <<= shift;
601 mask <<= (shift * 8);
602 data <<= (shift * 8);
603 index &= ~3;
604 }
605
c8826de8 606 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
ac718b69 607
c8826de8 608 data |= __le32_to_cpu(tmp) & ~mask;
609 tmp = __cpu_to_le32(data);
ac718b69 610
c8826de8 611 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
ac718b69 612}
613
614static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
615{
616 u32 data;
c8826de8 617 __le32 tmp;
ac718b69 618 u8 shift = index & 3;
619
620 index &= ~3;
621
c8826de8 622 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
ac718b69 623
c8826de8 624 data = __le32_to_cpu(tmp);
ac718b69 625 data >>= (shift * 8);
626 data &= 0xff;
627
628 return (u8)data;
629}
630
631static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
632{
c8826de8 633 u32 mask = 0xff;
634 __le32 tmp;
ac718b69 635 u16 byen = BYTE_EN_BYTE;
636 u8 shift = index & 3;
637
638 data &= mask;
639
640 if (index & 3) {
641 byen <<= shift;
642 mask <<= (shift * 8);
643 data <<= (shift * 8);
644 index &= ~3;
645 }
646
c8826de8 647 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
ac718b69 648
c8826de8 649 data |= __le32_to_cpu(tmp) & ~mask;
650 tmp = __cpu_to_le32(data);
ac718b69 651
c8826de8 652 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
ac718b69 653}
654
655static void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
656{
657 u32 ocp_data;
658 int i;
659
660 ocp_data = PHYAR_FLAG | ((reg_addr & 0x1f) << 16) |
661 (value & 0xffff);
662
663 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_PHYAR, ocp_data);
664
665 for (i = 20; i > 0; i--) {
666 udelay(25);
667 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_PHYAR);
668 if (!(ocp_data & PHYAR_FLAG))
669 break;
670 }
671 udelay(20);
672}
673
674static int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
675{
676 u32 ocp_data;
677 int i;
678
679 ocp_data = (reg_addr & 0x1f) << 16;
680 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_PHYAR, ocp_data);
681
682 for (i = 20; i > 0; i--) {
683 udelay(25);
684 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_PHYAR);
685 if (ocp_data & PHYAR_FLAG)
686 break;
687 }
688 udelay(20);
689
690 if (!(ocp_data & PHYAR_FLAG))
691 return -EAGAIN;
692
693 return (u16)(ocp_data & 0xffff);
694}
695
696static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
697{
698 struct r8152 *tp = netdev_priv(netdev);
699
700 if (phy_id != R8152_PHY_ID)
701 return -EINVAL;
702
703 return r8152_mdio_read(tp, reg);
704}
705
706static
707void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
708{
709 struct r8152 *tp = netdev_priv(netdev);
710
711 if (phy_id != R8152_PHY_ID)
712 return;
713
714 r8152_mdio_write(tp, reg, val);
715}
716
717static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
718{
719 u16 ocp_base, ocp_index;
720
721 ocp_base = addr & 0xf000;
722 if (ocp_base != tp->ocp_base) {
723 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
724 tp->ocp_base = ocp_base;
725 }
726
727 ocp_index = (addr & 0x0fff) | 0xb000;
728 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
729}
730
ebc2ec48 731static
732int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
733
ac718b69 734static inline void set_ethernet_addr(struct r8152 *tp)
735{
736 struct net_device *dev = tp->netdev;
31787f53 737 u8 node_id[8] = {0};
ac718b69 738
31787f53 739 if (pla_ocp_read(tp, PLA_IDR, sizeof(node_id), node_id) < 0)
ac718b69 740 netif_notice(tp, probe, dev, "inet addr fail\n");
741 else {
742 memcpy(dev->dev_addr, node_id, dev->addr_len);
743 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
744 }
ac718b69 745}
746
747static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
748{
749 struct r8152 *tp = netdev_priv(netdev);
750 struct sockaddr *addr = p;
751
752 if (!is_valid_ether_addr(addr->sa_data))
753 return -EADDRNOTAVAIL;
754
755 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
756
757 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
758 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
759 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
760
761 return 0;
762}
763
ac718b69 764static struct net_device_stats *rtl8152_get_stats(struct net_device *dev)
765{
766 return &dev->stats;
767}
768
769static void read_bulk_callback(struct urb *urb)
770{
ac718b69 771 struct net_device *netdev;
ebc2ec48 772 unsigned long lockflags;
ac718b69 773 int status = urb->status;
ebc2ec48 774 struct rx_agg *agg;
775 struct r8152 *tp;
ac718b69 776 int result;
ac718b69 777
ebc2ec48 778 agg = urb->context;
779 if (!agg)
780 return;
781
782 tp = agg->context;
ac718b69 783 if (!tp)
784 return;
ebc2ec48 785
ac718b69 786 if (test_bit(RTL8152_UNPLUG, &tp->flags))
787 return;
ebc2ec48 788
789 if (!test_bit(WORK_ENABLE, &tp->flags))
790 return;
791
ac718b69 792 netdev = tp->netdev;
ebc2ec48 793 if (!netif_carrier_ok(netdev))
ac718b69 794 return;
795
ac718b69 796 switch (status) {
797 case 0:
ebc2ec48 798 if (urb->actual_length < ETH_ZLEN)
799 break;
800
801 spin_lock_irqsave(&tp->rx_lock, lockflags);
802 list_add_tail(&agg->list, &tp->rx_done);
803 spin_unlock_irqrestore(&tp->rx_lock, lockflags);
804 tasklet_schedule(&tp->tl);
805 return;
ac718b69 806 case -ESHUTDOWN:
807 set_bit(RTL8152_UNPLUG, &tp->flags);
808 netif_device_detach(tp->netdev);
ebc2ec48 809 return;
ac718b69 810 case -ENOENT:
811 return; /* the urb is in unlink state */
812 case -ETIME:
813 pr_warn_ratelimited("may be reset is needed?..\n");
ebc2ec48 814 break;
ac718b69 815 default:
816 pr_warn_ratelimited("Rx status %d\n", status);
ebc2ec48 817 break;
ac718b69 818 }
819
ebc2ec48 820 result = r8152_submit_rx(tp, agg, GFP_ATOMIC);
ac718b69 821 if (result == -ENODEV) {
822 netif_device_detach(tp->netdev);
823 } else if (result) {
ebc2ec48 824 spin_lock_irqsave(&tp->rx_lock, lockflags);
825 list_add_tail(&agg->list, &tp->rx_done);
826 spin_unlock_irqrestore(&tp->rx_lock, lockflags);
827 tasklet_schedule(&tp->tl);
ac718b69 828 }
ac718b69 829}
830
ebc2ec48 831static void write_bulk_callback(struct urb *urb)
ac718b69 832{
ebc2ec48 833 struct net_device_stats *stats;
834 unsigned long lockflags;
835 struct tx_agg *agg;
ac718b69 836 struct r8152 *tp;
ebc2ec48 837 int status = urb->status;
ac718b69 838
ebc2ec48 839 agg = urb->context;
840 if (!agg)
ac718b69 841 return;
842
ebc2ec48 843 tp = agg->context;
844 if (!tp)
845 return;
846
847 stats = rtl8152_get_stats(tp->netdev);
848 if (status) {
849 pr_warn_ratelimited("Tx status %d\n", status);
850 stats->tx_errors += agg->skb_num;
ac718b69 851 } else {
ebc2ec48 852 stats->tx_packets += agg->skb_num;
853 stats->tx_bytes += agg->skb_len;
ac718b69 854 }
855
ebc2ec48 856 spin_lock_irqsave(&tp->tx_lock, lockflags);
857 list_add_tail(&agg->list, &tp->tx_free);
858 spin_unlock_irqrestore(&tp->tx_lock, lockflags);
859
860 if (!netif_carrier_ok(tp->netdev))
861 return;
862
863 if (!test_bit(WORK_ENABLE, &tp->flags))
864 return;
865
866 if (test_bit(RTL8152_UNPLUG, &tp->flags))
867 return;
868
869 if (!skb_queue_empty(&tp->tx_queue))
870 tasklet_schedule(&tp->tl);
ac718b69 871}
872
40a82917 873static void intr_callback(struct urb *urb)
874{
875 struct r8152 *tp;
876 __u16 *d;
877 int status = urb->status;
878 int res;
879
880 tp = urb->context;
881 if (!tp)
882 return;
883
884 if (!test_bit(WORK_ENABLE, &tp->flags))
885 return;
886
887 if (test_bit(RTL8152_UNPLUG, &tp->flags))
888 return;
889
890 switch (status) {
891 case 0: /* success */
892 break;
893 case -ECONNRESET: /* unlink */
894 case -ESHUTDOWN:
895 netif_device_detach(tp->netdev);
896 case -ENOENT:
897 return;
898 case -EOVERFLOW:
899 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
900 goto resubmit;
901 /* -EPIPE: should clear the halt */
902 default:
903 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
904 goto resubmit;
905 }
906
907 d = urb->transfer_buffer;
908 if (INTR_LINK & __le16_to_cpu(d[0])) {
909 if (!(tp->speed & LINK_STATUS)) {
910 set_bit(RTL8152_LINK_CHG, &tp->flags);
911 schedule_delayed_work(&tp->schedule, 0);
912 }
913 } else {
914 if (tp->speed & LINK_STATUS) {
915 set_bit(RTL8152_LINK_CHG, &tp->flags);
916 schedule_delayed_work(&tp->schedule, 0);
917 }
918 }
919
920resubmit:
921 res = usb_submit_urb(urb, GFP_ATOMIC);
922 if (res == -ENODEV)
923 netif_device_detach(tp->netdev);
924 else if (res)
925 netif_err(tp, intr, tp->netdev,
926 "can't resubmit intr, status %d\n", res);
927}
928
ebc2ec48 929static inline void *rx_agg_align(void *data)
930{
931 return (void *)ALIGN((uintptr_t)data, 8);
932}
933
934static inline void *tx_agg_align(void *data)
935{
936 return (void *)ALIGN((uintptr_t)data, 4);
937}
938
939static void free_all_mem(struct r8152 *tp)
940{
941 int i;
942
943 for (i = 0; i < RTL8152_MAX_RX; i++) {
944 if (tp->rx_info[i].urb) {
945 usb_free_urb(tp->rx_info[i].urb);
946 tp->rx_info[i].urb = NULL;
947 }
948
949 if (tp->rx_info[i].buffer) {
950 kfree(tp->rx_info[i].buffer);
951 tp->rx_info[i].buffer = NULL;
952 tp->rx_info[i].head = NULL;
953 }
954 }
955
956 for (i = 0; i < RTL8152_MAX_TX; i++) {
957 if (tp->tx_info[i].urb) {
958 usb_free_urb(tp->tx_info[i].urb);
959 tp->tx_info[i].urb = NULL;
960 }
961
962 if (tp->tx_info[i].buffer) {
963 kfree(tp->tx_info[i].buffer);
964 tp->tx_info[i].buffer = NULL;
965 tp->tx_info[i].head = NULL;
966 }
967 }
40a82917 968
969 if (tp->intr_urb) {
970 usb_free_urb(tp->intr_urb);
971 tp->intr_urb = NULL;
972 }
973
974 if (tp->intr_buff) {
975 kfree(tp->intr_buff);
976 tp->intr_buff = NULL;
977 }
ebc2ec48 978}
979
980static int alloc_all_mem(struct r8152 *tp)
981{
982 struct net_device *netdev = tp->netdev;
40a82917 983 struct usb_interface *intf = tp->intf;
984 struct usb_host_interface *alt = intf->cur_altsetting;
985 struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
ebc2ec48 986 struct urb *urb;
987 int node, i;
988 u8 *buf;
989
990 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
991
992 spin_lock_init(&tp->rx_lock);
993 spin_lock_init(&tp->tx_lock);
994 INIT_LIST_HEAD(&tp->rx_done);
995 INIT_LIST_HEAD(&tp->tx_free);
996 skb_queue_head_init(&tp->tx_queue);
997
998 for (i = 0; i < RTL8152_MAX_RX; i++) {
999 buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
1000 if (!buf)
1001 goto err1;
1002
1003 if (buf != rx_agg_align(buf)) {
1004 kfree(buf);
1005 buf = kmalloc_node(rx_buf_sz + 8, GFP_KERNEL, node);
1006 if (!buf)
1007 goto err1;
1008 }
1009
1010 urb = usb_alloc_urb(0, GFP_KERNEL);
1011 if (!urb) {
1012 kfree(buf);
1013 goto err1;
1014 }
1015
1016 INIT_LIST_HEAD(&tp->rx_info[i].list);
1017 tp->rx_info[i].context = tp;
1018 tp->rx_info[i].urb = urb;
1019 tp->rx_info[i].buffer = buf;
1020 tp->rx_info[i].head = rx_agg_align(buf);
1021 }
1022
1023 for (i = 0; i < RTL8152_MAX_TX; i++) {
1024 buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
1025 if (!buf)
1026 goto err1;
1027
1028 if (buf != tx_agg_align(buf)) {
1029 kfree(buf);
1030 buf = kmalloc_node(rx_buf_sz + 4, GFP_KERNEL, node);
1031 if (!buf)
1032 goto err1;
1033 }
1034
1035 urb = usb_alloc_urb(0, GFP_KERNEL);
1036 if (!urb) {
1037 kfree(buf);
1038 goto err1;
1039 }
1040
1041 INIT_LIST_HEAD(&tp->tx_info[i].list);
1042 tp->tx_info[i].context = tp;
1043 tp->tx_info[i].urb = urb;
1044 tp->tx_info[i].buffer = buf;
1045 tp->tx_info[i].head = tx_agg_align(buf);
1046
1047 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1048 }
1049
40a82917 1050 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1051 if (!tp->intr_urb)
1052 goto err1;
1053
1054 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1055 if (!tp->intr_buff)
1056 goto err1;
1057
1058 tp->intr_interval = (int)ep_intr->desc.bInterval;
1059 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1060 tp->intr_buff, INTBUFSIZE, intr_callback,
1061 tp, tp->intr_interval);
1062
ebc2ec48 1063 return 0;
1064
1065err1:
1066 free_all_mem(tp);
1067 return -ENOMEM;
1068}
1069
5bd23881 1070static void
1071r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, struct sk_buff *skb)
1072{
1073 memset(desc, 0, sizeof(*desc));
1074
1075 desc->opts1 = cpu_to_le32((skb->len & TX_LEN_MASK) | TX_FS | TX_LS);
1076
1077 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1078 __be16 protocol;
1079 u8 ip_protocol;
1080 u32 opts2 = 0;
1081
1082 if (skb->protocol == htons(ETH_P_8021Q))
1083 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
1084 else
1085 protocol = skb->protocol;
1086
1087 switch (protocol) {
1088 case htons(ETH_P_IP):
1089 opts2 |= IPV4_CS;
1090 ip_protocol = ip_hdr(skb)->protocol;
1091 break;
1092
1093 case htons(ETH_P_IPV6):
1094 opts2 |= IPV6_CS;
1095 ip_protocol = ipv6_hdr(skb)->nexthdr;
1096 break;
1097
1098 default:
1099 ip_protocol = IPPROTO_RAW;
1100 break;
1101 }
1102
1103 if (ip_protocol == IPPROTO_TCP) {
1104 opts2 |= TCP_CS;
1105 opts2 |= (skb_transport_offset(skb) & 0x7fff) << 17;
1106 } else if (ip_protocol == IPPROTO_UDP) {
1107 opts2 |= UDP_CS;
1108 } else {
1109 WARN_ON_ONCE(1);
1110 }
1111
1112 desc->opts2 = cpu_to_le32(opts2);
1113 }
1114}
1115
ebc2ec48 1116static void rx_bottom(struct r8152 *tp)
1117{
1118 struct net_device_stats *stats;
1119 struct net_device *netdev;
1120 struct rx_agg *agg;
1121 struct rx_desc *rx_desc;
1122 unsigned long lockflags;
1123 struct list_head *cursor, *next;
1124 struct sk_buff *skb;
1125 struct urb *urb;
1126 unsigned pkt_len;
1127 int len_used;
1128 u8 *rx_data;
1129 int ret;
1130
1131 netdev = tp->netdev;
1132
1133 stats = rtl8152_get_stats(netdev);
1134
1135 spin_lock_irqsave(&tp->rx_lock, lockflags);
1136 list_for_each_safe(cursor, next, &tp->rx_done) {
1137 list_del_init(cursor);
1138 spin_unlock_irqrestore(&tp->rx_lock, lockflags);
1139
1140 agg = list_entry(cursor, struct rx_agg, list);
1141 urb = agg->urb;
1142 if (urb->actual_length < ETH_ZLEN) {
1143 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
1144 spin_lock_irqsave(&tp->rx_lock, lockflags);
1145 if (ret && ret != -ENODEV) {
1146 list_add_tail(&agg->list, next);
1147 tasklet_schedule(&tp->tl);
1148 }
1149 continue;
1150 }
1151
1152 len_used = 0;
1153 rx_desc = agg->head;
1154 rx_data = agg->head;
1155 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1156 len_used += sizeof(struct rx_desc) + pkt_len;
1157
1158 while (urb->actual_length >= len_used) {
1159 if (pkt_len < ETH_ZLEN)
1160 break;
1161
1162 pkt_len -= 4; /* CRC */
1163 rx_data += sizeof(struct rx_desc);
1164
1165 skb = netdev_alloc_skb_ip_align(netdev, pkt_len);
1166 if (!skb) {
1167 stats->rx_dropped++;
1168 break;
1169 }
1170 memcpy(skb->data, rx_data, pkt_len);
1171 skb_put(skb, pkt_len);
1172 skb->protocol = eth_type_trans(skb, netdev);
1173 netif_rx(skb);
1174 stats->rx_packets++;
1175 stats->rx_bytes += pkt_len;
1176
1177 rx_data = rx_agg_align(rx_data + pkt_len + 4);
1178 rx_desc = (struct rx_desc *)rx_data;
1179 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1180 len_used = (int)(rx_data - (u8 *)agg->head);
1181 len_used += sizeof(struct rx_desc) + pkt_len;
1182 }
1183
1184 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
1185 spin_lock_irqsave(&tp->rx_lock, lockflags);
1186 if (ret && ret != -ENODEV) {
1187 list_add_tail(&agg->list, next);
1188 tasklet_schedule(&tp->tl);
1189 }
1190 }
1191 spin_unlock_irqrestore(&tp->rx_lock, lockflags);
1192}
1193
1194static void tx_bottom(struct r8152 *tp)
1195{
1196 struct net_device_stats *stats;
1197 struct net_device *netdev;
1198 struct tx_agg *agg;
1199 unsigned long lockflags;
1200 u32 remain, total;
1201 u8 *tx_data;
1202 int res;
1203
1204 netdev = tp->netdev;
1205
1206next_agg:
1207 agg = NULL;
1208 spin_lock_irqsave(&tp->tx_lock, lockflags);
1209 if (!skb_queue_empty(&tp->tx_queue) && !list_empty(&tp->tx_free)) {
1210 struct list_head *cursor;
1211
1212 cursor = tp->tx_free.next;
1213 list_del_init(cursor);
1214 agg = list_entry(cursor, struct tx_agg, list);
1215 }
1216 spin_unlock_irqrestore(&tp->tx_lock, lockflags);
1217
1218 if (!agg)
1219 return;
1220
1221 tx_data = agg->head;
1222 agg->skb_num = agg->skb_len = 0;
1223 remain = rx_buf_sz - sizeof(struct tx_desc);
1224 total = 0;
1225
1226 while (remain >= ETH_ZLEN) {
1227 struct tx_desc *tx_desc;
1228 struct sk_buff *skb;
1229 unsigned int len;
1230
1231 skb = skb_dequeue(&tp->tx_queue);
1232 if (!skb)
1233 break;
1234
1235 len = skb->len;
1236 if (remain < len) {
1237 skb_queue_head(&tp->tx_queue, skb);
1238 break;
1239 }
1240
1241 tx_data = tx_agg_align(tx_data);
1242 tx_desc = (struct tx_desc *)tx_data;
1243 tx_data += sizeof(*tx_desc);
1244
5bd23881 1245 r8152_tx_csum(tp, tx_desc, skb);
ebc2ec48 1246 memcpy(tx_data, skb->data, len);
1247 agg->skb_num++;
1248 agg->skb_len += len;
1249 dev_kfree_skb_any(skb);
1250
1251 tx_data += len;
1252 remain = rx_buf_sz - sizeof(*tx_desc) -
1253 (u32)(tx_agg_align(tx_data) - agg->head);
1254 }
1255
1256 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1257 agg->head, (int)(tx_data - (u8 *)agg->head),
1258 (usb_complete_t)write_bulk_callback, agg);
1259 res = usb_submit_urb(agg->urb, GFP_ATOMIC);
1260
1261 stats = rtl8152_get_stats(netdev);
1262
1263 if (res) {
1264 /* Can we get/handle EPIPE here? */
1265 if (res == -ENODEV) {
1266 netif_device_detach(netdev);
1267 } else {
1268 netif_warn(tp, tx_err, netdev,
1269 "failed tx_urb %d\n", res);
1270 stats->tx_dropped += agg->skb_num;
1271 spin_lock_irqsave(&tp->tx_lock, lockflags);
1272 list_add_tail(&agg->list, &tp->tx_free);
1273 spin_unlock_irqrestore(&tp->tx_lock, lockflags);
1274 }
1275 return;
1276 }
1277 goto next_agg;
1278}
1279
1280static void bottom_half(unsigned long data)
ac718b69 1281{
1282 struct r8152 *tp;
ac718b69 1283
ebc2ec48 1284 tp = (struct r8152 *)data;
1285
1286 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1287 return;
1288
1289 if (!test_bit(WORK_ENABLE, &tp->flags))
ac718b69 1290 return;
ebc2ec48 1291
1292 if (!netif_carrier_ok(tp->netdev))
ac718b69 1293 return;
ebc2ec48 1294
1295 rx_bottom(tp);
1296 tx_bottom(tp);
1297}
1298
1299static
1300int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
1301{
1302 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
1303 agg->head, rx_buf_sz,
1304 (usb_complete_t)read_bulk_callback, agg);
1305
1306 return usb_submit_urb(agg->urb, mem_flags);
ac718b69 1307}
1308
1309static void rtl8152_tx_timeout(struct net_device *netdev)
1310{
1311 struct r8152 *tp = netdev_priv(netdev);
ebc2ec48 1312 int i;
1313
ac718b69 1314 netif_warn(tp, tx_err, netdev, "Tx timeout.\n");
ebc2ec48 1315 for (i = 0; i < RTL8152_MAX_TX; i++)
1316 usb_unlink_urb(tp->tx_info[i].urb);
ac718b69 1317}
1318
1319static void rtl8152_set_rx_mode(struct net_device *netdev)
1320{
1321 struct r8152 *tp = netdev_priv(netdev);
1322
40a82917 1323 if (tp->speed & LINK_STATUS) {
ac718b69 1324 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
40a82917 1325 schedule_delayed_work(&tp->schedule, 0);
1326 }
ac718b69 1327}
1328
1329static void _rtl8152_set_rx_mode(struct net_device *netdev)
1330{
1331 struct r8152 *tp = netdev_priv(netdev);
31787f53 1332 u32 mc_filter[2]; /* Multicast hash filter */
1333 __le32 tmp[2];
ac718b69 1334 u32 ocp_data;
1335
ac718b69 1336 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
1337 netif_stop_queue(netdev);
1338 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1339 ocp_data &= ~RCR_ACPT_ALL;
1340 ocp_data |= RCR_AB | RCR_APM;
1341
1342 if (netdev->flags & IFF_PROMISC) {
1343 /* Unconditionally log net taps. */
1344 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
1345 ocp_data |= RCR_AM | RCR_AAP;
1346 mc_filter[1] = mc_filter[0] = 0xffffffff;
1347 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
1348 (netdev->flags & IFF_ALLMULTI)) {
1349 /* Too many to filter perfectly -- accept all multicasts. */
1350 ocp_data |= RCR_AM;
1351 mc_filter[1] = mc_filter[0] = 0xffffffff;
1352 } else {
1353 struct netdev_hw_addr *ha;
1354
1355 mc_filter[1] = mc_filter[0] = 0;
1356 netdev_for_each_mc_addr(ha, netdev) {
1357 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1358 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1359 ocp_data |= RCR_AM;
1360 }
1361 }
1362
31787f53 1363 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
1364 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
ac718b69 1365
31787f53 1366 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
ac718b69 1367 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1368 netif_wake_queue(netdev);
ac718b69 1369}
1370
1371static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
1372 struct net_device *netdev)
1373{
1374 struct r8152 *tp = netdev_priv(netdev);
1375 struct net_device_stats *stats = rtl8152_get_stats(netdev);
ebc2ec48 1376 unsigned long lockflags;
1377 struct tx_agg *agg = NULL;
ac718b69 1378 struct tx_desc *tx_desc;
3ff25e3c 1379 unsigned int len;
ebc2ec48 1380 u8 *tx_data;
3ff25e3c 1381 int res;
ac718b69 1382
ebc2ec48 1383 skb_tx_timestamp(skb);
ac718b69 1384
ebc2ec48 1385 spin_lock_irqsave(&tp->tx_lock, lockflags);
1386 if (!list_empty(&tp->tx_free) && skb_queue_empty(&tp->tx_queue)) {
1387 struct list_head *cursor;
1388
1389 cursor = tp->tx_free.next;
1390 list_del_init(cursor);
1391 agg = list_entry(cursor, struct tx_agg, list);
ac718b69 1392 }
ebc2ec48 1393 spin_unlock_irqrestore(&tp->tx_lock, lockflags);
1394
1395 if (!agg) {
1396 skb_queue_tail(&tp->tx_queue, skb);
1397 return NETDEV_TX_OK;
1398 }
1399
1400 tx_desc = (struct tx_desc *)agg->head;
1401 tx_data = agg->head + sizeof(*tx_desc);
1402 agg->skb_num = agg->skb_len = 0;
1403
1404 len = skb->len;
5bd23881 1405 r8152_tx_csum(tp, tx_desc, skb);
ebc2ec48 1406 memcpy(tx_data, skb->data, len);
1407 dev_kfree_skb_any(skb);
1408 agg->skb_num++;
1409 agg->skb_len += len;
1410 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1411 agg->head, len + sizeof(*tx_desc),
1412 (usb_complete_t)write_bulk_callback, agg);
1413 res = usb_submit_urb(agg->urb, GFP_ATOMIC);
ac718b69 1414 if (res) {
1415 /* Can we get/handle EPIPE here? */
1416 if (res == -ENODEV) {
1417 netif_device_detach(tp->netdev);
1418 } else {
1419 netif_warn(tp, tx_err, netdev,
1420 "failed tx_urb %d\n", res);
ebc2ec48 1421 stats->tx_dropped++;
1422 spin_lock_irqsave(&tp->tx_lock, lockflags);
1423 list_add_tail(&agg->list, &tp->tx_free);
1424 spin_unlock_irqrestore(&tp->tx_lock, lockflags);
ac718b69 1425 }
ac718b69 1426 }
1427
1428 return NETDEV_TX_OK;
1429}
1430
1431static void r8152b_reset_packet_filter(struct r8152 *tp)
1432{
1433 u32 ocp_data;
1434
1435 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
1436 ocp_data &= ~FMC_FCR_MCU_EN;
1437 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1438 ocp_data |= FMC_FCR_MCU_EN;
1439 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1440}
1441
1442static void rtl8152_nic_reset(struct r8152 *tp)
1443{
1444 int i;
1445
1446 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
1447
1448 for (i = 0; i < 1000; i++) {
1449 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
1450 break;
1451 udelay(100);
1452 }
1453}
1454
1455static inline u8 rtl8152_get_speed(struct r8152 *tp)
1456{
1457 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
1458}
1459
1460static int rtl8152_enable(struct r8152 *tp)
1461{
ebc2ec48 1462 u32 ocp_data;
1463 int i, ret;
ac718b69 1464 u8 speed;
1465
1466 speed = rtl8152_get_speed(tp);
ebc2ec48 1467 if (speed & _10bps) {
ac718b69 1468 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
ebc2ec48 1469 ocp_data |= EEEP_CR_EEEP_TX;
ac718b69 1470 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
1471 } else {
1472 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
ebc2ec48 1473 ocp_data &= ~EEEP_CR_EEEP_TX;
ac718b69 1474 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
1475 }
1476
1477 r8152b_reset_packet_filter(tp);
1478
1479 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
1480 ocp_data |= CR_RE | CR_TE;
1481 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
1482
1483 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
1484 ocp_data &= ~RXDY_GATED_EN;
1485 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
1486
ebc2ec48 1487 INIT_LIST_HEAD(&tp->rx_done);
1488 ret = 0;
1489 for (i = 0; i < RTL8152_MAX_RX; i++) {
1490 INIT_LIST_HEAD(&tp->rx_info[i].list);
1491 ret |= r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
1492 }
ac718b69 1493
ebc2ec48 1494 return ret;
ac718b69 1495}
1496
1497static void rtl8152_disable(struct r8152 *tp)
1498{
ebc2ec48 1499 struct net_device_stats *stats = rtl8152_get_stats(tp->netdev);
1500 struct sk_buff *skb;
1501 u32 ocp_data;
1502 int i;
ac718b69 1503
1504 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1505 ocp_data &= ~RCR_ACPT_ALL;
1506 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1507
ebc2ec48 1508 while ((skb = skb_dequeue(&tp->tx_queue))) {
1509 dev_kfree_skb(skb);
1510 stats->tx_dropped++;
1511 }
1512
1513 for (i = 0; i < RTL8152_MAX_TX; i++)
1514 usb_kill_urb(tp->tx_info[i].urb);
ac718b69 1515
1516 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
1517 ocp_data |= RXDY_GATED_EN;
1518 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
1519
1520 for (i = 0; i < 1000; i++) {
1521 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1522 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
1523 break;
1524 mdelay(1);
1525 }
1526
1527 for (i = 0; i < 1000; i++) {
1528 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
1529 break;
1530 mdelay(1);
1531 }
1532
ebc2ec48 1533 for (i = 0; i < RTL8152_MAX_RX; i++)
1534 usb_kill_urb(tp->rx_info[i].urb);
ac718b69 1535
1536 rtl8152_nic_reset(tp);
1537}
1538
1539static void r8152b_exit_oob(struct r8152 *tp)
1540{
1541 u32 ocp_data;
1542 int i;
1543
1544 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1545 ocp_data &= ~RCR_ACPT_ALL;
1546 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1547
1548 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
1549 ocp_data |= RXDY_GATED_EN;
1550 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
1551
1552 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1553 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
1554
1555 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1556 ocp_data &= ~NOW_IS_OOB;
1557 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
1558
1559 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
1560 ocp_data &= ~MCU_BORW_EN;
1561 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
1562
1563 for (i = 0; i < 1000; i++) {
1564 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1565 if (ocp_data & LINK_LIST_READY)
1566 break;
1567 mdelay(1);
1568 }
1569
1570 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
1571 ocp_data |= RE_INIT_LL;
1572 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
1573
1574 for (i = 0; i < 1000; i++) {
1575 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1576 if (ocp_data & LINK_LIST_READY)
1577 break;
1578 mdelay(1);
1579 }
1580
1581 rtl8152_nic_reset(tp);
1582
1583 /* rx share fifo credit full threshold */
1584 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
1585
1586 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_DEV_STAT);
1587 ocp_data &= STAT_SPEED_MASK;
1588 if (ocp_data == STAT_SPEED_FULL) {
1589 /* rx share fifo credit near full threshold */
1590 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
1591 RXFIFO_THR2_FULL);
1592 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
1593 RXFIFO_THR3_FULL);
1594 } else {
1595 /* rx share fifo credit near full threshold */
1596 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
1597 RXFIFO_THR2_HIGH);
1598 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
1599 RXFIFO_THR3_HIGH);
1600 }
1601
1602 /* TX share fifo free credit full threshold */
1603 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
1604
1605 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
1606 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_BUF_THR);
1607 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
1608 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
1609
1610 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
1611 ocp_data &= ~CPCR_RX_VLAN;
1612 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
1613
1614 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
1615
1616 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
1617 ocp_data |= TCR0_AUTO_FIFO;
1618 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
1619}
1620
1621static void r8152b_enter_oob(struct r8152 *tp)
1622{
1623 u32 ocp_data;
1624 int i;
1625
1626 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1627 ocp_data &= ~NOW_IS_OOB;
1628 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
1629
1630 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
1631 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
1632 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
1633
1634 rtl8152_disable(tp);
1635
1636 for (i = 0; i < 1000; i++) {
1637 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1638 if (ocp_data & LINK_LIST_READY)
1639 break;
1640 mdelay(1);
1641 }
1642
1643 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
1644 ocp_data |= RE_INIT_LL;
1645 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
1646
1647 for (i = 0; i < 1000; i++) {
1648 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1649 if (ocp_data & LINK_LIST_READY)
1650 break;
1651 mdelay(1);
1652 }
1653
1654 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
1655
1656 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
1657 ocp_data |= MAGIC_EN;
1658 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
1659
1660 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
1661 ocp_data |= CPCR_RX_VLAN;
1662 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
1663
1664 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
1665 ocp_data |= ALDPS_PROXY_MODE;
1666 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
1667
1668 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1669 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
1670 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
1671
1672 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5, LAN_WAKE_EN);
1673
1674 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
1675 ocp_data &= ~RXDY_GATED_EN;
1676 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
1677
1678 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1679 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
1680 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1681}
1682
1683static void r8152b_disable_aldps(struct r8152 *tp)
1684{
1685 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
1686 msleep(20);
1687}
1688
1689static inline void r8152b_enable_aldps(struct r8152 *tp)
1690{
1691 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
1692 LINKENA | DIS_SDSAVE);
1693}
1694
1695static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
1696{
1697 u16 bmcr, anar;
1698 int ret = 0;
1699
1700 cancel_delayed_work_sync(&tp->schedule);
1701 anar = r8152_mdio_read(tp, MII_ADVERTISE);
1702 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1703 ADVERTISE_100HALF | ADVERTISE_100FULL);
1704
1705 if (autoneg == AUTONEG_DISABLE) {
1706 if (speed == SPEED_10) {
1707 bmcr = 0;
1708 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1709 } else if (speed == SPEED_100) {
1710 bmcr = BMCR_SPEED100;
1711 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
1712 } else {
1713 ret = -EINVAL;
1714 goto out;
1715 }
1716
1717 if (duplex == DUPLEX_FULL)
1718 bmcr |= BMCR_FULLDPLX;
1719 } else {
1720 if (speed == SPEED_10) {
1721 if (duplex == DUPLEX_FULL)
1722 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1723 else
1724 anar |= ADVERTISE_10HALF;
1725 } else if (speed == SPEED_100) {
1726 if (duplex == DUPLEX_FULL) {
1727 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1728 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
1729 } else {
1730 anar |= ADVERTISE_10HALF;
1731 anar |= ADVERTISE_100HALF;
1732 }
1733 } else {
1734 ret = -EINVAL;
1735 goto out;
1736 }
1737
1738 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1739 }
1740
1741 r8152_mdio_write(tp, MII_ADVERTISE, anar);
1742 r8152_mdio_write(tp, MII_BMCR, bmcr);
1743
1744out:
ac718b69 1745
1746 return ret;
1747}
1748
1749static void rtl8152_down(struct r8152 *tp)
1750{
1751 u32 ocp_data;
1752
1753 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
1754 ocp_data &= ~POWER_CUT;
1755 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
1756
1757 r8152b_disable_aldps(tp);
1758 r8152b_enter_oob(tp);
1759 r8152b_enable_aldps(tp);
1760}
1761
1762static void set_carrier(struct r8152 *tp)
1763{
1764 struct net_device *netdev = tp->netdev;
1765 u8 speed;
1766
40a82917 1767 clear_bit(RTL8152_LINK_CHG, &tp->flags);
ac718b69 1768 speed = rtl8152_get_speed(tp);
1769
1770 if (speed & LINK_STATUS) {
1771 if (!(tp->speed & LINK_STATUS)) {
1772 rtl8152_enable(tp);
1773 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
1774 netif_carrier_on(netdev);
1775 }
1776 } else {
1777 if (tp->speed & LINK_STATUS) {
1778 netif_carrier_off(netdev);
ebc2ec48 1779 tasklet_disable(&tp->tl);
ac718b69 1780 rtl8152_disable(tp);
ebc2ec48 1781 tasklet_enable(&tp->tl);
ac718b69 1782 }
1783 }
1784 tp->speed = speed;
1785}
1786
1787static void rtl_work_func_t(struct work_struct *work)
1788{
1789 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
1790
1791 if (!test_bit(WORK_ENABLE, &tp->flags))
1792 goto out1;
1793
1794 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1795 goto out1;
1796
40a82917 1797 if (test_bit(RTL8152_LINK_CHG, &tp->flags))
1798 set_carrier(tp);
ac718b69 1799
1800 if (test_bit(RTL8152_SET_RX_MODE, &tp->flags))
1801 _rtl8152_set_rx_mode(tp->netdev);
1802
ac718b69 1803out1:
1804 return;
1805}
1806
1807static int rtl8152_open(struct net_device *netdev)
1808{
1809 struct r8152 *tp = netdev_priv(netdev);
1810 int res = 0;
1811
40a82917 1812 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
1813 if (res) {
1814 if (res == -ENODEV)
1815 netif_device_detach(tp->netdev);
1816 netif_warn(tp, ifup, netdev,
1817 "intr_urb submit failed: %d\n", res);
1818 return res;
ac718b69 1819 }
1820
1821 rtl8152_set_speed(tp, AUTONEG_ENABLE, SPEED_100, DUPLEX_FULL);
40a82917 1822 tp->speed = 0;
1823 netif_carrier_off(netdev);
ac718b69 1824 netif_start_queue(netdev);
1825 set_bit(WORK_ENABLE, &tp->flags);
ac718b69 1826
1827 return res;
1828}
1829
1830static int rtl8152_close(struct net_device *netdev)
1831{
1832 struct r8152 *tp = netdev_priv(netdev);
1833 int res = 0;
1834
40a82917 1835 usb_kill_urb(tp->intr_urb);
ac718b69 1836 clear_bit(WORK_ENABLE, &tp->flags);
1837 cancel_delayed_work_sync(&tp->schedule);
1838 netif_stop_queue(netdev);
ebc2ec48 1839 tasklet_disable(&tp->tl);
ac718b69 1840 rtl8152_disable(tp);
ebc2ec48 1841 tasklet_enable(&tp->tl);
ac718b69 1842
1843 return res;
1844}
1845
1846static void rtl_clear_bp(struct r8152 *tp)
1847{
1848 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_0, 0);
1849 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_2, 0);
1850 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_4, 0);
1851 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_6, 0);
1852 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_0, 0);
1853 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_2, 0);
1854 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_4, 0);
1855 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_6, 0);
1856 mdelay(3);
1857 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_BA, 0);
1858 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_BA, 0);
1859}
1860
1861static void r8152b_enable_eee(struct r8152 *tp)
1862{
1863 u32 ocp_data;
1864
1865 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
1866 ocp_data |= EEE_RX_EN | EEE_TX_EN;
1867 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
1868 ocp_reg_write(tp, OCP_EEE_CONFIG1, RG_TXLPI_MSK_HFDUP | RG_MATCLR_EN |
1869 EEE_10_CAP | EEE_NWAY_EN |
1870 TX_QUIET_EN | RX_QUIET_EN |
1871 SDRISETIME | RG_RXLPI_MSK_HFDUP |
1872 SDFALLTIME);
1873 ocp_reg_write(tp, OCP_EEE_CONFIG2, RG_LPIHYS_NUM | RG_DACQUIET_EN |
1874 RG_LDVQUIET_EN | RG_CKRSEL |
1875 RG_EEEPRG_EN);
1876 ocp_reg_write(tp, OCP_EEE_CONFIG3, FST_SNR_EYE_R | RG_LFS_SEL | MSK_PH);
1877 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | DEVICE_ADDR);
1878 ocp_reg_write(tp, OCP_EEE_DATA, EEE_ADDR);
1879 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | DEVICE_ADDR);
1880 ocp_reg_write(tp, OCP_EEE_DATA, EEE_DATA);
1881 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
1882}
1883
1884static void r8152b_enable_fc(struct r8152 *tp)
1885{
1886 u16 anar;
1887
1888 anar = r8152_mdio_read(tp, MII_ADVERTISE);
1889 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1890 r8152_mdio_write(tp, MII_ADVERTISE, anar);
1891}
1892
1893static void r8152b_hw_phy_cfg(struct r8152 *tp)
1894{
1895 r8152_mdio_write(tp, MII_BMCR, BMCR_ANENABLE);
1896 r8152b_disable_aldps(tp);
1897}
1898
1899static void r8152b_init(struct r8152 *tp)
1900{
ebc2ec48 1901 u32 ocp_data;
1902 int i;
ac718b69 1903
1904 rtl_clear_bp(tp);
1905
1906 if (tp->version == RTL_VER_01) {
1907 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
1908 ocp_data &= ~LED_MODE_MASK;
1909 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
1910 }
1911
1912 r8152b_hw_phy_cfg(tp);
1913
1914 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
1915 ocp_data &= ~POWER_CUT;
1916 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
1917
1918 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
1919 ocp_data &= ~RWSUME_INDICATE;
1920 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
1921
1922 r8152b_exit_oob(tp);
1923
1924 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
1925 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
1926 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
1927 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
1928 ocp_data &= ~MCU_CLK_RATIO_MASK;
1929 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
1930 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
1931 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
1932 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
1933 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
1934
1935 r8152b_enable_eee(tp);
1936 r8152b_enable_aldps(tp);
1937 r8152b_enable_fc(tp);
1938
1939 r8152_mdio_write(tp, MII_BMCR, BMCR_RESET | BMCR_ANENABLE |
1940 BMCR_ANRESTART);
1941 for (i = 0; i < 100; i++) {
1942 udelay(100);
1943 if (!(r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET))
1944 break;
1945 }
1946
ebc2ec48 1947 /* enable rx aggregation */
ac718b69 1948 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
ebc2ec48 1949 ocp_data &= ~RX_AGG_DISABLE;
ac718b69 1950 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
1951}
1952
1953static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
1954{
1955 struct r8152 *tp = usb_get_intfdata(intf);
1956
1957 netif_device_detach(tp->netdev);
1958
1959 if (netif_running(tp->netdev)) {
1960 clear_bit(WORK_ENABLE, &tp->flags);
40a82917 1961 usb_kill_urb(tp->intr_urb);
ac718b69 1962 cancel_delayed_work_sync(&tp->schedule);
ebc2ec48 1963 tasklet_disable(&tp->tl);
ac718b69 1964 }
1965
1966 rtl8152_down(tp);
1967
1968 return 0;
1969}
1970
1971static int rtl8152_resume(struct usb_interface *intf)
1972{
1973 struct r8152 *tp = usb_get_intfdata(intf);
1974
1975 r8152b_init(tp);
1976 netif_device_attach(tp->netdev);
1977 if (netif_running(tp->netdev)) {
40a82917 1978 rtl8152_set_speed(tp, AUTONEG_ENABLE, SPEED_100, DUPLEX_FULL);
1979 tp->speed = 0;
1980 netif_carrier_off(tp->netdev);
ac718b69 1981 set_bit(WORK_ENABLE, &tp->flags);
40a82917 1982 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
ebc2ec48 1983 tasklet_enable(&tp->tl);
ac718b69 1984 }
1985
1986 return 0;
1987}
1988
1989static void rtl8152_get_drvinfo(struct net_device *netdev,
1990 struct ethtool_drvinfo *info)
1991{
1992 struct r8152 *tp = netdev_priv(netdev);
1993
1994 strncpy(info->driver, MODULENAME, ETHTOOL_BUSINFO_LEN);
1995 strncpy(info->version, DRIVER_VERSION, ETHTOOL_BUSINFO_LEN);
1996 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
1997}
1998
1999static
2000int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
2001{
2002 struct r8152 *tp = netdev_priv(netdev);
2003
2004 if (!tp->mii.mdio_read)
2005 return -EOPNOTSUPP;
2006
2007 return mii_ethtool_gset(&tp->mii, cmd);
2008}
2009
2010static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2011{
2012 struct r8152 *tp = netdev_priv(dev);
2013
2014 return rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
2015}
2016
2017static struct ethtool_ops ops = {
2018 .get_drvinfo = rtl8152_get_drvinfo,
2019 .get_settings = rtl8152_get_settings,
2020 .set_settings = rtl8152_set_settings,
2021 .get_link = ethtool_op_get_link,
2022};
2023
2024static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2025{
2026 struct r8152 *tp = netdev_priv(netdev);
2027 struct mii_ioctl_data *data = if_mii(rq);
2028 int res = 0;
2029
2030 switch (cmd) {
2031 case SIOCGMIIPHY:
2032 data->phy_id = R8152_PHY_ID; /* Internal PHY */
2033 break;
2034
2035 case SIOCGMIIREG:
2036 data->val_out = r8152_mdio_read(tp, data->reg_num);
2037 break;
2038
2039 case SIOCSMIIREG:
2040 if (!capable(CAP_NET_ADMIN)) {
2041 res = -EPERM;
2042 break;
2043 }
2044 r8152_mdio_write(tp, data->reg_num, data->val_in);
2045 break;
2046
2047 default:
2048 res = -EOPNOTSUPP;
2049 }
2050
2051 return res;
2052}
2053
2054static const struct net_device_ops rtl8152_netdev_ops = {
2055 .ndo_open = rtl8152_open,
2056 .ndo_stop = rtl8152_close,
2057 .ndo_do_ioctl = rtl8152_ioctl,
2058 .ndo_start_xmit = rtl8152_start_xmit,
2059 .ndo_tx_timeout = rtl8152_tx_timeout,
2060 .ndo_set_rx_mode = rtl8152_set_rx_mode,
2061 .ndo_set_mac_address = rtl8152_set_mac_address,
2062
2063 .ndo_change_mtu = eth_change_mtu,
2064 .ndo_validate_addr = eth_validate_addr,
2065};
2066
2067static void r8152b_get_version(struct r8152 *tp)
2068{
2069 u32 ocp_data;
2070 u16 version;
2071
2072 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
2073 version = (u16)(ocp_data & VERSION_MASK);
2074
2075 switch (version) {
2076 case 0x4c00:
2077 tp->version = RTL_VER_01;
2078 break;
2079 case 0x4c10:
2080 tp->version = RTL_VER_02;
2081 break;
2082 default:
2083 netif_info(tp, probe, tp->netdev,
2084 "Unknown version 0x%04x\n", version);
2085 break;
2086 }
2087}
2088
2089static int rtl8152_probe(struct usb_interface *intf,
2090 const struct usb_device_id *id)
2091{
2092 struct usb_device *udev = interface_to_usbdev(intf);
2093 struct r8152 *tp;
2094 struct net_device *netdev;
ebc2ec48 2095 int ret;
ac718b69 2096
2097 if (udev->actconfig->desc.bConfigurationValue != 1) {
2098 usb_driver_set_configuration(udev, 1);
2099 return -ENODEV;
2100 }
2101
2102 netdev = alloc_etherdev(sizeof(struct r8152));
2103 if (!netdev) {
2104 dev_err(&intf->dev, "Out of memory");
2105 return -ENOMEM;
2106 }
2107
ebc2ec48 2108 SET_NETDEV_DEV(netdev, &intf->dev);
ac718b69 2109 tp = netdev_priv(netdev);
2110 tp->msg_enable = 0x7FFF;
2111
ebc2ec48 2112 tasklet_init(&tp->tl, bottom_half, (unsigned long)tp);
ac718b69 2113 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
2114
2115 tp->udev = udev;
2116 tp->netdev = netdev;
40a82917 2117 tp->intf = intf;
ac718b69 2118 netdev->netdev_ops = &rtl8152_netdev_ops;
2119 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
5bd23881 2120
2121 netdev->features |= NETIF_F_IP_CSUM;
2122 netdev->hw_features = NETIF_F_IP_CSUM;
ac718b69 2123 SET_ETHTOOL_OPS(netdev, &ops);
ac718b69 2124
2125 tp->mii.dev = netdev;
2126 tp->mii.mdio_read = read_mii_word;
2127 tp->mii.mdio_write = write_mii_word;
2128 tp->mii.phy_id_mask = 0x3f;
2129 tp->mii.reg_num_mask = 0x1f;
2130 tp->mii.phy_id = R8152_PHY_ID;
2131 tp->mii.supports_gmii = 0;
2132
2133 r8152b_get_version(tp);
2134 r8152b_init(tp);
2135 set_ethernet_addr(tp);
2136
ebc2ec48 2137 ret = alloc_all_mem(tp);
2138 if (ret)
ac718b69 2139 goto out;
ac718b69 2140
2141 usb_set_intfdata(intf, tp);
ac718b69 2142
ebc2ec48 2143 ret = register_netdev(netdev);
2144 if (ret != 0) {
ac718b69 2145 netif_err(tp, probe, netdev, "couldn't register the device");
ebc2ec48 2146 goto out1;
ac718b69 2147 }
2148
2149 netif_info(tp, probe, netdev, "%s", DRIVER_VERSION);
2150
2151 return 0;
2152
ac718b69 2153out1:
ebc2ec48 2154 usb_set_intfdata(intf, NULL);
ac718b69 2155out:
2156 free_netdev(netdev);
ebc2ec48 2157 return ret;
ac718b69 2158}
2159
2160static void rtl8152_unload(struct r8152 *tp)
2161{
2162 u32 ocp_data;
2163
2164 if (tp->version != RTL_VER_01) {
2165 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2166 ocp_data |= POWER_CUT;
2167 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2168 }
2169
2170 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2171 ocp_data &= ~RWSUME_INDICATE;
2172 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2173}
2174
2175static void rtl8152_disconnect(struct usb_interface *intf)
2176{
2177 struct r8152 *tp = usb_get_intfdata(intf);
2178
2179 usb_set_intfdata(intf, NULL);
2180 if (tp) {
2181 set_bit(RTL8152_UNPLUG, &tp->flags);
2182 tasklet_kill(&tp->tl);
2183 unregister_netdev(tp->netdev);
2184 rtl8152_unload(tp);
ebc2ec48 2185 free_all_mem(tp);
ac718b69 2186 free_netdev(tp->netdev);
2187 }
2188}
2189
2190/* table of devices that work with this driver */
2191static struct usb_device_id rtl8152_table[] = {
2192 {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8152)},
2193 {}
2194};
2195
2196MODULE_DEVICE_TABLE(usb, rtl8152_table);
2197
2198static struct usb_driver rtl8152_driver = {
2199 .name = MODULENAME,
ebc2ec48 2200 .id_table = rtl8152_table,
ac718b69 2201 .probe = rtl8152_probe,
2202 .disconnect = rtl8152_disconnect,
ac718b69 2203 .suspend = rtl8152_suspend,
ebc2ec48 2204 .resume = rtl8152_resume,
2205 .reset_resume = rtl8152_resume,
ac718b69 2206};
2207
b4236daa 2208module_usb_driver(rtl8152_driver);
ac718b69 2209
2210MODULE_AUTHOR(DRIVER_AUTHOR);
2211MODULE_DESCRIPTION(DRIVER_DESC);
2212MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)