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r8152: adjust tx_bottom function
[linux-2.6-block.git] / drivers / net / usb / r8152.c
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ac718b69 1/*
2 * Copyright (c) 2013 Realtek Semiconductor Corp. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * version 2 as published by the Free Software Foundation.
7 *
8 */
9
10#include <linux/init.h>
11#include <linux/signal.h>
12#include <linux/slab.h>
13#include <linux/module.h>
ac718b69 14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/mii.h>
17#include <linux/ethtool.h>
18#include <linux/usb.h>
19#include <linux/crc32.h>
20#include <linux/if_vlan.h>
21#include <linux/uaccess.h>
ebc2ec48 22#include <linux/list.h>
5bd23881 23#include <linux/ip.h>
24#include <linux/ipv6.h>
ac718b69 25
26/* Version Information */
ebc2ec48 27#define DRIVER_VERSION "v1.01.0 (2013/08/12)"
ac718b69 28#define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
29#define DRIVER_DESC "Realtek RTL8152 Based USB 2.0 Ethernet Adapters"
30#define MODULENAME "r8152"
31
32#define R8152_PHY_ID 32
33
34#define PLA_IDR 0xc000
35#define PLA_RCR 0xc010
36#define PLA_RMS 0xc016
37#define PLA_RXFIFO_CTRL0 0xc0a0
38#define PLA_RXFIFO_CTRL1 0xc0a4
39#define PLA_RXFIFO_CTRL2 0xc0a8
40#define PLA_FMC 0xc0b4
41#define PLA_CFG_WOL 0xc0b6
42#define PLA_MAR 0xcd00
43#define PAL_BDC_CR 0xd1a0
44#define PLA_LEDSEL 0xdd90
45#define PLA_LED_FEATURE 0xdd92
46#define PLA_PHYAR 0xde00
47#define PLA_GPHY_INTR_IMR 0xe022
48#define PLA_EEE_CR 0xe040
49#define PLA_EEEP_CR 0xe080
50#define PLA_MAC_PWR_CTRL 0xe0c0
51#define PLA_TCR0 0xe610
52#define PLA_TCR1 0xe612
53#define PLA_TXFIFO_CTRL 0xe618
54#define PLA_RSTTELLY 0xe800
55#define PLA_CR 0xe813
56#define PLA_CRWECR 0xe81c
57#define PLA_CONFIG5 0xe822
58#define PLA_PHY_PWR 0xe84c
59#define PLA_OOB_CTRL 0xe84f
60#define PLA_CPCR 0xe854
61#define PLA_MISC_0 0xe858
62#define PLA_MISC_1 0xe85a
63#define PLA_OCP_GPHY_BASE 0xe86c
64#define PLA_TELLYCNT 0xe890
65#define PLA_SFF_STS_7 0xe8de
66#define PLA_PHYSTATUS 0xe908
67#define PLA_BP_BA 0xfc26
68#define PLA_BP_0 0xfc28
69#define PLA_BP_1 0xfc2a
70#define PLA_BP_2 0xfc2c
71#define PLA_BP_3 0xfc2e
72#define PLA_BP_4 0xfc30
73#define PLA_BP_5 0xfc32
74#define PLA_BP_6 0xfc34
75#define PLA_BP_7 0xfc36
76
77#define USB_DEV_STAT 0xb808
78#define USB_USB_CTRL 0xd406
79#define USB_PHY_CTRL 0xd408
80#define USB_TX_AGG 0xd40a
81#define USB_RX_BUF_TH 0xd40c
82#define USB_USB_TIMER 0xd428
83#define USB_PM_CTRL_STATUS 0xd432
84#define USB_TX_DMA 0xd434
85#define USB_UPS_CTRL 0xd800
86#define USB_BP_BA 0xfc26
87#define USB_BP_0 0xfc28
88#define USB_BP_1 0xfc2a
89#define USB_BP_2 0xfc2c
90#define USB_BP_3 0xfc2e
91#define USB_BP_4 0xfc30
92#define USB_BP_5 0xfc32
93#define USB_BP_6 0xfc34
94#define USB_BP_7 0xfc36
95
96/* OCP Registers */
97#define OCP_ALDPS_CONFIG 0x2010
98#define OCP_EEE_CONFIG1 0x2080
99#define OCP_EEE_CONFIG2 0x2092
100#define OCP_EEE_CONFIG3 0x2094
101#define OCP_EEE_AR 0xa41a
102#define OCP_EEE_DATA 0xa41c
103
104/* PLA_RCR */
105#define RCR_AAP 0x00000001
106#define RCR_APM 0x00000002
107#define RCR_AM 0x00000004
108#define RCR_AB 0x00000008
109#define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
110
111/* PLA_RXFIFO_CTRL0 */
112#define RXFIFO_THR1_NORMAL 0x00080002
113#define RXFIFO_THR1_OOB 0x01800003
114
115/* PLA_RXFIFO_CTRL1 */
116#define RXFIFO_THR2_FULL 0x00000060
117#define RXFIFO_THR2_HIGH 0x00000038
118#define RXFIFO_THR2_OOB 0x0000004a
119
120/* PLA_RXFIFO_CTRL2 */
121#define RXFIFO_THR3_FULL 0x00000078
122#define RXFIFO_THR3_HIGH 0x00000048
123#define RXFIFO_THR3_OOB 0x0000005a
124
125/* PLA_TXFIFO_CTRL */
126#define TXFIFO_THR_NORMAL 0x00400008
127
128/* PLA_FMC */
129#define FMC_FCR_MCU_EN 0x0001
130
131/* PLA_EEEP_CR */
132#define EEEP_CR_EEEP_TX 0x0002
133
134/* PLA_TCR0 */
135#define TCR0_TX_EMPTY 0x0800
136#define TCR0_AUTO_FIFO 0x0080
137
138/* PLA_TCR1 */
139#define VERSION_MASK 0x7cf0
140
141/* PLA_CR */
142#define CR_RST 0x10
143#define CR_RE 0x08
144#define CR_TE 0x04
145
146/* PLA_CRWECR */
147#define CRWECR_NORAML 0x00
148#define CRWECR_CONFIG 0xc0
149
150/* PLA_OOB_CTRL */
151#define NOW_IS_OOB 0x80
152#define TXFIFO_EMPTY 0x20
153#define RXFIFO_EMPTY 0x10
154#define LINK_LIST_READY 0x02
155#define DIS_MCU_CLROOB 0x01
156#define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
157
158/* PLA_MISC_1 */
159#define RXDY_GATED_EN 0x0008
160
161/* PLA_SFF_STS_7 */
162#define RE_INIT_LL 0x8000
163#define MCU_BORW_EN 0x4000
164
165/* PLA_CPCR */
166#define CPCR_RX_VLAN 0x0040
167
168/* PLA_CFG_WOL */
169#define MAGIC_EN 0x0001
170
171/* PAL_BDC_CR */
172#define ALDPS_PROXY_MODE 0x0001
173
174/* PLA_CONFIG5 */
175#define LAN_WAKE_EN 0x0002
176
177/* PLA_LED_FEATURE */
178#define LED_MODE_MASK 0x0700
179
180/* PLA_PHY_PWR */
181#define TX_10M_IDLE_EN 0x0080
182#define PFM_PWM_SWITCH 0x0040
183
184/* PLA_MAC_PWR_CTRL */
185#define D3_CLK_GATED_EN 0x00004000
186#define MCU_CLK_RATIO 0x07010f07
187#define MCU_CLK_RATIO_MASK 0x0f0f0f0f
188
189/* PLA_GPHY_INTR_IMR */
190#define GPHY_STS_MSK 0x0001
191#define SPEED_DOWN_MSK 0x0002
192#define SPDWN_RXDV_MSK 0x0004
193#define SPDWN_LINKCHG_MSK 0x0008
194
195/* PLA_PHYAR */
196#define PHYAR_FLAG 0x80000000
197
198/* PLA_EEE_CR */
199#define EEE_RX_EN 0x0001
200#define EEE_TX_EN 0x0002
201
202/* USB_DEV_STAT */
203#define STAT_SPEED_MASK 0x0006
204#define STAT_SPEED_HIGH 0x0000
205#define STAT_SPEED_FULL 0x0001
206
207/* USB_TX_AGG */
208#define TX_AGG_MAX_THRESHOLD 0x03
209
210/* USB_RX_BUF_TH */
211#define RX_BUF_THR 0x7a120180
212
213/* USB_TX_DMA */
214#define TEST_MODE_DISABLE 0x00000001
215#define TX_SIZE_ADJUST1 0x00000100
216
217/* USB_UPS_CTRL */
218#define POWER_CUT 0x0100
219
220/* USB_PM_CTRL_STATUS */
221#define RWSUME_INDICATE 0x0001
222
223/* USB_USB_CTRL */
224#define RX_AGG_DISABLE 0x0010
225
226/* OCP_ALDPS_CONFIG */
227#define ENPWRSAVE 0x8000
228#define ENPDNPS 0x0200
229#define LINKENA 0x0100
230#define DIS_SDSAVE 0x0010
231
232/* OCP_EEE_CONFIG1 */
233#define RG_TXLPI_MSK_HFDUP 0x8000
234#define RG_MATCLR_EN 0x4000
235#define EEE_10_CAP 0x2000
236#define EEE_NWAY_EN 0x1000
237#define TX_QUIET_EN 0x0200
238#define RX_QUIET_EN 0x0100
239#define SDRISETIME 0x0010 /* bit 4 ~ 6 */
240#define RG_RXLPI_MSK_HFDUP 0x0008
241#define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
242
243/* OCP_EEE_CONFIG2 */
244#define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
245#define RG_DACQUIET_EN 0x0400
246#define RG_LDVQUIET_EN 0x0200
247#define RG_CKRSEL 0x0020
248#define RG_EEEPRG_EN 0x0010
249
250/* OCP_EEE_CONFIG3 */
251#define FST_SNR_EYE_R 0x1500 /* bit 7 ~ 15 */
252#define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
253#define MSK_PH 0x0006 /* bit 0 ~ 3 */
254
255/* OCP_EEE_AR */
256/* bit[15:14] function */
257#define FUN_ADDR 0x0000
258#define FUN_DATA 0x4000
259/* bit[4:0] device addr */
260#define DEVICE_ADDR 0x0007
261
262/* OCP_EEE_DATA */
263#define EEE_ADDR 0x003C
264#define EEE_DATA 0x0002
265
266enum rtl_register_content {
267 _100bps = 0x08,
268 _10bps = 0x04,
269 LINK_STATUS = 0x02,
270 FULL_DUP = 0x01,
271};
272
ebc2ec48 273#define RTL8152_MAX_TX 10
274#define RTL8152_MAX_RX 10
40a82917 275#define INTBUFSIZE 2
276
277#define INTR_LINK 0x0004
ebc2ec48 278
ac718b69 279#define RTL8152_REQT_READ 0xc0
280#define RTL8152_REQT_WRITE 0x40
281#define RTL8152_REQ_GET_REGS 0x05
282#define RTL8152_REQ_SET_REGS 0x05
283
284#define BYTE_EN_DWORD 0xff
285#define BYTE_EN_WORD 0x33
286#define BYTE_EN_BYTE 0x11
287#define BYTE_EN_SIX_BYTES 0x3f
288#define BYTE_EN_START_MASK 0x0f
289#define BYTE_EN_END_MASK 0xf0
290
291#define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
292#define RTL8152_TX_TIMEOUT (HZ)
293
294/* rtl8152 flags */
295enum rtl8152_flags {
296 RTL8152_UNPLUG = 0,
ac718b69 297 RTL8152_SET_RX_MODE,
40a82917 298 WORK_ENABLE,
299 RTL8152_LINK_CHG,
ac718b69 300};
301
302/* Define these values to match your device */
303#define VENDOR_ID_REALTEK 0x0bda
304#define PRODUCT_ID_RTL8152 0x8152
305
306#define MCU_TYPE_PLA 0x0100
307#define MCU_TYPE_USB 0x0000
308
309struct rx_desc {
310 u32 opts1;
311#define RX_LEN_MASK 0x7fff
312 u32 opts2;
313 u32 opts3;
314 u32 opts4;
315 u32 opts5;
316 u32 opts6;
317};
318
319struct tx_desc {
320 u32 opts1;
321#define TX_FS (1 << 31) /* First segment of a packet */
322#define TX_LS (1 << 30) /* Final segment of a packet */
5bd23881 323#define TX_LEN_MASK 0x3ffff
324
ac718b69 325 u32 opts2;
5bd23881 326#define UDP_CS (1 << 31) /* Calculate UDP/IP checksum */
327#define TCP_CS (1 << 30) /* Calculate TCP/IP checksum */
328#define IPV4_CS (1 << 29) /* Calculate IPv4 checksum */
329#define IPV6_CS (1 << 28) /* Calculate IPv6 checksum */
ac718b69 330};
331
dff4e8ad 332struct r8152;
333
ebc2ec48 334struct rx_agg {
335 struct list_head list;
336 struct urb *urb;
dff4e8ad 337 struct r8152 *context;
ebc2ec48 338 void *buffer;
339 void *head;
340};
341
342struct tx_agg {
343 struct list_head list;
344 struct urb *urb;
dff4e8ad 345 struct r8152 *context;
ebc2ec48 346 void *buffer;
347 void *head;
348 u32 skb_num;
349 u32 skb_len;
350};
351
ac718b69 352struct r8152 {
353 unsigned long flags;
354 struct usb_device *udev;
355 struct tasklet_struct tl;
40a82917 356 struct usb_interface *intf;
ac718b69 357 struct net_device *netdev;
40a82917 358 struct urb *intr_urb;
ebc2ec48 359 struct tx_agg tx_info[RTL8152_MAX_TX];
360 struct rx_agg rx_info[RTL8152_MAX_RX];
361 struct list_head rx_done, tx_free;
362 struct sk_buff_head tx_queue;
363 spinlock_t rx_lock, tx_lock;
ac718b69 364 struct delayed_work schedule;
365 struct mii_if_info mii;
40a82917 366 int intr_interval;
ac718b69 367 u32 msg_enable;
368 u16 ocp_base;
40a82917 369 u8 *intr_buff;
ac718b69 370 u8 version;
371 u8 speed;
372};
373
374enum rtl_version {
375 RTL_VER_UNKNOWN = 0,
376 RTL_VER_01,
377 RTL_VER_02
378};
379
380/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
381 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
382 */
383static const int multicast_filter_limit = 32;
ebc2ec48 384static unsigned int rx_buf_sz = 16384;
ac718b69 385
386static
387int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
388{
31787f53 389 int ret;
390 void *tmp;
391
392 tmp = kmalloc(size, GFP_KERNEL);
393 if (!tmp)
394 return -ENOMEM;
395
396 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
ac718b69 397 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
31787f53 398 value, index, tmp, size, 500);
399
400 memcpy(data, tmp, size);
401 kfree(tmp);
402
403 return ret;
ac718b69 404}
405
406static
407int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
408{
31787f53 409 int ret;
410 void *tmp;
411
412 tmp = kmalloc(size, GFP_KERNEL);
413 if (!tmp)
414 return -ENOMEM;
415
416 memcpy(tmp, data, size);
417
418 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
ac718b69 419 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
31787f53 420 value, index, tmp, size, 500);
421
422 kfree(tmp);
423 return ret;
ac718b69 424}
425
426static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
427 void *data, u16 type)
428{
429 u16 limit = 64;
430 int ret = 0;
431
432 if (test_bit(RTL8152_UNPLUG, &tp->flags))
433 return -ENODEV;
434
435 /* both size and indix must be 4 bytes align */
436 if ((size & 3) || !size || (index & 3) || !data)
437 return -EPERM;
438
439 if ((u32)index + (u32)size > 0xffff)
440 return -EPERM;
441
442 while (size) {
443 if (size > limit) {
444 ret = get_registers(tp, index, type, limit, data);
445 if (ret < 0)
446 break;
447
448 index += limit;
449 data += limit;
450 size -= limit;
451 } else {
452 ret = get_registers(tp, index, type, size, data);
453 if (ret < 0)
454 break;
455
456 index += size;
457 data += size;
458 size = 0;
459 break;
460 }
461 }
462
463 return ret;
464}
465
466static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
467 u16 size, void *data, u16 type)
468{
469 int ret;
470 u16 byteen_start, byteen_end, byen;
471 u16 limit = 512;
472
473 if (test_bit(RTL8152_UNPLUG, &tp->flags))
474 return -ENODEV;
475
476 /* both size and indix must be 4 bytes align */
477 if ((size & 3) || !size || (index & 3) || !data)
478 return -EPERM;
479
480 if ((u32)index + (u32)size > 0xffff)
481 return -EPERM;
482
483 byteen_start = byteen & BYTE_EN_START_MASK;
484 byteen_end = byteen & BYTE_EN_END_MASK;
485
486 byen = byteen_start | (byteen_start << 4);
487 ret = set_registers(tp, index, type | byen, 4, data);
488 if (ret < 0)
489 goto error1;
490
491 index += 4;
492 data += 4;
493 size -= 4;
494
495 if (size) {
496 size -= 4;
497
498 while (size) {
499 if (size > limit) {
500 ret = set_registers(tp, index,
501 type | BYTE_EN_DWORD,
502 limit, data);
503 if (ret < 0)
504 goto error1;
505
506 index += limit;
507 data += limit;
508 size -= limit;
509 } else {
510 ret = set_registers(tp, index,
511 type | BYTE_EN_DWORD,
512 size, data);
513 if (ret < 0)
514 goto error1;
515
516 index += size;
517 data += size;
518 size = 0;
519 break;
520 }
521 }
522
523 byen = byteen_end | (byteen_end >> 4);
524 ret = set_registers(tp, index, type | byen, 4, data);
525 if (ret < 0)
526 goto error1;
527 }
528
529error1:
530 return ret;
531}
532
533static inline
534int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
535{
536 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
537}
538
539static inline
540int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
541{
542 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
543}
544
545static inline
546int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
547{
548 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
549}
550
551static inline
552int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
553{
554 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
555}
556
557static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
558{
c8826de8 559 __le32 data;
ac718b69 560
c8826de8 561 generic_ocp_read(tp, index, sizeof(data), &data, type);
ac718b69 562
563 return __le32_to_cpu(data);
564}
565
566static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
567{
c8826de8 568 __le32 tmp = __cpu_to_le32(data);
569
570 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
ac718b69 571}
572
573static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
574{
575 u32 data;
c8826de8 576 __le32 tmp;
ac718b69 577 u8 shift = index & 2;
578
579 index &= ~3;
580
c8826de8 581 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
ac718b69 582
c8826de8 583 data = __le32_to_cpu(tmp);
ac718b69 584 data >>= (shift * 8);
585 data &= 0xffff;
586
587 return (u16)data;
588}
589
590static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
591{
c8826de8 592 u32 mask = 0xffff;
593 __le32 tmp;
ac718b69 594 u16 byen = BYTE_EN_WORD;
595 u8 shift = index & 2;
596
597 data &= mask;
598
599 if (index & 2) {
600 byen <<= shift;
601 mask <<= (shift * 8);
602 data <<= (shift * 8);
603 index &= ~3;
604 }
605
c8826de8 606 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
ac718b69 607
c8826de8 608 data |= __le32_to_cpu(tmp) & ~mask;
609 tmp = __cpu_to_le32(data);
ac718b69 610
c8826de8 611 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
ac718b69 612}
613
614static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
615{
616 u32 data;
c8826de8 617 __le32 tmp;
ac718b69 618 u8 shift = index & 3;
619
620 index &= ~3;
621
c8826de8 622 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
ac718b69 623
c8826de8 624 data = __le32_to_cpu(tmp);
ac718b69 625 data >>= (shift * 8);
626 data &= 0xff;
627
628 return (u8)data;
629}
630
631static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
632{
c8826de8 633 u32 mask = 0xff;
634 __le32 tmp;
ac718b69 635 u16 byen = BYTE_EN_BYTE;
636 u8 shift = index & 3;
637
638 data &= mask;
639
640 if (index & 3) {
641 byen <<= shift;
642 mask <<= (shift * 8);
643 data <<= (shift * 8);
644 index &= ~3;
645 }
646
c8826de8 647 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
ac718b69 648
c8826de8 649 data |= __le32_to_cpu(tmp) & ~mask;
650 tmp = __cpu_to_le32(data);
ac718b69 651
c8826de8 652 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
ac718b69 653}
654
655static void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
656{
657 u32 ocp_data;
658 int i;
659
660 ocp_data = PHYAR_FLAG | ((reg_addr & 0x1f) << 16) |
661 (value & 0xffff);
662
663 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_PHYAR, ocp_data);
664
665 for (i = 20; i > 0; i--) {
666 udelay(25);
667 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_PHYAR);
668 if (!(ocp_data & PHYAR_FLAG))
669 break;
670 }
671 udelay(20);
672}
673
674static int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
675{
676 u32 ocp_data;
677 int i;
678
679 ocp_data = (reg_addr & 0x1f) << 16;
680 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_PHYAR, ocp_data);
681
682 for (i = 20; i > 0; i--) {
683 udelay(25);
684 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_PHYAR);
685 if (ocp_data & PHYAR_FLAG)
686 break;
687 }
688 udelay(20);
689
690 if (!(ocp_data & PHYAR_FLAG))
691 return -EAGAIN;
692
693 return (u16)(ocp_data & 0xffff);
694}
695
696static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
697{
698 struct r8152 *tp = netdev_priv(netdev);
699
700 if (phy_id != R8152_PHY_ID)
701 return -EINVAL;
702
703 return r8152_mdio_read(tp, reg);
704}
705
706static
707void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
708{
709 struct r8152 *tp = netdev_priv(netdev);
710
711 if (phy_id != R8152_PHY_ID)
712 return;
713
714 r8152_mdio_write(tp, reg, val);
715}
716
717static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
718{
719 u16 ocp_base, ocp_index;
720
721 ocp_base = addr & 0xf000;
722 if (ocp_base != tp->ocp_base) {
723 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
724 tp->ocp_base = ocp_base;
725 }
726
727 ocp_index = (addr & 0x0fff) | 0xb000;
728 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
729}
730
ebc2ec48 731static
732int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
733
ac718b69 734static inline void set_ethernet_addr(struct r8152 *tp)
735{
736 struct net_device *dev = tp->netdev;
31787f53 737 u8 node_id[8] = {0};
ac718b69 738
31787f53 739 if (pla_ocp_read(tp, PLA_IDR, sizeof(node_id), node_id) < 0)
ac718b69 740 netif_notice(tp, probe, dev, "inet addr fail\n");
741 else {
742 memcpy(dev->dev_addr, node_id, dev->addr_len);
743 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
744 }
ac718b69 745}
746
747static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
748{
749 struct r8152 *tp = netdev_priv(netdev);
750 struct sockaddr *addr = p;
751
752 if (!is_valid_ether_addr(addr->sa_data))
753 return -EADDRNOTAVAIL;
754
755 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
756
757 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
758 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
759 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
760
761 return 0;
762}
763
ac718b69 764static struct net_device_stats *rtl8152_get_stats(struct net_device *dev)
765{
766 return &dev->stats;
767}
768
769static void read_bulk_callback(struct urb *urb)
770{
ac718b69 771 struct net_device *netdev;
a5a4f468 772 unsigned long flags;
ac718b69 773 int status = urb->status;
ebc2ec48 774 struct rx_agg *agg;
775 struct r8152 *tp;
ac718b69 776 int result;
ac718b69 777
ebc2ec48 778 agg = urb->context;
779 if (!agg)
780 return;
781
782 tp = agg->context;
ac718b69 783 if (!tp)
784 return;
ebc2ec48 785
ac718b69 786 if (test_bit(RTL8152_UNPLUG, &tp->flags))
787 return;
ebc2ec48 788
789 if (!test_bit(WORK_ENABLE, &tp->flags))
790 return;
791
ac718b69 792 netdev = tp->netdev;
ebc2ec48 793 if (!netif_carrier_ok(netdev))
ac718b69 794 return;
795
ac718b69 796 switch (status) {
797 case 0:
ebc2ec48 798 if (urb->actual_length < ETH_ZLEN)
799 break;
800
a5a4f468 801 spin_lock_irqsave(&tp->rx_lock, flags);
ebc2ec48 802 list_add_tail(&agg->list, &tp->rx_done);
a5a4f468 803 spin_unlock_irqrestore(&tp->rx_lock, flags);
ebc2ec48 804 tasklet_schedule(&tp->tl);
805 return;
ac718b69 806 case -ESHUTDOWN:
807 set_bit(RTL8152_UNPLUG, &tp->flags);
808 netif_device_detach(tp->netdev);
ebc2ec48 809 return;
ac718b69 810 case -ENOENT:
811 return; /* the urb is in unlink state */
812 case -ETIME:
813 pr_warn_ratelimited("may be reset is needed?..\n");
ebc2ec48 814 break;
ac718b69 815 default:
816 pr_warn_ratelimited("Rx status %d\n", status);
ebc2ec48 817 break;
ac718b69 818 }
819
ebc2ec48 820 result = r8152_submit_rx(tp, agg, GFP_ATOMIC);
ac718b69 821 if (result == -ENODEV) {
822 netif_device_detach(tp->netdev);
823 } else if (result) {
a5a4f468 824 spin_lock_irqsave(&tp->rx_lock, flags);
ebc2ec48 825 list_add_tail(&agg->list, &tp->rx_done);
a5a4f468 826 spin_unlock_irqrestore(&tp->rx_lock, flags);
ebc2ec48 827 tasklet_schedule(&tp->tl);
ac718b69 828 }
ac718b69 829}
830
ebc2ec48 831static void write_bulk_callback(struct urb *urb)
ac718b69 832{
ebc2ec48 833 struct net_device_stats *stats;
a5a4f468 834 unsigned long flags;
ebc2ec48 835 struct tx_agg *agg;
ac718b69 836 struct r8152 *tp;
ebc2ec48 837 int status = urb->status;
ac718b69 838
ebc2ec48 839 agg = urb->context;
840 if (!agg)
ac718b69 841 return;
842
ebc2ec48 843 tp = agg->context;
844 if (!tp)
845 return;
846
847 stats = rtl8152_get_stats(tp->netdev);
848 if (status) {
849 pr_warn_ratelimited("Tx status %d\n", status);
850 stats->tx_errors += agg->skb_num;
ac718b69 851 } else {
ebc2ec48 852 stats->tx_packets += agg->skb_num;
853 stats->tx_bytes += agg->skb_len;
ac718b69 854 }
855
a5a4f468 856 spin_lock_irqsave(&tp->tx_lock, flags);
ebc2ec48 857 list_add_tail(&agg->list, &tp->tx_free);
a5a4f468 858 spin_unlock_irqrestore(&tp->tx_lock, flags);
ebc2ec48 859
860 if (!netif_carrier_ok(tp->netdev))
861 return;
862
863 if (!test_bit(WORK_ENABLE, &tp->flags))
864 return;
865
866 if (test_bit(RTL8152_UNPLUG, &tp->flags))
867 return;
868
869 if (!skb_queue_empty(&tp->tx_queue))
870 tasklet_schedule(&tp->tl);
ac718b69 871}
872
40a82917 873static void intr_callback(struct urb *urb)
874{
875 struct r8152 *tp;
876 __u16 *d;
877 int status = urb->status;
878 int res;
879
880 tp = urb->context;
881 if (!tp)
882 return;
883
884 if (!test_bit(WORK_ENABLE, &tp->flags))
885 return;
886
887 if (test_bit(RTL8152_UNPLUG, &tp->flags))
888 return;
889
890 switch (status) {
891 case 0: /* success */
892 break;
893 case -ECONNRESET: /* unlink */
894 case -ESHUTDOWN:
895 netif_device_detach(tp->netdev);
896 case -ENOENT:
897 return;
898 case -EOVERFLOW:
899 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
900 goto resubmit;
901 /* -EPIPE: should clear the halt */
902 default:
903 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
904 goto resubmit;
905 }
906
907 d = urb->transfer_buffer;
908 if (INTR_LINK & __le16_to_cpu(d[0])) {
909 if (!(tp->speed & LINK_STATUS)) {
910 set_bit(RTL8152_LINK_CHG, &tp->flags);
911 schedule_delayed_work(&tp->schedule, 0);
912 }
913 } else {
914 if (tp->speed & LINK_STATUS) {
915 set_bit(RTL8152_LINK_CHG, &tp->flags);
916 schedule_delayed_work(&tp->schedule, 0);
917 }
918 }
919
920resubmit:
921 res = usb_submit_urb(urb, GFP_ATOMIC);
922 if (res == -ENODEV)
923 netif_device_detach(tp->netdev);
924 else if (res)
925 netif_err(tp, intr, tp->netdev,
926 "can't resubmit intr, status %d\n", res);
927}
928
ebc2ec48 929static inline void *rx_agg_align(void *data)
930{
931 return (void *)ALIGN((uintptr_t)data, 8);
932}
933
934static inline void *tx_agg_align(void *data)
935{
936 return (void *)ALIGN((uintptr_t)data, 4);
937}
938
939static void free_all_mem(struct r8152 *tp)
940{
941 int i;
942
943 for (i = 0; i < RTL8152_MAX_RX; i++) {
944 if (tp->rx_info[i].urb) {
945 usb_free_urb(tp->rx_info[i].urb);
946 tp->rx_info[i].urb = NULL;
947 }
948
949 if (tp->rx_info[i].buffer) {
950 kfree(tp->rx_info[i].buffer);
951 tp->rx_info[i].buffer = NULL;
952 tp->rx_info[i].head = NULL;
953 }
954 }
955
956 for (i = 0; i < RTL8152_MAX_TX; i++) {
957 if (tp->tx_info[i].urb) {
958 usb_free_urb(tp->tx_info[i].urb);
959 tp->tx_info[i].urb = NULL;
960 }
961
962 if (tp->tx_info[i].buffer) {
963 kfree(tp->tx_info[i].buffer);
964 tp->tx_info[i].buffer = NULL;
965 tp->tx_info[i].head = NULL;
966 }
967 }
40a82917 968
969 if (tp->intr_urb) {
970 usb_free_urb(tp->intr_urb);
971 tp->intr_urb = NULL;
972 }
973
974 if (tp->intr_buff) {
975 kfree(tp->intr_buff);
976 tp->intr_buff = NULL;
977 }
ebc2ec48 978}
979
980static int alloc_all_mem(struct r8152 *tp)
981{
982 struct net_device *netdev = tp->netdev;
40a82917 983 struct usb_interface *intf = tp->intf;
984 struct usb_host_interface *alt = intf->cur_altsetting;
985 struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
ebc2ec48 986 struct urb *urb;
987 int node, i;
988 u8 *buf;
989
990 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
991
992 spin_lock_init(&tp->rx_lock);
993 spin_lock_init(&tp->tx_lock);
994 INIT_LIST_HEAD(&tp->rx_done);
995 INIT_LIST_HEAD(&tp->tx_free);
996 skb_queue_head_init(&tp->tx_queue);
997
998 for (i = 0; i < RTL8152_MAX_RX; i++) {
999 buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
1000 if (!buf)
1001 goto err1;
1002
1003 if (buf != rx_agg_align(buf)) {
1004 kfree(buf);
1005 buf = kmalloc_node(rx_buf_sz + 8, GFP_KERNEL, node);
1006 if (!buf)
1007 goto err1;
1008 }
1009
1010 urb = usb_alloc_urb(0, GFP_KERNEL);
1011 if (!urb) {
1012 kfree(buf);
1013 goto err1;
1014 }
1015
1016 INIT_LIST_HEAD(&tp->rx_info[i].list);
1017 tp->rx_info[i].context = tp;
1018 tp->rx_info[i].urb = urb;
1019 tp->rx_info[i].buffer = buf;
1020 tp->rx_info[i].head = rx_agg_align(buf);
1021 }
1022
1023 for (i = 0; i < RTL8152_MAX_TX; i++) {
1024 buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
1025 if (!buf)
1026 goto err1;
1027
1028 if (buf != tx_agg_align(buf)) {
1029 kfree(buf);
1030 buf = kmalloc_node(rx_buf_sz + 4, GFP_KERNEL, node);
1031 if (!buf)
1032 goto err1;
1033 }
1034
1035 urb = usb_alloc_urb(0, GFP_KERNEL);
1036 if (!urb) {
1037 kfree(buf);
1038 goto err1;
1039 }
1040
1041 INIT_LIST_HEAD(&tp->tx_info[i].list);
1042 tp->tx_info[i].context = tp;
1043 tp->tx_info[i].urb = urb;
1044 tp->tx_info[i].buffer = buf;
1045 tp->tx_info[i].head = tx_agg_align(buf);
1046
1047 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1048 }
1049
40a82917 1050 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1051 if (!tp->intr_urb)
1052 goto err1;
1053
1054 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1055 if (!tp->intr_buff)
1056 goto err1;
1057
1058 tp->intr_interval = (int)ep_intr->desc.bInterval;
1059 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1060 tp->intr_buff, INTBUFSIZE, intr_callback,
1061 tp, tp->intr_interval);
1062
ebc2ec48 1063 return 0;
1064
1065err1:
1066 free_all_mem(tp);
1067 return -ENOMEM;
1068}
1069
0de98f6c 1070static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1071{
1072 struct tx_agg *agg = NULL;
1073 unsigned long flags;
1074
1075 spin_lock_irqsave(&tp->tx_lock, flags);
1076 if (!list_empty(&tp->tx_free)) {
1077 struct list_head *cursor;
1078
1079 cursor = tp->tx_free.next;
1080 list_del_init(cursor);
1081 agg = list_entry(cursor, struct tx_agg, list);
1082 }
1083 spin_unlock_irqrestore(&tp->tx_lock, flags);
1084
1085 return agg;
1086}
1087
5bd23881 1088static void
1089r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, struct sk_buff *skb)
1090{
1091 memset(desc, 0, sizeof(*desc));
1092
1093 desc->opts1 = cpu_to_le32((skb->len & TX_LEN_MASK) | TX_FS | TX_LS);
1094
1095 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1096 __be16 protocol;
1097 u8 ip_protocol;
1098 u32 opts2 = 0;
1099
1100 if (skb->protocol == htons(ETH_P_8021Q))
1101 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
1102 else
1103 protocol = skb->protocol;
1104
1105 switch (protocol) {
1106 case htons(ETH_P_IP):
1107 opts2 |= IPV4_CS;
1108 ip_protocol = ip_hdr(skb)->protocol;
1109 break;
1110
1111 case htons(ETH_P_IPV6):
1112 opts2 |= IPV6_CS;
1113 ip_protocol = ipv6_hdr(skb)->nexthdr;
1114 break;
1115
1116 default:
1117 ip_protocol = IPPROTO_RAW;
1118 break;
1119 }
1120
1121 if (ip_protocol == IPPROTO_TCP) {
1122 opts2 |= TCP_CS;
1123 opts2 |= (skb_transport_offset(skb) & 0x7fff) << 17;
1124 } else if (ip_protocol == IPPROTO_UDP) {
1125 opts2 |= UDP_CS;
1126 } else {
1127 WARN_ON_ONCE(1);
1128 }
1129
1130 desc->opts2 = cpu_to_le32(opts2);
1131 }
1132}
1133
b1379d9a 1134static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1135{
1136 u32 remain;
1137 u8 *tx_data;
1138
1139 tx_data = agg->head;
1140 agg->skb_num = agg->skb_len = 0;
1141 remain = rx_buf_sz - sizeof(struct tx_desc);
1142
1143 while (remain >= ETH_ZLEN) {
1144 struct tx_desc *tx_desc;
1145 struct sk_buff *skb;
1146 unsigned int len;
1147
1148 skb = skb_dequeue(&tp->tx_queue);
1149 if (!skb)
1150 break;
1151
1152 len = skb->len;
1153 if (remain < len) {
1154 skb_queue_head(&tp->tx_queue, skb);
1155 break;
1156 }
1157
1158 tx_desc = (struct tx_desc *)tx_data;
1159 tx_data += sizeof(*tx_desc);
1160
1161 r8152_tx_csum(tp, tx_desc, skb);
1162 memcpy(tx_data, skb->data, len);
1163 agg->skb_num++;
1164 agg->skb_len += len;
1165 dev_kfree_skb_any(skb);
1166
1167 tx_data = tx_agg_align(tx_data + len);
1168 remain = rx_buf_sz - sizeof(*tx_desc) -
1169 (u32)((void *)tx_data - agg->head);
1170 }
1171
1172 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1173 agg->head, (int)(tx_data - (u8 *)agg->head),
1174 (usb_complete_t)write_bulk_callback, agg);
1175
1176 return usb_submit_urb(agg->urb, GFP_ATOMIC);
1177}
1178
ebc2ec48 1179static void rx_bottom(struct r8152 *tp)
1180{
a5a4f468 1181 unsigned long flags;
ebc2ec48 1182 struct list_head *cursor, *next;
ebc2ec48 1183
a5a4f468 1184 spin_lock_irqsave(&tp->rx_lock, flags);
ebc2ec48 1185 list_for_each_safe(cursor, next, &tp->rx_done) {
43a4478d 1186 struct rx_desc *rx_desc;
1187 struct rx_agg *agg;
1188 unsigned pkt_len;
1189 int len_used = 0;
1190 struct urb *urb;
1191 u8 *rx_data;
1192 int ret;
1193
ebc2ec48 1194 list_del_init(cursor);
a5a4f468 1195 spin_unlock_irqrestore(&tp->rx_lock, flags);
ebc2ec48 1196
1197 agg = list_entry(cursor, struct rx_agg, list);
1198 urb = agg->urb;
0de98f6c 1199 if (urb->actual_length < ETH_ZLEN)
1200 goto submit;
ebc2ec48 1201
ebc2ec48 1202 rx_desc = agg->head;
1203 rx_data = agg->head;
1204 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1205 len_used += sizeof(struct rx_desc) + pkt_len;
1206
1207 while (urb->actual_length >= len_used) {
43a4478d 1208 struct net_device *netdev = tp->netdev;
1209 struct net_device_stats *stats;
1210 struct sk_buff *skb;
1211
ebc2ec48 1212 if (pkt_len < ETH_ZLEN)
1213 break;
1214
43a4478d 1215 stats = rtl8152_get_stats(netdev);
1216
ebc2ec48 1217 pkt_len -= 4; /* CRC */
1218 rx_data += sizeof(struct rx_desc);
1219
1220 skb = netdev_alloc_skb_ip_align(netdev, pkt_len);
1221 if (!skb) {
1222 stats->rx_dropped++;
1223 break;
1224 }
1225 memcpy(skb->data, rx_data, pkt_len);
1226 skb_put(skb, pkt_len);
1227 skb->protocol = eth_type_trans(skb, netdev);
1228 netif_rx(skb);
1229 stats->rx_packets++;
1230 stats->rx_bytes += pkt_len;
1231
1232 rx_data = rx_agg_align(rx_data + pkt_len + 4);
1233 rx_desc = (struct rx_desc *)rx_data;
1234 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1235 len_used = (int)(rx_data - (u8 *)agg->head);
1236 len_used += sizeof(struct rx_desc) + pkt_len;
1237 }
1238
0de98f6c 1239submit:
ebc2ec48 1240 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
a5a4f468 1241 spin_lock_irqsave(&tp->rx_lock, flags);
ebc2ec48 1242 if (ret && ret != -ENODEV) {
1243 list_add_tail(&agg->list, next);
1244 tasklet_schedule(&tp->tl);
1245 }
1246 }
a5a4f468 1247 spin_unlock_irqrestore(&tp->rx_lock, flags);
ebc2ec48 1248}
1249
1250static void tx_bottom(struct r8152 *tp)
1251{
ebc2ec48 1252 int res;
1253
b1379d9a 1254 do {
1255 struct tx_agg *agg;
ebc2ec48 1256
b1379d9a 1257 if (skb_queue_empty(&tp->tx_queue))
ebc2ec48 1258 break;
1259
b1379d9a 1260 agg = r8152_get_tx_agg(tp);
1261 if (!agg)
ebc2ec48 1262 break;
ebc2ec48 1263
b1379d9a 1264 res = r8152_tx_agg_fill(tp, agg);
1265 if (res) {
1266 struct net_device_stats *stats;
1267 struct net_device *netdev;
1268 unsigned long flags;
ebc2ec48 1269
b1379d9a 1270 netdev = tp->netdev;
1271 stats = rtl8152_get_stats(netdev);
ebc2ec48 1272
b1379d9a 1273 if (res == -ENODEV) {
1274 netif_device_detach(netdev);
1275 } else {
1276 netif_warn(tp, tx_err, netdev,
1277 "failed tx_urb %d\n", res);
1278 stats->tx_dropped += agg->skb_num;
1279 spin_lock_irqsave(&tp->tx_lock, flags);
1280 list_add_tail(&agg->list, &tp->tx_free);
1281 spin_unlock_irqrestore(&tp->tx_lock, flags);
1282 }
ebc2ec48 1283 }
b1379d9a 1284 } while (res == 0);
ebc2ec48 1285}
1286
1287static void bottom_half(unsigned long data)
ac718b69 1288{
1289 struct r8152 *tp;
ac718b69 1290
ebc2ec48 1291 tp = (struct r8152 *)data;
1292
1293 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1294 return;
1295
1296 if (!test_bit(WORK_ENABLE, &tp->flags))
ac718b69 1297 return;
ebc2ec48 1298
1299 if (!netif_carrier_ok(tp->netdev))
ac718b69 1300 return;
ebc2ec48 1301
1302 rx_bottom(tp);
1303 tx_bottom(tp);
1304}
1305
1306static
1307int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
1308{
1309 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
1310 agg->head, rx_buf_sz,
1311 (usb_complete_t)read_bulk_callback, agg);
1312
1313 return usb_submit_urb(agg->urb, mem_flags);
ac718b69 1314}
1315
1316static void rtl8152_tx_timeout(struct net_device *netdev)
1317{
1318 struct r8152 *tp = netdev_priv(netdev);
ebc2ec48 1319 int i;
1320
ac718b69 1321 netif_warn(tp, tx_err, netdev, "Tx timeout.\n");
ebc2ec48 1322 for (i = 0; i < RTL8152_MAX_TX; i++)
1323 usb_unlink_urb(tp->tx_info[i].urb);
ac718b69 1324}
1325
1326static void rtl8152_set_rx_mode(struct net_device *netdev)
1327{
1328 struct r8152 *tp = netdev_priv(netdev);
1329
40a82917 1330 if (tp->speed & LINK_STATUS) {
ac718b69 1331 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
40a82917 1332 schedule_delayed_work(&tp->schedule, 0);
1333 }
ac718b69 1334}
1335
1336static void _rtl8152_set_rx_mode(struct net_device *netdev)
1337{
1338 struct r8152 *tp = netdev_priv(netdev);
31787f53 1339 u32 mc_filter[2]; /* Multicast hash filter */
1340 __le32 tmp[2];
ac718b69 1341 u32 ocp_data;
1342
ac718b69 1343 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
1344 netif_stop_queue(netdev);
1345 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1346 ocp_data &= ~RCR_ACPT_ALL;
1347 ocp_data |= RCR_AB | RCR_APM;
1348
1349 if (netdev->flags & IFF_PROMISC) {
1350 /* Unconditionally log net taps. */
1351 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
1352 ocp_data |= RCR_AM | RCR_AAP;
1353 mc_filter[1] = mc_filter[0] = 0xffffffff;
1354 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
1355 (netdev->flags & IFF_ALLMULTI)) {
1356 /* Too many to filter perfectly -- accept all multicasts. */
1357 ocp_data |= RCR_AM;
1358 mc_filter[1] = mc_filter[0] = 0xffffffff;
1359 } else {
1360 struct netdev_hw_addr *ha;
1361
1362 mc_filter[1] = mc_filter[0] = 0;
1363 netdev_for_each_mc_addr(ha, netdev) {
1364 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1365 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1366 ocp_data |= RCR_AM;
1367 }
1368 }
1369
31787f53 1370 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
1371 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
ac718b69 1372
31787f53 1373 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
ac718b69 1374 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1375 netif_wake_queue(netdev);
ac718b69 1376}
1377
1378static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
1379 struct net_device *netdev)
1380{
1381 struct r8152 *tp = netdev_priv(netdev);
1382 struct net_device_stats *stats = rtl8152_get_stats(netdev);
a5a4f468 1383 unsigned long flags;
ebc2ec48 1384 struct tx_agg *agg = NULL;
ac718b69 1385 struct tx_desc *tx_desc;
3ff25e3c 1386 unsigned int len;
ebc2ec48 1387 u8 *tx_data;
3ff25e3c 1388 int res;
ac718b69 1389
ebc2ec48 1390 skb_tx_timestamp(skb);
ac718b69 1391
0de98f6c 1392 /* If tx_queue is not empty, it means at least one previous packt */
1393 /* is waiting for sending. Don't send current one before it. */
1394 if (skb_queue_empty(&tp->tx_queue))
1395 agg = r8152_get_tx_agg(tp);
ebc2ec48 1396
1397 if (!agg) {
1398 skb_queue_tail(&tp->tx_queue, skb);
1399 return NETDEV_TX_OK;
1400 }
1401
1402 tx_desc = (struct tx_desc *)agg->head;
1403 tx_data = agg->head + sizeof(*tx_desc);
1404 agg->skb_num = agg->skb_len = 0;
1405
1406 len = skb->len;
5bd23881 1407 r8152_tx_csum(tp, tx_desc, skb);
ebc2ec48 1408 memcpy(tx_data, skb->data, len);
1409 dev_kfree_skb_any(skb);
1410 agg->skb_num++;
1411 agg->skb_len += len;
1412 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1413 agg->head, len + sizeof(*tx_desc),
1414 (usb_complete_t)write_bulk_callback, agg);
1415 res = usb_submit_urb(agg->urb, GFP_ATOMIC);
ac718b69 1416 if (res) {
1417 /* Can we get/handle EPIPE here? */
1418 if (res == -ENODEV) {
1419 netif_device_detach(tp->netdev);
1420 } else {
1421 netif_warn(tp, tx_err, netdev,
1422 "failed tx_urb %d\n", res);
ebc2ec48 1423 stats->tx_dropped++;
a5a4f468 1424 spin_lock_irqsave(&tp->tx_lock, flags);
ebc2ec48 1425 list_add_tail(&agg->list, &tp->tx_free);
a5a4f468 1426 spin_unlock_irqrestore(&tp->tx_lock, flags);
ac718b69 1427 }
ac718b69 1428 }
1429
1430 return NETDEV_TX_OK;
1431}
1432
1433static void r8152b_reset_packet_filter(struct r8152 *tp)
1434{
1435 u32 ocp_data;
1436
1437 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
1438 ocp_data &= ~FMC_FCR_MCU_EN;
1439 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1440 ocp_data |= FMC_FCR_MCU_EN;
1441 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1442}
1443
1444static void rtl8152_nic_reset(struct r8152 *tp)
1445{
1446 int i;
1447
1448 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
1449
1450 for (i = 0; i < 1000; i++) {
1451 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
1452 break;
1453 udelay(100);
1454 }
1455}
1456
1457static inline u8 rtl8152_get_speed(struct r8152 *tp)
1458{
1459 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
1460}
1461
1462static int rtl8152_enable(struct r8152 *tp)
1463{
ebc2ec48 1464 u32 ocp_data;
1465 int i, ret;
ac718b69 1466 u8 speed;
1467
1468 speed = rtl8152_get_speed(tp);
ebc2ec48 1469 if (speed & _10bps) {
ac718b69 1470 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
ebc2ec48 1471 ocp_data |= EEEP_CR_EEEP_TX;
ac718b69 1472 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
1473 } else {
1474 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
ebc2ec48 1475 ocp_data &= ~EEEP_CR_EEEP_TX;
ac718b69 1476 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
1477 }
1478
1479 r8152b_reset_packet_filter(tp);
1480
1481 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
1482 ocp_data |= CR_RE | CR_TE;
1483 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
1484
1485 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
1486 ocp_data &= ~RXDY_GATED_EN;
1487 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
1488
ebc2ec48 1489 INIT_LIST_HEAD(&tp->rx_done);
1490 ret = 0;
1491 for (i = 0; i < RTL8152_MAX_RX; i++) {
1492 INIT_LIST_HEAD(&tp->rx_info[i].list);
1493 ret |= r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
1494 }
ac718b69 1495
ebc2ec48 1496 return ret;
ac718b69 1497}
1498
1499static void rtl8152_disable(struct r8152 *tp)
1500{
ebc2ec48 1501 struct net_device_stats *stats = rtl8152_get_stats(tp->netdev);
1502 struct sk_buff *skb;
1503 u32 ocp_data;
1504 int i;
ac718b69 1505
1506 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1507 ocp_data &= ~RCR_ACPT_ALL;
1508 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1509
ebc2ec48 1510 while ((skb = skb_dequeue(&tp->tx_queue))) {
1511 dev_kfree_skb(skb);
1512 stats->tx_dropped++;
1513 }
1514
1515 for (i = 0; i < RTL8152_MAX_TX; i++)
1516 usb_kill_urb(tp->tx_info[i].urb);
ac718b69 1517
1518 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
1519 ocp_data |= RXDY_GATED_EN;
1520 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
1521
1522 for (i = 0; i < 1000; i++) {
1523 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1524 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
1525 break;
1526 mdelay(1);
1527 }
1528
1529 for (i = 0; i < 1000; i++) {
1530 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
1531 break;
1532 mdelay(1);
1533 }
1534
ebc2ec48 1535 for (i = 0; i < RTL8152_MAX_RX; i++)
1536 usb_kill_urb(tp->rx_info[i].urb);
ac718b69 1537
1538 rtl8152_nic_reset(tp);
1539}
1540
1541static void r8152b_exit_oob(struct r8152 *tp)
1542{
1543 u32 ocp_data;
1544 int i;
1545
1546 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1547 ocp_data &= ~RCR_ACPT_ALL;
1548 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1549
1550 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
1551 ocp_data |= RXDY_GATED_EN;
1552 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
1553
1554 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1555 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
1556
1557 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1558 ocp_data &= ~NOW_IS_OOB;
1559 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
1560
1561 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
1562 ocp_data &= ~MCU_BORW_EN;
1563 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
1564
1565 for (i = 0; i < 1000; i++) {
1566 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1567 if (ocp_data & LINK_LIST_READY)
1568 break;
1569 mdelay(1);
1570 }
1571
1572 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
1573 ocp_data |= RE_INIT_LL;
1574 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
1575
1576 for (i = 0; i < 1000; i++) {
1577 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1578 if (ocp_data & LINK_LIST_READY)
1579 break;
1580 mdelay(1);
1581 }
1582
1583 rtl8152_nic_reset(tp);
1584
1585 /* rx share fifo credit full threshold */
1586 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
1587
1588 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_DEV_STAT);
1589 ocp_data &= STAT_SPEED_MASK;
1590 if (ocp_data == STAT_SPEED_FULL) {
1591 /* rx share fifo credit near full threshold */
1592 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
1593 RXFIFO_THR2_FULL);
1594 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
1595 RXFIFO_THR3_FULL);
1596 } else {
1597 /* rx share fifo credit near full threshold */
1598 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
1599 RXFIFO_THR2_HIGH);
1600 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
1601 RXFIFO_THR3_HIGH);
1602 }
1603
1604 /* TX share fifo free credit full threshold */
1605 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
1606
1607 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
1608 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_BUF_THR);
1609 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
1610 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
1611
1612 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
1613 ocp_data &= ~CPCR_RX_VLAN;
1614 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
1615
1616 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
1617
1618 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
1619 ocp_data |= TCR0_AUTO_FIFO;
1620 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
1621}
1622
1623static void r8152b_enter_oob(struct r8152 *tp)
1624{
1625 u32 ocp_data;
1626 int i;
1627
1628 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1629 ocp_data &= ~NOW_IS_OOB;
1630 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
1631
1632 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
1633 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
1634 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
1635
1636 rtl8152_disable(tp);
1637
1638 for (i = 0; i < 1000; i++) {
1639 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1640 if (ocp_data & LINK_LIST_READY)
1641 break;
1642 mdelay(1);
1643 }
1644
1645 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
1646 ocp_data |= RE_INIT_LL;
1647 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
1648
1649 for (i = 0; i < 1000; i++) {
1650 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1651 if (ocp_data & LINK_LIST_READY)
1652 break;
1653 mdelay(1);
1654 }
1655
1656 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
1657
1658 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
1659 ocp_data |= MAGIC_EN;
1660 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
1661
1662 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
1663 ocp_data |= CPCR_RX_VLAN;
1664 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
1665
1666 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
1667 ocp_data |= ALDPS_PROXY_MODE;
1668 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
1669
1670 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1671 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
1672 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
1673
1674 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5, LAN_WAKE_EN);
1675
1676 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
1677 ocp_data &= ~RXDY_GATED_EN;
1678 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
1679
1680 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1681 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
1682 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1683}
1684
1685static void r8152b_disable_aldps(struct r8152 *tp)
1686{
1687 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
1688 msleep(20);
1689}
1690
1691static inline void r8152b_enable_aldps(struct r8152 *tp)
1692{
1693 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
1694 LINKENA | DIS_SDSAVE);
1695}
1696
1697static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
1698{
1699 u16 bmcr, anar;
1700 int ret = 0;
1701
1702 cancel_delayed_work_sync(&tp->schedule);
1703 anar = r8152_mdio_read(tp, MII_ADVERTISE);
1704 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1705 ADVERTISE_100HALF | ADVERTISE_100FULL);
1706
1707 if (autoneg == AUTONEG_DISABLE) {
1708 if (speed == SPEED_10) {
1709 bmcr = 0;
1710 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1711 } else if (speed == SPEED_100) {
1712 bmcr = BMCR_SPEED100;
1713 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
1714 } else {
1715 ret = -EINVAL;
1716 goto out;
1717 }
1718
1719 if (duplex == DUPLEX_FULL)
1720 bmcr |= BMCR_FULLDPLX;
1721 } else {
1722 if (speed == SPEED_10) {
1723 if (duplex == DUPLEX_FULL)
1724 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1725 else
1726 anar |= ADVERTISE_10HALF;
1727 } else if (speed == SPEED_100) {
1728 if (duplex == DUPLEX_FULL) {
1729 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1730 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
1731 } else {
1732 anar |= ADVERTISE_10HALF;
1733 anar |= ADVERTISE_100HALF;
1734 }
1735 } else {
1736 ret = -EINVAL;
1737 goto out;
1738 }
1739
1740 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1741 }
1742
1743 r8152_mdio_write(tp, MII_ADVERTISE, anar);
1744 r8152_mdio_write(tp, MII_BMCR, bmcr);
1745
1746out:
ac718b69 1747
1748 return ret;
1749}
1750
1751static void rtl8152_down(struct r8152 *tp)
1752{
1753 u32 ocp_data;
1754
1755 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
1756 ocp_data &= ~POWER_CUT;
1757 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
1758
1759 r8152b_disable_aldps(tp);
1760 r8152b_enter_oob(tp);
1761 r8152b_enable_aldps(tp);
1762}
1763
1764static void set_carrier(struct r8152 *tp)
1765{
1766 struct net_device *netdev = tp->netdev;
1767 u8 speed;
1768
40a82917 1769 clear_bit(RTL8152_LINK_CHG, &tp->flags);
ac718b69 1770 speed = rtl8152_get_speed(tp);
1771
1772 if (speed & LINK_STATUS) {
1773 if (!(tp->speed & LINK_STATUS)) {
1774 rtl8152_enable(tp);
1775 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
1776 netif_carrier_on(netdev);
1777 }
1778 } else {
1779 if (tp->speed & LINK_STATUS) {
1780 netif_carrier_off(netdev);
ebc2ec48 1781 tasklet_disable(&tp->tl);
ac718b69 1782 rtl8152_disable(tp);
ebc2ec48 1783 tasklet_enable(&tp->tl);
ac718b69 1784 }
1785 }
1786 tp->speed = speed;
1787}
1788
1789static void rtl_work_func_t(struct work_struct *work)
1790{
1791 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
1792
1793 if (!test_bit(WORK_ENABLE, &tp->flags))
1794 goto out1;
1795
1796 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1797 goto out1;
1798
40a82917 1799 if (test_bit(RTL8152_LINK_CHG, &tp->flags))
1800 set_carrier(tp);
ac718b69 1801
1802 if (test_bit(RTL8152_SET_RX_MODE, &tp->flags))
1803 _rtl8152_set_rx_mode(tp->netdev);
1804
ac718b69 1805out1:
1806 return;
1807}
1808
1809static int rtl8152_open(struct net_device *netdev)
1810{
1811 struct r8152 *tp = netdev_priv(netdev);
1812 int res = 0;
1813
40a82917 1814 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
1815 if (res) {
1816 if (res == -ENODEV)
1817 netif_device_detach(tp->netdev);
1818 netif_warn(tp, ifup, netdev,
1819 "intr_urb submit failed: %d\n", res);
1820 return res;
ac718b69 1821 }
1822
1823 rtl8152_set_speed(tp, AUTONEG_ENABLE, SPEED_100, DUPLEX_FULL);
40a82917 1824 tp->speed = 0;
1825 netif_carrier_off(netdev);
ac718b69 1826 netif_start_queue(netdev);
1827 set_bit(WORK_ENABLE, &tp->flags);
ac718b69 1828
1829 return res;
1830}
1831
1832static int rtl8152_close(struct net_device *netdev)
1833{
1834 struct r8152 *tp = netdev_priv(netdev);
1835 int res = 0;
1836
40a82917 1837 usb_kill_urb(tp->intr_urb);
ac718b69 1838 clear_bit(WORK_ENABLE, &tp->flags);
1839 cancel_delayed_work_sync(&tp->schedule);
1840 netif_stop_queue(netdev);
ebc2ec48 1841 tasklet_disable(&tp->tl);
ac718b69 1842 rtl8152_disable(tp);
ebc2ec48 1843 tasklet_enable(&tp->tl);
ac718b69 1844
1845 return res;
1846}
1847
1848static void rtl_clear_bp(struct r8152 *tp)
1849{
1850 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_0, 0);
1851 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_2, 0);
1852 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_4, 0);
1853 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_6, 0);
1854 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_0, 0);
1855 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_2, 0);
1856 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_4, 0);
1857 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_6, 0);
1858 mdelay(3);
1859 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_BA, 0);
1860 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_BA, 0);
1861}
1862
1863static void r8152b_enable_eee(struct r8152 *tp)
1864{
1865 u32 ocp_data;
1866
1867 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
1868 ocp_data |= EEE_RX_EN | EEE_TX_EN;
1869 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
1870 ocp_reg_write(tp, OCP_EEE_CONFIG1, RG_TXLPI_MSK_HFDUP | RG_MATCLR_EN |
1871 EEE_10_CAP | EEE_NWAY_EN |
1872 TX_QUIET_EN | RX_QUIET_EN |
1873 SDRISETIME | RG_RXLPI_MSK_HFDUP |
1874 SDFALLTIME);
1875 ocp_reg_write(tp, OCP_EEE_CONFIG2, RG_LPIHYS_NUM | RG_DACQUIET_EN |
1876 RG_LDVQUIET_EN | RG_CKRSEL |
1877 RG_EEEPRG_EN);
1878 ocp_reg_write(tp, OCP_EEE_CONFIG3, FST_SNR_EYE_R | RG_LFS_SEL | MSK_PH);
1879 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | DEVICE_ADDR);
1880 ocp_reg_write(tp, OCP_EEE_DATA, EEE_ADDR);
1881 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | DEVICE_ADDR);
1882 ocp_reg_write(tp, OCP_EEE_DATA, EEE_DATA);
1883 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
1884}
1885
1886static void r8152b_enable_fc(struct r8152 *tp)
1887{
1888 u16 anar;
1889
1890 anar = r8152_mdio_read(tp, MII_ADVERTISE);
1891 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1892 r8152_mdio_write(tp, MII_ADVERTISE, anar);
1893}
1894
1895static void r8152b_hw_phy_cfg(struct r8152 *tp)
1896{
1897 r8152_mdio_write(tp, MII_BMCR, BMCR_ANENABLE);
1898 r8152b_disable_aldps(tp);
1899}
1900
1901static void r8152b_init(struct r8152 *tp)
1902{
ebc2ec48 1903 u32 ocp_data;
1904 int i;
ac718b69 1905
1906 rtl_clear_bp(tp);
1907
1908 if (tp->version == RTL_VER_01) {
1909 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
1910 ocp_data &= ~LED_MODE_MASK;
1911 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
1912 }
1913
1914 r8152b_hw_phy_cfg(tp);
1915
1916 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
1917 ocp_data &= ~POWER_CUT;
1918 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
1919
1920 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
1921 ocp_data &= ~RWSUME_INDICATE;
1922 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
1923
1924 r8152b_exit_oob(tp);
1925
1926 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
1927 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
1928 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
1929 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
1930 ocp_data &= ~MCU_CLK_RATIO_MASK;
1931 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
1932 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
1933 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
1934 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
1935 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
1936
1937 r8152b_enable_eee(tp);
1938 r8152b_enable_aldps(tp);
1939 r8152b_enable_fc(tp);
1940
1941 r8152_mdio_write(tp, MII_BMCR, BMCR_RESET | BMCR_ANENABLE |
1942 BMCR_ANRESTART);
1943 for (i = 0; i < 100; i++) {
1944 udelay(100);
1945 if (!(r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET))
1946 break;
1947 }
1948
ebc2ec48 1949 /* enable rx aggregation */
ac718b69 1950 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
ebc2ec48 1951 ocp_data &= ~RX_AGG_DISABLE;
ac718b69 1952 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
1953}
1954
1955static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
1956{
1957 struct r8152 *tp = usb_get_intfdata(intf);
1958
1959 netif_device_detach(tp->netdev);
1960
1961 if (netif_running(tp->netdev)) {
1962 clear_bit(WORK_ENABLE, &tp->flags);
40a82917 1963 usb_kill_urb(tp->intr_urb);
ac718b69 1964 cancel_delayed_work_sync(&tp->schedule);
ebc2ec48 1965 tasklet_disable(&tp->tl);
ac718b69 1966 }
1967
1968 rtl8152_down(tp);
1969
1970 return 0;
1971}
1972
1973static int rtl8152_resume(struct usb_interface *intf)
1974{
1975 struct r8152 *tp = usb_get_intfdata(intf);
1976
1977 r8152b_init(tp);
1978 netif_device_attach(tp->netdev);
1979 if (netif_running(tp->netdev)) {
40a82917 1980 rtl8152_set_speed(tp, AUTONEG_ENABLE, SPEED_100, DUPLEX_FULL);
1981 tp->speed = 0;
1982 netif_carrier_off(tp->netdev);
ac718b69 1983 set_bit(WORK_ENABLE, &tp->flags);
40a82917 1984 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
ebc2ec48 1985 tasklet_enable(&tp->tl);
ac718b69 1986 }
1987
1988 return 0;
1989}
1990
1991static void rtl8152_get_drvinfo(struct net_device *netdev,
1992 struct ethtool_drvinfo *info)
1993{
1994 struct r8152 *tp = netdev_priv(netdev);
1995
1996 strncpy(info->driver, MODULENAME, ETHTOOL_BUSINFO_LEN);
1997 strncpy(info->version, DRIVER_VERSION, ETHTOOL_BUSINFO_LEN);
1998 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
1999}
2000
2001static
2002int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
2003{
2004 struct r8152 *tp = netdev_priv(netdev);
2005
2006 if (!tp->mii.mdio_read)
2007 return -EOPNOTSUPP;
2008
2009 return mii_ethtool_gset(&tp->mii, cmd);
2010}
2011
2012static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2013{
2014 struct r8152 *tp = netdev_priv(dev);
2015
2016 return rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
2017}
2018
2019static struct ethtool_ops ops = {
2020 .get_drvinfo = rtl8152_get_drvinfo,
2021 .get_settings = rtl8152_get_settings,
2022 .set_settings = rtl8152_set_settings,
2023 .get_link = ethtool_op_get_link,
2024};
2025
2026static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2027{
2028 struct r8152 *tp = netdev_priv(netdev);
2029 struct mii_ioctl_data *data = if_mii(rq);
2030 int res = 0;
2031
2032 switch (cmd) {
2033 case SIOCGMIIPHY:
2034 data->phy_id = R8152_PHY_ID; /* Internal PHY */
2035 break;
2036
2037 case SIOCGMIIREG:
2038 data->val_out = r8152_mdio_read(tp, data->reg_num);
2039 break;
2040
2041 case SIOCSMIIREG:
2042 if (!capable(CAP_NET_ADMIN)) {
2043 res = -EPERM;
2044 break;
2045 }
2046 r8152_mdio_write(tp, data->reg_num, data->val_in);
2047 break;
2048
2049 default:
2050 res = -EOPNOTSUPP;
2051 }
2052
2053 return res;
2054}
2055
2056static const struct net_device_ops rtl8152_netdev_ops = {
2057 .ndo_open = rtl8152_open,
2058 .ndo_stop = rtl8152_close,
2059 .ndo_do_ioctl = rtl8152_ioctl,
2060 .ndo_start_xmit = rtl8152_start_xmit,
2061 .ndo_tx_timeout = rtl8152_tx_timeout,
2062 .ndo_set_rx_mode = rtl8152_set_rx_mode,
2063 .ndo_set_mac_address = rtl8152_set_mac_address,
2064
2065 .ndo_change_mtu = eth_change_mtu,
2066 .ndo_validate_addr = eth_validate_addr,
2067};
2068
2069static void r8152b_get_version(struct r8152 *tp)
2070{
2071 u32 ocp_data;
2072 u16 version;
2073
2074 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
2075 version = (u16)(ocp_data & VERSION_MASK);
2076
2077 switch (version) {
2078 case 0x4c00:
2079 tp->version = RTL_VER_01;
2080 break;
2081 case 0x4c10:
2082 tp->version = RTL_VER_02;
2083 break;
2084 default:
2085 netif_info(tp, probe, tp->netdev,
2086 "Unknown version 0x%04x\n", version);
2087 break;
2088 }
2089}
2090
2091static int rtl8152_probe(struct usb_interface *intf,
2092 const struct usb_device_id *id)
2093{
2094 struct usb_device *udev = interface_to_usbdev(intf);
2095 struct r8152 *tp;
2096 struct net_device *netdev;
ebc2ec48 2097 int ret;
ac718b69 2098
2099 if (udev->actconfig->desc.bConfigurationValue != 1) {
2100 usb_driver_set_configuration(udev, 1);
2101 return -ENODEV;
2102 }
2103
2104 netdev = alloc_etherdev(sizeof(struct r8152));
2105 if (!netdev) {
2106 dev_err(&intf->dev, "Out of memory");
2107 return -ENOMEM;
2108 }
2109
ebc2ec48 2110 SET_NETDEV_DEV(netdev, &intf->dev);
ac718b69 2111 tp = netdev_priv(netdev);
2112 tp->msg_enable = 0x7FFF;
2113
ebc2ec48 2114 tasklet_init(&tp->tl, bottom_half, (unsigned long)tp);
ac718b69 2115 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
2116
2117 tp->udev = udev;
2118 tp->netdev = netdev;
40a82917 2119 tp->intf = intf;
ac718b69 2120 netdev->netdev_ops = &rtl8152_netdev_ops;
2121 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
5bd23881 2122
2123 netdev->features |= NETIF_F_IP_CSUM;
2124 netdev->hw_features = NETIF_F_IP_CSUM;
ac718b69 2125 SET_ETHTOOL_OPS(netdev, &ops);
ac718b69 2126
2127 tp->mii.dev = netdev;
2128 tp->mii.mdio_read = read_mii_word;
2129 tp->mii.mdio_write = write_mii_word;
2130 tp->mii.phy_id_mask = 0x3f;
2131 tp->mii.reg_num_mask = 0x1f;
2132 tp->mii.phy_id = R8152_PHY_ID;
2133 tp->mii.supports_gmii = 0;
2134
2135 r8152b_get_version(tp);
2136 r8152b_init(tp);
2137 set_ethernet_addr(tp);
2138
ebc2ec48 2139 ret = alloc_all_mem(tp);
2140 if (ret)
ac718b69 2141 goto out;
ac718b69 2142
2143 usb_set_intfdata(intf, tp);
ac718b69 2144
ebc2ec48 2145 ret = register_netdev(netdev);
2146 if (ret != 0) {
ac718b69 2147 netif_err(tp, probe, netdev, "couldn't register the device");
ebc2ec48 2148 goto out1;
ac718b69 2149 }
2150
2151 netif_info(tp, probe, netdev, "%s", DRIVER_VERSION);
2152
2153 return 0;
2154
ac718b69 2155out1:
ebc2ec48 2156 usb_set_intfdata(intf, NULL);
ac718b69 2157out:
2158 free_netdev(netdev);
ebc2ec48 2159 return ret;
ac718b69 2160}
2161
2162static void rtl8152_unload(struct r8152 *tp)
2163{
2164 u32 ocp_data;
2165
2166 if (tp->version != RTL_VER_01) {
2167 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2168 ocp_data |= POWER_CUT;
2169 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2170 }
2171
2172 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2173 ocp_data &= ~RWSUME_INDICATE;
2174 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2175}
2176
2177static void rtl8152_disconnect(struct usb_interface *intf)
2178{
2179 struct r8152 *tp = usb_get_intfdata(intf);
2180
2181 usb_set_intfdata(intf, NULL);
2182 if (tp) {
2183 set_bit(RTL8152_UNPLUG, &tp->flags);
2184 tasklet_kill(&tp->tl);
2185 unregister_netdev(tp->netdev);
2186 rtl8152_unload(tp);
ebc2ec48 2187 free_all_mem(tp);
ac718b69 2188 free_netdev(tp->netdev);
2189 }
2190}
2191
2192/* table of devices that work with this driver */
2193static struct usb_device_id rtl8152_table[] = {
2194 {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8152)},
2195 {}
2196};
2197
2198MODULE_DEVICE_TABLE(usb, rtl8152_table);
2199
2200static struct usb_driver rtl8152_driver = {
2201 .name = MODULENAME,
ebc2ec48 2202 .id_table = rtl8152_table,
ac718b69 2203 .probe = rtl8152_probe,
2204 .disconnect = rtl8152_disconnect,
ac718b69 2205 .suspend = rtl8152_suspend,
ebc2ec48 2206 .resume = rtl8152_resume,
2207 .reset_resume = rtl8152_resume,
ac718b69 2208};
2209
b4236daa 2210module_usb_driver(rtl8152_driver);
ac718b69 2211
2212MODULE_AUTHOR(DRIVER_AUTHOR);
2213MODULE_DESCRIPTION(DRIVER_DESC);
2214MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)