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ac718b69 | 1 | /* |
c7de7dec | 2 | * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved. |
ac718b69 | 3 | * |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * version 2 as published by the Free Software Foundation. | |
7 | * | |
8 | */ | |
9 | ||
ac718b69 | 10 | #include <linux/signal.h> |
11 | #include <linux/slab.h> | |
12 | #include <linux/module.h> | |
ac718b69 | 13 | #include <linux/netdevice.h> |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/mii.h> | |
16 | #include <linux/ethtool.h> | |
17 | #include <linux/usb.h> | |
18 | #include <linux/crc32.h> | |
19 | #include <linux/if_vlan.h> | |
20 | #include <linux/uaccess.h> | |
ebc2ec48 | 21 | #include <linux/list.h> |
5bd23881 | 22 | #include <linux/ip.h> |
23 | #include <linux/ipv6.h> | |
ac718b69 | 24 | |
25 | /* Version Information */ | |
21ff2e89 | 26 | #define DRIVER_VERSION "v1.05.0 (2014/02/18)" |
ac718b69 | 27 | #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>" |
44d942a9 | 28 | #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters" |
ac718b69 | 29 | #define MODULENAME "r8152" |
30 | ||
31 | #define R8152_PHY_ID 32 | |
32 | ||
33 | #define PLA_IDR 0xc000 | |
34 | #define PLA_RCR 0xc010 | |
35 | #define PLA_RMS 0xc016 | |
36 | #define PLA_RXFIFO_CTRL0 0xc0a0 | |
37 | #define PLA_RXFIFO_CTRL1 0xc0a4 | |
38 | #define PLA_RXFIFO_CTRL2 0xc0a8 | |
39 | #define PLA_FMC 0xc0b4 | |
40 | #define PLA_CFG_WOL 0xc0b6 | |
43779f8d | 41 | #define PLA_TEREDO_CFG 0xc0bc |
ac718b69 | 42 | #define PLA_MAR 0xcd00 |
43779f8d | 43 | #define PLA_BACKUP 0xd000 |
ac718b69 | 44 | #define PAL_BDC_CR 0xd1a0 |
43779f8d | 45 | #define PLA_TEREDO_TIMER 0xd2cc |
46 | #define PLA_REALWOW_TIMER 0xd2e8 | |
ac718b69 | 47 | #define PLA_LEDSEL 0xdd90 |
48 | #define PLA_LED_FEATURE 0xdd92 | |
49 | #define PLA_PHYAR 0xde00 | |
43779f8d | 50 | #define PLA_BOOT_CTRL 0xe004 |
ac718b69 | 51 | #define PLA_GPHY_INTR_IMR 0xe022 |
52 | #define PLA_EEE_CR 0xe040 | |
53 | #define PLA_EEEP_CR 0xe080 | |
54 | #define PLA_MAC_PWR_CTRL 0xe0c0 | |
43779f8d | 55 | #define PLA_MAC_PWR_CTRL2 0xe0ca |
56 | #define PLA_MAC_PWR_CTRL3 0xe0cc | |
57 | #define PLA_MAC_PWR_CTRL4 0xe0ce | |
58 | #define PLA_WDT6_CTRL 0xe428 | |
ac718b69 | 59 | #define PLA_TCR0 0xe610 |
60 | #define PLA_TCR1 0xe612 | |
61 | #define PLA_TXFIFO_CTRL 0xe618 | |
62 | #define PLA_RSTTELLY 0xe800 | |
63 | #define PLA_CR 0xe813 | |
64 | #define PLA_CRWECR 0xe81c | |
21ff2e89 | 65 | #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */ |
66 | #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */ | |
ac718b69 | 67 | #define PLA_CONFIG5 0xe822 |
68 | #define PLA_PHY_PWR 0xe84c | |
69 | #define PLA_OOB_CTRL 0xe84f | |
70 | #define PLA_CPCR 0xe854 | |
71 | #define PLA_MISC_0 0xe858 | |
72 | #define PLA_MISC_1 0xe85a | |
73 | #define PLA_OCP_GPHY_BASE 0xe86c | |
74 | #define PLA_TELLYCNT 0xe890 | |
75 | #define PLA_SFF_STS_7 0xe8de | |
76 | #define PLA_PHYSTATUS 0xe908 | |
77 | #define PLA_BP_BA 0xfc26 | |
78 | #define PLA_BP_0 0xfc28 | |
79 | #define PLA_BP_1 0xfc2a | |
80 | #define PLA_BP_2 0xfc2c | |
81 | #define PLA_BP_3 0xfc2e | |
82 | #define PLA_BP_4 0xfc30 | |
83 | #define PLA_BP_5 0xfc32 | |
84 | #define PLA_BP_6 0xfc34 | |
85 | #define PLA_BP_7 0xfc36 | |
43779f8d | 86 | #define PLA_BP_EN 0xfc38 |
ac718b69 | 87 | |
43779f8d | 88 | #define USB_U2P3_CTRL 0xb460 |
ac718b69 | 89 | #define USB_DEV_STAT 0xb808 |
90 | #define USB_USB_CTRL 0xd406 | |
91 | #define USB_PHY_CTRL 0xd408 | |
92 | #define USB_TX_AGG 0xd40a | |
93 | #define USB_RX_BUF_TH 0xd40c | |
94 | #define USB_USB_TIMER 0xd428 | |
43779f8d | 95 | #define USB_RX_EARLY_AGG 0xd42c |
ac718b69 | 96 | #define USB_PM_CTRL_STATUS 0xd432 |
97 | #define USB_TX_DMA 0xd434 | |
43779f8d | 98 | #define USB_TOLERANCE 0xd490 |
99 | #define USB_LPM_CTRL 0xd41a | |
ac718b69 | 100 | #define USB_UPS_CTRL 0xd800 |
43779f8d | 101 | #define USB_MISC_0 0xd81a |
102 | #define USB_POWER_CUT 0xd80a | |
103 | #define USB_AFE_CTRL2 0xd824 | |
104 | #define USB_WDT11_CTRL 0xe43c | |
ac718b69 | 105 | #define USB_BP_BA 0xfc26 |
106 | #define USB_BP_0 0xfc28 | |
107 | #define USB_BP_1 0xfc2a | |
108 | #define USB_BP_2 0xfc2c | |
109 | #define USB_BP_3 0xfc2e | |
110 | #define USB_BP_4 0xfc30 | |
111 | #define USB_BP_5 0xfc32 | |
112 | #define USB_BP_6 0xfc34 | |
113 | #define USB_BP_7 0xfc36 | |
43779f8d | 114 | #define USB_BP_EN 0xfc38 |
ac718b69 | 115 | |
116 | /* OCP Registers */ | |
117 | #define OCP_ALDPS_CONFIG 0x2010 | |
118 | #define OCP_EEE_CONFIG1 0x2080 | |
119 | #define OCP_EEE_CONFIG2 0x2092 | |
120 | #define OCP_EEE_CONFIG3 0x2094 | |
ac244d3e | 121 | #define OCP_BASE_MII 0xa400 |
ac718b69 | 122 | #define OCP_EEE_AR 0xa41a |
123 | #define OCP_EEE_DATA 0xa41c | |
43779f8d | 124 | #define OCP_PHY_STATUS 0xa420 |
125 | #define OCP_POWER_CFG 0xa430 | |
126 | #define OCP_EEE_CFG 0xa432 | |
127 | #define OCP_SRAM_ADDR 0xa436 | |
128 | #define OCP_SRAM_DATA 0xa438 | |
129 | #define OCP_DOWN_SPEED 0xa442 | |
130 | #define OCP_EEE_CFG2 0xa5d0 | |
131 | #define OCP_ADC_CFG 0xbc06 | |
132 | ||
133 | /* SRAM Register */ | |
134 | #define SRAM_LPF_CFG 0x8012 | |
135 | #define SRAM_10M_AMP1 0x8080 | |
136 | #define SRAM_10M_AMP2 0x8082 | |
137 | #define SRAM_IMPEDANCE 0x8084 | |
ac718b69 | 138 | |
139 | /* PLA_RCR */ | |
140 | #define RCR_AAP 0x00000001 | |
141 | #define RCR_APM 0x00000002 | |
142 | #define RCR_AM 0x00000004 | |
143 | #define RCR_AB 0x00000008 | |
144 | #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB) | |
145 | ||
146 | /* PLA_RXFIFO_CTRL0 */ | |
147 | #define RXFIFO_THR1_NORMAL 0x00080002 | |
148 | #define RXFIFO_THR1_OOB 0x01800003 | |
149 | ||
150 | /* PLA_RXFIFO_CTRL1 */ | |
151 | #define RXFIFO_THR2_FULL 0x00000060 | |
152 | #define RXFIFO_THR2_HIGH 0x00000038 | |
153 | #define RXFIFO_THR2_OOB 0x0000004a | |
43779f8d | 154 | #define RXFIFO_THR2_NORMAL 0x00a0 |
ac718b69 | 155 | |
156 | /* PLA_RXFIFO_CTRL2 */ | |
157 | #define RXFIFO_THR3_FULL 0x00000078 | |
158 | #define RXFIFO_THR3_HIGH 0x00000048 | |
159 | #define RXFIFO_THR3_OOB 0x0000005a | |
43779f8d | 160 | #define RXFIFO_THR3_NORMAL 0x0110 |
ac718b69 | 161 | |
162 | /* PLA_TXFIFO_CTRL */ | |
163 | #define TXFIFO_THR_NORMAL 0x00400008 | |
43779f8d | 164 | #define TXFIFO_THR_NORMAL2 0x01000008 |
ac718b69 | 165 | |
166 | /* PLA_FMC */ | |
167 | #define FMC_FCR_MCU_EN 0x0001 | |
168 | ||
169 | /* PLA_EEEP_CR */ | |
170 | #define EEEP_CR_EEEP_TX 0x0002 | |
171 | ||
43779f8d | 172 | /* PLA_WDT6_CTRL */ |
173 | #define WDT6_SET_MODE 0x0010 | |
174 | ||
ac718b69 | 175 | /* PLA_TCR0 */ |
176 | #define TCR0_TX_EMPTY 0x0800 | |
177 | #define TCR0_AUTO_FIFO 0x0080 | |
178 | ||
179 | /* PLA_TCR1 */ | |
180 | #define VERSION_MASK 0x7cf0 | |
181 | ||
182 | /* PLA_CR */ | |
183 | #define CR_RST 0x10 | |
184 | #define CR_RE 0x08 | |
185 | #define CR_TE 0x04 | |
186 | ||
187 | /* PLA_CRWECR */ | |
188 | #define CRWECR_NORAML 0x00 | |
189 | #define CRWECR_CONFIG 0xc0 | |
190 | ||
191 | /* PLA_OOB_CTRL */ | |
192 | #define NOW_IS_OOB 0x80 | |
193 | #define TXFIFO_EMPTY 0x20 | |
194 | #define RXFIFO_EMPTY 0x10 | |
195 | #define LINK_LIST_READY 0x02 | |
196 | #define DIS_MCU_CLROOB 0x01 | |
197 | #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY) | |
198 | ||
199 | /* PLA_MISC_1 */ | |
200 | #define RXDY_GATED_EN 0x0008 | |
201 | ||
202 | /* PLA_SFF_STS_7 */ | |
203 | #define RE_INIT_LL 0x8000 | |
204 | #define MCU_BORW_EN 0x4000 | |
205 | ||
206 | /* PLA_CPCR */ | |
207 | #define CPCR_RX_VLAN 0x0040 | |
208 | ||
209 | /* PLA_CFG_WOL */ | |
210 | #define MAGIC_EN 0x0001 | |
211 | ||
43779f8d | 212 | /* PLA_TEREDO_CFG */ |
213 | #define TEREDO_SEL 0x8000 | |
214 | #define TEREDO_WAKE_MASK 0x7f00 | |
215 | #define TEREDO_RS_EVENT_MASK 0x00fe | |
216 | #define OOB_TEREDO_EN 0x0001 | |
217 | ||
ac718b69 | 218 | /* PAL_BDC_CR */ |
219 | #define ALDPS_PROXY_MODE 0x0001 | |
220 | ||
21ff2e89 | 221 | /* PLA_CONFIG34 */ |
222 | #define LINK_ON_WAKE_EN 0x0010 | |
223 | #define LINK_OFF_WAKE_EN 0x0008 | |
224 | ||
ac718b69 | 225 | /* PLA_CONFIG5 */ |
21ff2e89 | 226 | #define BWF_EN 0x0040 |
227 | #define MWF_EN 0x0020 | |
228 | #define UWF_EN 0x0010 | |
ac718b69 | 229 | #define LAN_WAKE_EN 0x0002 |
230 | ||
231 | /* PLA_LED_FEATURE */ | |
232 | #define LED_MODE_MASK 0x0700 | |
233 | ||
234 | /* PLA_PHY_PWR */ | |
235 | #define TX_10M_IDLE_EN 0x0080 | |
236 | #define PFM_PWM_SWITCH 0x0040 | |
237 | ||
238 | /* PLA_MAC_PWR_CTRL */ | |
239 | #define D3_CLK_GATED_EN 0x00004000 | |
240 | #define MCU_CLK_RATIO 0x07010f07 | |
241 | #define MCU_CLK_RATIO_MASK 0x0f0f0f0f | |
43779f8d | 242 | #define ALDPS_SPDWN_RATIO 0x0f87 |
243 | ||
244 | /* PLA_MAC_PWR_CTRL2 */ | |
245 | #define EEE_SPDWN_RATIO 0x8007 | |
246 | ||
247 | /* PLA_MAC_PWR_CTRL3 */ | |
248 | #define PKT_AVAIL_SPDWN_EN 0x0100 | |
249 | #define SUSPEND_SPDWN_EN 0x0004 | |
250 | #define U1U2_SPDWN_EN 0x0002 | |
251 | #define L1_SPDWN_EN 0x0001 | |
252 | ||
253 | /* PLA_MAC_PWR_CTRL4 */ | |
254 | #define PWRSAVE_SPDWN_EN 0x1000 | |
255 | #define RXDV_SPDWN_EN 0x0800 | |
256 | #define TX10MIDLE_EN 0x0100 | |
257 | #define TP100_SPDWN_EN 0x0020 | |
258 | #define TP500_SPDWN_EN 0x0010 | |
259 | #define TP1000_SPDWN_EN 0x0008 | |
260 | #define EEE_SPDWN_EN 0x0001 | |
ac718b69 | 261 | |
262 | /* PLA_GPHY_INTR_IMR */ | |
263 | #define GPHY_STS_MSK 0x0001 | |
264 | #define SPEED_DOWN_MSK 0x0002 | |
265 | #define SPDWN_RXDV_MSK 0x0004 | |
266 | #define SPDWN_LINKCHG_MSK 0x0008 | |
267 | ||
268 | /* PLA_PHYAR */ | |
269 | #define PHYAR_FLAG 0x80000000 | |
270 | ||
271 | /* PLA_EEE_CR */ | |
272 | #define EEE_RX_EN 0x0001 | |
273 | #define EEE_TX_EN 0x0002 | |
274 | ||
43779f8d | 275 | /* PLA_BOOT_CTRL */ |
276 | #define AUTOLOAD_DONE 0x0002 | |
277 | ||
ac718b69 | 278 | /* USB_DEV_STAT */ |
279 | #define STAT_SPEED_MASK 0x0006 | |
280 | #define STAT_SPEED_HIGH 0x0000 | |
281 | #define STAT_SPEED_FULL 0x0001 | |
282 | ||
283 | /* USB_TX_AGG */ | |
284 | #define TX_AGG_MAX_THRESHOLD 0x03 | |
285 | ||
286 | /* USB_RX_BUF_TH */ | |
43779f8d | 287 | #define RX_THR_SUPPER 0x0c350180 |
8e1f51bd | 288 | #define RX_THR_HIGH 0x7a120180 |
43779f8d | 289 | #define RX_THR_SLOW 0xffff0180 |
ac718b69 | 290 | |
291 | /* USB_TX_DMA */ | |
292 | #define TEST_MODE_DISABLE 0x00000001 | |
293 | #define TX_SIZE_ADJUST1 0x00000100 | |
294 | ||
295 | /* USB_UPS_CTRL */ | |
296 | #define POWER_CUT 0x0100 | |
297 | ||
298 | /* USB_PM_CTRL_STATUS */ | |
8e1f51bd | 299 | #define RESUME_INDICATE 0x0001 |
ac718b69 | 300 | |
301 | /* USB_USB_CTRL */ | |
302 | #define RX_AGG_DISABLE 0x0010 | |
303 | ||
43779f8d | 304 | /* USB_U2P3_CTRL */ |
305 | #define U2P3_ENABLE 0x0001 | |
306 | ||
307 | /* USB_POWER_CUT */ | |
308 | #define PWR_EN 0x0001 | |
309 | #define PHASE2_EN 0x0008 | |
310 | ||
311 | /* USB_MISC_0 */ | |
312 | #define PCUT_STATUS 0x0001 | |
313 | ||
314 | /* USB_RX_EARLY_AGG */ | |
315 | #define EARLY_AGG_SUPPER 0x0e832981 | |
316 | #define EARLY_AGG_HIGH 0x0e837a12 | |
317 | #define EARLY_AGG_SLOW 0x0e83ffff | |
318 | ||
319 | /* USB_WDT11_CTRL */ | |
320 | #define TIMER11_EN 0x0001 | |
321 | ||
322 | /* USB_LPM_CTRL */ | |
323 | #define LPM_TIMER_MASK 0x0c | |
324 | #define LPM_TIMER_500MS 0x04 /* 500 ms */ | |
325 | #define LPM_TIMER_500US 0x0c /* 500 us */ | |
326 | ||
327 | /* USB_AFE_CTRL2 */ | |
328 | #define SEN_VAL_MASK 0xf800 | |
329 | #define SEN_VAL_NORMAL 0xa000 | |
330 | #define SEL_RXIDLE 0x0100 | |
331 | ||
ac718b69 | 332 | /* OCP_ALDPS_CONFIG */ |
333 | #define ENPWRSAVE 0x8000 | |
334 | #define ENPDNPS 0x0200 | |
335 | #define LINKENA 0x0100 | |
336 | #define DIS_SDSAVE 0x0010 | |
337 | ||
43779f8d | 338 | /* OCP_PHY_STATUS */ |
339 | #define PHY_STAT_MASK 0x0007 | |
340 | #define PHY_STAT_LAN_ON 3 | |
341 | #define PHY_STAT_PWRDN 5 | |
342 | ||
343 | /* OCP_POWER_CFG */ | |
344 | #define EEE_CLKDIV_EN 0x8000 | |
345 | #define EN_ALDPS 0x0004 | |
346 | #define EN_10M_PLLOFF 0x0001 | |
347 | ||
ac718b69 | 348 | /* OCP_EEE_CONFIG1 */ |
349 | #define RG_TXLPI_MSK_HFDUP 0x8000 | |
350 | #define RG_MATCLR_EN 0x4000 | |
351 | #define EEE_10_CAP 0x2000 | |
352 | #define EEE_NWAY_EN 0x1000 | |
353 | #define TX_QUIET_EN 0x0200 | |
354 | #define RX_QUIET_EN 0x0100 | |
355 | #define SDRISETIME 0x0010 /* bit 4 ~ 6 */ | |
356 | #define RG_RXLPI_MSK_HFDUP 0x0008 | |
357 | #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */ | |
358 | ||
359 | /* OCP_EEE_CONFIG2 */ | |
360 | #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */ | |
361 | #define RG_DACQUIET_EN 0x0400 | |
362 | #define RG_LDVQUIET_EN 0x0200 | |
363 | #define RG_CKRSEL 0x0020 | |
364 | #define RG_EEEPRG_EN 0x0010 | |
365 | ||
366 | /* OCP_EEE_CONFIG3 */ | |
367 | #define FST_SNR_EYE_R 0x1500 /* bit 7 ~ 15 */ | |
368 | #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */ | |
369 | #define MSK_PH 0x0006 /* bit 0 ~ 3 */ | |
370 | ||
371 | /* OCP_EEE_AR */ | |
372 | /* bit[15:14] function */ | |
373 | #define FUN_ADDR 0x0000 | |
374 | #define FUN_DATA 0x4000 | |
375 | /* bit[4:0] device addr */ | |
376 | #define DEVICE_ADDR 0x0007 | |
377 | ||
378 | /* OCP_EEE_DATA */ | |
379 | #define EEE_ADDR 0x003C | |
380 | #define EEE_DATA 0x0002 | |
381 | ||
43779f8d | 382 | /* OCP_EEE_CFG */ |
383 | #define CTAP_SHORT_EN 0x0040 | |
384 | #define EEE10_EN 0x0010 | |
385 | ||
386 | /* OCP_DOWN_SPEED */ | |
387 | #define EN_10M_BGOFF 0x0080 | |
388 | ||
389 | /* OCP_EEE_CFG2 */ | |
390 | #define MY1000_EEE 0x0004 | |
391 | #define MY100_EEE 0x0002 | |
392 | ||
393 | /* OCP_ADC_CFG */ | |
394 | #define CKADSEL_L 0x0100 | |
395 | #define ADC_EN 0x0080 | |
396 | #define EN_EMI_L 0x0040 | |
397 | ||
398 | /* SRAM_LPF_CFG */ | |
399 | #define LPF_AUTO_TUNE 0x8000 | |
400 | ||
401 | /* SRAM_10M_AMP1 */ | |
402 | #define GDAC_IB_UPALL 0x0008 | |
403 | ||
404 | /* SRAM_10M_AMP2 */ | |
405 | #define AMP_DN 0x0200 | |
406 | ||
407 | /* SRAM_IMPEDANCE */ | |
408 | #define RX_DRIVING_MASK 0x6000 | |
409 | ||
ac718b69 | 410 | enum rtl_register_content { |
43779f8d | 411 | _1000bps = 0x10, |
ac718b69 | 412 | _100bps = 0x08, |
413 | _10bps = 0x04, | |
414 | LINK_STATUS = 0x02, | |
415 | FULL_DUP = 0x01, | |
416 | }; | |
417 | ||
ebc2ec48 | 418 | #define RTL8152_MAX_TX 10 |
419 | #define RTL8152_MAX_RX 10 | |
40a82917 | 420 | #define INTBUFSIZE 2 |
8e1f51bd | 421 | #define CRC_SIZE 4 |
422 | #define TX_ALIGN 4 | |
423 | #define RX_ALIGN 8 | |
40a82917 | 424 | |
425 | #define INTR_LINK 0x0004 | |
ebc2ec48 | 426 | |
ac718b69 | 427 | #define RTL8152_REQT_READ 0xc0 |
428 | #define RTL8152_REQT_WRITE 0x40 | |
429 | #define RTL8152_REQ_GET_REGS 0x05 | |
430 | #define RTL8152_REQ_SET_REGS 0x05 | |
431 | ||
432 | #define BYTE_EN_DWORD 0xff | |
433 | #define BYTE_EN_WORD 0x33 | |
434 | #define BYTE_EN_BYTE 0x11 | |
435 | #define BYTE_EN_SIX_BYTES 0x3f | |
436 | #define BYTE_EN_START_MASK 0x0f | |
437 | #define BYTE_EN_END_MASK 0xf0 | |
438 | ||
439 | #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN) | |
440 | #define RTL8152_TX_TIMEOUT (HZ) | |
441 | ||
442 | /* rtl8152 flags */ | |
443 | enum rtl8152_flags { | |
444 | RTL8152_UNPLUG = 0, | |
ac718b69 | 445 | RTL8152_SET_RX_MODE, |
40a82917 | 446 | WORK_ENABLE, |
447 | RTL8152_LINK_CHG, | |
9a4be1bd | 448 | SELECTIVE_SUSPEND, |
aa66a5f1 | 449 | PHY_RESET, |
ac718b69 | 450 | }; |
451 | ||
452 | /* Define these values to match your device */ | |
453 | #define VENDOR_ID_REALTEK 0x0bda | |
454 | #define PRODUCT_ID_RTL8152 0x8152 | |
43779f8d | 455 | #define PRODUCT_ID_RTL8153 0x8153 |
456 | ||
457 | #define VENDOR_ID_SAMSUNG 0x04e8 | |
458 | #define PRODUCT_ID_SAMSUNG 0xa101 | |
ac718b69 | 459 | |
460 | #define MCU_TYPE_PLA 0x0100 | |
461 | #define MCU_TYPE_USB 0x0000 | |
462 | ||
c7de7dec | 463 | #define REALTEK_USB_DEVICE(vend, prod) \ |
464 | USB_DEVICE_INTERFACE_CLASS(vend, prod, USB_CLASS_VENDOR_SPEC) | |
465 | ||
ac718b69 | 466 | struct rx_desc { |
500b6d7e | 467 | __le32 opts1; |
ac718b69 | 468 | #define RX_LEN_MASK 0x7fff |
500b6d7e | 469 | __le32 opts2; |
470 | __le32 opts3; | |
471 | __le32 opts4; | |
472 | __le32 opts5; | |
473 | __le32 opts6; | |
ac718b69 | 474 | }; |
475 | ||
476 | struct tx_desc { | |
500b6d7e | 477 | __le32 opts1; |
ac718b69 | 478 | #define TX_FS (1 << 31) /* First segment of a packet */ |
479 | #define TX_LS (1 << 30) /* Final segment of a packet */ | |
5bd23881 | 480 | #define TX_LEN_MASK 0x3ffff |
481 | ||
500b6d7e | 482 | __le32 opts2; |
5bd23881 | 483 | #define UDP_CS (1 << 31) /* Calculate UDP/IP checksum */ |
484 | #define TCP_CS (1 << 30) /* Calculate TCP/IP checksum */ | |
485 | #define IPV4_CS (1 << 29) /* Calculate IPv4 checksum */ | |
486 | #define IPV6_CS (1 << 28) /* Calculate IPv6 checksum */ | |
ac718b69 | 487 | }; |
488 | ||
dff4e8ad | 489 | struct r8152; |
490 | ||
ebc2ec48 | 491 | struct rx_agg { |
492 | struct list_head list; | |
493 | struct urb *urb; | |
dff4e8ad | 494 | struct r8152 *context; |
ebc2ec48 | 495 | void *buffer; |
496 | void *head; | |
497 | }; | |
498 | ||
499 | struct tx_agg { | |
500 | struct list_head list; | |
501 | struct urb *urb; | |
dff4e8ad | 502 | struct r8152 *context; |
ebc2ec48 | 503 | void *buffer; |
504 | void *head; | |
505 | u32 skb_num; | |
506 | u32 skb_len; | |
507 | }; | |
508 | ||
ac718b69 | 509 | struct r8152 { |
510 | unsigned long flags; | |
511 | struct usb_device *udev; | |
512 | struct tasklet_struct tl; | |
40a82917 | 513 | struct usb_interface *intf; |
ac718b69 | 514 | struct net_device *netdev; |
40a82917 | 515 | struct urb *intr_urb; |
ebc2ec48 | 516 | struct tx_agg tx_info[RTL8152_MAX_TX]; |
517 | struct rx_agg rx_info[RTL8152_MAX_RX]; | |
518 | struct list_head rx_done, tx_free; | |
519 | struct sk_buff_head tx_queue; | |
520 | spinlock_t rx_lock, tx_lock; | |
ac718b69 | 521 | struct delayed_work schedule; |
522 | struct mii_if_info mii; | |
c81229c9 | 523 | |
524 | struct rtl_ops { | |
525 | void (*init)(struct r8152 *); | |
526 | int (*enable)(struct r8152 *); | |
527 | void (*disable)(struct r8152 *); | |
7e9da481 | 528 | void (*up)(struct r8152 *); |
c81229c9 | 529 | void (*down)(struct r8152 *); |
530 | void (*unload)(struct r8152 *); | |
531 | } rtl_ops; | |
532 | ||
40a82917 | 533 | int intr_interval; |
21ff2e89 | 534 | u32 saved_wolopts; |
ac718b69 | 535 | u32 msg_enable; |
dd1b119c | 536 | u32 tx_qlen; |
ac718b69 | 537 | u16 ocp_base; |
40a82917 | 538 | u8 *intr_buff; |
ac718b69 | 539 | u8 version; |
540 | u8 speed; | |
541 | }; | |
542 | ||
543 | enum rtl_version { | |
544 | RTL_VER_UNKNOWN = 0, | |
545 | RTL_VER_01, | |
43779f8d | 546 | RTL_VER_02, |
547 | RTL_VER_03, | |
548 | RTL_VER_04, | |
549 | RTL_VER_05, | |
550 | RTL_VER_MAX | |
ac718b69 | 551 | }; |
552 | ||
553 | /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). | |
554 | * The RTL chips use a 64 element hash table based on the Ethernet CRC. | |
555 | */ | |
556 | static const int multicast_filter_limit = 32; | |
ebc2ec48 | 557 | static unsigned int rx_buf_sz = 16384; |
ac718b69 | 558 | |
559 | static | |
560 | int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) | |
561 | { | |
31787f53 | 562 | int ret; |
563 | void *tmp; | |
564 | ||
565 | tmp = kmalloc(size, GFP_KERNEL); | |
566 | if (!tmp) | |
567 | return -ENOMEM; | |
568 | ||
569 | ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0), | |
ac718b69 | 570 | RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, |
31787f53 | 571 | value, index, tmp, size, 500); |
572 | ||
573 | memcpy(data, tmp, size); | |
574 | kfree(tmp); | |
575 | ||
576 | return ret; | |
ac718b69 | 577 | } |
578 | ||
579 | static | |
580 | int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) | |
581 | { | |
31787f53 | 582 | int ret; |
583 | void *tmp; | |
584 | ||
585 | tmp = kmalloc(size, GFP_KERNEL); | |
586 | if (!tmp) | |
587 | return -ENOMEM; | |
588 | ||
589 | memcpy(tmp, data, size); | |
590 | ||
591 | ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0), | |
ac718b69 | 592 | RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE, |
31787f53 | 593 | value, index, tmp, size, 500); |
594 | ||
595 | kfree(tmp); | |
db8515ef | 596 | |
31787f53 | 597 | return ret; |
ac718b69 | 598 | } |
599 | ||
600 | static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size, | |
601 | void *data, u16 type) | |
602 | { | |
45f4a19f | 603 | u16 limit = 64; |
604 | int ret = 0; | |
ac718b69 | 605 | |
606 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
607 | return -ENODEV; | |
608 | ||
609 | /* both size and indix must be 4 bytes align */ | |
610 | if ((size & 3) || !size || (index & 3) || !data) | |
611 | return -EPERM; | |
612 | ||
613 | if ((u32)index + (u32)size > 0xffff) | |
614 | return -EPERM; | |
615 | ||
616 | while (size) { | |
617 | if (size > limit) { | |
618 | ret = get_registers(tp, index, type, limit, data); | |
619 | if (ret < 0) | |
620 | break; | |
621 | ||
622 | index += limit; | |
623 | data += limit; | |
624 | size -= limit; | |
625 | } else { | |
626 | ret = get_registers(tp, index, type, size, data); | |
627 | if (ret < 0) | |
628 | break; | |
629 | ||
630 | index += size; | |
631 | data += size; | |
632 | size = 0; | |
633 | break; | |
634 | } | |
635 | } | |
636 | ||
637 | return ret; | |
638 | } | |
639 | ||
640 | static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, | |
641 | u16 size, void *data, u16 type) | |
642 | { | |
45f4a19f | 643 | int ret; |
644 | u16 byteen_start, byteen_end, byen; | |
645 | u16 limit = 512; | |
ac718b69 | 646 | |
647 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
648 | return -ENODEV; | |
649 | ||
650 | /* both size and indix must be 4 bytes align */ | |
651 | if ((size & 3) || !size || (index & 3) || !data) | |
652 | return -EPERM; | |
653 | ||
654 | if ((u32)index + (u32)size > 0xffff) | |
655 | return -EPERM; | |
656 | ||
657 | byteen_start = byteen & BYTE_EN_START_MASK; | |
658 | byteen_end = byteen & BYTE_EN_END_MASK; | |
659 | ||
660 | byen = byteen_start | (byteen_start << 4); | |
661 | ret = set_registers(tp, index, type | byen, 4, data); | |
662 | if (ret < 0) | |
663 | goto error1; | |
664 | ||
665 | index += 4; | |
666 | data += 4; | |
667 | size -= 4; | |
668 | ||
669 | if (size) { | |
670 | size -= 4; | |
671 | ||
672 | while (size) { | |
673 | if (size > limit) { | |
674 | ret = set_registers(tp, index, | |
675 | type | BYTE_EN_DWORD, | |
676 | limit, data); | |
677 | if (ret < 0) | |
678 | goto error1; | |
679 | ||
680 | index += limit; | |
681 | data += limit; | |
682 | size -= limit; | |
683 | } else { | |
684 | ret = set_registers(tp, index, | |
685 | type | BYTE_EN_DWORD, | |
686 | size, data); | |
687 | if (ret < 0) | |
688 | goto error1; | |
689 | ||
690 | index += size; | |
691 | data += size; | |
692 | size = 0; | |
693 | break; | |
694 | } | |
695 | } | |
696 | ||
697 | byen = byteen_end | (byteen_end >> 4); | |
698 | ret = set_registers(tp, index, type | byen, 4, data); | |
699 | if (ret < 0) | |
700 | goto error1; | |
701 | } | |
702 | ||
703 | error1: | |
704 | return ret; | |
705 | } | |
706 | ||
707 | static inline | |
708 | int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) | |
709 | { | |
710 | return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA); | |
711 | } | |
712 | ||
713 | static inline | |
714 | int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) | |
715 | { | |
716 | return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA); | |
717 | } | |
718 | ||
719 | static inline | |
720 | int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) | |
721 | { | |
722 | return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB); | |
723 | } | |
724 | ||
725 | static inline | |
726 | int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) | |
727 | { | |
728 | return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB); | |
729 | } | |
730 | ||
731 | static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index) | |
732 | { | |
c8826de8 | 733 | __le32 data; |
ac718b69 | 734 | |
c8826de8 | 735 | generic_ocp_read(tp, index, sizeof(data), &data, type); |
ac718b69 | 736 | |
737 | return __le32_to_cpu(data); | |
738 | } | |
739 | ||
740 | static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data) | |
741 | { | |
c8826de8 | 742 | __le32 tmp = __cpu_to_le32(data); |
743 | ||
744 | generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type); | |
ac718b69 | 745 | } |
746 | ||
747 | static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index) | |
748 | { | |
749 | u32 data; | |
c8826de8 | 750 | __le32 tmp; |
ac718b69 | 751 | u8 shift = index & 2; |
752 | ||
753 | index &= ~3; | |
754 | ||
c8826de8 | 755 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 756 | |
c8826de8 | 757 | data = __le32_to_cpu(tmp); |
ac718b69 | 758 | data >>= (shift * 8); |
759 | data &= 0xffff; | |
760 | ||
761 | return (u16)data; | |
762 | } | |
763 | ||
764 | static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data) | |
765 | { | |
c8826de8 | 766 | u32 mask = 0xffff; |
767 | __le32 tmp; | |
ac718b69 | 768 | u16 byen = BYTE_EN_WORD; |
769 | u8 shift = index & 2; | |
770 | ||
771 | data &= mask; | |
772 | ||
773 | if (index & 2) { | |
774 | byen <<= shift; | |
775 | mask <<= (shift * 8); | |
776 | data <<= (shift * 8); | |
777 | index &= ~3; | |
778 | } | |
779 | ||
c8826de8 | 780 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 781 | |
c8826de8 | 782 | data |= __le32_to_cpu(tmp) & ~mask; |
783 | tmp = __cpu_to_le32(data); | |
ac718b69 | 784 | |
c8826de8 | 785 | generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); |
ac718b69 | 786 | } |
787 | ||
788 | static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index) | |
789 | { | |
790 | u32 data; | |
c8826de8 | 791 | __le32 tmp; |
ac718b69 | 792 | u8 shift = index & 3; |
793 | ||
794 | index &= ~3; | |
795 | ||
c8826de8 | 796 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 797 | |
c8826de8 | 798 | data = __le32_to_cpu(tmp); |
ac718b69 | 799 | data >>= (shift * 8); |
800 | data &= 0xff; | |
801 | ||
802 | return (u8)data; | |
803 | } | |
804 | ||
805 | static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data) | |
806 | { | |
c8826de8 | 807 | u32 mask = 0xff; |
808 | __le32 tmp; | |
ac718b69 | 809 | u16 byen = BYTE_EN_BYTE; |
810 | u8 shift = index & 3; | |
811 | ||
812 | data &= mask; | |
813 | ||
814 | if (index & 3) { | |
815 | byen <<= shift; | |
816 | mask <<= (shift * 8); | |
817 | data <<= (shift * 8); | |
818 | index &= ~3; | |
819 | } | |
820 | ||
c8826de8 | 821 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 822 | |
c8826de8 | 823 | data |= __le32_to_cpu(tmp) & ~mask; |
824 | tmp = __cpu_to_le32(data); | |
ac718b69 | 825 | |
c8826de8 | 826 | generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); |
ac718b69 | 827 | } |
828 | ||
ac244d3e | 829 | static u16 ocp_reg_read(struct r8152 *tp, u16 addr) |
e3fe0b1a | 830 | { |
831 | u16 ocp_base, ocp_index; | |
832 | ||
833 | ocp_base = addr & 0xf000; | |
834 | if (ocp_base != tp->ocp_base) { | |
835 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); | |
836 | tp->ocp_base = ocp_base; | |
837 | } | |
838 | ||
839 | ocp_index = (addr & 0x0fff) | 0xb000; | |
ac244d3e | 840 | return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index); |
e3fe0b1a | 841 | } |
842 | ||
ac244d3e | 843 | static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) |
ac718b69 | 844 | { |
ac244d3e | 845 | u16 ocp_base, ocp_index; |
ac718b69 | 846 | |
ac244d3e | 847 | ocp_base = addr & 0xf000; |
848 | if (ocp_base != tp->ocp_base) { | |
849 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); | |
850 | tp->ocp_base = ocp_base; | |
ac718b69 | 851 | } |
ac244d3e | 852 | |
853 | ocp_index = (addr & 0x0fff) | 0xb000; | |
854 | ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); | |
ac718b69 | 855 | } |
856 | ||
ac244d3e | 857 | static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value) |
ac718b69 | 858 | { |
ac244d3e | 859 | ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value); |
860 | } | |
ac718b69 | 861 | |
ac244d3e | 862 | static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr) |
863 | { | |
864 | return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2); | |
ac718b69 | 865 | } |
866 | ||
43779f8d | 867 | static void sram_write(struct r8152 *tp, u16 addr, u16 data) |
868 | { | |
869 | ocp_reg_write(tp, OCP_SRAM_ADDR, addr); | |
870 | ocp_reg_write(tp, OCP_SRAM_DATA, data); | |
871 | } | |
872 | ||
873 | static u16 sram_read(struct r8152 *tp, u16 addr) | |
874 | { | |
875 | ocp_reg_write(tp, OCP_SRAM_ADDR, addr); | |
876 | return ocp_reg_read(tp, OCP_SRAM_DATA); | |
877 | } | |
878 | ||
ac718b69 | 879 | static int read_mii_word(struct net_device *netdev, int phy_id, int reg) |
880 | { | |
881 | struct r8152 *tp = netdev_priv(netdev); | |
9a4be1bd | 882 | int ret; |
ac718b69 | 883 | |
884 | if (phy_id != R8152_PHY_ID) | |
885 | return -EINVAL; | |
886 | ||
9a4be1bd | 887 | ret = usb_autopm_get_interface(tp->intf); |
888 | if (ret < 0) | |
889 | goto out; | |
890 | ||
891 | ret = r8152_mdio_read(tp, reg); | |
892 | ||
893 | usb_autopm_put_interface(tp->intf); | |
894 | ||
895 | out: | |
896 | return ret; | |
ac718b69 | 897 | } |
898 | ||
899 | static | |
900 | void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val) | |
901 | { | |
902 | struct r8152 *tp = netdev_priv(netdev); | |
903 | ||
904 | if (phy_id != R8152_PHY_ID) | |
905 | return; | |
906 | ||
9a4be1bd | 907 | if (usb_autopm_get_interface(tp->intf) < 0) |
908 | return; | |
909 | ||
ac718b69 | 910 | r8152_mdio_write(tp, reg, val); |
9a4be1bd | 911 | |
912 | usb_autopm_put_interface(tp->intf); | |
ac718b69 | 913 | } |
914 | ||
ebc2ec48 | 915 | static |
916 | int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags); | |
917 | ||
ac718b69 | 918 | static inline void set_ethernet_addr(struct r8152 *tp) |
919 | { | |
920 | struct net_device *dev = tp->netdev; | |
8a91c824 | 921 | int ret; |
31787f53 | 922 | u8 node_id[8] = {0}; |
ac718b69 | 923 | |
8a91c824 | 924 | if (tp->version == RTL_VER_01) |
925 | ret = pla_ocp_read(tp, PLA_IDR, sizeof(node_id), node_id); | |
926 | else | |
927 | ret = pla_ocp_read(tp, PLA_BACKUP, sizeof(node_id), node_id); | |
928 | ||
929 | if (ret < 0) { | |
ac718b69 | 930 | netif_notice(tp, probe, dev, "inet addr fail\n"); |
8a91c824 | 931 | } else { |
932 | if (tp->version != RTL_VER_01) { | |
933 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, | |
934 | CRWECR_CONFIG); | |
935 | pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, | |
936 | sizeof(node_id), node_id); | |
937 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, | |
938 | CRWECR_NORAML); | |
939 | } | |
940 | ||
ac718b69 | 941 | memcpy(dev->dev_addr, node_id, dev->addr_len); |
942 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); | |
943 | } | |
ac718b69 | 944 | } |
945 | ||
946 | static int rtl8152_set_mac_address(struct net_device *netdev, void *p) | |
947 | { | |
948 | struct r8152 *tp = netdev_priv(netdev); | |
949 | struct sockaddr *addr = p; | |
950 | ||
951 | if (!is_valid_ether_addr(addr->sa_data)) | |
952 | return -EADDRNOTAVAIL; | |
953 | ||
954 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
955 | ||
956 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
957 | pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data); | |
958 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
959 | ||
960 | return 0; | |
961 | } | |
962 | ||
ac718b69 | 963 | static void read_bulk_callback(struct urb *urb) |
964 | { | |
ac718b69 | 965 | struct net_device *netdev; |
a5a4f468 | 966 | unsigned long flags; |
ac718b69 | 967 | int status = urb->status; |
ebc2ec48 | 968 | struct rx_agg *agg; |
969 | struct r8152 *tp; | |
ac718b69 | 970 | int result; |
ac718b69 | 971 | |
ebc2ec48 | 972 | agg = urb->context; |
973 | if (!agg) | |
974 | return; | |
975 | ||
976 | tp = agg->context; | |
ac718b69 | 977 | if (!tp) |
978 | return; | |
ebc2ec48 | 979 | |
ac718b69 | 980 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
981 | return; | |
ebc2ec48 | 982 | |
983 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
984 | return; | |
985 | ||
ac718b69 | 986 | netdev = tp->netdev; |
7559fb2f | 987 | |
988 | /* When link down, the driver would cancel all bulks. */ | |
989 | /* This avoid the re-submitting bulk */ | |
ebc2ec48 | 990 | if (!netif_carrier_ok(netdev)) |
ac718b69 | 991 | return; |
992 | ||
9a4be1bd | 993 | usb_mark_last_busy(tp->udev); |
994 | ||
ac718b69 | 995 | switch (status) { |
996 | case 0: | |
ebc2ec48 | 997 | if (urb->actual_length < ETH_ZLEN) |
998 | break; | |
999 | ||
a5a4f468 | 1000 | spin_lock_irqsave(&tp->rx_lock, flags); |
ebc2ec48 | 1001 | list_add_tail(&agg->list, &tp->rx_done); |
a5a4f468 | 1002 | spin_unlock_irqrestore(&tp->rx_lock, flags); |
ebc2ec48 | 1003 | tasklet_schedule(&tp->tl); |
1004 | return; | |
ac718b69 | 1005 | case -ESHUTDOWN: |
1006 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
1007 | netif_device_detach(tp->netdev); | |
ebc2ec48 | 1008 | return; |
ac718b69 | 1009 | case -ENOENT: |
1010 | return; /* the urb is in unlink state */ | |
1011 | case -ETIME: | |
4a8deae2 HW |
1012 | if (net_ratelimit()) |
1013 | netdev_warn(netdev, "maybe reset is needed?\n"); | |
ebc2ec48 | 1014 | break; |
ac718b69 | 1015 | default: |
4a8deae2 HW |
1016 | if (net_ratelimit()) |
1017 | netdev_warn(netdev, "Rx status %d\n", status); | |
ebc2ec48 | 1018 | break; |
ac718b69 | 1019 | } |
1020 | ||
ebc2ec48 | 1021 | result = r8152_submit_rx(tp, agg, GFP_ATOMIC); |
ac718b69 | 1022 | if (result == -ENODEV) { |
1023 | netif_device_detach(tp->netdev); | |
1024 | } else if (result) { | |
a5a4f468 | 1025 | spin_lock_irqsave(&tp->rx_lock, flags); |
ebc2ec48 | 1026 | list_add_tail(&agg->list, &tp->rx_done); |
a5a4f468 | 1027 | spin_unlock_irqrestore(&tp->rx_lock, flags); |
ebc2ec48 | 1028 | tasklet_schedule(&tp->tl); |
ac718b69 | 1029 | } |
ac718b69 | 1030 | } |
1031 | ||
ebc2ec48 | 1032 | static void write_bulk_callback(struct urb *urb) |
ac718b69 | 1033 | { |
ebc2ec48 | 1034 | struct net_device_stats *stats; |
d104eafa | 1035 | struct net_device *netdev; |
a5a4f468 | 1036 | unsigned long flags; |
ebc2ec48 | 1037 | struct tx_agg *agg; |
ac718b69 | 1038 | struct r8152 *tp; |
ebc2ec48 | 1039 | int status = urb->status; |
ac718b69 | 1040 | |
ebc2ec48 | 1041 | agg = urb->context; |
1042 | if (!agg) | |
ac718b69 | 1043 | return; |
1044 | ||
ebc2ec48 | 1045 | tp = agg->context; |
1046 | if (!tp) | |
1047 | return; | |
1048 | ||
d104eafa | 1049 | netdev = tp->netdev; |
05e0f1aa | 1050 | stats = &netdev->stats; |
ebc2ec48 | 1051 | if (status) { |
4a8deae2 | 1052 | if (net_ratelimit()) |
d104eafa | 1053 | netdev_warn(netdev, "Tx status %d\n", status); |
ebc2ec48 | 1054 | stats->tx_errors += agg->skb_num; |
ac718b69 | 1055 | } else { |
ebc2ec48 | 1056 | stats->tx_packets += agg->skb_num; |
1057 | stats->tx_bytes += agg->skb_len; | |
ac718b69 | 1058 | } |
1059 | ||
a5a4f468 | 1060 | spin_lock_irqsave(&tp->tx_lock, flags); |
ebc2ec48 | 1061 | list_add_tail(&agg->list, &tp->tx_free); |
a5a4f468 | 1062 | spin_unlock_irqrestore(&tp->tx_lock, flags); |
ebc2ec48 | 1063 | |
9a4be1bd | 1064 | usb_autopm_put_interface_async(tp->intf); |
1065 | ||
d104eafa | 1066 | if (!netif_carrier_ok(netdev)) |
ebc2ec48 | 1067 | return; |
1068 | ||
1069 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
1070 | return; | |
1071 | ||
1072 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
1073 | return; | |
1074 | ||
1075 | if (!skb_queue_empty(&tp->tx_queue)) | |
9a4be1bd | 1076 | schedule_delayed_work(&tp->schedule, 0); |
ac718b69 | 1077 | } |
1078 | ||
40a82917 | 1079 | static void intr_callback(struct urb *urb) |
1080 | { | |
1081 | struct r8152 *tp; | |
500b6d7e | 1082 | __le16 *d; |
40a82917 | 1083 | int status = urb->status; |
1084 | int res; | |
1085 | ||
1086 | tp = urb->context; | |
1087 | if (!tp) | |
1088 | return; | |
1089 | ||
1090 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
1091 | return; | |
1092 | ||
1093 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
1094 | return; | |
1095 | ||
1096 | switch (status) { | |
1097 | case 0: /* success */ | |
1098 | break; | |
1099 | case -ECONNRESET: /* unlink */ | |
1100 | case -ESHUTDOWN: | |
1101 | netif_device_detach(tp->netdev); | |
1102 | case -ENOENT: | |
1103 | return; | |
1104 | case -EOVERFLOW: | |
1105 | netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n"); | |
1106 | goto resubmit; | |
1107 | /* -EPIPE: should clear the halt */ | |
1108 | default: | |
1109 | netif_info(tp, intr, tp->netdev, "intr status %d\n", status); | |
1110 | goto resubmit; | |
1111 | } | |
1112 | ||
1113 | d = urb->transfer_buffer; | |
1114 | if (INTR_LINK & __le16_to_cpu(d[0])) { | |
1115 | if (!(tp->speed & LINK_STATUS)) { | |
1116 | set_bit(RTL8152_LINK_CHG, &tp->flags); | |
1117 | schedule_delayed_work(&tp->schedule, 0); | |
1118 | } | |
1119 | } else { | |
1120 | if (tp->speed & LINK_STATUS) { | |
1121 | set_bit(RTL8152_LINK_CHG, &tp->flags); | |
1122 | schedule_delayed_work(&tp->schedule, 0); | |
1123 | } | |
1124 | } | |
1125 | ||
1126 | resubmit: | |
1127 | res = usb_submit_urb(urb, GFP_ATOMIC); | |
1128 | if (res == -ENODEV) | |
1129 | netif_device_detach(tp->netdev); | |
1130 | else if (res) | |
1131 | netif_err(tp, intr, tp->netdev, | |
4a8deae2 | 1132 | "can't resubmit intr, status %d\n", res); |
40a82917 | 1133 | } |
1134 | ||
ebc2ec48 | 1135 | static inline void *rx_agg_align(void *data) |
1136 | { | |
8e1f51bd | 1137 | return (void *)ALIGN((uintptr_t)data, RX_ALIGN); |
ebc2ec48 | 1138 | } |
1139 | ||
1140 | static inline void *tx_agg_align(void *data) | |
1141 | { | |
8e1f51bd | 1142 | return (void *)ALIGN((uintptr_t)data, TX_ALIGN); |
ebc2ec48 | 1143 | } |
1144 | ||
1145 | static void free_all_mem(struct r8152 *tp) | |
1146 | { | |
1147 | int i; | |
1148 | ||
1149 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
9629e3c0 | 1150 | usb_free_urb(tp->rx_info[i].urb); |
1151 | tp->rx_info[i].urb = NULL; | |
ebc2ec48 | 1152 | |
9629e3c0 | 1153 | kfree(tp->rx_info[i].buffer); |
1154 | tp->rx_info[i].buffer = NULL; | |
1155 | tp->rx_info[i].head = NULL; | |
ebc2ec48 | 1156 | } |
1157 | ||
1158 | for (i = 0; i < RTL8152_MAX_TX; i++) { | |
9629e3c0 | 1159 | usb_free_urb(tp->tx_info[i].urb); |
1160 | tp->tx_info[i].urb = NULL; | |
ebc2ec48 | 1161 | |
9629e3c0 | 1162 | kfree(tp->tx_info[i].buffer); |
1163 | tp->tx_info[i].buffer = NULL; | |
1164 | tp->tx_info[i].head = NULL; | |
ebc2ec48 | 1165 | } |
40a82917 | 1166 | |
9629e3c0 | 1167 | usb_free_urb(tp->intr_urb); |
1168 | tp->intr_urb = NULL; | |
40a82917 | 1169 | |
9629e3c0 | 1170 | kfree(tp->intr_buff); |
1171 | tp->intr_buff = NULL; | |
ebc2ec48 | 1172 | } |
1173 | ||
1174 | static int alloc_all_mem(struct r8152 *tp) | |
1175 | { | |
1176 | struct net_device *netdev = tp->netdev; | |
40a82917 | 1177 | struct usb_interface *intf = tp->intf; |
1178 | struct usb_host_interface *alt = intf->cur_altsetting; | |
1179 | struct usb_host_endpoint *ep_intr = alt->endpoint + 2; | |
ebc2ec48 | 1180 | struct urb *urb; |
1181 | int node, i; | |
1182 | u8 *buf; | |
1183 | ||
1184 | node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; | |
1185 | ||
1186 | spin_lock_init(&tp->rx_lock); | |
1187 | spin_lock_init(&tp->tx_lock); | |
1188 | INIT_LIST_HEAD(&tp->rx_done); | |
1189 | INIT_LIST_HEAD(&tp->tx_free); | |
1190 | skb_queue_head_init(&tp->tx_queue); | |
1191 | ||
1192 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
1193 | buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node); | |
1194 | if (!buf) | |
1195 | goto err1; | |
1196 | ||
1197 | if (buf != rx_agg_align(buf)) { | |
1198 | kfree(buf); | |
8e1f51bd | 1199 | buf = kmalloc_node(rx_buf_sz + RX_ALIGN, GFP_KERNEL, |
1200 | node); | |
ebc2ec48 | 1201 | if (!buf) |
1202 | goto err1; | |
1203 | } | |
1204 | ||
1205 | urb = usb_alloc_urb(0, GFP_KERNEL); | |
1206 | if (!urb) { | |
1207 | kfree(buf); | |
1208 | goto err1; | |
1209 | } | |
1210 | ||
1211 | INIT_LIST_HEAD(&tp->rx_info[i].list); | |
1212 | tp->rx_info[i].context = tp; | |
1213 | tp->rx_info[i].urb = urb; | |
1214 | tp->rx_info[i].buffer = buf; | |
1215 | tp->rx_info[i].head = rx_agg_align(buf); | |
1216 | } | |
1217 | ||
1218 | for (i = 0; i < RTL8152_MAX_TX; i++) { | |
1219 | buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node); | |
1220 | if (!buf) | |
1221 | goto err1; | |
1222 | ||
1223 | if (buf != tx_agg_align(buf)) { | |
1224 | kfree(buf); | |
8e1f51bd | 1225 | buf = kmalloc_node(rx_buf_sz + TX_ALIGN, GFP_KERNEL, |
1226 | node); | |
ebc2ec48 | 1227 | if (!buf) |
1228 | goto err1; | |
1229 | } | |
1230 | ||
1231 | urb = usb_alloc_urb(0, GFP_KERNEL); | |
1232 | if (!urb) { | |
1233 | kfree(buf); | |
1234 | goto err1; | |
1235 | } | |
1236 | ||
1237 | INIT_LIST_HEAD(&tp->tx_info[i].list); | |
1238 | tp->tx_info[i].context = tp; | |
1239 | tp->tx_info[i].urb = urb; | |
1240 | tp->tx_info[i].buffer = buf; | |
1241 | tp->tx_info[i].head = tx_agg_align(buf); | |
1242 | ||
1243 | list_add_tail(&tp->tx_info[i].list, &tp->tx_free); | |
1244 | } | |
1245 | ||
40a82917 | 1246 | tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL); |
1247 | if (!tp->intr_urb) | |
1248 | goto err1; | |
1249 | ||
1250 | tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL); | |
1251 | if (!tp->intr_buff) | |
1252 | goto err1; | |
1253 | ||
1254 | tp->intr_interval = (int)ep_intr->desc.bInterval; | |
1255 | usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3), | |
1256 | tp->intr_buff, INTBUFSIZE, intr_callback, | |
1257 | tp, tp->intr_interval); | |
1258 | ||
ebc2ec48 | 1259 | return 0; |
1260 | ||
1261 | err1: | |
1262 | free_all_mem(tp); | |
1263 | return -ENOMEM; | |
1264 | } | |
1265 | ||
0de98f6c | 1266 | static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp) |
1267 | { | |
1268 | struct tx_agg *agg = NULL; | |
1269 | unsigned long flags; | |
1270 | ||
1271 | spin_lock_irqsave(&tp->tx_lock, flags); | |
1272 | if (!list_empty(&tp->tx_free)) { | |
1273 | struct list_head *cursor; | |
1274 | ||
1275 | cursor = tp->tx_free.next; | |
1276 | list_del_init(cursor); | |
1277 | agg = list_entry(cursor, struct tx_agg, list); | |
1278 | } | |
1279 | spin_unlock_irqrestore(&tp->tx_lock, flags); | |
1280 | ||
1281 | return agg; | |
1282 | } | |
1283 | ||
5bd23881 | 1284 | static void |
1285 | r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, struct sk_buff *skb) | |
1286 | { | |
1287 | memset(desc, 0, sizeof(*desc)); | |
1288 | ||
1289 | desc->opts1 = cpu_to_le32((skb->len & TX_LEN_MASK) | TX_FS | TX_LS); | |
1290 | ||
1291 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
1292 | __be16 protocol; | |
1293 | u8 ip_protocol; | |
1294 | u32 opts2 = 0; | |
1295 | ||
1296 | if (skb->protocol == htons(ETH_P_8021Q)) | |
1297 | protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto; | |
1298 | else | |
1299 | protocol = skb->protocol; | |
1300 | ||
1301 | switch (protocol) { | |
1302 | case htons(ETH_P_IP): | |
1303 | opts2 |= IPV4_CS; | |
1304 | ip_protocol = ip_hdr(skb)->protocol; | |
1305 | break; | |
1306 | ||
1307 | case htons(ETH_P_IPV6): | |
1308 | opts2 |= IPV6_CS; | |
1309 | ip_protocol = ipv6_hdr(skb)->nexthdr; | |
1310 | break; | |
1311 | ||
1312 | default: | |
1313 | ip_protocol = IPPROTO_RAW; | |
1314 | break; | |
1315 | } | |
1316 | ||
1317 | if (ip_protocol == IPPROTO_TCP) { | |
1318 | opts2 |= TCP_CS; | |
1319 | opts2 |= (skb_transport_offset(skb) & 0x7fff) << 17; | |
1320 | } else if (ip_protocol == IPPROTO_UDP) { | |
1321 | opts2 |= UDP_CS; | |
1322 | } else { | |
1323 | WARN_ON_ONCE(1); | |
1324 | } | |
1325 | ||
1326 | desc->opts2 = cpu_to_le32(opts2); | |
1327 | } | |
1328 | } | |
1329 | ||
b1379d9a | 1330 | static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg) |
1331 | { | |
d84130a1 | 1332 | struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; |
1333 | unsigned long flags; | |
9a4be1bd | 1334 | int remain, ret; |
b1379d9a | 1335 | u8 *tx_data; |
1336 | ||
d84130a1 | 1337 | __skb_queue_head_init(&skb_head); |
1338 | spin_lock_irqsave(&tx_queue->lock, flags); | |
1339 | skb_queue_splice_init(tx_queue, &skb_head); | |
1340 | spin_unlock_irqrestore(&tx_queue->lock, flags); | |
1341 | ||
b1379d9a | 1342 | tx_data = agg->head; |
1343 | agg->skb_num = agg->skb_len = 0; | |
7937f9e5 | 1344 | remain = rx_buf_sz; |
b1379d9a | 1345 | |
7937f9e5 | 1346 | while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) { |
b1379d9a | 1347 | struct tx_desc *tx_desc; |
1348 | struct sk_buff *skb; | |
1349 | unsigned int len; | |
1350 | ||
d84130a1 | 1351 | skb = __skb_dequeue(&skb_head); |
b1379d9a | 1352 | if (!skb) |
1353 | break; | |
1354 | ||
7937f9e5 | 1355 | remain -= sizeof(*tx_desc); |
b1379d9a | 1356 | len = skb->len; |
1357 | if (remain < len) { | |
d84130a1 | 1358 | __skb_queue_head(&skb_head, skb); |
b1379d9a | 1359 | break; |
1360 | } | |
1361 | ||
7937f9e5 | 1362 | tx_data = tx_agg_align(tx_data); |
b1379d9a | 1363 | tx_desc = (struct tx_desc *)tx_data; |
1364 | tx_data += sizeof(*tx_desc); | |
1365 | ||
1366 | r8152_tx_csum(tp, tx_desc, skb); | |
1367 | memcpy(tx_data, skb->data, len); | |
1368 | agg->skb_num++; | |
1369 | agg->skb_len += len; | |
1370 | dev_kfree_skb_any(skb); | |
1371 | ||
7937f9e5 | 1372 | tx_data += len; |
1373 | remain = rx_buf_sz - (int)(tx_agg_align(tx_data) - agg->head); | |
b1379d9a | 1374 | } |
1375 | ||
d84130a1 | 1376 | if (!skb_queue_empty(&skb_head)) { |
1377 | spin_lock_irqsave(&tx_queue->lock, flags); | |
1378 | skb_queue_splice(&skb_head, tx_queue); | |
1379 | spin_unlock_irqrestore(&tx_queue->lock, flags); | |
1380 | } | |
1381 | ||
9a4be1bd | 1382 | netif_tx_lock_bh(tp->netdev); |
dd1b119c | 1383 | |
1384 | if (netif_queue_stopped(tp->netdev) && | |
1385 | skb_queue_len(&tp->tx_queue) < tp->tx_qlen) | |
1386 | netif_wake_queue(tp->netdev); | |
1387 | ||
9a4be1bd | 1388 | netif_tx_unlock_bh(tp->netdev); |
1389 | ||
1390 | ret = usb_autopm_get_interface(tp->intf); | |
1391 | if (ret < 0) | |
1392 | goto out_tx_fill; | |
dd1b119c | 1393 | |
b1379d9a | 1394 | usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2), |
1395 | agg->head, (int)(tx_data - (u8 *)agg->head), | |
1396 | (usb_complete_t)write_bulk_callback, agg); | |
1397 | ||
9a4be1bd | 1398 | ret = usb_submit_urb(agg->urb, GFP_KERNEL); |
1399 | if (ret < 0) | |
1400 | usb_autopm_put_interface(tp->intf); | |
1401 | ||
1402 | out_tx_fill: | |
1403 | return ret; | |
b1379d9a | 1404 | } |
1405 | ||
ebc2ec48 | 1406 | static void rx_bottom(struct r8152 *tp) |
1407 | { | |
a5a4f468 | 1408 | unsigned long flags; |
d84130a1 | 1409 | struct list_head *cursor, *next, rx_queue; |
ebc2ec48 | 1410 | |
d84130a1 | 1411 | if (list_empty(&tp->rx_done)) |
1412 | return; | |
1413 | ||
1414 | INIT_LIST_HEAD(&rx_queue); | |
a5a4f468 | 1415 | spin_lock_irqsave(&tp->rx_lock, flags); |
d84130a1 | 1416 | list_splice_init(&tp->rx_done, &rx_queue); |
1417 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
1418 | ||
1419 | list_for_each_safe(cursor, next, &rx_queue) { | |
43a4478d | 1420 | struct rx_desc *rx_desc; |
1421 | struct rx_agg *agg; | |
43a4478d | 1422 | int len_used = 0; |
1423 | struct urb *urb; | |
1424 | u8 *rx_data; | |
1425 | int ret; | |
1426 | ||
ebc2ec48 | 1427 | list_del_init(cursor); |
ebc2ec48 | 1428 | |
1429 | agg = list_entry(cursor, struct rx_agg, list); | |
1430 | urb = agg->urb; | |
0de98f6c | 1431 | if (urb->actual_length < ETH_ZLEN) |
1432 | goto submit; | |
ebc2ec48 | 1433 | |
ebc2ec48 | 1434 | rx_desc = agg->head; |
1435 | rx_data = agg->head; | |
7937f9e5 | 1436 | len_used += sizeof(struct rx_desc); |
ebc2ec48 | 1437 | |
7937f9e5 | 1438 | while (urb->actual_length > len_used) { |
43a4478d | 1439 | struct net_device *netdev = tp->netdev; |
05e0f1aa | 1440 | struct net_device_stats *stats = &netdev->stats; |
7937f9e5 | 1441 | unsigned int pkt_len; |
43a4478d | 1442 | struct sk_buff *skb; |
1443 | ||
7937f9e5 | 1444 | pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; |
ebc2ec48 | 1445 | if (pkt_len < ETH_ZLEN) |
1446 | break; | |
1447 | ||
7937f9e5 | 1448 | len_used += pkt_len; |
1449 | if (urb->actual_length < len_used) | |
1450 | break; | |
1451 | ||
8e1f51bd | 1452 | pkt_len -= CRC_SIZE; |
ebc2ec48 | 1453 | rx_data += sizeof(struct rx_desc); |
1454 | ||
1455 | skb = netdev_alloc_skb_ip_align(netdev, pkt_len); | |
1456 | if (!skb) { | |
1457 | stats->rx_dropped++; | |
1458 | break; | |
1459 | } | |
1460 | memcpy(skb->data, rx_data, pkt_len); | |
1461 | skb_put(skb, pkt_len); | |
1462 | skb->protocol = eth_type_trans(skb, netdev); | |
9d9aafa1 | 1463 | netif_receive_skb(skb); |
ebc2ec48 | 1464 | stats->rx_packets++; |
1465 | stats->rx_bytes += pkt_len; | |
1466 | ||
8e1f51bd | 1467 | rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE); |
ebc2ec48 | 1468 | rx_desc = (struct rx_desc *)rx_data; |
ebc2ec48 | 1469 | len_used = (int)(rx_data - (u8 *)agg->head); |
7937f9e5 | 1470 | len_used += sizeof(struct rx_desc); |
ebc2ec48 | 1471 | } |
1472 | ||
0de98f6c | 1473 | submit: |
ebc2ec48 | 1474 | ret = r8152_submit_rx(tp, agg, GFP_ATOMIC); |
ebc2ec48 | 1475 | if (ret && ret != -ENODEV) { |
d84130a1 | 1476 | spin_lock_irqsave(&tp->rx_lock, flags); |
1477 | list_add_tail(&agg->list, &tp->rx_done); | |
1478 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
ebc2ec48 | 1479 | tasklet_schedule(&tp->tl); |
1480 | } | |
1481 | } | |
ebc2ec48 | 1482 | } |
1483 | ||
1484 | static void tx_bottom(struct r8152 *tp) | |
1485 | { | |
ebc2ec48 | 1486 | int res; |
1487 | ||
b1379d9a | 1488 | do { |
1489 | struct tx_agg *agg; | |
ebc2ec48 | 1490 | |
b1379d9a | 1491 | if (skb_queue_empty(&tp->tx_queue)) |
ebc2ec48 | 1492 | break; |
1493 | ||
b1379d9a | 1494 | agg = r8152_get_tx_agg(tp); |
1495 | if (!agg) | |
ebc2ec48 | 1496 | break; |
ebc2ec48 | 1497 | |
b1379d9a | 1498 | res = r8152_tx_agg_fill(tp, agg); |
1499 | if (res) { | |
05e0f1aa | 1500 | struct net_device *netdev = tp->netdev; |
ebc2ec48 | 1501 | |
b1379d9a | 1502 | if (res == -ENODEV) { |
1503 | netif_device_detach(netdev); | |
1504 | } else { | |
05e0f1aa | 1505 | struct net_device_stats *stats = &netdev->stats; |
1506 | unsigned long flags; | |
1507 | ||
b1379d9a | 1508 | netif_warn(tp, tx_err, netdev, |
1509 | "failed tx_urb %d\n", res); | |
1510 | stats->tx_dropped += agg->skb_num; | |
db8515ef | 1511 | |
b1379d9a | 1512 | spin_lock_irqsave(&tp->tx_lock, flags); |
1513 | list_add_tail(&agg->list, &tp->tx_free); | |
1514 | spin_unlock_irqrestore(&tp->tx_lock, flags); | |
1515 | } | |
ebc2ec48 | 1516 | } |
b1379d9a | 1517 | } while (res == 0); |
ebc2ec48 | 1518 | } |
1519 | ||
1520 | static void bottom_half(unsigned long data) | |
ac718b69 | 1521 | { |
1522 | struct r8152 *tp; | |
ac718b69 | 1523 | |
ebc2ec48 | 1524 | tp = (struct r8152 *)data; |
1525 | ||
1526 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
1527 | return; | |
1528 | ||
1529 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
ac718b69 | 1530 | return; |
ebc2ec48 | 1531 | |
7559fb2f | 1532 | /* When link down, the driver would cancel all bulks. */ |
1533 | /* This avoid the re-submitting bulk */ | |
ebc2ec48 | 1534 | if (!netif_carrier_ok(tp->netdev)) |
ac718b69 | 1535 | return; |
ebc2ec48 | 1536 | |
1537 | rx_bottom(tp); | |
ebc2ec48 | 1538 | } |
1539 | ||
1540 | static | |
1541 | int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags) | |
1542 | { | |
1543 | usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1), | |
1544 | agg->head, rx_buf_sz, | |
1545 | (usb_complete_t)read_bulk_callback, agg); | |
1546 | ||
1547 | return usb_submit_urb(agg->urb, mem_flags); | |
ac718b69 | 1548 | } |
1549 | ||
00a5e360 | 1550 | static void rtl_drop_queued_tx(struct r8152 *tp) |
1551 | { | |
1552 | struct net_device_stats *stats = &tp->netdev->stats; | |
d84130a1 | 1553 | struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; |
1554 | unsigned long flags; | |
00a5e360 | 1555 | struct sk_buff *skb; |
1556 | ||
d84130a1 | 1557 | if (skb_queue_empty(tx_queue)) |
1558 | return; | |
1559 | ||
1560 | __skb_queue_head_init(&skb_head); | |
1561 | spin_lock_irqsave(&tx_queue->lock, flags); | |
1562 | skb_queue_splice_init(tx_queue, &skb_head); | |
1563 | spin_unlock_irqrestore(&tx_queue->lock, flags); | |
1564 | ||
1565 | while ((skb = __skb_dequeue(&skb_head))) { | |
00a5e360 | 1566 | dev_kfree_skb(skb); |
1567 | stats->tx_dropped++; | |
1568 | } | |
1569 | } | |
1570 | ||
ac718b69 | 1571 | static void rtl8152_tx_timeout(struct net_device *netdev) |
1572 | { | |
1573 | struct r8152 *tp = netdev_priv(netdev); | |
ebc2ec48 | 1574 | int i; |
1575 | ||
4a8deae2 | 1576 | netif_warn(tp, tx_err, netdev, "Tx timeout\n"); |
ebc2ec48 | 1577 | for (i = 0; i < RTL8152_MAX_TX; i++) |
1578 | usb_unlink_urb(tp->tx_info[i].urb); | |
ac718b69 | 1579 | } |
1580 | ||
1581 | static void rtl8152_set_rx_mode(struct net_device *netdev) | |
1582 | { | |
1583 | struct r8152 *tp = netdev_priv(netdev); | |
1584 | ||
40a82917 | 1585 | if (tp->speed & LINK_STATUS) { |
ac718b69 | 1586 | set_bit(RTL8152_SET_RX_MODE, &tp->flags); |
40a82917 | 1587 | schedule_delayed_work(&tp->schedule, 0); |
1588 | } | |
ac718b69 | 1589 | } |
1590 | ||
1591 | static void _rtl8152_set_rx_mode(struct net_device *netdev) | |
1592 | { | |
1593 | struct r8152 *tp = netdev_priv(netdev); | |
31787f53 | 1594 | u32 mc_filter[2]; /* Multicast hash filter */ |
1595 | __le32 tmp[2]; | |
ac718b69 | 1596 | u32 ocp_data; |
1597 | ||
ac718b69 | 1598 | clear_bit(RTL8152_SET_RX_MODE, &tp->flags); |
1599 | netif_stop_queue(netdev); | |
1600 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
1601 | ocp_data &= ~RCR_ACPT_ALL; | |
1602 | ocp_data |= RCR_AB | RCR_APM; | |
1603 | ||
1604 | if (netdev->flags & IFF_PROMISC) { | |
1605 | /* Unconditionally log net taps. */ | |
1606 | netif_notice(tp, link, netdev, "Promiscuous mode enabled\n"); | |
1607 | ocp_data |= RCR_AM | RCR_AAP; | |
1608 | mc_filter[1] = mc_filter[0] = 0xffffffff; | |
1609 | } else if ((netdev_mc_count(netdev) > multicast_filter_limit) || | |
1610 | (netdev->flags & IFF_ALLMULTI)) { | |
1611 | /* Too many to filter perfectly -- accept all multicasts. */ | |
1612 | ocp_data |= RCR_AM; | |
1613 | mc_filter[1] = mc_filter[0] = 0xffffffff; | |
1614 | } else { | |
1615 | struct netdev_hw_addr *ha; | |
1616 | ||
1617 | mc_filter[1] = mc_filter[0] = 0; | |
1618 | netdev_for_each_mc_addr(ha, netdev) { | |
1619 | int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; | |
1620 | mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); | |
1621 | ocp_data |= RCR_AM; | |
1622 | } | |
1623 | } | |
1624 | ||
31787f53 | 1625 | tmp[0] = __cpu_to_le32(swab32(mc_filter[1])); |
1626 | tmp[1] = __cpu_to_le32(swab32(mc_filter[0])); | |
ac718b69 | 1627 | |
31787f53 | 1628 | pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp); |
ac718b69 | 1629 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); |
1630 | netif_wake_queue(netdev); | |
ac718b69 | 1631 | } |
1632 | ||
1633 | static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb, | |
1634 | struct net_device *netdev) | |
1635 | { | |
1636 | struct r8152 *tp = netdev_priv(netdev); | |
ac718b69 | 1637 | |
ebc2ec48 | 1638 | skb_tx_timestamp(skb); |
ac718b69 | 1639 | |
61598788 | 1640 | skb_queue_tail(&tp->tx_queue, skb); |
ebc2ec48 | 1641 | |
dd1b119c | 1642 | if (list_empty(&tp->tx_free) && |
1643 | skb_queue_len(&tp->tx_queue) > tp->tx_qlen) | |
1644 | netif_stop_queue(netdev); | |
1645 | ||
61598788 | 1646 | if (!list_empty(&tp->tx_free)) |
9a4be1bd | 1647 | schedule_delayed_work(&tp->schedule, 0); |
ac718b69 | 1648 | |
1649 | return NETDEV_TX_OK; | |
1650 | } | |
1651 | ||
1652 | static void r8152b_reset_packet_filter(struct r8152 *tp) | |
1653 | { | |
1654 | u32 ocp_data; | |
1655 | ||
1656 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); | |
1657 | ocp_data &= ~FMC_FCR_MCU_EN; | |
1658 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); | |
1659 | ocp_data |= FMC_FCR_MCU_EN; | |
1660 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); | |
1661 | } | |
1662 | ||
1663 | static void rtl8152_nic_reset(struct r8152 *tp) | |
1664 | { | |
1665 | int i; | |
1666 | ||
1667 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST); | |
1668 | ||
1669 | for (i = 0; i < 1000; i++) { | |
1670 | if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST)) | |
1671 | break; | |
1672 | udelay(100); | |
1673 | } | |
1674 | } | |
1675 | ||
dd1b119c | 1676 | static void set_tx_qlen(struct r8152 *tp) |
1677 | { | |
1678 | struct net_device *netdev = tp->netdev; | |
1679 | ||
1680 | tp->tx_qlen = rx_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN + | |
1681 | sizeof(struct tx_desc)); | |
1682 | } | |
1683 | ||
ac718b69 | 1684 | static inline u8 rtl8152_get_speed(struct r8152 *tp) |
1685 | { | |
1686 | return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); | |
1687 | } | |
1688 | ||
507605a8 | 1689 | static void rtl_set_eee_plus(struct r8152 *tp) |
ac718b69 | 1690 | { |
ebc2ec48 | 1691 | u32 ocp_data; |
ac718b69 | 1692 | u8 speed; |
1693 | ||
1694 | speed = rtl8152_get_speed(tp); | |
ebc2ec48 | 1695 | if (speed & _10bps) { |
ac718b69 | 1696 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); |
ebc2ec48 | 1697 | ocp_data |= EEEP_CR_EEEP_TX; |
ac718b69 | 1698 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); |
1699 | } else { | |
1700 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); | |
ebc2ec48 | 1701 | ocp_data &= ~EEEP_CR_EEEP_TX; |
ac718b69 | 1702 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); |
1703 | } | |
507605a8 | 1704 | } |
1705 | ||
00a5e360 | 1706 | static void rxdy_gated_en(struct r8152 *tp, bool enable) |
1707 | { | |
1708 | u32 ocp_data; | |
1709 | ||
1710 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); | |
1711 | if (enable) | |
1712 | ocp_data |= RXDY_GATED_EN; | |
1713 | else | |
1714 | ocp_data &= ~RXDY_GATED_EN; | |
1715 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); | |
1716 | } | |
1717 | ||
507605a8 | 1718 | static int rtl_enable(struct r8152 *tp) |
1719 | { | |
1720 | u32 ocp_data; | |
1721 | int i, ret; | |
ac718b69 | 1722 | |
1723 | r8152b_reset_packet_filter(tp); | |
1724 | ||
1725 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); | |
1726 | ocp_data |= CR_RE | CR_TE; | |
1727 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); | |
1728 | ||
00a5e360 | 1729 | rxdy_gated_en(tp, false); |
ac718b69 | 1730 | |
ebc2ec48 | 1731 | INIT_LIST_HEAD(&tp->rx_done); |
1732 | ret = 0; | |
1733 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
1734 | INIT_LIST_HEAD(&tp->rx_info[i].list); | |
1735 | ret |= r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL); | |
1736 | } | |
ac718b69 | 1737 | |
ebc2ec48 | 1738 | return ret; |
ac718b69 | 1739 | } |
1740 | ||
507605a8 | 1741 | static int rtl8152_enable(struct r8152 *tp) |
1742 | { | |
1743 | set_tx_qlen(tp); | |
1744 | rtl_set_eee_plus(tp); | |
1745 | ||
1746 | return rtl_enable(tp); | |
1747 | } | |
1748 | ||
43779f8d | 1749 | static void r8153_set_rx_agg(struct r8152 *tp) |
1750 | { | |
1751 | u8 speed; | |
1752 | ||
1753 | speed = rtl8152_get_speed(tp); | |
1754 | if (speed & _1000bps) { | |
1755 | if (tp->udev->speed == USB_SPEED_SUPER) { | |
1756 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, | |
1757 | RX_THR_SUPPER); | |
1758 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG, | |
1759 | EARLY_AGG_SUPPER); | |
1760 | } else { | |
1761 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, | |
1762 | RX_THR_HIGH); | |
1763 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG, | |
1764 | EARLY_AGG_HIGH); | |
1765 | } | |
1766 | } else { | |
1767 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_SLOW); | |
1768 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG, | |
1769 | EARLY_AGG_SLOW); | |
1770 | } | |
1771 | } | |
1772 | ||
1773 | static int rtl8153_enable(struct r8152 *tp) | |
1774 | { | |
1775 | set_tx_qlen(tp); | |
1776 | rtl_set_eee_plus(tp); | |
1777 | r8153_set_rx_agg(tp); | |
1778 | ||
1779 | return rtl_enable(tp); | |
1780 | } | |
1781 | ||
ac718b69 | 1782 | static void rtl8152_disable(struct r8152 *tp) |
1783 | { | |
ebc2ec48 | 1784 | u32 ocp_data; |
1785 | int i; | |
ac718b69 | 1786 | |
1787 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
1788 | ocp_data &= ~RCR_ACPT_ALL; | |
1789 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
1790 | ||
00a5e360 | 1791 | rtl_drop_queued_tx(tp); |
ebc2ec48 | 1792 | |
1793 | for (i = 0; i < RTL8152_MAX_TX; i++) | |
1794 | usb_kill_urb(tp->tx_info[i].urb); | |
ac718b69 | 1795 | |
00a5e360 | 1796 | rxdy_gated_en(tp, true); |
ac718b69 | 1797 | |
1798 | for (i = 0; i < 1000; i++) { | |
1799 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
1800 | if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY) | |
1801 | break; | |
1802 | mdelay(1); | |
1803 | } | |
1804 | ||
1805 | for (i = 0; i < 1000; i++) { | |
1806 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY) | |
1807 | break; | |
1808 | mdelay(1); | |
1809 | } | |
1810 | ||
ebc2ec48 | 1811 | for (i = 0; i < RTL8152_MAX_RX; i++) |
1812 | usb_kill_urb(tp->rx_info[i].urb); | |
ac718b69 | 1813 | |
1814 | rtl8152_nic_reset(tp); | |
1815 | } | |
1816 | ||
00a5e360 | 1817 | static void r8152_power_cut_en(struct r8152 *tp, bool enable) |
1818 | { | |
1819 | u32 ocp_data; | |
1820 | ||
1821 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); | |
1822 | if (enable) | |
1823 | ocp_data |= POWER_CUT; | |
1824 | else | |
1825 | ocp_data &= ~POWER_CUT; | |
1826 | ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); | |
1827 | ||
1828 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); | |
1829 | ocp_data &= ~RESUME_INDICATE; | |
1830 | ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); | |
00a5e360 | 1831 | } |
1832 | ||
21ff2e89 | 1833 | #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) |
1834 | ||
1835 | static u32 __rtl_get_wol(struct r8152 *tp) | |
1836 | { | |
1837 | u32 ocp_data; | |
1838 | u32 wolopts = 0; | |
1839 | ||
1840 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5); | |
1841 | if (!(ocp_data & LAN_WAKE_EN)) | |
1842 | return 0; | |
1843 | ||
1844 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); | |
1845 | if (ocp_data & LINK_ON_WAKE_EN) | |
1846 | wolopts |= WAKE_PHY; | |
1847 | ||
1848 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); | |
1849 | if (ocp_data & UWF_EN) | |
1850 | wolopts |= WAKE_UCAST; | |
1851 | if (ocp_data & BWF_EN) | |
1852 | wolopts |= WAKE_BCAST; | |
1853 | if (ocp_data & MWF_EN) | |
1854 | wolopts |= WAKE_MCAST; | |
1855 | ||
1856 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); | |
1857 | if (ocp_data & MAGIC_EN) | |
1858 | wolopts |= WAKE_MAGIC; | |
1859 | ||
1860 | return wolopts; | |
1861 | } | |
1862 | ||
1863 | static void __rtl_set_wol(struct r8152 *tp, u32 wolopts) | |
1864 | { | |
1865 | u32 ocp_data; | |
1866 | ||
1867 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
1868 | ||
1869 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); | |
1870 | ocp_data &= ~LINK_ON_WAKE_EN; | |
1871 | if (wolopts & WAKE_PHY) | |
1872 | ocp_data |= LINK_ON_WAKE_EN; | |
1873 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); | |
1874 | ||
1875 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); | |
1876 | ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN); | |
1877 | if (wolopts & WAKE_UCAST) | |
1878 | ocp_data |= UWF_EN; | |
1879 | if (wolopts & WAKE_BCAST) | |
1880 | ocp_data |= BWF_EN; | |
1881 | if (wolopts & WAKE_MCAST) | |
1882 | ocp_data |= MWF_EN; | |
1883 | if (wolopts & WAKE_ANY) | |
1884 | ocp_data |= LAN_WAKE_EN; | |
1885 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data); | |
1886 | ||
1887 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
1888 | ||
1889 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); | |
1890 | ocp_data &= ~MAGIC_EN; | |
1891 | if (wolopts & WAKE_MAGIC) | |
1892 | ocp_data |= MAGIC_EN; | |
1893 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data); | |
1894 | ||
1895 | if (wolopts & WAKE_ANY) | |
1896 | device_set_wakeup_enable(&tp->udev->dev, true); | |
1897 | else | |
1898 | device_set_wakeup_enable(&tp->udev->dev, false); | |
1899 | } | |
1900 | ||
9a4be1bd | 1901 | static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable) |
1902 | { | |
1903 | if (enable) { | |
1904 | u32 ocp_data; | |
1905 | ||
1906 | __rtl_set_wol(tp, WAKE_ANY); | |
1907 | ||
1908 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
1909 | ||
1910 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); | |
1911 | ocp_data |= LINK_OFF_WAKE_EN; | |
1912 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); | |
1913 | ||
1914 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
1915 | } else { | |
1916 | __rtl_set_wol(tp, tp->saved_wolopts); | |
1917 | } | |
1918 | } | |
1919 | ||
aa66a5f1 | 1920 | static void rtl_phy_reset(struct r8152 *tp) |
1921 | { | |
1922 | u16 data; | |
1923 | int i; | |
1924 | ||
1925 | clear_bit(PHY_RESET, &tp->flags); | |
1926 | ||
1927 | data = r8152_mdio_read(tp, MII_BMCR); | |
1928 | ||
1929 | /* don't reset again before the previous one complete */ | |
1930 | if (data & BMCR_RESET) | |
1931 | return; | |
1932 | ||
1933 | data |= BMCR_RESET; | |
1934 | r8152_mdio_write(tp, MII_BMCR, data); | |
1935 | ||
1936 | for (i = 0; i < 50; i++) { | |
1937 | msleep(20); | |
1938 | if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) | |
1939 | break; | |
1940 | } | |
1941 | } | |
1942 | ||
4349968a | 1943 | static void rtl_clear_bp(struct r8152 *tp) |
1944 | { | |
1945 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_0, 0); | |
1946 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_2, 0); | |
1947 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_4, 0); | |
1948 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_6, 0); | |
1949 | ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_0, 0); | |
1950 | ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_2, 0); | |
1951 | ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_4, 0); | |
1952 | ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_6, 0); | |
1953 | mdelay(3); | |
1954 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_BA, 0); | |
1955 | ocp_write_word(tp, MCU_TYPE_USB, USB_BP_BA, 0); | |
1956 | } | |
1957 | ||
1958 | static void r8153_clear_bp(struct r8152 *tp) | |
1959 | { | |
1960 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_BP_EN, 0); | |
1961 | ocp_write_byte(tp, MCU_TYPE_USB, USB_BP_EN, 0); | |
1962 | rtl_clear_bp(tp); | |
1963 | } | |
1964 | ||
1965 | static void r8153_teredo_off(struct r8152 *tp) | |
1966 | { | |
1967 | u32 ocp_data; | |
1968 | ||
1969 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); | |
1970 | ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN); | |
1971 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); | |
1972 | ||
1973 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE); | |
1974 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0); | |
1975 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0); | |
1976 | } | |
1977 | ||
1978 | static void r8152b_disable_aldps(struct r8152 *tp) | |
1979 | { | |
1980 | ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE); | |
1981 | msleep(20); | |
1982 | } | |
1983 | ||
1984 | static inline void r8152b_enable_aldps(struct r8152 *tp) | |
1985 | { | |
1986 | ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS | | |
1987 | LINKENA | DIS_SDSAVE); | |
1988 | } | |
1989 | ||
1990 | static void r8152b_hw_phy_cfg(struct r8152 *tp) | |
1991 | { | |
f0cbe0ac | 1992 | u16 data; |
1993 | ||
1994 | data = r8152_mdio_read(tp, MII_BMCR); | |
1995 | if (data & BMCR_PDOWN) { | |
1996 | data &= ~BMCR_PDOWN; | |
1997 | r8152_mdio_write(tp, MII_BMCR, data); | |
1998 | } | |
1999 | ||
4349968a | 2000 | r8152b_disable_aldps(tp); |
7e9da481 | 2001 | |
2002 | rtl_clear_bp(tp); | |
2003 | ||
2004 | r8152b_enable_aldps(tp); | |
aa66a5f1 | 2005 | set_bit(PHY_RESET, &tp->flags); |
4349968a | 2006 | } |
2007 | ||
ac718b69 | 2008 | static void r8152b_exit_oob(struct r8152 *tp) |
2009 | { | |
db8515ef | 2010 | u32 ocp_data; |
2011 | int i; | |
ac718b69 | 2012 | |
2013 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2014 | ocp_data &= ~RCR_ACPT_ALL; | |
2015 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2016 | ||
00a5e360 | 2017 | rxdy_gated_en(tp, true); |
da9bd117 | 2018 | r8153_teredo_off(tp); |
7e9da481 | 2019 | r8152b_hw_phy_cfg(tp); |
ac718b69 | 2020 | |
2021 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
2022 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); | |
2023 | ||
2024 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2025 | ocp_data &= ~NOW_IS_OOB; | |
2026 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2027 | ||
2028 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2029 | ocp_data &= ~MCU_BORW_EN; | |
2030 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2031 | ||
2032 | for (i = 0; i < 1000; i++) { | |
2033 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2034 | if (ocp_data & LINK_LIST_READY) | |
2035 | break; | |
2036 | mdelay(1); | |
2037 | } | |
2038 | ||
2039 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2040 | ocp_data |= RE_INIT_LL; | |
2041 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2042 | ||
2043 | for (i = 0; i < 1000; i++) { | |
2044 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2045 | if (ocp_data & LINK_LIST_READY) | |
2046 | break; | |
2047 | mdelay(1); | |
2048 | } | |
2049 | ||
2050 | rtl8152_nic_reset(tp); | |
2051 | ||
2052 | /* rx share fifo credit full threshold */ | |
2053 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); | |
2054 | ||
2055 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_DEV_STAT); | |
2056 | ocp_data &= STAT_SPEED_MASK; | |
2057 | if (ocp_data == STAT_SPEED_FULL) { | |
2058 | /* rx share fifo credit near full threshold */ | |
2059 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, | |
2060 | RXFIFO_THR2_FULL); | |
2061 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, | |
2062 | RXFIFO_THR3_FULL); | |
2063 | } else { | |
2064 | /* rx share fifo credit near full threshold */ | |
2065 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, | |
2066 | RXFIFO_THR2_HIGH); | |
2067 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, | |
2068 | RXFIFO_THR3_HIGH); | |
2069 | } | |
2070 | ||
2071 | /* TX share fifo free credit full threshold */ | |
2072 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL); | |
2073 | ||
2074 | ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); | |
8e1f51bd | 2075 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH); |
ac718b69 | 2076 | ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA, |
2077 | TEST_MODE_DISABLE | TX_SIZE_ADJUST1); | |
2078 | ||
2079 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); | |
2080 | ocp_data &= ~CPCR_RX_VLAN; | |
2081 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); | |
2082 | ||
2083 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); | |
2084 | ||
2085 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); | |
2086 | ocp_data |= TCR0_AUTO_FIFO; | |
2087 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); | |
2088 | } | |
2089 | ||
2090 | static void r8152b_enter_oob(struct r8152 *tp) | |
2091 | { | |
45f4a19f | 2092 | u32 ocp_data; |
2093 | int i; | |
ac718b69 | 2094 | |
2095 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2096 | ocp_data &= ~NOW_IS_OOB; | |
2097 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2098 | ||
2099 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); | |
2100 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); | |
2101 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); | |
2102 | ||
2103 | rtl8152_disable(tp); | |
2104 | ||
2105 | for (i = 0; i < 1000; i++) { | |
2106 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2107 | if (ocp_data & LINK_LIST_READY) | |
2108 | break; | |
2109 | mdelay(1); | |
2110 | } | |
2111 | ||
2112 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2113 | ocp_data |= RE_INIT_LL; | |
2114 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2115 | ||
2116 | for (i = 0; i < 1000; i++) { | |
2117 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2118 | if (ocp_data & LINK_LIST_READY) | |
2119 | break; | |
2120 | mdelay(1); | |
2121 | } | |
2122 | ||
2123 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); | |
2124 | ||
ac718b69 | 2125 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); |
2126 | ocp_data |= CPCR_RX_VLAN; | |
2127 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); | |
2128 | ||
2129 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); | |
2130 | ocp_data |= ALDPS_PROXY_MODE; | |
2131 | ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); | |
2132 | ||
2133 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2134 | ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; | |
2135 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2136 | ||
00a5e360 | 2137 | rxdy_gated_en(tp, false); |
ac718b69 | 2138 | |
2139 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2140 | ocp_data |= RCR_APM | RCR_AM | RCR_AB; | |
2141 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2142 | } | |
2143 | ||
43779f8d | 2144 | static void r8153_hw_phy_cfg(struct r8152 *tp) |
2145 | { | |
2146 | u32 ocp_data; | |
2147 | u16 data; | |
2148 | ||
2149 | ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L); | |
f0cbe0ac | 2150 | data = r8152_mdio_read(tp, MII_BMCR); |
2151 | if (data & BMCR_PDOWN) { | |
2152 | data &= ~BMCR_PDOWN; | |
2153 | r8152_mdio_write(tp, MII_BMCR, data); | |
2154 | } | |
43779f8d | 2155 | |
7e9da481 | 2156 | r8153_clear_bp(tp); |
2157 | ||
43779f8d | 2158 | if (tp->version == RTL_VER_03) { |
2159 | data = ocp_reg_read(tp, OCP_EEE_CFG); | |
2160 | data &= ~CTAP_SHORT_EN; | |
2161 | ocp_reg_write(tp, OCP_EEE_CFG, data); | |
2162 | } | |
2163 | ||
2164 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
2165 | data |= EEE_CLKDIV_EN; | |
2166 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
2167 | ||
2168 | data = ocp_reg_read(tp, OCP_DOWN_SPEED); | |
2169 | data |= EN_10M_BGOFF; | |
2170 | ocp_reg_write(tp, OCP_DOWN_SPEED, data); | |
2171 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
2172 | data |= EN_10M_PLLOFF; | |
2173 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
2174 | data = sram_read(tp, SRAM_IMPEDANCE); | |
2175 | data &= ~RX_DRIVING_MASK; | |
2176 | sram_write(tp, SRAM_IMPEDANCE, data); | |
2177 | ||
2178 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); | |
2179 | ocp_data |= PFM_PWM_SWITCH; | |
2180 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); | |
2181 | ||
2182 | data = sram_read(tp, SRAM_LPF_CFG); | |
2183 | data |= LPF_AUTO_TUNE; | |
2184 | sram_write(tp, SRAM_LPF_CFG, data); | |
2185 | ||
2186 | data = sram_read(tp, SRAM_10M_AMP1); | |
2187 | data |= GDAC_IB_UPALL; | |
2188 | sram_write(tp, SRAM_10M_AMP1, data); | |
2189 | data = sram_read(tp, SRAM_10M_AMP2); | |
2190 | data |= AMP_DN; | |
2191 | sram_write(tp, SRAM_10M_AMP2, data); | |
aa66a5f1 | 2192 | |
2193 | set_bit(PHY_RESET, &tp->flags); | |
43779f8d | 2194 | } |
2195 | ||
b9702723 | 2196 | static void r8153_u1u2en(struct r8152 *tp, bool enable) |
43779f8d | 2197 | { |
2198 | u8 u1u2[8]; | |
2199 | ||
2200 | if (enable) | |
2201 | memset(u1u2, 0xff, sizeof(u1u2)); | |
2202 | else | |
2203 | memset(u1u2, 0x00, sizeof(u1u2)); | |
2204 | ||
2205 | usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2); | |
2206 | } | |
2207 | ||
b9702723 | 2208 | static void r8153_u2p3en(struct r8152 *tp, bool enable) |
43779f8d | 2209 | { |
2210 | u32 ocp_data; | |
2211 | ||
2212 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); | |
2213 | if (enable) | |
2214 | ocp_data |= U2P3_ENABLE; | |
2215 | else | |
2216 | ocp_data &= ~U2P3_ENABLE; | |
2217 | ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); | |
2218 | } | |
2219 | ||
b9702723 | 2220 | static void r8153_power_cut_en(struct r8152 *tp, bool enable) |
43779f8d | 2221 | { |
2222 | u32 ocp_data; | |
2223 | ||
2224 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); | |
2225 | if (enable) | |
2226 | ocp_data |= PWR_EN | PHASE2_EN; | |
2227 | else | |
2228 | ocp_data &= ~(PWR_EN | PHASE2_EN); | |
2229 | ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); | |
2230 | ||
2231 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); | |
2232 | ocp_data &= ~PCUT_STATUS; | |
2233 | ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); | |
2234 | } | |
2235 | ||
43779f8d | 2236 | static void r8153_first_init(struct r8152 *tp) |
2237 | { | |
2238 | u32 ocp_data; | |
2239 | int i; | |
2240 | ||
00a5e360 | 2241 | rxdy_gated_en(tp, true); |
43779f8d | 2242 | r8153_teredo_off(tp); |
2243 | ||
2244 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2245 | ocp_data &= ~RCR_ACPT_ALL; | |
2246 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2247 | ||
2248 | r8153_hw_phy_cfg(tp); | |
2249 | ||
2250 | rtl8152_nic_reset(tp); | |
2251 | ||
2252 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2253 | ocp_data &= ~NOW_IS_OOB; | |
2254 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2255 | ||
2256 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2257 | ocp_data &= ~MCU_BORW_EN; | |
2258 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2259 | ||
2260 | for (i = 0; i < 1000; i++) { | |
2261 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2262 | if (ocp_data & LINK_LIST_READY) | |
2263 | break; | |
2264 | mdelay(1); | |
2265 | } | |
2266 | ||
2267 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2268 | ocp_data |= RE_INIT_LL; | |
2269 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2270 | ||
2271 | for (i = 0; i < 1000; i++) { | |
2272 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2273 | if (ocp_data & LINK_LIST_READY) | |
2274 | break; | |
2275 | mdelay(1); | |
2276 | } | |
2277 | ||
2278 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); | |
2279 | ocp_data &= ~CPCR_RX_VLAN; | |
2280 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); | |
2281 | ||
2282 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); | |
2283 | ||
2284 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); | |
2285 | ocp_data |= TCR0_AUTO_FIFO; | |
2286 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); | |
2287 | ||
2288 | rtl8152_nic_reset(tp); | |
2289 | ||
2290 | /* rx share fifo credit full threshold */ | |
2291 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); | |
2292 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL); | |
2293 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL); | |
2294 | /* TX share fifo free credit full threshold */ | |
2295 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2); | |
2296 | ||
9629e3c0 | 2297 | /* rx aggregation */ |
43779f8d | 2298 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); |
2299 | ocp_data &= ~RX_AGG_DISABLE; | |
2300 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); | |
2301 | } | |
2302 | ||
2303 | static void r8153_enter_oob(struct r8152 *tp) | |
2304 | { | |
2305 | u32 ocp_data; | |
2306 | int i; | |
2307 | ||
2308 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2309 | ocp_data &= ~NOW_IS_OOB; | |
2310 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2311 | ||
2312 | rtl8152_disable(tp); | |
2313 | ||
2314 | for (i = 0; i < 1000; i++) { | |
2315 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2316 | if (ocp_data & LINK_LIST_READY) | |
2317 | break; | |
2318 | mdelay(1); | |
2319 | } | |
2320 | ||
2321 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2322 | ocp_data |= RE_INIT_LL; | |
2323 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2324 | ||
2325 | for (i = 0; i < 1000; i++) { | |
2326 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2327 | if (ocp_data & LINK_LIST_READY) | |
2328 | break; | |
2329 | mdelay(1); | |
2330 | } | |
2331 | ||
2332 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); | |
2333 | ||
43779f8d | 2334 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); |
2335 | ocp_data &= ~TEREDO_WAKE_MASK; | |
2336 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); | |
2337 | ||
2338 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); | |
2339 | ocp_data |= CPCR_RX_VLAN; | |
2340 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); | |
2341 | ||
2342 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); | |
2343 | ocp_data |= ALDPS_PROXY_MODE; | |
2344 | ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); | |
2345 | ||
2346 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2347 | ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; | |
2348 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2349 | ||
00a5e360 | 2350 | rxdy_gated_en(tp, false); |
43779f8d | 2351 | |
2352 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2353 | ocp_data |= RCR_APM | RCR_AM | RCR_AB; | |
2354 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2355 | } | |
2356 | ||
2357 | static void r8153_disable_aldps(struct r8152 *tp) | |
2358 | { | |
2359 | u16 data; | |
2360 | ||
2361 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
2362 | data &= ~EN_ALDPS; | |
2363 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
2364 | msleep(20); | |
2365 | } | |
2366 | ||
2367 | static void r8153_enable_aldps(struct r8152 *tp) | |
2368 | { | |
2369 | u16 data; | |
2370 | ||
2371 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
2372 | data |= EN_ALDPS; | |
2373 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
2374 | } | |
2375 | ||
ac718b69 | 2376 | static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex) |
2377 | { | |
43779f8d | 2378 | u16 bmcr, anar, gbcr; |
ac718b69 | 2379 | int ret = 0; |
2380 | ||
2381 | cancel_delayed_work_sync(&tp->schedule); | |
2382 | anar = r8152_mdio_read(tp, MII_ADVERTISE); | |
2383 | anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | | |
2384 | ADVERTISE_100HALF | ADVERTISE_100FULL); | |
43779f8d | 2385 | if (tp->mii.supports_gmii) { |
2386 | gbcr = r8152_mdio_read(tp, MII_CTRL1000); | |
2387 | gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); | |
2388 | } else { | |
2389 | gbcr = 0; | |
2390 | } | |
ac718b69 | 2391 | |
2392 | if (autoneg == AUTONEG_DISABLE) { | |
2393 | if (speed == SPEED_10) { | |
2394 | bmcr = 0; | |
2395 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
2396 | } else if (speed == SPEED_100) { | |
2397 | bmcr = BMCR_SPEED100; | |
2398 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; | |
43779f8d | 2399 | } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { |
2400 | bmcr = BMCR_SPEED1000; | |
2401 | gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; | |
ac718b69 | 2402 | } else { |
2403 | ret = -EINVAL; | |
2404 | goto out; | |
2405 | } | |
2406 | ||
2407 | if (duplex == DUPLEX_FULL) | |
2408 | bmcr |= BMCR_FULLDPLX; | |
2409 | } else { | |
2410 | if (speed == SPEED_10) { | |
2411 | if (duplex == DUPLEX_FULL) | |
2412 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
2413 | else | |
2414 | anar |= ADVERTISE_10HALF; | |
2415 | } else if (speed == SPEED_100) { | |
2416 | if (duplex == DUPLEX_FULL) { | |
2417 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
2418 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; | |
2419 | } else { | |
2420 | anar |= ADVERTISE_10HALF; | |
2421 | anar |= ADVERTISE_100HALF; | |
2422 | } | |
43779f8d | 2423 | } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { |
2424 | if (duplex == DUPLEX_FULL) { | |
2425 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
2426 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; | |
2427 | gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; | |
2428 | } else { | |
2429 | anar |= ADVERTISE_10HALF; | |
2430 | anar |= ADVERTISE_100HALF; | |
2431 | gbcr |= ADVERTISE_1000HALF; | |
2432 | } | |
ac718b69 | 2433 | } else { |
2434 | ret = -EINVAL; | |
2435 | goto out; | |
2436 | } | |
2437 | ||
2438 | bmcr = BMCR_ANENABLE | BMCR_ANRESTART; | |
2439 | } | |
2440 | ||
aa66a5f1 | 2441 | if (test_bit(PHY_RESET, &tp->flags)) |
2442 | bmcr |= BMCR_RESET; | |
2443 | ||
43779f8d | 2444 | if (tp->mii.supports_gmii) |
2445 | r8152_mdio_write(tp, MII_CTRL1000, gbcr); | |
2446 | ||
ac718b69 | 2447 | r8152_mdio_write(tp, MII_ADVERTISE, anar); |
2448 | r8152_mdio_write(tp, MII_BMCR, bmcr); | |
2449 | ||
aa66a5f1 | 2450 | if (test_bit(PHY_RESET, &tp->flags)) { |
2451 | int i; | |
2452 | ||
2453 | clear_bit(PHY_RESET, &tp->flags); | |
2454 | for (i = 0; i < 50; i++) { | |
2455 | msleep(20); | |
2456 | if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) | |
2457 | break; | |
2458 | } | |
2459 | } | |
2460 | ||
ac718b69 | 2461 | out: |
ac718b69 | 2462 | |
2463 | return ret; | |
2464 | } | |
2465 | ||
2466 | static void rtl8152_down(struct r8152 *tp) | |
2467 | { | |
00a5e360 | 2468 | r8152_power_cut_en(tp, false); |
ac718b69 | 2469 | r8152b_disable_aldps(tp); |
2470 | r8152b_enter_oob(tp); | |
2471 | r8152b_enable_aldps(tp); | |
2472 | } | |
2473 | ||
43779f8d | 2474 | static void rtl8153_down(struct r8152 *tp) |
2475 | { | |
b9702723 | 2476 | r8153_u1u2en(tp, false); |
2477 | r8153_power_cut_en(tp, false); | |
43779f8d | 2478 | r8153_disable_aldps(tp); |
2479 | r8153_enter_oob(tp); | |
2480 | r8153_enable_aldps(tp); | |
2481 | } | |
2482 | ||
ac718b69 | 2483 | static void set_carrier(struct r8152 *tp) |
2484 | { | |
2485 | struct net_device *netdev = tp->netdev; | |
2486 | u8 speed; | |
2487 | ||
40a82917 | 2488 | clear_bit(RTL8152_LINK_CHG, &tp->flags); |
ac718b69 | 2489 | speed = rtl8152_get_speed(tp); |
2490 | ||
2491 | if (speed & LINK_STATUS) { | |
2492 | if (!(tp->speed & LINK_STATUS)) { | |
c81229c9 | 2493 | tp->rtl_ops.enable(tp); |
ac718b69 | 2494 | set_bit(RTL8152_SET_RX_MODE, &tp->flags); |
2495 | netif_carrier_on(netdev); | |
2496 | } | |
2497 | } else { | |
2498 | if (tp->speed & LINK_STATUS) { | |
2499 | netif_carrier_off(netdev); | |
ebc2ec48 | 2500 | tasklet_disable(&tp->tl); |
c81229c9 | 2501 | tp->rtl_ops.disable(tp); |
ebc2ec48 | 2502 | tasklet_enable(&tp->tl); |
ac718b69 | 2503 | } |
2504 | } | |
2505 | tp->speed = speed; | |
2506 | } | |
2507 | ||
2508 | static void rtl_work_func_t(struct work_struct *work) | |
2509 | { | |
2510 | struct r8152 *tp = container_of(work, struct r8152, schedule.work); | |
2511 | ||
9a4be1bd | 2512 | if (usb_autopm_get_interface(tp->intf) < 0) |
2513 | return; | |
2514 | ||
ac718b69 | 2515 | if (!test_bit(WORK_ENABLE, &tp->flags)) |
2516 | goto out1; | |
2517 | ||
2518 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
2519 | goto out1; | |
2520 | ||
40a82917 | 2521 | if (test_bit(RTL8152_LINK_CHG, &tp->flags)) |
2522 | set_carrier(tp); | |
ac718b69 | 2523 | |
2524 | if (test_bit(RTL8152_SET_RX_MODE, &tp->flags)) | |
2525 | _rtl8152_set_rx_mode(tp->netdev); | |
2526 | ||
9a4be1bd | 2527 | if (tp->speed & LINK_STATUS) |
2528 | tx_bottom(tp); | |
aa66a5f1 | 2529 | |
2530 | if (test_bit(PHY_RESET, &tp->flags)) | |
2531 | rtl_phy_reset(tp); | |
2532 | ||
ac718b69 | 2533 | out1: |
9a4be1bd | 2534 | usb_autopm_put_interface(tp->intf); |
ac718b69 | 2535 | } |
2536 | ||
2537 | static int rtl8152_open(struct net_device *netdev) | |
2538 | { | |
2539 | struct r8152 *tp = netdev_priv(netdev); | |
2540 | int res = 0; | |
2541 | ||
7e9da481 | 2542 | res = alloc_all_mem(tp); |
2543 | if (res) | |
2544 | goto out; | |
2545 | ||
9a4be1bd | 2546 | res = usb_autopm_get_interface(tp->intf); |
2547 | if (res < 0) { | |
2548 | free_all_mem(tp); | |
2549 | goto out; | |
2550 | } | |
2551 | ||
2552 | /* The WORK_ENABLE may be set when autoresume occurs */ | |
2553 | if (test_bit(WORK_ENABLE, &tp->flags)) { | |
2554 | clear_bit(WORK_ENABLE, &tp->flags); | |
2555 | usb_kill_urb(tp->intr_urb); | |
2556 | cancel_delayed_work_sync(&tp->schedule); | |
2557 | if (tp->speed & LINK_STATUS) | |
2558 | tp->rtl_ops.disable(tp); | |
2559 | } | |
2560 | ||
7e9da481 | 2561 | tp->rtl_ops.up(tp); |
2562 | ||
3d55f44f | 2563 | rtl8152_set_speed(tp, AUTONEG_ENABLE, |
2564 | tp->mii.supports_gmii ? SPEED_1000 : SPEED_100, | |
2565 | DUPLEX_FULL); | |
2566 | tp->speed = 0; | |
2567 | netif_carrier_off(netdev); | |
2568 | netif_start_queue(netdev); | |
2569 | set_bit(WORK_ENABLE, &tp->flags); | |
db8515ef | 2570 | |
40a82917 | 2571 | res = usb_submit_urb(tp->intr_urb, GFP_KERNEL); |
2572 | if (res) { | |
2573 | if (res == -ENODEV) | |
2574 | netif_device_detach(tp->netdev); | |
4a8deae2 HW |
2575 | netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n", |
2576 | res); | |
7e9da481 | 2577 | free_all_mem(tp); |
ac718b69 | 2578 | } |
2579 | ||
9a4be1bd | 2580 | usb_autopm_put_interface(tp->intf); |
ac718b69 | 2581 | |
7e9da481 | 2582 | out: |
ac718b69 | 2583 | return res; |
2584 | } | |
2585 | ||
2586 | static int rtl8152_close(struct net_device *netdev) | |
2587 | { | |
2588 | struct r8152 *tp = netdev_priv(netdev); | |
2589 | int res = 0; | |
2590 | ||
2591 | clear_bit(WORK_ENABLE, &tp->flags); | |
3d55f44f | 2592 | usb_kill_urb(tp->intr_urb); |
ac718b69 | 2593 | cancel_delayed_work_sync(&tp->schedule); |
2594 | netif_stop_queue(netdev); | |
9a4be1bd | 2595 | |
2596 | res = usb_autopm_get_interface(tp->intf); | |
2597 | if (res < 0) { | |
2598 | rtl_drop_queued_tx(tp); | |
2599 | } else { | |
2600 | /* | |
2601 | * The autosuspend may have been enabled and wouldn't | |
2602 | * be disable when autoresume occurs, because the | |
2603 | * netif_running() would be false. | |
2604 | */ | |
2605 | if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { | |
2606 | rtl_runtime_suspend_enable(tp, false); | |
2607 | clear_bit(SELECTIVE_SUSPEND, &tp->flags); | |
2608 | } | |
2609 | ||
2610 | tasklet_disable(&tp->tl); | |
2611 | tp->rtl_ops.down(tp); | |
2612 | tasklet_enable(&tp->tl); | |
2613 | usb_autopm_put_interface(tp->intf); | |
2614 | } | |
ac718b69 | 2615 | |
7e9da481 | 2616 | free_all_mem(tp); |
2617 | ||
ac718b69 | 2618 | return res; |
2619 | } | |
2620 | ||
ac718b69 | 2621 | static void r8152b_enable_eee(struct r8152 *tp) |
2622 | { | |
45f4a19f | 2623 | u32 ocp_data; |
ac718b69 | 2624 | |
2625 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
2626 | ocp_data |= EEE_RX_EN | EEE_TX_EN; | |
2627 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); | |
2628 | ocp_reg_write(tp, OCP_EEE_CONFIG1, RG_TXLPI_MSK_HFDUP | RG_MATCLR_EN | | |
2629 | EEE_10_CAP | EEE_NWAY_EN | | |
2630 | TX_QUIET_EN | RX_QUIET_EN | | |
2631 | SDRISETIME | RG_RXLPI_MSK_HFDUP | | |
2632 | SDFALLTIME); | |
2633 | ocp_reg_write(tp, OCP_EEE_CONFIG2, RG_LPIHYS_NUM | RG_DACQUIET_EN | | |
2634 | RG_LDVQUIET_EN | RG_CKRSEL | | |
2635 | RG_EEEPRG_EN); | |
2636 | ocp_reg_write(tp, OCP_EEE_CONFIG3, FST_SNR_EYE_R | RG_LFS_SEL | MSK_PH); | |
2637 | ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | DEVICE_ADDR); | |
2638 | ocp_reg_write(tp, OCP_EEE_DATA, EEE_ADDR); | |
2639 | ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | DEVICE_ADDR); | |
2640 | ocp_reg_write(tp, OCP_EEE_DATA, EEE_DATA); | |
2641 | ocp_reg_write(tp, OCP_EEE_AR, 0x0000); | |
2642 | } | |
2643 | ||
43779f8d | 2644 | static void r8153_enable_eee(struct r8152 *tp) |
2645 | { | |
2646 | u32 ocp_data; | |
2647 | u16 data; | |
2648 | ||
2649 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
2650 | ocp_data |= EEE_RX_EN | EEE_TX_EN; | |
2651 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); | |
2652 | data = ocp_reg_read(tp, OCP_EEE_CFG); | |
2653 | data |= EEE10_EN; | |
2654 | ocp_reg_write(tp, OCP_EEE_CFG, data); | |
2655 | data = ocp_reg_read(tp, OCP_EEE_CFG2); | |
2656 | data |= MY1000_EEE | MY100_EEE; | |
2657 | ocp_reg_write(tp, OCP_EEE_CFG2, data); | |
2658 | } | |
2659 | ||
ac718b69 | 2660 | static void r8152b_enable_fc(struct r8152 *tp) |
2661 | { | |
2662 | u16 anar; | |
2663 | ||
2664 | anar = r8152_mdio_read(tp, MII_ADVERTISE); | |
2665 | anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; | |
2666 | r8152_mdio_write(tp, MII_ADVERTISE, anar); | |
2667 | } | |
2668 | ||
ac718b69 | 2669 | static void r8152b_init(struct r8152 *tp) |
2670 | { | |
ebc2ec48 | 2671 | u32 ocp_data; |
ac718b69 | 2672 | |
ac718b69 | 2673 | if (tp->version == RTL_VER_01) { |
2674 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); | |
2675 | ocp_data &= ~LED_MODE_MASK; | |
2676 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); | |
2677 | } | |
2678 | ||
00a5e360 | 2679 | r8152_power_cut_en(tp, false); |
ac718b69 | 2680 | |
ac718b69 | 2681 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); |
2682 | ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH; | |
2683 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); | |
2684 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); | |
2685 | ocp_data &= ~MCU_CLK_RATIO_MASK; | |
2686 | ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN; | |
2687 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); | |
2688 | ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK | | |
2689 | SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; | |
2690 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); | |
2691 | ||
2692 | r8152b_enable_eee(tp); | |
2693 | r8152b_enable_aldps(tp); | |
2694 | r8152b_enable_fc(tp); | |
2695 | ||
ebc2ec48 | 2696 | /* enable rx aggregation */ |
ac718b69 | 2697 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); |
ebc2ec48 | 2698 | ocp_data &= ~RX_AGG_DISABLE; |
ac718b69 | 2699 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); |
2700 | } | |
2701 | ||
43779f8d | 2702 | static void r8153_init(struct r8152 *tp) |
2703 | { | |
2704 | u32 ocp_data; | |
2705 | int i; | |
2706 | ||
b9702723 | 2707 | r8153_u1u2en(tp, false); |
43779f8d | 2708 | |
2709 | for (i = 0; i < 500; i++) { | |
2710 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & | |
2711 | AUTOLOAD_DONE) | |
2712 | break; | |
2713 | msleep(20); | |
2714 | } | |
2715 | ||
2716 | for (i = 0; i < 500; i++) { | |
2717 | ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK; | |
2718 | if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN) | |
2719 | break; | |
2720 | msleep(20); | |
2721 | } | |
2722 | ||
b9702723 | 2723 | r8153_u2p3en(tp, false); |
43779f8d | 2724 | |
2725 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL); | |
2726 | ocp_data &= ~TIMER11_EN; | |
2727 | ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data); | |
2728 | ||
43779f8d | 2729 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); |
2730 | ocp_data &= ~LED_MODE_MASK; | |
2731 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); | |
2732 | ||
2733 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL); | |
2734 | ocp_data &= ~LPM_TIMER_MASK; | |
2735 | if (tp->udev->speed == USB_SPEED_SUPER) | |
2736 | ocp_data |= LPM_TIMER_500US; | |
2737 | else | |
2738 | ocp_data |= LPM_TIMER_500MS; | |
2739 | ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data); | |
2740 | ||
2741 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2); | |
2742 | ocp_data &= ~SEN_VAL_MASK; | |
2743 | ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE; | |
2744 | ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data); | |
2745 | ||
b9702723 | 2746 | r8153_power_cut_en(tp, false); |
2747 | r8153_u1u2en(tp, true); | |
43779f8d | 2748 | |
43779f8d | 2749 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO); |
2750 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO); | |
2751 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, | |
2752 | PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN | | |
2753 | U1U2_SPDWN_EN | L1_SPDWN_EN); | |
2754 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, | |
2755 | PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN | | |
2756 | TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN | | |
2757 | EEE_SPDWN_EN); | |
2758 | ||
2759 | r8153_enable_eee(tp); | |
2760 | r8153_enable_aldps(tp); | |
2761 | r8152b_enable_fc(tp); | |
43779f8d | 2762 | } |
2763 | ||
ac718b69 | 2764 | static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message) |
2765 | { | |
2766 | struct r8152 *tp = usb_get_intfdata(intf); | |
2767 | ||
9a4be1bd | 2768 | if (PMSG_IS_AUTO(message)) |
2769 | set_bit(SELECTIVE_SUSPEND, &tp->flags); | |
2770 | else | |
2771 | netif_device_detach(tp->netdev); | |
ac718b69 | 2772 | |
2773 | if (netif_running(tp->netdev)) { | |
2774 | clear_bit(WORK_ENABLE, &tp->flags); | |
40a82917 | 2775 | usb_kill_urb(tp->intr_urb); |
ac718b69 | 2776 | cancel_delayed_work_sync(&tp->schedule); |
9a4be1bd | 2777 | if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { |
2778 | rtl_runtime_suspend_enable(tp, true); | |
2779 | } else { | |
2780 | tasklet_disable(&tp->tl); | |
2781 | tp->rtl_ops.down(tp); | |
2782 | tasklet_enable(&tp->tl); | |
2783 | } | |
ac718b69 | 2784 | } |
2785 | ||
ac718b69 | 2786 | return 0; |
2787 | } | |
2788 | ||
2789 | static int rtl8152_resume(struct usb_interface *intf) | |
2790 | { | |
2791 | struct r8152 *tp = usb_get_intfdata(intf); | |
2792 | ||
9a4be1bd | 2793 | if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) { |
2794 | tp->rtl_ops.init(tp); | |
2795 | netif_device_attach(tp->netdev); | |
2796 | } | |
2797 | ||
ac718b69 | 2798 | if (netif_running(tp->netdev)) { |
9a4be1bd | 2799 | if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { |
2800 | rtl_runtime_suspend_enable(tp, false); | |
2801 | clear_bit(SELECTIVE_SUSPEND, &tp->flags); | |
2802 | if (tp->speed & LINK_STATUS) | |
2803 | tp->rtl_ops.disable(tp); | |
2804 | } else { | |
2805 | tp->rtl_ops.up(tp); | |
2806 | rtl8152_set_speed(tp, AUTONEG_ENABLE, | |
43779f8d | 2807 | tp->mii.supports_gmii ? SPEED_1000 : SPEED_100, |
2808 | DUPLEX_FULL); | |
9a4be1bd | 2809 | } |
40a82917 | 2810 | tp->speed = 0; |
2811 | netif_carrier_off(tp->netdev); | |
ac718b69 | 2812 | set_bit(WORK_ENABLE, &tp->flags); |
40a82917 | 2813 | usb_submit_urb(tp->intr_urb, GFP_KERNEL); |
ac718b69 | 2814 | } |
2815 | ||
2816 | return 0; | |
2817 | } | |
2818 | ||
21ff2e89 | 2819 | static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
2820 | { | |
2821 | struct r8152 *tp = netdev_priv(dev); | |
2822 | ||
9a4be1bd | 2823 | if (usb_autopm_get_interface(tp->intf) < 0) |
2824 | return; | |
2825 | ||
21ff2e89 | 2826 | wol->supported = WAKE_ANY; |
2827 | wol->wolopts = __rtl_get_wol(tp); | |
9a4be1bd | 2828 | |
2829 | usb_autopm_put_interface(tp->intf); | |
21ff2e89 | 2830 | } |
2831 | ||
2832 | static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
2833 | { | |
2834 | struct r8152 *tp = netdev_priv(dev); | |
9a4be1bd | 2835 | int ret; |
2836 | ||
2837 | ret = usb_autopm_get_interface(tp->intf); | |
2838 | if (ret < 0) | |
2839 | goto out_set_wol; | |
21ff2e89 | 2840 | |
2841 | __rtl_set_wol(tp, wol->wolopts); | |
2842 | tp->saved_wolopts = wol->wolopts & WAKE_ANY; | |
2843 | ||
9a4be1bd | 2844 | usb_autopm_put_interface(tp->intf); |
2845 | ||
2846 | out_set_wol: | |
2847 | return ret; | |
21ff2e89 | 2848 | } |
2849 | ||
a5ec27c1 | 2850 | static u32 rtl8152_get_msglevel(struct net_device *dev) |
2851 | { | |
2852 | struct r8152 *tp = netdev_priv(dev); | |
2853 | ||
2854 | return tp->msg_enable; | |
2855 | } | |
2856 | ||
2857 | static void rtl8152_set_msglevel(struct net_device *dev, u32 value) | |
2858 | { | |
2859 | struct r8152 *tp = netdev_priv(dev); | |
2860 | ||
2861 | tp->msg_enable = value; | |
2862 | } | |
2863 | ||
ac718b69 | 2864 | static void rtl8152_get_drvinfo(struct net_device *netdev, |
2865 | struct ethtool_drvinfo *info) | |
2866 | { | |
2867 | struct r8152 *tp = netdev_priv(netdev); | |
2868 | ||
2869 | strncpy(info->driver, MODULENAME, ETHTOOL_BUSINFO_LEN); | |
2870 | strncpy(info->version, DRIVER_VERSION, ETHTOOL_BUSINFO_LEN); | |
2871 | usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info)); | |
2872 | } | |
2873 | ||
2874 | static | |
2875 | int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd) | |
2876 | { | |
2877 | struct r8152 *tp = netdev_priv(netdev); | |
2878 | ||
2879 | if (!tp->mii.mdio_read) | |
2880 | return -EOPNOTSUPP; | |
2881 | ||
2882 | return mii_ethtool_gset(&tp->mii, cmd); | |
2883 | } | |
2884 | ||
2885 | static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
2886 | { | |
2887 | struct r8152 *tp = netdev_priv(dev); | |
9a4be1bd | 2888 | int ret; |
2889 | ||
2890 | ret = usb_autopm_get_interface(tp->intf); | |
2891 | if (ret < 0) | |
2892 | goto out; | |
ac718b69 | 2893 | |
9a4be1bd | 2894 | ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex); |
2895 | ||
2896 | usb_autopm_put_interface(tp->intf); | |
2897 | ||
2898 | out: | |
2899 | return ret; | |
ac718b69 | 2900 | } |
2901 | ||
2902 | static struct ethtool_ops ops = { | |
2903 | .get_drvinfo = rtl8152_get_drvinfo, | |
2904 | .get_settings = rtl8152_get_settings, | |
2905 | .set_settings = rtl8152_set_settings, | |
2906 | .get_link = ethtool_op_get_link, | |
a5ec27c1 | 2907 | .get_msglevel = rtl8152_get_msglevel, |
2908 | .set_msglevel = rtl8152_set_msglevel, | |
21ff2e89 | 2909 | .get_wol = rtl8152_get_wol, |
2910 | .set_wol = rtl8152_set_wol, | |
ac718b69 | 2911 | }; |
2912 | ||
2913 | static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) | |
2914 | { | |
2915 | struct r8152 *tp = netdev_priv(netdev); | |
2916 | struct mii_ioctl_data *data = if_mii(rq); | |
9a4be1bd | 2917 | int res; |
2918 | ||
2919 | res = usb_autopm_get_interface(tp->intf); | |
2920 | if (res < 0) | |
2921 | goto out; | |
ac718b69 | 2922 | |
2923 | switch (cmd) { | |
2924 | case SIOCGMIIPHY: | |
2925 | data->phy_id = R8152_PHY_ID; /* Internal PHY */ | |
2926 | break; | |
2927 | ||
2928 | case SIOCGMIIREG: | |
2929 | data->val_out = r8152_mdio_read(tp, data->reg_num); | |
2930 | break; | |
2931 | ||
2932 | case SIOCSMIIREG: | |
2933 | if (!capable(CAP_NET_ADMIN)) { | |
2934 | res = -EPERM; | |
2935 | break; | |
2936 | } | |
2937 | r8152_mdio_write(tp, data->reg_num, data->val_in); | |
2938 | break; | |
2939 | ||
2940 | default: | |
2941 | res = -EOPNOTSUPP; | |
2942 | } | |
2943 | ||
9a4be1bd | 2944 | usb_autopm_put_interface(tp->intf); |
2945 | ||
2946 | out: | |
ac718b69 | 2947 | return res; |
2948 | } | |
2949 | ||
2950 | static const struct net_device_ops rtl8152_netdev_ops = { | |
2951 | .ndo_open = rtl8152_open, | |
2952 | .ndo_stop = rtl8152_close, | |
2953 | .ndo_do_ioctl = rtl8152_ioctl, | |
2954 | .ndo_start_xmit = rtl8152_start_xmit, | |
2955 | .ndo_tx_timeout = rtl8152_tx_timeout, | |
2956 | .ndo_set_rx_mode = rtl8152_set_rx_mode, | |
2957 | .ndo_set_mac_address = rtl8152_set_mac_address, | |
2958 | ||
2959 | .ndo_change_mtu = eth_change_mtu, | |
2960 | .ndo_validate_addr = eth_validate_addr, | |
2961 | }; | |
2962 | ||
2963 | static void r8152b_get_version(struct r8152 *tp) | |
2964 | { | |
2965 | u32 ocp_data; | |
2966 | u16 version; | |
2967 | ||
2968 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1); | |
2969 | version = (u16)(ocp_data & VERSION_MASK); | |
2970 | ||
2971 | switch (version) { | |
2972 | case 0x4c00: | |
2973 | tp->version = RTL_VER_01; | |
2974 | break; | |
2975 | case 0x4c10: | |
2976 | tp->version = RTL_VER_02; | |
2977 | break; | |
43779f8d | 2978 | case 0x5c00: |
2979 | tp->version = RTL_VER_03; | |
2980 | tp->mii.supports_gmii = 1; | |
2981 | break; | |
2982 | case 0x5c10: | |
2983 | tp->version = RTL_VER_04; | |
2984 | tp->mii.supports_gmii = 1; | |
2985 | break; | |
2986 | case 0x5c20: | |
2987 | tp->version = RTL_VER_05; | |
2988 | tp->mii.supports_gmii = 1; | |
2989 | break; | |
ac718b69 | 2990 | default: |
2991 | netif_info(tp, probe, tp->netdev, | |
2992 | "Unknown version 0x%04x\n", version); | |
2993 | break; | |
2994 | } | |
2995 | } | |
2996 | ||
e3fe0b1a | 2997 | static void rtl8152_unload(struct r8152 *tp) |
2998 | { | |
00a5e360 | 2999 | if (tp->version != RTL_VER_01) |
3000 | r8152_power_cut_en(tp, true); | |
e3fe0b1a | 3001 | } |
3002 | ||
43779f8d | 3003 | static void rtl8153_unload(struct r8152 *tp) |
3004 | { | |
b9702723 | 3005 | r8153_power_cut_en(tp, true); |
43779f8d | 3006 | } |
3007 | ||
31ca1dec | 3008 | static int rtl_ops_init(struct r8152 *tp, const struct usb_device_id *id) |
c81229c9 | 3009 | { |
3010 | struct rtl_ops *ops = &tp->rtl_ops; | |
31ca1dec | 3011 | int ret = -ENODEV; |
c81229c9 | 3012 | |
3013 | switch (id->idVendor) { | |
3014 | case VENDOR_ID_REALTEK: | |
3015 | switch (id->idProduct) { | |
3016 | case PRODUCT_ID_RTL8152: | |
3017 | ops->init = r8152b_init; | |
3018 | ops->enable = rtl8152_enable; | |
3019 | ops->disable = rtl8152_disable; | |
7e9da481 | 3020 | ops->up = r8152b_exit_oob; |
c81229c9 | 3021 | ops->down = rtl8152_down; |
3022 | ops->unload = rtl8152_unload; | |
31ca1dec | 3023 | ret = 0; |
c81229c9 | 3024 | break; |
43779f8d | 3025 | case PRODUCT_ID_RTL8153: |
3026 | ops->init = r8153_init; | |
3027 | ops->enable = rtl8153_enable; | |
3028 | ops->disable = rtl8152_disable; | |
7e9da481 | 3029 | ops->up = r8153_first_init; |
43779f8d | 3030 | ops->down = rtl8153_down; |
3031 | ops->unload = rtl8153_unload; | |
31ca1dec | 3032 | ret = 0; |
43779f8d | 3033 | break; |
3034 | default: | |
43779f8d | 3035 | break; |
3036 | } | |
3037 | break; | |
3038 | ||
3039 | case VENDOR_ID_SAMSUNG: | |
3040 | switch (id->idProduct) { | |
3041 | case PRODUCT_ID_SAMSUNG: | |
3042 | ops->init = r8153_init; | |
3043 | ops->enable = rtl8153_enable; | |
3044 | ops->disable = rtl8152_disable; | |
7e9da481 | 3045 | ops->up = r8153_first_init; |
43779f8d | 3046 | ops->down = rtl8153_down; |
3047 | ops->unload = rtl8153_unload; | |
31ca1dec | 3048 | ret = 0; |
43779f8d | 3049 | break; |
c81229c9 | 3050 | default: |
c81229c9 | 3051 | break; |
3052 | } | |
3053 | break; | |
3054 | ||
3055 | default: | |
c81229c9 | 3056 | break; |
3057 | } | |
3058 | ||
31ca1dec | 3059 | if (ret) |
3060 | netif_err(tp, probe, tp->netdev, "Unknown Device\n"); | |
3061 | ||
c81229c9 | 3062 | return ret; |
3063 | } | |
3064 | ||
ac718b69 | 3065 | static int rtl8152_probe(struct usb_interface *intf, |
3066 | const struct usb_device_id *id) | |
3067 | { | |
3068 | struct usb_device *udev = interface_to_usbdev(intf); | |
3069 | struct r8152 *tp; | |
3070 | struct net_device *netdev; | |
ebc2ec48 | 3071 | int ret; |
ac718b69 | 3072 | |
ac718b69 | 3073 | netdev = alloc_etherdev(sizeof(struct r8152)); |
3074 | if (!netdev) { | |
4a8deae2 | 3075 | dev_err(&intf->dev, "Out of memory\n"); |
ac718b69 | 3076 | return -ENOMEM; |
3077 | } | |
3078 | ||
ebc2ec48 | 3079 | SET_NETDEV_DEV(netdev, &intf->dev); |
ac718b69 | 3080 | tp = netdev_priv(netdev); |
3081 | tp->msg_enable = 0x7FFF; | |
3082 | ||
e3ad412a | 3083 | tp->udev = udev; |
3084 | tp->netdev = netdev; | |
3085 | tp->intf = intf; | |
3086 | ||
31ca1dec | 3087 | ret = rtl_ops_init(tp, id); |
3088 | if (ret) | |
3089 | goto out; | |
c81229c9 | 3090 | |
ebc2ec48 | 3091 | tasklet_init(&tp->tl, bottom_half, (unsigned long)tp); |
ac718b69 | 3092 | INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t); |
3093 | ||
ac718b69 | 3094 | netdev->netdev_ops = &rtl8152_netdev_ops; |
3095 | netdev->watchdog_timeo = RTL8152_TX_TIMEOUT; | |
5bd23881 | 3096 | |
3097 | netdev->features |= NETIF_F_IP_CSUM; | |
3098 | netdev->hw_features = NETIF_F_IP_CSUM; | |
db8515ef | 3099 | |
ac718b69 | 3100 | SET_ETHTOOL_OPS(netdev, &ops); |
ac718b69 | 3101 | |
3102 | tp->mii.dev = netdev; | |
3103 | tp->mii.mdio_read = read_mii_word; | |
3104 | tp->mii.mdio_write = write_mii_word; | |
3105 | tp->mii.phy_id_mask = 0x3f; | |
3106 | tp->mii.reg_num_mask = 0x1f; | |
3107 | tp->mii.phy_id = R8152_PHY_ID; | |
3108 | tp->mii.supports_gmii = 0; | |
3109 | ||
9a4be1bd | 3110 | intf->needs_remote_wakeup = 1; |
3111 | ||
ac718b69 | 3112 | r8152b_get_version(tp); |
c81229c9 | 3113 | tp->rtl_ops.init(tp); |
ac718b69 | 3114 | set_ethernet_addr(tp); |
3115 | ||
ac718b69 | 3116 | usb_set_intfdata(intf, tp); |
ac718b69 | 3117 | |
ebc2ec48 | 3118 | ret = register_netdev(netdev); |
3119 | if (ret != 0) { | |
4a8deae2 | 3120 | netif_err(tp, probe, netdev, "couldn't register the device\n"); |
ebc2ec48 | 3121 | goto out1; |
ac718b69 | 3122 | } |
3123 | ||
21ff2e89 | 3124 | tp->saved_wolopts = __rtl_get_wol(tp); |
3125 | if (tp->saved_wolopts) | |
3126 | device_set_wakeup_enable(&udev->dev, true); | |
3127 | else | |
3128 | device_set_wakeup_enable(&udev->dev, false); | |
3129 | ||
4a8deae2 | 3130 | netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION); |
ac718b69 | 3131 | |
3132 | return 0; | |
3133 | ||
ac718b69 | 3134 | out1: |
ebc2ec48 | 3135 | usb_set_intfdata(intf, NULL); |
ac718b69 | 3136 | out: |
3137 | free_netdev(netdev); | |
ebc2ec48 | 3138 | return ret; |
ac718b69 | 3139 | } |
3140 | ||
ac718b69 | 3141 | static void rtl8152_disconnect(struct usb_interface *intf) |
3142 | { | |
3143 | struct r8152 *tp = usb_get_intfdata(intf); | |
3144 | ||
3145 | usb_set_intfdata(intf, NULL); | |
3146 | if (tp) { | |
3147 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
3148 | tasklet_kill(&tp->tl); | |
3149 | unregister_netdev(tp->netdev); | |
c81229c9 | 3150 | tp->rtl_ops.unload(tp); |
ac718b69 | 3151 | free_netdev(tp->netdev); |
3152 | } | |
3153 | } | |
3154 | ||
3155 | /* table of devices that work with this driver */ | |
3156 | static struct usb_device_id rtl8152_table[] = { | |
c7de7dec | 3157 | {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8152)}, |
3158 | {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8153)}, | |
3159 | {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, PRODUCT_ID_SAMSUNG)}, | |
ac718b69 | 3160 | {} |
3161 | }; | |
3162 | ||
3163 | MODULE_DEVICE_TABLE(usb, rtl8152_table); | |
3164 | ||
3165 | static struct usb_driver rtl8152_driver = { | |
3166 | .name = MODULENAME, | |
ebc2ec48 | 3167 | .id_table = rtl8152_table, |
ac718b69 | 3168 | .probe = rtl8152_probe, |
3169 | .disconnect = rtl8152_disconnect, | |
ac718b69 | 3170 | .suspend = rtl8152_suspend, |
ebc2ec48 | 3171 | .resume = rtl8152_resume, |
3172 | .reset_resume = rtl8152_resume, | |
9a4be1bd | 3173 | .supports_autosuspend = 1, |
a634782f | 3174 | .disable_hub_initiated_lpm = 1, |
ac718b69 | 3175 | }; |
3176 | ||
b4236daa | 3177 | module_usb_driver(rtl8152_driver); |
ac718b69 | 3178 | |
3179 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
3180 | MODULE_DESCRIPTION(DRIVER_DESC); | |
3181 | MODULE_LICENSE("GPL"); |