r8152: move r8152b_get_version
[linux-2.6-block.git] / drivers / net / usb / r8152.c
CommitLineData
ac718b69 1/*
c7de7dec 2 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
ac718b69 3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * version 2 as published by the Free Software Foundation.
7 *
8 */
9
ac718b69 10#include <linux/signal.h>
11#include <linux/slab.h>
12#include <linux/module.h>
ac718b69 13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/mii.h>
16#include <linux/ethtool.h>
17#include <linux/usb.h>
18#include <linux/crc32.h>
19#include <linux/if_vlan.h>
20#include <linux/uaccess.h>
ebc2ec48 21#include <linux/list.h>
5bd23881 22#include <linux/ip.h>
23#include <linux/ipv6.h>
6128d1bb 24#include <net/ip6_checksum.h>
4c4a6b1b 25#include <uapi/linux/mdio.h>
26#include <linux/mdio.h>
ac718b69 27
28/* Version Information */
b5403273 29#define DRIVER_VERSION "v1.07.0 (2014/10/09)"
ac718b69 30#define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
44d942a9 31#define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
ac718b69 32#define MODULENAME "r8152"
33
34#define R8152_PHY_ID 32
35
36#define PLA_IDR 0xc000
37#define PLA_RCR 0xc010
38#define PLA_RMS 0xc016
39#define PLA_RXFIFO_CTRL0 0xc0a0
40#define PLA_RXFIFO_CTRL1 0xc0a4
41#define PLA_RXFIFO_CTRL2 0xc0a8
42#define PLA_FMC 0xc0b4
43#define PLA_CFG_WOL 0xc0b6
43779f8d 44#define PLA_TEREDO_CFG 0xc0bc
ac718b69 45#define PLA_MAR 0xcd00
43779f8d 46#define PLA_BACKUP 0xd000
ac718b69 47#define PAL_BDC_CR 0xd1a0
43779f8d 48#define PLA_TEREDO_TIMER 0xd2cc
49#define PLA_REALWOW_TIMER 0xd2e8
ac718b69 50#define PLA_LEDSEL 0xdd90
51#define PLA_LED_FEATURE 0xdd92
52#define PLA_PHYAR 0xde00
43779f8d 53#define PLA_BOOT_CTRL 0xe004
ac718b69 54#define PLA_GPHY_INTR_IMR 0xe022
55#define PLA_EEE_CR 0xe040
56#define PLA_EEEP_CR 0xe080
57#define PLA_MAC_PWR_CTRL 0xe0c0
43779f8d 58#define PLA_MAC_PWR_CTRL2 0xe0ca
59#define PLA_MAC_PWR_CTRL3 0xe0cc
60#define PLA_MAC_PWR_CTRL4 0xe0ce
61#define PLA_WDT6_CTRL 0xe428
ac718b69 62#define PLA_TCR0 0xe610
63#define PLA_TCR1 0xe612
69b4b7a4 64#define PLA_MTPS 0xe615
ac718b69 65#define PLA_TXFIFO_CTRL 0xe618
4f1d4d54 66#define PLA_RSTTALLY 0xe800
ac718b69 67#define PLA_CR 0xe813
68#define PLA_CRWECR 0xe81c
21ff2e89 69#define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
70#define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
ac718b69 71#define PLA_CONFIG5 0xe822
72#define PLA_PHY_PWR 0xe84c
73#define PLA_OOB_CTRL 0xe84f
74#define PLA_CPCR 0xe854
75#define PLA_MISC_0 0xe858
76#define PLA_MISC_1 0xe85a
77#define PLA_OCP_GPHY_BASE 0xe86c
4f1d4d54 78#define PLA_TALLYCNT 0xe890
ac718b69 79#define PLA_SFF_STS_7 0xe8de
80#define PLA_PHYSTATUS 0xe908
81#define PLA_BP_BA 0xfc26
82#define PLA_BP_0 0xfc28
83#define PLA_BP_1 0xfc2a
84#define PLA_BP_2 0xfc2c
85#define PLA_BP_3 0xfc2e
86#define PLA_BP_4 0xfc30
87#define PLA_BP_5 0xfc32
88#define PLA_BP_6 0xfc34
89#define PLA_BP_7 0xfc36
43779f8d 90#define PLA_BP_EN 0xfc38
ac718b69 91
43779f8d 92#define USB_U2P3_CTRL 0xb460
ac718b69 93#define USB_DEV_STAT 0xb808
94#define USB_USB_CTRL 0xd406
95#define USB_PHY_CTRL 0xd408
96#define USB_TX_AGG 0xd40a
97#define USB_RX_BUF_TH 0xd40c
98#define USB_USB_TIMER 0xd428
43779f8d 99#define USB_RX_EARLY_AGG 0xd42c
ac718b69 100#define USB_PM_CTRL_STATUS 0xd432
101#define USB_TX_DMA 0xd434
43779f8d 102#define USB_TOLERANCE 0xd490
103#define USB_LPM_CTRL 0xd41a
ac718b69 104#define USB_UPS_CTRL 0xd800
43779f8d 105#define USB_MISC_0 0xd81a
106#define USB_POWER_CUT 0xd80a
107#define USB_AFE_CTRL2 0xd824
108#define USB_WDT11_CTRL 0xe43c
ac718b69 109#define USB_BP_BA 0xfc26
110#define USB_BP_0 0xfc28
111#define USB_BP_1 0xfc2a
112#define USB_BP_2 0xfc2c
113#define USB_BP_3 0xfc2e
114#define USB_BP_4 0xfc30
115#define USB_BP_5 0xfc32
116#define USB_BP_6 0xfc34
117#define USB_BP_7 0xfc36
43779f8d 118#define USB_BP_EN 0xfc38
ac718b69 119
120/* OCP Registers */
121#define OCP_ALDPS_CONFIG 0x2010
122#define OCP_EEE_CONFIG1 0x2080
123#define OCP_EEE_CONFIG2 0x2092
124#define OCP_EEE_CONFIG3 0x2094
ac244d3e 125#define OCP_BASE_MII 0xa400
ac718b69 126#define OCP_EEE_AR 0xa41a
127#define OCP_EEE_DATA 0xa41c
43779f8d 128#define OCP_PHY_STATUS 0xa420
129#define OCP_POWER_CFG 0xa430
130#define OCP_EEE_CFG 0xa432
131#define OCP_SRAM_ADDR 0xa436
132#define OCP_SRAM_DATA 0xa438
133#define OCP_DOWN_SPEED 0xa442
df35d283 134#define OCP_EEE_ABLE 0xa5c4
4c4a6b1b 135#define OCP_EEE_ADV 0xa5d0
df35d283 136#define OCP_EEE_LPABLE 0xa5d2
43779f8d 137#define OCP_ADC_CFG 0xbc06
138
139/* SRAM Register */
140#define SRAM_LPF_CFG 0x8012
141#define SRAM_10M_AMP1 0x8080
142#define SRAM_10M_AMP2 0x8082
143#define SRAM_IMPEDANCE 0x8084
ac718b69 144
145/* PLA_RCR */
146#define RCR_AAP 0x00000001
147#define RCR_APM 0x00000002
148#define RCR_AM 0x00000004
149#define RCR_AB 0x00000008
150#define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
151
152/* PLA_RXFIFO_CTRL0 */
153#define RXFIFO_THR1_NORMAL 0x00080002
154#define RXFIFO_THR1_OOB 0x01800003
155
156/* PLA_RXFIFO_CTRL1 */
157#define RXFIFO_THR2_FULL 0x00000060
158#define RXFIFO_THR2_HIGH 0x00000038
159#define RXFIFO_THR2_OOB 0x0000004a
43779f8d 160#define RXFIFO_THR2_NORMAL 0x00a0
ac718b69 161
162/* PLA_RXFIFO_CTRL2 */
163#define RXFIFO_THR3_FULL 0x00000078
164#define RXFIFO_THR3_HIGH 0x00000048
165#define RXFIFO_THR3_OOB 0x0000005a
43779f8d 166#define RXFIFO_THR3_NORMAL 0x0110
ac718b69 167
168/* PLA_TXFIFO_CTRL */
169#define TXFIFO_THR_NORMAL 0x00400008
43779f8d 170#define TXFIFO_THR_NORMAL2 0x01000008
ac718b69 171
172/* PLA_FMC */
173#define FMC_FCR_MCU_EN 0x0001
174
175/* PLA_EEEP_CR */
176#define EEEP_CR_EEEP_TX 0x0002
177
43779f8d 178/* PLA_WDT6_CTRL */
179#define WDT6_SET_MODE 0x0010
180
ac718b69 181/* PLA_TCR0 */
182#define TCR0_TX_EMPTY 0x0800
183#define TCR0_AUTO_FIFO 0x0080
184
185/* PLA_TCR1 */
186#define VERSION_MASK 0x7cf0
187
69b4b7a4 188/* PLA_MTPS */
189#define MTPS_JUMBO (12 * 1024 / 64)
190#define MTPS_DEFAULT (6 * 1024 / 64)
191
4f1d4d54 192/* PLA_RSTTALLY */
193#define TALLY_RESET 0x0001
194
ac718b69 195/* PLA_CR */
196#define CR_RST 0x10
197#define CR_RE 0x08
198#define CR_TE 0x04
199
200/* PLA_CRWECR */
201#define CRWECR_NORAML 0x00
202#define CRWECR_CONFIG 0xc0
203
204/* PLA_OOB_CTRL */
205#define NOW_IS_OOB 0x80
206#define TXFIFO_EMPTY 0x20
207#define RXFIFO_EMPTY 0x10
208#define LINK_LIST_READY 0x02
209#define DIS_MCU_CLROOB 0x01
210#define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
211
212/* PLA_MISC_1 */
213#define RXDY_GATED_EN 0x0008
214
215/* PLA_SFF_STS_7 */
216#define RE_INIT_LL 0x8000
217#define MCU_BORW_EN 0x4000
218
219/* PLA_CPCR */
220#define CPCR_RX_VLAN 0x0040
221
222/* PLA_CFG_WOL */
223#define MAGIC_EN 0x0001
224
43779f8d 225/* PLA_TEREDO_CFG */
226#define TEREDO_SEL 0x8000
227#define TEREDO_WAKE_MASK 0x7f00
228#define TEREDO_RS_EVENT_MASK 0x00fe
229#define OOB_TEREDO_EN 0x0001
230
ac718b69 231/* PAL_BDC_CR */
232#define ALDPS_PROXY_MODE 0x0001
233
21ff2e89 234/* PLA_CONFIG34 */
235#define LINK_ON_WAKE_EN 0x0010
236#define LINK_OFF_WAKE_EN 0x0008
237
ac718b69 238/* PLA_CONFIG5 */
21ff2e89 239#define BWF_EN 0x0040
240#define MWF_EN 0x0020
241#define UWF_EN 0x0010
ac718b69 242#define LAN_WAKE_EN 0x0002
243
244/* PLA_LED_FEATURE */
245#define LED_MODE_MASK 0x0700
246
247/* PLA_PHY_PWR */
248#define TX_10M_IDLE_EN 0x0080
249#define PFM_PWM_SWITCH 0x0040
250
251/* PLA_MAC_PWR_CTRL */
252#define D3_CLK_GATED_EN 0x00004000
253#define MCU_CLK_RATIO 0x07010f07
254#define MCU_CLK_RATIO_MASK 0x0f0f0f0f
43779f8d 255#define ALDPS_SPDWN_RATIO 0x0f87
256
257/* PLA_MAC_PWR_CTRL2 */
258#define EEE_SPDWN_RATIO 0x8007
259
260/* PLA_MAC_PWR_CTRL3 */
261#define PKT_AVAIL_SPDWN_EN 0x0100
262#define SUSPEND_SPDWN_EN 0x0004
263#define U1U2_SPDWN_EN 0x0002
264#define L1_SPDWN_EN 0x0001
265
266/* PLA_MAC_PWR_CTRL4 */
267#define PWRSAVE_SPDWN_EN 0x1000
268#define RXDV_SPDWN_EN 0x0800
269#define TX10MIDLE_EN 0x0100
270#define TP100_SPDWN_EN 0x0020
271#define TP500_SPDWN_EN 0x0010
272#define TP1000_SPDWN_EN 0x0008
273#define EEE_SPDWN_EN 0x0001
ac718b69 274
275/* PLA_GPHY_INTR_IMR */
276#define GPHY_STS_MSK 0x0001
277#define SPEED_DOWN_MSK 0x0002
278#define SPDWN_RXDV_MSK 0x0004
279#define SPDWN_LINKCHG_MSK 0x0008
280
281/* PLA_PHYAR */
282#define PHYAR_FLAG 0x80000000
283
284/* PLA_EEE_CR */
285#define EEE_RX_EN 0x0001
286#define EEE_TX_EN 0x0002
287
43779f8d 288/* PLA_BOOT_CTRL */
289#define AUTOLOAD_DONE 0x0002
290
ac718b69 291/* USB_DEV_STAT */
292#define STAT_SPEED_MASK 0x0006
293#define STAT_SPEED_HIGH 0x0000
a3cc465d 294#define STAT_SPEED_FULL 0x0002
ac718b69 295
296/* USB_TX_AGG */
297#define TX_AGG_MAX_THRESHOLD 0x03
298
299/* USB_RX_BUF_TH */
43779f8d 300#define RX_THR_SUPPER 0x0c350180
8e1f51bd 301#define RX_THR_HIGH 0x7a120180
43779f8d 302#define RX_THR_SLOW 0xffff0180
ac718b69 303
304/* USB_TX_DMA */
305#define TEST_MODE_DISABLE 0x00000001
306#define TX_SIZE_ADJUST1 0x00000100
307
308/* USB_UPS_CTRL */
309#define POWER_CUT 0x0100
310
311/* USB_PM_CTRL_STATUS */
8e1f51bd 312#define RESUME_INDICATE 0x0001
ac718b69 313
314/* USB_USB_CTRL */
315#define RX_AGG_DISABLE 0x0010
316
43779f8d 317/* USB_U2P3_CTRL */
318#define U2P3_ENABLE 0x0001
319
320/* USB_POWER_CUT */
321#define PWR_EN 0x0001
322#define PHASE2_EN 0x0008
323
324/* USB_MISC_0 */
325#define PCUT_STATUS 0x0001
326
327/* USB_RX_EARLY_AGG */
328#define EARLY_AGG_SUPPER 0x0e832981
329#define EARLY_AGG_HIGH 0x0e837a12
330#define EARLY_AGG_SLOW 0x0e83ffff
331
332/* USB_WDT11_CTRL */
333#define TIMER11_EN 0x0001
334
335/* USB_LPM_CTRL */
336#define LPM_TIMER_MASK 0x0c
337#define LPM_TIMER_500MS 0x04 /* 500 ms */
338#define LPM_TIMER_500US 0x0c /* 500 us */
339
340/* USB_AFE_CTRL2 */
341#define SEN_VAL_MASK 0xf800
342#define SEN_VAL_NORMAL 0xa000
343#define SEL_RXIDLE 0x0100
344
ac718b69 345/* OCP_ALDPS_CONFIG */
346#define ENPWRSAVE 0x8000
347#define ENPDNPS 0x0200
348#define LINKENA 0x0100
349#define DIS_SDSAVE 0x0010
350
43779f8d 351/* OCP_PHY_STATUS */
352#define PHY_STAT_MASK 0x0007
353#define PHY_STAT_LAN_ON 3
354#define PHY_STAT_PWRDN 5
355
356/* OCP_POWER_CFG */
357#define EEE_CLKDIV_EN 0x8000
358#define EN_ALDPS 0x0004
359#define EN_10M_PLLOFF 0x0001
360
ac718b69 361/* OCP_EEE_CONFIG1 */
362#define RG_TXLPI_MSK_HFDUP 0x8000
363#define RG_MATCLR_EN 0x4000
364#define EEE_10_CAP 0x2000
365#define EEE_NWAY_EN 0x1000
366#define TX_QUIET_EN 0x0200
367#define RX_QUIET_EN 0x0100
d24f6134 368#define sd_rise_time_mask 0x0070
4c4a6b1b 369#define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
ac718b69 370#define RG_RXLPI_MSK_HFDUP 0x0008
371#define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
372
373/* OCP_EEE_CONFIG2 */
374#define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
375#define RG_DACQUIET_EN 0x0400
376#define RG_LDVQUIET_EN 0x0200
377#define RG_CKRSEL 0x0020
378#define RG_EEEPRG_EN 0x0010
379
380/* OCP_EEE_CONFIG3 */
d24f6134 381#define fast_snr_mask 0xff80
4c4a6b1b 382#define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
ac718b69 383#define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
384#define MSK_PH 0x0006 /* bit 0 ~ 3 */
385
386/* OCP_EEE_AR */
387/* bit[15:14] function */
388#define FUN_ADDR 0x0000
389#define FUN_DATA 0x4000
390/* bit[4:0] device addr */
ac718b69 391
43779f8d 392/* OCP_EEE_CFG */
393#define CTAP_SHORT_EN 0x0040
394#define EEE10_EN 0x0010
395
396/* OCP_DOWN_SPEED */
397#define EN_10M_BGOFF 0x0080
398
43779f8d 399/* OCP_ADC_CFG */
400#define CKADSEL_L 0x0100
401#define ADC_EN 0x0080
402#define EN_EMI_L 0x0040
403
404/* SRAM_LPF_CFG */
405#define LPF_AUTO_TUNE 0x8000
406
407/* SRAM_10M_AMP1 */
408#define GDAC_IB_UPALL 0x0008
409
410/* SRAM_10M_AMP2 */
411#define AMP_DN 0x0200
412
413/* SRAM_IMPEDANCE */
414#define RX_DRIVING_MASK 0x6000
415
ac718b69 416enum rtl_register_content {
43779f8d 417 _1000bps = 0x10,
ac718b69 418 _100bps = 0x08,
419 _10bps = 0x04,
420 LINK_STATUS = 0x02,
421 FULL_DUP = 0x01,
422};
423
1764bcd9 424#define RTL8152_MAX_TX 4
ebc2ec48 425#define RTL8152_MAX_RX 10
40a82917 426#define INTBUFSIZE 2
8e1f51bd 427#define CRC_SIZE 4
428#define TX_ALIGN 4
429#define RX_ALIGN 8
40a82917 430
431#define INTR_LINK 0x0004
ebc2ec48 432
ac718b69 433#define RTL8152_REQT_READ 0xc0
434#define RTL8152_REQT_WRITE 0x40
435#define RTL8152_REQ_GET_REGS 0x05
436#define RTL8152_REQ_SET_REGS 0x05
437
438#define BYTE_EN_DWORD 0xff
439#define BYTE_EN_WORD 0x33
440#define BYTE_EN_BYTE 0x11
441#define BYTE_EN_SIX_BYTES 0x3f
442#define BYTE_EN_START_MASK 0x0f
443#define BYTE_EN_END_MASK 0xf0
444
69b4b7a4 445#define RTL8153_MAX_PACKET 9216 /* 9K */
446#define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN)
ac718b69 447#define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
69b4b7a4 448#define RTL8153_RMS RTL8153_MAX_PACKET
b8125404 449#define RTL8152_TX_TIMEOUT (5 * HZ)
ac718b69 450
451/* rtl8152 flags */
452enum rtl8152_flags {
453 RTL8152_UNPLUG = 0,
ac718b69 454 RTL8152_SET_RX_MODE,
40a82917 455 WORK_ENABLE,
456 RTL8152_LINK_CHG,
9a4be1bd 457 SELECTIVE_SUSPEND,
aa66a5f1 458 PHY_RESET,
0c3121fc 459 SCHEDULE_TASKLET,
ac718b69 460};
461
462/* Define these values to match your device */
463#define VENDOR_ID_REALTEK 0x0bda
464#define PRODUCT_ID_RTL8152 0x8152
43779f8d 465#define PRODUCT_ID_RTL8153 0x8153
466
467#define VENDOR_ID_SAMSUNG 0x04e8
468#define PRODUCT_ID_SAMSUNG 0xa101
ac718b69 469
470#define MCU_TYPE_PLA 0x0100
471#define MCU_TYPE_USB 0x0000
472
c7de7dec 473#define REALTEK_USB_DEVICE(vend, prod) \
474 USB_DEVICE_INTERFACE_CLASS(vend, prod, USB_CLASS_VENDOR_SPEC)
475
4f1d4d54 476struct tally_counter {
477 __le64 tx_packets;
478 __le64 rx_packets;
479 __le64 tx_errors;
480 __le32 rx_errors;
481 __le16 rx_missed;
482 __le16 align_errors;
483 __le32 tx_one_collision;
484 __le32 tx_multi_collision;
485 __le64 rx_unicast;
486 __le64 rx_broadcast;
487 __le32 rx_multicast;
488 __le16 tx_aborted;
f37119c5 489 __le16 tx_underrun;
4f1d4d54 490};
491
ac718b69 492struct rx_desc {
500b6d7e 493 __le32 opts1;
ac718b69 494#define RX_LEN_MASK 0x7fff
565cab0a 495
500b6d7e 496 __le32 opts2;
565cab0a 497#define RD_UDP_CS (1 << 23)
498#define RD_TCP_CS (1 << 22)
6128d1bb 499#define RD_IPV6_CS (1 << 20)
565cab0a 500#define RD_IPV4_CS (1 << 19)
501
500b6d7e 502 __le32 opts3;
565cab0a 503#define IPF (1 << 23) /* IP checksum fail */
504#define UDPF (1 << 22) /* UDP checksum fail */
505#define TCPF (1 << 21) /* TCP checksum fail */
c5554298 506#define RX_VLAN_TAG (1 << 16)
565cab0a 507
500b6d7e 508 __le32 opts4;
509 __le32 opts5;
510 __le32 opts6;
ac718b69 511};
512
513struct tx_desc {
500b6d7e 514 __le32 opts1;
ac718b69 515#define TX_FS (1 << 31) /* First segment of a packet */
516#define TX_LS (1 << 30) /* Final segment of a packet */
60c89071 517#define GTSENDV4 (1 << 28)
6128d1bb 518#define GTSENDV6 (1 << 27)
60c89071 519#define GTTCPHO_SHIFT 18
6128d1bb 520#define GTTCPHO_MAX 0x7fU
60c89071 521#define TX_LEN_MAX 0x3ffffU
5bd23881 522
500b6d7e 523 __le32 opts2;
5bd23881 524#define UDP_CS (1 << 31) /* Calculate UDP/IP checksum */
525#define TCP_CS (1 << 30) /* Calculate TCP/IP checksum */
526#define IPV4_CS (1 << 29) /* Calculate IPv4 checksum */
527#define IPV6_CS (1 << 28) /* Calculate IPv6 checksum */
60c89071 528#define MSS_SHIFT 17
529#define MSS_MAX 0x7ffU
530#define TCPHO_SHIFT 17
6128d1bb 531#define TCPHO_MAX 0x7ffU
c5554298 532#define TX_VLAN_TAG (1 << 16)
ac718b69 533};
534
dff4e8ad 535struct r8152;
536
ebc2ec48 537struct rx_agg {
538 struct list_head list;
539 struct urb *urb;
dff4e8ad 540 struct r8152 *context;
ebc2ec48 541 void *buffer;
542 void *head;
543};
544
545struct tx_agg {
546 struct list_head list;
547 struct urb *urb;
dff4e8ad 548 struct r8152 *context;
ebc2ec48 549 void *buffer;
550 void *head;
551 u32 skb_num;
552 u32 skb_len;
553};
554
ac718b69 555struct r8152 {
556 unsigned long flags;
557 struct usb_device *udev;
558 struct tasklet_struct tl;
40a82917 559 struct usb_interface *intf;
ac718b69 560 struct net_device *netdev;
40a82917 561 struct urb *intr_urb;
ebc2ec48 562 struct tx_agg tx_info[RTL8152_MAX_TX];
563 struct rx_agg rx_info[RTL8152_MAX_RX];
564 struct list_head rx_done, tx_free;
565 struct sk_buff_head tx_queue;
566 spinlock_t rx_lock, tx_lock;
ac718b69 567 struct delayed_work schedule;
568 struct mii_if_info mii;
b5403273 569 struct mutex control; /* use for hw setting */
c81229c9 570
571 struct rtl_ops {
572 void (*init)(struct r8152 *);
573 int (*enable)(struct r8152 *);
574 void (*disable)(struct r8152 *);
7e9da481 575 void (*up)(struct r8152 *);
c81229c9 576 void (*down)(struct r8152 *);
577 void (*unload)(struct r8152 *);
df35d283 578 int (*eee_get)(struct r8152 *, struct ethtool_eee *);
579 int (*eee_set)(struct r8152 *, struct ethtool_eee *);
c81229c9 580 } rtl_ops;
581
40a82917 582 int intr_interval;
21ff2e89 583 u32 saved_wolopts;
ac718b69 584 u32 msg_enable;
dd1b119c 585 u32 tx_qlen;
ac718b69 586 u16 ocp_base;
40a82917 587 u8 *intr_buff;
ac718b69 588 u8 version;
589 u8 speed;
590};
591
592enum rtl_version {
593 RTL_VER_UNKNOWN = 0,
594 RTL_VER_01,
43779f8d 595 RTL_VER_02,
596 RTL_VER_03,
597 RTL_VER_04,
598 RTL_VER_05,
599 RTL_VER_MAX
ac718b69 600};
601
60c89071 602enum tx_csum_stat {
603 TX_CSUM_SUCCESS = 0,
604 TX_CSUM_TSO,
605 TX_CSUM_NONE
606};
607
ac718b69 608/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
609 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
610 */
611static const int multicast_filter_limit = 32;
52aec126 612static unsigned int agg_buf_sz = 16384;
ac718b69 613
52aec126 614#define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \
60c89071 615 VLAN_ETH_HLEN - VLAN_HLEN)
616
ac718b69 617static
618int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
619{
31787f53 620 int ret;
621 void *tmp;
622
623 tmp = kmalloc(size, GFP_KERNEL);
624 if (!tmp)
625 return -ENOMEM;
626
627 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
b209af99 628 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
629 value, index, tmp, size, 500);
31787f53 630
631 memcpy(data, tmp, size);
632 kfree(tmp);
633
634 return ret;
ac718b69 635}
636
637static
638int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
639{
31787f53 640 int ret;
641 void *tmp;
642
c4438f03 643 tmp = kmemdup(data, size, GFP_KERNEL);
31787f53 644 if (!tmp)
645 return -ENOMEM;
646
31787f53 647 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
b209af99 648 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
649 value, index, tmp, size, 500);
31787f53 650
651 kfree(tmp);
db8515ef 652
31787f53 653 return ret;
ac718b69 654}
655
656static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
b209af99 657 void *data, u16 type)
ac718b69 658{
45f4a19f 659 u16 limit = 64;
660 int ret = 0;
ac718b69 661
662 if (test_bit(RTL8152_UNPLUG, &tp->flags))
663 return -ENODEV;
664
665 /* both size and indix must be 4 bytes align */
666 if ((size & 3) || !size || (index & 3) || !data)
667 return -EPERM;
668
669 if ((u32)index + (u32)size > 0xffff)
670 return -EPERM;
671
672 while (size) {
673 if (size > limit) {
674 ret = get_registers(tp, index, type, limit, data);
675 if (ret < 0)
676 break;
677
678 index += limit;
679 data += limit;
680 size -= limit;
681 } else {
682 ret = get_registers(tp, index, type, size, data);
683 if (ret < 0)
684 break;
685
686 index += size;
687 data += size;
688 size = 0;
689 break;
690 }
691 }
692
67610496 693 if (ret == -ENODEV)
694 set_bit(RTL8152_UNPLUG, &tp->flags);
695
ac718b69 696 return ret;
697}
698
699static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
b209af99 700 u16 size, void *data, u16 type)
ac718b69 701{
45f4a19f 702 int ret;
703 u16 byteen_start, byteen_end, byen;
704 u16 limit = 512;
ac718b69 705
706 if (test_bit(RTL8152_UNPLUG, &tp->flags))
707 return -ENODEV;
708
709 /* both size and indix must be 4 bytes align */
710 if ((size & 3) || !size || (index & 3) || !data)
711 return -EPERM;
712
713 if ((u32)index + (u32)size > 0xffff)
714 return -EPERM;
715
716 byteen_start = byteen & BYTE_EN_START_MASK;
717 byteen_end = byteen & BYTE_EN_END_MASK;
718
719 byen = byteen_start | (byteen_start << 4);
720 ret = set_registers(tp, index, type | byen, 4, data);
721 if (ret < 0)
722 goto error1;
723
724 index += 4;
725 data += 4;
726 size -= 4;
727
728 if (size) {
729 size -= 4;
730
731 while (size) {
732 if (size > limit) {
733 ret = set_registers(tp, index,
b209af99 734 type | BYTE_EN_DWORD,
735 limit, data);
ac718b69 736 if (ret < 0)
737 goto error1;
738
739 index += limit;
740 data += limit;
741 size -= limit;
742 } else {
743 ret = set_registers(tp, index,
b209af99 744 type | BYTE_EN_DWORD,
745 size, data);
ac718b69 746 if (ret < 0)
747 goto error1;
748
749 index += size;
750 data += size;
751 size = 0;
752 break;
753 }
754 }
755
756 byen = byteen_end | (byteen_end >> 4);
757 ret = set_registers(tp, index, type | byen, 4, data);
758 if (ret < 0)
759 goto error1;
760 }
761
762error1:
67610496 763 if (ret == -ENODEV)
764 set_bit(RTL8152_UNPLUG, &tp->flags);
765
ac718b69 766 return ret;
767}
768
769static inline
770int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
771{
772 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
773}
774
775static inline
776int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
777{
778 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
779}
780
781static inline
782int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
783{
784 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
785}
786
787static inline
788int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
789{
790 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
791}
792
793static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
794{
c8826de8 795 __le32 data;
ac718b69 796
c8826de8 797 generic_ocp_read(tp, index, sizeof(data), &data, type);
ac718b69 798
799 return __le32_to_cpu(data);
800}
801
802static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
803{
c8826de8 804 __le32 tmp = __cpu_to_le32(data);
805
806 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
ac718b69 807}
808
809static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
810{
811 u32 data;
c8826de8 812 __le32 tmp;
ac718b69 813 u8 shift = index & 2;
814
815 index &= ~3;
816
c8826de8 817 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
ac718b69 818
c8826de8 819 data = __le32_to_cpu(tmp);
ac718b69 820 data >>= (shift * 8);
821 data &= 0xffff;
822
823 return (u16)data;
824}
825
826static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
827{
c8826de8 828 u32 mask = 0xffff;
829 __le32 tmp;
ac718b69 830 u16 byen = BYTE_EN_WORD;
831 u8 shift = index & 2;
832
833 data &= mask;
834
835 if (index & 2) {
836 byen <<= shift;
837 mask <<= (shift * 8);
838 data <<= (shift * 8);
839 index &= ~3;
840 }
841
c8826de8 842 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
ac718b69 843
c8826de8 844 data |= __le32_to_cpu(tmp) & ~mask;
845 tmp = __cpu_to_le32(data);
ac718b69 846
c8826de8 847 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
ac718b69 848}
849
850static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
851{
852 u32 data;
c8826de8 853 __le32 tmp;
ac718b69 854 u8 shift = index & 3;
855
856 index &= ~3;
857
c8826de8 858 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
ac718b69 859
c8826de8 860 data = __le32_to_cpu(tmp);
ac718b69 861 data >>= (shift * 8);
862 data &= 0xff;
863
864 return (u8)data;
865}
866
867static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
868{
c8826de8 869 u32 mask = 0xff;
870 __le32 tmp;
ac718b69 871 u16 byen = BYTE_EN_BYTE;
872 u8 shift = index & 3;
873
874 data &= mask;
875
876 if (index & 3) {
877 byen <<= shift;
878 mask <<= (shift * 8);
879 data <<= (shift * 8);
880 index &= ~3;
881 }
882
c8826de8 883 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
ac718b69 884
c8826de8 885 data |= __le32_to_cpu(tmp) & ~mask;
886 tmp = __cpu_to_le32(data);
ac718b69 887
c8826de8 888 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
ac718b69 889}
890
ac244d3e 891static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
e3fe0b1a 892{
893 u16 ocp_base, ocp_index;
894
895 ocp_base = addr & 0xf000;
896 if (ocp_base != tp->ocp_base) {
897 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
898 tp->ocp_base = ocp_base;
899 }
900
901 ocp_index = (addr & 0x0fff) | 0xb000;
ac244d3e 902 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
e3fe0b1a 903}
904
ac244d3e 905static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
ac718b69 906{
ac244d3e 907 u16 ocp_base, ocp_index;
ac718b69 908
ac244d3e 909 ocp_base = addr & 0xf000;
910 if (ocp_base != tp->ocp_base) {
911 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
912 tp->ocp_base = ocp_base;
ac718b69 913 }
ac244d3e 914
915 ocp_index = (addr & 0x0fff) | 0xb000;
916 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
ac718b69 917}
918
ac244d3e 919static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
ac718b69 920{
ac244d3e 921 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
922}
ac718b69 923
ac244d3e 924static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
925{
926 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
ac718b69 927}
928
43779f8d 929static void sram_write(struct r8152 *tp, u16 addr, u16 data)
930{
931 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
932 ocp_reg_write(tp, OCP_SRAM_DATA, data);
933}
934
935static u16 sram_read(struct r8152 *tp, u16 addr)
936{
937 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
938 return ocp_reg_read(tp, OCP_SRAM_DATA);
939}
940
ac718b69 941static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
942{
943 struct r8152 *tp = netdev_priv(netdev);
9a4be1bd 944 int ret;
ac718b69 945
6871438c 946 if (test_bit(RTL8152_UNPLUG, &tp->flags))
947 return -ENODEV;
948
ac718b69 949 if (phy_id != R8152_PHY_ID)
950 return -EINVAL;
951
9a4be1bd 952 ret = r8152_mdio_read(tp, reg);
953
9a4be1bd 954 return ret;
ac718b69 955}
956
957static
958void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
959{
960 struct r8152 *tp = netdev_priv(netdev);
961
6871438c 962 if (test_bit(RTL8152_UNPLUG, &tp->flags))
963 return;
964
ac718b69 965 if (phy_id != R8152_PHY_ID)
966 return;
967
968 r8152_mdio_write(tp, reg, val);
969}
970
b209af99 971static int
972r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
ebc2ec48 973
8ba789ab 974static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
975{
976 struct r8152 *tp = netdev_priv(netdev);
977 struct sockaddr *addr = p;
ea6a7112 978 int ret = -EADDRNOTAVAIL;
8ba789ab 979
980 if (!is_valid_ether_addr(addr->sa_data))
ea6a7112 981 goto out1;
982
983 ret = usb_autopm_get_interface(tp->intf);
984 if (ret < 0)
985 goto out1;
8ba789ab 986
b5403273 987 mutex_lock(&tp->control);
988
8ba789ab 989 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
990
991 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
992 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
993 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
994
b5403273 995 mutex_unlock(&tp->control);
996
ea6a7112 997 usb_autopm_put_interface(tp->intf);
998out1:
999 return ret;
8ba789ab 1000}
1001
179bb6d7 1002static int set_ethernet_addr(struct r8152 *tp)
ac718b69 1003{
1004 struct net_device *dev = tp->netdev;
179bb6d7 1005 struct sockaddr sa;
8a91c824 1006 int ret;
ac718b69 1007
8a91c824 1008 if (tp->version == RTL_VER_01)
179bb6d7 1009 ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data);
8a91c824 1010 else
179bb6d7 1011 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data);
8a91c824 1012
1013 if (ret < 0) {
179bb6d7 1014 netif_err(tp, probe, dev, "Get ether addr fail\n");
1015 } else if (!is_valid_ether_addr(sa.sa_data)) {
1016 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1017 sa.sa_data);
1018 eth_hw_addr_random(dev);
1019 ether_addr_copy(sa.sa_data, dev->dev_addr);
1020 ret = rtl8152_set_mac_address(dev, &sa);
1021 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1022 sa.sa_data);
8a91c824 1023 } else {
179bb6d7 1024 if (tp->version == RTL_VER_01)
1025 ether_addr_copy(dev->dev_addr, sa.sa_data);
1026 else
1027 ret = rtl8152_set_mac_address(dev, &sa);
ac718b69 1028 }
179bb6d7 1029
1030 return ret;
ac718b69 1031}
1032
ac718b69 1033static void read_bulk_callback(struct urb *urb)
1034{
ac718b69 1035 struct net_device *netdev;
ac718b69 1036 int status = urb->status;
ebc2ec48 1037 struct rx_agg *agg;
1038 struct r8152 *tp;
ac718b69 1039 int result;
ac718b69 1040
ebc2ec48 1041 agg = urb->context;
1042 if (!agg)
1043 return;
1044
1045 tp = agg->context;
ac718b69 1046 if (!tp)
1047 return;
ebc2ec48 1048
ac718b69 1049 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1050 return;
ebc2ec48 1051
1052 if (!test_bit(WORK_ENABLE, &tp->flags))
1053 return;
1054
ac718b69 1055 netdev = tp->netdev;
7559fb2f 1056
1057 /* When link down, the driver would cancel all bulks. */
1058 /* This avoid the re-submitting bulk */
ebc2ec48 1059 if (!netif_carrier_ok(netdev))
ac718b69 1060 return;
1061
9a4be1bd 1062 usb_mark_last_busy(tp->udev);
1063
ac718b69 1064 switch (status) {
1065 case 0:
ebc2ec48 1066 if (urb->actual_length < ETH_ZLEN)
1067 break;
1068
2685d410 1069 spin_lock(&tp->rx_lock);
ebc2ec48 1070 list_add_tail(&agg->list, &tp->rx_done);
2685d410 1071 spin_unlock(&tp->rx_lock);
ebc2ec48 1072 tasklet_schedule(&tp->tl);
1073 return;
ac718b69 1074 case -ESHUTDOWN:
1075 set_bit(RTL8152_UNPLUG, &tp->flags);
1076 netif_device_detach(tp->netdev);
ebc2ec48 1077 return;
ac718b69 1078 case -ENOENT:
1079 return; /* the urb is in unlink state */
1080 case -ETIME:
4a8deae2
HW
1081 if (net_ratelimit())
1082 netdev_warn(netdev, "maybe reset is needed?\n");
ebc2ec48 1083 break;
ac718b69 1084 default:
4a8deae2
HW
1085 if (net_ratelimit())
1086 netdev_warn(netdev, "Rx status %d\n", status);
ebc2ec48 1087 break;
ac718b69 1088 }
1089
ebc2ec48 1090 result = r8152_submit_rx(tp, agg, GFP_ATOMIC);
ac718b69 1091 if (result == -ENODEV) {
67610496 1092 set_bit(RTL8152_UNPLUG, &tp->flags);
ac718b69 1093 netif_device_detach(tp->netdev);
1094 } else if (result) {
2685d410 1095 spin_lock(&tp->rx_lock);
ebc2ec48 1096 list_add_tail(&agg->list, &tp->rx_done);
2685d410 1097 spin_unlock(&tp->rx_lock);
ebc2ec48 1098 tasklet_schedule(&tp->tl);
ac718b69 1099 }
ac718b69 1100}
1101
ebc2ec48 1102static void write_bulk_callback(struct urb *urb)
ac718b69 1103{
ebc2ec48 1104 struct net_device_stats *stats;
d104eafa 1105 struct net_device *netdev;
ebc2ec48 1106 struct tx_agg *agg;
ac718b69 1107 struct r8152 *tp;
ebc2ec48 1108 int status = urb->status;
ac718b69 1109
ebc2ec48 1110 agg = urb->context;
1111 if (!agg)
ac718b69 1112 return;
1113
ebc2ec48 1114 tp = agg->context;
1115 if (!tp)
1116 return;
1117
d104eafa 1118 netdev = tp->netdev;
05e0f1aa 1119 stats = &netdev->stats;
ebc2ec48 1120 if (status) {
4a8deae2 1121 if (net_ratelimit())
d104eafa 1122 netdev_warn(netdev, "Tx status %d\n", status);
ebc2ec48 1123 stats->tx_errors += agg->skb_num;
ac718b69 1124 } else {
ebc2ec48 1125 stats->tx_packets += agg->skb_num;
1126 stats->tx_bytes += agg->skb_len;
ac718b69 1127 }
1128
2685d410 1129 spin_lock(&tp->tx_lock);
ebc2ec48 1130 list_add_tail(&agg->list, &tp->tx_free);
2685d410 1131 spin_unlock(&tp->tx_lock);
ebc2ec48 1132
9a4be1bd 1133 usb_autopm_put_interface_async(tp->intf);
1134
d104eafa 1135 if (!netif_carrier_ok(netdev))
ebc2ec48 1136 return;
1137
1138 if (!test_bit(WORK_ENABLE, &tp->flags))
1139 return;
1140
1141 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1142 return;
1143
1144 if (!skb_queue_empty(&tp->tx_queue))
0c3121fc 1145 tasklet_schedule(&tp->tl);
ac718b69 1146}
1147
40a82917 1148static void intr_callback(struct urb *urb)
1149{
1150 struct r8152 *tp;
500b6d7e 1151 __le16 *d;
40a82917 1152 int status = urb->status;
1153 int res;
1154
1155 tp = urb->context;
1156 if (!tp)
1157 return;
1158
1159 if (!test_bit(WORK_ENABLE, &tp->flags))
1160 return;
1161
1162 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1163 return;
1164
1165 switch (status) {
1166 case 0: /* success */
1167 break;
1168 case -ECONNRESET: /* unlink */
1169 case -ESHUTDOWN:
1170 netif_device_detach(tp->netdev);
1171 case -ENOENT:
d59c876d 1172 case -EPROTO:
1173 netif_info(tp, intr, tp->netdev,
1174 "Stop submitting intr, status %d\n", status);
40a82917 1175 return;
1176 case -EOVERFLOW:
1177 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1178 goto resubmit;
1179 /* -EPIPE: should clear the halt */
1180 default:
1181 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1182 goto resubmit;
1183 }
1184
1185 d = urb->transfer_buffer;
1186 if (INTR_LINK & __le16_to_cpu(d[0])) {
1187 if (!(tp->speed & LINK_STATUS)) {
1188 set_bit(RTL8152_LINK_CHG, &tp->flags);
1189 schedule_delayed_work(&tp->schedule, 0);
1190 }
1191 } else {
1192 if (tp->speed & LINK_STATUS) {
1193 set_bit(RTL8152_LINK_CHG, &tp->flags);
1194 schedule_delayed_work(&tp->schedule, 0);
1195 }
1196 }
1197
1198resubmit:
1199 res = usb_submit_urb(urb, GFP_ATOMIC);
67610496 1200 if (res == -ENODEV) {
1201 set_bit(RTL8152_UNPLUG, &tp->flags);
40a82917 1202 netif_device_detach(tp->netdev);
67610496 1203 } else if (res) {
40a82917 1204 netif_err(tp, intr, tp->netdev,
4a8deae2 1205 "can't resubmit intr, status %d\n", res);
67610496 1206 }
40a82917 1207}
1208
ebc2ec48 1209static inline void *rx_agg_align(void *data)
1210{
8e1f51bd 1211 return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
ebc2ec48 1212}
1213
1214static inline void *tx_agg_align(void *data)
1215{
8e1f51bd 1216 return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
ebc2ec48 1217}
1218
1219static void free_all_mem(struct r8152 *tp)
1220{
1221 int i;
1222
1223 for (i = 0; i < RTL8152_MAX_RX; i++) {
9629e3c0 1224 usb_free_urb(tp->rx_info[i].urb);
1225 tp->rx_info[i].urb = NULL;
ebc2ec48 1226
9629e3c0 1227 kfree(tp->rx_info[i].buffer);
1228 tp->rx_info[i].buffer = NULL;
1229 tp->rx_info[i].head = NULL;
ebc2ec48 1230 }
1231
1232 for (i = 0; i < RTL8152_MAX_TX; i++) {
9629e3c0 1233 usb_free_urb(tp->tx_info[i].urb);
1234 tp->tx_info[i].urb = NULL;
ebc2ec48 1235
9629e3c0 1236 kfree(tp->tx_info[i].buffer);
1237 tp->tx_info[i].buffer = NULL;
1238 tp->tx_info[i].head = NULL;
ebc2ec48 1239 }
40a82917 1240
9629e3c0 1241 usb_free_urb(tp->intr_urb);
1242 tp->intr_urb = NULL;
40a82917 1243
9629e3c0 1244 kfree(tp->intr_buff);
1245 tp->intr_buff = NULL;
ebc2ec48 1246}
1247
1248static int alloc_all_mem(struct r8152 *tp)
1249{
1250 struct net_device *netdev = tp->netdev;
40a82917 1251 struct usb_interface *intf = tp->intf;
1252 struct usb_host_interface *alt = intf->cur_altsetting;
1253 struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
ebc2ec48 1254 struct urb *urb;
1255 int node, i;
1256 u8 *buf;
1257
1258 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1259
1260 spin_lock_init(&tp->rx_lock);
1261 spin_lock_init(&tp->tx_lock);
1262 INIT_LIST_HEAD(&tp->rx_done);
1263 INIT_LIST_HEAD(&tp->tx_free);
1264 skb_queue_head_init(&tp->tx_queue);
1265
1266 for (i = 0; i < RTL8152_MAX_RX; i++) {
52aec126 1267 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
ebc2ec48 1268 if (!buf)
1269 goto err1;
1270
1271 if (buf != rx_agg_align(buf)) {
1272 kfree(buf);
52aec126 1273 buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL,
8e1f51bd 1274 node);
ebc2ec48 1275 if (!buf)
1276 goto err1;
1277 }
1278
1279 urb = usb_alloc_urb(0, GFP_KERNEL);
1280 if (!urb) {
1281 kfree(buf);
1282 goto err1;
1283 }
1284
1285 INIT_LIST_HEAD(&tp->rx_info[i].list);
1286 tp->rx_info[i].context = tp;
1287 tp->rx_info[i].urb = urb;
1288 tp->rx_info[i].buffer = buf;
1289 tp->rx_info[i].head = rx_agg_align(buf);
1290 }
1291
1292 for (i = 0; i < RTL8152_MAX_TX; i++) {
52aec126 1293 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
ebc2ec48 1294 if (!buf)
1295 goto err1;
1296
1297 if (buf != tx_agg_align(buf)) {
1298 kfree(buf);
52aec126 1299 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
8e1f51bd 1300 node);
ebc2ec48 1301 if (!buf)
1302 goto err1;
1303 }
1304
1305 urb = usb_alloc_urb(0, GFP_KERNEL);
1306 if (!urb) {
1307 kfree(buf);
1308 goto err1;
1309 }
1310
1311 INIT_LIST_HEAD(&tp->tx_info[i].list);
1312 tp->tx_info[i].context = tp;
1313 tp->tx_info[i].urb = urb;
1314 tp->tx_info[i].buffer = buf;
1315 tp->tx_info[i].head = tx_agg_align(buf);
1316
1317 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1318 }
1319
40a82917 1320 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1321 if (!tp->intr_urb)
1322 goto err1;
1323
1324 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1325 if (!tp->intr_buff)
1326 goto err1;
1327
1328 tp->intr_interval = (int)ep_intr->desc.bInterval;
1329 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
b209af99 1330 tp->intr_buff, INTBUFSIZE, intr_callback,
1331 tp, tp->intr_interval);
40a82917 1332
ebc2ec48 1333 return 0;
1334
1335err1:
1336 free_all_mem(tp);
1337 return -ENOMEM;
1338}
1339
0de98f6c 1340static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1341{
1342 struct tx_agg *agg = NULL;
1343 unsigned long flags;
1344
21949ab7 1345 if (list_empty(&tp->tx_free))
1346 return NULL;
1347
0de98f6c 1348 spin_lock_irqsave(&tp->tx_lock, flags);
1349 if (!list_empty(&tp->tx_free)) {
1350 struct list_head *cursor;
1351
1352 cursor = tp->tx_free.next;
1353 list_del_init(cursor);
1354 agg = list_entry(cursor, struct tx_agg, list);
1355 }
1356 spin_unlock_irqrestore(&tp->tx_lock, flags);
1357
1358 return agg;
1359}
1360
60c89071 1361static inline __be16 get_protocol(struct sk_buff *skb)
5bd23881 1362{
60c89071 1363 __be16 protocol;
5bd23881 1364
60c89071 1365 if (skb->protocol == htons(ETH_P_8021Q))
1366 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
1367 else
1368 protocol = skb->protocol;
5bd23881 1369
60c89071 1370 return protocol;
1371}
5bd23881 1372
b209af99 1373/* r8152_csum_workaround()
6128d1bb 1374 * The hw limites the value the transport offset. When the offset is out of the
1375 * range, calculate the checksum by sw.
1376 */
1377static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1378 struct sk_buff_head *list)
1379{
1380 if (skb_shinfo(skb)->gso_size) {
1381 netdev_features_t features = tp->netdev->features;
1382 struct sk_buff_head seg_list;
1383 struct sk_buff *segs, *nskb;
1384
a91d45f1 1385 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6128d1bb 1386 segs = skb_gso_segment(skb, features);
1387 if (IS_ERR(segs) || !segs)
1388 goto drop;
1389
1390 __skb_queue_head_init(&seg_list);
1391
1392 do {
1393 nskb = segs;
1394 segs = segs->next;
1395 nskb->next = NULL;
1396 __skb_queue_tail(&seg_list, nskb);
1397 } while (segs);
1398
1399 skb_queue_splice(&seg_list, list);
1400 dev_kfree_skb(skb);
1401 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1402 if (skb_checksum_help(skb) < 0)
1403 goto drop;
1404
1405 __skb_queue_head(list, skb);
1406 } else {
1407 struct net_device_stats *stats;
1408
1409drop:
1410 stats = &tp->netdev->stats;
1411 stats->tx_dropped++;
1412 dev_kfree_skb(skb);
1413 }
1414}
1415
b209af99 1416/* msdn_giant_send_check()
6128d1bb 1417 * According to the document of microsoft, the TCP Pseudo Header excludes the
1418 * packet length for IPv6 TCP large packets.
1419 */
1420static int msdn_giant_send_check(struct sk_buff *skb)
1421{
1422 const struct ipv6hdr *ipv6h;
1423 struct tcphdr *th;
fcb308d5 1424 int ret;
1425
1426 ret = skb_cow_head(skb, 0);
1427 if (ret)
1428 return ret;
6128d1bb 1429
1430 ipv6h = ipv6_hdr(skb);
1431 th = tcp_hdr(skb);
1432
1433 th->check = 0;
1434 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
1435
fcb308d5 1436 return ret;
6128d1bb 1437}
1438
c5554298 1439static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1440{
1441 if (vlan_tx_tag_present(skb)) {
1442 u32 opts2;
1443
1444 opts2 = TX_VLAN_TAG | swab16(vlan_tx_tag_get(skb));
1445 desc->opts2 |= cpu_to_le32(opts2);
1446 }
1447}
1448
1449static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1450{
1451 u32 opts2 = le32_to_cpu(desc->opts2);
1452
1453 if (opts2 & RX_VLAN_TAG)
1454 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1455 swab16(opts2 & 0xffff));
1456}
1457
60c89071 1458static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1459 struct sk_buff *skb, u32 len, u32 transport_offset)
1460{
1461 u32 mss = skb_shinfo(skb)->gso_size;
1462 u32 opts1, opts2 = 0;
1463 int ret = TX_CSUM_SUCCESS;
1464
1465 WARN_ON_ONCE(len > TX_LEN_MAX);
1466
1467 opts1 = len | TX_FS | TX_LS;
1468
1469 if (mss) {
6128d1bb 1470 if (transport_offset > GTTCPHO_MAX) {
1471 netif_warn(tp, tx_err, tp->netdev,
1472 "Invalid transport offset 0x%x for TSO\n",
1473 transport_offset);
1474 ret = TX_CSUM_TSO;
1475 goto unavailable;
1476 }
1477
60c89071 1478 switch (get_protocol(skb)) {
1479 case htons(ETH_P_IP):
1480 opts1 |= GTSENDV4;
1481 break;
1482
6128d1bb 1483 case htons(ETH_P_IPV6):
fcb308d5 1484 if (msdn_giant_send_check(skb)) {
1485 ret = TX_CSUM_TSO;
1486 goto unavailable;
1487 }
6128d1bb 1488 opts1 |= GTSENDV6;
6128d1bb 1489 break;
1490
60c89071 1491 default:
1492 WARN_ON_ONCE(1);
1493 break;
1494 }
1495
1496 opts1 |= transport_offset << GTTCPHO_SHIFT;
1497 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
1498 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1499 u8 ip_protocol;
5bd23881 1500
6128d1bb 1501 if (transport_offset > TCPHO_MAX) {
1502 netif_warn(tp, tx_err, tp->netdev,
1503 "Invalid transport offset 0x%x\n",
1504 transport_offset);
1505 ret = TX_CSUM_NONE;
1506 goto unavailable;
1507 }
1508
60c89071 1509 switch (get_protocol(skb)) {
5bd23881 1510 case htons(ETH_P_IP):
1511 opts2 |= IPV4_CS;
1512 ip_protocol = ip_hdr(skb)->protocol;
1513 break;
1514
1515 case htons(ETH_P_IPV6):
1516 opts2 |= IPV6_CS;
1517 ip_protocol = ipv6_hdr(skb)->nexthdr;
1518 break;
1519
1520 default:
1521 ip_protocol = IPPROTO_RAW;
1522 break;
1523 }
1524
60c89071 1525 if (ip_protocol == IPPROTO_TCP)
5bd23881 1526 opts2 |= TCP_CS;
60c89071 1527 else if (ip_protocol == IPPROTO_UDP)
5bd23881 1528 opts2 |= UDP_CS;
60c89071 1529 else
5bd23881 1530 WARN_ON_ONCE(1);
5bd23881 1531
60c89071 1532 opts2 |= transport_offset << TCPHO_SHIFT;
5bd23881 1533 }
60c89071 1534
1535 desc->opts2 = cpu_to_le32(opts2);
1536 desc->opts1 = cpu_to_le32(opts1);
1537
6128d1bb 1538unavailable:
60c89071 1539 return ret;
5bd23881 1540}
1541
b1379d9a 1542static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1543{
d84130a1 1544 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
9a4be1bd 1545 int remain, ret;
b1379d9a 1546 u8 *tx_data;
1547
d84130a1 1548 __skb_queue_head_init(&skb_head);
0c3121fc 1549 spin_lock(&tx_queue->lock);
d84130a1 1550 skb_queue_splice_init(tx_queue, &skb_head);
0c3121fc 1551 spin_unlock(&tx_queue->lock);
d84130a1 1552
b1379d9a 1553 tx_data = agg->head;
b209af99 1554 agg->skb_num = 0;
1555 agg->skb_len = 0;
52aec126 1556 remain = agg_buf_sz;
b1379d9a 1557
7937f9e5 1558 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
b1379d9a 1559 struct tx_desc *tx_desc;
1560 struct sk_buff *skb;
1561 unsigned int len;
60c89071 1562 u32 offset;
b1379d9a 1563
d84130a1 1564 skb = __skb_dequeue(&skb_head);
b1379d9a 1565 if (!skb)
1566 break;
1567
60c89071 1568 len = skb->len + sizeof(*tx_desc);
1569
1570 if (len > remain) {
d84130a1 1571 __skb_queue_head(&skb_head, skb);
b1379d9a 1572 break;
1573 }
1574
7937f9e5 1575 tx_data = tx_agg_align(tx_data);
b1379d9a 1576 tx_desc = (struct tx_desc *)tx_data;
60c89071 1577
1578 offset = (u32)skb_transport_offset(skb);
1579
6128d1bb 1580 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
1581 r8152_csum_workaround(tp, skb, &skb_head);
1582 continue;
1583 }
60c89071 1584
c5554298 1585 rtl_tx_vlan_tag(tx_desc, skb);
1586
b1379d9a 1587 tx_data += sizeof(*tx_desc);
1588
60c89071 1589 len = skb->len;
1590 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
1591 struct net_device_stats *stats = &tp->netdev->stats;
1592
1593 stats->tx_dropped++;
1594 dev_kfree_skb_any(skb);
1595 tx_data -= sizeof(*tx_desc);
1596 continue;
1597 }
1598
1599 tx_data += len;
b1379d9a 1600 agg->skb_len += len;
60c89071 1601 agg->skb_num++;
1602
b1379d9a 1603 dev_kfree_skb_any(skb);
1604
52aec126 1605 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
b1379d9a 1606 }
1607
d84130a1 1608 if (!skb_queue_empty(&skb_head)) {
0c3121fc 1609 spin_lock(&tx_queue->lock);
d84130a1 1610 skb_queue_splice(&skb_head, tx_queue);
0c3121fc 1611 spin_unlock(&tx_queue->lock);
d84130a1 1612 }
1613
0c3121fc 1614 netif_tx_lock(tp->netdev);
dd1b119c 1615
1616 if (netif_queue_stopped(tp->netdev) &&
1617 skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
1618 netif_wake_queue(tp->netdev);
1619
0c3121fc 1620 netif_tx_unlock(tp->netdev);
9a4be1bd 1621
0c3121fc 1622 ret = usb_autopm_get_interface_async(tp->intf);
9a4be1bd 1623 if (ret < 0)
1624 goto out_tx_fill;
dd1b119c 1625
b1379d9a 1626 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1627 agg->head, (int)(tx_data - (u8 *)agg->head),
1628 (usb_complete_t)write_bulk_callback, agg);
1629
0c3121fc 1630 ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
9a4be1bd 1631 if (ret < 0)
0c3121fc 1632 usb_autopm_put_interface_async(tp->intf);
9a4be1bd 1633
1634out_tx_fill:
1635 return ret;
b1379d9a 1636}
1637
565cab0a 1638static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
1639{
1640 u8 checksum = CHECKSUM_NONE;
1641 u32 opts2, opts3;
1642
1643 if (tp->version == RTL_VER_01)
1644 goto return_result;
1645
1646 opts2 = le32_to_cpu(rx_desc->opts2);
1647 opts3 = le32_to_cpu(rx_desc->opts3);
1648
1649 if (opts2 & RD_IPV4_CS) {
1650 if (opts3 & IPF)
1651 checksum = CHECKSUM_NONE;
1652 else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF))
1653 checksum = CHECKSUM_NONE;
1654 else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF))
1655 checksum = CHECKSUM_NONE;
1656 else
1657 checksum = CHECKSUM_UNNECESSARY;
6128d1bb 1658 } else if (RD_IPV6_CS) {
1659 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1660 checksum = CHECKSUM_UNNECESSARY;
1661 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1662 checksum = CHECKSUM_UNNECESSARY;
565cab0a 1663 }
1664
1665return_result:
1666 return checksum;
1667}
1668
ebc2ec48 1669static void rx_bottom(struct r8152 *tp)
1670{
a5a4f468 1671 unsigned long flags;
d84130a1 1672 struct list_head *cursor, *next, rx_queue;
ebc2ec48 1673
d84130a1 1674 if (list_empty(&tp->rx_done))
1675 return;
1676
1677 INIT_LIST_HEAD(&rx_queue);
a5a4f468 1678 spin_lock_irqsave(&tp->rx_lock, flags);
d84130a1 1679 list_splice_init(&tp->rx_done, &rx_queue);
1680 spin_unlock_irqrestore(&tp->rx_lock, flags);
1681
1682 list_for_each_safe(cursor, next, &rx_queue) {
43a4478d 1683 struct rx_desc *rx_desc;
1684 struct rx_agg *agg;
43a4478d 1685 int len_used = 0;
1686 struct urb *urb;
1687 u8 *rx_data;
1688 int ret;
1689
ebc2ec48 1690 list_del_init(cursor);
ebc2ec48 1691
1692 agg = list_entry(cursor, struct rx_agg, list);
1693 urb = agg->urb;
0de98f6c 1694 if (urb->actual_length < ETH_ZLEN)
1695 goto submit;
ebc2ec48 1696
ebc2ec48 1697 rx_desc = agg->head;
1698 rx_data = agg->head;
7937f9e5 1699 len_used += sizeof(struct rx_desc);
ebc2ec48 1700
7937f9e5 1701 while (urb->actual_length > len_used) {
43a4478d 1702 struct net_device *netdev = tp->netdev;
05e0f1aa 1703 struct net_device_stats *stats = &netdev->stats;
7937f9e5 1704 unsigned int pkt_len;
43a4478d 1705 struct sk_buff *skb;
1706
7937f9e5 1707 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
ebc2ec48 1708 if (pkt_len < ETH_ZLEN)
1709 break;
1710
7937f9e5 1711 len_used += pkt_len;
1712 if (urb->actual_length < len_used)
1713 break;
1714
8e1f51bd 1715 pkt_len -= CRC_SIZE;
ebc2ec48 1716 rx_data += sizeof(struct rx_desc);
1717
1718 skb = netdev_alloc_skb_ip_align(netdev, pkt_len);
1719 if (!skb) {
1720 stats->rx_dropped++;
5e2f7485 1721 goto find_next_rx;
ebc2ec48 1722 }
565cab0a 1723
1724 skb->ip_summed = r8152_rx_csum(tp, rx_desc);
ebc2ec48 1725 memcpy(skb->data, rx_data, pkt_len);
1726 skb_put(skb, pkt_len);
1727 skb->protocol = eth_type_trans(skb, netdev);
c5554298 1728 rtl_rx_vlan_tag(rx_desc, skb);
9d9aafa1 1729 netif_receive_skb(skb);
ebc2ec48 1730 stats->rx_packets++;
1731 stats->rx_bytes += pkt_len;
1732
5e2f7485 1733find_next_rx:
8e1f51bd 1734 rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE);
ebc2ec48 1735 rx_desc = (struct rx_desc *)rx_data;
ebc2ec48 1736 len_used = (int)(rx_data - (u8 *)agg->head);
7937f9e5 1737 len_used += sizeof(struct rx_desc);
ebc2ec48 1738 }
1739
0de98f6c 1740submit:
ebc2ec48 1741 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
ebc2ec48 1742 if (ret && ret != -ENODEV) {
d84130a1 1743 spin_lock_irqsave(&tp->rx_lock, flags);
1744 list_add_tail(&agg->list, &tp->rx_done);
1745 spin_unlock_irqrestore(&tp->rx_lock, flags);
ebc2ec48 1746 tasklet_schedule(&tp->tl);
1747 }
1748 }
ebc2ec48 1749}
1750
1751static void tx_bottom(struct r8152 *tp)
1752{
ebc2ec48 1753 int res;
1754
b1379d9a 1755 do {
1756 struct tx_agg *agg;
ebc2ec48 1757
b1379d9a 1758 if (skb_queue_empty(&tp->tx_queue))
ebc2ec48 1759 break;
1760
b1379d9a 1761 agg = r8152_get_tx_agg(tp);
1762 if (!agg)
ebc2ec48 1763 break;
ebc2ec48 1764
b1379d9a 1765 res = r8152_tx_agg_fill(tp, agg);
1766 if (res) {
05e0f1aa 1767 struct net_device *netdev = tp->netdev;
ebc2ec48 1768
b1379d9a 1769 if (res == -ENODEV) {
67610496 1770 set_bit(RTL8152_UNPLUG, &tp->flags);
b1379d9a 1771 netif_device_detach(netdev);
1772 } else {
05e0f1aa 1773 struct net_device_stats *stats = &netdev->stats;
1774 unsigned long flags;
1775
b1379d9a 1776 netif_warn(tp, tx_err, netdev,
1777 "failed tx_urb %d\n", res);
1778 stats->tx_dropped += agg->skb_num;
db8515ef 1779
b1379d9a 1780 spin_lock_irqsave(&tp->tx_lock, flags);
1781 list_add_tail(&agg->list, &tp->tx_free);
1782 spin_unlock_irqrestore(&tp->tx_lock, flags);
1783 }
ebc2ec48 1784 }
b1379d9a 1785 } while (res == 0);
ebc2ec48 1786}
1787
1788static void bottom_half(unsigned long data)
ac718b69 1789{
1790 struct r8152 *tp;
ac718b69 1791
ebc2ec48 1792 tp = (struct r8152 *)data;
1793
1794 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1795 return;
1796
1797 if (!test_bit(WORK_ENABLE, &tp->flags))
ac718b69 1798 return;
ebc2ec48 1799
7559fb2f 1800 /* When link down, the driver would cancel all bulks. */
1801 /* This avoid the re-submitting bulk */
ebc2ec48 1802 if (!netif_carrier_ok(tp->netdev))
ac718b69 1803 return;
ebc2ec48 1804
1805 rx_bottom(tp);
0c3121fc 1806 tx_bottom(tp);
ebc2ec48 1807}
1808
1809static
1810int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
1811{
1812 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
52aec126 1813 agg->head, agg_buf_sz,
b209af99 1814 (usb_complete_t)read_bulk_callback, agg);
ebc2ec48 1815
1816 return usb_submit_urb(agg->urb, mem_flags);
ac718b69 1817}
1818
00a5e360 1819static void rtl_drop_queued_tx(struct r8152 *tp)
1820{
1821 struct net_device_stats *stats = &tp->netdev->stats;
d84130a1 1822 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
00a5e360 1823 struct sk_buff *skb;
1824
d84130a1 1825 if (skb_queue_empty(tx_queue))
1826 return;
1827
1828 __skb_queue_head_init(&skb_head);
2685d410 1829 spin_lock_bh(&tx_queue->lock);
d84130a1 1830 skb_queue_splice_init(tx_queue, &skb_head);
2685d410 1831 spin_unlock_bh(&tx_queue->lock);
d84130a1 1832
1833 while ((skb = __skb_dequeue(&skb_head))) {
00a5e360 1834 dev_kfree_skb(skb);
1835 stats->tx_dropped++;
1836 }
1837}
1838
ac718b69 1839static void rtl8152_tx_timeout(struct net_device *netdev)
1840{
1841 struct r8152 *tp = netdev_priv(netdev);
ebc2ec48 1842 int i;
1843
4a8deae2 1844 netif_warn(tp, tx_err, netdev, "Tx timeout\n");
ebc2ec48 1845 for (i = 0; i < RTL8152_MAX_TX; i++)
1846 usb_unlink_urb(tp->tx_info[i].urb);
ac718b69 1847}
1848
1849static void rtl8152_set_rx_mode(struct net_device *netdev)
1850{
1851 struct r8152 *tp = netdev_priv(netdev);
1852
40a82917 1853 if (tp->speed & LINK_STATUS) {
ac718b69 1854 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
40a82917 1855 schedule_delayed_work(&tp->schedule, 0);
1856 }
ac718b69 1857}
1858
1859static void _rtl8152_set_rx_mode(struct net_device *netdev)
1860{
1861 struct r8152 *tp = netdev_priv(netdev);
31787f53 1862 u32 mc_filter[2]; /* Multicast hash filter */
1863 __le32 tmp[2];
ac718b69 1864 u32 ocp_data;
1865
ac718b69 1866 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
1867 netif_stop_queue(netdev);
1868 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1869 ocp_data &= ~RCR_ACPT_ALL;
1870 ocp_data |= RCR_AB | RCR_APM;
1871
1872 if (netdev->flags & IFF_PROMISC) {
1873 /* Unconditionally log net taps. */
1874 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
1875 ocp_data |= RCR_AM | RCR_AAP;
b209af99 1876 mc_filter[1] = 0xffffffff;
1877 mc_filter[0] = 0xffffffff;
ac718b69 1878 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
1879 (netdev->flags & IFF_ALLMULTI)) {
1880 /* Too many to filter perfectly -- accept all multicasts. */
1881 ocp_data |= RCR_AM;
b209af99 1882 mc_filter[1] = 0xffffffff;
1883 mc_filter[0] = 0xffffffff;
ac718b69 1884 } else {
1885 struct netdev_hw_addr *ha;
1886
b209af99 1887 mc_filter[1] = 0;
1888 mc_filter[0] = 0;
ac718b69 1889 netdev_for_each_mc_addr(ha, netdev) {
1890 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
b209af99 1891
ac718b69 1892 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1893 ocp_data |= RCR_AM;
1894 }
1895 }
1896
31787f53 1897 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
1898 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
ac718b69 1899
31787f53 1900 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
ac718b69 1901 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1902 netif_wake_queue(netdev);
ac718b69 1903}
1904
1905static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
b209af99 1906 struct net_device *netdev)
ac718b69 1907{
1908 struct r8152 *tp = netdev_priv(netdev);
ac718b69 1909
ebc2ec48 1910 skb_tx_timestamp(skb);
ac718b69 1911
61598788 1912 skb_queue_tail(&tp->tx_queue, skb);
ebc2ec48 1913
0c3121fc 1914 if (!list_empty(&tp->tx_free)) {
1915 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
1916 set_bit(SCHEDULE_TASKLET, &tp->flags);
1917 schedule_delayed_work(&tp->schedule, 0);
1918 } else {
1919 usb_mark_last_busy(tp->udev);
1920 tasklet_schedule(&tp->tl);
1921 }
b209af99 1922 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
dd1b119c 1923 netif_stop_queue(netdev);
b209af99 1924 }
dd1b119c 1925
ac718b69 1926 return NETDEV_TX_OK;
1927}
1928
1929static void r8152b_reset_packet_filter(struct r8152 *tp)
1930{
1931 u32 ocp_data;
1932
1933 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
1934 ocp_data &= ~FMC_FCR_MCU_EN;
1935 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1936 ocp_data |= FMC_FCR_MCU_EN;
1937 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1938}
1939
1940static void rtl8152_nic_reset(struct r8152 *tp)
1941{
1942 int i;
1943
1944 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
1945
1946 for (i = 0; i < 1000; i++) {
1947 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
1948 break;
b209af99 1949 usleep_range(100, 400);
ac718b69 1950 }
1951}
1952
dd1b119c 1953static void set_tx_qlen(struct r8152 *tp)
1954{
1955 struct net_device *netdev = tp->netdev;
1956
52aec126 1957 tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN +
1958 sizeof(struct tx_desc));
dd1b119c 1959}
1960
ac718b69 1961static inline u8 rtl8152_get_speed(struct r8152 *tp)
1962{
1963 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
1964}
1965
507605a8 1966static void rtl_set_eee_plus(struct r8152 *tp)
ac718b69 1967{
ebc2ec48 1968 u32 ocp_data;
ac718b69 1969 u8 speed;
1970
1971 speed = rtl8152_get_speed(tp);
ebc2ec48 1972 if (speed & _10bps) {
ac718b69 1973 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
ebc2ec48 1974 ocp_data |= EEEP_CR_EEEP_TX;
ac718b69 1975 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
1976 } else {
1977 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
ebc2ec48 1978 ocp_data &= ~EEEP_CR_EEEP_TX;
ac718b69 1979 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
1980 }
507605a8 1981}
1982
00a5e360 1983static void rxdy_gated_en(struct r8152 *tp, bool enable)
1984{
1985 u32 ocp_data;
1986
1987 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
1988 if (enable)
1989 ocp_data |= RXDY_GATED_EN;
1990 else
1991 ocp_data &= ~RXDY_GATED_EN;
1992 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
1993}
1994
445f7f4d 1995static int rtl_start_rx(struct r8152 *tp)
1996{
1997 int i, ret = 0;
1998
1999 INIT_LIST_HEAD(&tp->rx_done);
2000 for (i = 0; i < RTL8152_MAX_RX; i++) {
2001 INIT_LIST_HEAD(&tp->rx_info[i].list);
2002 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
2003 if (ret)
2004 break;
2005 }
2006
2007 return ret;
2008}
2009
2010static int rtl_stop_rx(struct r8152 *tp)
2011{
2012 int i;
2013
2014 for (i = 0; i < RTL8152_MAX_RX; i++)
2015 usb_kill_urb(tp->rx_info[i].urb);
2016
2017 return 0;
2018}
2019
507605a8 2020static int rtl_enable(struct r8152 *tp)
2021{
2022 u32 ocp_data;
ac718b69 2023
2024 r8152b_reset_packet_filter(tp);
2025
2026 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2027 ocp_data |= CR_RE | CR_TE;
2028 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2029
00a5e360 2030 rxdy_gated_en(tp, false);
ac718b69 2031
445f7f4d 2032 return rtl_start_rx(tp);
ac718b69 2033}
2034
507605a8 2035static int rtl8152_enable(struct r8152 *tp)
2036{
6871438c 2037 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2038 return -ENODEV;
2039
507605a8 2040 set_tx_qlen(tp);
2041 rtl_set_eee_plus(tp);
2042
2043 return rtl_enable(tp);
2044}
2045
43779f8d 2046static void r8153_set_rx_agg(struct r8152 *tp)
2047{
2048 u8 speed;
2049
2050 speed = rtl8152_get_speed(tp);
2051 if (speed & _1000bps) {
2052 if (tp->udev->speed == USB_SPEED_SUPER) {
2053 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
2054 RX_THR_SUPPER);
2055 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2056 EARLY_AGG_SUPPER);
2057 } else {
2058 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
2059 RX_THR_HIGH);
2060 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2061 EARLY_AGG_HIGH);
2062 }
2063 } else {
2064 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_SLOW);
2065 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2066 EARLY_AGG_SLOW);
2067 }
2068}
2069
2070static int rtl8153_enable(struct r8152 *tp)
2071{
6871438c 2072 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2073 return -ENODEV;
2074
43779f8d 2075 set_tx_qlen(tp);
2076 rtl_set_eee_plus(tp);
2077 r8153_set_rx_agg(tp);
2078
2079 return rtl_enable(tp);
2080}
2081
d70b1137 2082static void rtl_disable(struct r8152 *tp)
ac718b69 2083{
ebc2ec48 2084 u32 ocp_data;
2085 int i;
ac718b69 2086
6871438c 2087 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2088 rtl_drop_queued_tx(tp);
2089 return;
2090 }
2091
ac718b69 2092 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2093 ocp_data &= ~RCR_ACPT_ALL;
2094 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2095
00a5e360 2096 rtl_drop_queued_tx(tp);
ebc2ec48 2097
2098 for (i = 0; i < RTL8152_MAX_TX; i++)
2099 usb_kill_urb(tp->tx_info[i].urb);
ac718b69 2100
00a5e360 2101 rxdy_gated_en(tp, true);
ac718b69 2102
2103 for (i = 0; i < 1000; i++) {
2104 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2105 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2106 break;
8ddfa077 2107 usleep_range(1000, 2000);
ac718b69 2108 }
2109
2110 for (i = 0; i < 1000; i++) {
2111 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2112 break;
8ddfa077 2113 usleep_range(1000, 2000);
ac718b69 2114 }
2115
445f7f4d 2116 rtl_stop_rx(tp);
ac718b69 2117
2118 rtl8152_nic_reset(tp);
2119}
2120
00a5e360 2121static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2122{
2123 u32 ocp_data;
2124
2125 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2126 if (enable)
2127 ocp_data |= POWER_CUT;
2128 else
2129 ocp_data &= ~POWER_CUT;
2130 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2131
2132 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2133 ocp_data &= ~RESUME_INDICATE;
2134 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
00a5e360 2135}
2136
c5554298 2137static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2138{
2139 u32 ocp_data;
2140
2141 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2142 if (enable)
2143 ocp_data |= CPCR_RX_VLAN;
2144 else
2145 ocp_data &= ~CPCR_RX_VLAN;
2146 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2147}
2148
2149static int rtl8152_set_features(struct net_device *dev,
2150 netdev_features_t features)
2151{
2152 netdev_features_t changed = features ^ dev->features;
2153 struct r8152 *tp = netdev_priv(dev);
405f8a0e 2154 int ret;
2155
2156 ret = usb_autopm_get_interface(tp->intf);
2157 if (ret < 0)
2158 goto out;
c5554298 2159
b5403273 2160 mutex_lock(&tp->control);
2161
c5554298 2162 if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2163 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2164 rtl_rx_vlan_en(tp, true);
2165 else
2166 rtl_rx_vlan_en(tp, false);
2167 }
2168
b5403273 2169 mutex_unlock(&tp->control);
2170
405f8a0e 2171 usb_autopm_put_interface(tp->intf);
2172
2173out:
2174 return ret;
c5554298 2175}
2176
21ff2e89 2177#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2178
2179static u32 __rtl_get_wol(struct r8152 *tp)
2180{
2181 u32 ocp_data;
2182 u32 wolopts = 0;
2183
2184 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2185 if (!(ocp_data & LAN_WAKE_EN))
2186 return 0;
2187
2188 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2189 if (ocp_data & LINK_ON_WAKE_EN)
2190 wolopts |= WAKE_PHY;
2191
2192 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2193 if (ocp_data & UWF_EN)
2194 wolopts |= WAKE_UCAST;
2195 if (ocp_data & BWF_EN)
2196 wolopts |= WAKE_BCAST;
2197 if (ocp_data & MWF_EN)
2198 wolopts |= WAKE_MCAST;
2199
2200 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2201 if (ocp_data & MAGIC_EN)
2202 wolopts |= WAKE_MAGIC;
2203
2204 return wolopts;
2205}
2206
2207static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2208{
2209 u32 ocp_data;
2210
2211 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2212
2213 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2214 ocp_data &= ~LINK_ON_WAKE_EN;
2215 if (wolopts & WAKE_PHY)
2216 ocp_data |= LINK_ON_WAKE_EN;
2217 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2218
2219 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2220 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN);
2221 if (wolopts & WAKE_UCAST)
2222 ocp_data |= UWF_EN;
2223 if (wolopts & WAKE_BCAST)
2224 ocp_data |= BWF_EN;
2225 if (wolopts & WAKE_MCAST)
2226 ocp_data |= MWF_EN;
2227 if (wolopts & WAKE_ANY)
2228 ocp_data |= LAN_WAKE_EN;
2229 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
2230
2231 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2232
2233 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2234 ocp_data &= ~MAGIC_EN;
2235 if (wolopts & WAKE_MAGIC)
2236 ocp_data |= MAGIC_EN;
2237 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
2238
2239 if (wolopts & WAKE_ANY)
2240 device_set_wakeup_enable(&tp->udev->dev, true);
2241 else
2242 device_set_wakeup_enable(&tp->udev->dev, false);
2243}
2244
9a4be1bd 2245static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
2246{
2247 if (enable) {
2248 u32 ocp_data;
2249
2250 __rtl_set_wol(tp, WAKE_ANY);
2251
2252 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2253
2254 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2255 ocp_data |= LINK_OFF_WAKE_EN;
2256 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2257
2258 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2259 } else {
2260 __rtl_set_wol(tp, tp->saved_wolopts);
2261 }
2262}
2263
aa66a5f1 2264static void rtl_phy_reset(struct r8152 *tp)
2265{
2266 u16 data;
2267 int i;
2268
2269 clear_bit(PHY_RESET, &tp->flags);
2270
2271 data = r8152_mdio_read(tp, MII_BMCR);
2272
2273 /* don't reset again before the previous one complete */
2274 if (data & BMCR_RESET)
2275 return;
2276
2277 data |= BMCR_RESET;
2278 r8152_mdio_write(tp, MII_BMCR, data);
2279
2280 for (i = 0; i < 50; i++) {
2281 msleep(20);
2282 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2283 break;
2284 }
2285}
2286
4349968a 2287static void r8153_teredo_off(struct r8152 *tp)
2288{
2289 u32 ocp_data;
2290
2291 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2292 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN);
2293 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2294
2295 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
2296 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
2297 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
2298}
2299
2300static void r8152b_disable_aldps(struct r8152 *tp)
2301{
2302 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
2303 msleep(20);
2304}
2305
2306static inline void r8152b_enable_aldps(struct r8152 *tp)
2307{
2308 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
2309 LINKENA | DIS_SDSAVE);
2310}
2311
d70b1137 2312static void rtl8152_disable(struct r8152 *tp)
2313{
2314 r8152b_disable_aldps(tp);
2315 rtl_disable(tp);
2316 r8152b_enable_aldps(tp);
2317}
2318
4349968a 2319static void r8152b_hw_phy_cfg(struct r8152 *tp)
2320{
f0cbe0ac 2321 u16 data;
2322
2323 data = r8152_mdio_read(tp, MII_BMCR);
2324 if (data & BMCR_PDOWN) {
2325 data &= ~BMCR_PDOWN;
2326 r8152_mdio_write(tp, MII_BMCR, data);
2327 }
2328
aa66a5f1 2329 set_bit(PHY_RESET, &tp->flags);
4349968a 2330}
2331
ac718b69 2332static void r8152b_exit_oob(struct r8152 *tp)
2333{
db8515ef 2334 u32 ocp_data;
2335 int i;
ac718b69 2336
2337 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2338 ocp_data &= ~RCR_ACPT_ALL;
2339 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2340
00a5e360 2341 rxdy_gated_en(tp, true);
da9bd117 2342 r8153_teredo_off(tp);
7e9da481 2343 r8152b_hw_phy_cfg(tp);
ac718b69 2344
2345 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2346 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
2347
2348 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2349 ocp_data &= ~NOW_IS_OOB;
2350 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2351
2352 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2353 ocp_data &= ~MCU_BORW_EN;
2354 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2355
2356 for (i = 0; i < 1000; i++) {
2357 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2358 if (ocp_data & LINK_LIST_READY)
2359 break;
8ddfa077 2360 usleep_range(1000, 2000);
ac718b69 2361 }
2362
2363 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2364 ocp_data |= RE_INIT_LL;
2365 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2366
2367 for (i = 0; i < 1000; i++) {
2368 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2369 if (ocp_data & LINK_LIST_READY)
2370 break;
8ddfa077 2371 usleep_range(1000, 2000);
ac718b69 2372 }
2373
2374 rtl8152_nic_reset(tp);
2375
2376 /* rx share fifo credit full threshold */
2377 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2378
a3cc465d 2379 if (tp->udev->speed == USB_SPEED_FULL ||
2380 tp->udev->speed == USB_SPEED_LOW) {
ac718b69 2381 /* rx share fifo credit near full threshold */
2382 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2383 RXFIFO_THR2_FULL);
2384 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2385 RXFIFO_THR3_FULL);
2386 } else {
2387 /* rx share fifo credit near full threshold */
2388 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2389 RXFIFO_THR2_HIGH);
2390 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2391 RXFIFO_THR3_HIGH);
2392 }
2393
2394 /* TX share fifo free credit full threshold */
2395 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
2396
2397 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
8e1f51bd 2398 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
ac718b69 2399 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
2400 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
2401
c5554298 2402 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
ac718b69 2403
2404 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2405
2406 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2407 ocp_data |= TCR0_AUTO_FIFO;
2408 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2409}
2410
2411static void r8152b_enter_oob(struct r8152 *tp)
2412{
45f4a19f 2413 u32 ocp_data;
2414 int i;
ac718b69 2415
2416 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2417 ocp_data &= ~NOW_IS_OOB;
2418 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2419
2420 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
2421 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
2422 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
2423
d70b1137 2424 rtl_disable(tp);
ac718b69 2425
2426 for (i = 0; i < 1000; i++) {
2427 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2428 if (ocp_data & LINK_LIST_READY)
2429 break;
8ddfa077 2430 usleep_range(1000, 2000);
ac718b69 2431 }
2432
2433 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2434 ocp_data |= RE_INIT_LL;
2435 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2436
2437 for (i = 0; i < 1000; i++) {
2438 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2439 if (ocp_data & LINK_LIST_READY)
2440 break;
8ddfa077 2441 usleep_range(1000, 2000);
ac718b69 2442 }
2443
2444 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2445
c5554298 2446 rtl_rx_vlan_en(tp, true);
ac718b69 2447
2448 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2449 ocp_data |= ALDPS_PROXY_MODE;
2450 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2451
2452 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2453 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2454 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2455
00a5e360 2456 rxdy_gated_en(tp, false);
ac718b69 2457
2458 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2459 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2460 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2461}
2462
43779f8d 2463static void r8153_hw_phy_cfg(struct r8152 *tp)
2464{
2465 u32 ocp_data;
2466 u16 data;
2467
2468 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
f0cbe0ac 2469 data = r8152_mdio_read(tp, MII_BMCR);
2470 if (data & BMCR_PDOWN) {
2471 data &= ~BMCR_PDOWN;
2472 r8152_mdio_write(tp, MII_BMCR, data);
2473 }
43779f8d 2474
2475 if (tp->version == RTL_VER_03) {
2476 data = ocp_reg_read(tp, OCP_EEE_CFG);
2477 data &= ~CTAP_SHORT_EN;
2478 ocp_reg_write(tp, OCP_EEE_CFG, data);
2479 }
2480
2481 data = ocp_reg_read(tp, OCP_POWER_CFG);
2482 data |= EEE_CLKDIV_EN;
2483 ocp_reg_write(tp, OCP_POWER_CFG, data);
2484
2485 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
2486 data |= EN_10M_BGOFF;
2487 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
2488 data = ocp_reg_read(tp, OCP_POWER_CFG);
2489 data |= EN_10M_PLLOFF;
2490 ocp_reg_write(tp, OCP_POWER_CFG, data);
2491 data = sram_read(tp, SRAM_IMPEDANCE);
2492 data &= ~RX_DRIVING_MASK;
2493 sram_write(tp, SRAM_IMPEDANCE, data);
2494
2495 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
2496 ocp_data |= PFM_PWM_SWITCH;
2497 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
2498
2499 data = sram_read(tp, SRAM_LPF_CFG);
2500 data |= LPF_AUTO_TUNE;
2501 sram_write(tp, SRAM_LPF_CFG, data);
2502
2503 data = sram_read(tp, SRAM_10M_AMP1);
2504 data |= GDAC_IB_UPALL;
2505 sram_write(tp, SRAM_10M_AMP1, data);
2506 data = sram_read(tp, SRAM_10M_AMP2);
2507 data |= AMP_DN;
2508 sram_write(tp, SRAM_10M_AMP2, data);
aa66a5f1 2509
2510 set_bit(PHY_RESET, &tp->flags);
43779f8d 2511}
2512
b9702723 2513static void r8153_u1u2en(struct r8152 *tp, bool enable)
43779f8d 2514{
2515 u8 u1u2[8];
2516
2517 if (enable)
2518 memset(u1u2, 0xff, sizeof(u1u2));
2519 else
2520 memset(u1u2, 0x00, sizeof(u1u2));
2521
2522 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
2523}
2524
b9702723 2525static void r8153_u2p3en(struct r8152 *tp, bool enable)
43779f8d 2526{
2527 u32 ocp_data;
2528
2529 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
2530 if (enable)
2531 ocp_data |= U2P3_ENABLE;
2532 else
2533 ocp_data &= ~U2P3_ENABLE;
2534 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
2535}
2536
b9702723 2537static void r8153_power_cut_en(struct r8152 *tp, bool enable)
43779f8d 2538{
2539 u32 ocp_data;
2540
2541 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2542 if (enable)
2543 ocp_data |= PWR_EN | PHASE2_EN;
2544 else
2545 ocp_data &= ~(PWR_EN | PHASE2_EN);
2546 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2547
2548 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2549 ocp_data &= ~PCUT_STATUS;
2550 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2551}
2552
43779f8d 2553static void r8153_first_init(struct r8152 *tp)
2554{
2555 u32 ocp_data;
2556 int i;
2557
00a5e360 2558 rxdy_gated_en(tp, true);
43779f8d 2559 r8153_teredo_off(tp);
2560
2561 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2562 ocp_data &= ~RCR_ACPT_ALL;
2563 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2564
2565 r8153_hw_phy_cfg(tp);
2566
2567 rtl8152_nic_reset(tp);
2568
2569 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2570 ocp_data &= ~NOW_IS_OOB;
2571 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2572
2573 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2574 ocp_data &= ~MCU_BORW_EN;
2575 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2576
2577 for (i = 0; i < 1000; i++) {
2578 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2579 if (ocp_data & LINK_LIST_READY)
2580 break;
8ddfa077 2581 usleep_range(1000, 2000);
43779f8d 2582 }
2583
2584 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2585 ocp_data |= RE_INIT_LL;
2586 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2587
2588 for (i = 0; i < 1000; i++) {
2589 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2590 if (ocp_data & LINK_LIST_READY)
2591 break;
8ddfa077 2592 usleep_range(1000, 2000);
43779f8d 2593 }
2594
c5554298 2595 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
43779f8d 2596
69b4b7a4 2597 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
2598 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
43779f8d 2599
2600 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2601 ocp_data |= TCR0_AUTO_FIFO;
2602 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2603
2604 rtl8152_nic_reset(tp);
2605
2606 /* rx share fifo credit full threshold */
2607 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2608 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
2609 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
2610 /* TX share fifo free credit full threshold */
2611 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
2612
9629e3c0 2613 /* rx aggregation */
43779f8d 2614 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2615 ocp_data &= ~RX_AGG_DISABLE;
2616 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2617}
2618
2619static void r8153_enter_oob(struct r8152 *tp)
2620{
2621 u32 ocp_data;
2622 int i;
2623
2624 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2625 ocp_data &= ~NOW_IS_OOB;
2626 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2627
d70b1137 2628 rtl_disable(tp);
43779f8d 2629
2630 for (i = 0; i < 1000; i++) {
2631 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2632 if (ocp_data & LINK_LIST_READY)
2633 break;
8ddfa077 2634 usleep_range(1000, 2000);
43779f8d 2635 }
2636
2637 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2638 ocp_data |= RE_INIT_LL;
2639 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2640
2641 for (i = 0; i < 1000; i++) {
2642 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2643 if (ocp_data & LINK_LIST_READY)
2644 break;
8ddfa077 2645 usleep_range(1000, 2000);
43779f8d 2646 }
2647
69b4b7a4 2648 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
43779f8d 2649
43779f8d 2650 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2651 ocp_data &= ~TEREDO_WAKE_MASK;
2652 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2653
c5554298 2654 rtl_rx_vlan_en(tp, true);
43779f8d 2655
2656 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2657 ocp_data |= ALDPS_PROXY_MODE;
2658 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2659
2660 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2661 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2662 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2663
00a5e360 2664 rxdy_gated_en(tp, false);
43779f8d 2665
2666 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2667 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2668 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2669}
2670
2671static void r8153_disable_aldps(struct r8152 *tp)
2672{
2673 u16 data;
2674
2675 data = ocp_reg_read(tp, OCP_POWER_CFG);
2676 data &= ~EN_ALDPS;
2677 ocp_reg_write(tp, OCP_POWER_CFG, data);
2678 msleep(20);
2679}
2680
2681static void r8153_enable_aldps(struct r8152 *tp)
2682{
2683 u16 data;
2684
2685 data = ocp_reg_read(tp, OCP_POWER_CFG);
2686 data |= EN_ALDPS;
2687 ocp_reg_write(tp, OCP_POWER_CFG, data);
2688}
2689
d70b1137 2690static void rtl8153_disable(struct r8152 *tp)
2691{
2692 r8153_disable_aldps(tp);
2693 rtl_disable(tp);
2694 r8153_enable_aldps(tp);
2695}
2696
ac718b69 2697static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
2698{
43779f8d 2699 u16 bmcr, anar, gbcr;
ac718b69 2700 int ret = 0;
2701
2702 cancel_delayed_work_sync(&tp->schedule);
2703 anar = r8152_mdio_read(tp, MII_ADVERTISE);
2704 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
2705 ADVERTISE_100HALF | ADVERTISE_100FULL);
43779f8d 2706 if (tp->mii.supports_gmii) {
2707 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
2708 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
2709 } else {
2710 gbcr = 0;
2711 }
ac718b69 2712
2713 if (autoneg == AUTONEG_DISABLE) {
2714 if (speed == SPEED_10) {
2715 bmcr = 0;
2716 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2717 } else if (speed == SPEED_100) {
2718 bmcr = BMCR_SPEED100;
2719 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
43779f8d 2720 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2721 bmcr = BMCR_SPEED1000;
2722 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
ac718b69 2723 } else {
2724 ret = -EINVAL;
2725 goto out;
2726 }
2727
2728 if (duplex == DUPLEX_FULL)
2729 bmcr |= BMCR_FULLDPLX;
2730 } else {
2731 if (speed == SPEED_10) {
2732 if (duplex == DUPLEX_FULL)
2733 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2734 else
2735 anar |= ADVERTISE_10HALF;
2736 } else if (speed == SPEED_100) {
2737 if (duplex == DUPLEX_FULL) {
2738 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2739 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2740 } else {
2741 anar |= ADVERTISE_10HALF;
2742 anar |= ADVERTISE_100HALF;
2743 }
43779f8d 2744 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2745 if (duplex == DUPLEX_FULL) {
2746 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2747 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2748 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2749 } else {
2750 anar |= ADVERTISE_10HALF;
2751 anar |= ADVERTISE_100HALF;
2752 gbcr |= ADVERTISE_1000HALF;
2753 }
ac718b69 2754 } else {
2755 ret = -EINVAL;
2756 goto out;
2757 }
2758
2759 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
2760 }
2761
aa66a5f1 2762 if (test_bit(PHY_RESET, &tp->flags))
2763 bmcr |= BMCR_RESET;
2764
43779f8d 2765 if (tp->mii.supports_gmii)
2766 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
2767
ac718b69 2768 r8152_mdio_write(tp, MII_ADVERTISE, anar);
2769 r8152_mdio_write(tp, MII_BMCR, bmcr);
2770
aa66a5f1 2771 if (test_bit(PHY_RESET, &tp->flags)) {
2772 int i;
2773
2774 clear_bit(PHY_RESET, &tp->flags);
2775 for (i = 0; i < 50; i++) {
2776 msleep(20);
2777 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2778 break;
2779 }
2780 }
2781
ac718b69 2782out:
ac718b69 2783
2784 return ret;
2785}
2786
d70b1137 2787static void rtl8152_up(struct r8152 *tp)
2788{
2789 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2790 return;
2791
2792 r8152b_disable_aldps(tp);
2793 r8152b_exit_oob(tp);
2794 r8152b_enable_aldps(tp);
2795}
2796
ac718b69 2797static void rtl8152_down(struct r8152 *tp)
2798{
6871438c 2799 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2800 rtl_drop_queued_tx(tp);
2801 return;
2802 }
2803
00a5e360 2804 r8152_power_cut_en(tp, false);
ac718b69 2805 r8152b_disable_aldps(tp);
2806 r8152b_enter_oob(tp);
2807 r8152b_enable_aldps(tp);
2808}
2809
d70b1137 2810static void rtl8153_up(struct r8152 *tp)
2811{
2812 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2813 return;
2814
2815 r8153_disable_aldps(tp);
2816 r8153_first_init(tp);
2817 r8153_enable_aldps(tp);
2818}
2819
43779f8d 2820static void rtl8153_down(struct r8152 *tp)
2821{
6871438c 2822 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2823 rtl_drop_queued_tx(tp);
2824 return;
2825 }
2826
b9702723 2827 r8153_u1u2en(tp, false);
2828 r8153_power_cut_en(tp, false);
43779f8d 2829 r8153_disable_aldps(tp);
2830 r8153_enter_oob(tp);
2831 r8153_enable_aldps(tp);
2832}
2833
ac718b69 2834static void set_carrier(struct r8152 *tp)
2835{
2836 struct net_device *netdev = tp->netdev;
2837 u8 speed;
2838
40a82917 2839 clear_bit(RTL8152_LINK_CHG, &tp->flags);
ac718b69 2840 speed = rtl8152_get_speed(tp);
2841
2842 if (speed & LINK_STATUS) {
2843 if (!(tp->speed & LINK_STATUS)) {
c81229c9 2844 tp->rtl_ops.enable(tp);
ac718b69 2845 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2846 netif_carrier_on(netdev);
2847 }
2848 } else {
2849 if (tp->speed & LINK_STATUS) {
2850 netif_carrier_off(netdev);
ebc2ec48 2851 tasklet_disable(&tp->tl);
c81229c9 2852 tp->rtl_ops.disable(tp);
ebc2ec48 2853 tasklet_enable(&tp->tl);
ac718b69 2854 }
2855 }
2856 tp->speed = speed;
2857}
2858
2859static void rtl_work_func_t(struct work_struct *work)
2860{
2861 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
2862
9a4be1bd 2863 if (usb_autopm_get_interface(tp->intf) < 0)
2864 return;
2865
ac718b69 2866 if (!test_bit(WORK_ENABLE, &tp->flags))
2867 goto out1;
2868
2869 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2870 goto out1;
2871
b5403273 2872 if (!mutex_trylock(&tp->control)) {
2873 schedule_delayed_work(&tp->schedule, 0);
2874 goto out1;
2875 }
2876
40a82917 2877 if (test_bit(RTL8152_LINK_CHG, &tp->flags))
2878 set_carrier(tp);
ac718b69 2879
2880 if (test_bit(RTL8152_SET_RX_MODE, &tp->flags))
2881 _rtl8152_set_rx_mode(tp->netdev);
2882
0c3121fc 2883 if (test_bit(SCHEDULE_TASKLET, &tp->flags) &&
2884 (tp->speed & LINK_STATUS)) {
2885 clear_bit(SCHEDULE_TASKLET, &tp->flags);
2886 tasklet_schedule(&tp->tl);
2887 }
aa66a5f1 2888
2889 if (test_bit(PHY_RESET, &tp->flags))
2890 rtl_phy_reset(tp);
2891
b5403273 2892 mutex_unlock(&tp->control);
2893
ac718b69 2894out1:
9a4be1bd 2895 usb_autopm_put_interface(tp->intf);
ac718b69 2896}
2897
2898static int rtl8152_open(struct net_device *netdev)
2899{
2900 struct r8152 *tp = netdev_priv(netdev);
2901 int res = 0;
2902
7e9da481 2903 res = alloc_all_mem(tp);
2904 if (res)
2905 goto out;
2906
f4c7476b 2907 /* set speed to 0 to avoid autoresume try to submit rx */
2908 tp->speed = 0;
2909
9a4be1bd 2910 res = usb_autopm_get_interface(tp->intf);
2911 if (res < 0) {
2912 free_all_mem(tp);
2913 goto out;
2914 }
2915
b5403273 2916 mutex_lock(&tp->control);
2917
9a4be1bd 2918 /* The WORK_ENABLE may be set when autoresume occurs */
2919 if (test_bit(WORK_ENABLE, &tp->flags)) {
2920 clear_bit(WORK_ENABLE, &tp->flags);
2921 usb_kill_urb(tp->intr_urb);
2922 cancel_delayed_work_sync(&tp->schedule);
f4c7476b 2923
2924 /* disable the tx/rx, if the workqueue has enabled them. */
9a4be1bd 2925 if (tp->speed & LINK_STATUS)
2926 tp->rtl_ops.disable(tp);
2927 }
2928
7e9da481 2929 tp->rtl_ops.up(tp);
2930
3d55f44f 2931 rtl8152_set_speed(tp, AUTONEG_ENABLE,
2932 tp->mii.supports_gmii ? SPEED_1000 : SPEED_100,
2933 DUPLEX_FULL);
2934 tp->speed = 0;
2935 netif_carrier_off(netdev);
2936 netif_start_queue(netdev);
2937 set_bit(WORK_ENABLE, &tp->flags);
db8515ef 2938
40a82917 2939 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
2940 if (res) {
2941 if (res == -ENODEV)
2942 netif_device_detach(tp->netdev);
4a8deae2
HW
2943 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
2944 res);
7e9da481 2945 free_all_mem(tp);
93ffbeab 2946 } else {
2947 tasklet_enable(&tp->tl);
ac718b69 2948 }
2949
b5403273 2950 mutex_unlock(&tp->control);
2951
9a4be1bd 2952 usb_autopm_put_interface(tp->intf);
ac718b69 2953
7e9da481 2954out:
ac718b69 2955 return res;
2956}
2957
2958static int rtl8152_close(struct net_device *netdev)
2959{
2960 struct r8152 *tp = netdev_priv(netdev);
2961 int res = 0;
2962
93ffbeab 2963 tasklet_disable(&tp->tl);
ac718b69 2964 clear_bit(WORK_ENABLE, &tp->flags);
3d55f44f 2965 usb_kill_urb(tp->intr_urb);
ac718b69 2966 cancel_delayed_work_sync(&tp->schedule);
2967 netif_stop_queue(netdev);
9a4be1bd 2968
2969 res = usb_autopm_get_interface(tp->intf);
2970 if (res < 0) {
2971 rtl_drop_queued_tx(tp);
2972 } else {
b5403273 2973 mutex_lock(&tp->control);
2974
b209af99 2975 /* The autosuspend may have been enabled and wouldn't
9a4be1bd 2976 * be disable when autoresume occurs, because the
2977 * netif_running() would be false.
2978 */
923e1ee3 2979 rtl_runtime_suspend_enable(tp, false);
9a4be1bd 2980
9a4be1bd 2981 tp->rtl_ops.down(tp);
b5403273 2982
2983 mutex_unlock(&tp->control);
2984
9a4be1bd 2985 usb_autopm_put_interface(tp->intf);
2986 }
ac718b69 2987
7e9da481 2988 free_all_mem(tp);
2989
ac718b69 2990 return res;
2991}
2992
d24f6134 2993static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
2994{
2995 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
2996 ocp_reg_write(tp, OCP_EEE_DATA, reg);
2997 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
2998}
2999
3000static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
3001{
3002 u16 data;
3003
3004 r8152_mmd_indirect(tp, dev, reg);
3005 data = ocp_reg_read(tp, OCP_EEE_DATA);
3006 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
3007
3008 return data;
3009}
3010
3011static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
ac718b69 3012{
d24f6134 3013 r8152_mmd_indirect(tp, dev, reg);
3014 ocp_reg_write(tp, OCP_EEE_DATA, data);
3015 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
3016}
3017
3018static void r8152_eee_en(struct r8152 *tp, bool enable)
3019{
3020 u16 config1, config2, config3;
45f4a19f 3021 u32 ocp_data;
ac718b69 3022
3023 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
d24f6134 3024 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
3025 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
3026 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
3027
3028 if (enable) {
3029 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3030 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
3031 config1 |= sd_rise_time(1);
3032 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
3033 config3 |= fast_snr(42);
3034 } else {
3035 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3036 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
3037 RX_QUIET_EN);
3038 config1 |= sd_rise_time(7);
3039 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
3040 config3 |= fast_snr(511);
3041 }
3042
ac718b69 3043 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
d24f6134 3044 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
3045 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
3046 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
ac718b69 3047}
3048
d24f6134 3049static void r8152b_enable_eee(struct r8152 *tp)
3050{
3051 r8152_eee_en(tp, true);
3052 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
3053}
3054
3055static void r8153_eee_en(struct r8152 *tp, bool enable)
43779f8d 3056{
3057 u32 ocp_data;
d24f6134 3058 u16 config;
43779f8d 3059
3060 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
d24f6134 3061 config = ocp_reg_read(tp, OCP_EEE_CFG);
3062
3063 if (enable) {
3064 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3065 config |= EEE10_EN;
3066 } else {
3067 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3068 config &= ~EEE10_EN;
3069 }
3070
43779f8d 3071 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
d24f6134 3072 ocp_reg_write(tp, OCP_EEE_CFG, config);
3073}
3074
3075static void r8153_enable_eee(struct r8152 *tp)
3076{
3077 r8153_eee_en(tp, true);
3078 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
43779f8d 3079}
3080
ac718b69 3081static void r8152b_enable_fc(struct r8152 *tp)
3082{
3083 u16 anar;
3084
3085 anar = r8152_mdio_read(tp, MII_ADVERTISE);
3086 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3087 r8152_mdio_write(tp, MII_ADVERTISE, anar);
3088}
3089
4f1d4d54 3090static void rtl_tally_reset(struct r8152 *tp)
3091{
3092 u32 ocp_data;
3093
3094 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
3095 ocp_data |= TALLY_RESET;
3096 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
3097}
3098
ac718b69 3099static void r8152b_init(struct r8152 *tp)
3100{
ebc2ec48 3101 u32 ocp_data;
ac718b69 3102
6871438c 3103 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3104 return;
3105
d70b1137 3106 r8152b_disable_aldps(tp);
3107
ac718b69 3108 if (tp->version == RTL_VER_01) {
3109 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3110 ocp_data &= ~LED_MODE_MASK;
3111 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3112 }
3113
00a5e360 3114 r8152_power_cut_en(tp, false);
ac718b69 3115
ac718b69 3116 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3117 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
3118 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3119 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
3120 ocp_data &= ~MCU_CLK_RATIO_MASK;
3121 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
3122 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
3123 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
3124 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
3125 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
3126
3127 r8152b_enable_eee(tp);
3128 r8152b_enable_aldps(tp);
3129 r8152b_enable_fc(tp);
4f1d4d54 3130 rtl_tally_reset(tp);
ac718b69 3131
ebc2ec48 3132 /* enable rx aggregation */
ac718b69 3133 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
ebc2ec48 3134 ocp_data &= ~RX_AGG_DISABLE;
ac718b69 3135 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
3136}
3137
43779f8d 3138static void r8153_init(struct r8152 *tp)
3139{
3140 u32 ocp_data;
3141 int i;
3142
6871438c 3143 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3144 return;
3145
d70b1137 3146 r8153_disable_aldps(tp);
b9702723 3147 r8153_u1u2en(tp, false);
43779f8d 3148
3149 for (i = 0; i < 500; i++) {
3150 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3151 AUTOLOAD_DONE)
3152 break;
3153 msleep(20);
3154 }
3155
3156 for (i = 0; i < 500; i++) {
3157 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
3158 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
3159 break;
3160 msleep(20);
3161 }
3162
b9702723 3163 r8153_u2p3en(tp, false);
43779f8d 3164
3165 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
3166 ocp_data &= ~TIMER11_EN;
3167 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
3168
43779f8d 3169 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3170 ocp_data &= ~LED_MODE_MASK;
3171 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3172
3173 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL);
3174 ocp_data &= ~LPM_TIMER_MASK;
3175 if (tp->udev->speed == USB_SPEED_SUPER)
3176 ocp_data |= LPM_TIMER_500US;
3177 else
3178 ocp_data |= LPM_TIMER_500MS;
3179 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
3180
3181 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
3182 ocp_data &= ~SEN_VAL_MASK;
3183 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
3184 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
3185
b9702723 3186 r8153_power_cut_en(tp, false);
3187 r8153_u1u2en(tp, true);
43779f8d 3188
43779f8d 3189 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO);
3190 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO);
3191 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
3192 PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
3193 U1U2_SPDWN_EN | L1_SPDWN_EN);
3194 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
3195 PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
3196 TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN |
3197 EEE_SPDWN_EN);
3198
3199 r8153_enable_eee(tp);
3200 r8153_enable_aldps(tp);
3201 r8152b_enable_fc(tp);
4f1d4d54 3202 rtl_tally_reset(tp);
43779f8d 3203}
3204
ac718b69 3205static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
3206{
3207 struct r8152 *tp = usb_get_intfdata(intf);
6cc69f2a 3208 struct net_device *netdev = tp->netdev;
3209 int ret = 0;
ac718b69 3210
b5403273 3211 mutex_lock(&tp->control);
3212
6cc69f2a 3213 if (PMSG_IS_AUTO(message)) {
3214 if (netif_running(netdev) && work_busy(&tp->schedule.work)) {
3215 ret = -EBUSY;
3216 goto out1;
3217 }
3218
9a4be1bd 3219 set_bit(SELECTIVE_SUSPEND, &tp->flags);
6cc69f2a 3220 } else {
3221 netif_device_detach(netdev);
3222 }
ac718b69 3223
e3bd1a81 3224 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
ac718b69 3225 clear_bit(WORK_ENABLE, &tp->flags);
40a82917 3226 usb_kill_urb(tp->intr_urb);
445f7f4d 3227 tasklet_disable(&tp->tl);
9a4be1bd 3228 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
445f7f4d 3229 rtl_stop_rx(tp);
9a4be1bd 3230 rtl_runtime_suspend_enable(tp, true);
3231 } else {
6cc69f2a 3232 cancel_delayed_work_sync(&tp->schedule);
9a4be1bd 3233 tp->rtl_ops.down(tp);
9a4be1bd 3234 }
445f7f4d 3235 tasklet_enable(&tp->tl);
ac718b69 3236 }
6cc69f2a 3237out1:
b5403273 3238 mutex_unlock(&tp->control);
3239
6cc69f2a 3240 return ret;
ac718b69 3241}
3242
3243static int rtl8152_resume(struct usb_interface *intf)
3244{
3245 struct r8152 *tp = usb_get_intfdata(intf);
3246
b5403273 3247 mutex_lock(&tp->control);
3248
9a4be1bd 3249 if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3250 tp->rtl_ops.init(tp);
3251 netif_device_attach(tp->netdev);
3252 }
3253
ac718b69 3254 if (netif_running(tp->netdev)) {
9a4be1bd 3255 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3256 rtl_runtime_suspend_enable(tp, false);
3257 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
445f7f4d 3258 set_bit(WORK_ENABLE, &tp->flags);
9a4be1bd 3259 if (tp->speed & LINK_STATUS)
445f7f4d 3260 rtl_start_rx(tp);
9a4be1bd 3261 } else {
3262 tp->rtl_ops.up(tp);
3263 rtl8152_set_speed(tp, AUTONEG_ENABLE,
b209af99 3264 tp->mii.supports_gmii ?
3265 SPEED_1000 : SPEED_100,
3266 DUPLEX_FULL);
445f7f4d 3267 tp->speed = 0;
3268 netif_carrier_off(tp->netdev);
3269 set_bit(WORK_ENABLE, &tp->flags);
9a4be1bd 3270 }
40a82917 3271 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
923e1ee3 3272 } else if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3273 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
ac718b69 3274 }
3275
b5403273 3276 mutex_unlock(&tp->control);
3277
ac718b69 3278 return 0;
3279}
3280
21ff2e89 3281static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3282{
3283 struct r8152 *tp = netdev_priv(dev);
3284
9a4be1bd 3285 if (usb_autopm_get_interface(tp->intf) < 0)
3286 return;
3287
b5403273 3288 mutex_lock(&tp->control);
3289
21ff2e89 3290 wol->supported = WAKE_ANY;
3291 wol->wolopts = __rtl_get_wol(tp);
9a4be1bd 3292
b5403273 3293 mutex_unlock(&tp->control);
3294
9a4be1bd 3295 usb_autopm_put_interface(tp->intf);
21ff2e89 3296}
3297
3298static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3299{
3300 struct r8152 *tp = netdev_priv(dev);
9a4be1bd 3301 int ret;
3302
3303 ret = usb_autopm_get_interface(tp->intf);
3304 if (ret < 0)
3305 goto out_set_wol;
21ff2e89 3306
b5403273 3307 mutex_lock(&tp->control);
3308
21ff2e89 3309 __rtl_set_wol(tp, wol->wolopts);
3310 tp->saved_wolopts = wol->wolopts & WAKE_ANY;
3311
b5403273 3312 mutex_unlock(&tp->control);
3313
9a4be1bd 3314 usb_autopm_put_interface(tp->intf);
3315
3316out_set_wol:
3317 return ret;
21ff2e89 3318}
3319
a5ec27c1 3320static u32 rtl8152_get_msglevel(struct net_device *dev)
3321{
3322 struct r8152 *tp = netdev_priv(dev);
3323
3324 return tp->msg_enable;
3325}
3326
3327static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
3328{
3329 struct r8152 *tp = netdev_priv(dev);
3330
3331 tp->msg_enable = value;
3332}
3333
ac718b69 3334static void rtl8152_get_drvinfo(struct net_device *netdev,
3335 struct ethtool_drvinfo *info)
3336{
3337 struct r8152 *tp = netdev_priv(netdev);
3338
b0b46c77 3339 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
3340 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
ac718b69 3341 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
3342}
3343
3344static
3345int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
3346{
3347 struct r8152 *tp = netdev_priv(netdev);
8d4a4d72 3348 int ret;
ac718b69 3349
3350 if (!tp->mii.mdio_read)
3351 return -EOPNOTSUPP;
3352
8d4a4d72 3353 ret = usb_autopm_get_interface(tp->intf);
3354 if (ret < 0)
3355 goto out;
3356
b5403273 3357 mutex_lock(&tp->control);
3358
8d4a4d72 3359 ret = mii_ethtool_gset(&tp->mii, cmd);
3360
b5403273 3361 mutex_unlock(&tp->control);
3362
8d4a4d72 3363 usb_autopm_put_interface(tp->intf);
3364
3365out:
3366 return ret;
ac718b69 3367}
3368
3369static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
3370{
3371 struct r8152 *tp = netdev_priv(dev);
9a4be1bd 3372 int ret;
3373
3374 ret = usb_autopm_get_interface(tp->intf);
3375 if (ret < 0)
3376 goto out;
ac718b69 3377
b5403273 3378 mutex_lock(&tp->control);
3379
9a4be1bd 3380 ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
3381
b5403273 3382 mutex_unlock(&tp->control);
3383
9a4be1bd 3384 usb_autopm_put_interface(tp->intf);
3385
3386out:
3387 return ret;
ac718b69 3388}
3389
4f1d4d54 3390static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
3391 "tx_packets",
3392 "rx_packets",
3393 "tx_errors",
3394 "rx_errors",
3395 "rx_missed",
3396 "align_errors",
3397 "tx_single_collisions",
3398 "tx_multi_collisions",
3399 "rx_unicast",
3400 "rx_broadcast",
3401 "rx_multicast",
3402 "tx_aborted",
3403 "tx_underrun",
3404};
3405
3406static int rtl8152_get_sset_count(struct net_device *dev, int sset)
3407{
3408 switch (sset) {
3409 case ETH_SS_STATS:
3410 return ARRAY_SIZE(rtl8152_gstrings);
3411 default:
3412 return -EOPNOTSUPP;
3413 }
3414}
3415
3416static void rtl8152_get_ethtool_stats(struct net_device *dev,
3417 struct ethtool_stats *stats, u64 *data)
3418{
3419 struct r8152 *tp = netdev_priv(dev);
3420 struct tally_counter tally;
3421
0b030244 3422 if (usb_autopm_get_interface(tp->intf) < 0)
3423 return;
3424
4f1d4d54 3425 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
3426
0b030244 3427 usb_autopm_put_interface(tp->intf);
3428
4f1d4d54 3429 data[0] = le64_to_cpu(tally.tx_packets);
3430 data[1] = le64_to_cpu(tally.rx_packets);
3431 data[2] = le64_to_cpu(tally.tx_errors);
3432 data[3] = le32_to_cpu(tally.rx_errors);
3433 data[4] = le16_to_cpu(tally.rx_missed);
3434 data[5] = le16_to_cpu(tally.align_errors);
3435 data[6] = le32_to_cpu(tally.tx_one_collision);
3436 data[7] = le32_to_cpu(tally.tx_multi_collision);
3437 data[8] = le64_to_cpu(tally.rx_unicast);
3438 data[9] = le64_to_cpu(tally.rx_broadcast);
3439 data[10] = le32_to_cpu(tally.rx_multicast);
3440 data[11] = le16_to_cpu(tally.tx_aborted);
f37119c5 3441 data[12] = le16_to_cpu(tally.tx_underrun);
4f1d4d54 3442}
3443
3444static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
3445{
3446 switch (stringset) {
3447 case ETH_SS_STATS:
3448 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
3449 break;
3450 }
3451}
3452
df35d283 3453static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
3454{
3455 u32 ocp_data, lp, adv, supported = 0;
3456 u16 val;
3457
3458 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
3459 supported = mmd_eee_cap_to_ethtool_sup_t(val);
3460
3461 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
3462 adv = mmd_eee_adv_to_ethtool_adv_t(val);
3463
3464 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
3465 lp = mmd_eee_adv_to_ethtool_adv_t(val);
3466
3467 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3468 ocp_data &= EEE_RX_EN | EEE_TX_EN;
3469
3470 eee->eee_enabled = !!ocp_data;
3471 eee->eee_active = !!(supported & adv & lp);
3472 eee->supported = supported;
3473 eee->advertised = adv;
3474 eee->lp_advertised = lp;
3475
3476 return 0;
3477}
3478
3479static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
3480{
3481 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
3482
3483 r8152_eee_en(tp, eee->eee_enabled);
3484
3485 if (!eee->eee_enabled)
3486 val = 0;
3487
3488 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3489
3490 return 0;
3491}
3492
3493static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
3494{
3495 u32 ocp_data, lp, adv, supported = 0;
3496 u16 val;
3497
3498 val = ocp_reg_read(tp, OCP_EEE_ABLE);
3499 supported = mmd_eee_cap_to_ethtool_sup_t(val);
3500
3501 val = ocp_reg_read(tp, OCP_EEE_ADV);
3502 adv = mmd_eee_adv_to_ethtool_adv_t(val);
3503
3504 val = ocp_reg_read(tp, OCP_EEE_LPABLE);
3505 lp = mmd_eee_adv_to_ethtool_adv_t(val);
3506
3507 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3508 ocp_data &= EEE_RX_EN | EEE_TX_EN;
3509
3510 eee->eee_enabled = !!ocp_data;
3511 eee->eee_active = !!(supported & adv & lp);
3512 eee->supported = supported;
3513 eee->advertised = adv;
3514 eee->lp_advertised = lp;
3515
3516 return 0;
3517}
3518
3519static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
3520{
3521 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
3522
3523 r8153_eee_en(tp, eee->eee_enabled);
3524
3525 if (!eee->eee_enabled)
3526 val = 0;
3527
3528 ocp_reg_write(tp, OCP_EEE_ADV, val);
3529
3530 return 0;
3531}
3532
3533static int
3534rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
3535{
3536 struct r8152 *tp = netdev_priv(net);
3537 int ret;
3538
3539 ret = usb_autopm_get_interface(tp->intf);
3540 if (ret < 0)
3541 goto out;
3542
b5403273 3543 mutex_lock(&tp->control);
3544
df35d283 3545 ret = tp->rtl_ops.eee_get(tp, edata);
3546
b5403273 3547 mutex_unlock(&tp->control);
3548
df35d283 3549 usb_autopm_put_interface(tp->intf);
3550
3551out:
3552 return ret;
3553}
3554
3555static int
3556rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
3557{
3558 struct r8152 *tp = netdev_priv(net);
3559 int ret;
3560
3561 ret = usb_autopm_get_interface(tp->intf);
3562 if (ret < 0)
3563 goto out;
3564
b5403273 3565 mutex_lock(&tp->control);
3566
df35d283 3567 ret = tp->rtl_ops.eee_set(tp, edata);
9d31a7b9 3568 if (!ret)
3569 ret = mii_nway_restart(&tp->mii);
df35d283 3570
b5403273 3571 mutex_unlock(&tp->control);
3572
df35d283 3573 usb_autopm_put_interface(tp->intf);
3574
3575out:
3576 return ret;
3577}
3578
8884f507 3579static int rtl8152_nway_reset(struct net_device *dev)
3580{
3581 struct r8152 *tp = netdev_priv(dev);
3582 int ret;
3583
3584 ret = usb_autopm_get_interface(tp->intf);
3585 if (ret < 0)
3586 goto out;
3587
3588 mutex_lock(&tp->control);
3589
3590 ret = mii_nway_restart(&tp->mii);
3591
3592 mutex_unlock(&tp->control);
3593
3594 usb_autopm_put_interface(tp->intf);
3595
3596out:
3597 return ret;
3598}
3599
ac718b69 3600static struct ethtool_ops ops = {
3601 .get_drvinfo = rtl8152_get_drvinfo,
3602 .get_settings = rtl8152_get_settings,
3603 .set_settings = rtl8152_set_settings,
3604 .get_link = ethtool_op_get_link,
8884f507 3605 .nway_reset = rtl8152_nway_reset,
a5ec27c1 3606 .get_msglevel = rtl8152_get_msglevel,
3607 .set_msglevel = rtl8152_set_msglevel,
21ff2e89 3608 .get_wol = rtl8152_get_wol,
3609 .set_wol = rtl8152_set_wol,
4f1d4d54 3610 .get_strings = rtl8152_get_strings,
3611 .get_sset_count = rtl8152_get_sset_count,
3612 .get_ethtool_stats = rtl8152_get_ethtool_stats,
df35d283 3613 .get_eee = rtl_ethtool_get_eee,
3614 .set_eee = rtl_ethtool_set_eee,
ac718b69 3615};
3616
3617static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
3618{
3619 struct r8152 *tp = netdev_priv(netdev);
3620 struct mii_ioctl_data *data = if_mii(rq);
9a4be1bd 3621 int res;
3622
6871438c 3623 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3624 return -ENODEV;
3625
9a4be1bd 3626 res = usb_autopm_get_interface(tp->intf);
3627 if (res < 0)
3628 goto out;
ac718b69 3629
3630 switch (cmd) {
3631 case SIOCGMIIPHY:
3632 data->phy_id = R8152_PHY_ID; /* Internal PHY */
3633 break;
3634
3635 case SIOCGMIIREG:
b5403273 3636 mutex_lock(&tp->control);
ac718b69 3637 data->val_out = r8152_mdio_read(tp, data->reg_num);
b5403273 3638 mutex_unlock(&tp->control);
ac718b69 3639 break;
3640
3641 case SIOCSMIIREG:
3642 if (!capable(CAP_NET_ADMIN)) {
3643 res = -EPERM;
3644 break;
3645 }
b5403273 3646 mutex_lock(&tp->control);
ac718b69 3647 r8152_mdio_write(tp, data->reg_num, data->val_in);
b5403273 3648 mutex_unlock(&tp->control);
ac718b69 3649 break;
3650
3651 default:
3652 res = -EOPNOTSUPP;
3653 }
3654
9a4be1bd 3655 usb_autopm_put_interface(tp->intf);
3656
3657out:
ac718b69 3658 return res;
3659}
3660
69b4b7a4 3661static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
3662{
3663 struct r8152 *tp = netdev_priv(dev);
3664
3665 switch (tp->version) {
3666 case RTL_VER_01:
3667 case RTL_VER_02:
3668 return eth_change_mtu(dev, new_mtu);
3669 default:
3670 break;
3671 }
3672
3673 if (new_mtu < 68 || new_mtu > RTL8153_MAX_MTU)
3674 return -EINVAL;
3675
3676 dev->mtu = new_mtu;
3677
3678 return 0;
3679}
3680
ac718b69 3681static const struct net_device_ops rtl8152_netdev_ops = {
3682 .ndo_open = rtl8152_open,
3683 .ndo_stop = rtl8152_close,
3684 .ndo_do_ioctl = rtl8152_ioctl,
3685 .ndo_start_xmit = rtl8152_start_xmit,
3686 .ndo_tx_timeout = rtl8152_tx_timeout,
c5554298 3687 .ndo_set_features = rtl8152_set_features,
ac718b69 3688 .ndo_set_rx_mode = rtl8152_set_rx_mode,
3689 .ndo_set_mac_address = rtl8152_set_mac_address,
69b4b7a4 3690 .ndo_change_mtu = rtl8152_change_mtu,
ac718b69 3691 .ndo_validate_addr = eth_validate_addr,
3692};
3693
3694static void r8152b_get_version(struct r8152 *tp)
3695{
3696 u32 ocp_data;
3697 u16 version;
3698
3699 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
3700 version = (u16)(ocp_data & VERSION_MASK);
3701
3702 switch (version) {
3703 case 0x4c00:
3704 tp->version = RTL_VER_01;
3705 break;
3706 case 0x4c10:
3707 tp->version = RTL_VER_02;
3708 break;
43779f8d 3709 case 0x5c00:
3710 tp->version = RTL_VER_03;
3711 tp->mii.supports_gmii = 1;
3712 break;
3713 case 0x5c10:
3714 tp->version = RTL_VER_04;
3715 tp->mii.supports_gmii = 1;
3716 break;
3717 case 0x5c20:
3718 tp->version = RTL_VER_05;
3719 tp->mii.supports_gmii = 1;
3720 break;
ac718b69 3721 default:
3722 netif_info(tp, probe, tp->netdev,
3723 "Unknown version 0x%04x\n", version);
3724 break;
3725 }
3726}
3727
e3fe0b1a 3728static void rtl8152_unload(struct r8152 *tp)
3729{
6871438c 3730 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3731 return;
3732
00a5e360 3733 if (tp->version != RTL_VER_01)
3734 r8152_power_cut_en(tp, true);
e3fe0b1a 3735}
3736
43779f8d 3737static void rtl8153_unload(struct r8152 *tp)
3738{
6871438c 3739 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3740 return;
3741
49be1723 3742 r8153_power_cut_en(tp, false);
43779f8d 3743}
3744
31ca1dec 3745static int rtl_ops_init(struct r8152 *tp, const struct usb_device_id *id)
c81229c9 3746{
3747 struct rtl_ops *ops = &tp->rtl_ops;
31ca1dec 3748 int ret = -ENODEV;
c81229c9 3749
3750 switch (id->idVendor) {
3751 case VENDOR_ID_REALTEK:
3752 switch (id->idProduct) {
3753 case PRODUCT_ID_RTL8152:
3754 ops->init = r8152b_init;
3755 ops->enable = rtl8152_enable;
3756 ops->disable = rtl8152_disable;
d70b1137 3757 ops->up = rtl8152_up;
c81229c9 3758 ops->down = rtl8152_down;
3759 ops->unload = rtl8152_unload;
df35d283 3760 ops->eee_get = r8152_get_eee;
3761 ops->eee_set = r8152_set_eee;
31ca1dec 3762 ret = 0;
c81229c9 3763 break;
43779f8d 3764 case PRODUCT_ID_RTL8153:
3765 ops->init = r8153_init;
3766 ops->enable = rtl8153_enable;
d70b1137 3767 ops->disable = rtl8153_disable;
3768 ops->up = rtl8153_up;
43779f8d 3769 ops->down = rtl8153_down;
3770 ops->unload = rtl8153_unload;
df35d283 3771 ops->eee_get = r8153_get_eee;
3772 ops->eee_set = r8153_set_eee;
31ca1dec 3773 ret = 0;
43779f8d 3774 break;
3775 default:
43779f8d 3776 break;
3777 }
3778 break;
3779
3780 case VENDOR_ID_SAMSUNG:
3781 switch (id->idProduct) {
3782 case PRODUCT_ID_SAMSUNG:
3783 ops->init = r8153_init;
3784 ops->enable = rtl8153_enable;
d70b1137 3785 ops->disable = rtl8153_disable;
3786 ops->up = rtl8153_up;
43779f8d 3787 ops->down = rtl8153_down;
3788 ops->unload = rtl8153_unload;
df35d283 3789 ops->eee_get = r8153_get_eee;
3790 ops->eee_set = r8153_set_eee;
31ca1dec 3791 ret = 0;
43779f8d 3792 break;
c81229c9 3793 default:
c81229c9 3794 break;
3795 }
3796 break;
3797
3798 default:
c81229c9 3799 break;
3800 }
3801
31ca1dec 3802 if (ret)
3803 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
3804
c81229c9 3805 return ret;
3806}
3807
ac718b69 3808static int rtl8152_probe(struct usb_interface *intf,
3809 const struct usb_device_id *id)
3810{
3811 struct usb_device *udev = interface_to_usbdev(intf);
3812 struct r8152 *tp;
3813 struct net_device *netdev;
ebc2ec48 3814 int ret;
ac718b69 3815
10c32717 3816 if (udev->actconfig->desc.bConfigurationValue != 1) {
3817 usb_driver_set_configuration(udev, 1);
3818 return -ENODEV;
3819 }
3820
3821 usb_reset_device(udev);
ac718b69 3822 netdev = alloc_etherdev(sizeof(struct r8152));
3823 if (!netdev) {
4a8deae2 3824 dev_err(&intf->dev, "Out of memory\n");
ac718b69 3825 return -ENOMEM;
3826 }
3827
ebc2ec48 3828 SET_NETDEV_DEV(netdev, &intf->dev);
ac718b69 3829 tp = netdev_priv(netdev);
3830 tp->msg_enable = 0x7FFF;
3831
e3ad412a 3832 tp->udev = udev;
3833 tp->netdev = netdev;
3834 tp->intf = intf;
3835
82cf94cb 3836 r8152b_get_version(tp);
31ca1dec 3837 ret = rtl_ops_init(tp, id);
3838 if (ret)
3839 goto out;
c81229c9 3840
ebc2ec48 3841 tasklet_init(&tp->tl, bottom_half, (unsigned long)tp);
b5403273 3842 mutex_init(&tp->control);
ac718b69 3843 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
3844
ac718b69 3845 netdev->netdev_ops = &rtl8152_netdev_ops;
3846 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
5bd23881 3847
60c89071 3848 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
6128d1bb 3849 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
c5554298 3850 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
3851 NETIF_F_HW_VLAN_CTAG_TX;
60c89071 3852 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
6128d1bb 3853 NETIF_F_TSO | NETIF_F_FRAGLIST |
c5554298 3854 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
3855 NETIF_F_HW_VLAN_CTAG_RX |
3856 NETIF_F_HW_VLAN_CTAG_TX;
3857 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3858 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
3859 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
db8515ef 3860
7ad24ea4 3861 netdev->ethtool_ops = &ops;
60c89071 3862 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
ac718b69 3863
3864 tp->mii.dev = netdev;
3865 tp->mii.mdio_read = read_mii_word;
3866 tp->mii.mdio_write = write_mii_word;
3867 tp->mii.phy_id_mask = 0x3f;
3868 tp->mii.reg_num_mask = 0x1f;
3869 tp->mii.phy_id = R8152_PHY_ID;
ac718b69 3870
9a4be1bd 3871 intf->needs_remote_wakeup = 1;
3872
c81229c9 3873 tp->rtl_ops.init(tp);
ac718b69 3874 set_ethernet_addr(tp);
3875
ac718b69 3876 usb_set_intfdata(intf, tp);
ac718b69 3877
ebc2ec48 3878 ret = register_netdev(netdev);
3879 if (ret != 0) {
4a8deae2 3880 netif_err(tp, probe, netdev, "couldn't register the device\n");
ebc2ec48 3881 goto out1;
ac718b69 3882 }
3883
21ff2e89 3884 tp->saved_wolopts = __rtl_get_wol(tp);
3885 if (tp->saved_wolopts)
3886 device_set_wakeup_enable(&udev->dev, true);
3887 else
3888 device_set_wakeup_enable(&udev->dev, false);
3889
93ffbeab 3890 tasklet_disable(&tp->tl);
3891
4a8deae2 3892 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
ac718b69 3893
3894 return 0;
3895
ac718b69 3896out1:
ebc2ec48 3897 usb_set_intfdata(intf, NULL);
93ffbeab 3898 tasklet_kill(&tp->tl);
ac718b69 3899out:
3900 free_netdev(netdev);
ebc2ec48 3901 return ret;
ac718b69 3902}
3903
ac718b69 3904static void rtl8152_disconnect(struct usb_interface *intf)
3905{
3906 struct r8152 *tp = usb_get_intfdata(intf);
3907
3908 usb_set_intfdata(intf, NULL);
3909 if (tp) {
f561de33 3910 struct usb_device *udev = tp->udev;
3911
3912 if (udev->state == USB_STATE_NOTATTACHED)
3913 set_bit(RTL8152_UNPLUG, &tp->flags);
3914
ac718b69 3915 tasklet_kill(&tp->tl);
3916 unregister_netdev(tp->netdev);
c81229c9 3917 tp->rtl_ops.unload(tp);
ac718b69 3918 free_netdev(tp->netdev);
3919 }
3920}
3921
3922/* table of devices that work with this driver */
3923static struct usb_device_id rtl8152_table[] = {
10c32717 3924 {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8152)},
3925 {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8153)},
3926 {USB_DEVICE(VENDOR_ID_SAMSUNG, PRODUCT_ID_SAMSUNG)},
ac718b69 3927 {}
3928};
3929
3930MODULE_DEVICE_TABLE(usb, rtl8152_table);
3931
3932static struct usb_driver rtl8152_driver = {
3933 .name = MODULENAME,
ebc2ec48 3934 .id_table = rtl8152_table,
ac718b69 3935 .probe = rtl8152_probe,
3936 .disconnect = rtl8152_disconnect,
ac718b69 3937 .suspend = rtl8152_suspend,
ebc2ec48 3938 .resume = rtl8152_resume,
3939 .reset_resume = rtl8152_resume,
9a4be1bd 3940 .supports_autosuspend = 1,
a634782f 3941 .disable_hub_initiated_lpm = 1,
ac718b69 3942};
3943
b4236daa 3944module_usb_driver(rtl8152_driver);
ac718b69 3945
3946MODULE_AUTHOR(DRIVER_AUTHOR);
3947MODULE_DESCRIPTION(DRIVER_DESC);
3948MODULE_LICENSE("GPL");