Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * tg3.c: Broadcom Tigon3 ethernet driver. | |
3 | * | |
4 | * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com) | |
5 | * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com) | |
6 | * Copyright (C) 2004 Sun Microsystems Inc. | |
b86fb2cf | 7 | * Copyright (C) 2005-2011 Broadcom Corporation. |
1da177e4 LT |
8 | * |
9 | * Firmware is: | |
49cabf49 MC |
10 | * Derived from proprietary unpublished source code, |
11 | * Copyright (C) 2000-2003 Broadcom Corporation. | |
12 | * | |
13 | * Permission is hereby granted for the distribution of this firmware | |
14 | * data in hexadecimal or equivalent format, provided this copyright | |
15 | * notice is accompanying it. | |
1da177e4 LT |
16 | */ |
17 | ||
1da177e4 LT |
18 | |
19 | #include <linux/module.h> | |
20 | #include <linux/moduleparam.h> | |
6867c843 | 21 | #include <linux/stringify.h> |
1da177e4 LT |
22 | #include <linux/kernel.h> |
23 | #include <linux/types.h> | |
24 | #include <linux/compiler.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/delay.h> | |
14c85021 | 27 | #include <linux/in.h> |
1da177e4 | 28 | #include <linux/init.h> |
a6b7a407 | 29 | #include <linux/interrupt.h> |
1da177e4 LT |
30 | #include <linux/ioport.h> |
31 | #include <linux/pci.h> | |
32 | #include <linux/netdevice.h> | |
33 | #include <linux/etherdevice.h> | |
34 | #include <linux/skbuff.h> | |
35 | #include <linux/ethtool.h> | |
3110f5f5 | 36 | #include <linux/mdio.h> |
1da177e4 | 37 | #include <linux/mii.h> |
158d7abd | 38 | #include <linux/phy.h> |
a9daf367 | 39 | #include <linux/brcmphy.h> |
1da177e4 LT |
40 | #include <linux/if_vlan.h> |
41 | #include <linux/ip.h> | |
42 | #include <linux/tcp.h> | |
43 | #include <linux/workqueue.h> | |
61487480 | 44 | #include <linux/prefetch.h> |
f9a5f7d3 | 45 | #include <linux/dma-mapping.h> |
077f849d | 46 | #include <linux/firmware.h> |
1da177e4 LT |
47 | |
48 | #include <net/checksum.h> | |
c9bdd4b5 | 49 | #include <net/ip.h> |
1da177e4 LT |
50 | |
51 | #include <asm/system.h> | |
27fd9de8 | 52 | #include <linux/io.h> |
1da177e4 | 53 | #include <asm/byteorder.h> |
27fd9de8 | 54 | #include <linux/uaccess.h> |
1da177e4 | 55 | |
49b6e95f | 56 | #ifdef CONFIG_SPARC |
1da177e4 | 57 | #include <asm/idprom.h> |
49b6e95f | 58 | #include <asm/prom.h> |
1da177e4 LT |
59 | #endif |
60 | ||
63532394 MC |
61 | #define BAR_0 0 |
62 | #define BAR_2 2 | |
63 | ||
1da177e4 LT |
64 | #include "tg3.h" |
65 | ||
63c3a66f JP |
66 | /* Functions & macros to verify TG3_FLAGS types */ |
67 | ||
68 | static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits) | |
69 | { | |
70 | return test_bit(flag, bits); | |
71 | } | |
72 | ||
73 | static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits) | |
74 | { | |
75 | set_bit(flag, bits); | |
76 | } | |
77 | ||
78 | static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits) | |
79 | { | |
80 | clear_bit(flag, bits); | |
81 | } | |
82 | ||
83 | #define tg3_flag(tp, flag) \ | |
84 | _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags) | |
85 | #define tg3_flag_set(tp, flag) \ | |
86 | _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags) | |
87 | #define tg3_flag_clear(tp, flag) \ | |
88 | _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags) | |
89 | ||
1da177e4 | 90 | #define DRV_MODULE_NAME "tg3" |
6867c843 | 91 | #define TG3_MAJ_NUM 3 |
43a5f002 | 92 | #define TG3_MIN_NUM 119 |
6867c843 MC |
93 | #define DRV_MODULE_VERSION \ |
94 | __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM) | |
43a5f002 | 95 | #define DRV_MODULE_RELDATE "May 18, 2011" |
1da177e4 LT |
96 | |
97 | #define TG3_DEF_MAC_MODE 0 | |
98 | #define TG3_DEF_RX_MODE 0 | |
99 | #define TG3_DEF_TX_MODE 0 | |
100 | #define TG3_DEF_MSG_ENABLE \ | |
101 | (NETIF_MSG_DRV | \ | |
102 | NETIF_MSG_PROBE | \ | |
103 | NETIF_MSG_LINK | \ | |
104 | NETIF_MSG_TIMER | \ | |
105 | NETIF_MSG_IFDOWN | \ | |
106 | NETIF_MSG_IFUP | \ | |
107 | NETIF_MSG_RX_ERR | \ | |
108 | NETIF_MSG_TX_ERR) | |
109 | ||
520b2756 MC |
110 | #define TG3_GRC_LCLCTL_PWRSW_DELAY 100 |
111 | ||
1da177e4 LT |
112 | /* length of time before we decide the hardware is borked, |
113 | * and dev->tx_timeout() should be called to fix the problem | |
114 | */ | |
63c3a66f | 115 | |
1da177e4 LT |
116 | #define TG3_TX_TIMEOUT (5 * HZ) |
117 | ||
118 | /* hardware minimum and maximum for a single frame's data payload */ | |
119 | #define TG3_MIN_MTU 60 | |
120 | #define TG3_MAX_MTU(tp) \ | |
63c3a66f | 121 | (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500) |
1da177e4 LT |
122 | |
123 | /* These numbers seem to be hard coded in the NIC firmware somehow. | |
124 | * You can't change the ring sizes, but you can change where you place | |
125 | * them in the NIC onboard memory. | |
126 | */ | |
7cb32cf2 | 127 | #define TG3_RX_STD_RING_SIZE(tp) \ |
63c3a66f | 128 | (tg3_flag(tp, LRG_PROD_RING_CAP) ? \ |
de9f5230 | 129 | TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700) |
1da177e4 | 130 | #define TG3_DEF_RX_RING_PENDING 200 |
7cb32cf2 | 131 | #define TG3_RX_JMB_RING_SIZE(tp) \ |
63c3a66f | 132 | (tg3_flag(tp, LRG_PROD_RING_CAP) ? \ |
de9f5230 | 133 | TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700) |
1da177e4 | 134 | #define TG3_DEF_RX_JUMBO_RING_PENDING 100 |
c6cdf436 | 135 | #define TG3_RSS_INDIR_TBL_SIZE 128 |
1da177e4 LT |
136 | |
137 | /* Do not place this n-ring entries value into the tp struct itself, | |
138 | * we really want to expose these constants to GCC so that modulo et | |
139 | * al. operations are done with shifts and masks instead of with | |
140 | * hw multiply/modulo instructions. Another solution would be to | |
141 | * replace things like '% foo' with '& (foo - 1)'. | |
142 | */ | |
1da177e4 LT |
143 | |
144 | #define TG3_TX_RING_SIZE 512 | |
145 | #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1) | |
146 | ||
2c49a44d MC |
147 | #define TG3_RX_STD_RING_BYTES(tp) \ |
148 | (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp)) | |
149 | #define TG3_RX_JMB_RING_BYTES(tp) \ | |
150 | (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp)) | |
151 | #define TG3_RX_RCB_RING_BYTES(tp) \ | |
7cb32cf2 | 152 | (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1)) |
1da177e4 LT |
153 | #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \ |
154 | TG3_TX_RING_SIZE) | |
1da177e4 LT |
155 | #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1)) |
156 | ||
287be12e MC |
157 | #define TG3_DMA_BYTE_ENAB 64 |
158 | ||
159 | #define TG3_RX_STD_DMA_SZ 1536 | |
160 | #define TG3_RX_JMB_DMA_SZ 9046 | |
161 | ||
162 | #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB) | |
163 | ||
164 | #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ) | |
165 | #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ) | |
1da177e4 | 166 | |
2c49a44d MC |
167 | #define TG3_RX_STD_BUFF_RING_SIZE(tp) \ |
168 | (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp)) | |
2b2cdb65 | 169 | |
2c49a44d MC |
170 | #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \ |
171 | (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp)) | |
2b2cdb65 | 172 | |
d2757fc4 MC |
173 | /* Due to a hardware bug, the 5701 can only DMA to memory addresses |
174 | * that are at least dword aligned when used in PCIX mode. The driver | |
175 | * works around this bug by double copying the packet. This workaround | |
176 | * is built into the normal double copy length check for efficiency. | |
177 | * | |
178 | * However, the double copy is only necessary on those architectures | |
179 | * where unaligned memory accesses are inefficient. For those architectures | |
180 | * where unaligned memory accesses incur little penalty, we can reintegrate | |
181 | * the 5701 in the normal rx path. Doing so saves a device structure | |
182 | * dereference by hardcoding the double copy threshold in place. | |
183 | */ | |
184 | #define TG3_RX_COPY_THRESHOLD 256 | |
185 | #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS) | |
186 | #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD | |
187 | #else | |
188 | #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh) | |
189 | #endif | |
190 | ||
1da177e4 | 191 | /* minimum number of free TX descriptors required to wake up TX process */ |
f3f3f27e | 192 | #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4) |
1da177e4 | 193 | |
ad829268 MC |
194 | #define TG3_RAW_IP_ALIGN 2 |
195 | ||
c6cdf436 MC |
196 | #define TG3_FW_UPDATE_TIMEOUT_SEC 5 |
197 | ||
077f849d JSR |
198 | #define FIRMWARE_TG3 "tigon/tg3.bin" |
199 | #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin" | |
200 | #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin" | |
201 | ||
1da177e4 | 202 | static char version[] __devinitdata = |
05dbe005 | 203 | DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")"; |
1da177e4 LT |
204 | |
205 | MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)"); | |
206 | MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver"); | |
207 | MODULE_LICENSE("GPL"); | |
208 | MODULE_VERSION(DRV_MODULE_VERSION); | |
077f849d JSR |
209 | MODULE_FIRMWARE(FIRMWARE_TG3); |
210 | MODULE_FIRMWARE(FIRMWARE_TG3TSO); | |
211 | MODULE_FIRMWARE(FIRMWARE_TG3TSO5); | |
212 | ||
1da177e4 LT |
213 | static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */ |
214 | module_param(tg3_debug, int, 0); | |
215 | MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value"); | |
216 | ||
a3aa1884 | 217 | static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = { |
13185217 HK |
218 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)}, |
219 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)}, | |
220 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)}, | |
221 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)}, | |
222 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)}, | |
223 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)}, | |
224 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)}, | |
225 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)}, | |
226 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)}, | |
227 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)}, | |
228 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)}, | |
229 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)}, | |
230 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)}, | |
231 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)}, | |
232 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)}, | |
233 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)}, | |
234 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)}, | |
235 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)}, | |
236 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)}, | |
237 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)}, | |
238 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)}, | |
239 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)}, | |
13185217 | 240 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)}, |
126a3368 | 241 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)}, |
13185217 | 242 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)}, |
13185217 HK |
243 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)}, |
244 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)}, | |
245 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)}, | |
246 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)}, | |
247 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)}, | |
248 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)}, | |
249 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)}, | |
250 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)}, | |
251 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)}, | |
252 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)}, | |
253 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)}, | |
126a3368 | 254 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)}, |
13185217 HK |
255 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)}, |
256 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)}, | |
257 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)}, | |
676917d4 | 258 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)}, |
13185217 HK |
259 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)}, |
260 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)}, | |
261 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)}, | |
262 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)}, | |
263 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)}, | |
264 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)}, | |
265 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)}, | |
b5d3772c MC |
266 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)}, |
267 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)}, | |
d30cdd28 MC |
268 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)}, |
269 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)}, | |
6c7af27c | 270 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)}, |
9936bcf6 MC |
271 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)}, |
272 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)}, | |
c88e668b MC |
273 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)}, |
274 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)}, | |
2befdcea MC |
275 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)}, |
276 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)}, | |
321d32a0 MC |
277 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)}, |
278 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)}, | |
279 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)}, | |
5e7ccf20 | 280 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)}, |
5001e2f6 MC |
281 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)}, |
282 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)}, | |
b0f75221 MC |
283 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)}, |
284 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)}, | |
285 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)}, | |
286 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)}, | |
287 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)}, | |
288 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)}, | |
302b500b | 289 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)}, |
ba1f3c76 | 290 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)}, |
13185217 HK |
291 | {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)}, |
292 | {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)}, | |
293 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)}, | |
294 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)}, | |
295 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)}, | |
296 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)}, | |
297 | {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)}, | |
1dcb14d9 | 298 | {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */ |
13185217 | 299 | {} |
1da177e4 LT |
300 | }; |
301 | ||
302 | MODULE_DEVICE_TABLE(pci, tg3_pci_tbl); | |
303 | ||
50da859d | 304 | static const struct { |
1da177e4 | 305 | const char string[ETH_GSTRING_LEN]; |
48fa55a0 | 306 | } ethtool_stats_keys[] = { |
1da177e4 LT |
307 | { "rx_octets" }, |
308 | { "rx_fragments" }, | |
309 | { "rx_ucast_packets" }, | |
310 | { "rx_mcast_packets" }, | |
311 | { "rx_bcast_packets" }, | |
312 | { "rx_fcs_errors" }, | |
313 | { "rx_align_errors" }, | |
314 | { "rx_xon_pause_rcvd" }, | |
315 | { "rx_xoff_pause_rcvd" }, | |
316 | { "rx_mac_ctrl_rcvd" }, | |
317 | { "rx_xoff_entered" }, | |
318 | { "rx_frame_too_long_errors" }, | |
319 | { "rx_jabbers" }, | |
320 | { "rx_undersize_packets" }, | |
321 | { "rx_in_length_errors" }, | |
322 | { "rx_out_length_errors" }, | |
323 | { "rx_64_or_less_octet_packets" }, | |
324 | { "rx_65_to_127_octet_packets" }, | |
325 | { "rx_128_to_255_octet_packets" }, | |
326 | { "rx_256_to_511_octet_packets" }, | |
327 | { "rx_512_to_1023_octet_packets" }, | |
328 | { "rx_1024_to_1522_octet_packets" }, | |
329 | { "rx_1523_to_2047_octet_packets" }, | |
330 | { "rx_2048_to_4095_octet_packets" }, | |
331 | { "rx_4096_to_8191_octet_packets" }, | |
332 | { "rx_8192_to_9022_octet_packets" }, | |
333 | ||
334 | { "tx_octets" }, | |
335 | { "tx_collisions" }, | |
336 | ||
337 | { "tx_xon_sent" }, | |
338 | { "tx_xoff_sent" }, | |
339 | { "tx_flow_control" }, | |
340 | { "tx_mac_errors" }, | |
341 | { "tx_single_collisions" }, | |
342 | { "tx_mult_collisions" }, | |
343 | { "tx_deferred" }, | |
344 | { "tx_excessive_collisions" }, | |
345 | { "tx_late_collisions" }, | |
346 | { "tx_collide_2times" }, | |
347 | { "tx_collide_3times" }, | |
348 | { "tx_collide_4times" }, | |
349 | { "tx_collide_5times" }, | |
350 | { "tx_collide_6times" }, | |
351 | { "tx_collide_7times" }, | |
352 | { "tx_collide_8times" }, | |
353 | { "tx_collide_9times" }, | |
354 | { "tx_collide_10times" }, | |
355 | { "tx_collide_11times" }, | |
356 | { "tx_collide_12times" }, | |
357 | { "tx_collide_13times" }, | |
358 | { "tx_collide_14times" }, | |
359 | { "tx_collide_15times" }, | |
360 | { "tx_ucast_packets" }, | |
361 | { "tx_mcast_packets" }, | |
362 | { "tx_bcast_packets" }, | |
363 | { "tx_carrier_sense_errors" }, | |
364 | { "tx_discards" }, | |
365 | { "tx_errors" }, | |
366 | ||
367 | { "dma_writeq_full" }, | |
368 | { "dma_write_prioq_full" }, | |
369 | { "rxbds_empty" }, | |
370 | { "rx_discards" }, | |
371 | { "rx_errors" }, | |
372 | { "rx_threshold_hit" }, | |
373 | ||
374 | { "dma_readq_full" }, | |
375 | { "dma_read_prioq_full" }, | |
376 | { "tx_comp_queue_full" }, | |
377 | ||
378 | { "ring_set_send_prod_index" }, | |
379 | { "ring_status_update" }, | |
380 | { "nic_irqs" }, | |
381 | { "nic_avoided_irqs" }, | |
4452d099 MC |
382 | { "nic_tx_threshold_hit" }, |
383 | ||
384 | { "mbuf_lwm_thresh_hit" }, | |
1da177e4 LT |
385 | }; |
386 | ||
48fa55a0 MC |
387 | #define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys) |
388 | ||
389 | ||
50da859d | 390 | static const struct { |
4cafd3f5 | 391 | const char string[ETH_GSTRING_LEN]; |
48fa55a0 | 392 | } ethtool_test_keys[] = { |
4cafd3f5 MC |
393 | { "nvram test (online) " }, |
394 | { "link test (online) " }, | |
395 | { "register test (offline)" }, | |
396 | { "memory test (offline)" }, | |
397 | { "loopback test (offline)" }, | |
398 | { "interrupt test (offline)" }, | |
399 | }; | |
400 | ||
48fa55a0 MC |
401 | #define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys) |
402 | ||
403 | ||
b401e9e2 MC |
404 | static void tg3_write32(struct tg3 *tp, u32 off, u32 val) |
405 | { | |
406 | writel(val, tp->regs + off); | |
407 | } | |
408 | ||
409 | static u32 tg3_read32(struct tg3 *tp, u32 off) | |
410 | { | |
de6f31eb | 411 | return readl(tp->regs + off); |
b401e9e2 MC |
412 | } |
413 | ||
0d3031d9 MC |
414 | static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val) |
415 | { | |
416 | writel(val, tp->aperegs + off); | |
417 | } | |
418 | ||
419 | static u32 tg3_ape_read32(struct tg3 *tp, u32 off) | |
420 | { | |
de6f31eb | 421 | return readl(tp->aperegs + off); |
0d3031d9 MC |
422 | } |
423 | ||
1da177e4 LT |
424 | static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val) |
425 | { | |
6892914f MC |
426 | unsigned long flags; |
427 | ||
428 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
1ee582d8 MC |
429 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); |
430 | pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); | |
6892914f | 431 | spin_unlock_irqrestore(&tp->indirect_lock, flags); |
1ee582d8 MC |
432 | } |
433 | ||
434 | static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val) | |
435 | { | |
436 | writel(val, tp->regs + off); | |
437 | readl(tp->regs + off); | |
1da177e4 LT |
438 | } |
439 | ||
6892914f | 440 | static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off) |
1da177e4 | 441 | { |
6892914f MC |
442 | unsigned long flags; |
443 | u32 val; | |
444 | ||
445 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
446 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); | |
447 | pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); | |
448 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
449 | return val; | |
450 | } | |
451 | ||
452 | static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val) | |
453 | { | |
454 | unsigned long flags; | |
455 | ||
456 | if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) { | |
457 | pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX + | |
458 | TG3_64BIT_REG_LOW, val); | |
459 | return; | |
460 | } | |
66711e66 | 461 | if (off == TG3_RX_STD_PROD_IDX_REG) { |
6892914f MC |
462 | pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX + |
463 | TG3_64BIT_REG_LOW, val); | |
464 | return; | |
1da177e4 | 465 | } |
6892914f MC |
466 | |
467 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
468 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); | |
469 | pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); | |
470 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
471 | ||
472 | /* In indirect mode when disabling interrupts, we also need | |
473 | * to clear the interrupt bit in the GRC local ctrl register. | |
474 | */ | |
475 | if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) && | |
476 | (val == 0x1)) { | |
477 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL, | |
478 | tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT); | |
479 | } | |
480 | } | |
481 | ||
482 | static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off) | |
483 | { | |
484 | unsigned long flags; | |
485 | u32 val; | |
486 | ||
487 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
488 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); | |
489 | pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); | |
490 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
491 | return val; | |
492 | } | |
493 | ||
b401e9e2 MC |
494 | /* usec_wait specifies the wait time in usec when writing to certain registers |
495 | * where it is unsafe to read back the register without some delay. | |
496 | * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power. | |
497 | * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed. | |
498 | */ | |
499 | static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait) | |
6892914f | 500 | { |
63c3a66f | 501 | if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND)) |
b401e9e2 MC |
502 | /* Non-posted methods */ |
503 | tp->write32(tp, off, val); | |
504 | else { | |
505 | /* Posted method */ | |
506 | tg3_write32(tp, off, val); | |
507 | if (usec_wait) | |
508 | udelay(usec_wait); | |
509 | tp->read32(tp, off); | |
510 | } | |
511 | /* Wait again after the read for the posted method to guarantee that | |
512 | * the wait time is met. | |
513 | */ | |
514 | if (usec_wait) | |
515 | udelay(usec_wait); | |
1da177e4 LT |
516 | } |
517 | ||
09ee929c MC |
518 | static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val) |
519 | { | |
520 | tp->write32_mbox(tp, off, val); | |
63c3a66f | 521 | if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND)) |
6892914f | 522 | tp->read32_mbox(tp, off); |
09ee929c MC |
523 | } |
524 | ||
20094930 | 525 | static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val) |
1da177e4 LT |
526 | { |
527 | void __iomem *mbox = tp->regs + off; | |
528 | writel(val, mbox); | |
63c3a66f | 529 | if (tg3_flag(tp, TXD_MBOX_HWBUG)) |
1da177e4 | 530 | writel(val, mbox); |
63c3a66f | 531 | if (tg3_flag(tp, MBOX_WRITE_REORDER)) |
1da177e4 LT |
532 | readl(mbox); |
533 | } | |
534 | ||
b5d3772c MC |
535 | static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off) |
536 | { | |
de6f31eb | 537 | return readl(tp->regs + off + GRCMBOX_BASE); |
b5d3772c MC |
538 | } |
539 | ||
540 | static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val) | |
541 | { | |
542 | writel(val, tp->regs + off + GRCMBOX_BASE); | |
543 | } | |
544 | ||
c6cdf436 | 545 | #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val) |
09ee929c | 546 | #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val)) |
c6cdf436 MC |
547 | #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val) |
548 | #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val) | |
549 | #define tr32_mailbox(reg) tp->read32_mbox(tp, reg) | |
20094930 | 550 | |
c6cdf436 MC |
551 | #define tw32(reg, val) tp->write32(tp, reg, val) |
552 | #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0) | |
553 | #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us)) | |
554 | #define tr32(reg) tp->read32(tp, reg) | |
1da177e4 LT |
555 | |
556 | static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val) | |
557 | { | |
6892914f MC |
558 | unsigned long flags; |
559 | ||
6ff6f81d | 560 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 && |
b5d3772c MC |
561 | (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) |
562 | return; | |
563 | ||
6892914f | 564 | spin_lock_irqsave(&tp->indirect_lock, flags); |
63c3a66f | 565 | if (tg3_flag(tp, SRAM_USE_CONFIG)) { |
bbadf503 MC |
566 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); |
567 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
1da177e4 | 568 | |
bbadf503 MC |
569 | /* Always leave this as zero. */ |
570 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
571 | } else { | |
572 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off); | |
573 | tw32_f(TG3PCI_MEM_WIN_DATA, val); | |
28fbef78 | 574 | |
bbadf503 MC |
575 | /* Always leave this as zero. */ |
576 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
577 | } | |
578 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
758a6139 DM |
579 | } |
580 | ||
1da177e4 LT |
581 | static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val) |
582 | { | |
6892914f MC |
583 | unsigned long flags; |
584 | ||
6ff6f81d | 585 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 && |
b5d3772c MC |
586 | (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) { |
587 | *val = 0; | |
588 | return; | |
589 | } | |
590 | ||
6892914f | 591 | spin_lock_irqsave(&tp->indirect_lock, flags); |
63c3a66f | 592 | if (tg3_flag(tp, SRAM_USE_CONFIG)) { |
bbadf503 MC |
593 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); |
594 | pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
1da177e4 | 595 | |
bbadf503 MC |
596 | /* Always leave this as zero. */ |
597 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
598 | } else { | |
599 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off); | |
600 | *val = tr32(TG3PCI_MEM_WIN_DATA); | |
601 | ||
602 | /* Always leave this as zero. */ | |
603 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
604 | } | |
6892914f | 605 | spin_unlock_irqrestore(&tp->indirect_lock, flags); |
1da177e4 LT |
606 | } |
607 | ||
0d3031d9 MC |
608 | static void tg3_ape_lock_init(struct tg3 *tp) |
609 | { | |
610 | int i; | |
6f5c8f83 | 611 | u32 regbase, bit; |
f92d9dc1 MC |
612 | |
613 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | |
614 | regbase = TG3_APE_LOCK_GRANT; | |
615 | else | |
616 | regbase = TG3_APE_PER_LOCK_GRANT; | |
0d3031d9 MC |
617 | |
618 | /* Make sure the driver hasn't any stale locks. */ | |
6f5c8f83 MC |
619 | for (i = 0; i < 8; i++) { |
620 | if (i == TG3_APE_LOCK_GPIO) | |
621 | continue; | |
f92d9dc1 | 622 | tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER); |
6f5c8f83 MC |
623 | } |
624 | ||
625 | /* Clear the correct bit of the GPIO lock too. */ | |
626 | if (!tp->pci_fn) | |
627 | bit = APE_LOCK_GRANT_DRIVER; | |
628 | else | |
629 | bit = 1 << tp->pci_fn; | |
630 | ||
631 | tg3_ape_write32(tp, regbase + 4 * TG3_APE_LOCK_GPIO, bit); | |
0d3031d9 MC |
632 | } |
633 | ||
634 | static int tg3_ape_lock(struct tg3 *tp, int locknum) | |
635 | { | |
636 | int i, off; | |
637 | int ret = 0; | |
6f5c8f83 | 638 | u32 status, req, gnt, bit; |
0d3031d9 | 639 | |
63c3a66f | 640 | if (!tg3_flag(tp, ENABLE_APE)) |
0d3031d9 MC |
641 | return 0; |
642 | ||
643 | switch (locknum) { | |
6f5c8f83 MC |
644 | case TG3_APE_LOCK_GPIO: |
645 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | |
646 | return 0; | |
33f401ae MC |
647 | case TG3_APE_LOCK_GRC: |
648 | case TG3_APE_LOCK_MEM: | |
649 | break; | |
650 | default: | |
651 | return -EINVAL; | |
0d3031d9 MC |
652 | } |
653 | ||
f92d9dc1 MC |
654 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) { |
655 | req = TG3_APE_LOCK_REQ; | |
656 | gnt = TG3_APE_LOCK_GRANT; | |
657 | } else { | |
658 | req = TG3_APE_PER_LOCK_REQ; | |
659 | gnt = TG3_APE_PER_LOCK_GRANT; | |
660 | } | |
661 | ||
0d3031d9 MC |
662 | off = 4 * locknum; |
663 | ||
6f5c8f83 MC |
664 | if (locknum != TG3_APE_LOCK_GPIO || !tp->pci_fn) |
665 | bit = APE_LOCK_REQ_DRIVER; | |
666 | else | |
667 | bit = 1 << tp->pci_fn; | |
668 | ||
669 | tg3_ape_write32(tp, req + off, bit); | |
0d3031d9 MC |
670 | |
671 | /* Wait for up to 1 millisecond to acquire lock. */ | |
672 | for (i = 0; i < 100; i++) { | |
f92d9dc1 | 673 | status = tg3_ape_read32(tp, gnt + off); |
6f5c8f83 | 674 | if (status == bit) |
0d3031d9 MC |
675 | break; |
676 | udelay(10); | |
677 | } | |
678 | ||
6f5c8f83 | 679 | if (status != bit) { |
0d3031d9 | 680 | /* Revoke the lock request. */ |
6f5c8f83 | 681 | tg3_ape_write32(tp, gnt + off, bit); |
0d3031d9 MC |
682 | ret = -EBUSY; |
683 | } | |
684 | ||
685 | return ret; | |
686 | } | |
687 | ||
688 | static void tg3_ape_unlock(struct tg3 *tp, int locknum) | |
689 | { | |
6f5c8f83 | 690 | u32 gnt, bit; |
0d3031d9 | 691 | |
63c3a66f | 692 | if (!tg3_flag(tp, ENABLE_APE)) |
0d3031d9 MC |
693 | return; |
694 | ||
695 | switch (locknum) { | |
6f5c8f83 MC |
696 | case TG3_APE_LOCK_GPIO: |
697 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | |
698 | return; | |
33f401ae MC |
699 | case TG3_APE_LOCK_GRC: |
700 | case TG3_APE_LOCK_MEM: | |
701 | break; | |
702 | default: | |
703 | return; | |
0d3031d9 MC |
704 | } |
705 | ||
f92d9dc1 MC |
706 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) |
707 | gnt = TG3_APE_LOCK_GRANT; | |
708 | else | |
709 | gnt = TG3_APE_PER_LOCK_GRANT; | |
710 | ||
6f5c8f83 MC |
711 | if (locknum != TG3_APE_LOCK_GPIO || !tp->pci_fn) |
712 | bit = APE_LOCK_GRANT_DRIVER; | |
713 | else | |
714 | bit = 1 << tp->pci_fn; | |
715 | ||
716 | tg3_ape_write32(tp, gnt + 4 * locknum, bit); | |
0d3031d9 MC |
717 | } |
718 | ||
1da177e4 LT |
719 | static void tg3_disable_ints(struct tg3 *tp) |
720 | { | |
89aeb3bc MC |
721 | int i; |
722 | ||
1da177e4 LT |
723 | tw32(TG3PCI_MISC_HOST_CTRL, |
724 | (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT)); | |
89aeb3bc MC |
725 | for (i = 0; i < tp->irq_max; i++) |
726 | tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001); | |
1da177e4 LT |
727 | } |
728 | ||
1da177e4 LT |
729 | static void tg3_enable_ints(struct tg3 *tp) |
730 | { | |
89aeb3bc | 731 | int i; |
89aeb3bc | 732 | |
bbe832c0 MC |
733 | tp->irq_sync = 0; |
734 | wmb(); | |
735 | ||
1da177e4 LT |
736 | tw32(TG3PCI_MISC_HOST_CTRL, |
737 | (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT)); | |
89aeb3bc | 738 | |
f89f38b8 | 739 | tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE; |
89aeb3bc MC |
740 | for (i = 0; i < tp->irq_cnt; i++) { |
741 | struct tg3_napi *tnapi = &tp->napi[i]; | |
c6cdf436 | 742 | |
898a56f8 | 743 | tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); |
63c3a66f | 744 | if (tg3_flag(tp, 1SHOT_MSI)) |
89aeb3bc | 745 | tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); |
f19af9c2 | 746 | |
f89f38b8 | 747 | tp->coal_now |= tnapi->coal_now; |
89aeb3bc | 748 | } |
f19af9c2 MC |
749 | |
750 | /* Force an initial interrupt */ | |
63c3a66f | 751 | if (!tg3_flag(tp, TAGGED_STATUS) && |
f19af9c2 MC |
752 | (tp->napi[0].hw_status->status & SD_STATUS_UPDATED)) |
753 | tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); | |
754 | else | |
f89f38b8 MC |
755 | tw32(HOSTCC_MODE, tp->coal_now); |
756 | ||
757 | tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now); | |
1da177e4 LT |
758 | } |
759 | ||
17375d25 | 760 | static inline unsigned int tg3_has_work(struct tg3_napi *tnapi) |
04237ddd | 761 | { |
17375d25 | 762 | struct tg3 *tp = tnapi->tp; |
898a56f8 | 763 | struct tg3_hw_status *sblk = tnapi->hw_status; |
04237ddd MC |
764 | unsigned int work_exists = 0; |
765 | ||
766 | /* check for phy events */ | |
63c3a66f | 767 | if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) { |
04237ddd MC |
768 | if (sblk->status & SD_STATUS_LINK_CHG) |
769 | work_exists = 1; | |
770 | } | |
771 | /* check for RX/TX work to do */ | |
f3f3f27e | 772 | if (sblk->idx[0].tx_consumer != tnapi->tx_cons || |
8d9d7cfc | 773 | *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr) |
04237ddd MC |
774 | work_exists = 1; |
775 | ||
776 | return work_exists; | |
777 | } | |
778 | ||
17375d25 | 779 | /* tg3_int_reenable |
04237ddd MC |
780 | * similar to tg3_enable_ints, but it accurately determines whether there |
781 | * is new work pending and can return without flushing the PIO write | |
6aa20a22 | 782 | * which reenables interrupts |
1da177e4 | 783 | */ |
17375d25 | 784 | static void tg3_int_reenable(struct tg3_napi *tnapi) |
1da177e4 | 785 | { |
17375d25 MC |
786 | struct tg3 *tp = tnapi->tp; |
787 | ||
898a56f8 | 788 | tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); |
1da177e4 LT |
789 | mmiowb(); |
790 | ||
fac9b83e DM |
791 | /* When doing tagged status, this work check is unnecessary. |
792 | * The last_tag we write above tells the chip which piece of | |
793 | * work we've completed. | |
794 | */ | |
63c3a66f | 795 | if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi)) |
04237ddd | 796 | tw32(HOSTCC_MODE, tp->coalesce_mode | |
fd2ce37f | 797 | HOSTCC_MODE_ENABLE | tnapi->coal_now); |
1da177e4 LT |
798 | } |
799 | ||
1da177e4 LT |
800 | static void tg3_switch_clocks(struct tg3 *tp) |
801 | { | |
f6eb9b1f | 802 | u32 clock_ctrl; |
1da177e4 LT |
803 | u32 orig_clock_ctrl; |
804 | ||
63c3a66f | 805 | if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS)) |
4cf78e4f MC |
806 | return; |
807 | ||
f6eb9b1f MC |
808 | clock_ctrl = tr32(TG3PCI_CLOCK_CTRL); |
809 | ||
1da177e4 LT |
810 | orig_clock_ctrl = clock_ctrl; |
811 | clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN | | |
812 | CLOCK_CTRL_CLKRUN_OENABLE | | |
813 | 0x1f); | |
814 | tp->pci_clock_ctrl = clock_ctrl; | |
815 | ||
63c3a66f | 816 | if (tg3_flag(tp, 5705_PLUS)) { |
1da177e4 | 817 | if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) { |
b401e9e2 MC |
818 | tw32_wait_f(TG3PCI_CLOCK_CTRL, |
819 | clock_ctrl | CLOCK_CTRL_625_CORE, 40); | |
1da177e4 LT |
820 | } |
821 | } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) { | |
b401e9e2 MC |
822 | tw32_wait_f(TG3PCI_CLOCK_CTRL, |
823 | clock_ctrl | | |
824 | (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK), | |
825 | 40); | |
826 | tw32_wait_f(TG3PCI_CLOCK_CTRL, | |
827 | clock_ctrl | (CLOCK_CTRL_ALTCLK), | |
828 | 40); | |
1da177e4 | 829 | } |
b401e9e2 | 830 | tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40); |
1da177e4 LT |
831 | } |
832 | ||
833 | #define PHY_BUSY_LOOPS 5000 | |
834 | ||
835 | static int tg3_readphy(struct tg3 *tp, int reg, u32 *val) | |
836 | { | |
837 | u32 frame_val; | |
838 | unsigned int loops; | |
839 | int ret; | |
840 | ||
841 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
842 | tw32_f(MAC_MI_MODE, | |
843 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
844 | udelay(80); | |
845 | } | |
846 | ||
847 | *val = 0x0; | |
848 | ||
882e9793 | 849 | frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) & |
1da177e4 LT |
850 | MI_COM_PHY_ADDR_MASK); |
851 | frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & | |
852 | MI_COM_REG_ADDR_MASK); | |
853 | frame_val |= (MI_COM_CMD_READ | MI_COM_START); | |
6aa20a22 | 854 | |
1da177e4 LT |
855 | tw32_f(MAC_MI_COM, frame_val); |
856 | ||
857 | loops = PHY_BUSY_LOOPS; | |
858 | while (loops != 0) { | |
859 | udelay(10); | |
860 | frame_val = tr32(MAC_MI_COM); | |
861 | ||
862 | if ((frame_val & MI_COM_BUSY) == 0) { | |
863 | udelay(5); | |
864 | frame_val = tr32(MAC_MI_COM); | |
865 | break; | |
866 | } | |
867 | loops -= 1; | |
868 | } | |
869 | ||
870 | ret = -EBUSY; | |
871 | if (loops != 0) { | |
872 | *val = frame_val & MI_COM_DATA_MASK; | |
873 | ret = 0; | |
874 | } | |
875 | ||
876 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
877 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
878 | udelay(80); | |
879 | } | |
880 | ||
881 | return ret; | |
882 | } | |
883 | ||
884 | static int tg3_writephy(struct tg3 *tp, int reg, u32 val) | |
885 | { | |
886 | u32 frame_val; | |
887 | unsigned int loops; | |
888 | int ret; | |
889 | ||
f07e9af3 | 890 | if ((tp->phy_flags & TG3_PHYFLG_IS_FET) && |
221c5637 | 891 | (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL)) |
b5d3772c MC |
892 | return 0; |
893 | ||
1da177e4 LT |
894 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { |
895 | tw32_f(MAC_MI_MODE, | |
896 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
897 | udelay(80); | |
898 | } | |
899 | ||
882e9793 | 900 | frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) & |
1da177e4 LT |
901 | MI_COM_PHY_ADDR_MASK); |
902 | frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & | |
903 | MI_COM_REG_ADDR_MASK); | |
904 | frame_val |= (val & MI_COM_DATA_MASK); | |
905 | frame_val |= (MI_COM_CMD_WRITE | MI_COM_START); | |
6aa20a22 | 906 | |
1da177e4 LT |
907 | tw32_f(MAC_MI_COM, frame_val); |
908 | ||
909 | loops = PHY_BUSY_LOOPS; | |
910 | while (loops != 0) { | |
911 | udelay(10); | |
912 | frame_val = tr32(MAC_MI_COM); | |
913 | if ((frame_val & MI_COM_BUSY) == 0) { | |
914 | udelay(5); | |
915 | frame_val = tr32(MAC_MI_COM); | |
916 | break; | |
917 | } | |
918 | loops -= 1; | |
919 | } | |
920 | ||
921 | ret = -EBUSY; | |
922 | if (loops != 0) | |
923 | ret = 0; | |
924 | ||
925 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
926 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
927 | udelay(80); | |
928 | } | |
929 | ||
930 | return ret; | |
931 | } | |
932 | ||
b0988c15 MC |
933 | static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val) |
934 | { | |
935 | int err; | |
936 | ||
937 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad); | |
938 | if (err) | |
939 | goto done; | |
940 | ||
941 | err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr); | |
942 | if (err) | |
943 | goto done; | |
944 | ||
945 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, | |
946 | MII_TG3_MMD_CTRL_DATA_NOINC | devad); | |
947 | if (err) | |
948 | goto done; | |
949 | ||
950 | err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val); | |
951 | ||
952 | done: | |
953 | return err; | |
954 | } | |
955 | ||
956 | static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val) | |
957 | { | |
958 | int err; | |
959 | ||
960 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad); | |
961 | if (err) | |
962 | goto done; | |
963 | ||
964 | err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr); | |
965 | if (err) | |
966 | goto done; | |
967 | ||
968 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, | |
969 | MII_TG3_MMD_CTRL_DATA_NOINC | devad); | |
970 | if (err) | |
971 | goto done; | |
972 | ||
973 | err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val); | |
974 | ||
975 | done: | |
976 | return err; | |
977 | } | |
978 | ||
979 | static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val) | |
980 | { | |
981 | int err; | |
982 | ||
983 | err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); | |
984 | if (!err) | |
985 | err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val); | |
986 | ||
987 | return err; | |
988 | } | |
989 | ||
990 | static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val) | |
991 | { | |
992 | int err; | |
993 | ||
994 | err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); | |
995 | if (!err) | |
996 | err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val); | |
997 | ||
998 | return err; | |
999 | } | |
1000 | ||
15ee95c3 MC |
1001 | static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val) |
1002 | { | |
1003 | int err; | |
1004 | ||
1005 | err = tg3_writephy(tp, MII_TG3_AUX_CTRL, | |
1006 | (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) | | |
1007 | MII_TG3_AUXCTL_SHDWSEL_MISC); | |
1008 | if (!err) | |
1009 | err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val); | |
1010 | ||
1011 | return err; | |
1012 | } | |
1013 | ||
b4bd2929 MC |
1014 | static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set) |
1015 | { | |
1016 | if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC) | |
1017 | set |= MII_TG3_AUXCTL_MISC_WREN; | |
1018 | ||
1019 | return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg); | |
1020 | } | |
1021 | ||
1d36ba45 MC |
1022 | #define TG3_PHY_AUXCTL_SMDSP_ENABLE(tp) \ |
1023 | tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \ | |
1024 | MII_TG3_AUXCTL_ACTL_SMDSP_ENA | \ | |
1025 | MII_TG3_AUXCTL_ACTL_TX_6DB) | |
1026 | ||
1027 | #define TG3_PHY_AUXCTL_SMDSP_DISABLE(tp) \ | |
1028 | tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \ | |
1029 | MII_TG3_AUXCTL_ACTL_TX_6DB); | |
1030 | ||
95e2869a MC |
1031 | static int tg3_bmcr_reset(struct tg3 *tp) |
1032 | { | |
1033 | u32 phy_control; | |
1034 | int limit, err; | |
1035 | ||
1036 | /* OK, reset it, and poll the BMCR_RESET bit until it | |
1037 | * clears or we time out. | |
1038 | */ | |
1039 | phy_control = BMCR_RESET; | |
1040 | err = tg3_writephy(tp, MII_BMCR, phy_control); | |
1041 | if (err != 0) | |
1042 | return -EBUSY; | |
1043 | ||
1044 | limit = 5000; | |
1045 | while (limit--) { | |
1046 | err = tg3_readphy(tp, MII_BMCR, &phy_control); | |
1047 | if (err != 0) | |
1048 | return -EBUSY; | |
1049 | ||
1050 | if ((phy_control & BMCR_RESET) == 0) { | |
1051 | udelay(40); | |
1052 | break; | |
1053 | } | |
1054 | udelay(10); | |
1055 | } | |
d4675b52 | 1056 | if (limit < 0) |
95e2869a MC |
1057 | return -EBUSY; |
1058 | ||
1059 | return 0; | |
1060 | } | |
1061 | ||
158d7abd MC |
1062 | static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg) |
1063 | { | |
3d16543d | 1064 | struct tg3 *tp = bp->priv; |
158d7abd MC |
1065 | u32 val; |
1066 | ||
24bb4fb6 | 1067 | spin_lock_bh(&tp->lock); |
158d7abd MC |
1068 | |
1069 | if (tg3_readphy(tp, reg, &val)) | |
24bb4fb6 MC |
1070 | val = -EIO; |
1071 | ||
1072 | spin_unlock_bh(&tp->lock); | |
158d7abd MC |
1073 | |
1074 | return val; | |
1075 | } | |
1076 | ||
1077 | static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val) | |
1078 | { | |
3d16543d | 1079 | struct tg3 *tp = bp->priv; |
24bb4fb6 | 1080 | u32 ret = 0; |
158d7abd | 1081 | |
24bb4fb6 | 1082 | spin_lock_bh(&tp->lock); |
158d7abd MC |
1083 | |
1084 | if (tg3_writephy(tp, reg, val)) | |
24bb4fb6 | 1085 | ret = -EIO; |
158d7abd | 1086 | |
24bb4fb6 MC |
1087 | spin_unlock_bh(&tp->lock); |
1088 | ||
1089 | return ret; | |
158d7abd MC |
1090 | } |
1091 | ||
1092 | static int tg3_mdio_reset(struct mii_bus *bp) | |
1093 | { | |
1094 | return 0; | |
1095 | } | |
1096 | ||
9c61d6bc | 1097 | static void tg3_mdio_config_5785(struct tg3 *tp) |
a9daf367 MC |
1098 | { |
1099 | u32 val; | |
fcb389df | 1100 | struct phy_device *phydev; |
a9daf367 | 1101 | |
3f0e3ad7 | 1102 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
fcb389df | 1103 | switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { |
6a443a0f MC |
1104 | case PHY_ID_BCM50610: |
1105 | case PHY_ID_BCM50610M: | |
fcb389df MC |
1106 | val = MAC_PHYCFG2_50610_LED_MODES; |
1107 | break; | |
6a443a0f | 1108 | case PHY_ID_BCMAC131: |
fcb389df MC |
1109 | val = MAC_PHYCFG2_AC131_LED_MODES; |
1110 | break; | |
6a443a0f | 1111 | case PHY_ID_RTL8211C: |
fcb389df MC |
1112 | val = MAC_PHYCFG2_RTL8211C_LED_MODES; |
1113 | break; | |
6a443a0f | 1114 | case PHY_ID_RTL8201E: |
fcb389df MC |
1115 | val = MAC_PHYCFG2_RTL8201E_LED_MODES; |
1116 | break; | |
1117 | default: | |
a9daf367 | 1118 | return; |
fcb389df MC |
1119 | } |
1120 | ||
1121 | if (phydev->interface != PHY_INTERFACE_MODE_RGMII) { | |
1122 | tw32(MAC_PHYCFG2, val); | |
1123 | ||
1124 | val = tr32(MAC_PHYCFG1); | |
bb85fbb6 MC |
1125 | val &= ~(MAC_PHYCFG1_RGMII_INT | |
1126 | MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK); | |
1127 | val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT; | |
fcb389df MC |
1128 | tw32(MAC_PHYCFG1, val); |
1129 | ||
1130 | return; | |
1131 | } | |
1132 | ||
63c3a66f | 1133 | if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) |
fcb389df MC |
1134 | val |= MAC_PHYCFG2_EMODE_MASK_MASK | |
1135 | MAC_PHYCFG2_FMODE_MASK_MASK | | |
1136 | MAC_PHYCFG2_GMODE_MASK_MASK | | |
1137 | MAC_PHYCFG2_ACT_MASK_MASK | | |
1138 | MAC_PHYCFG2_QUAL_MASK_MASK | | |
1139 | MAC_PHYCFG2_INBAND_ENABLE; | |
1140 | ||
1141 | tw32(MAC_PHYCFG2, val); | |
a9daf367 | 1142 | |
bb85fbb6 MC |
1143 | val = tr32(MAC_PHYCFG1); |
1144 | val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK | | |
1145 | MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN); | |
63c3a66f JP |
1146 | if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) { |
1147 | if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN)) | |
a9daf367 | 1148 | val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC; |
63c3a66f | 1149 | if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN)) |
a9daf367 MC |
1150 | val |= MAC_PHYCFG1_RGMII_SND_STAT_EN; |
1151 | } | |
bb85fbb6 MC |
1152 | val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT | |
1153 | MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV; | |
1154 | tw32(MAC_PHYCFG1, val); | |
a9daf367 | 1155 | |
a9daf367 MC |
1156 | val = tr32(MAC_EXT_RGMII_MODE); |
1157 | val &= ~(MAC_RGMII_MODE_RX_INT_B | | |
1158 | MAC_RGMII_MODE_RX_QUALITY | | |
1159 | MAC_RGMII_MODE_RX_ACTIVITY | | |
1160 | MAC_RGMII_MODE_RX_ENG_DET | | |
1161 | MAC_RGMII_MODE_TX_ENABLE | | |
1162 | MAC_RGMII_MODE_TX_LOWPWR | | |
1163 | MAC_RGMII_MODE_TX_RESET); | |
63c3a66f JP |
1164 | if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) { |
1165 | if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN)) | |
a9daf367 MC |
1166 | val |= MAC_RGMII_MODE_RX_INT_B | |
1167 | MAC_RGMII_MODE_RX_QUALITY | | |
1168 | MAC_RGMII_MODE_RX_ACTIVITY | | |
1169 | MAC_RGMII_MODE_RX_ENG_DET; | |
63c3a66f | 1170 | if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN)) |
a9daf367 MC |
1171 | val |= MAC_RGMII_MODE_TX_ENABLE | |
1172 | MAC_RGMII_MODE_TX_LOWPWR | | |
1173 | MAC_RGMII_MODE_TX_RESET; | |
1174 | } | |
1175 | tw32(MAC_EXT_RGMII_MODE, val); | |
1176 | } | |
1177 | ||
158d7abd MC |
1178 | static void tg3_mdio_start(struct tg3 *tp) |
1179 | { | |
158d7abd MC |
1180 | tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL; |
1181 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
1182 | udelay(80); | |
a9daf367 | 1183 | |
63c3a66f | 1184 | if (tg3_flag(tp, MDIOBUS_INITED) && |
9ea4818d MC |
1185 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) |
1186 | tg3_mdio_config_5785(tp); | |
1187 | } | |
1188 | ||
1189 | static int tg3_mdio_init(struct tg3 *tp) | |
1190 | { | |
1191 | int i; | |
1192 | u32 reg; | |
1193 | struct phy_device *phydev; | |
1194 | ||
63c3a66f | 1195 | if (tg3_flag(tp, 5717_PLUS)) { |
9c7df915 | 1196 | u32 is_serdes; |
882e9793 | 1197 | |
69f11c99 | 1198 | tp->phy_addr = tp->pci_fn + 1; |
882e9793 | 1199 | |
d1ec96af MC |
1200 | if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) |
1201 | is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES; | |
1202 | else | |
1203 | is_serdes = tr32(TG3_CPMU_PHY_STRAP) & | |
1204 | TG3_CPMU_PHY_STRAP_IS_SERDES; | |
882e9793 MC |
1205 | if (is_serdes) |
1206 | tp->phy_addr += 7; | |
1207 | } else | |
3f0e3ad7 | 1208 | tp->phy_addr = TG3_PHY_MII_ADDR; |
882e9793 | 1209 | |
158d7abd MC |
1210 | tg3_mdio_start(tp); |
1211 | ||
63c3a66f | 1212 | if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED)) |
158d7abd MC |
1213 | return 0; |
1214 | ||
298cf9be LB |
1215 | tp->mdio_bus = mdiobus_alloc(); |
1216 | if (tp->mdio_bus == NULL) | |
1217 | return -ENOMEM; | |
158d7abd | 1218 | |
298cf9be LB |
1219 | tp->mdio_bus->name = "tg3 mdio bus"; |
1220 | snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x", | |
158d7abd | 1221 | (tp->pdev->bus->number << 8) | tp->pdev->devfn); |
298cf9be LB |
1222 | tp->mdio_bus->priv = tp; |
1223 | tp->mdio_bus->parent = &tp->pdev->dev; | |
1224 | tp->mdio_bus->read = &tg3_mdio_read; | |
1225 | tp->mdio_bus->write = &tg3_mdio_write; | |
1226 | tp->mdio_bus->reset = &tg3_mdio_reset; | |
3f0e3ad7 | 1227 | tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR); |
298cf9be | 1228 | tp->mdio_bus->irq = &tp->mdio_irq[0]; |
158d7abd MC |
1229 | |
1230 | for (i = 0; i < PHY_MAX_ADDR; i++) | |
298cf9be | 1231 | tp->mdio_bus->irq[i] = PHY_POLL; |
158d7abd MC |
1232 | |
1233 | /* The bus registration will look for all the PHYs on the mdio bus. | |
1234 | * Unfortunately, it does not ensure the PHY is powered up before | |
1235 | * accessing the PHY ID registers. A chip reset is the | |
1236 | * quickest way to bring the device back to an operational state.. | |
1237 | */ | |
1238 | if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN)) | |
1239 | tg3_bmcr_reset(tp); | |
1240 | ||
298cf9be | 1241 | i = mdiobus_register(tp->mdio_bus); |
a9daf367 | 1242 | if (i) { |
ab96b241 | 1243 | dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i); |
9c61d6bc | 1244 | mdiobus_free(tp->mdio_bus); |
a9daf367 MC |
1245 | return i; |
1246 | } | |
158d7abd | 1247 | |
3f0e3ad7 | 1248 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
a9daf367 | 1249 | |
9c61d6bc | 1250 | if (!phydev || !phydev->drv) { |
ab96b241 | 1251 | dev_warn(&tp->pdev->dev, "No PHY devices\n"); |
9c61d6bc MC |
1252 | mdiobus_unregister(tp->mdio_bus); |
1253 | mdiobus_free(tp->mdio_bus); | |
1254 | return -ENODEV; | |
1255 | } | |
1256 | ||
1257 | switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { | |
6a443a0f | 1258 | case PHY_ID_BCM57780: |
321d32a0 | 1259 | phydev->interface = PHY_INTERFACE_MODE_GMII; |
c704dc23 | 1260 | phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE; |
321d32a0 | 1261 | break; |
6a443a0f MC |
1262 | case PHY_ID_BCM50610: |
1263 | case PHY_ID_BCM50610M: | |
32e5a8d6 | 1264 | phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE | |
c704dc23 | 1265 | PHY_BRCM_RX_REFCLK_UNUSED | |
52fae083 | 1266 | PHY_BRCM_DIS_TXCRXC_NOENRGY | |
c704dc23 | 1267 | PHY_BRCM_AUTO_PWRDWN_ENABLE; |
63c3a66f | 1268 | if (tg3_flag(tp, RGMII_INBAND_DISABLE)) |
a9daf367 | 1269 | phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE; |
63c3a66f | 1270 | if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN)) |
a9daf367 | 1271 | phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE; |
63c3a66f | 1272 | if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN)) |
a9daf367 | 1273 | phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE; |
fcb389df | 1274 | /* fallthru */ |
6a443a0f | 1275 | case PHY_ID_RTL8211C: |
fcb389df | 1276 | phydev->interface = PHY_INTERFACE_MODE_RGMII; |
a9daf367 | 1277 | break; |
6a443a0f MC |
1278 | case PHY_ID_RTL8201E: |
1279 | case PHY_ID_BCMAC131: | |
a9daf367 | 1280 | phydev->interface = PHY_INTERFACE_MODE_MII; |
cdd4e09d | 1281 | phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE; |
f07e9af3 | 1282 | tp->phy_flags |= TG3_PHYFLG_IS_FET; |
a9daf367 MC |
1283 | break; |
1284 | } | |
1285 | ||
63c3a66f | 1286 | tg3_flag_set(tp, MDIOBUS_INITED); |
9c61d6bc MC |
1287 | |
1288 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
1289 | tg3_mdio_config_5785(tp); | |
a9daf367 MC |
1290 | |
1291 | return 0; | |
158d7abd MC |
1292 | } |
1293 | ||
1294 | static void tg3_mdio_fini(struct tg3 *tp) | |
1295 | { | |
63c3a66f JP |
1296 | if (tg3_flag(tp, MDIOBUS_INITED)) { |
1297 | tg3_flag_clear(tp, MDIOBUS_INITED); | |
298cf9be LB |
1298 | mdiobus_unregister(tp->mdio_bus); |
1299 | mdiobus_free(tp->mdio_bus); | |
158d7abd MC |
1300 | } |
1301 | } | |
1302 | ||
4ba526ce MC |
1303 | /* tp->lock is held. */ |
1304 | static inline void tg3_generate_fw_event(struct tg3 *tp) | |
1305 | { | |
1306 | u32 val; | |
1307 | ||
1308 | val = tr32(GRC_RX_CPU_EVENT); | |
1309 | val |= GRC_RX_CPU_DRIVER_EVENT; | |
1310 | tw32_f(GRC_RX_CPU_EVENT, val); | |
1311 | ||
1312 | tp->last_event_jiffies = jiffies; | |
1313 | } | |
1314 | ||
1315 | #define TG3_FW_EVENT_TIMEOUT_USEC 2500 | |
1316 | ||
95e2869a MC |
1317 | /* tp->lock is held. */ |
1318 | static void tg3_wait_for_event_ack(struct tg3 *tp) | |
1319 | { | |
1320 | int i; | |
4ba526ce MC |
1321 | unsigned int delay_cnt; |
1322 | long time_remain; | |
1323 | ||
1324 | /* If enough time has passed, no wait is necessary. */ | |
1325 | time_remain = (long)(tp->last_event_jiffies + 1 + | |
1326 | usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) - | |
1327 | (long)jiffies; | |
1328 | if (time_remain < 0) | |
1329 | return; | |
1330 | ||
1331 | /* Check if we can shorten the wait time. */ | |
1332 | delay_cnt = jiffies_to_usecs(time_remain); | |
1333 | if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC) | |
1334 | delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC; | |
1335 | delay_cnt = (delay_cnt >> 3) + 1; | |
95e2869a | 1336 | |
4ba526ce | 1337 | for (i = 0; i < delay_cnt; i++) { |
95e2869a MC |
1338 | if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT)) |
1339 | break; | |
4ba526ce | 1340 | udelay(8); |
95e2869a MC |
1341 | } |
1342 | } | |
1343 | ||
1344 | /* tp->lock is held. */ | |
1345 | static void tg3_ump_link_report(struct tg3 *tp) | |
1346 | { | |
1347 | u32 reg; | |
1348 | u32 val; | |
1349 | ||
63c3a66f | 1350 | if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF)) |
95e2869a MC |
1351 | return; |
1352 | ||
1353 | tg3_wait_for_event_ack(tp); | |
1354 | ||
1355 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE); | |
1356 | ||
1357 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14); | |
1358 | ||
1359 | val = 0; | |
1360 | if (!tg3_readphy(tp, MII_BMCR, ®)) | |
1361 | val = reg << 16; | |
1362 | if (!tg3_readphy(tp, MII_BMSR, ®)) | |
1363 | val |= (reg & 0xffff); | |
1364 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val); | |
1365 | ||
1366 | val = 0; | |
1367 | if (!tg3_readphy(tp, MII_ADVERTISE, ®)) | |
1368 | val = reg << 16; | |
1369 | if (!tg3_readphy(tp, MII_LPA, ®)) | |
1370 | val |= (reg & 0xffff); | |
1371 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val); | |
1372 | ||
1373 | val = 0; | |
f07e9af3 | 1374 | if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) { |
95e2869a MC |
1375 | if (!tg3_readphy(tp, MII_CTRL1000, ®)) |
1376 | val = reg << 16; | |
1377 | if (!tg3_readphy(tp, MII_STAT1000, ®)) | |
1378 | val |= (reg & 0xffff); | |
1379 | } | |
1380 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val); | |
1381 | ||
1382 | if (!tg3_readphy(tp, MII_PHYADDR, ®)) | |
1383 | val = reg << 16; | |
1384 | else | |
1385 | val = 0; | |
1386 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val); | |
1387 | ||
4ba526ce | 1388 | tg3_generate_fw_event(tp); |
95e2869a MC |
1389 | } |
1390 | ||
1391 | static void tg3_link_report(struct tg3 *tp) | |
1392 | { | |
1393 | if (!netif_carrier_ok(tp->dev)) { | |
05dbe005 | 1394 | netif_info(tp, link, tp->dev, "Link is down\n"); |
95e2869a MC |
1395 | tg3_ump_link_report(tp); |
1396 | } else if (netif_msg_link(tp)) { | |
05dbe005 JP |
1397 | netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n", |
1398 | (tp->link_config.active_speed == SPEED_1000 ? | |
1399 | 1000 : | |
1400 | (tp->link_config.active_speed == SPEED_100 ? | |
1401 | 100 : 10)), | |
1402 | (tp->link_config.active_duplex == DUPLEX_FULL ? | |
1403 | "full" : "half")); | |
1404 | ||
1405 | netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n", | |
1406 | (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ? | |
1407 | "on" : "off", | |
1408 | (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ? | |
1409 | "on" : "off"); | |
47007831 MC |
1410 | |
1411 | if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) | |
1412 | netdev_info(tp->dev, "EEE is %s\n", | |
1413 | tp->setlpicnt ? "enabled" : "disabled"); | |
1414 | ||
95e2869a MC |
1415 | tg3_ump_link_report(tp); |
1416 | } | |
1417 | } | |
1418 | ||
1419 | static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl) | |
1420 | { | |
1421 | u16 miireg; | |
1422 | ||
e18ce346 | 1423 | if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX)) |
95e2869a | 1424 | miireg = ADVERTISE_PAUSE_CAP; |
e18ce346 | 1425 | else if (flow_ctrl & FLOW_CTRL_TX) |
95e2869a | 1426 | miireg = ADVERTISE_PAUSE_ASYM; |
e18ce346 | 1427 | else if (flow_ctrl & FLOW_CTRL_RX) |
95e2869a MC |
1428 | miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
1429 | else | |
1430 | miireg = 0; | |
1431 | ||
1432 | return miireg; | |
1433 | } | |
1434 | ||
1435 | static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl) | |
1436 | { | |
1437 | u16 miireg; | |
1438 | ||
e18ce346 | 1439 | if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX)) |
95e2869a | 1440 | miireg = ADVERTISE_1000XPAUSE; |
e18ce346 | 1441 | else if (flow_ctrl & FLOW_CTRL_TX) |
95e2869a | 1442 | miireg = ADVERTISE_1000XPSE_ASYM; |
e18ce346 | 1443 | else if (flow_ctrl & FLOW_CTRL_RX) |
95e2869a MC |
1444 | miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM; |
1445 | else | |
1446 | miireg = 0; | |
1447 | ||
1448 | return miireg; | |
1449 | } | |
1450 | ||
95e2869a MC |
1451 | static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv) |
1452 | { | |
1453 | u8 cap = 0; | |
1454 | ||
1455 | if (lcladv & ADVERTISE_1000XPAUSE) { | |
1456 | if (lcladv & ADVERTISE_1000XPSE_ASYM) { | |
1457 | if (rmtadv & LPA_1000XPAUSE) | |
e18ce346 | 1458 | cap = FLOW_CTRL_TX | FLOW_CTRL_RX; |
95e2869a | 1459 | else if (rmtadv & LPA_1000XPAUSE_ASYM) |
e18ce346 | 1460 | cap = FLOW_CTRL_RX; |
95e2869a MC |
1461 | } else { |
1462 | if (rmtadv & LPA_1000XPAUSE) | |
e18ce346 | 1463 | cap = FLOW_CTRL_TX | FLOW_CTRL_RX; |
95e2869a MC |
1464 | } |
1465 | } else if (lcladv & ADVERTISE_1000XPSE_ASYM) { | |
1466 | if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM)) | |
e18ce346 | 1467 | cap = FLOW_CTRL_TX; |
95e2869a MC |
1468 | } |
1469 | ||
1470 | return cap; | |
1471 | } | |
1472 | ||
f51f3562 | 1473 | static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv) |
95e2869a | 1474 | { |
b02fd9e3 | 1475 | u8 autoneg; |
f51f3562 | 1476 | u8 flowctrl = 0; |
95e2869a MC |
1477 | u32 old_rx_mode = tp->rx_mode; |
1478 | u32 old_tx_mode = tp->tx_mode; | |
1479 | ||
63c3a66f | 1480 | if (tg3_flag(tp, USE_PHYLIB)) |
3f0e3ad7 | 1481 | autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg; |
b02fd9e3 MC |
1482 | else |
1483 | autoneg = tp->link_config.autoneg; | |
1484 | ||
63c3a66f | 1485 | if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) { |
f07e9af3 | 1486 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) |
f51f3562 | 1487 | flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv); |
95e2869a | 1488 | else |
bc02ff95 | 1489 | flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv); |
f51f3562 MC |
1490 | } else |
1491 | flowctrl = tp->link_config.flowctrl; | |
95e2869a | 1492 | |
f51f3562 | 1493 | tp->link_config.active_flowctrl = flowctrl; |
95e2869a | 1494 | |
e18ce346 | 1495 | if (flowctrl & FLOW_CTRL_RX) |
95e2869a MC |
1496 | tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE; |
1497 | else | |
1498 | tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE; | |
1499 | ||
f51f3562 | 1500 | if (old_rx_mode != tp->rx_mode) |
95e2869a | 1501 | tw32_f(MAC_RX_MODE, tp->rx_mode); |
95e2869a | 1502 | |
e18ce346 | 1503 | if (flowctrl & FLOW_CTRL_TX) |
95e2869a MC |
1504 | tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE; |
1505 | else | |
1506 | tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE; | |
1507 | ||
f51f3562 | 1508 | if (old_tx_mode != tp->tx_mode) |
95e2869a | 1509 | tw32_f(MAC_TX_MODE, tp->tx_mode); |
95e2869a MC |
1510 | } |
1511 | ||
b02fd9e3 MC |
1512 | static void tg3_adjust_link(struct net_device *dev) |
1513 | { | |
1514 | u8 oldflowctrl, linkmesg = 0; | |
1515 | u32 mac_mode, lcl_adv, rmt_adv; | |
1516 | struct tg3 *tp = netdev_priv(dev); | |
3f0e3ad7 | 1517 | struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 | 1518 | |
24bb4fb6 | 1519 | spin_lock_bh(&tp->lock); |
b02fd9e3 MC |
1520 | |
1521 | mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK | | |
1522 | MAC_MODE_HALF_DUPLEX); | |
1523 | ||
1524 | oldflowctrl = tp->link_config.active_flowctrl; | |
1525 | ||
1526 | if (phydev->link) { | |
1527 | lcl_adv = 0; | |
1528 | rmt_adv = 0; | |
1529 | ||
1530 | if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10) | |
1531 | mac_mode |= MAC_MODE_PORT_MODE_MII; | |
c3df0748 MC |
1532 | else if (phydev->speed == SPEED_1000 || |
1533 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) | |
b02fd9e3 | 1534 | mac_mode |= MAC_MODE_PORT_MODE_GMII; |
c3df0748 MC |
1535 | else |
1536 | mac_mode |= MAC_MODE_PORT_MODE_MII; | |
b02fd9e3 MC |
1537 | |
1538 | if (phydev->duplex == DUPLEX_HALF) | |
1539 | mac_mode |= MAC_MODE_HALF_DUPLEX; | |
1540 | else { | |
1541 | lcl_adv = tg3_advert_flowctrl_1000T( | |
1542 | tp->link_config.flowctrl); | |
1543 | ||
1544 | if (phydev->pause) | |
1545 | rmt_adv = LPA_PAUSE_CAP; | |
1546 | if (phydev->asym_pause) | |
1547 | rmt_adv |= LPA_PAUSE_ASYM; | |
1548 | } | |
1549 | ||
1550 | tg3_setup_flow_control(tp, lcl_adv, rmt_adv); | |
1551 | } else | |
1552 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
1553 | ||
1554 | if (mac_mode != tp->mac_mode) { | |
1555 | tp->mac_mode = mac_mode; | |
1556 | tw32_f(MAC_MODE, tp->mac_mode); | |
1557 | udelay(40); | |
1558 | } | |
1559 | ||
fcb389df MC |
1560 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { |
1561 | if (phydev->speed == SPEED_10) | |
1562 | tw32(MAC_MI_STAT, | |
1563 | MAC_MI_STAT_10MBPS_MODE | | |
1564 | MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
1565 | else | |
1566 | tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
1567 | } | |
1568 | ||
b02fd9e3 MC |
1569 | if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF) |
1570 | tw32(MAC_TX_LENGTHS, | |
1571 | ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
1572 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
1573 | (0xff << TX_LENGTHS_SLOT_TIME_SHIFT))); | |
1574 | else | |
1575 | tw32(MAC_TX_LENGTHS, | |
1576 | ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
1577 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
1578 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT))); | |
1579 | ||
1580 | if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) || | |
1581 | (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) || | |
1582 | phydev->speed != tp->link_config.active_speed || | |
1583 | phydev->duplex != tp->link_config.active_duplex || | |
1584 | oldflowctrl != tp->link_config.active_flowctrl) | |
c6cdf436 | 1585 | linkmesg = 1; |
b02fd9e3 MC |
1586 | |
1587 | tp->link_config.active_speed = phydev->speed; | |
1588 | tp->link_config.active_duplex = phydev->duplex; | |
1589 | ||
24bb4fb6 | 1590 | spin_unlock_bh(&tp->lock); |
b02fd9e3 MC |
1591 | |
1592 | if (linkmesg) | |
1593 | tg3_link_report(tp); | |
1594 | } | |
1595 | ||
1596 | static int tg3_phy_init(struct tg3 *tp) | |
1597 | { | |
1598 | struct phy_device *phydev; | |
1599 | ||
f07e9af3 | 1600 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) |
b02fd9e3 MC |
1601 | return 0; |
1602 | ||
1603 | /* Bring the PHY back to a known state. */ | |
1604 | tg3_bmcr_reset(tp); | |
1605 | ||
3f0e3ad7 | 1606 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 MC |
1607 | |
1608 | /* Attach the MAC to the PHY. */ | |
fb28ad35 | 1609 | phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link, |
a9daf367 | 1610 | phydev->dev_flags, phydev->interface); |
b02fd9e3 | 1611 | if (IS_ERR(phydev)) { |
ab96b241 | 1612 | dev_err(&tp->pdev->dev, "Could not attach to PHY\n"); |
b02fd9e3 MC |
1613 | return PTR_ERR(phydev); |
1614 | } | |
1615 | ||
b02fd9e3 | 1616 | /* Mask with MAC supported features. */ |
9c61d6bc MC |
1617 | switch (phydev->interface) { |
1618 | case PHY_INTERFACE_MODE_GMII: | |
1619 | case PHY_INTERFACE_MODE_RGMII: | |
f07e9af3 | 1620 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { |
321d32a0 MC |
1621 | phydev->supported &= (PHY_GBIT_FEATURES | |
1622 | SUPPORTED_Pause | | |
1623 | SUPPORTED_Asym_Pause); | |
1624 | break; | |
1625 | } | |
1626 | /* fallthru */ | |
9c61d6bc MC |
1627 | case PHY_INTERFACE_MODE_MII: |
1628 | phydev->supported &= (PHY_BASIC_FEATURES | | |
1629 | SUPPORTED_Pause | | |
1630 | SUPPORTED_Asym_Pause); | |
1631 | break; | |
1632 | default: | |
3f0e3ad7 | 1633 | phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
9c61d6bc MC |
1634 | return -EINVAL; |
1635 | } | |
1636 | ||
f07e9af3 | 1637 | tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED; |
b02fd9e3 MC |
1638 | |
1639 | phydev->advertising = phydev->supported; | |
1640 | ||
b02fd9e3 MC |
1641 | return 0; |
1642 | } | |
1643 | ||
1644 | static void tg3_phy_start(struct tg3 *tp) | |
1645 | { | |
1646 | struct phy_device *phydev; | |
1647 | ||
f07e9af3 | 1648 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 MC |
1649 | return; |
1650 | ||
3f0e3ad7 | 1651 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 | 1652 | |
80096068 MC |
1653 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { |
1654 | tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; | |
b02fd9e3 MC |
1655 | phydev->speed = tp->link_config.orig_speed; |
1656 | phydev->duplex = tp->link_config.orig_duplex; | |
1657 | phydev->autoneg = tp->link_config.orig_autoneg; | |
1658 | phydev->advertising = tp->link_config.orig_advertising; | |
1659 | } | |
1660 | ||
1661 | phy_start(phydev); | |
1662 | ||
1663 | phy_start_aneg(phydev); | |
1664 | } | |
1665 | ||
1666 | static void tg3_phy_stop(struct tg3 *tp) | |
1667 | { | |
f07e9af3 | 1668 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 MC |
1669 | return; |
1670 | ||
3f0e3ad7 | 1671 | phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
b02fd9e3 MC |
1672 | } |
1673 | ||
1674 | static void tg3_phy_fini(struct tg3 *tp) | |
1675 | { | |
f07e9af3 | 1676 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { |
3f0e3ad7 | 1677 | phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
f07e9af3 | 1678 | tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED; |
b02fd9e3 MC |
1679 | } |
1680 | } | |
1681 | ||
7f97a4bd MC |
1682 | static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable) |
1683 | { | |
1684 | u32 phytest; | |
1685 | ||
1686 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { | |
1687 | u32 phy; | |
1688 | ||
1689 | tg3_writephy(tp, MII_TG3_FET_TEST, | |
1690 | phytest | MII_TG3_FET_SHADOW_EN); | |
1691 | if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) { | |
1692 | if (enable) | |
1693 | phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD; | |
1694 | else | |
1695 | phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD; | |
1696 | tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy); | |
1697 | } | |
1698 | tg3_writephy(tp, MII_TG3_FET_TEST, phytest); | |
1699 | } | |
1700 | } | |
1701 | ||
6833c043 MC |
1702 | static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable) |
1703 | { | |
1704 | u32 reg; | |
1705 | ||
63c3a66f JP |
1706 | if (!tg3_flag(tp, 5705_PLUS) || |
1707 | (tg3_flag(tp, 5717_PLUS) && | |
f07e9af3 | 1708 | (tp->phy_flags & TG3_PHYFLG_MII_SERDES))) |
6833c043 MC |
1709 | return; |
1710 | ||
f07e9af3 | 1711 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
7f97a4bd MC |
1712 | tg3_phy_fet_toggle_apd(tp, enable); |
1713 | return; | |
1714 | } | |
1715 | ||
6833c043 MC |
1716 | reg = MII_TG3_MISC_SHDW_WREN | |
1717 | MII_TG3_MISC_SHDW_SCR5_SEL | | |
1718 | MII_TG3_MISC_SHDW_SCR5_LPED | | |
1719 | MII_TG3_MISC_SHDW_SCR5_DLPTLM | | |
1720 | MII_TG3_MISC_SHDW_SCR5_SDTL | | |
1721 | MII_TG3_MISC_SHDW_SCR5_C125OE; | |
1722 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable) | |
1723 | reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD; | |
1724 | ||
1725 | tg3_writephy(tp, MII_TG3_MISC_SHDW, reg); | |
1726 | ||
1727 | ||
1728 | reg = MII_TG3_MISC_SHDW_WREN | | |
1729 | MII_TG3_MISC_SHDW_APD_SEL | | |
1730 | MII_TG3_MISC_SHDW_APD_WKTM_84MS; | |
1731 | if (enable) | |
1732 | reg |= MII_TG3_MISC_SHDW_APD_ENABLE; | |
1733 | ||
1734 | tg3_writephy(tp, MII_TG3_MISC_SHDW, reg); | |
1735 | } | |
1736 | ||
9ef8ca99 MC |
1737 | static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable) |
1738 | { | |
1739 | u32 phy; | |
1740 | ||
63c3a66f | 1741 | if (!tg3_flag(tp, 5705_PLUS) || |
f07e9af3 | 1742 | (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) |
9ef8ca99 MC |
1743 | return; |
1744 | ||
f07e9af3 | 1745 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
9ef8ca99 MC |
1746 | u32 ephy; |
1747 | ||
535ef6e1 MC |
1748 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) { |
1749 | u32 reg = MII_TG3_FET_SHDW_MISCCTRL; | |
1750 | ||
1751 | tg3_writephy(tp, MII_TG3_FET_TEST, | |
1752 | ephy | MII_TG3_FET_SHADOW_EN); | |
1753 | if (!tg3_readphy(tp, reg, &phy)) { | |
9ef8ca99 | 1754 | if (enable) |
535ef6e1 | 1755 | phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX; |
9ef8ca99 | 1756 | else |
535ef6e1 MC |
1757 | phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX; |
1758 | tg3_writephy(tp, reg, phy); | |
9ef8ca99 | 1759 | } |
535ef6e1 | 1760 | tg3_writephy(tp, MII_TG3_FET_TEST, ephy); |
9ef8ca99 MC |
1761 | } |
1762 | } else { | |
15ee95c3 MC |
1763 | int ret; |
1764 | ||
1765 | ret = tg3_phy_auxctl_read(tp, | |
1766 | MII_TG3_AUXCTL_SHDWSEL_MISC, &phy); | |
1767 | if (!ret) { | |
9ef8ca99 MC |
1768 | if (enable) |
1769 | phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX; | |
1770 | else | |
1771 | phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX; | |
b4bd2929 MC |
1772 | tg3_phy_auxctl_write(tp, |
1773 | MII_TG3_AUXCTL_SHDWSEL_MISC, phy); | |
9ef8ca99 MC |
1774 | } |
1775 | } | |
1776 | } | |
1777 | ||
1da177e4 LT |
1778 | static void tg3_phy_set_wirespeed(struct tg3 *tp) |
1779 | { | |
15ee95c3 | 1780 | int ret; |
1da177e4 LT |
1781 | u32 val; |
1782 | ||
f07e9af3 | 1783 | if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) |
1da177e4 LT |
1784 | return; |
1785 | ||
15ee95c3 MC |
1786 | ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val); |
1787 | if (!ret) | |
b4bd2929 MC |
1788 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, |
1789 | val | MII_TG3_AUXCTL_MISC_WIRESPD_EN); | |
1da177e4 LT |
1790 | } |
1791 | ||
b2a5c19c MC |
1792 | static void tg3_phy_apply_otp(struct tg3 *tp) |
1793 | { | |
1794 | u32 otp, phy; | |
1795 | ||
1796 | if (!tp->phy_otp) | |
1797 | return; | |
1798 | ||
1799 | otp = tp->phy_otp; | |
1800 | ||
1d36ba45 MC |
1801 | if (TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) |
1802 | return; | |
b2a5c19c MC |
1803 | |
1804 | phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT); | |
1805 | phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT; | |
1806 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy); | |
1807 | ||
1808 | phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) | | |
1809 | ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT); | |
1810 | tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy); | |
1811 | ||
1812 | phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT); | |
1813 | phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ; | |
1814 | tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy); | |
1815 | ||
1816 | phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT); | |
1817 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy); | |
1818 | ||
1819 | phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT); | |
1820 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy); | |
1821 | ||
1822 | phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) | | |
1823 | ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT); | |
1824 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy); | |
1825 | ||
1d36ba45 | 1826 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); |
b2a5c19c MC |
1827 | } |
1828 | ||
52b02d04 MC |
1829 | static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up) |
1830 | { | |
1831 | u32 val; | |
1832 | ||
1833 | if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) | |
1834 | return; | |
1835 | ||
1836 | tp->setlpicnt = 0; | |
1837 | ||
1838 | if (tp->link_config.autoneg == AUTONEG_ENABLE && | |
1839 | current_link_up == 1 && | |
a6b68dab MC |
1840 | tp->link_config.active_duplex == DUPLEX_FULL && |
1841 | (tp->link_config.active_speed == SPEED_100 || | |
1842 | tp->link_config.active_speed == SPEED_1000)) { | |
52b02d04 MC |
1843 | u32 eeectl; |
1844 | ||
1845 | if (tp->link_config.active_speed == SPEED_1000) | |
1846 | eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US; | |
1847 | else | |
1848 | eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US; | |
1849 | ||
1850 | tw32(TG3_CPMU_EEE_CTRL, eeectl); | |
1851 | ||
3110f5f5 MC |
1852 | tg3_phy_cl45_read(tp, MDIO_MMD_AN, |
1853 | TG3_CL45_D7_EEERES_STAT, &val); | |
52b02d04 | 1854 | |
b0c5943f MC |
1855 | if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T || |
1856 | val == TG3_CL45_D7_EEERES_STAT_LP_100TX) | |
52b02d04 MC |
1857 | tp->setlpicnt = 2; |
1858 | } | |
1859 | ||
1860 | if (!tp->setlpicnt) { | |
1861 | val = tr32(TG3_CPMU_EEE_MODE); | |
1862 | tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE); | |
1863 | } | |
1864 | } | |
1865 | ||
b0c5943f MC |
1866 | static void tg3_phy_eee_enable(struct tg3 *tp) |
1867 | { | |
1868 | u32 val; | |
1869 | ||
1870 | if (tp->link_config.active_speed == SPEED_1000 && | |
1871 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
1872 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
1873 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) && | |
1874 | !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { | |
1875 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0003); | |
1876 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); | |
1877 | } | |
1878 | ||
1879 | val = tr32(TG3_CPMU_EEE_MODE); | |
1880 | tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE); | |
1881 | } | |
1882 | ||
1da177e4 LT |
1883 | static int tg3_wait_macro_done(struct tg3 *tp) |
1884 | { | |
1885 | int limit = 100; | |
1886 | ||
1887 | while (limit--) { | |
1888 | u32 tmp32; | |
1889 | ||
f08aa1a8 | 1890 | if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) { |
1da177e4 LT |
1891 | if ((tmp32 & 0x1000) == 0) |
1892 | break; | |
1893 | } | |
1894 | } | |
d4675b52 | 1895 | if (limit < 0) |
1da177e4 LT |
1896 | return -EBUSY; |
1897 | ||
1898 | return 0; | |
1899 | } | |
1900 | ||
1901 | static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp) | |
1902 | { | |
1903 | static const u32 test_pat[4][6] = { | |
1904 | { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 }, | |
1905 | { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 }, | |
1906 | { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 }, | |
1907 | { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 } | |
1908 | }; | |
1909 | int chan; | |
1910 | ||
1911 | for (chan = 0; chan < 4; chan++) { | |
1912 | int i; | |
1913 | ||
1914 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
1915 | (chan * 0x2000) | 0x0200); | |
f08aa1a8 | 1916 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); |
1da177e4 LT |
1917 | |
1918 | for (i = 0; i < 6; i++) | |
1919 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, | |
1920 | test_pat[chan][i]); | |
1921 | ||
f08aa1a8 | 1922 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); |
1da177e4 LT |
1923 | if (tg3_wait_macro_done(tp)) { |
1924 | *resetp = 1; | |
1925 | return -EBUSY; | |
1926 | } | |
1927 | ||
1928 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
1929 | (chan * 0x2000) | 0x0200); | |
f08aa1a8 | 1930 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082); |
1da177e4 LT |
1931 | if (tg3_wait_macro_done(tp)) { |
1932 | *resetp = 1; | |
1933 | return -EBUSY; | |
1934 | } | |
1935 | ||
f08aa1a8 | 1936 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802); |
1da177e4 LT |
1937 | if (tg3_wait_macro_done(tp)) { |
1938 | *resetp = 1; | |
1939 | return -EBUSY; | |
1940 | } | |
1941 | ||
1942 | for (i = 0; i < 6; i += 2) { | |
1943 | u32 low, high; | |
1944 | ||
1945 | if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) || | |
1946 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) || | |
1947 | tg3_wait_macro_done(tp)) { | |
1948 | *resetp = 1; | |
1949 | return -EBUSY; | |
1950 | } | |
1951 | low &= 0x7fff; | |
1952 | high &= 0x000f; | |
1953 | if (low != test_pat[chan][i] || | |
1954 | high != test_pat[chan][i+1]) { | |
1955 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b); | |
1956 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001); | |
1957 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005); | |
1958 | ||
1959 | return -EBUSY; | |
1960 | } | |
1961 | } | |
1962 | } | |
1963 | ||
1964 | return 0; | |
1965 | } | |
1966 | ||
1967 | static int tg3_phy_reset_chanpat(struct tg3 *tp) | |
1968 | { | |
1969 | int chan; | |
1970 | ||
1971 | for (chan = 0; chan < 4; chan++) { | |
1972 | int i; | |
1973 | ||
1974 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
1975 | (chan * 0x2000) | 0x0200); | |
f08aa1a8 | 1976 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); |
1da177e4 LT |
1977 | for (i = 0; i < 6; i++) |
1978 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000); | |
f08aa1a8 | 1979 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); |
1da177e4 LT |
1980 | if (tg3_wait_macro_done(tp)) |
1981 | return -EBUSY; | |
1982 | } | |
1983 | ||
1984 | return 0; | |
1985 | } | |
1986 | ||
1987 | static int tg3_phy_reset_5703_4_5(struct tg3 *tp) | |
1988 | { | |
1989 | u32 reg32, phy9_orig; | |
1990 | int retries, do_phy_reset, err; | |
1991 | ||
1992 | retries = 10; | |
1993 | do_phy_reset = 1; | |
1994 | do { | |
1995 | if (do_phy_reset) { | |
1996 | err = tg3_bmcr_reset(tp); | |
1997 | if (err) | |
1998 | return err; | |
1999 | do_phy_reset = 0; | |
2000 | } | |
2001 | ||
2002 | /* Disable transmitter and interrupt. */ | |
2003 | if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) | |
2004 | continue; | |
2005 | ||
2006 | reg32 |= 0x3000; | |
2007 | tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); | |
2008 | ||
2009 | /* Set full-duplex, 1000 mbps. */ | |
2010 | tg3_writephy(tp, MII_BMCR, | |
221c5637 | 2011 | BMCR_FULLDPLX | BMCR_SPEED1000); |
1da177e4 LT |
2012 | |
2013 | /* Set to master mode. */ | |
221c5637 | 2014 | if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig)) |
1da177e4 LT |
2015 | continue; |
2016 | ||
221c5637 MC |
2017 | tg3_writephy(tp, MII_CTRL1000, |
2018 | CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER); | |
1da177e4 | 2019 | |
1d36ba45 MC |
2020 | err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp); |
2021 | if (err) | |
2022 | return err; | |
1da177e4 LT |
2023 | |
2024 | /* Block the PHY control access. */ | |
6ee7c0a0 | 2025 | tg3_phydsp_write(tp, 0x8005, 0x0800); |
1da177e4 LT |
2026 | |
2027 | err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset); | |
2028 | if (!err) | |
2029 | break; | |
2030 | } while (--retries); | |
2031 | ||
2032 | err = tg3_phy_reset_chanpat(tp); | |
2033 | if (err) | |
2034 | return err; | |
2035 | ||
6ee7c0a0 | 2036 | tg3_phydsp_write(tp, 0x8005, 0x0000); |
1da177e4 LT |
2037 | |
2038 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200); | |
f08aa1a8 | 2039 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000); |
1da177e4 | 2040 | |
1d36ba45 | 2041 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); |
1da177e4 | 2042 | |
221c5637 | 2043 | tg3_writephy(tp, MII_CTRL1000, phy9_orig); |
1da177e4 LT |
2044 | |
2045 | if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) { | |
2046 | reg32 &= ~0x3000; | |
2047 | tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); | |
2048 | } else if (!err) | |
2049 | err = -EBUSY; | |
2050 | ||
2051 | return err; | |
2052 | } | |
2053 | ||
2054 | /* This will reset the tigon3 PHY if there is no valid | |
2055 | * link unless the FORCE argument is non-zero. | |
2056 | */ | |
2057 | static int tg3_phy_reset(struct tg3 *tp) | |
2058 | { | |
f833c4c1 | 2059 | u32 val, cpmuctrl; |
1da177e4 LT |
2060 | int err; |
2061 | ||
60189ddf | 2062 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
60189ddf MC |
2063 | val = tr32(GRC_MISC_CFG); |
2064 | tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ); | |
2065 | udelay(40); | |
2066 | } | |
f833c4c1 MC |
2067 | err = tg3_readphy(tp, MII_BMSR, &val); |
2068 | err |= tg3_readphy(tp, MII_BMSR, &val); | |
1da177e4 LT |
2069 | if (err != 0) |
2070 | return -EBUSY; | |
2071 | ||
c8e1e82b MC |
2072 | if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) { |
2073 | netif_carrier_off(tp->dev); | |
2074 | tg3_link_report(tp); | |
2075 | } | |
2076 | ||
1da177e4 LT |
2077 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || |
2078 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
2079 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
2080 | err = tg3_phy_reset_5703_4_5(tp); | |
2081 | if (err) | |
2082 | return err; | |
2083 | goto out; | |
2084 | } | |
2085 | ||
b2a5c19c MC |
2086 | cpmuctrl = 0; |
2087 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && | |
2088 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) { | |
2089 | cpmuctrl = tr32(TG3_CPMU_CTRL); | |
2090 | if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) | |
2091 | tw32(TG3_CPMU_CTRL, | |
2092 | cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY); | |
2093 | } | |
2094 | ||
1da177e4 LT |
2095 | err = tg3_bmcr_reset(tp); |
2096 | if (err) | |
2097 | return err; | |
2098 | ||
b2a5c19c | 2099 | if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) { |
f833c4c1 MC |
2100 | val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz; |
2101 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val); | |
b2a5c19c MC |
2102 | |
2103 | tw32(TG3_CPMU_CTRL, cpmuctrl); | |
2104 | } | |
2105 | ||
bcb37f6c MC |
2106 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX || |
2107 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) { | |
ce057f01 MC |
2108 | val = tr32(TG3_CPMU_LSPD_1000MB_CLK); |
2109 | if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) == | |
2110 | CPMU_LSPD_1000MB_MACCLK_12_5) { | |
2111 | val &= ~CPMU_LSPD_1000MB_MACCLK_MASK; | |
2112 | udelay(40); | |
2113 | tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val); | |
2114 | } | |
2115 | } | |
2116 | ||
63c3a66f | 2117 | if (tg3_flag(tp, 5717_PLUS) && |
f07e9af3 | 2118 | (tp->phy_flags & TG3_PHYFLG_MII_SERDES)) |
ecf1410b MC |
2119 | return 0; |
2120 | ||
b2a5c19c MC |
2121 | tg3_phy_apply_otp(tp); |
2122 | ||
f07e9af3 | 2123 | if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) |
6833c043 MC |
2124 | tg3_phy_toggle_apd(tp, true); |
2125 | else | |
2126 | tg3_phy_toggle_apd(tp, false); | |
2127 | ||
1da177e4 | 2128 | out: |
1d36ba45 MC |
2129 | if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) && |
2130 | !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { | |
6ee7c0a0 MC |
2131 | tg3_phydsp_write(tp, 0x201f, 0x2aaa); |
2132 | tg3_phydsp_write(tp, 0x000a, 0x0323); | |
1d36ba45 | 2133 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); |
1da177e4 | 2134 | } |
1d36ba45 | 2135 | |
f07e9af3 | 2136 | if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) { |
f08aa1a8 MC |
2137 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); |
2138 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); | |
1da177e4 | 2139 | } |
1d36ba45 | 2140 | |
f07e9af3 | 2141 | if (tp->phy_flags & TG3_PHYFLG_BER_BUG) { |
1d36ba45 MC |
2142 | if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { |
2143 | tg3_phydsp_write(tp, 0x000a, 0x310b); | |
2144 | tg3_phydsp_write(tp, 0x201f, 0x9506); | |
2145 | tg3_phydsp_write(tp, 0x401f, 0x14e2); | |
2146 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); | |
2147 | } | |
f07e9af3 | 2148 | } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) { |
1d36ba45 MC |
2149 | if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { |
2150 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a); | |
2151 | if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) { | |
2152 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b); | |
2153 | tg3_writephy(tp, MII_TG3_TEST1, | |
2154 | MII_TG3_TEST1_TRIM_EN | 0x4); | |
2155 | } else | |
2156 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b); | |
2157 | ||
2158 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); | |
2159 | } | |
c424cb24 | 2160 | } |
1d36ba45 | 2161 | |
1da177e4 LT |
2162 | /* Set Extended packet length bit (bit 14) on all chips that */ |
2163 | /* support jumbo frames */ | |
79eb6904 | 2164 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { |
1da177e4 | 2165 | /* Cannot do read-modify-write on 5401 */ |
b4bd2929 | 2166 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20); |
63c3a66f | 2167 | } else if (tg3_flag(tp, JUMBO_CAPABLE)) { |
1da177e4 | 2168 | /* Set bit 14 with read-modify-write to preserve other bits */ |
15ee95c3 MC |
2169 | err = tg3_phy_auxctl_read(tp, |
2170 | MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val); | |
2171 | if (!err) | |
b4bd2929 MC |
2172 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, |
2173 | val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN); | |
1da177e4 LT |
2174 | } |
2175 | ||
2176 | /* Set phy register 0x10 bit 0 to high fifo elasticity to support | |
2177 | * jumbo frames transmission. | |
2178 | */ | |
63c3a66f | 2179 | if (tg3_flag(tp, JUMBO_CAPABLE)) { |
f833c4c1 | 2180 | if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val)) |
c6cdf436 | 2181 | tg3_writephy(tp, MII_TG3_EXT_CTRL, |
f833c4c1 | 2182 | val | MII_TG3_EXT_CTRL_FIFO_ELASTIC); |
1da177e4 LT |
2183 | } |
2184 | ||
715116a1 | 2185 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
715116a1 | 2186 | /* adjust output voltage */ |
535ef6e1 | 2187 | tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12); |
715116a1 MC |
2188 | } |
2189 | ||
9ef8ca99 | 2190 | tg3_phy_toggle_automdix(tp, 1); |
1da177e4 LT |
2191 | tg3_phy_set_wirespeed(tp); |
2192 | return 0; | |
2193 | } | |
2194 | ||
3a1e19d3 MC |
2195 | #define TG3_GPIO_MSG_DRVR_PRES 0x00000001 |
2196 | #define TG3_GPIO_MSG_NEED_VAUX 0x00000002 | |
2197 | #define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \ | |
2198 | TG3_GPIO_MSG_NEED_VAUX) | |
2199 | #define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \ | |
2200 | ((TG3_GPIO_MSG_DRVR_PRES << 0) | \ | |
2201 | (TG3_GPIO_MSG_DRVR_PRES << 4) | \ | |
2202 | (TG3_GPIO_MSG_DRVR_PRES << 8) | \ | |
2203 | (TG3_GPIO_MSG_DRVR_PRES << 12)) | |
2204 | ||
2205 | #define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \ | |
2206 | ((TG3_GPIO_MSG_NEED_VAUX << 0) | \ | |
2207 | (TG3_GPIO_MSG_NEED_VAUX << 4) | \ | |
2208 | (TG3_GPIO_MSG_NEED_VAUX << 8) | \ | |
2209 | (TG3_GPIO_MSG_NEED_VAUX << 12)) | |
2210 | ||
2211 | static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat) | |
2212 | { | |
2213 | u32 status, shift; | |
2214 | ||
2215 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
2216 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | |
2217 | status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG); | |
2218 | else | |
2219 | status = tr32(TG3_CPMU_DRV_STATUS); | |
2220 | ||
2221 | shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn; | |
2222 | status &= ~(TG3_GPIO_MSG_MASK << shift); | |
2223 | status |= (newstat << shift); | |
2224 | ||
2225 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
2226 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | |
2227 | tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status); | |
2228 | else | |
2229 | tw32(TG3_CPMU_DRV_STATUS, status); | |
2230 | ||
2231 | return status >> TG3_APE_GPIO_MSG_SHIFT; | |
2232 | } | |
2233 | ||
520b2756 MC |
2234 | static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp) |
2235 | { | |
2236 | if (!tg3_flag(tp, IS_NIC)) | |
2237 | return 0; | |
2238 | ||
3a1e19d3 MC |
2239 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
2240 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
2241 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
2242 | if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO)) | |
2243 | return -EIO; | |
520b2756 | 2244 | |
3a1e19d3 MC |
2245 | tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES); |
2246 | ||
2247 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, | |
2248 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2249 | ||
2250 | tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO); | |
2251 | } else { | |
2252 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, | |
2253 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2254 | } | |
6f5c8f83 | 2255 | |
520b2756 MC |
2256 | return 0; |
2257 | } | |
2258 | ||
2259 | static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp) | |
2260 | { | |
2261 | u32 grc_local_ctrl; | |
2262 | ||
2263 | if (!tg3_flag(tp, IS_NIC) || | |
2264 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2265 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) | |
2266 | return; | |
2267 | ||
2268 | grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1; | |
2269 | ||
2270 | tw32_wait_f(GRC_LOCAL_CTRL, | |
2271 | grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1, | |
2272 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2273 | ||
2274 | tw32_wait_f(GRC_LOCAL_CTRL, | |
2275 | grc_local_ctrl, | |
2276 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2277 | ||
2278 | tw32_wait_f(GRC_LOCAL_CTRL, | |
2279 | grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1, | |
2280 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2281 | } | |
2282 | ||
2283 | static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp) | |
2284 | { | |
2285 | if (!tg3_flag(tp, IS_NIC)) | |
2286 | return; | |
2287 | ||
2288 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2289 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
2290 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | | |
2291 | (GRC_LCLCTRL_GPIO_OE0 | | |
2292 | GRC_LCLCTRL_GPIO_OE1 | | |
2293 | GRC_LCLCTRL_GPIO_OE2 | | |
2294 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
2295 | GRC_LCLCTRL_GPIO_OUTPUT1), | |
2296 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2297 | } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || | |
2298 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { | |
2299 | /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */ | |
2300 | u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 | | |
2301 | GRC_LCLCTRL_GPIO_OE1 | | |
2302 | GRC_LCLCTRL_GPIO_OE2 | | |
2303 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
2304 | GRC_LCLCTRL_GPIO_OUTPUT1 | | |
2305 | tp->grc_local_ctrl; | |
2306 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, | |
2307 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2308 | ||
2309 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2; | |
2310 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, | |
2311 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2312 | ||
2313 | grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0; | |
2314 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, | |
2315 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2316 | } else { | |
2317 | u32 no_gpio2; | |
2318 | u32 grc_local_ctrl = 0; | |
2319 | ||
2320 | /* Workaround to prevent overdrawing Amps. */ | |
2321 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { | |
2322 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; | |
2323 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | | |
2324 | grc_local_ctrl, | |
2325 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2326 | } | |
2327 | ||
2328 | /* On 5753 and variants, GPIO2 cannot be used. */ | |
2329 | no_gpio2 = tp->nic_sram_data_cfg & | |
2330 | NIC_SRAM_DATA_CFG_NO_GPIO2; | |
2331 | ||
2332 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 | | |
2333 | GRC_LCLCTRL_GPIO_OE1 | | |
2334 | GRC_LCLCTRL_GPIO_OE2 | | |
2335 | GRC_LCLCTRL_GPIO_OUTPUT1 | | |
2336 | GRC_LCLCTRL_GPIO_OUTPUT2; | |
2337 | if (no_gpio2) { | |
2338 | grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 | | |
2339 | GRC_LCLCTRL_GPIO_OUTPUT2); | |
2340 | } | |
2341 | tw32_wait_f(GRC_LOCAL_CTRL, | |
2342 | tp->grc_local_ctrl | grc_local_ctrl, | |
2343 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2344 | ||
2345 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0; | |
2346 | ||
2347 | tw32_wait_f(GRC_LOCAL_CTRL, | |
2348 | tp->grc_local_ctrl | grc_local_ctrl, | |
2349 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2350 | ||
2351 | if (!no_gpio2) { | |
2352 | grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2; | |
2353 | tw32_wait_f(GRC_LOCAL_CTRL, | |
2354 | tp->grc_local_ctrl | grc_local_ctrl, | |
2355 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2356 | } | |
2357 | } | |
3a1e19d3 MC |
2358 | } |
2359 | ||
cd0d7228 | 2360 | static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable) |
3a1e19d3 MC |
2361 | { |
2362 | u32 msg = 0; | |
2363 | ||
2364 | /* Serialize power state transitions */ | |
2365 | if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO)) | |
2366 | return; | |
2367 | ||
cd0d7228 | 2368 | if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable) |
3a1e19d3 MC |
2369 | msg = TG3_GPIO_MSG_NEED_VAUX; |
2370 | ||
2371 | msg = tg3_set_function_status(tp, msg); | |
2372 | ||
2373 | if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK) | |
2374 | goto done; | |
6f5c8f83 | 2375 | |
3a1e19d3 MC |
2376 | if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK) |
2377 | tg3_pwrsrc_switch_to_vaux(tp); | |
2378 | else | |
2379 | tg3_pwrsrc_die_with_vmain(tp); | |
2380 | ||
2381 | done: | |
6f5c8f83 | 2382 | tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO); |
520b2756 MC |
2383 | } |
2384 | ||
cd0d7228 | 2385 | static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol) |
1da177e4 | 2386 | { |
683644b7 | 2387 | bool need_vaux = false; |
1da177e4 | 2388 | |
334355aa | 2389 | /* The GPIOs do something completely different on 57765. */ |
63c3a66f | 2390 | if (!tg3_flag(tp, IS_NIC) || |
334355aa | 2391 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) |
1da177e4 LT |
2392 | return; |
2393 | ||
3a1e19d3 MC |
2394 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
2395 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
2396 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
cd0d7228 MC |
2397 | tg3_frob_aux_power_5717(tp, include_wol ? |
2398 | tg3_flag(tp, WOL_ENABLE) != 0 : 0); | |
3a1e19d3 MC |
2399 | return; |
2400 | } | |
2401 | ||
2402 | if (tp->pdev_peer && tp->pdev_peer != tp->pdev) { | |
8c2dc7e1 MC |
2403 | struct net_device *dev_peer; |
2404 | ||
2405 | dev_peer = pci_get_drvdata(tp->pdev_peer); | |
683644b7 | 2406 | |
bc1c7567 | 2407 | /* remove_one() may have been run on the peer. */ |
683644b7 MC |
2408 | if (dev_peer) { |
2409 | struct tg3 *tp_peer = netdev_priv(dev_peer); | |
2410 | ||
63c3a66f | 2411 | if (tg3_flag(tp_peer, INIT_COMPLETE)) |
683644b7 MC |
2412 | return; |
2413 | ||
cd0d7228 | 2414 | if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) || |
63c3a66f | 2415 | tg3_flag(tp_peer, ENABLE_ASF)) |
683644b7 MC |
2416 | need_vaux = true; |
2417 | } | |
1da177e4 LT |
2418 | } |
2419 | ||
cd0d7228 MC |
2420 | if ((include_wol && tg3_flag(tp, WOL_ENABLE)) || |
2421 | tg3_flag(tp, ENABLE_ASF)) | |
683644b7 MC |
2422 | need_vaux = true; |
2423 | ||
520b2756 MC |
2424 | if (need_vaux) |
2425 | tg3_pwrsrc_switch_to_vaux(tp); | |
2426 | else | |
2427 | tg3_pwrsrc_die_with_vmain(tp); | |
1da177e4 LT |
2428 | } |
2429 | ||
e8f3f6ca MC |
2430 | static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed) |
2431 | { | |
2432 | if (tp->led_ctrl == LED_CTRL_MODE_PHY_2) | |
2433 | return 1; | |
79eb6904 | 2434 | else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) { |
e8f3f6ca MC |
2435 | if (speed != SPEED_10) |
2436 | return 1; | |
2437 | } else if (speed == SPEED_10) | |
2438 | return 1; | |
2439 | ||
2440 | return 0; | |
2441 | } | |
2442 | ||
1da177e4 LT |
2443 | static int tg3_setup_phy(struct tg3 *, int); |
2444 | ||
2445 | #define RESET_KIND_SHUTDOWN 0 | |
2446 | #define RESET_KIND_INIT 1 | |
2447 | #define RESET_KIND_SUSPEND 2 | |
2448 | ||
2449 | static void tg3_write_sig_post_reset(struct tg3 *, int); | |
2450 | static int tg3_halt_cpu(struct tg3 *, u32); | |
2451 | ||
0a459aac | 2452 | static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power) |
15c3b696 | 2453 | { |
ce057f01 MC |
2454 | u32 val; |
2455 | ||
f07e9af3 | 2456 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
5129724a MC |
2457 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { |
2458 | u32 sg_dig_ctrl = tr32(SG_DIG_CTRL); | |
2459 | u32 serdes_cfg = tr32(MAC_SERDES_CFG); | |
2460 | ||
2461 | sg_dig_ctrl |= | |
2462 | SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET; | |
2463 | tw32(SG_DIG_CTRL, sg_dig_ctrl); | |
2464 | tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15)); | |
2465 | } | |
3f7045c1 | 2466 | return; |
5129724a | 2467 | } |
3f7045c1 | 2468 | |
60189ddf | 2469 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
60189ddf MC |
2470 | tg3_bmcr_reset(tp); |
2471 | val = tr32(GRC_MISC_CFG); | |
2472 | tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ); | |
2473 | udelay(40); | |
2474 | return; | |
f07e9af3 | 2475 | } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
0e5f784c MC |
2476 | u32 phytest; |
2477 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { | |
2478 | u32 phy; | |
2479 | ||
2480 | tg3_writephy(tp, MII_ADVERTISE, 0); | |
2481 | tg3_writephy(tp, MII_BMCR, | |
2482 | BMCR_ANENABLE | BMCR_ANRESTART); | |
2483 | ||
2484 | tg3_writephy(tp, MII_TG3_FET_TEST, | |
2485 | phytest | MII_TG3_FET_SHADOW_EN); | |
2486 | if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) { | |
2487 | phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD; | |
2488 | tg3_writephy(tp, | |
2489 | MII_TG3_FET_SHDW_AUXMODE4, | |
2490 | phy); | |
2491 | } | |
2492 | tg3_writephy(tp, MII_TG3_FET_TEST, phytest); | |
2493 | } | |
2494 | return; | |
0a459aac | 2495 | } else if (do_low_power) { |
715116a1 MC |
2496 | tg3_writephy(tp, MII_TG3_EXT_CTRL, |
2497 | MII_TG3_EXT_CTRL_FORCE_LED_OFF); | |
0a459aac | 2498 | |
b4bd2929 MC |
2499 | val = MII_TG3_AUXCTL_PCTL_100TX_LPWR | |
2500 | MII_TG3_AUXCTL_PCTL_SPR_ISOLATE | | |
2501 | MII_TG3_AUXCTL_PCTL_VREG_11V; | |
2502 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val); | |
715116a1 | 2503 | } |
3f7045c1 | 2504 | |
15c3b696 MC |
2505 | /* The PHY should not be powered down on some chips because |
2506 | * of bugs. | |
2507 | */ | |
2508 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2509 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
2510 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 && | |
f07e9af3 | 2511 | (tp->phy_flags & TG3_PHYFLG_MII_SERDES))) |
15c3b696 | 2512 | return; |
ce057f01 | 2513 | |
bcb37f6c MC |
2514 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX || |
2515 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) { | |
ce057f01 MC |
2516 | val = tr32(TG3_CPMU_LSPD_1000MB_CLK); |
2517 | val &= ~CPMU_LSPD_1000MB_MACCLK_MASK; | |
2518 | val |= CPMU_LSPD_1000MB_MACCLK_12_5; | |
2519 | tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val); | |
2520 | } | |
2521 | ||
15c3b696 MC |
2522 | tg3_writephy(tp, MII_BMCR, BMCR_PDOWN); |
2523 | } | |
2524 | ||
ffbcfed4 MC |
2525 | /* tp->lock is held. */ |
2526 | static int tg3_nvram_lock(struct tg3 *tp) | |
2527 | { | |
63c3a66f | 2528 | if (tg3_flag(tp, NVRAM)) { |
ffbcfed4 MC |
2529 | int i; |
2530 | ||
2531 | if (tp->nvram_lock_cnt == 0) { | |
2532 | tw32(NVRAM_SWARB, SWARB_REQ_SET1); | |
2533 | for (i = 0; i < 8000; i++) { | |
2534 | if (tr32(NVRAM_SWARB) & SWARB_GNT1) | |
2535 | break; | |
2536 | udelay(20); | |
2537 | } | |
2538 | if (i == 8000) { | |
2539 | tw32(NVRAM_SWARB, SWARB_REQ_CLR1); | |
2540 | return -ENODEV; | |
2541 | } | |
2542 | } | |
2543 | tp->nvram_lock_cnt++; | |
2544 | } | |
2545 | return 0; | |
2546 | } | |
2547 | ||
2548 | /* tp->lock is held. */ | |
2549 | static void tg3_nvram_unlock(struct tg3 *tp) | |
2550 | { | |
63c3a66f | 2551 | if (tg3_flag(tp, NVRAM)) { |
ffbcfed4 MC |
2552 | if (tp->nvram_lock_cnt > 0) |
2553 | tp->nvram_lock_cnt--; | |
2554 | if (tp->nvram_lock_cnt == 0) | |
2555 | tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1); | |
2556 | } | |
2557 | } | |
2558 | ||
2559 | /* tp->lock is held. */ | |
2560 | static void tg3_enable_nvram_access(struct tg3 *tp) | |
2561 | { | |
63c3a66f | 2562 | if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) { |
ffbcfed4 MC |
2563 | u32 nvaccess = tr32(NVRAM_ACCESS); |
2564 | ||
2565 | tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE); | |
2566 | } | |
2567 | } | |
2568 | ||
2569 | /* tp->lock is held. */ | |
2570 | static void tg3_disable_nvram_access(struct tg3 *tp) | |
2571 | { | |
63c3a66f | 2572 | if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) { |
ffbcfed4 MC |
2573 | u32 nvaccess = tr32(NVRAM_ACCESS); |
2574 | ||
2575 | tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE); | |
2576 | } | |
2577 | } | |
2578 | ||
2579 | static int tg3_nvram_read_using_eeprom(struct tg3 *tp, | |
2580 | u32 offset, u32 *val) | |
2581 | { | |
2582 | u32 tmp; | |
2583 | int i; | |
2584 | ||
2585 | if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0) | |
2586 | return -EINVAL; | |
2587 | ||
2588 | tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK | | |
2589 | EEPROM_ADDR_DEVID_MASK | | |
2590 | EEPROM_ADDR_READ); | |
2591 | tw32(GRC_EEPROM_ADDR, | |
2592 | tmp | | |
2593 | (0 << EEPROM_ADDR_DEVID_SHIFT) | | |
2594 | ((offset << EEPROM_ADDR_ADDR_SHIFT) & | |
2595 | EEPROM_ADDR_ADDR_MASK) | | |
2596 | EEPROM_ADDR_READ | EEPROM_ADDR_START); | |
2597 | ||
2598 | for (i = 0; i < 1000; i++) { | |
2599 | tmp = tr32(GRC_EEPROM_ADDR); | |
2600 | ||
2601 | if (tmp & EEPROM_ADDR_COMPLETE) | |
2602 | break; | |
2603 | msleep(1); | |
2604 | } | |
2605 | if (!(tmp & EEPROM_ADDR_COMPLETE)) | |
2606 | return -EBUSY; | |
2607 | ||
62cedd11 MC |
2608 | tmp = tr32(GRC_EEPROM_DATA); |
2609 | ||
2610 | /* | |
2611 | * The data will always be opposite the native endian | |
2612 | * format. Perform a blind byteswap to compensate. | |
2613 | */ | |
2614 | *val = swab32(tmp); | |
2615 | ||
ffbcfed4 MC |
2616 | return 0; |
2617 | } | |
2618 | ||
2619 | #define NVRAM_CMD_TIMEOUT 10000 | |
2620 | ||
2621 | static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd) | |
2622 | { | |
2623 | int i; | |
2624 | ||
2625 | tw32(NVRAM_CMD, nvram_cmd); | |
2626 | for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) { | |
2627 | udelay(10); | |
2628 | if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) { | |
2629 | udelay(10); | |
2630 | break; | |
2631 | } | |
2632 | } | |
2633 | ||
2634 | if (i == NVRAM_CMD_TIMEOUT) | |
2635 | return -EBUSY; | |
2636 | ||
2637 | return 0; | |
2638 | } | |
2639 | ||
2640 | static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr) | |
2641 | { | |
63c3a66f JP |
2642 | if (tg3_flag(tp, NVRAM) && |
2643 | tg3_flag(tp, NVRAM_BUFFERED) && | |
2644 | tg3_flag(tp, FLASH) && | |
2645 | !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) && | |
ffbcfed4 MC |
2646 | (tp->nvram_jedecnum == JEDEC_ATMEL)) |
2647 | ||
2648 | addr = ((addr / tp->nvram_pagesize) << | |
2649 | ATMEL_AT45DB0X1B_PAGE_POS) + | |
2650 | (addr % tp->nvram_pagesize); | |
2651 | ||
2652 | return addr; | |
2653 | } | |
2654 | ||
2655 | static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr) | |
2656 | { | |
63c3a66f JP |
2657 | if (tg3_flag(tp, NVRAM) && |
2658 | tg3_flag(tp, NVRAM_BUFFERED) && | |
2659 | tg3_flag(tp, FLASH) && | |
2660 | !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) && | |
ffbcfed4 MC |
2661 | (tp->nvram_jedecnum == JEDEC_ATMEL)) |
2662 | ||
2663 | addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) * | |
2664 | tp->nvram_pagesize) + | |
2665 | (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1)); | |
2666 | ||
2667 | return addr; | |
2668 | } | |
2669 | ||
e4f34110 MC |
2670 | /* NOTE: Data read in from NVRAM is byteswapped according to |
2671 | * the byteswapping settings for all other register accesses. | |
2672 | * tg3 devices are BE devices, so on a BE machine, the data | |
2673 | * returned will be exactly as it is seen in NVRAM. On a LE | |
2674 | * machine, the 32-bit value will be byteswapped. | |
2675 | */ | |
ffbcfed4 MC |
2676 | static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val) |
2677 | { | |
2678 | int ret; | |
2679 | ||
63c3a66f | 2680 | if (!tg3_flag(tp, NVRAM)) |
ffbcfed4 MC |
2681 | return tg3_nvram_read_using_eeprom(tp, offset, val); |
2682 | ||
2683 | offset = tg3_nvram_phys_addr(tp, offset); | |
2684 | ||
2685 | if (offset > NVRAM_ADDR_MSK) | |
2686 | return -EINVAL; | |
2687 | ||
2688 | ret = tg3_nvram_lock(tp); | |
2689 | if (ret) | |
2690 | return ret; | |
2691 | ||
2692 | tg3_enable_nvram_access(tp); | |
2693 | ||
2694 | tw32(NVRAM_ADDR, offset); | |
2695 | ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO | | |
2696 | NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE); | |
2697 | ||
2698 | if (ret == 0) | |
e4f34110 | 2699 | *val = tr32(NVRAM_RDDATA); |
ffbcfed4 MC |
2700 | |
2701 | tg3_disable_nvram_access(tp); | |
2702 | ||
2703 | tg3_nvram_unlock(tp); | |
2704 | ||
2705 | return ret; | |
2706 | } | |
2707 | ||
a9dc529d MC |
2708 | /* Ensures NVRAM data is in bytestream format. */ |
2709 | static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val) | |
ffbcfed4 MC |
2710 | { |
2711 | u32 v; | |
a9dc529d | 2712 | int res = tg3_nvram_read(tp, offset, &v); |
ffbcfed4 | 2713 | if (!res) |
a9dc529d | 2714 | *val = cpu_to_be32(v); |
ffbcfed4 MC |
2715 | return res; |
2716 | } | |
2717 | ||
3f007891 MC |
2718 | /* tp->lock is held. */ |
2719 | static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1) | |
2720 | { | |
2721 | u32 addr_high, addr_low; | |
2722 | int i; | |
2723 | ||
2724 | addr_high = ((tp->dev->dev_addr[0] << 8) | | |
2725 | tp->dev->dev_addr[1]); | |
2726 | addr_low = ((tp->dev->dev_addr[2] << 24) | | |
2727 | (tp->dev->dev_addr[3] << 16) | | |
2728 | (tp->dev->dev_addr[4] << 8) | | |
2729 | (tp->dev->dev_addr[5] << 0)); | |
2730 | for (i = 0; i < 4; i++) { | |
2731 | if (i == 1 && skip_mac_1) | |
2732 | continue; | |
2733 | tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high); | |
2734 | tw32(MAC_ADDR_0_LOW + (i * 8), addr_low); | |
2735 | } | |
2736 | ||
2737 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
2738 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
2739 | for (i = 0; i < 12; i++) { | |
2740 | tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high); | |
2741 | tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low); | |
2742 | } | |
2743 | } | |
2744 | ||
2745 | addr_high = (tp->dev->dev_addr[0] + | |
2746 | tp->dev->dev_addr[1] + | |
2747 | tp->dev->dev_addr[2] + | |
2748 | tp->dev->dev_addr[3] + | |
2749 | tp->dev->dev_addr[4] + | |
2750 | tp->dev->dev_addr[5]) & | |
2751 | TX_BACKOFF_SEED_MASK; | |
2752 | tw32(MAC_TX_BACKOFF_SEED, addr_high); | |
2753 | } | |
2754 | ||
c866b7ea | 2755 | static void tg3_enable_register_access(struct tg3 *tp) |
1da177e4 | 2756 | { |
c866b7ea RW |
2757 | /* |
2758 | * Make sure register accesses (indirect or otherwise) will function | |
2759 | * correctly. | |
1da177e4 LT |
2760 | */ |
2761 | pci_write_config_dword(tp->pdev, | |
c866b7ea RW |
2762 | TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl); |
2763 | } | |
1da177e4 | 2764 | |
c866b7ea RW |
2765 | static int tg3_power_up(struct tg3 *tp) |
2766 | { | |
bed9829f | 2767 | int err; |
8c6bda1a | 2768 | |
bed9829f | 2769 | tg3_enable_register_access(tp); |
1da177e4 | 2770 | |
bed9829f MC |
2771 | err = pci_set_power_state(tp->pdev, PCI_D0); |
2772 | if (!err) { | |
2773 | /* Switch out of Vaux if it is a NIC */ | |
2774 | tg3_pwrsrc_switch_to_vmain(tp); | |
2775 | } else { | |
2776 | netdev_err(tp->dev, "Transition to D0 failed\n"); | |
2777 | } | |
1da177e4 | 2778 | |
bed9829f | 2779 | return err; |
c866b7ea | 2780 | } |
1da177e4 | 2781 | |
c866b7ea RW |
2782 | static int tg3_power_down_prepare(struct tg3 *tp) |
2783 | { | |
2784 | u32 misc_host_ctrl; | |
2785 | bool device_should_wake, do_low_power; | |
2786 | ||
2787 | tg3_enable_register_access(tp); | |
5e7dfd0f MC |
2788 | |
2789 | /* Restore the CLKREQ setting. */ | |
63c3a66f | 2790 | if (tg3_flag(tp, CLKREQ_BUG)) { |
5e7dfd0f MC |
2791 | u16 lnkctl; |
2792 | ||
2793 | pci_read_config_word(tp->pdev, | |
708ebb3a | 2794 | pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL, |
5e7dfd0f MC |
2795 | &lnkctl); |
2796 | lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN; | |
2797 | pci_write_config_word(tp->pdev, | |
708ebb3a | 2798 | pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL, |
5e7dfd0f MC |
2799 | lnkctl); |
2800 | } | |
2801 | ||
1da177e4 LT |
2802 | misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL); |
2803 | tw32(TG3PCI_MISC_HOST_CTRL, | |
2804 | misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT); | |
2805 | ||
c866b7ea | 2806 | device_should_wake = device_may_wakeup(&tp->pdev->dev) && |
63c3a66f | 2807 | tg3_flag(tp, WOL_ENABLE); |
05ac4cb7 | 2808 | |
63c3a66f | 2809 | if (tg3_flag(tp, USE_PHYLIB)) { |
0a459aac | 2810 | do_low_power = false; |
f07e9af3 | 2811 | if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) && |
80096068 | 2812 | !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { |
b02fd9e3 | 2813 | struct phy_device *phydev; |
0a459aac | 2814 | u32 phyid, advertising; |
b02fd9e3 | 2815 | |
3f0e3ad7 | 2816 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 | 2817 | |
80096068 | 2818 | tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; |
b02fd9e3 MC |
2819 | |
2820 | tp->link_config.orig_speed = phydev->speed; | |
2821 | tp->link_config.orig_duplex = phydev->duplex; | |
2822 | tp->link_config.orig_autoneg = phydev->autoneg; | |
2823 | tp->link_config.orig_advertising = phydev->advertising; | |
2824 | ||
2825 | advertising = ADVERTISED_TP | | |
2826 | ADVERTISED_Pause | | |
2827 | ADVERTISED_Autoneg | | |
2828 | ADVERTISED_10baseT_Half; | |
2829 | ||
63c3a66f JP |
2830 | if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) { |
2831 | if (tg3_flag(tp, WOL_SPEED_100MB)) | |
b02fd9e3 MC |
2832 | advertising |= |
2833 | ADVERTISED_100baseT_Half | | |
2834 | ADVERTISED_100baseT_Full | | |
2835 | ADVERTISED_10baseT_Full; | |
2836 | else | |
2837 | advertising |= ADVERTISED_10baseT_Full; | |
2838 | } | |
2839 | ||
2840 | phydev->advertising = advertising; | |
2841 | ||
2842 | phy_start_aneg(phydev); | |
0a459aac MC |
2843 | |
2844 | phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask; | |
6a443a0f MC |
2845 | if (phyid != PHY_ID_BCMAC131) { |
2846 | phyid &= PHY_BCM_OUI_MASK; | |
2847 | if (phyid == PHY_BCM_OUI_1 || | |
2848 | phyid == PHY_BCM_OUI_2 || | |
2849 | phyid == PHY_BCM_OUI_3) | |
0a459aac MC |
2850 | do_low_power = true; |
2851 | } | |
b02fd9e3 | 2852 | } |
dd477003 | 2853 | } else { |
2023276e | 2854 | do_low_power = true; |
0a459aac | 2855 | |
80096068 MC |
2856 | if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { |
2857 | tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; | |
dd477003 MC |
2858 | tp->link_config.orig_speed = tp->link_config.speed; |
2859 | tp->link_config.orig_duplex = tp->link_config.duplex; | |
2860 | tp->link_config.orig_autoneg = tp->link_config.autoneg; | |
2861 | } | |
1da177e4 | 2862 | |
f07e9af3 | 2863 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { |
dd477003 MC |
2864 | tp->link_config.speed = SPEED_10; |
2865 | tp->link_config.duplex = DUPLEX_HALF; | |
2866 | tp->link_config.autoneg = AUTONEG_ENABLE; | |
2867 | tg3_setup_phy(tp, 0); | |
2868 | } | |
1da177e4 LT |
2869 | } |
2870 | ||
b5d3772c MC |
2871 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
2872 | u32 val; | |
2873 | ||
2874 | val = tr32(GRC_VCPU_EXT_CTRL); | |
2875 | tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL); | |
63c3a66f | 2876 | } else if (!tg3_flag(tp, ENABLE_ASF)) { |
6921d201 MC |
2877 | int i; |
2878 | u32 val; | |
2879 | ||
2880 | for (i = 0; i < 200; i++) { | |
2881 | tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val); | |
2882 | if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1) | |
2883 | break; | |
2884 | msleep(1); | |
2885 | } | |
2886 | } | |
63c3a66f | 2887 | if (tg3_flag(tp, WOL_CAP)) |
a85feb8c GZ |
2888 | tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE | |
2889 | WOL_DRV_STATE_SHUTDOWN | | |
2890 | WOL_DRV_WOL | | |
2891 | WOL_SET_MAGIC_PKT); | |
6921d201 | 2892 | |
05ac4cb7 | 2893 | if (device_should_wake) { |
1da177e4 LT |
2894 | u32 mac_mode; |
2895 | ||
f07e9af3 | 2896 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { |
b4bd2929 MC |
2897 | if (do_low_power && |
2898 | !(tp->phy_flags & TG3_PHYFLG_IS_FET)) { | |
2899 | tg3_phy_auxctl_write(tp, | |
2900 | MII_TG3_AUXCTL_SHDWSEL_PWRCTL, | |
2901 | MII_TG3_AUXCTL_PCTL_WOL_EN | | |
2902 | MII_TG3_AUXCTL_PCTL_100TX_LPWR | | |
2903 | MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC); | |
dd477003 MC |
2904 | udelay(40); |
2905 | } | |
1da177e4 | 2906 | |
f07e9af3 | 2907 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) |
3f7045c1 MC |
2908 | mac_mode = MAC_MODE_PORT_MODE_GMII; |
2909 | else | |
2910 | mac_mode = MAC_MODE_PORT_MODE_MII; | |
1da177e4 | 2911 | |
e8f3f6ca MC |
2912 | mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY; |
2913 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | |
2914 | ASIC_REV_5700) { | |
63c3a66f | 2915 | u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ? |
e8f3f6ca MC |
2916 | SPEED_100 : SPEED_10; |
2917 | if (tg3_5700_link_polarity(tp, speed)) | |
2918 | mac_mode |= MAC_MODE_LINK_POLARITY; | |
2919 | else | |
2920 | mac_mode &= ~MAC_MODE_LINK_POLARITY; | |
2921 | } | |
1da177e4 LT |
2922 | } else { |
2923 | mac_mode = MAC_MODE_PORT_MODE_TBI; | |
2924 | } | |
2925 | ||
63c3a66f | 2926 | if (!tg3_flag(tp, 5750_PLUS)) |
1da177e4 LT |
2927 | tw32(MAC_LED_CTRL, tp->led_ctrl); |
2928 | ||
05ac4cb7 | 2929 | mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE; |
63c3a66f JP |
2930 | if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) && |
2931 | (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE))) | |
05ac4cb7 | 2932 | mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL; |
1da177e4 | 2933 | |
63c3a66f | 2934 | if (tg3_flag(tp, ENABLE_APE)) |
d2394e6b MC |
2935 | mac_mode |= MAC_MODE_APE_TX_EN | |
2936 | MAC_MODE_APE_RX_EN | | |
2937 | MAC_MODE_TDE_ENABLE; | |
3bda1258 | 2938 | |
1da177e4 LT |
2939 | tw32_f(MAC_MODE, mac_mode); |
2940 | udelay(100); | |
2941 | ||
2942 | tw32_f(MAC_RX_MODE, RX_MODE_ENABLE); | |
2943 | udelay(10); | |
2944 | } | |
2945 | ||
63c3a66f | 2946 | if (!tg3_flag(tp, WOL_SPEED_100MB) && |
1da177e4 LT |
2947 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
2948 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) { | |
2949 | u32 base_val; | |
2950 | ||
2951 | base_val = tp->pci_clock_ctrl; | |
2952 | base_val |= (CLOCK_CTRL_RXCLK_DISABLE | | |
2953 | CLOCK_CTRL_TXCLK_DISABLE); | |
2954 | ||
b401e9e2 MC |
2955 | tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK | |
2956 | CLOCK_CTRL_PWRDOWN_PLL133, 40); | |
63c3a66f JP |
2957 | } else if (tg3_flag(tp, 5780_CLASS) || |
2958 | tg3_flag(tp, CPMU_PRESENT) || | |
6ff6f81d | 2959 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
4cf78e4f | 2960 | /* do nothing */ |
63c3a66f | 2961 | } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) { |
1da177e4 LT |
2962 | u32 newbits1, newbits2; |
2963 | ||
2964 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2965 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
2966 | newbits1 = (CLOCK_CTRL_RXCLK_DISABLE | | |
2967 | CLOCK_CTRL_TXCLK_DISABLE | | |
2968 | CLOCK_CTRL_ALTCLK); | |
2969 | newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE; | |
63c3a66f | 2970 | } else if (tg3_flag(tp, 5705_PLUS)) { |
1da177e4 LT |
2971 | newbits1 = CLOCK_CTRL_625_CORE; |
2972 | newbits2 = newbits1 | CLOCK_CTRL_ALTCLK; | |
2973 | } else { | |
2974 | newbits1 = CLOCK_CTRL_ALTCLK; | |
2975 | newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE; | |
2976 | } | |
2977 | ||
b401e9e2 MC |
2978 | tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1, |
2979 | 40); | |
1da177e4 | 2980 | |
b401e9e2 MC |
2981 | tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2, |
2982 | 40); | |
1da177e4 | 2983 | |
63c3a66f | 2984 | if (!tg3_flag(tp, 5705_PLUS)) { |
1da177e4 LT |
2985 | u32 newbits3; |
2986 | ||
2987 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2988 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
2989 | newbits3 = (CLOCK_CTRL_RXCLK_DISABLE | | |
2990 | CLOCK_CTRL_TXCLK_DISABLE | | |
2991 | CLOCK_CTRL_44MHZ_CORE); | |
2992 | } else { | |
2993 | newbits3 = CLOCK_CTRL_44MHZ_CORE; | |
2994 | } | |
2995 | ||
b401e9e2 MC |
2996 | tw32_wait_f(TG3PCI_CLOCK_CTRL, |
2997 | tp->pci_clock_ctrl | newbits3, 40); | |
1da177e4 LT |
2998 | } |
2999 | } | |
3000 | ||
63c3a66f | 3001 | if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF)) |
0a459aac | 3002 | tg3_power_down_phy(tp, do_low_power); |
6921d201 | 3003 | |
cd0d7228 | 3004 | tg3_frob_aux_power(tp, true); |
1da177e4 LT |
3005 | |
3006 | /* Workaround for unstable PLL clock */ | |
3007 | if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) || | |
3008 | (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) { | |
3009 | u32 val = tr32(0x7d00); | |
3010 | ||
3011 | val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1); | |
3012 | tw32(0x7d00, val); | |
63c3a66f | 3013 | if (!tg3_flag(tp, ENABLE_ASF)) { |
ec41c7df MC |
3014 | int err; |
3015 | ||
3016 | err = tg3_nvram_lock(tp); | |
1da177e4 | 3017 | tg3_halt_cpu(tp, RX_CPU_BASE); |
ec41c7df MC |
3018 | if (!err) |
3019 | tg3_nvram_unlock(tp); | |
6921d201 | 3020 | } |
1da177e4 LT |
3021 | } |
3022 | ||
bbadf503 MC |
3023 | tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN); |
3024 | ||
c866b7ea RW |
3025 | return 0; |
3026 | } | |
12dac075 | 3027 | |
c866b7ea RW |
3028 | static void tg3_power_down(struct tg3 *tp) |
3029 | { | |
3030 | tg3_power_down_prepare(tp); | |
1da177e4 | 3031 | |
63c3a66f | 3032 | pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE)); |
c866b7ea | 3033 | pci_set_power_state(tp->pdev, PCI_D3hot); |
1da177e4 LT |
3034 | } |
3035 | ||
1da177e4 LT |
3036 | static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex) |
3037 | { | |
3038 | switch (val & MII_TG3_AUX_STAT_SPDMASK) { | |
3039 | case MII_TG3_AUX_STAT_10HALF: | |
3040 | *speed = SPEED_10; | |
3041 | *duplex = DUPLEX_HALF; | |
3042 | break; | |
3043 | ||
3044 | case MII_TG3_AUX_STAT_10FULL: | |
3045 | *speed = SPEED_10; | |
3046 | *duplex = DUPLEX_FULL; | |
3047 | break; | |
3048 | ||
3049 | case MII_TG3_AUX_STAT_100HALF: | |
3050 | *speed = SPEED_100; | |
3051 | *duplex = DUPLEX_HALF; | |
3052 | break; | |
3053 | ||
3054 | case MII_TG3_AUX_STAT_100FULL: | |
3055 | *speed = SPEED_100; | |
3056 | *duplex = DUPLEX_FULL; | |
3057 | break; | |
3058 | ||
3059 | case MII_TG3_AUX_STAT_1000HALF: | |
3060 | *speed = SPEED_1000; | |
3061 | *duplex = DUPLEX_HALF; | |
3062 | break; | |
3063 | ||
3064 | case MII_TG3_AUX_STAT_1000FULL: | |
3065 | *speed = SPEED_1000; | |
3066 | *duplex = DUPLEX_FULL; | |
3067 | break; | |
3068 | ||
3069 | default: | |
f07e9af3 | 3070 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
715116a1 MC |
3071 | *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 : |
3072 | SPEED_10; | |
3073 | *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL : | |
3074 | DUPLEX_HALF; | |
3075 | break; | |
3076 | } | |
1da177e4 LT |
3077 | *speed = SPEED_INVALID; |
3078 | *duplex = DUPLEX_INVALID; | |
3079 | break; | |
855e1111 | 3080 | } |
1da177e4 LT |
3081 | } |
3082 | ||
42b64a45 | 3083 | static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl) |
1da177e4 | 3084 | { |
42b64a45 MC |
3085 | int err = 0; |
3086 | u32 val, new_adv; | |
1da177e4 | 3087 | |
42b64a45 MC |
3088 | new_adv = ADVERTISE_CSMA; |
3089 | if (advertise & ADVERTISED_10baseT_Half) | |
3090 | new_adv |= ADVERTISE_10HALF; | |
3091 | if (advertise & ADVERTISED_10baseT_Full) | |
3092 | new_adv |= ADVERTISE_10FULL; | |
3093 | if (advertise & ADVERTISED_100baseT_Half) | |
3094 | new_adv |= ADVERTISE_100HALF; | |
3095 | if (advertise & ADVERTISED_100baseT_Full) | |
3096 | new_adv |= ADVERTISE_100FULL; | |
1da177e4 | 3097 | |
42b64a45 | 3098 | new_adv |= tg3_advert_flowctrl_1000T(flowctrl); |
1da177e4 | 3099 | |
42b64a45 MC |
3100 | err = tg3_writephy(tp, MII_ADVERTISE, new_adv); |
3101 | if (err) | |
3102 | goto done; | |
ba4d07a8 | 3103 | |
42b64a45 MC |
3104 | if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) |
3105 | goto done; | |
1da177e4 | 3106 | |
42b64a45 MC |
3107 | new_adv = 0; |
3108 | if (advertise & ADVERTISED_1000baseT_Half) | |
221c5637 | 3109 | new_adv |= ADVERTISE_1000HALF; |
42b64a45 | 3110 | if (advertise & ADVERTISED_1000baseT_Full) |
221c5637 | 3111 | new_adv |= ADVERTISE_1000FULL; |
ba4d07a8 | 3112 | |
42b64a45 MC |
3113 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || |
3114 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) | |
221c5637 | 3115 | new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER; |
ba4d07a8 | 3116 | |
221c5637 | 3117 | err = tg3_writephy(tp, MII_CTRL1000, new_adv); |
42b64a45 MC |
3118 | if (err) |
3119 | goto done; | |
1da177e4 | 3120 | |
42b64a45 MC |
3121 | if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) |
3122 | goto done; | |
52b02d04 | 3123 | |
42b64a45 MC |
3124 | tw32(TG3_CPMU_EEE_MODE, |
3125 | tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE); | |
52b02d04 | 3126 | |
42b64a45 MC |
3127 | err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp); |
3128 | if (!err) { | |
3129 | u32 err2; | |
52b02d04 | 3130 | |
21a00ab2 MC |
3131 | switch (GET_ASIC_REV(tp->pci_chip_rev_id)) { |
3132 | case ASIC_REV_5717: | |
3133 | case ASIC_REV_57765: | |
21a00ab2 MC |
3134 | case ASIC_REV_5719: |
3135 | val = MII_TG3_DSP_TAP26_ALNOKO | | |
3136 | MII_TG3_DSP_TAP26_RMRXSTO | | |
3137 | MII_TG3_DSP_TAP26_OPCSINPT; | |
3138 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val); | |
be671947 MC |
3139 | /* Fall through */ |
3140 | case ASIC_REV_5720: | |
3141 | if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val)) | |
3142 | tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val | | |
3143 | MII_TG3_DSP_CH34TP2_HIBW01); | |
21a00ab2 | 3144 | } |
52b02d04 | 3145 | |
a6b68dab | 3146 | val = 0; |
42b64a45 MC |
3147 | /* Advertise 100-BaseTX EEE ability */ |
3148 | if (advertise & ADVERTISED_100baseT_Full) | |
3149 | val |= MDIO_AN_EEE_ADV_100TX; | |
3150 | /* Advertise 1000-BaseT EEE ability */ | |
3151 | if (advertise & ADVERTISED_1000baseT_Full) | |
3152 | val |= MDIO_AN_EEE_ADV_1000T; | |
3153 | err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val); | |
3154 | ||
3155 | err2 = TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); | |
3156 | if (!err) | |
3157 | err = err2; | |
3158 | } | |
3159 | ||
3160 | done: | |
3161 | return err; | |
3162 | } | |
3163 | ||
3164 | static void tg3_phy_copper_begin(struct tg3 *tp) | |
3165 | { | |
3166 | u32 new_adv; | |
3167 | int i; | |
3168 | ||
3169 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { | |
3170 | new_adv = ADVERTISED_10baseT_Half | | |
3171 | ADVERTISED_10baseT_Full; | |
3172 | if (tg3_flag(tp, WOL_SPEED_100MB)) | |
3173 | new_adv |= ADVERTISED_100baseT_Half | | |
3174 | ADVERTISED_100baseT_Full; | |
3175 | ||
3176 | tg3_phy_autoneg_cfg(tp, new_adv, | |
3177 | FLOW_CTRL_TX | FLOW_CTRL_RX); | |
3178 | } else if (tp->link_config.speed == SPEED_INVALID) { | |
3179 | if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) | |
3180 | tp->link_config.advertising &= | |
3181 | ~(ADVERTISED_1000baseT_Half | | |
3182 | ADVERTISED_1000baseT_Full); | |
3183 | ||
3184 | tg3_phy_autoneg_cfg(tp, tp->link_config.advertising, | |
3185 | tp->link_config.flowctrl); | |
3186 | } else { | |
3187 | /* Asking for a specific link mode. */ | |
3188 | if (tp->link_config.speed == SPEED_1000) { | |
3189 | if (tp->link_config.duplex == DUPLEX_FULL) | |
3190 | new_adv = ADVERTISED_1000baseT_Full; | |
3191 | else | |
3192 | new_adv = ADVERTISED_1000baseT_Half; | |
3193 | } else if (tp->link_config.speed == SPEED_100) { | |
3194 | if (tp->link_config.duplex == DUPLEX_FULL) | |
3195 | new_adv = ADVERTISED_100baseT_Full; | |
3196 | else | |
3197 | new_adv = ADVERTISED_100baseT_Half; | |
3198 | } else { | |
3199 | if (tp->link_config.duplex == DUPLEX_FULL) | |
3200 | new_adv = ADVERTISED_10baseT_Full; | |
3201 | else | |
3202 | new_adv = ADVERTISED_10baseT_Half; | |
52b02d04 | 3203 | } |
52b02d04 | 3204 | |
42b64a45 MC |
3205 | tg3_phy_autoneg_cfg(tp, new_adv, |
3206 | tp->link_config.flowctrl); | |
52b02d04 MC |
3207 | } |
3208 | ||
1da177e4 LT |
3209 | if (tp->link_config.autoneg == AUTONEG_DISABLE && |
3210 | tp->link_config.speed != SPEED_INVALID) { | |
3211 | u32 bmcr, orig_bmcr; | |
3212 | ||
3213 | tp->link_config.active_speed = tp->link_config.speed; | |
3214 | tp->link_config.active_duplex = tp->link_config.duplex; | |
3215 | ||
3216 | bmcr = 0; | |
3217 | switch (tp->link_config.speed) { | |
3218 | default: | |
3219 | case SPEED_10: | |
3220 | break; | |
3221 | ||
3222 | case SPEED_100: | |
3223 | bmcr |= BMCR_SPEED100; | |
3224 | break; | |
3225 | ||
3226 | case SPEED_1000: | |
221c5637 | 3227 | bmcr |= BMCR_SPEED1000; |
1da177e4 | 3228 | break; |
855e1111 | 3229 | } |
1da177e4 LT |
3230 | |
3231 | if (tp->link_config.duplex == DUPLEX_FULL) | |
3232 | bmcr |= BMCR_FULLDPLX; | |
3233 | ||
3234 | if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) && | |
3235 | (bmcr != orig_bmcr)) { | |
3236 | tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK); | |
3237 | for (i = 0; i < 1500; i++) { | |
3238 | u32 tmp; | |
3239 | ||
3240 | udelay(10); | |
3241 | if (tg3_readphy(tp, MII_BMSR, &tmp) || | |
3242 | tg3_readphy(tp, MII_BMSR, &tmp)) | |
3243 | continue; | |
3244 | if (!(tmp & BMSR_LSTATUS)) { | |
3245 | udelay(40); | |
3246 | break; | |
3247 | } | |
3248 | } | |
3249 | tg3_writephy(tp, MII_BMCR, bmcr); | |
3250 | udelay(40); | |
3251 | } | |
3252 | } else { | |
3253 | tg3_writephy(tp, MII_BMCR, | |
3254 | BMCR_ANENABLE | BMCR_ANRESTART); | |
3255 | } | |
3256 | } | |
3257 | ||
3258 | static int tg3_init_5401phy_dsp(struct tg3 *tp) | |
3259 | { | |
3260 | int err; | |
3261 | ||
3262 | /* Turn off tap power management. */ | |
3263 | /* Set Extended packet length bit */ | |
b4bd2929 | 3264 | err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20); |
1da177e4 | 3265 | |
6ee7c0a0 MC |
3266 | err |= tg3_phydsp_write(tp, 0x0012, 0x1804); |
3267 | err |= tg3_phydsp_write(tp, 0x0013, 0x1204); | |
3268 | err |= tg3_phydsp_write(tp, 0x8006, 0x0132); | |
3269 | err |= tg3_phydsp_write(tp, 0x8006, 0x0232); | |
3270 | err |= tg3_phydsp_write(tp, 0x201f, 0x0a20); | |
1da177e4 LT |
3271 | |
3272 | udelay(40); | |
3273 | ||
3274 | return err; | |
3275 | } | |
3276 | ||
3600d918 | 3277 | static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask) |
1da177e4 | 3278 | { |
3600d918 MC |
3279 | u32 adv_reg, all_mask = 0; |
3280 | ||
3281 | if (mask & ADVERTISED_10baseT_Half) | |
3282 | all_mask |= ADVERTISE_10HALF; | |
3283 | if (mask & ADVERTISED_10baseT_Full) | |
3284 | all_mask |= ADVERTISE_10FULL; | |
3285 | if (mask & ADVERTISED_100baseT_Half) | |
3286 | all_mask |= ADVERTISE_100HALF; | |
3287 | if (mask & ADVERTISED_100baseT_Full) | |
3288 | all_mask |= ADVERTISE_100FULL; | |
1da177e4 LT |
3289 | |
3290 | if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg)) | |
3291 | return 0; | |
3292 | ||
1da177e4 LT |
3293 | if ((adv_reg & all_mask) != all_mask) |
3294 | return 0; | |
f07e9af3 | 3295 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { |
1da177e4 LT |
3296 | u32 tg3_ctrl; |
3297 | ||
3600d918 MC |
3298 | all_mask = 0; |
3299 | if (mask & ADVERTISED_1000baseT_Half) | |
3300 | all_mask |= ADVERTISE_1000HALF; | |
3301 | if (mask & ADVERTISED_1000baseT_Full) | |
3302 | all_mask |= ADVERTISE_1000FULL; | |
3303 | ||
221c5637 | 3304 | if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl)) |
1da177e4 LT |
3305 | return 0; |
3306 | ||
1da177e4 LT |
3307 | if ((tg3_ctrl & all_mask) != all_mask) |
3308 | return 0; | |
3309 | } | |
3310 | return 1; | |
3311 | } | |
3312 | ||
ef167e27 MC |
3313 | static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv) |
3314 | { | |
3315 | u32 curadv, reqadv; | |
3316 | ||
3317 | if (tg3_readphy(tp, MII_ADVERTISE, lcladv)) | |
3318 | return 1; | |
3319 | ||
3320 | curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); | |
3321 | reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl); | |
3322 | ||
3323 | if (tp->link_config.active_duplex == DUPLEX_FULL) { | |
3324 | if (curadv != reqadv) | |
3325 | return 0; | |
3326 | ||
63c3a66f | 3327 | if (tg3_flag(tp, PAUSE_AUTONEG)) |
ef167e27 MC |
3328 | tg3_readphy(tp, MII_LPA, rmtadv); |
3329 | } else { | |
3330 | /* Reprogram the advertisement register, even if it | |
3331 | * does not affect the current link. If the link | |
3332 | * gets renegotiated in the future, we can save an | |
3333 | * additional renegotiation cycle by advertising | |
3334 | * it correctly in the first place. | |
3335 | */ | |
3336 | if (curadv != reqadv) { | |
3337 | *lcladv &= ~(ADVERTISE_PAUSE_CAP | | |
3338 | ADVERTISE_PAUSE_ASYM); | |
3339 | tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv); | |
3340 | } | |
3341 | } | |
3342 | ||
3343 | return 1; | |
3344 | } | |
3345 | ||
1da177e4 LT |
3346 | static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset) |
3347 | { | |
3348 | int current_link_up; | |
f833c4c1 | 3349 | u32 bmsr, val; |
ef167e27 | 3350 | u32 lcl_adv, rmt_adv; |
1da177e4 LT |
3351 | u16 current_speed; |
3352 | u8 current_duplex; | |
3353 | int i, err; | |
3354 | ||
3355 | tw32(MAC_EVENT, 0); | |
3356 | ||
3357 | tw32_f(MAC_STATUS, | |
3358 | (MAC_STATUS_SYNC_CHANGED | | |
3359 | MAC_STATUS_CFG_CHANGED | | |
3360 | MAC_STATUS_MI_COMPLETION | | |
3361 | MAC_STATUS_LNKSTATE_CHANGED)); | |
3362 | udelay(40); | |
3363 | ||
8ef21428 MC |
3364 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { |
3365 | tw32_f(MAC_MI_MODE, | |
3366 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
3367 | udelay(80); | |
3368 | } | |
1da177e4 | 3369 | |
b4bd2929 | 3370 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0); |
1da177e4 LT |
3371 | |
3372 | /* Some third-party PHYs need to be reset on link going | |
3373 | * down. | |
3374 | */ | |
3375 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
3376 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
3377 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) && | |
3378 | netif_carrier_ok(tp->dev)) { | |
3379 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
3380 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
3381 | !(bmsr & BMSR_LSTATUS)) | |
3382 | force_reset = 1; | |
3383 | } | |
3384 | if (force_reset) | |
3385 | tg3_phy_reset(tp); | |
3386 | ||
79eb6904 | 3387 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { |
1da177e4 LT |
3388 | tg3_readphy(tp, MII_BMSR, &bmsr); |
3389 | if (tg3_readphy(tp, MII_BMSR, &bmsr) || | |
63c3a66f | 3390 | !tg3_flag(tp, INIT_COMPLETE)) |
1da177e4 LT |
3391 | bmsr = 0; |
3392 | ||
3393 | if (!(bmsr & BMSR_LSTATUS)) { | |
3394 | err = tg3_init_5401phy_dsp(tp); | |
3395 | if (err) | |
3396 | return err; | |
3397 | ||
3398 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
3399 | for (i = 0; i < 1000; i++) { | |
3400 | udelay(10); | |
3401 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
3402 | (bmsr & BMSR_LSTATUS)) { | |
3403 | udelay(40); | |
3404 | break; | |
3405 | } | |
3406 | } | |
3407 | ||
79eb6904 MC |
3408 | if ((tp->phy_id & TG3_PHY_ID_REV_MASK) == |
3409 | TG3_PHY_REV_BCM5401_B0 && | |
1da177e4 LT |
3410 | !(bmsr & BMSR_LSTATUS) && |
3411 | tp->link_config.active_speed == SPEED_1000) { | |
3412 | err = tg3_phy_reset(tp); | |
3413 | if (!err) | |
3414 | err = tg3_init_5401phy_dsp(tp); | |
3415 | if (err) | |
3416 | return err; | |
3417 | } | |
3418 | } | |
3419 | } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
3420 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) { | |
3421 | /* 5701 {A0,B0} CRC bug workaround */ | |
3422 | tg3_writephy(tp, 0x15, 0x0a75); | |
f08aa1a8 MC |
3423 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68); |
3424 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); | |
3425 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68); | |
1da177e4 LT |
3426 | } |
3427 | ||
3428 | /* Clear pending interrupts... */ | |
f833c4c1 MC |
3429 | tg3_readphy(tp, MII_TG3_ISTAT, &val); |
3430 | tg3_readphy(tp, MII_TG3_ISTAT, &val); | |
1da177e4 | 3431 | |
f07e9af3 | 3432 | if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) |
1da177e4 | 3433 | tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG); |
f07e9af3 | 3434 | else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) |
1da177e4 LT |
3435 | tg3_writephy(tp, MII_TG3_IMASK, ~0); |
3436 | ||
3437 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
3438 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
3439 | if (tp->led_ctrl == LED_CTRL_MODE_PHY_1) | |
3440 | tg3_writephy(tp, MII_TG3_EXT_CTRL, | |
3441 | MII_TG3_EXT_CTRL_LNK3_LED_MODE); | |
3442 | else | |
3443 | tg3_writephy(tp, MII_TG3_EXT_CTRL, 0); | |
3444 | } | |
3445 | ||
3446 | current_link_up = 0; | |
3447 | current_speed = SPEED_INVALID; | |
3448 | current_duplex = DUPLEX_INVALID; | |
3449 | ||
f07e9af3 | 3450 | if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) { |
15ee95c3 MC |
3451 | err = tg3_phy_auxctl_read(tp, |
3452 | MII_TG3_AUXCTL_SHDWSEL_MISCTEST, | |
3453 | &val); | |
3454 | if (!err && !(val & (1 << 10))) { | |
b4bd2929 MC |
3455 | tg3_phy_auxctl_write(tp, |
3456 | MII_TG3_AUXCTL_SHDWSEL_MISCTEST, | |
3457 | val | (1 << 10)); | |
1da177e4 LT |
3458 | goto relink; |
3459 | } | |
3460 | } | |
3461 | ||
3462 | bmsr = 0; | |
3463 | for (i = 0; i < 100; i++) { | |
3464 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
3465 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
3466 | (bmsr & BMSR_LSTATUS)) | |
3467 | break; | |
3468 | udelay(40); | |
3469 | } | |
3470 | ||
3471 | if (bmsr & BMSR_LSTATUS) { | |
3472 | u32 aux_stat, bmcr; | |
3473 | ||
3474 | tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat); | |
3475 | for (i = 0; i < 2000; i++) { | |
3476 | udelay(10); | |
3477 | if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) && | |
3478 | aux_stat) | |
3479 | break; | |
3480 | } | |
3481 | ||
3482 | tg3_aux_stat_to_speed_duplex(tp, aux_stat, | |
3483 | ¤t_speed, | |
3484 | ¤t_duplex); | |
3485 | ||
3486 | bmcr = 0; | |
3487 | for (i = 0; i < 200; i++) { | |
3488 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
3489 | if (tg3_readphy(tp, MII_BMCR, &bmcr)) | |
3490 | continue; | |
3491 | if (bmcr && bmcr != 0x7fff) | |
3492 | break; | |
3493 | udelay(10); | |
3494 | } | |
3495 | ||
ef167e27 MC |
3496 | lcl_adv = 0; |
3497 | rmt_adv = 0; | |
1da177e4 | 3498 | |
ef167e27 MC |
3499 | tp->link_config.active_speed = current_speed; |
3500 | tp->link_config.active_duplex = current_duplex; | |
3501 | ||
3502 | if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
3503 | if ((bmcr & BMCR_ANENABLE) && | |
3504 | tg3_copper_is_advertising_all(tp, | |
3505 | tp->link_config.advertising)) { | |
3506 | if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv, | |
3507 | &rmt_adv)) | |
3508 | current_link_up = 1; | |
1da177e4 LT |
3509 | } |
3510 | } else { | |
3511 | if (!(bmcr & BMCR_ANENABLE) && | |
3512 | tp->link_config.speed == current_speed && | |
ef167e27 MC |
3513 | tp->link_config.duplex == current_duplex && |
3514 | tp->link_config.flowctrl == | |
3515 | tp->link_config.active_flowctrl) { | |
1da177e4 | 3516 | current_link_up = 1; |
1da177e4 LT |
3517 | } |
3518 | } | |
3519 | ||
ef167e27 MC |
3520 | if (current_link_up == 1 && |
3521 | tp->link_config.active_duplex == DUPLEX_FULL) | |
3522 | tg3_setup_flow_control(tp, lcl_adv, rmt_adv); | |
1da177e4 LT |
3523 | } |
3524 | ||
1da177e4 | 3525 | relink: |
80096068 | 3526 | if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { |
1da177e4 LT |
3527 | tg3_phy_copper_begin(tp); |
3528 | ||
f833c4c1 | 3529 | tg3_readphy(tp, MII_BMSR, &bmsr); |
06c03c02 MB |
3530 | if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) || |
3531 | (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) | |
1da177e4 LT |
3532 | current_link_up = 1; |
3533 | } | |
3534 | ||
3535 | tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK; | |
3536 | if (current_link_up == 1) { | |
3537 | if (tp->link_config.active_speed == SPEED_100 || | |
3538 | tp->link_config.active_speed == SPEED_10) | |
3539 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; | |
3540 | else | |
3541 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
f07e9af3 | 3542 | } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) |
7f97a4bd MC |
3543 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; |
3544 | else | |
1da177e4 LT |
3545 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; |
3546 | ||
3547 | tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; | |
3548 | if (tp->link_config.active_duplex == DUPLEX_HALF) | |
3549 | tp->mac_mode |= MAC_MODE_HALF_DUPLEX; | |
3550 | ||
1da177e4 | 3551 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) { |
e8f3f6ca MC |
3552 | if (current_link_up == 1 && |
3553 | tg3_5700_link_polarity(tp, tp->link_config.active_speed)) | |
1da177e4 | 3554 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; |
e8f3f6ca MC |
3555 | else |
3556 | tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; | |
1da177e4 LT |
3557 | } |
3558 | ||
3559 | /* ??? Without this setting Netgear GA302T PHY does not | |
3560 | * ??? send/receive packets... | |
3561 | */ | |
79eb6904 | 3562 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 && |
1da177e4 LT |
3563 | tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) { |
3564 | tp->mi_mode |= MAC_MI_MODE_AUTO_POLL; | |
3565 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
3566 | udelay(80); | |
3567 | } | |
3568 | ||
3569 | tw32_f(MAC_MODE, tp->mac_mode); | |
3570 | udelay(40); | |
3571 | ||
52b02d04 MC |
3572 | tg3_phy_eee_adjust(tp, current_link_up); |
3573 | ||
63c3a66f | 3574 | if (tg3_flag(tp, USE_LINKCHG_REG)) { |
1da177e4 LT |
3575 | /* Polled via timer. */ |
3576 | tw32_f(MAC_EVENT, 0); | |
3577 | } else { | |
3578 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
3579 | } | |
3580 | udelay(40); | |
3581 | ||
3582 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 && | |
3583 | current_link_up == 1 && | |
3584 | tp->link_config.active_speed == SPEED_1000 && | |
63c3a66f | 3585 | (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) { |
1da177e4 LT |
3586 | udelay(120); |
3587 | tw32_f(MAC_STATUS, | |
3588 | (MAC_STATUS_SYNC_CHANGED | | |
3589 | MAC_STATUS_CFG_CHANGED)); | |
3590 | udelay(40); | |
3591 | tg3_write_mem(tp, | |
3592 | NIC_SRAM_FIRMWARE_MBOX, | |
3593 | NIC_SRAM_FIRMWARE_MBOX_MAGIC2); | |
3594 | } | |
3595 | ||
5e7dfd0f | 3596 | /* Prevent send BD corruption. */ |
63c3a66f | 3597 | if (tg3_flag(tp, CLKREQ_BUG)) { |
5e7dfd0f MC |
3598 | u16 oldlnkctl, newlnkctl; |
3599 | ||
3600 | pci_read_config_word(tp->pdev, | |
708ebb3a | 3601 | pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL, |
5e7dfd0f MC |
3602 | &oldlnkctl); |
3603 | if (tp->link_config.active_speed == SPEED_100 || | |
3604 | tp->link_config.active_speed == SPEED_10) | |
3605 | newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN; | |
3606 | else | |
3607 | newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN; | |
3608 | if (newlnkctl != oldlnkctl) | |
3609 | pci_write_config_word(tp->pdev, | |
708ebb3a | 3610 | pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL, |
5e7dfd0f MC |
3611 | newlnkctl); |
3612 | } | |
3613 | ||
1da177e4 LT |
3614 | if (current_link_up != netif_carrier_ok(tp->dev)) { |
3615 | if (current_link_up) | |
3616 | netif_carrier_on(tp->dev); | |
3617 | else | |
3618 | netif_carrier_off(tp->dev); | |
3619 | tg3_link_report(tp); | |
3620 | } | |
3621 | ||
3622 | return 0; | |
3623 | } | |
3624 | ||
3625 | struct tg3_fiber_aneginfo { | |
3626 | int state; | |
3627 | #define ANEG_STATE_UNKNOWN 0 | |
3628 | #define ANEG_STATE_AN_ENABLE 1 | |
3629 | #define ANEG_STATE_RESTART_INIT 2 | |
3630 | #define ANEG_STATE_RESTART 3 | |
3631 | #define ANEG_STATE_DISABLE_LINK_OK 4 | |
3632 | #define ANEG_STATE_ABILITY_DETECT_INIT 5 | |
3633 | #define ANEG_STATE_ABILITY_DETECT 6 | |
3634 | #define ANEG_STATE_ACK_DETECT_INIT 7 | |
3635 | #define ANEG_STATE_ACK_DETECT 8 | |
3636 | #define ANEG_STATE_COMPLETE_ACK_INIT 9 | |
3637 | #define ANEG_STATE_COMPLETE_ACK 10 | |
3638 | #define ANEG_STATE_IDLE_DETECT_INIT 11 | |
3639 | #define ANEG_STATE_IDLE_DETECT 12 | |
3640 | #define ANEG_STATE_LINK_OK 13 | |
3641 | #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14 | |
3642 | #define ANEG_STATE_NEXT_PAGE_WAIT 15 | |
3643 | ||
3644 | u32 flags; | |
3645 | #define MR_AN_ENABLE 0x00000001 | |
3646 | #define MR_RESTART_AN 0x00000002 | |
3647 | #define MR_AN_COMPLETE 0x00000004 | |
3648 | #define MR_PAGE_RX 0x00000008 | |
3649 | #define MR_NP_LOADED 0x00000010 | |
3650 | #define MR_TOGGLE_TX 0x00000020 | |
3651 | #define MR_LP_ADV_FULL_DUPLEX 0x00000040 | |
3652 | #define MR_LP_ADV_HALF_DUPLEX 0x00000080 | |
3653 | #define MR_LP_ADV_SYM_PAUSE 0x00000100 | |
3654 | #define MR_LP_ADV_ASYM_PAUSE 0x00000200 | |
3655 | #define MR_LP_ADV_REMOTE_FAULT1 0x00000400 | |
3656 | #define MR_LP_ADV_REMOTE_FAULT2 0x00000800 | |
3657 | #define MR_LP_ADV_NEXT_PAGE 0x00001000 | |
3658 | #define MR_TOGGLE_RX 0x00002000 | |
3659 | #define MR_NP_RX 0x00004000 | |
3660 | ||
3661 | #define MR_LINK_OK 0x80000000 | |
3662 | ||
3663 | unsigned long link_time, cur_time; | |
3664 | ||
3665 | u32 ability_match_cfg; | |
3666 | int ability_match_count; | |
3667 | ||
3668 | char ability_match, idle_match, ack_match; | |
3669 | ||
3670 | u32 txconfig, rxconfig; | |
3671 | #define ANEG_CFG_NP 0x00000080 | |
3672 | #define ANEG_CFG_ACK 0x00000040 | |
3673 | #define ANEG_CFG_RF2 0x00000020 | |
3674 | #define ANEG_CFG_RF1 0x00000010 | |
3675 | #define ANEG_CFG_PS2 0x00000001 | |
3676 | #define ANEG_CFG_PS1 0x00008000 | |
3677 | #define ANEG_CFG_HD 0x00004000 | |
3678 | #define ANEG_CFG_FD 0x00002000 | |
3679 | #define ANEG_CFG_INVAL 0x00001f06 | |
3680 | ||
3681 | }; | |
3682 | #define ANEG_OK 0 | |
3683 | #define ANEG_DONE 1 | |
3684 | #define ANEG_TIMER_ENAB 2 | |
3685 | #define ANEG_FAILED -1 | |
3686 | ||
3687 | #define ANEG_STATE_SETTLE_TIME 10000 | |
3688 | ||
3689 | static int tg3_fiber_aneg_smachine(struct tg3 *tp, | |
3690 | struct tg3_fiber_aneginfo *ap) | |
3691 | { | |
5be73b47 | 3692 | u16 flowctrl; |
1da177e4 LT |
3693 | unsigned long delta; |
3694 | u32 rx_cfg_reg; | |
3695 | int ret; | |
3696 | ||
3697 | if (ap->state == ANEG_STATE_UNKNOWN) { | |
3698 | ap->rxconfig = 0; | |
3699 | ap->link_time = 0; | |
3700 | ap->cur_time = 0; | |
3701 | ap->ability_match_cfg = 0; | |
3702 | ap->ability_match_count = 0; | |
3703 | ap->ability_match = 0; | |
3704 | ap->idle_match = 0; | |
3705 | ap->ack_match = 0; | |
3706 | } | |
3707 | ap->cur_time++; | |
3708 | ||
3709 | if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) { | |
3710 | rx_cfg_reg = tr32(MAC_RX_AUTO_NEG); | |
3711 | ||
3712 | if (rx_cfg_reg != ap->ability_match_cfg) { | |
3713 | ap->ability_match_cfg = rx_cfg_reg; | |
3714 | ap->ability_match = 0; | |
3715 | ap->ability_match_count = 0; | |
3716 | } else { | |
3717 | if (++ap->ability_match_count > 1) { | |
3718 | ap->ability_match = 1; | |
3719 | ap->ability_match_cfg = rx_cfg_reg; | |
3720 | } | |
3721 | } | |
3722 | if (rx_cfg_reg & ANEG_CFG_ACK) | |
3723 | ap->ack_match = 1; | |
3724 | else | |
3725 | ap->ack_match = 0; | |
3726 | ||
3727 | ap->idle_match = 0; | |
3728 | } else { | |
3729 | ap->idle_match = 1; | |
3730 | ap->ability_match_cfg = 0; | |
3731 | ap->ability_match_count = 0; | |
3732 | ap->ability_match = 0; | |
3733 | ap->ack_match = 0; | |
3734 | ||
3735 | rx_cfg_reg = 0; | |
3736 | } | |
3737 | ||
3738 | ap->rxconfig = rx_cfg_reg; | |
3739 | ret = ANEG_OK; | |
3740 | ||
33f401ae | 3741 | switch (ap->state) { |
1da177e4 LT |
3742 | case ANEG_STATE_UNKNOWN: |
3743 | if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN)) | |
3744 | ap->state = ANEG_STATE_AN_ENABLE; | |
3745 | ||
3746 | /* fallthru */ | |
3747 | case ANEG_STATE_AN_ENABLE: | |
3748 | ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX); | |
3749 | if (ap->flags & MR_AN_ENABLE) { | |
3750 | ap->link_time = 0; | |
3751 | ap->cur_time = 0; | |
3752 | ap->ability_match_cfg = 0; | |
3753 | ap->ability_match_count = 0; | |
3754 | ap->ability_match = 0; | |
3755 | ap->idle_match = 0; | |
3756 | ap->ack_match = 0; | |
3757 | ||
3758 | ap->state = ANEG_STATE_RESTART_INIT; | |
3759 | } else { | |
3760 | ap->state = ANEG_STATE_DISABLE_LINK_OK; | |
3761 | } | |
3762 | break; | |
3763 | ||
3764 | case ANEG_STATE_RESTART_INIT: | |
3765 | ap->link_time = ap->cur_time; | |
3766 | ap->flags &= ~(MR_NP_LOADED); | |
3767 | ap->txconfig = 0; | |
3768 | tw32(MAC_TX_AUTO_NEG, 0); | |
3769 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
3770 | tw32_f(MAC_MODE, tp->mac_mode); | |
3771 | udelay(40); | |
3772 | ||
3773 | ret = ANEG_TIMER_ENAB; | |
3774 | ap->state = ANEG_STATE_RESTART; | |
3775 | ||
3776 | /* fallthru */ | |
3777 | case ANEG_STATE_RESTART: | |
3778 | delta = ap->cur_time - ap->link_time; | |
859a5887 | 3779 | if (delta > ANEG_STATE_SETTLE_TIME) |
1da177e4 | 3780 | ap->state = ANEG_STATE_ABILITY_DETECT_INIT; |
859a5887 | 3781 | else |
1da177e4 | 3782 | ret = ANEG_TIMER_ENAB; |
1da177e4 LT |
3783 | break; |
3784 | ||
3785 | case ANEG_STATE_DISABLE_LINK_OK: | |
3786 | ret = ANEG_DONE; | |
3787 | break; | |
3788 | ||
3789 | case ANEG_STATE_ABILITY_DETECT_INIT: | |
3790 | ap->flags &= ~(MR_TOGGLE_TX); | |
5be73b47 MC |
3791 | ap->txconfig = ANEG_CFG_FD; |
3792 | flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); | |
3793 | if (flowctrl & ADVERTISE_1000XPAUSE) | |
3794 | ap->txconfig |= ANEG_CFG_PS1; | |
3795 | if (flowctrl & ADVERTISE_1000XPSE_ASYM) | |
3796 | ap->txconfig |= ANEG_CFG_PS2; | |
1da177e4 LT |
3797 | tw32(MAC_TX_AUTO_NEG, ap->txconfig); |
3798 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
3799 | tw32_f(MAC_MODE, tp->mac_mode); | |
3800 | udelay(40); | |
3801 | ||
3802 | ap->state = ANEG_STATE_ABILITY_DETECT; | |
3803 | break; | |
3804 | ||
3805 | case ANEG_STATE_ABILITY_DETECT: | |
859a5887 | 3806 | if (ap->ability_match != 0 && ap->rxconfig != 0) |
1da177e4 | 3807 | ap->state = ANEG_STATE_ACK_DETECT_INIT; |
1da177e4 LT |
3808 | break; |
3809 | ||
3810 | case ANEG_STATE_ACK_DETECT_INIT: | |
3811 | ap->txconfig |= ANEG_CFG_ACK; | |
3812 | tw32(MAC_TX_AUTO_NEG, ap->txconfig); | |
3813 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
3814 | tw32_f(MAC_MODE, tp->mac_mode); | |
3815 | udelay(40); | |
3816 | ||
3817 | ap->state = ANEG_STATE_ACK_DETECT; | |
3818 | ||
3819 | /* fallthru */ | |
3820 | case ANEG_STATE_ACK_DETECT: | |
3821 | if (ap->ack_match != 0) { | |
3822 | if ((ap->rxconfig & ~ANEG_CFG_ACK) == | |
3823 | (ap->ability_match_cfg & ~ANEG_CFG_ACK)) { | |
3824 | ap->state = ANEG_STATE_COMPLETE_ACK_INIT; | |
3825 | } else { | |
3826 | ap->state = ANEG_STATE_AN_ENABLE; | |
3827 | } | |
3828 | } else if (ap->ability_match != 0 && | |
3829 | ap->rxconfig == 0) { | |
3830 | ap->state = ANEG_STATE_AN_ENABLE; | |
3831 | } | |
3832 | break; | |
3833 | ||
3834 | case ANEG_STATE_COMPLETE_ACK_INIT: | |
3835 | if (ap->rxconfig & ANEG_CFG_INVAL) { | |
3836 | ret = ANEG_FAILED; | |
3837 | break; | |
3838 | } | |
3839 | ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX | | |
3840 | MR_LP_ADV_HALF_DUPLEX | | |
3841 | MR_LP_ADV_SYM_PAUSE | | |
3842 | MR_LP_ADV_ASYM_PAUSE | | |
3843 | MR_LP_ADV_REMOTE_FAULT1 | | |
3844 | MR_LP_ADV_REMOTE_FAULT2 | | |
3845 | MR_LP_ADV_NEXT_PAGE | | |
3846 | MR_TOGGLE_RX | | |
3847 | MR_NP_RX); | |
3848 | if (ap->rxconfig & ANEG_CFG_FD) | |
3849 | ap->flags |= MR_LP_ADV_FULL_DUPLEX; | |
3850 | if (ap->rxconfig & ANEG_CFG_HD) | |
3851 | ap->flags |= MR_LP_ADV_HALF_DUPLEX; | |
3852 | if (ap->rxconfig & ANEG_CFG_PS1) | |
3853 | ap->flags |= MR_LP_ADV_SYM_PAUSE; | |
3854 | if (ap->rxconfig & ANEG_CFG_PS2) | |
3855 | ap->flags |= MR_LP_ADV_ASYM_PAUSE; | |
3856 | if (ap->rxconfig & ANEG_CFG_RF1) | |
3857 | ap->flags |= MR_LP_ADV_REMOTE_FAULT1; | |
3858 | if (ap->rxconfig & ANEG_CFG_RF2) | |
3859 | ap->flags |= MR_LP_ADV_REMOTE_FAULT2; | |
3860 | if (ap->rxconfig & ANEG_CFG_NP) | |
3861 | ap->flags |= MR_LP_ADV_NEXT_PAGE; | |
3862 | ||
3863 | ap->link_time = ap->cur_time; | |
3864 | ||
3865 | ap->flags ^= (MR_TOGGLE_TX); | |
3866 | if (ap->rxconfig & 0x0008) | |
3867 | ap->flags |= MR_TOGGLE_RX; | |
3868 | if (ap->rxconfig & ANEG_CFG_NP) | |
3869 | ap->flags |= MR_NP_RX; | |
3870 | ap->flags |= MR_PAGE_RX; | |
3871 | ||
3872 | ap->state = ANEG_STATE_COMPLETE_ACK; | |
3873 | ret = ANEG_TIMER_ENAB; | |
3874 | break; | |
3875 | ||
3876 | case ANEG_STATE_COMPLETE_ACK: | |
3877 | if (ap->ability_match != 0 && | |
3878 | ap->rxconfig == 0) { | |
3879 | ap->state = ANEG_STATE_AN_ENABLE; | |
3880 | break; | |
3881 | } | |
3882 | delta = ap->cur_time - ap->link_time; | |
3883 | if (delta > ANEG_STATE_SETTLE_TIME) { | |
3884 | if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) { | |
3885 | ap->state = ANEG_STATE_IDLE_DETECT_INIT; | |
3886 | } else { | |
3887 | if ((ap->txconfig & ANEG_CFG_NP) == 0 && | |
3888 | !(ap->flags & MR_NP_RX)) { | |
3889 | ap->state = ANEG_STATE_IDLE_DETECT_INIT; | |
3890 | } else { | |
3891 | ret = ANEG_FAILED; | |
3892 | } | |
3893 | } | |
3894 | } | |
3895 | break; | |
3896 | ||
3897 | case ANEG_STATE_IDLE_DETECT_INIT: | |
3898 | ap->link_time = ap->cur_time; | |
3899 | tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; | |
3900 | tw32_f(MAC_MODE, tp->mac_mode); | |
3901 | udelay(40); | |
3902 | ||
3903 | ap->state = ANEG_STATE_IDLE_DETECT; | |
3904 | ret = ANEG_TIMER_ENAB; | |
3905 | break; | |
3906 | ||
3907 | case ANEG_STATE_IDLE_DETECT: | |
3908 | if (ap->ability_match != 0 && | |
3909 | ap->rxconfig == 0) { | |
3910 | ap->state = ANEG_STATE_AN_ENABLE; | |
3911 | break; | |
3912 | } | |
3913 | delta = ap->cur_time - ap->link_time; | |
3914 | if (delta > ANEG_STATE_SETTLE_TIME) { | |
3915 | /* XXX another gem from the Broadcom driver :( */ | |
3916 | ap->state = ANEG_STATE_LINK_OK; | |
3917 | } | |
3918 | break; | |
3919 | ||
3920 | case ANEG_STATE_LINK_OK: | |
3921 | ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK); | |
3922 | ret = ANEG_DONE; | |
3923 | break; | |
3924 | ||
3925 | case ANEG_STATE_NEXT_PAGE_WAIT_INIT: | |
3926 | /* ??? unimplemented */ | |
3927 | break; | |
3928 | ||
3929 | case ANEG_STATE_NEXT_PAGE_WAIT: | |
3930 | /* ??? unimplemented */ | |
3931 | break; | |
3932 | ||
3933 | default: | |
3934 | ret = ANEG_FAILED; | |
3935 | break; | |
855e1111 | 3936 | } |
1da177e4 LT |
3937 | |
3938 | return ret; | |
3939 | } | |
3940 | ||
5be73b47 | 3941 | static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags) |
1da177e4 LT |
3942 | { |
3943 | int res = 0; | |
3944 | struct tg3_fiber_aneginfo aninfo; | |
3945 | int status = ANEG_FAILED; | |
3946 | unsigned int tick; | |
3947 | u32 tmp; | |
3948 | ||
3949 | tw32_f(MAC_TX_AUTO_NEG, 0); | |
3950 | ||
3951 | tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK; | |
3952 | tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII); | |
3953 | udelay(40); | |
3954 | ||
3955 | tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS); | |
3956 | udelay(40); | |
3957 | ||
3958 | memset(&aninfo, 0, sizeof(aninfo)); | |
3959 | aninfo.flags |= MR_AN_ENABLE; | |
3960 | aninfo.state = ANEG_STATE_UNKNOWN; | |
3961 | aninfo.cur_time = 0; | |
3962 | tick = 0; | |
3963 | while (++tick < 195000) { | |
3964 | status = tg3_fiber_aneg_smachine(tp, &aninfo); | |
3965 | if (status == ANEG_DONE || status == ANEG_FAILED) | |
3966 | break; | |
3967 | ||
3968 | udelay(1); | |
3969 | } | |
3970 | ||
3971 | tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; | |
3972 | tw32_f(MAC_MODE, tp->mac_mode); | |
3973 | udelay(40); | |
3974 | ||
5be73b47 MC |
3975 | *txflags = aninfo.txconfig; |
3976 | *rxflags = aninfo.flags; | |
1da177e4 LT |
3977 | |
3978 | if (status == ANEG_DONE && | |
3979 | (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK | | |
3980 | MR_LP_ADV_FULL_DUPLEX))) | |
3981 | res = 1; | |
3982 | ||
3983 | return res; | |
3984 | } | |
3985 | ||
3986 | static void tg3_init_bcm8002(struct tg3 *tp) | |
3987 | { | |
3988 | u32 mac_status = tr32(MAC_STATUS); | |
3989 | int i; | |
3990 | ||
3991 | /* Reset when initting first time or we have a link. */ | |
63c3a66f | 3992 | if (tg3_flag(tp, INIT_COMPLETE) && |
1da177e4 LT |
3993 | !(mac_status & MAC_STATUS_PCS_SYNCED)) |
3994 | return; | |
3995 | ||
3996 | /* Set PLL lock range. */ | |
3997 | tg3_writephy(tp, 0x16, 0x8007); | |
3998 | ||
3999 | /* SW reset */ | |
4000 | tg3_writephy(tp, MII_BMCR, BMCR_RESET); | |
4001 | ||
4002 | /* Wait for reset to complete. */ | |
4003 | /* XXX schedule_timeout() ... */ | |
4004 | for (i = 0; i < 500; i++) | |
4005 | udelay(10); | |
4006 | ||
4007 | /* Config mode; select PMA/Ch 1 regs. */ | |
4008 | tg3_writephy(tp, 0x10, 0x8411); | |
4009 | ||
4010 | /* Enable auto-lock and comdet, select txclk for tx. */ | |
4011 | tg3_writephy(tp, 0x11, 0x0a10); | |
4012 | ||
4013 | tg3_writephy(tp, 0x18, 0x00a0); | |
4014 | tg3_writephy(tp, 0x16, 0x41ff); | |
4015 | ||
4016 | /* Assert and deassert POR. */ | |
4017 | tg3_writephy(tp, 0x13, 0x0400); | |
4018 | udelay(40); | |
4019 | tg3_writephy(tp, 0x13, 0x0000); | |
4020 | ||
4021 | tg3_writephy(tp, 0x11, 0x0a50); | |
4022 | udelay(40); | |
4023 | tg3_writephy(tp, 0x11, 0x0a10); | |
4024 | ||
4025 | /* Wait for signal to stabilize */ | |
4026 | /* XXX schedule_timeout() ... */ | |
4027 | for (i = 0; i < 15000; i++) | |
4028 | udelay(10); | |
4029 | ||
4030 | /* Deselect the channel register so we can read the PHYID | |
4031 | * later. | |
4032 | */ | |
4033 | tg3_writephy(tp, 0x10, 0x8011); | |
4034 | } | |
4035 | ||
4036 | static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status) | |
4037 | { | |
82cd3d11 | 4038 | u16 flowctrl; |
1da177e4 LT |
4039 | u32 sg_dig_ctrl, sg_dig_status; |
4040 | u32 serdes_cfg, expected_sg_dig_ctrl; | |
4041 | int workaround, port_a; | |
4042 | int current_link_up; | |
4043 | ||
4044 | serdes_cfg = 0; | |
4045 | expected_sg_dig_ctrl = 0; | |
4046 | workaround = 0; | |
4047 | port_a = 1; | |
4048 | current_link_up = 0; | |
4049 | ||
4050 | if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 && | |
4051 | tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) { | |
4052 | workaround = 1; | |
4053 | if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) | |
4054 | port_a = 0; | |
4055 | ||
4056 | /* preserve bits 0-11,13,14 for signal pre-emphasis */ | |
4057 | /* preserve bits 20-23 for voltage regulator */ | |
4058 | serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff; | |
4059 | } | |
4060 | ||
4061 | sg_dig_ctrl = tr32(SG_DIG_CTRL); | |
4062 | ||
4063 | if (tp->link_config.autoneg != AUTONEG_ENABLE) { | |
c98f6e3b | 4064 | if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) { |
1da177e4 LT |
4065 | if (workaround) { |
4066 | u32 val = serdes_cfg; | |
4067 | ||
4068 | if (port_a) | |
4069 | val |= 0xc010000; | |
4070 | else | |
4071 | val |= 0x4010000; | |
4072 | tw32_f(MAC_SERDES_CFG, val); | |
4073 | } | |
c98f6e3b MC |
4074 | |
4075 | tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP); | |
1da177e4 LT |
4076 | } |
4077 | if (mac_status & MAC_STATUS_PCS_SYNCED) { | |
4078 | tg3_setup_flow_control(tp, 0, 0); | |
4079 | current_link_up = 1; | |
4080 | } | |
4081 | goto out; | |
4082 | } | |
4083 | ||
4084 | /* Want auto-negotiation. */ | |
c98f6e3b | 4085 | expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP; |
1da177e4 | 4086 | |
82cd3d11 MC |
4087 | flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); |
4088 | if (flowctrl & ADVERTISE_1000XPAUSE) | |
4089 | expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP; | |
4090 | if (flowctrl & ADVERTISE_1000XPSE_ASYM) | |
4091 | expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE; | |
1da177e4 LT |
4092 | |
4093 | if (sg_dig_ctrl != expected_sg_dig_ctrl) { | |
f07e9af3 | 4094 | if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) && |
3d3ebe74 MC |
4095 | tp->serdes_counter && |
4096 | ((mac_status & (MAC_STATUS_PCS_SYNCED | | |
4097 | MAC_STATUS_RCVD_CFG)) == | |
4098 | MAC_STATUS_PCS_SYNCED)) { | |
4099 | tp->serdes_counter--; | |
4100 | current_link_up = 1; | |
4101 | goto out; | |
4102 | } | |
4103 | restart_autoneg: | |
1da177e4 LT |
4104 | if (workaround) |
4105 | tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000); | |
c98f6e3b | 4106 | tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET); |
1da177e4 LT |
4107 | udelay(5); |
4108 | tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl); | |
4109 | ||
3d3ebe74 | 4110 | tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; |
f07e9af3 | 4111 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
1da177e4 LT |
4112 | } else if (mac_status & (MAC_STATUS_PCS_SYNCED | |
4113 | MAC_STATUS_SIGNAL_DET)) { | |
3d3ebe74 | 4114 | sg_dig_status = tr32(SG_DIG_STATUS); |
1da177e4 LT |
4115 | mac_status = tr32(MAC_STATUS); |
4116 | ||
c98f6e3b | 4117 | if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) && |
1da177e4 | 4118 | (mac_status & MAC_STATUS_PCS_SYNCED)) { |
82cd3d11 MC |
4119 | u32 local_adv = 0, remote_adv = 0; |
4120 | ||
4121 | if (sg_dig_ctrl & SG_DIG_PAUSE_CAP) | |
4122 | local_adv |= ADVERTISE_1000XPAUSE; | |
4123 | if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE) | |
4124 | local_adv |= ADVERTISE_1000XPSE_ASYM; | |
1da177e4 | 4125 | |
c98f6e3b | 4126 | if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE) |
82cd3d11 | 4127 | remote_adv |= LPA_1000XPAUSE; |
c98f6e3b | 4128 | if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE) |
82cd3d11 | 4129 | remote_adv |= LPA_1000XPAUSE_ASYM; |
1da177e4 LT |
4130 | |
4131 | tg3_setup_flow_control(tp, local_adv, remote_adv); | |
4132 | current_link_up = 1; | |
3d3ebe74 | 4133 | tp->serdes_counter = 0; |
f07e9af3 | 4134 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
c98f6e3b | 4135 | } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) { |
3d3ebe74 MC |
4136 | if (tp->serdes_counter) |
4137 | tp->serdes_counter--; | |
1da177e4 LT |
4138 | else { |
4139 | if (workaround) { | |
4140 | u32 val = serdes_cfg; | |
4141 | ||
4142 | if (port_a) | |
4143 | val |= 0xc010000; | |
4144 | else | |
4145 | val |= 0x4010000; | |
4146 | ||
4147 | tw32_f(MAC_SERDES_CFG, val); | |
4148 | } | |
4149 | ||
c98f6e3b | 4150 | tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP); |
1da177e4 LT |
4151 | udelay(40); |
4152 | ||
4153 | /* Link parallel detection - link is up */ | |
4154 | /* only if we have PCS_SYNC and not */ | |
4155 | /* receiving config code words */ | |
4156 | mac_status = tr32(MAC_STATUS); | |
4157 | if ((mac_status & MAC_STATUS_PCS_SYNCED) && | |
4158 | !(mac_status & MAC_STATUS_RCVD_CFG)) { | |
4159 | tg3_setup_flow_control(tp, 0, 0); | |
4160 | current_link_up = 1; | |
f07e9af3 MC |
4161 | tp->phy_flags |= |
4162 | TG3_PHYFLG_PARALLEL_DETECT; | |
3d3ebe74 MC |
4163 | tp->serdes_counter = |
4164 | SERDES_PARALLEL_DET_TIMEOUT; | |
4165 | } else | |
4166 | goto restart_autoneg; | |
1da177e4 LT |
4167 | } |
4168 | } | |
3d3ebe74 MC |
4169 | } else { |
4170 | tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; | |
f07e9af3 | 4171 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
1da177e4 LT |
4172 | } |
4173 | ||
4174 | out: | |
4175 | return current_link_up; | |
4176 | } | |
4177 | ||
4178 | static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status) | |
4179 | { | |
4180 | int current_link_up = 0; | |
4181 | ||
5cf64b8a | 4182 | if (!(mac_status & MAC_STATUS_PCS_SYNCED)) |
1da177e4 | 4183 | goto out; |
1da177e4 LT |
4184 | |
4185 | if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
5be73b47 | 4186 | u32 txflags, rxflags; |
1da177e4 | 4187 | int i; |
6aa20a22 | 4188 | |
5be73b47 MC |
4189 | if (fiber_autoneg(tp, &txflags, &rxflags)) { |
4190 | u32 local_adv = 0, remote_adv = 0; | |
1da177e4 | 4191 | |
5be73b47 MC |
4192 | if (txflags & ANEG_CFG_PS1) |
4193 | local_adv |= ADVERTISE_1000XPAUSE; | |
4194 | if (txflags & ANEG_CFG_PS2) | |
4195 | local_adv |= ADVERTISE_1000XPSE_ASYM; | |
4196 | ||
4197 | if (rxflags & MR_LP_ADV_SYM_PAUSE) | |
4198 | remote_adv |= LPA_1000XPAUSE; | |
4199 | if (rxflags & MR_LP_ADV_ASYM_PAUSE) | |
4200 | remote_adv |= LPA_1000XPAUSE_ASYM; | |
1da177e4 LT |
4201 | |
4202 | tg3_setup_flow_control(tp, local_adv, remote_adv); | |
4203 | ||
1da177e4 LT |
4204 | current_link_up = 1; |
4205 | } | |
4206 | for (i = 0; i < 30; i++) { | |
4207 | udelay(20); | |
4208 | tw32_f(MAC_STATUS, | |
4209 | (MAC_STATUS_SYNC_CHANGED | | |
4210 | MAC_STATUS_CFG_CHANGED)); | |
4211 | udelay(40); | |
4212 | if ((tr32(MAC_STATUS) & | |
4213 | (MAC_STATUS_SYNC_CHANGED | | |
4214 | MAC_STATUS_CFG_CHANGED)) == 0) | |
4215 | break; | |
4216 | } | |
4217 | ||
4218 | mac_status = tr32(MAC_STATUS); | |
4219 | if (current_link_up == 0 && | |
4220 | (mac_status & MAC_STATUS_PCS_SYNCED) && | |
4221 | !(mac_status & MAC_STATUS_RCVD_CFG)) | |
4222 | current_link_up = 1; | |
4223 | } else { | |
5be73b47 MC |
4224 | tg3_setup_flow_control(tp, 0, 0); |
4225 | ||
1da177e4 LT |
4226 | /* Forcing 1000FD link up. */ |
4227 | current_link_up = 1; | |
1da177e4 LT |
4228 | |
4229 | tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS)); | |
4230 | udelay(40); | |
e8f3f6ca MC |
4231 | |
4232 | tw32_f(MAC_MODE, tp->mac_mode); | |
4233 | udelay(40); | |
1da177e4 LT |
4234 | } |
4235 | ||
4236 | out: | |
4237 | return current_link_up; | |
4238 | } | |
4239 | ||
4240 | static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset) | |
4241 | { | |
4242 | u32 orig_pause_cfg; | |
4243 | u16 orig_active_speed; | |
4244 | u8 orig_active_duplex; | |
4245 | u32 mac_status; | |
4246 | int current_link_up; | |
4247 | int i; | |
4248 | ||
8d018621 | 4249 | orig_pause_cfg = tp->link_config.active_flowctrl; |
1da177e4 LT |
4250 | orig_active_speed = tp->link_config.active_speed; |
4251 | orig_active_duplex = tp->link_config.active_duplex; | |
4252 | ||
63c3a66f | 4253 | if (!tg3_flag(tp, HW_AUTONEG) && |
1da177e4 | 4254 | netif_carrier_ok(tp->dev) && |
63c3a66f | 4255 | tg3_flag(tp, INIT_COMPLETE)) { |
1da177e4 LT |
4256 | mac_status = tr32(MAC_STATUS); |
4257 | mac_status &= (MAC_STATUS_PCS_SYNCED | | |
4258 | MAC_STATUS_SIGNAL_DET | | |
4259 | MAC_STATUS_CFG_CHANGED | | |
4260 | MAC_STATUS_RCVD_CFG); | |
4261 | if (mac_status == (MAC_STATUS_PCS_SYNCED | | |
4262 | MAC_STATUS_SIGNAL_DET)) { | |
4263 | tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED | | |
4264 | MAC_STATUS_CFG_CHANGED)); | |
4265 | return 0; | |
4266 | } | |
4267 | } | |
4268 | ||
4269 | tw32_f(MAC_TX_AUTO_NEG, 0); | |
4270 | ||
4271 | tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); | |
4272 | tp->mac_mode |= MAC_MODE_PORT_MODE_TBI; | |
4273 | tw32_f(MAC_MODE, tp->mac_mode); | |
4274 | udelay(40); | |
4275 | ||
79eb6904 | 4276 | if (tp->phy_id == TG3_PHY_ID_BCM8002) |
1da177e4 LT |
4277 | tg3_init_bcm8002(tp); |
4278 | ||
4279 | /* Enable link change event even when serdes polling. */ | |
4280 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
4281 | udelay(40); | |
4282 | ||
4283 | current_link_up = 0; | |
4284 | mac_status = tr32(MAC_STATUS); | |
4285 | ||
63c3a66f | 4286 | if (tg3_flag(tp, HW_AUTONEG)) |
1da177e4 LT |
4287 | current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status); |
4288 | else | |
4289 | current_link_up = tg3_setup_fiber_by_hand(tp, mac_status); | |
4290 | ||
898a56f8 | 4291 | tp->napi[0].hw_status->status = |
1da177e4 | 4292 | (SD_STATUS_UPDATED | |
898a56f8 | 4293 | (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG)); |
1da177e4 LT |
4294 | |
4295 | for (i = 0; i < 100; i++) { | |
4296 | tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED | | |
4297 | MAC_STATUS_CFG_CHANGED)); | |
4298 | udelay(5); | |
4299 | if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED | | |
3d3ebe74 MC |
4300 | MAC_STATUS_CFG_CHANGED | |
4301 | MAC_STATUS_LNKSTATE_CHANGED)) == 0) | |
1da177e4 LT |
4302 | break; |
4303 | } | |
4304 | ||
4305 | mac_status = tr32(MAC_STATUS); | |
4306 | if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) { | |
4307 | current_link_up = 0; | |
3d3ebe74 MC |
4308 | if (tp->link_config.autoneg == AUTONEG_ENABLE && |
4309 | tp->serdes_counter == 0) { | |
1da177e4 LT |
4310 | tw32_f(MAC_MODE, (tp->mac_mode | |
4311 | MAC_MODE_SEND_CONFIGS)); | |
4312 | udelay(1); | |
4313 | tw32_f(MAC_MODE, tp->mac_mode); | |
4314 | } | |
4315 | } | |
4316 | ||
4317 | if (current_link_up == 1) { | |
4318 | tp->link_config.active_speed = SPEED_1000; | |
4319 | tp->link_config.active_duplex = DUPLEX_FULL; | |
4320 | tw32(MAC_LED_CTRL, (tp->led_ctrl | | |
4321 | LED_CTRL_LNKLED_OVERRIDE | | |
4322 | LED_CTRL_1000MBPS_ON)); | |
4323 | } else { | |
4324 | tp->link_config.active_speed = SPEED_INVALID; | |
4325 | tp->link_config.active_duplex = DUPLEX_INVALID; | |
4326 | tw32(MAC_LED_CTRL, (tp->led_ctrl | | |
4327 | LED_CTRL_LNKLED_OVERRIDE | | |
4328 | LED_CTRL_TRAFFIC_OVERRIDE)); | |
4329 | } | |
4330 | ||
4331 | if (current_link_up != netif_carrier_ok(tp->dev)) { | |
4332 | if (current_link_up) | |
4333 | netif_carrier_on(tp->dev); | |
4334 | else | |
4335 | netif_carrier_off(tp->dev); | |
4336 | tg3_link_report(tp); | |
4337 | } else { | |
8d018621 | 4338 | u32 now_pause_cfg = tp->link_config.active_flowctrl; |
1da177e4 LT |
4339 | if (orig_pause_cfg != now_pause_cfg || |
4340 | orig_active_speed != tp->link_config.active_speed || | |
4341 | orig_active_duplex != tp->link_config.active_duplex) | |
4342 | tg3_link_report(tp); | |
4343 | } | |
4344 | ||
4345 | return 0; | |
4346 | } | |
4347 | ||
747e8f8b MC |
4348 | static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset) |
4349 | { | |
4350 | int current_link_up, err = 0; | |
4351 | u32 bmsr, bmcr; | |
4352 | u16 current_speed; | |
4353 | u8 current_duplex; | |
ef167e27 | 4354 | u32 local_adv, remote_adv; |
747e8f8b MC |
4355 | |
4356 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
4357 | tw32_f(MAC_MODE, tp->mac_mode); | |
4358 | udelay(40); | |
4359 | ||
4360 | tw32(MAC_EVENT, 0); | |
4361 | ||
4362 | tw32_f(MAC_STATUS, | |
4363 | (MAC_STATUS_SYNC_CHANGED | | |
4364 | MAC_STATUS_CFG_CHANGED | | |
4365 | MAC_STATUS_MI_COMPLETION | | |
4366 | MAC_STATUS_LNKSTATE_CHANGED)); | |
4367 | udelay(40); | |
4368 | ||
4369 | if (force_reset) | |
4370 | tg3_phy_reset(tp); | |
4371 | ||
4372 | current_link_up = 0; | |
4373 | current_speed = SPEED_INVALID; | |
4374 | current_duplex = DUPLEX_INVALID; | |
4375 | ||
4376 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
4377 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
d4d2c558 MC |
4378 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { |
4379 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) | |
4380 | bmsr |= BMSR_LSTATUS; | |
4381 | else | |
4382 | bmsr &= ~BMSR_LSTATUS; | |
4383 | } | |
747e8f8b MC |
4384 | |
4385 | err |= tg3_readphy(tp, MII_BMCR, &bmcr); | |
4386 | ||
4387 | if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset && | |
f07e9af3 | 4388 | (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { |
747e8f8b MC |
4389 | /* do nothing, just check for link up at the end */ |
4390 | } else if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
4391 | u32 adv, new_adv; | |
4392 | ||
4393 | err |= tg3_readphy(tp, MII_ADVERTISE, &adv); | |
4394 | new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF | | |
4395 | ADVERTISE_1000XPAUSE | | |
4396 | ADVERTISE_1000XPSE_ASYM | | |
4397 | ADVERTISE_SLCT); | |
4398 | ||
ba4d07a8 | 4399 | new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); |
747e8f8b MC |
4400 | |
4401 | if (tp->link_config.advertising & ADVERTISED_1000baseT_Half) | |
4402 | new_adv |= ADVERTISE_1000XHALF; | |
4403 | if (tp->link_config.advertising & ADVERTISED_1000baseT_Full) | |
4404 | new_adv |= ADVERTISE_1000XFULL; | |
4405 | ||
4406 | if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) { | |
4407 | tg3_writephy(tp, MII_ADVERTISE, new_adv); | |
4408 | bmcr |= BMCR_ANENABLE | BMCR_ANRESTART; | |
4409 | tg3_writephy(tp, MII_BMCR, bmcr); | |
4410 | ||
4411 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
3d3ebe74 | 4412 | tp->serdes_counter = SERDES_AN_TIMEOUT_5714S; |
f07e9af3 | 4413 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
4414 | |
4415 | return err; | |
4416 | } | |
4417 | } else { | |
4418 | u32 new_bmcr; | |
4419 | ||
4420 | bmcr &= ~BMCR_SPEED1000; | |
4421 | new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX); | |
4422 | ||
4423 | if (tp->link_config.duplex == DUPLEX_FULL) | |
4424 | new_bmcr |= BMCR_FULLDPLX; | |
4425 | ||
4426 | if (new_bmcr != bmcr) { | |
4427 | /* BMCR_SPEED1000 is a reserved bit that needs | |
4428 | * to be set on write. | |
4429 | */ | |
4430 | new_bmcr |= BMCR_SPEED1000; | |
4431 | ||
4432 | /* Force a linkdown */ | |
4433 | if (netif_carrier_ok(tp->dev)) { | |
4434 | u32 adv; | |
4435 | ||
4436 | err |= tg3_readphy(tp, MII_ADVERTISE, &adv); | |
4437 | adv &= ~(ADVERTISE_1000XFULL | | |
4438 | ADVERTISE_1000XHALF | | |
4439 | ADVERTISE_SLCT); | |
4440 | tg3_writephy(tp, MII_ADVERTISE, adv); | |
4441 | tg3_writephy(tp, MII_BMCR, bmcr | | |
4442 | BMCR_ANRESTART | | |
4443 | BMCR_ANENABLE); | |
4444 | udelay(10); | |
4445 | netif_carrier_off(tp->dev); | |
4446 | } | |
4447 | tg3_writephy(tp, MII_BMCR, new_bmcr); | |
4448 | bmcr = new_bmcr; | |
4449 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
4450 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
d4d2c558 MC |
4451 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == |
4452 | ASIC_REV_5714) { | |
4453 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) | |
4454 | bmsr |= BMSR_LSTATUS; | |
4455 | else | |
4456 | bmsr &= ~BMSR_LSTATUS; | |
4457 | } | |
f07e9af3 | 4458 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
4459 | } |
4460 | } | |
4461 | ||
4462 | if (bmsr & BMSR_LSTATUS) { | |
4463 | current_speed = SPEED_1000; | |
4464 | current_link_up = 1; | |
4465 | if (bmcr & BMCR_FULLDPLX) | |
4466 | current_duplex = DUPLEX_FULL; | |
4467 | else | |
4468 | current_duplex = DUPLEX_HALF; | |
4469 | ||
ef167e27 MC |
4470 | local_adv = 0; |
4471 | remote_adv = 0; | |
4472 | ||
747e8f8b | 4473 | if (bmcr & BMCR_ANENABLE) { |
ef167e27 | 4474 | u32 common; |
747e8f8b MC |
4475 | |
4476 | err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv); | |
4477 | err |= tg3_readphy(tp, MII_LPA, &remote_adv); | |
4478 | common = local_adv & remote_adv; | |
4479 | if (common & (ADVERTISE_1000XHALF | | |
4480 | ADVERTISE_1000XFULL)) { | |
4481 | if (common & ADVERTISE_1000XFULL) | |
4482 | current_duplex = DUPLEX_FULL; | |
4483 | else | |
4484 | current_duplex = DUPLEX_HALF; | |
63c3a66f | 4485 | } else if (!tg3_flag(tp, 5780_CLASS)) { |
57d8b880 | 4486 | /* Link is up via parallel detect */ |
859a5887 | 4487 | } else { |
747e8f8b | 4488 | current_link_up = 0; |
859a5887 | 4489 | } |
747e8f8b MC |
4490 | } |
4491 | } | |
4492 | ||
ef167e27 MC |
4493 | if (current_link_up == 1 && current_duplex == DUPLEX_FULL) |
4494 | tg3_setup_flow_control(tp, local_adv, remote_adv); | |
4495 | ||
747e8f8b MC |
4496 | tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; |
4497 | if (tp->link_config.active_duplex == DUPLEX_HALF) | |
4498 | tp->mac_mode |= MAC_MODE_HALF_DUPLEX; | |
4499 | ||
4500 | tw32_f(MAC_MODE, tp->mac_mode); | |
4501 | udelay(40); | |
4502 | ||
4503 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
4504 | ||
4505 | tp->link_config.active_speed = current_speed; | |
4506 | tp->link_config.active_duplex = current_duplex; | |
4507 | ||
4508 | if (current_link_up != netif_carrier_ok(tp->dev)) { | |
4509 | if (current_link_up) | |
4510 | netif_carrier_on(tp->dev); | |
4511 | else { | |
4512 | netif_carrier_off(tp->dev); | |
f07e9af3 | 4513 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
4514 | } |
4515 | tg3_link_report(tp); | |
4516 | } | |
4517 | return err; | |
4518 | } | |
4519 | ||
4520 | static void tg3_serdes_parallel_detect(struct tg3 *tp) | |
4521 | { | |
3d3ebe74 | 4522 | if (tp->serdes_counter) { |
747e8f8b | 4523 | /* Give autoneg time to complete. */ |
3d3ebe74 | 4524 | tp->serdes_counter--; |
747e8f8b MC |
4525 | return; |
4526 | } | |
c6cdf436 | 4527 | |
747e8f8b MC |
4528 | if (!netif_carrier_ok(tp->dev) && |
4529 | (tp->link_config.autoneg == AUTONEG_ENABLE)) { | |
4530 | u32 bmcr; | |
4531 | ||
4532 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
4533 | if (bmcr & BMCR_ANENABLE) { | |
4534 | u32 phy1, phy2; | |
4535 | ||
4536 | /* Select shadow register 0x1f */ | |
f08aa1a8 MC |
4537 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00); |
4538 | tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1); | |
747e8f8b MC |
4539 | |
4540 | /* Select expansion interrupt status register */ | |
f08aa1a8 MC |
4541 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, |
4542 | MII_TG3_DSP_EXP1_INT_STAT); | |
4543 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); | |
4544 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); | |
747e8f8b MC |
4545 | |
4546 | if ((phy1 & 0x10) && !(phy2 & 0x20)) { | |
4547 | /* We have signal detect and not receiving | |
4548 | * config code words, link is up by parallel | |
4549 | * detection. | |
4550 | */ | |
4551 | ||
4552 | bmcr &= ~BMCR_ANENABLE; | |
4553 | bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX; | |
4554 | tg3_writephy(tp, MII_BMCR, bmcr); | |
f07e9af3 | 4555 | tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
4556 | } |
4557 | } | |
859a5887 MC |
4558 | } else if (netif_carrier_ok(tp->dev) && |
4559 | (tp->link_config.autoneg == AUTONEG_ENABLE) && | |
f07e9af3 | 4560 | (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { |
747e8f8b MC |
4561 | u32 phy2; |
4562 | ||
4563 | /* Select expansion interrupt status register */ | |
f08aa1a8 MC |
4564 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, |
4565 | MII_TG3_DSP_EXP1_INT_STAT); | |
4566 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); | |
747e8f8b MC |
4567 | if (phy2 & 0x20) { |
4568 | u32 bmcr; | |
4569 | ||
4570 | /* Config code words received, turn on autoneg. */ | |
4571 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
4572 | tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE); | |
4573 | ||
f07e9af3 | 4574 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
4575 | |
4576 | } | |
4577 | } | |
4578 | } | |
4579 | ||
1da177e4 LT |
4580 | static int tg3_setup_phy(struct tg3 *tp, int force_reset) |
4581 | { | |
f2096f94 | 4582 | u32 val; |
1da177e4 LT |
4583 | int err; |
4584 | ||
f07e9af3 | 4585 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
1da177e4 | 4586 | err = tg3_setup_fiber_phy(tp, force_reset); |
f07e9af3 | 4587 | else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) |
747e8f8b | 4588 | err = tg3_setup_fiber_mii_phy(tp, force_reset); |
859a5887 | 4589 | else |
1da177e4 | 4590 | err = tg3_setup_copper_phy(tp, force_reset); |
1da177e4 | 4591 | |
bcb37f6c | 4592 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) { |
f2096f94 | 4593 | u32 scale; |
aa6c91fe MC |
4594 | |
4595 | val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK; | |
4596 | if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5) | |
4597 | scale = 65; | |
4598 | else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25) | |
4599 | scale = 6; | |
4600 | else | |
4601 | scale = 12; | |
4602 | ||
4603 | val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK; | |
4604 | val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT); | |
4605 | tw32(GRC_MISC_CFG, val); | |
4606 | } | |
4607 | ||
f2096f94 MC |
4608 | val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) | |
4609 | (6 << TX_LENGTHS_IPG_SHIFT); | |
4610 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
4611 | val |= tr32(MAC_TX_LENGTHS) & | |
4612 | (TX_LENGTHS_JMB_FRM_LEN_MSK | | |
4613 | TX_LENGTHS_CNT_DWN_VAL_MSK); | |
4614 | ||
1da177e4 LT |
4615 | if (tp->link_config.active_speed == SPEED_1000 && |
4616 | tp->link_config.active_duplex == DUPLEX_HALF) | |
f2096f94 MC |
4617 | tw32(MAC_TX_LENGTHS, val | |
4618 | (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)); | |
1da177e4 | 4619 | else |
f2096f94 MC |
4620 | tw32(MAC_TX_LENGTHS, val | |
4621 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT)); | |
1da177e4 | 4622 | |
63c3a66f | 4623 | if (!tg3_flag(tp, 5705_PLUS)) { |
1da177e4 LT |
4624 | if (netif_carrier_ok(tp->dev)) { |
4625 | tw32(HOSTCC_STAT_COAL_TICKS, | |
15f9850d | 4626 | tp->coal.stats_block_coalesce_usecs); |
1da177e4 LT |
4627 | } else { |
4628 | tw32(HOSTCC_STAT_COAL_TICKS, 0); | |
4629 | } | |
4630 | } | |
4631 | ||
63c3a66f | 4632 | if (tg3_flag(tp, ASPM_WORKAROUND)) { |
f2096f94 | 4633 | val = tr32(PCIE_PWR_MGMT_THRESH); |
8ed5d97e MC |
4634 | if (!netif_carrier_ok(tp->dev)) |
4635 | val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) | | |
4636 | tp->pwrmgmt_thresh; | |
4637 | else | |
4638 | val |= PCIE_PWR_MGMT_L1_THRESH_MSK; | |
4639 | tw32(PCIE_PWR_MGMT_THRESH, val); | |
4640 | } | |
4641 | ||
1da177e4 LT |
4642 | return err; |
4643 | } | |
4644 | ||
66cfd1bd MC |
4645 | static inline int tg3_irq_sync(struct tg3 *tp) |
4646 | { | |
4647 | return tp->irq_sync; | |
4648 | } | |
4649 | ||
97bd8e49 MC |
4650 | static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len) |
4651 | { | |
4652 | int i; | |
4653 | ||
4654 | dst = (u32 *)((u8 *)dst + off); | |
4655 | for (i = 0; i < len; i += sizeof(u32)) | |
4656 | *dst++ = tr32(off + i); | |
4657 | } | |
4658 | ||
4659 | static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs) | |
4660 | { | |
4661 | tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0); | |
4662 | tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200); | |
4663 | tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0); | |
4664 | tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0); | |
4665 | tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04); | |
4666 | tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80); | |
4667 | tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48); | |
4668 | tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04); | |
4669 | tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20); | |
4670 | tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c); | |
4671 | tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c); | |
4672 | tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c); | |
4673 | tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44); | |
4674 | tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04); | |
4675 | tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20); | |
4676 | tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14); | |
4677 | tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08); | |
4678 | tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08); | |
4679 | tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100); | |
4680 | ||
63c3a66f | 4681 | if (tg3_flag(tp, SUPPORT_MSIX)) |
97bd8e49 MC |
4682 | tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180); |
4683 | ||
4684 | tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10); | |
4685 | tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58); | |
4686 | tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08); | |
4687 | tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08); | |
4688 | tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04); | |
4689 | tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04); | |
4690 | tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04); | |
4691 | tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04); | |
4692 | ||
63c3a66f | 4693 | if (!tg3_flag(tp, 5705_PLUS)) { |
97bd8e49 MC |
4694 | tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04); |
4695 | tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04); | |
4696 | tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04); | |
4697 | } | |
4698 | ||
4699 | tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110); | |
4700 | tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120); | |
4701 | tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c); | |
4702 | tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04); | |
4703 | tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c); | |
4704 | ||
63c3a66f | 4705 | if (tg3_flag(tp, NVRAM)) |
97bd8e49 MC |
4706 | tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24); |
4707 | } | |
4708 | ||
4709 | static void tg3_dump_state(struct tg3 *tp) | |
4710 | { | |
4711 | int i; | |
4712 | u32 *regs; | |
4713 | ||
4714 | regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC); | |
4715 | if (!regs) { | |
4716 | netdev_err(tp->dev, "Failed allocating register dump buffer\n"); | |
4717 | return; | |
4718 | } | |
4719 | ||
63c3a66f | 4720 | if (tg3_flag(tp, PCI_EXPRESS)) { |
97bd8e49 MC |
4721 | /* Read up to but not including private PCI registers */ |
4722 | for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32)) | |
4723 | regs[i / sizeof(u32)] = tr32(i); | |
4724 | } else | |
4725 | tg3_dump_legacy_regs(tp, regs); | |
4726 | ||
4727 | for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) { | |
4728 | if (!regs[i + 0] && !regs[i + 1] && | |
4729 | !regs[i + 2] && !regs[i + 3]) | |
4730 | continue; | |
4731 | ||
4732 | netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n", | |
4733 | i * 4, | |
4734 | regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]); | |
4735 | } | |
4736 | ||
4737 | kfree(regs); | |
4738 | ||
4739 | for (i = 0; i < tp->irq_cnt; i++) { | |
4740 | struct tg3_napi *tnapi = &tp->napi[i]; | |
4741 | ||
4742 | /* SW status block */ | |
4743 | netdev_err(tp->dev, | |
4744 | "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n", | |
4745 | i, | |
4746 | tnapi->hw_status->status, | |
4747 | tnapi->hw_status->status_tag, | |
4748 | tnapi->hw_status->rx_jumbo_consumer, | |
4749 | tnapi->hw_status->rx_consumer, | |
4750 | tnapi->hw_status->rx_mini_consumer, | |
4751 | tnapi->hw_status->idx[0].rx_producer, | |
4752 | tnapi->hw_status->idx[0].tx_consumer); | |
4753 | ||
4754 | netdev_err(tp->dev, | |
4755 | "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n", | |
4756 | i, | |
4757 | tnapi->last_tag, tnapi->last_irq_tag, | |
4758 | tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending, | |
4759 | tnapi->rx_rcb_ptr, | |
4760 | tnapi->prodring.rx_std_prod_idx, | |
4761 | tnapi->prodring.rx_std_cons_idx, | |
4762 | tnapi->prodring.rx_jmb_prod_idx, | |
4763 | tnapi->prodring.rx_jmb_cons_idx); | |
4764 | } | |
4765 | } | |
4766 | ||
df3e6548 MC |
4767 | /* This is called whenever we suspect that the system chipset is re- |
4768 | * ordering the sequence of MMIO to the tx send mailbox. The symptom | |
4769 | * is bogus tx completions. We try to recover by setting the | |
4770 | * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later | |
4771 | * in the workqueue. | |
4772 | */ | |
4773 | static void tg3_tx_recover(struct tg3 *tp) | |
4774 | { | |
63c3a66f | 4775 | BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) || |
df3e6548 MC |
4776 | tp->write32_tx_mbox == tg3_write_indirect_mbox); |
4777 | ||
5129c3a3 MC |
4778 | netdev_warn(tp->dev, |
4779 | "The system may be re-ordering memory-mapped I/O " | |
4780 | "cycles to the network device, attempting to recover. " | |
4781 | "Please report the problem to the driver maintainer " | |
4782 | "and include system chipset information.\n"); | |
df3e6548 MC |
4783 | |
4784 | spin_lock(&tp->lock); | |
63c3a66f | 4785 | tg3_flag_set(tp, TX_RECOVERY_PENDING); |
df3e6548 MC |
4786 | spin_unlock(&tp->lock); |
4787 | } | |
4788 | ||
f3f3f27e | 4789 | static inline u32 tg3_tx_avail(struct tg3_napi *tnapi) |
1b2a7205 | 4790 | { |
f65aac16 MC |
4791 | /* Tell compiler to fetch tx indices from memory. */ |
4792 | barrier(); | |
f3f3f27e MC |
4793 | return tnapi->tx_pending - |
4794 | ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1)); | |
1b2a7205 MC |
4795 | } |
4796 | ||
1da177e4 LT |
4797 | /* Tigon3 never reports partial packet sends. So we do not |
4798 | * need special logic to handle SKBs that have not had all | |
4799 | * of their frags sent yet, like SunGEM does. | |
4800 | */ | |
17375d25 | 4801 | static void tg3_tx(struct tg3_napi *tnapi) |
1da177e4 | 4802 | { |
17375d25 | 4803 | struct tg3 *tp = tnapi->tp; |
898a56f8 | 4804 | u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer; |
f3f3f27e | 4805 | u32 sw_idx = tnapi->tx_cons; |
fe5f5787 MC |
4806 | struct netdev_queue *txq; |
4807 | int index = tnapi - tp->napi; | |
4808 | ||
63c3a66f | 4809 | if (tg3_flag(tp, ENABLE_TSS)) |
fe5f5787 MC |
4810 | index--; |
4811 | ||
4812 | txq = netdev_get_tx_queue(tp->dev, index); | |
1da177e4 LT |
4813 | |
4814 | while (sw_idx != hw_idx) { | |
f4188d8a | 4815 | struct ring_info *ri = &tnapi->tx_buffers[sw_idx]; |
1da177e4 | 4816 | struct sk_buff *skb = ri->skb; |
df3e6548 MC |
4817 | int i, tx_bug = 0; |
4818 | ||
4819 | if (unlikely(skb == NULL)) { | |
4820 | tg3_tx_recover(tp); | |
4821 | return; | |
4822 | } | |
1da177e4 | 4823 | |
f4188d8a | 4824 | pci_unmap_single(tp->pdev, |
4e5e4f0d | 4825 | dma_unmap_addr(ri, mapping), |
f4188d8a AD |
4826 | skb_headlen(skb), |
4827 | PCI_DMA_TODEVICE); | |
1da177e4 LT |
4828 | |
4829 | ri->skb = NULL; | |
4830 | ||
4831 | sw_idx = NEXT_TX(sw_idx); | |
4832 | ||
4833 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
f3f3f27e | 4834 | ri = &tnapi->tx_buffers[sw_idx]; |
df3e6548 MC |
4835 | if (unlikely(ri->skb != NULL || sw_idx == hw_idx)) |
4836 | tx_bug = 1; | |
f4188d8a AD |
4837 | |
4838 | pci_unmap_page(tp->pdev, | |
4e5e4f0d | 4839 | dma_unmap_addr(ri, mapping), |
f4188d8a AD |
4840 | skb_shinfo(skb)->frags[i].size, |
4841 | PCI_DMA_TODEVICE); | |
1da177e4 LT |
4842 | sw_idx = NEXT_TX(sw_idx); |
4843 | } | |
4844 | ||
f47c11ee | 4845 | dev_kfree_skb(skb); |
df3e6548 MC |
4846 | |
4847 | if (unlikely(tx_bug)) { | |
4848 | tg3_tx_recover(tp); | |
4849 | return; | |
4850 | } | |
1da177e4 LT |
4851 | } |
4852 | ||
f3f3f27e | 4853 | tnapi->tx_cons = sw_idx; |
1da177e4 | 4854 | |
1b2a7205 MC |
4855 | /* Need to make the tx_cons update visible to tg3_start_xmit() |
4856 | * before checking for netif_queue_stopped(). Without the | |
4857 | * memory barrier, there is a small possibility that tg3_start_xmit() | |
4858 | * will miss it and cause the queue to be stopped forever. | |
4859 | */ | |
4860 | smp_mb(); | |
4861 | ||
fe5f5787 | 4862 | if (unlikely(netif_tx_queue_stopped(txq) && |
f3f3f27e | 4863 | (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) { |
fe5f5787 MC |
4864 | __netif_tx_lock(txq, smp_processor_id()); |
4865 | if (netif_tx_queue_stopped(txq) && | |
f3f3f27e | 4866 | (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))) |
fe5f5787 MC |
4867 | netif_tx_wake_queue(txq); |
4868 | __netif_tx_unlock(txq); | |
51b91468 | 4869 | } |
1da177e4 LT |
4870 | } |
4871 | ||
2b2cdb65 MC |
4872 | static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz) |
4873 | { | |
4874 | if (!ri->skb) | |
4875 | return; | |
4876 | ||
4e5e4f0d | 4877 | pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping), |
2b2cdb65 MC |
4878 | map_sz, PCI_DMA_FROMDEVICE); |
4879 | dev_kfree_skb_any(ri->skb); | |
4880 | ri->skb = NULL; | |
4881 | } | |
4882 | ||
1da177e4 LT |
4883 | /* Returns size of skb allocated or < 0 on error. |
4884 | * | |
4885 | * We only need to fill in the address because the other members | |
4886 | * of the RX descriptor are invariant, see tg3_init_rings. | |
4887 | * | |
4888 | * Note the purposeful assymetry of cpu vs. chip accesses. For | |
4889 | * posting buffers we only dirty the first cache line of the RX | |
4890 | * descriptor (containing the address). Whereas for the RX status | |
4891 | * buffers the cpu only reads the last cacheline of the RX descriptor | |
4892 | * (to fetch the error flags, vlan tag, checksum, and opaque cookie). | |
4893 | */ | |
86b21e59 | 4894 | static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr, |
a3896167 | 4895 | u32 opaque_key, u32 dest_idx_unmasked) |
1da177e4 LT |
4896 | { |
4897 | struct tg3_rx_buffer_desc *desc; | |
f94e290e | 4898 | struct ring_info *map; |
1da177e4 LT |
4899 | struct sk_buff *skb; |
4900 | dma_addr_t mapping; | |
4901 | int skb_size, dest_idx; | |
4902 | ||
1da177e4 LT |
4903 | switch (opaque_key) { |
4904 | case RXD_OPAQUE_RING_STD: | |
2c49a44d | 4905 | dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; |
21f581a5 MC |
4906 | desc = &tpr->rx_std[dest_idx]; |
4907 | map = &tpr->rx_std_buffers[dest_idx]; | |
287be12e | 4908 | skb_size = tp->rx_pkt_map_sz; |
1da177e4 LT |
4909 | break; |
4910 | ||
4911 | case RXD_OPAQUE_RING_JUMBO: | |
2c49a44d | 4912 | dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; |
79ed5ac7 | 4913 | desc = &tpr->rx_jmb[dest_idx].std; |
21f581a5 | 4914 | map = &tpr->rx_jmb_buffers[dest_idx]; |
287be12e | 4915 | skb_size = TG3_RX_JMB_MAP_SZ; |
1da177e4 LT |
4916 | break; |
4917 | ||
4918 | default: | |
4919 | return -EINVAL; | |
855e1111 | 4920 | } |
1da177e4 LT |
4921 | |
4922 | /* Do not overwrite any of the map or rp information | |
4923 | * until we are sure we can commit to a new buffer. | |
4924 | * | |
4925 | * Callers depend upon this behavior and assume that | |
4926 | * we leave everything unchanged if we fail. | |
4927 | */ | |
287be12e | 4928 | skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset); |
1da177e4 LT |
4929 | if (skb == NULL) |
4930 | return -ENOMEM; | |
4931 | ||
1da177e4 LT |
4932 | skb_reserve(skb, tp->rx_offset); |
4933 | ||
287be12e | 4934 | mapping = pci_map_single(tp->pdev, skb->data, skb_size, |
1da177e4 | 4935 | PCI_DMA_FROMDEVICE); |
a21771dd MC |
4936 | if (pci_dma_mapping_error(tp->pdev, mapping)) { |
4937 | dev_kfree_skb(skb); | |
4938 | return -EIO; | |
4939 | } | |
1da177e4 LT |
4940 | |
4941 | map->skb = skb; | |
4e5e4f0d | 4942 | dma_unmap_addr_set(map, mapping, mapping); |
1da177e4 | 4943 | |
1da177e4 LT |
4944 | desc->addr_hi = ((u64)mapping >> 32); |
4945 | desc->addr_lo = ((u64)mapping & 0xffffffff); | |
4946 | ||
4947 | return skb_size; | |
4948 | } | |
4949 | ||
4950 | /* We only need to move over in the address because the other | |
4951 | * members of the RX descriptor are invariant. See notes above | |
4952 | * tg3_alloc_rx_skb for full details. | |
4953 | */ | |
a3896167 MC |
4954 | static void tg3_recycle_rx(struct tg3_napi *tnapi, |
4955 | struct tg3_rx_prodring_set *dpr, | |
4956 | u32 opaque_key, int src_idx, | |
4957 | u32 dest_idx_unmasked) | |
1da177e4 | 4958 | { |
17375d25 | 4959 | struct tg3 *tp = tnapi->tp; |
1da177e4 LT |
4960 | struct tg3_rx_buffer_desc *src_desc, *dest_desc; |
4961 | struct ring_info *src_map, *dest_map; | |
8fea32b9 | 4962 | struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring; |
c6cdf436 | 4963 | int dest_idx; |
1da177e4 LT |
4964 | |
4965 | switch (opaque_key) { | |
4966 | case RXD_OPAQUE_RING_STD: | |
2c49a44d | 4967 | dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; |
a3896167 MC |
4968 | dest_desc = &dpr->rx_std[dest_idx]; |
4969 | dest_map = &dpr->rx_std_buffers[dest_idx]; | |
4970 | src_desc = &spr->rx_std[src_idx]; | |
4971 | src_map = &spr->rx_std_buffers[src_idx]; | |
1da177e4 LT |
4972 | break; |
4973 | ||
4974 | case RXD_OPAQUE_RING_JUMBO: | |
2c49a44d | 4975 | dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; |
a3896167 MC |
4976 | dest_desc = &dpr->rx_jmb[dest_idx].std; |
4977 | dest_map = &dpr->rx_jmb_buffers[dest_idx]; | |
4978 | src_desc = &spr->rx_jmb[src_idx].std; | |
4979 | src_map = &spr->rx_jmb_buffers[src_idx]; | |
1da177e4 LT |
4980 | break; |
4981 | ||
4982 | default: | |
4983 | return; | |
855e1111 | 4984 | } |
1da177e4 LT |
4985 | |
4986 | dest_map->skb = src_map->skb; | |
4e5e4f0d FT |
4987 | dma_unmap_addr_set(dest_map, mapping, |
4988 | dma_unmap_addr(src_map, mapping)); | |
1da177e4 LT |
4989 | dest_desc->addr_hi = src_desc->addr_hi; |
4990 | dest_desc->addr_lo = src_desc->addr_lo; | |
e92967bf MC |
4991 | |
4992 | /* Ensure that the update to the skb happens after the physical | |
4993 | * addresses have been transferred to the new BD location. | |
4994 | */ | |
4995 | smp_wmb(); | |
4996 | ||
1da177e4 LT |
4997 | src_map->skb = NULL; |
4998 | } | |
4999 | ||
1da177e4 LT |
5000 | /* The RX ring scheme is composed of multiple rings which post fresh |
5001 | * buffers to the chip, and one special ring the chip uses to report | |
5002 | * status back to the host. | |
5003 | * | |
5004 | * The special ring reports the status of received packets to the | |
5005 | * host. The chip does not write into the original descriptor the | |
5006 | * RX buffer was obtained from. The chip simply takes the original | |
5007 | * descriptor as provided by the host, updates the status and length | |
5008 | * field, then writes this into the next status ring entry. | |
5009 | * | |
5010 | * Each ring the host uses to post buffers to the chip is described | |
5011 | * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives, | |
5012 | * it is first placed into the on-chip ram. When the packet's length | |
5013 | * is known, it walks down the TG3_BDINFO entries to select the ring. | |
5014 | * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO | |
5015 | * which is within the range of the new packet's length is chosen. | |
5016 | * | |
5017 | * The "separate ring for rx status" scheme may sound queer, but it makes | |
5018 | * sense from a cache coherency perspective. If only the host writes | |
5019 | * to the buffer post rings, and only the chip writes to the rx status | |
5020 | * rings, then cache lines never move beyond shared-modified state. | |
5021 | * If both the host and chip were to write into the same ring, cache line | |
5022 | * eviction could occur since both entities want it in an exclusive state. | |
5023 | */ | |
17375d25 | 5024 | static int tg3_rx(struct tg3_napi *tnapi, int budget) |
1da177e4 | 5025 | { |
17375d25 | 5026 | struct tg3 *tp = tnapi->tp; |
f92905de | 5027 | u32 work_mask, rx_std_posted = 0; |
4361935a | 5028 | u32 std_prod_idx, jmb_prod_idx; |
72334482 | 5029 | u32 sw_idx = tnapi->rx_rcb_ptr; |
483ba50b | 5030 | u16 hw_idx; |
1da177e4 | 5031 | int received; |
8fea32b9 | 5032 | struct tg3_rx_prodring_set *tpr = &tnapi->prodring; |
1da177e4 | 5033 | |
8d9d7cfc | 5034 | hw_idx = *(tnapi->rx_rcb_prod_idx); |
1da177e4 LT |
5035 | /* |
5036 | * We need to order the read of hw_idx and the read of | |
5037 | * the opaque cookie. | |
5038 | */ | |
5039 | rmb(); | |
1da177e4 LT |
5040 | work_mask = 0; |
5041 | received = 0; | |
4361935a MC |
5042 | std_prod_idx = tpr->rx_std_prod_idx; |
5043 | jmb_prod_idx = tpr->rx_jmb_prod_idx; | |
1da177e4 | 5044 | while (sw_idx != hw_idx && budget > 0) { |
afc081f8 | 5045 | struct ring_info *ri; |
72334482 | 5046 | struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx]; |
1da177e4 LT |
5047 | unsigned int len; |
5048 | struct sk_buff *skb; | |
5049 | dma_addr_t dma_addr; | |
5050 | u32 opaque_key, desc_idx, *post_ptr; | |
5051 | ||
5052 | desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; | |
5053 | opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; | |
5054 | if (opaque_key == RXD_OPAQUE_RING_STD) { | |
8fea32b9 | 5055 | ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx]; |
4e5e4f0d | 5056 | dma_addr = dma_unmap_addr(ri, mapping); |
21f581a5 | 5057 | skb = ri->skb; |
4361935a | 5058 | post_ptr = &std_prod_idx; |
f92905de | 5059 | rx_std_posted++; |
1da177e4 | 5060 | } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) { |
8fea32b9 | 5061 | ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx]; |
4e5e4f0d | 5062 | dma_addr = dma_unmap_addr(ri, mapping); |
21f581a5 | 5063 | skb = ri->skb; |
4361935a | 5064 | post_ptr = &jmb_prod_idx; |
21f581a5 | 5065 | } else |
1da177e4 | 5066 | goto next_pkt_nopost; |
1da177e4 LT |
5067 | |
5068 | work_mask |= opaque_key; | |
5069 | ||
5070 | if ((desc->err_vlan & RXD_ERR_MASK) != 0 && | |
5071 | (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) { | |
5072 | drop_it: | |
a3896167 | 5073 | tg3_recycle_rx(tnapi, tpr, opaque_key, |
1da177e4 LT |
5074 | desc_idx, *post_ptr); |
5075 | drop_it_no_recycle: | |
5076 | /* Other statistics kept track of by card. */ | |
b0057c51 | 5077 | tp->rx_dropped++; |
1da177e4 LT |
5078 | goto next_pkt; |
5079 | } | |
5080 | ||
ad829268 MC |
5081 | len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - |
5082 | ETH_FCS_LEN; | |
1da177e4 | 5083 | |
d2757fc4 | 5084 | if (len > TG3_RX_COPY_THRESH(tp)) { |
1da177e4 LT |
5085 | int skb_size; |
5086 | ||
86b21e59 | 5087 | skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key, |
afc081f8 | 5088 | *post_ptr); |
1da177e4 LT |
5089 | if (skb_size < 0) |
5090 | goto drop_it; | |
5091 | ||
287be12e | 5092 | pci_unmap_single(tp->pdev, dma_addr, skb_size, |
1da177e4 LT |
5093 | PCI_DMA_FROMDEVICE); |
5094 | ||
61e800cf MC |
5095 | /* Ensure that the update to the skb happens |
5096 | * after the usage of the old DMA mapping. | |
5097 | */ | |
5098 | smp_wmb(); | |
5099 | ||
5100 | ri->skb = NULL; | |
5101 | ||
1da177e4 LT |
5102 | skb_put(skb, len); |
5103 | } else { | |
5104 | struct sk_buff *copy_skb; | |
5105 | ||
a3896167 | 5106 | tg3_recycle_rx(tnapi, tpr, opaque_key, |
1da177e4 LT |
5107 | desc_idx, *post_ptr); |
5108 | ||
bf933c80 | 5109 | copy_skb = netdev_alloc_skb(tp->dev, len + |
9dc7a113 | 5110 | TG3_RAW_IP_ALIGN); |
1da177e4 LT |
5111 | if (copy_skb == NULL) |
5112 | goto drop_it_no_recycle; | |
5113 | ||
bf933c80 | 5114 | skb_reserve(copy_skb, TG3_RAW_IP_ALIGN); |
1da177e4 LT |
5115 | skb_put(copy_skb, len); |
5116 | pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); | |
d626f62b | 5117 | skb_copy_from_linear_data(skb, copy_skb->data, len); |
1da177e4 LT |
5118 | pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); |
5119 | ||
5120 | /* We'll reuse the original ring buffer. */ | |
5121 | skb = copy_skb; | |
5122 | } | |
5123 | ||
dc668910 | 5124 | if ((tp->dev->features & NETIF_F_RXCSUM) && |
1da177e4 LT |
5125 | (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) && |
5126 | (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK) | |
5127 | >> RXD_TCPCSUM_SHIFT) == 0xffff)) | |
5128 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
5129 | else | |
bc8acf2c | 5130 | skb_checksum_none_assert(skb); |
1da177e4 LT |
5131 | |
5132 | skb->protocol = eth_type_trans(skb, tp->dev); | |
f7b493e0 MC |
5133 | |
5134 | if (len > (tp->dev->mtu + ETH_HLEN) && | |
5135 | skb->protocol != htons(ETH_P_8021Q)) { | |
5136 | dev_kfree_skb(skb); | |
b0057c51 | 5137 | goto drop_it_no_recycle; |
f7b493e0 MC |
5138 | } |
5139 | ||
9dc7a113 | 5140 | if (desc->type_flags & RXD_FLAG_VLAN && |
bf933c80 MC |
5141 | !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) |
5142 | __vlan_hwaccel_put_tag(skb, | |
5143 | desc->err_vlan & RXD_VLAN_MASK); | |
9dc7a113 | 5144 | |
bf933c80 | 5145 | napi_gro_receive(&tnapi->napi, skb); |
1da177e4 | 5146 | |
1da177e4 LT |
5147 | received++; |
5148 | budget--; | |
5149 | ||
5150 | next_pkt: | |
5151 | (*post_ptr)++; | |
f92905de MC |
5152 | |
5153 | if (unlikely(rx_std_posted >= tp->rx_std_max_post)) { | |
2c49a44d MC |
5154 | tpr->rx_std_prod_idx = std_prod_idx & |
5155 | tp->rx_std_ring_mask; | |
86cfe4ff MC |
5156 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, |
5157 | tpr->rx_std_prod_idx); | |
f92905de MC |
5158 | work_mask &= ~RXD_OPAQUE_RING_STD; |
5159 | rx_std_posted = 0; | |
5160 | } | |
1da177e4 | 5161 | next_pkt_nopost: |
483ba50b | 5162 | sw_idx++; |
7cb32cf2 | 5163 | sw_idx &= tp->rx_ret_ring_mask; |
52f6d697 MC |
5164 | |
5165 | /* Refresh hw_idx to see if there is new work */ | |
5166 | if (sw_idx == hw_idx) { | |
8d9d7cfc | 5167 | hw_idx = *(tnapi->rx_rcb_prod_idx); |
52f6d697 MC |
5168 | rmb(); |
5169 | } | |
1da177e4 LT |
5170 | } |
5171 | ||
5172 | /* ACK the status ring. */ | |
72334482 MC |
5173 | tnapi->rx_rcb_ptr = sw_idx; |
5174 | tw32_rx_mbox(tnapi->consmbox, sw_idx); | |
1da177e4 LT |
5175 | |
5176 | /* Refill RX ring(s). */ | |
63c3a66f | 5177 | if (!tg3_flag(tp, ENABLE_RSS)) { |
b196c7e4 | 5178 | if (work_mask & RXD_OPAQUE_RING_STD) { |
2c49a44d MC |
5179 | tpr->rx_std_prod_idx = std_prod_idx & |
5180 | tp->rx_std_ring_mask; | |
b196c7e4 MC |
5181 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, |
5182 | tpr->rx_std_prod_idx); | |
5183 | } | |
5184 | if (work_mask & RXD_OPAQUE_RING_JUMBO) { | |
2c49a44d MC |
5185 | tpr->rx_jmb_prod_idx = jmb_prod_idx & |
5186 | tp->rx_jmb_ring_mask; | |
b196c7e4 MC |
5187 | tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, |
5188 | tpr->rx_jmb_prod_idx); | |
5189 | } | |
5190 | mmiowb(); | |
5191 | } else if (work_mask) { | |
5192 | /* rx_std_buffers[] and rx_jmb_buffers[] entries must be | |
5193 | * updated before the producer indices can be updated. | |
5194 | */ | |
5195 | smp_wmb(); | |
5196 | ||
2c49a44d MC |
5197 | tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask; |
5198 | tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask; | |
b196c7e4 | 5199 | |
e4af1af9 MC |
5200 | if (tnapi != &tp->napi[1]) |
5201 | napi_schedule(&tp->napi[1].napi); | |
1da177e4 | 5202 | } |
1da177e4 LT |
5203 | |
5204 | return received; | |
5205 | } | |
5206 | ||
35f2d7d0 | 5207 | static void tg3_poll_link(struct tg3 *tp) |
1da177e4 | 5208 | { |
1da177e4 | 5209 | /* handle link change and other phy events */ |
63c3a66f | 5210 | if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) { |
35f2d7d0 MC |
5211 | struct tg3_hw_status *sblk = tp->napi[0].hw_status; |
5212 | ||
1da177e4 LT |
5213 | if (sblk->status & SD_STATUS_LINK_CHG) { |
5214 | sblk->status = SD_STATUS_UPDATED | | |
35f2d7d0 | 5215 | (sblk->status & ~SD_STATUS_LINK_CHG); |
f47c11ee | 5216 | spin_lock(&tp->lock); |
63c3a66f | 5217 | if (tg3_flag(tp, USE_PHYLIB)) { |
dd477003 MC |
5218 | tw32_f(MAC_STATUS, |
5219 | (MAC_STATUS_SYNC_CHANGED | | |
5220 | MAC_STATUS_CFG_CHANGED | | |
5221 | MAC_STATUS_MI_COMPLETION | | |
5222 | MAC_STATUS_LNKSTATE_CHANGED)); | |
5223 | udelay(40); | |
5224 | } else | |
5225 | tg3_setup_phy(tp, 0); | |
f47c11ee | 5226 | spin_unlock(&tp->lock); |
1da177e4 LT |
5227 | } |
5228 | } | |
35f2d7d0 MC |
5229 | } |
5230 | ||
f89f38b8 MC |
5231 | static int tg3_rx_prodring_xfer(struct tg3 *tp, |
5232 | struct tg3_rx_prodring_set *dpr, | |
5233 | struct tg3_rx_prodring_set *spr) | |
b196c7e4 MC |
5234 | { |
5235 | u32 si, di, cpycnt, src_prod_idx; | |
f89f38b8 | 5236 | int i, err = 0; |
b196c7e4 MC |
5237 | |
5238 | while (1) { | |
5239 | src_prod_idx = spr->rx_std_prod_idx; | |
5240 | ||
5241 | /* Make sure updates to the rx_std_buffers[] entries and the | |
5242 | * standard producer index are seen in the correct order. | |
5243 | */ | |
5244 | smp_rmb(); | |
5245 | ||
5246 | if (spr->rx_std_cons_idx == src_prod_idx) | |
5247 | break; | |
5248 | ||
5249 | if (spr->rx_std_cons_idx < src_prod_idx) | |
5250 | cpycnt = src_prod_idx - spr->rx_std_cons_idx; | |
5251 | else | |
2c49a44d MC |
5252 | cpycnt = tp->rx_std_ring_mask + 1 - |
5253 | spr->rx_std_cons_idx; | |
b196c7e4 | 5254 | |
2c49a44d MC |
5255 | cpycnt = min(cpycnt, |
5256 | tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx); | |
b196c7e4 MC |
5257 | |
5258 | si = spr->rx_std_cons_idx; | |
5259 | di = dpr->rx_std_prod_idx; | |
5260 | ||
e92967bf MC |
5261 | for (i = di; i < di + cpycnt; i++) { |
5262 | if (dpr->rx_std_buffers[i].skb) { | |
5263 | cpycnt = i - di; | |
f89f38b8 | 5264 | err = -ENOSPC; |
e92967bf MC |
5265 | break; |
5266 | } | |
5267 | } | |
5268 | ||
5269 | if (!cpycnt) | |
5270 | break; | |
5271 | ||
5272 | /* Ensure that updates to the rx_std_buffers ring and the | |
5273 | * shadowed hardware producer ring from tg3_recycle_skb() are | |
5274 | * ordered correctly WRT the skb check above. | |
5275 | */ | |
5276 | smp_rmb(); | |
5277 | ||
b196c7e4 MC |
5278 | memcpy(&dpr->rx_std_buffers[di], |
5279 | &spr->rx_std_buffers[si], | |
5280 | cpycnt * sizeof(struct ring_info)); | |
5281 | ||
5282 | for (i = 0; i < cpycnt; i++, di++, si++) { | |
5283 | struct tg3_rx_buffer_desc *sbd, *dbd; | |
5284 | sbd = &spr->rx_std[si]; | |
5285 | dbd = &dpr->rx_std[di]; | |
5286 | dbd->addr_hi = sbd->addr_hi; | |
5287 | dbd->addr_lo = sbd->addr_lo; | |
5288 | } | |
5289 | ||
2c49a44d MC |
5290 | spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) & |
5291 | tp->rx_std_ring_mask; | |
5292 | dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) & | |
5293 | tp->rx_std_ring_mask; | |
b196c7e4 MC |
5294 | } |
5295 | ||
5296 | while (1) { | |
5297 | src_prod_idx = spr->rx_jmb_prod_idx; | |
5298 | ||
5299 | /* Make sure updates to the rx_jmb_buffers[] entries and | |
5300 | * the jumbo producer index are seen in the correct order. | |
5301 | */ | |
5302 | smp_rmb(); | |
5303 | ||
5304 | if (spr->rx_jmb_cons_idx == src_prod_idx) | |
5305 | break; | |
5306 | ||
5307 | if (spr->rx_jmb_cons_idx < src_prod_idx) | |
5308 | cpycnt = src_prod_idx - spr->rx_jmb_cons_idx; | |
5309 | else | |
2c49a44d MC |
5310 | cpycnt = tp->rx_jmb_ring_mask + 1 - |
5311 | spr->rx_jmb_cons_idx; | |
b196c7e4 MC |
5312 | |
5313 | cpycnt = min(cpycnt, | |
2c49a44d | 5314 | tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx); |
b196c7e4 MC |
5315 | |
5316 | si = spr->rx_jmb_cons_idx; | |
5317 | di = dpr->rx_jmb_prod_idx; | |
5318 | ||
e92967bf MC |
5319 | for (i = di; i < di + cpycnt; i++) { |
5320 | if (dpr->rx_jmb_buffers[i].skb) { | |
5321 | cpycnt = i - di; | |
f89f38b8 | 5322 | err = -ENOSPC; |
e92967bf MC |
5323 | break; |
5324 | } | |
5325 | } | |
5326 | ||
5327 | if (!cpycnt) | |
5328 | break; | |
5329 | ||
5330 | /* Ensure that updates to the rx_jmb_buffers ring and the | |
5331 | * shadowed hardware producer ring from tg3_recycle_skb() are | |
5332 | * ordered correctly WRT the skb check above. | |
5333 | */ | |
5334 | smp_rmb(); | |
5335 | ||
b196c7e4 MC |
5336 | memcpy(&dpr->rx_jmb_buffers[di], |
5337 | &spr->rx_jmb_buffers[si], | |
5338 | cpycnt * sizeof(struct ring_info)); | |
5339 | ||
5340 | for (i = 0; i < cpycnt; i++, di++, si++) { | |
5341 | struct tg3_rx_buffer_desc *sbd, *dbd; | |
5342 | sbd = &spr->rx_jmb[si].std; | |
5343 | dbd = &dpr->rx_jmb[di].std; | |
5344 | dbd->addr_hi = sbd->addr_hi; | |
5345 | dbd->addr_lo = sbd->addr_lo; | |
5346 | } | |
5347 | ||
2c49a44d MC |
5348 | spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) & |
5349 | tp->rx_jmb_ring_mask; | |
5350 | dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) & | |
5351 | tp->rx_jmb_ring_mask; | |
b196c7e4 | 5352 | } |
f89f38b8 MC |
5353 | |
5354 | return err; | |
b196c7e4 MC |
5355 | } |
5356 | ||
35f2d7d0 MC |
5357 | static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget) |
5358 | { | |
5359 | struct tg3 *tp = tnapi->tp; | |
1da177e4 LT |
5360 | |
5361 | /* run TX completion thread */ | |
f3f3f27e | 5362 | if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) { |
17375d25 | 5363 | tg3_tx(tnapi); |
63c3a66f | 5364 | if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) |
4fd7ab59 | 5365 | return work_done; |
1da177e4 LT |
5366 | } |
5367 | ||
1da177e4 LT |
5368 | /* run RX thread, within the bounds set by NAPI. |
5369 | * All RX "locking" is done by ensuring outside | |
bea3348e | 5370 | * code synchronizes with tg3->napi.poll() |
1da177e4 | 5371 | */ |
8d9d7cfc | 5372 | if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr) |
17375d25 | 5373 | work_done += tg3_rx(tnapi, budget - work_done); |
1da177e4 | 5374 | |
63c3a66f | 5375 | if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) { |
8fea32b9 | 5376 | struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring; |
f89f38b8 | 5377 | int i, err = 0; |
e4af1af9 MC |
5378 | u32 std_prod_idx = dpr->rx_std_prod_idx; |
5379 | u32 jmb_prod_idx = dpr->rx_jmb_prod_idx; | |
b196c7e4 | 5380 | |
e4af1af9 | 5381 | for (i = 1; i < tp->irq_cnt; i++) |
f89f38b8 | 5382 | err |= tg3_rx_prodring_xfer(tp, dpr, |
8fea32b9 | 5383 | &tp->napi[i].prodring); |
b196c7e4 MC |
5384 | |
5385 | wmb(); | |
5386 | ||
e4af1af9 MC |
5387 | if (std_prod_idx != dpr->rx_std_prod_idx) |
5388 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, | |
5389 | dpr->rx_std_prod_idx); | |
b196c7e4 | 5390 | |
e4af1af9 MC |
5391 | if (jmb_prod_idx != dpr->rx_jmb_prod_idx) |
5392 | tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, | |
5393 | dpr->rx_jmb_prod_idx); | |
b196c7e4 MC |
5394 | |
5395 | mmiowb(); | |
f89f38b8 MC |
5396 | |
5397 | if (err) | |
5398 | tw32_f(HOSTCC_MODE, tp->coal_now); | |
b196c7e4 MC |
5399 | } |
5400 | ||
6f535763 DM |
5401 | return work_done; |
5402 | } | |
5403 | ||
35f2d7d0 MC |
5404 | static int tg3_poll_msix(struct napi_struct *napi, int budget) |
5405 | { | |
5406 | struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi); | |
5407 | struct tg3 *tp = tnapi->tp; | |
5408 | int work_done = 0; | |
5409 | struct tg3_hw_status *sblk = tnapi->hw_status; | |
5410 | ||
5411 | while (1) { | |
5412 | work_done = tg3_poll_work(tnapi, work_done, budget); | |
5413 | ||
63c3a66f | 5414 | if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) |
35f2d7d0 MC |
5415 | goto tx_recovery; |
5416 | ||
5417 | if (unlikely(work_done >= budget)) | |
5418 | break; | |
5419 | ||
c6cdf436 | 5420 | /* tp->last_tag is used in tg3_int_reenable() below |
35f2d7d0 MC |
5421 | * to tell the hw how much work has been processed, |
5422 | * so we must read it before checking for more work. | |
5423 | */ | |
5424 | tnapi->last_tag = sblk->status_tag; | |
5425 | tnapi->last_irq_tag = tnapi->last_tag; | |
5426 | rmb(); | |
5427 | ||
5428 | /* check for RX/TX work to do */ | |
6d40db7b MC |
5429 | if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons && |
5430 | *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) { | |
35f2d7d0 MC |
5431 | napi_complete(napi); |
5432 | /* Reenable interrupts. */ | |
5433 | tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); | |
5434 | mmiowb(); | |
5435 | break; | |
5436 | } | |
5437 | } | |
5438 | ||
5439 | return work_done; | |
5440 | ||
5441 | tx_recovery: | |
5442 | /* work_done is guaranteed to be less than budget. */ | |
5443 | napi_complete(napi); | |
5444 | schedule_work(&tp->reset_task); | |
5445 | return work_done; | |
5446 | } | |
5447 | ||
e64de4e6 MC |
5448 | static void tg3_process_error(struct tg3 *tp) |
5449 | { | |
5450 | u32 val; | |
5451 | bool real_error = false; | |
5452 | ||
63c3a66f | 5453 | if (tg3_flag(tp, ERROR_PROCESSED)) |
e64de4e6 MC |
5454 | return; |
5455 | ||
5456 | /* Check Flow Attention register */ | |
5457 | val = tr32(HOSTCC_FLOW_ATTN); | |
5458 | if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) { | |
5459 | netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n"); | |
5460 | real_error = true; | |
5461 | } | |
5462 | ||
5463 | if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) { | |
5464 | netdev_err(tp->dev, "MSI Status error. Resetting chip.\n"); | |
5465 | real_error = true; | |
5466 | } | |
5467 | ||
5468 | if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) { | |
5469 | netdev_err(tp->dev, "DMA Status error. Resetting chip.\n"); | |
5470 | real_error = true; | |
5471 | } | |
5472 | ||
5473 | if (!real_error) | |
5474 | return; | |
5475 | ||
5476 | tg3_dump_state(tp); | |
5477 | ||
63c3a66f | 5478 | tg3_flag_set(tp, ERROR_PROCESSED); |
e64de4e6 MC |
5479 | schedule_work(&tp->reset_task); |
5480 | } | |
5481 | ||
6f535763 DM |
5482 | static int tg3_poll(struct napi_struct *napi, int budget) |
5483 | { | |
8ef0442f MC |
5484 | struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi); |
5485 | struct tg3 *tp = tnapi->tp; | |
6f535763 | 5486 | int work_done = 0; |
898a56f8 | 5487 | struct tg3_hw_status *sblk = tnapi->hw_status; |
6f535763 DM |
5488 | |
5489 | while (1) { | |
e64de4e6 MC |
5490 | if (sblk->status & SD_STATUS_ERROR) |
5491 | tg3_process_error(tp); | |
5492 | ||
35f2d7d0 MC |
5493 | tg3_poll_link(tp); |
5494 | ||
17375d25 | 5495 | work_done = tg3_poll_work(tnapi, work_done, budget); |
6f535763 | 5496 | |
63c3a66f | 5497 | if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) |
6f535763 DM |
5498 | goto tx_recovery; |
5499 | ||
5500 | if (unlikely(work_done >= budget)) | |
5501 | break; | |
5502 | ||
63c3a66f | 5503 | if (tg3_flag(tp, TAGGED_STATUS)) { |
17375d25 | 5504 | /* tp->last_tag is used in tg3_int_reenable() below |
4fd7ab59 MC |
5505 | * to tell the hw how much work has been processed, |
5506 | * so we must read it before checking for more work. | |
5507 | */ | |
898a56f8 MC |
5508 | tnapi->last_tag = sblk->status_tag; |
5509 | tnapi->last_irq_tag = tnapi->last_tag; | |
4fd7ab59 MC |
5510 | rmb(); |
5511 | } else | |
5512 | sblk->status &= ~SD_STATUS_UPDATED; | |
6f535763 | 5513 | |
17375d25 | 5514 | if (likely(!tg3_has_work(tnapi))) { |
288379f0 | 5515 | napi_complete(napi); |
17375d25 | 5516 | tg3_int_reenable(tnapi); |
6f535763 DM |
5517 | break; |
5518 | } | |
1da177e4 LT |
5519 | } |
5520 | ||
bea3348e | 5521 | return work_done; |
6f535763 DM |
5522 | |
5523 | tx_recovery: | |
4fd7ab59 | 5524 | /* work_done is guaranteed to be less than budget. */ |
288379f0 | 5525 | napi_complete(napi); |
6f535763 | 5526 | schedule_work(&tp->reset_task); |
4fd7ab59 | 5527 | return work_done; |
1da177e4 LT |
5528 | } |
5529 | ||
66cfd1bd MC |
5530 | static void tg3_napi_disable(struct tg3 *tp) |
5531 | { | |
5532 | int i; | |
5533 | ||
5534 | for (i = tp->irq_cnt - 1; i >= 0; i--) | |
5535 | napi_disable(&tp->napi[i].napi); | |
5536 | } | |
5537 | ||
5538 | static void tg3_napi_enable(struct tg3 *tp) | |
5539 | { | |
5540 | int i; | |
5541 | ||
5542 | for (i = 0; i < tp->irq_cnt; i++) | |
5543 | napi_enable(&tp->napi[i].napi); | |
5544 | } | |
5545 | ||
5546 | static void tg3_napi_init(struct tg3 *tp) | |
5547 | { | |
5548 | int i; | |
5549 | ||
5550 | netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64); | |
5551 | for (i = 1; i < tp->irq_cnt; i++) | |
5552 | netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64); | |
5553 | } | |
5554 | ||
5555 | static void tg3_napi_fini(struct tg3 *tp) | |
5556 | { | |
5557 | int i; | |
5558 | ||
5559 | for (i = 0; i < tp->irq_cnt; i++) | |
5560 | netif_napi_del(&tp->napi[i].napi); | |
5561 | } | |
5562 | ||
5563 | static inline void tg3_netif_stop(struct tg3 *tp) | |
5564 | { | |
5565 | tp->dev->trans_start = jiffies; /* prevent tx timeout */ | |
5566 | tg3_napi_disable(tp); | |
5567 | netif_tx_disable(tp->dev); | |
5568 | } | |
5569 | ||
5570 | static inline void tg3_netif_start(struct tg3 *tp) | |
5571 | { | |
5572 | /* NOTE: unconditional netif_tx_wake_all_queues is only | |
5573 | * appropriate so long as all callers are assured to | |
5574 | * have free tx slots (such as after tg3_init_hw) | |
5575 | */ | |
5576 | netif_tx_wake_all_queues(tp->dev); | |
5577 | ||
5578 | tg3_napi_enable(tp); | |
5579 | tp->napi[0].hw_status->status |= SD_STATUS_UPDATED; | |
5580 | tg3_enable_ints(tp); | |
5581 | } | |
5582 | ||
f47c11ee DM |
5583 | static void tg3_irq_quiesce(struct tg3 *tp) |
5584 | { | |
4f125f42 MC |
5585 | int i; |
5586 | ||
f47c11ee DM |
5587 | BUG_ON(tp->irq_sync); |
5588 | ||
5589 | tp->irq_sync = 1; | |
5590 | smp_mb(); | |
5591 | ||
4f125f42 MC |
5592 | for (i = 0; i < tp->irq_cnt; i++) |
5593 | synchronize_irq(tp->napi[i].irq_vec); | |
f47c11ee DM |
5594 | } |
5595 | ||
f47c11ee DM |
5596 | /* Fully shutdown all tg3 driver activity elsewhere in the system. |
5597 | * If irq_sync is non-zero, then the IRQ handler must be synchronized | |
5598 | * with as well. Most of the time, this is not necessary except when | |
5599 | * shutting down the device. | |
5600 | */ | |
5601 | static inline void tg3_full_lock(struct tg3 *tp, int irq_sync) | |
5602 | { | |
46966545 | 5603 | spin_lock_bh(&tp->lock); |
f47c11ee DM |
5604 | if (irq_sync) |
5605 | tg3_irq_quiesce(tp); | |
f47c11ee DM |
5606 | } |
5607 | ||
5608 | static inline void tg3_full_unlock(struct tg3 *tp) | |
5609 | { | |
f47c11ee DM |
5610 | spin_unlock_bh(&tp->lock); |
5611 | } | |
5612 | ||
fcfa0a32 MC |
5613 | /* One-shot MSI handler - Chip automatically disables interrupt |
5614 | * after sending MSI so driver doesn't have to do it. | |
5615 | */ | |
7d12e780 | 5616 | static irqreturn_t tg3_msi_1shot(int irq, void *dev_id) |
fcfa0a32 | 5617 | { |
09943a18 MC |
5618 | struct tg3_napi *tnapi = dev_id; |
5619 | struct tg3 *tp = tnapi->tp; | |
fcfa0a32 | 5620 | |
898a56f8 | 5621 | prefetch(tnapi->hw_status); |
0c1d0e2b MC |
5622 | if (tnapi->rx_rcb) |
5623 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); | |
fcfa0a32 MC |
5624 | |
5625 | if (likely(!tg3_irq_sync(tp))) | |
09943a18 | 5626 | napi_schedule(&tnapi->napi); |
fcfa0a32 MC |
5627 | |
5628 | return IRQ_HANDLED; | |
5629 | } | |
5630 | ||
88b06bc2 MC |
5631 | /* MSI ISR - No need to check for interrupt sharing and no need to |
5632 | * flush status block and interrupt mailbox. PCI ordering rules | |
5633 | * guarantee that MSI will arrive after the status block. | |
5634 | */ | |
7d12e780 | 5635 | static irqreturn_t tg3_msi(int irq, void *dev_id) |
88b06bc2 | 5636 | { |
09943a18 MC |
5637 | struct tg3_napi *tnapi = dev_id; |
5638 | struct tg3 *tp = tnapi->tp; | |
88b06bc2 | 5639 | |
898a56f8 | 5640 | prefetch(tnapi->hw_status); |
0c1d0e2b MC |
5641 | if (tnapi->rx_rcb) |
5642 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); | |
88b06bc2 | 5643 | /* |
fac9b83e | 5644 | * Writing any value to intr-mbox-0 clears PCI INTA# and |
88b06bc2 | 5645 | * chip-internal interrupt pending events. |
fac9b83e | 5646 | * Writing non-zero to intr-mbox-0 additional tells the |
88b06bc2 MC |
5647 | * NIC to stop sending us irqs, engaging "in-intr-handler" |
5648 | * event coalescing. | |
5649 | */ | |
5650 | tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); | |
61487480 | 5651 | if (likely(!tg3_irq_sync(tp))) |
09943a18 | 5652 | napi_schedule(&tnapi->napi); |
61487480 | 5653 | |
88b06bc2 MC |
5654 | return IRQ_RETVAL(1); |
5655 | } | |
5656 | ||
7d12e780 | 5657 | static irqreturn_t tg3_interrupt(int irq, void *dev_id) |
1da177e4 | 5658 | { |
09943a18 MC |
5659 | struct tg3_napi *tnapi = dev_id; |
5660 | struct tg3 *tp = tnapi->tp; | |
898a56f8 | 5661 | struct tg3_hw_status *sblk = tnapi->hw_status; |
1da177e4 LT |
5662 | unsigned int handled = 1; |
5663 | ||
1da177e4 LT |
5664 | /* In INTx mode, it is possible for the interrupt to arrive at |
5665 | * the CPU before the status block posted prior to the interrupt. | |
5666 | * Reading the PCI State register will confirm whether the | |
5667 | * interrupt is ours and will flush the status block. | |
5668 | */ | |
d18edcb2 | 5669 | if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) { |
63c3a66f | 5670 | if (tg3_flag(tp, CHIP_RESETTING) || |
d18edcb2 MC |
5671 | (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { |
5672 | handled = 0; | |
f47c11ee | 5673 | goto out; |
fac9b83e | 5674 | } |
d18edcb2 MC |
5675 | } |
5676 | ||
5677 | /* | |
5678 | * Writing any value to intr-mbox-0 clears PCI INTA# and | |
5679 | * chip-internal interrupt pending events. | |
5680 | * Writing non-zero to intr-mbox-0 additional tells the | |
5681 | * NIC to stop sending us irqs, engaging "in-intr-handler" | |
5682 | * event coalescing. | |
c04cb347 MC |
5683 | * |
5684 | * Flush the mailbox to de-assert the IRQ immediately to prevent | |
5685 | * spurious interrupts. The flush impacts performance but | |
5686 | * excessive spurious interrupts can be worse in some cases. | |
d18edcb2 | 5687 | */ |
c04cb347 | 5688 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); |
d18edcb2 MC |
5689 | if (tg3_irq_sync(tp)) |
5690 | goto out; | |
5691 | sblk->status &= ~SD_STATUS_UPDATED; | |
17375d25 | 5692 | if (likely(tg3_has_work(tnapi))) { |
72334482 | 5693 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); |
09943a18 | 5694 | napi_schedule(&tnapi->napi); |
d18edcb2 MC |
5695 | } else { |
5696 | /* No work, shared interrupt perhaps? re-enable | |
5697 | * interrupts, and flush that PCI write | |
5698 | */ | |
5699 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, | |
5700 | 0x00000000); | |
fac9b83e | 5701 | } |
f47c11ee | 5702 | out: |
fac9b83e DM |
5703 | return IRQ_RETVAL(handled); |
5704 | } | |
5705 | ||
7d12e780 | 5706 | static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id) |
fac9b83e | 5707 | { |
09943a18 MC |
5708 | struct tg3_napi *tnapi = dev_id; |
5709 | struct tg3 *tp = tnapi->tp; | |
898a56f8 | 5710 | struct tg3_hw_status *sblk = tnapi->hw_status; |
fac9b83e DM |
5711 | unsigned int handled = 1; |
5712 | ||
fac9b83e DM |
5713 | /* In INTx mode, it is possible for the interrupt to arrive at |
5714 | * the CPU before the status block posted prior to the interrupt. | |
5715 | * Reading the PCI State register will confirm whether the | |
5716 | * interrupt is ours and will flush the status block. | |
5717 | */ | |
898a56f8 | 5718 | if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) { |
63c3a66f | 5719 | if (tg3_flag(tp, CHIP_RESETTING) || |
d18edcb2 MC |
5720 | (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { |
5721 | handled = 0; | |
f47c11ee | 5722 | goto out; |
1da177e4 | 5723 | } |
d18edcb2 MC |
5724 | } |
5725 | ||
5726 | /* | |
5727 | * writing any value to intr-mbox-0 clears PCI INTA# and | |
5728 | * chip-internal interrupt pending events. | |
5729 | * writing non-zero to intr-mbox-0 additional tells the | |
5730 | * NIC to stop sending us irqs, engaging "in-intr-handler" | |
5731 | * event coalescing. | |
c04cb347 MC |
5732 | * |
5733 | * Flush the mailbox to de-assert the IRQ immediately to prevent | |
5734 | * spurious interrupts. The flush impacts performance but | |
5735 | * excessive spurious interrupts can be worse in some cases. | |
d18edcb2 | 5736 | */ |
c04cb347 | 5737 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); |
624f8e50 MC |
5738 | |
5739 | /* | |
5740 | * In a shared interrupt configuration, sometimes other devices' | |
5741 | * interrupts will scream. We record the current status tag here | |
5742 | * so that the above check can report that the screaming interrupts | |
5743 | * are unhandled. Eventually they will be silenced. | |
5744 | */ | |
898a56f8 | 5745 | tnapi->last_irq_tag = sblk->status_tag; |
624f8e50 | 5746 | |
d18edcb2 MC |
5747 | if (tg3_irq_sync(tp)) |
5748 | goto out; | |
624f8e50 | 5749 | |
72334482 | 5750 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); |
624f8e50 | 5751 | |
09943a18 | 5752 | napi_schedule(&tnapi->napi); |
624f8e50 | 5753 | |
f47c11ee | 5754 | out: |
1da177e4 LT |
5755 | return IRQ_RETVAL(handled); |
5756 | } | |
5757 | ||
7938109f | 5758 | /* ISR for interrupt test */ |
7d12e780 | 5759 | static irqreturn_t tg3_test_isr(int irq, void *dev_id) |
7938109f | 5760 | { |
09943a18 MC |
5761 | struct tg3_napi *tnapi = dev_id; |
5762 | struct tg3 *tp = tnapi->tp; | |
898a56f8 | 5763 | struct tg3_hw_status *sblk = tnapi->hw_status; |
7938109f | 5764 | |
f9804ddb MC |
5765 | if ((sblk->status & SD_STATUS_UPDATED) || |
5766 | !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { | |
b16250e3 | 5767 | tg3_disable_ints(tp); |
7938109f MC |
5768 | return IRQ_RETVAL(1); |
5769 | } | |
5770 | return IRQ_RETVAL(0); | |
5771 | } | |
5772 | ||
8e7a22e3 | 5773 | static int tg3_init_hw(struct tg3 *, int); |
944d980e | 5774 | static int tg3_halt(struct tg3 *, int, int); |
1da177e4 | 5775 | |
b9ec6c1b MC |
5776 | /* Restart hardware after configuration changes, self-test, etc. |
5777 | * Invoked with tp->lock held. | |
5778 | */ | |
5779 | static int tg3_restart_hw(struct tg3 *tp, int reset_phy) | |
78c6146f ED |
5780 | __releases(tp->lock) |
5781 | __acquires(tp->lock) | |
b9ec6c1b MC |
5782 | { |
5783 | int err; | |
5784 | ||
5785 | err = tg3_init_hw(tp, reset_phy); | |
5786 | if (err) { | |
5129c3a3 MC |
5787 | netdev_err(tp->dev, |
5788 | "Failed to re-initialize device, aborting\n"); | |
b9ec6c1b MC |
5789 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
5790 | tg3_full_unlock(tp); | |
5791 | del_timer_sync(&tp->timer); | |
5792 | tp->irq_sync = 0; | |
fed97810 | 5793 | tg3_napi_enable(tp); |
b9ec6c1b MC |
5794 | dev_close(tp->dev); |
5795 | tg3_full_lock(tp, 0); | |
5796 | } | |
5797 | return err; | |
5798 | } | |
5799 | ||
1da177e4 LT |
5800 | #ifdef CONFIG_NET_POLL_CONTROLLER |
5801 | static void tg3_poll_controller(struct net_device *dev) | |
5802 | { | |
4f125f42 | 5803 | int i; |
88b06bc2 MC |
5804 | struct tg3 *tp = netdev_priv(dev); |
5805 | ||
4f125f42 | 5806 | for (i = 0; i < tp->irq_cnt; i++) |
fe234f0e | 5807 | tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]); |
1da177e4 LT |
5808 | } |
5809 | #endif | |
5810 | ||
c4028958 | 5811 | static void tg3_reset_task(struct work_struct *work) |
1da177e4 | 5812 | { |
c4028958 | 5813 | struct tg3 *tp = container_of(work, struct tg3, reset_task); |
b02fd9e3 | 5814 | int err; |
1da177e4 LT |
5815 | unsigned int restart_timer; |
5816 | ||
7faa006f | 5817 | tg3_full_lock(tp, 0); |
7faa006f MC |
5818 | |
5819 | if (!netif_running(tp->dev)) { | |
7faa006f MC |
5820 | tg3_full_unlock(tp); |
5821 | return; | |
5822 | } | |
5823 | ||
5824 | tg3_full_unlock(tp); | |
5825 | ||
b02fd9e3 MC |
5826 | tg3_phy_stop(tp); |
5827 | ||
1da177e4 LT |
5828 | tg3_netif_stop(tp); |
5829 | ||
f47c11ee | 5830 | tg3_full_lock(tp, 1); |
1da177e4 | 5831 | |
63c3a66f JP |
5832 | restart_timer = tg3_flag(tp, RESTART_TIMER); |
5833 | tg3_flag_clear(tp, RESTART_TIMER); | |
1da177e4 | 5834 | |
63c3a66f | 5835 | if (tg3_flag(tp, TX_RECOVERY_PENDING)) { |
df3e6548 MC |
5836 | tp->write32_tx_mbox = tg3_write32_tx_mbox; |
5837 | tp->write32_rx_mbox = tg3_write_flush_reg32; | |
63c3a66f JP |
5838 | tg3_flag_set(tp, MBOX_WRITE_REORDER); |
5839 | tg3_flag_clear(tp, TX_RECOVERY_PENDING); | |
df3e6548 MC |
5840 | } |
5841 | ||
944d980e | 5842 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); |
b02fd9e3 MC |
5843 | err = tg3_init_hw(tp, 1); |
5844 | if (err) | |
b9ec6c1b | 5845 | goto out; |
1da177e4 LT |
5846 | |
5847 | tg3_netif_start(tp); | |
5848 | ||
1da177e4 LT |
5849 | if (restart_timer) |
5850 | mod_timer(&tp->timer, jiffies + 1); | |
7faa006f | 5851 | |
b9ec6c1b | 5852 | out: |
7faa006f | 5853 | tg3_full_unlock(tp); |
b02fd9e3 MC |
5854 | |
5855 | if (!err) | |
5856 | tg3_phy_start(tp); | |
1da177e4 LT |
5857 | } |
5858 | ||
5859 | static void tg3_tx_timeout(struct net_device *dev) | |
5860 | { | |
5861 | struct tg3 *tp = netdev_priv(dev); | |
5862 | ||
b0408751 | 5863 | if (netif_msg_tx_err(tp)) { |
05dbe005 | 5864 | netdev_err(dev, "transmit timed out, resetting\n"); |
97bd8e49 | 5865 | tg3_dump_state(tp); |
b0408751 | 5866 | } |
1da177e4 LT |
5867 | |
5868 | schedule_work(&tp->reset_task); | |
5869 | } | |
5870 | ||
c58ec932 MC |
5871 | /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */ |
5872 | static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len) | |
5873 | { | |
5874 | u32 base = (u32) mapping & 0xffffffff; | |
5875 | ||
807540ba | 5876 | return (base > 0xffffdcc0) && (base + len + 8 < base); |
c58ec932 MC |
5877 | } |
5878 | ||
72f2afb8 MC |
5879 | /* Test for DMA addresses > 40-bit */ |
5880 | static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping, | |
5881 | int len) | |
5882 | { | |
5883 | #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64) | |
63c3a66f | 5884 | if (tg3_flag(tp, 40BIT_DMA_BUG)) |
807540ba | 5885 | return ((u64) mapping + len) > DMA_BIT_MASK(40); |
72f2afb8 MC |
5886 | return 0; |
5887 | #else | |
5888 | return 0; | |
5889 | #endif | |
5890 | } | |
5891 | ||
2ffcc981 MC |
5892 | static void tg3_set_txd(struct tg3_napi *tnapi, int entry, |
5893 | dma_addr_t mapping, int len, u32 flags, | |
5894 | u32 mss_and_is_end) | |
5895 | { | |
5896 | struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry]; | |
5897 | int is_end = (mss_and_is_end & 0x1); | |
5898 | u32 mss = (mss_and_is_end >> 1); | |
5899 | u32 vlan_tag = 0; | |
5900 | ||
5901 | if (is_end) | |
5902 | flags |= TXD_FLAG_END; | |
5903 | if (flags & TXD_FLAG_VLAN) { | |
5904 | vlan_tag = flags >> 16; | |
5905 | flags &= 0xffff; | |
5906 | } | |
5907 | vlan_tag |= (mss << TXD_MSS_SHIFT); | |
5908 | ||
5909 | txd->addr_hi = ((u64) mapping >> 32); | |
5910 | txd->addr_lo = ((u64) mapping & 0xffffffff); | |
5911 | txd->len_flags = (len << TXD_LEN_SHIFT) | flags; | |
5912 | txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT; | |
5913 | } | |
1da177e4 | 5914 | |
432aa7ed MC |
5915 | static void tg3_skb_error_unmap(struct tg3_napi *tnapi, |
5916 | struct sk_buff *skb, int last) | |
5917 | { | |
5918 | int i; | |
5919 | u32 entry = tnapi->tx_prod; | |
5920 | struct ring_info *txb = &tnapi->tx_buffers[entry]; | |
5921 | ||
5922 | pci_unmap_single(tnapi->tp->pdev, | |
5923 | dma_unmap_addr(txb, mapping), | |
5924 | skb_headlen(skb), | |
5925 | PCI_DMA_TODEVICE); | |
9a2e0fb0 | 5926 | for (i = 0; i < last; i++) { |
432aa7ed MC |
5927 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
5928 | ||
5929 | entry = NEXT_TX(entry); | |
5930 | txb = &tnapi->tx_buffers[entry]; | |
5931 | ||
5932 | pci_unmap_page(tnapi->tp->pdev, | |
5933 | dma_unmap_addr(txb, mapping), | |
5934 | frag->size, PCI_DMA_TODEVICE); | |
5935 | } | |
5936 | } | |
5937 | ||
72f2afb8 | 5938 | /* Workaround 4GB and 40-bit hardware DMA bugs. */ |
24f4efd4 | 5939 | static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi, |
432aa7ed MC |
5940 | struct sk_buff *skb, |
5941 | u32 base_flags, u32 mss) | |
1da177e4 | 5942 | { |
24f4efd4 | 5943 | struct tg3 *tp = tnapi->tp; |
41588ba1 | 5944 | struct sk_buff *new_skb; |
c58ec932 | 5945 | dma_addr_t new_addr = 0; |
432aa7ed MC |
5946 | u32 entry = tnapi->tx_prod; |
5947 | int ret = 0; | |
1da177e4 | 5948 | |
41588ba1 MC |
5949 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) |
5950 | new_skb = skb_copy(skb, GFP_ATOMIC); | |
5951 | else { | |
5952 | int more_headroom = 4 - ((unsigned long)skb->data & 3); | |
5953 | ||
5954 | new_skb = skb_copy_expand(skb, | |
5955 | skb_headroom(skb) + more_headroom, | |
5956 | skb_tailroom(skb), GFP_ATOMIC); | |
5957 | } | |
5958 | ||
1da177e4 | 5959 | if (!new_skb) { |
c58ec932 MC |
5960 | ret = -1; |
5961 | } else { | |
5962 | /* New SKB is guaranteed to be linear. */ | |
f4188d8a AD |
5963 | new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len, |
5964 | PCI_DMA_TODEVICE); | |
5965 | /* Make sure the mapping succeeded */ | |
5966 | if (pci_dma_mapping_error(tp->pdev, new_addr)) { | |
5967 | ret = -1; | |
5968 | dev_kfree_skb(new_skb); | |
90079ce8 | 5969 | |
c58ec932 MC |
5970 | /* Make sure new skb does not cross any 4G boundaries. |
5971 | * Drop the packet if it does. | |
5972 | */ | |
eb69d564 | 5973 | } else if (tg3_4g_overflow_test(new_addr, new_skb->len)) { |
f4188d8a AD |
5974 | pci_unmap_single(tp->pdev, new_addr, new_skb->len, |
5975 | PCI_DMA_TODEVICE); | |
c58ec932 MC |
5976 | ret = -1; |
5977 | dev_kfree_skb(new_skb); | |
c58ec932 | 5978 | } else { |
432aa7ed MC |
5979 | tnapi->tx_buffers[entry].skb = new_skb; |
5980 | dma_unmap_addr_set(&tnapi->tx_buffers[entry], | |
5981 | mapping, new_addr); | |
5982 | ||
f3f3f27e | 5983 | tg3_set_txd(tnapi, entry, new_addr, new_skb->len, |
c58ec932 | 5984 | base_flags, 1 | (mss << 1)); |
f4188d8a | 5985 | } |
1da177e4 LT |
5986 | } |
5987 | ||
5988 | dev_kfree_skb(skb); | |
5989 | ||
c58ec932 | 5990 | return ret; |
1da177e4 LT |
5991 | } |
5992 | ||
2ffcc981 | 5993 | static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *); |
52c0fd83 MC |
5994 | |
5995 | /* Use GSO to workaround a rare TSO bug that may be triggered when the | |
5996 | * TSO header is greater than 80 bytes. | |
5997 | */ | |
5998 | static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb) | |
5999 | { | |
6000 | struct sk_buff *segs, *nskb; | |
f3f3f27e | 6001 | u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3; |
52c0fd83 MC |
6002 | |
6003 | /* Estimate the number of fragments in the worst case */ | |
f3f3f27e | 6004 | if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) { |
52c0fd83 | 6005 | netif_stop_queue(tp->dev); |
f65aac16 MC |
6006 | |
6007 | /* netif_tx_stop_queue() must be done before checking | |
6008 | * checking tx index in tg3_tx_avail() below, because in | |
6009 | * tg3_tx(), we update tx index before checking for | |
6010 | * netif_tx_queue_stopped(). | |
6011 | */ | |
6012 | smp_mb(); | |
f3f3f27e | 6013 | if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est) |
7f62ad5d MC |
6014 | return NETDEV_TX_BUSY; |
6015 | ||
6016 | netif_wake_queue(tp->dev); | |
52c0fd83 MC |
6017 | } |
6018 | ||
6019 | segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO); | |
801678c5 | 6020 | if (IS_ERR(segs)) |
52c0fd83 MC |
6021 | goto tg3_tso_bug_end; |
6022 | ||
6023 | do { | |
6024 | nskb = segs; | |
6025 | segs = segs->next; | |
6026 | nskb->next = NULL; | |
2ffcc981 | 6027 | tg3_start_xmit(nskb, tp->dev); |
52c0fd83 MC |
6028 | } while (segs); |
6029 | ||
6030 | tg3_tso_bug_end: | |
6031 | dev_kfree_skb(skb); | |
6032 | ||
6033 | return NETDEV_TX_OK; | |
6034 | } | |
52c0fd83 | 6035 | |
5a6f3074 | 6036 | /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and |
63c3a66f | 6037 | * support TG3_FLAG_HW_TSO_1 or firmware TSO only. |
5a6f3074 | 6038 | */ |
2ffcc981 | 6039 | static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev) |
1da177e4 LT |
6040 | { |
6041 | struct tg3 *tp = netdev_priv(dev); | |
1da177e4 | 6042 | u32 len, entry, base_flags, mss; |
432aa7ed | 6043 | int i = -1, would_hit_hwbug; |
90079ce8 | 6044 | dma_addr_t mapping; |
24f4efd4 MC |
6045 | struct tg3_napi *tnapi; |
6046 | struct netdev_queue *txq; | |
432aa7ed | 6047 | unsigned int last; |
f4188d8a | 6048 | |
24f4efd4 MC |
6049 | txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb)); |
6050 | tnapi = &tp->napi[skb_get_queue_mapping(skb)]; | |
63c3a66f | 6051 | if (tg3_flag(tp, ENABLE_TSS)) |
24f4efd4 | 6052 | tnapi++; |
1da177e4 | 6053 | |
00b70504 | 6054 | /* We are running in BH disabled context with netif_tx_lock |
bea3348e | 6055 | * and TX reclaim runs via tp->napi.poll inside of a software |
f47c11ee DM |
6056 | * interrupt. Furthermore, IRQ processing runs lockless so we have |
6057 | * no IRQ context deadlocks to worry about either. Rejoice! | |
1da177e4 | 6058 | */ |
f3f3f27e | 6059 | if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) { |
24f4efd4 MC |
6060 | if (!netif_tx_queue_stopped(txq)) { |
6061 | netif_tx_stop_queue(txq); | |
1f064a87 SH |
6062 | |
6063 | /* This is a hard error, log it. */ | |
5129c3a3 MC |
6064 | netdev_err(dev, |
6065 | "BUG! Tx Ring full when queue awake!\n"); | |
1f064a87 | 6066 | } |
1da177e4 LT |
6067 | return NETDEV_TX_BUSY; |
6068 | } | |
6069 | ||
f3f3f27e | 6070 | entry = tnapi->tx_prod; |
1da177e4 | 6071 | base_flags = 0; |
84fa7933 | 6072 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
1da177e4 | 6073 | base_flags |= TXD_FLAG_TCPUDP_CSUM; |
24f4efd4 | 6074 | |
be98da6a MC |
6075 | mss = skb_shinfo(skb)->gso_size; |
6076 | if (mss) { | |
eddc9ec5 | 6077 | struct iphdr *iph; |
34195c3d | 6078 | u32 tcp_opt_len, hdr_len; |
1da177e4 LT |
6079 | |
6080 | if (skb_header_cloned(skb) && | |
6081 | pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) { | |
6082 | dev_kfree_skb(skb); | |
6083 | goto out_unlock; | |
6084 | } | |
6085 | ||
34195c3d | 6086 | iph = ip_hdr(skb); |
ab6a5bb6 | 6087 | tcp_opt_len = tcp_optlen(skb); |
1da177e4 | 6088 | |
02e96080 | 6089 | if (skb_is_gso_v6(skb)) { |
34195c3d MC |
6090 | hdr_len = skb_headlen(skb) - ETH_HLEN; |
6091 | } else { | |
6092 | u32 ip_tcp_len; | |
6093 | ||
6094 | ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr); | |
6095 | hdr_len = ip_tcp_len + tcp_opt_len; | |
6096 | ||
6097 | iph->check = 0; | |
6098 | iph->tot_len = htons(mss + hdr_len); | |
6099 | } | |
6100 | ||
52c0fd83 | 6101 | if (unlikely((ETH_HLEN + hdr_len) > 80) && |
63c3a66f | 6102 | tg3_flag(tp, TSO_BUG)) |
de6f31eb | 6103 | return tg3_tso_bug(tp, skb); |
52c0fd83 | 6104 | |
1da177e4 LT |
6105 | base_flags |= (TXD_FLAG_CPU_PRE_DMA | |
6106 | TXD_FLAG_CPU_POST_DMA); | |
6107 | ||
63c3a66f JP |
6108 | if (tg3_flag(tp, HW_TSO_1) || |
6109 | tg3_flag(tp, HW_TSO_2) || | |
6110 | tg3_flag(tp, HW_TSO_3)) { | |
aa8223c7 | 6111 | tcp_hdr(skb)->check = 0; |
1da177e4 | 6112 | base_flags &= ~TXD_FLAG_TCPUDP_CSUM; |
aa8223c7 ACM |
6113 | } else |
6114 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
6115 | iph->daddr, 0, | |
6116 | IPPROTO_TCP, | |
6117 | 0); | |
1da177e4 | 6118 | |
63c3a66f | 6119 | if (tg3_flag(tp, HW_TSO_3)) { |
615774fe MC |
6120 | mss |= (hdr_len & 0xc) << 12; |
6121 | if (hdr_len & 0x10) | |
6122 | base_flags |= 0x00000010; | |
6123 | base_flags |= (hdr_len & 0x3e0) << 5; | |
63c3a66f | 6124 | } else if (tg3_flag(tp, HW_TSO_2)) |
92c6b8d1 | 6125 | mss |= hdr_len << 9; |
63c3a66f | 6126 | else if (tg3_flag(tp, HW_TSO_1) || |
92c6b8d1 | 6127 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { |
eddc9ec5 | 6128 | if (tcp_opt_len || iph->ihl > 5) { |
1da177e4 LT |
6129 | int tsflags; |
6130 | ||
eddc9ec5 | 6131 | tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); |
1da177e4 LT |
6132 | mss |= (tsflags << 11); |
6133 | } | |
6134 | } else { | |
eddc9ec5 | 6135 | if (tcp_opt_len || iph->ihl > 5) { |
1da177e4 LT |
6136 | int tsflags; |
6137 | ||
eddc9ec5 | 6138 | tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); |
1da177e4 LT |
6139 | base_flags |= tsflags << 12; |
6140 | } | |
6141 | } | |
6142 | } | |
bf933c80 | 6143 | |
eab6d18d | 6144 | if (vlan_tx_tag_present(skb)) |
1da177e4 LT |
6145 | base_flags |= (TXD_FLAG_VLAN | |
6146 | (vlan_tx_tag_get(skb) << 16)); | |
1da177e4 | 6147 | |
63c3a66f | 6148 | if (tg3_flag(tp, USE_JUMBO_BDFLAG) && |
8fc2f995 | 6149 | !mss && skb->len > VLAN_ETH_FRAME_LEN) |
615774fe MC |
6150 | base_flags |= TXD_FLAG_JMB_PKT; |
6151 | ||
f4188d8a AD |
6152 | len = skb_headlen(skb); |
6153 | ||
6154 | mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE); | |
6155 | if (pci_dma_mapping_error(tp->pdev, mapping)) { | |
90079ce8 DM |
6156 | dev_kfree_skb(skb); |
6157 | goto out_unlock; | |
6158 | } | |
6159 | ||
f3f3f27e | 6160 | tnapi->tx_buffers[entry].skb = skb; |
4e5e4f0d | 6161 | dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping); |
1da177e4 LT |
6162 | |
6163 | would_hit_hwbug = 0; | |
6164 | ||
63c3a66f | 6165 | if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8) |
92c6b8d1 MC |
6166 | would_hit_hwbug = 1; |
6167 | ||
eb69d564 | 6168 | if (tg3_4g_overflow_test(mapping, len)) |
0e1406dd MC |
6169 | would_hit_hwbug = 1; |
6170 | ||
daf9a553 | 6171 | if (tg3_40bit_overflow_test(tp, mapping, len)) |
41588ba1 | 6172 | would_hit_hwbug = 1; |
0e1406dd | 6173 | |
63c3a66f | 6174 | if (tg3_flag(tp, 5701_DMA_BUG)) |
c58ec932 | 6175 | would_hit_hwbug = 1; |
1da177e4 | 6176 | |
f3f3f27e | 6177 | tg3_set_txd(tnapi, entry, mapping, len, base_flags, |
1da177e4 LT |
6178 | (skb_shinfo(skb)->nr_frags == 0) | (mss << 1)); |
6179 | ||
6180 | entry = NEXT_TX(entry); | |
6181 | ||
6182 | /* Now loop through additional data fragments, and queue them. */ | |
6183 | if (skb_shinfo(skb)->nr_frags > 0) { | |
1da177e4 LT |
6184 | last = skb_shinfo(skb)->nr_frags - 1; |
6185 | for (i = 0; i <= last; i++) { | |
6186 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
6187 | ||
6188 | len = frag->size; | |
f4188d8a AD |
6189 | mapping = pci_map_page(tp->pdev, |
6190 | frag->page, | |
6191 | frag->page_offset, | |
6192 | len, PCI_DMA_TODEVICE); | |
1da177e4 | 6193 | |
f3f3f27e | 6194 | tnapi->tx_buffers[entry].skb = NULL; |
4e5e4f0d | 6195 | dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, |
f4188d8a AD |
6196 | mapping); |
6197 | if (pci_dma_mapping_error(tp->pdev, mapping)) | |
6198 | goto dma_error; | |
1da177e4 | 6199 | |
63c3a66f | 6200 | if (tg3_flag(tp, SHORT_DMA_BUG) && |
92c6b8d1 MC |
6201 | len <= 8) |
6202 | would_hit_hwbug = 1; | |
6203 | ||
eb69d564 | 6204 | if (tg3_4g_overflow_test(mapping, len)) |
c58ec932 | 6205 | would_hit_hwbug = 1; |
1da177e4 | 6206 | |
daf9a553 | 6207 | if (tg3_40bit_overflow_test(tp, mapping, len)) |
72f2afb8 MC |
6208 | would_hit_hwbug = 1; |
6209 | ||
63c3a66f JP |
6210 | if (tg3_flag(tp, HW_TSO_1) || |
6211 | tg3_flag(tp, HW_TSO_2) || | |
6212 | tg3_flag(tp, HW_TSO_3)) | |
f3f3f27e | 6213 | tg3_set_txd(tnapi, entry, mapping, len, |
1da177e4 LT |
6214 | base_flags, (i == last)|(mss << 1)); |
6215 | else | |
f3f3f27e | 6216 | tg3_set_txd(tnapi, entry, mapping, len, |
1da177e4 LT |
6217 | base_flags, (i == last)); |
6218 | ||
6219 | entry = NEXT_TX(entry); | |
6220 | } | |
6221 | } | |
6222 | ||
6223 | if (would_hit_hwbug) { | |
432aa7ed | 6224 | tg3_skb_error_unmap(tnapi, skb, i); |
1da177e4 LT |
6225 | |
6226 | /* If the workaround fails due to memory/mapping | |
6227 | * failure, silently drop this packet. | |
6228 | */ | |
432aa7ed | 6229 | if (tigon3_dma_hwbug_workaround(tnapi, skb, base_flags, mss)) |
1da177e4 LT |
6230 | goto out_unlock; |
6231 | ||
432aa7ed | 6232 | entry = NEXT_TX(tnapi->tx_prod); |
1da177e4 LT |
6233 | } |
6234 | ||
d515b450 RC |
6235 | skb_tx_timestamp(skb); |
6236 | ||
1da177e4 | 6237 | /* Packets are ready, update Tx producer idx local and on card. */ |
24f4efd4 | 6238 | tw32_tx_mbox(tnapi->prodmbox, entry); |
1da177e4 | 6239 | |
f3f3f27e MC |
6240 | tnapi->tx_prod = entry; |
6241 | if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) { | |
24f4efd4 | 6242 | netif_tx_stop_queue(txq); |
f65aac16 MC |
6243 | |
6244 | /* netif_tx_stop_queue() must be done before checking | |
6245 | * checking tx index in tg3_tx_avail() below, because in | |
6246 | * tg3_tx(), we update tx index before checking for | |
6247 | * netif_tx_queue_stopped(). | |
6248 | */ | |
6249 | smp_mb(); | |
f3f3f27e | 6250 | if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)) |
24f4efd4 | 6251 | netif_tx_wake_queue(txq); |
51b91468 | 6252 | } |
1da177e4 LT |
6253 | |
6254 | out_unlock: | |
cdd0db05 | 6255 | mmiowb(); |
1da177e4 LT |
6256 | |
6257 | return NETDEV_TX_OK; | |
f4188d8a AD |
6258 | |
6259 | dma_error: | |
432aa7ed | 6260 | tg3_skb_error_unmap(tnapi, skb, i); |
f4188d8a | 6261 | dev_kfree_skb(skb); |
432aa7ed | 6262 | tnapi->tx_buffers[tnapi->tx_prod].skb = NULL; |
f4188d8a | 6263 | return NETDEV_TX_OK; |
1da177e4 LT |
6264 | } |
6265 | ||
06c03c02 MB |
6266 | static void tg3_set_loopback(struct net_device *dev, u32 features) |
6267 | { | |
6268 | struct tg3 *tp = netdev_priv(dev); | |
6269 | ||
6270 | if (features & NETIF_F_LOOPBACK) { | |
6271 | if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK) | |
6272 | return; | |
6273 | ||
6274 | /* | |
6275 | * Clear MAC_MODE_HALF_DUPLEX or you won't get packets back in | |
6276 | * loopback mode if Half-Duplex mode was negotiated earlier. | |
6277 | */ | |
6278 | tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; | |
6279 | ||
6280 | /* Enable internal MAC loopback mode */ | |
6281 | tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK; | |
6282 | spin_lock_bh(&tp->lock); | |
6283 | tw32(MAC_MODE, tp->mac_mode); | |
6284 | netif_carrier_on(tp->dev); | |
6285 | spin_unlock_bh(&tp->lock); | |
6286 | netdev_info(dev, "Internal MAC loopback mode enabled.\n"); | |
6287 | } else { | |
6288 | if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) | |
6289 | return; | |
6290 | ||
6291 | /* Disable internal MAC loopback mode */ | |
6292 | tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK; | |
6293 | spin_lock_bh(&tp->lock); | |
6294 | tw32(MAC_MODE, tp->mac_mode); | |
6295 | /* Force link status check */ | |
6296 | tg3_setup_phy(tp, 1); | |
6297 | spin_unlock_bh(&tp->lock); | |
6298 | netdev_info(dev, "Internal MAC loopback mode disabled.\n"); | |
6299 | } | |
6300 | } | |
6301 | ||
dc668910 MM |
6302 | static u32 tg3_fix_features(struct net_device *dev, u32 features) |
6303 | { | |
6304 | struct tg3 *tp = netdev_priv(dev); | |
6305 | ||
63c3a66f | 6306 | if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS)) |
dc668910 MM |
6307 | features &= ~NETIF_F_ALL_TSO; |
6308 | ||
6309 | return features; | |
6310 | } | |
6311 | ||
06c03c02 MB |
6312 | static int tg3_set_features(struct net_device *dev, u32 features) |
6313 | { | |
6314 | u32 changed = dev->features ^ features; | |
6315 | ||
6316 | if ((changed & NETIF_F_LOOPBACK) && netif_running(dev)) | |
6317 | tg3_set_loopback(dev, features); | |
6318 | ||
6319 | return 0; | |
6320 | } | |
6321 | ||
1da177e4 LT |
6322 | static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp, |
6323 | int new_mtu) | |
6324 | { | |
6325 | dev->mtu = new_mtu; | |
6326 | ||
ef7f5ec0 | 6327 | if (new_mtu > ETH_DATA_LEN) { |
63c3a66f | 6328 | if (tg3_flag(tp, 5780_CLASS)) { |
dc668910 | 6329 | netdev_update_features(dev); |
63c3a66f | 6330 | tg3_flag_clear(tp, TSO_CAPABLE); |
859a5887 | 6331 | } else { |
63c3a66f | 6332 | tg3_flag_set(tp, JUMBO_RING_ENABLE); |
859a5887 | 6333 | } |
ef7f5ec0 | 6334 | } else { |
63c3a66f JP |
6335 | if (tg3_flag(tp, 5780_CLASS)) { |
6336 | tg3_flag_set(tp, TSO_CAPABLE); | |
dc668910 MM |
6337 | netdev_update_features(dev); |
6338 | } | |
63c3a66f | 6339 | tg3_flag_clear(tp, JUMBO_RING_ENABLE); |
ef7f5ec0 | 6340 | } |
1da177e4 LT |
6341 | } |
6342 | ||
6343 | static int tg3_change_mtu(struct net_device *dev, int new_mtu) | |
6344 | { | |
6345 | struct tg3 *tp = netdev_priv(dev); | |
b9ec6c1b | 6346 | int err; |
1da177e4 LT |
6347 | |
6348 | if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp)) | |
6349 | return -EINVAL; | |
6350 | ||
6351 | if (!netif_running(dev)) { | |
6352 | /* We'll just catch it later when the | |
6353 | * device is up'd. | |
6354 | */ | |
6355 | tg3_set_mtu(dev, tp, new_mtu); | |
6356 | return 0; | |
6357 | } | |
6358 | ||
b02fd9e3 MC |
6359 | tg3_phy_stop(tp); |
6360 | ||
1da177e4 | 6361 | tg3_netif_stop(tp); |
f47c11ee DM |
6362 | |
6363 | tg3_full_lock(tp, 1); | |
1da177e4 | 6364 | |
944d980e | 6365 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 LT |
6366 | |
6367 | tg3_set_mtu(dev, tp, new_mtu); | |
6368 | ||
b9ec6c1b | 6369 | err = tg3_restart_hw(tp, 0); |
1da177e4 | 6370 | |
b9ec6c1b MC |
6371 | if (!err) |
6372 | tg3_netif_start(tp); | |
1da177e4 | 6373 | |
f47c11ee | 6374 | tg3_full_unlock(tp); |
1da177e4 | 6375 | |
b02fd9e3 MC |
6376 | if (!err) |
6377 | tg3_phy_start(tp); | |
6378 | ||
b9ec6c1b | 6379 | return err; |
1da177e4 LT |
6380 | } |
6381 | ||
21f581a5 MC |
6382 | static void tg3_rx_prodring_free(struct tg3 *tp, |
6383 | struct tg3_rx_prodring_set *tpr) | |
1da177e4 | 6384 | { |
1da177e4 LT |
6385 | int i; |
6386 | ||
8fea32b9 | 6387 | if (tpr != &tp->napi[0].prodring) { |
b196c7e4 | 6388 | for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx; |
2c49a44d | 6389 | i = (i + 1) & tp->rx_std_ring_mask) |
b196c7e4 MC |
6390 | tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i], |
6391 | tp->rx_pkt_map_sz); | |
6392 | ||
63c3a66f | 6393 | if (tg3_flag(tp, JUMBO_CAPABLE)) { |
b196c7e4 MC |
6394 | for (i = tpr->rx_jmb_cons_idx; |
6395 | i != tpr->rx_jmb_prod_idx; | |
2c49a44d | 6396 | i = (i + 1) & tp->rx_jmb_ring_mask) { |
b196c7e4 MC |
6397 | tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i], |
6398 | TG3_RX_JMB_MAP_SZ); | |
6399 | } | |
6400 | } | |
6401 | ||
2b2cdb65 | 6402 | return; |
b196c7e4 | 6403 | } |
1da177e4 | 6404 | |
2c49a44d | 6405 | for (i = 0; i <= tp->rx_std_ring_mask; i++) |
2b2cdb65 MC |
6406 | tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i], |
6407 | tp->rx_pkt_map_sz); | |
1da177e4 | 6408 | |
63c3a66f | 6409 | if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) { |
2c49a44d | 6410 | for (i = 0; i <= tp->rx_jmb_ring_mask; i++) |
2b2cdb65 MC |
6411 | tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i], |
6412 | TG3_RX_JMB_MAP_SZ); | |
1da177e4 LT |
6413 | } |
6414 | } | |
6415 | ||
c6cdf436 | 6416 | /* Initialize rx rings for packet processing. |
1da177e4 LT |
6417 | * |
6418 | * The chip has been shut down and the driver detached from | |
6419 | * the networking, so no interrupts or new tx packets will | |
6420 | * end up in the driver. tp->{tx,}lock are held and thus | |
6421 | * we may not sleep. | |
6422 | */ | |
21f581a5 MC |
6423 | static int tg3_rx_prodring_alloc(struct tg3 *tp, |
6424 | struct tg3_rx_prodring_set *tpr) | |
1da177e4 | 6425 | { |
287be12e | 6426 | u32 i, rx_pkt_dma_sz; |
1da177e4 | 6427 | |
b196c7e4 MC |
6428 | tpr->rx_std_cons_idx = 0; |
6429 | tpr->rx_std_prod_idx = 0; | |
6430 | tpr->rx_jmb_cons_idx = 0; | |
6431 | tpr->rx_jmb_prod_idx = 0; | |
6432 | ||
8fea32b9 | 6433 | if (tpr != &tp->napi[0].prodring) { |
2c49a44d MC |
6434 | memset(&tpr->rx_std_buffers[0], 0, |
6435 | TG3_RX_STD_BUFF_RING_SIZE(tp)); | |
48035728 | 6436 | if (tpr->rx_jmb_buffers) |
2b2cdb65 | 6437 | memset(&tpr->rx_jmb_buffers[0], 0, |
2c49a44d | 6438 | TG3_RX_JMB_BUFF_RING_SIZE(tp)); |
2b2cdb65 MC |
6439 | goto done; |
6440 | } | |
6441 | ||
1da177e4 | 6442 | /* Zero out all descriptors. */ |
2c49a44d | 6443 | memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp)); |
1da177e4 | 6444 | |
287be12e | 6445 | rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ; |
63c3a66f | 6446 | if (tg3_flag(tp, 5780_CLASS) && |
287be12e MC |
6447 | tp->dev->mtu > ETH_DATA_LEN) |
6448 | rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ; | |
6449 | tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz); | |
7e72aad4 | 6450 | |
1da177e4 LT |
6451 | /* Initialize invariants of the rings, we only set this |
6452 | * stuff once. This works because the card does not | |
6453 | * write into the rx buffer posting rings. | |
6454 | */ | |
2c49a44d | 6455 | for (i = 0; i <= tp->rx_std_ring_mask; i++) { |
1da177e4 LT |
6456 | struct tg3_rx_buffer_desc *rxd; |
6457 | ||
21f581a5 | 6458 | rxd = &tpr->rx_std[i]; |
287be12e | 6459 | rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT; |
1da177e4 LT |
6460 | rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT); |
6461 | rxd->opaque = (RXD_OPAQUE_RING_STD | | |
6462 | (i << RXD_OPAQUE_INDEX_SHIFT)); | |
6463 | } | |
6464 | ||
1da177e4 LT |
6465 | /* Now allocate fresh SKBs for each rx ring. */ |
6466 | for (i = 0; i < tp->rx_pending; i++) { | |
86b21e59 | 6467 | if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) { |
5129c3a3 MC |
6468 | netdev_warn(tp->dev, |
6469 | "Using a smaller RX standard ring. Only " | |
6470 | "%d out of %d buffers were allocated " | |
6471 | "successfully\n", i, tp->rx_pending); | |
32d8c572 | 6472 | if (i == 0) |
cf7a7298 | 6473 | goto initfail; |
32d8c572 | 6474 | tp->rx_pending = i; |
1da177e4 | 6475 | break; |
32d8c572 | 6476 | } |
1da177e4 LT |
6477 | } |
6478 | ||
63c3a66f | 6479 | if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS)) |
cf7a7298 MC |
6480 | goto done; |
6481 | ||
2c49a44d | 6482 | memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp)); |
cf7a7298 | 6483 | |
63c3a66f | 6484 | if (!tg3_flag(tp, JUMBO_RING_ENABLE)) |
0d86df80 | 6485 | goto done; |
cf7a7298 | 6486 | |
2c49a44d | 6487 | for (i = 0; i <= tp->rx_jmb_ring_mask; i++) { |
0d86df80 MC |
6488 | struct tg3_rx_buffer_desc *rxd; |
6489 | ||
6490 | rxd = &tpr->rx_jmb[i].std; | |
6491 | rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT; | |
6492 | rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) | | |
6493 | RXD_FLAG_JUMBO; | |
6494 | rxd->opaque = (RXD_OPAQUE_RING_JUMBO | | |
6495 | (i << RXD_OPAQUE_INDEX_SHIFT)); | |
6496 | } | |
6497 | ||
6498 | for (i = 0; i < tp->rx_jumbo_pending; i++) { | |
6499 | if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) { | |
5129c3a3 MC |
6500 | netdev_warn(tp->dev, |
6501 | "Using a smaller RX jumbo ring. Only %d " | |
6502 | "out of %d buffers were allocated " | |
6503 | "successfully\n", i, tp->rx_jumbo_pending); | |
0d86df80 MC |
6504 | if (i == 0) |
6505 | goto initfail; | |
6506 | tp->rx_jumbo_pending = i; | |
6507 | break; | |
1da177e4 LT |
6508 | } |
6509 | } | |
cf7a7298 MC |
6510 | |
6511 | done: | |
32d8c572 | 6512 | return 0; |
cf7a7298 MC |
6513 | |
6514 | initfail: | |
21f581a5 | 6515 | tg3_rx_prodring_free(tp, tpr); |
cf7a7298 | 6516 | return -ENOMEM; |
1da177e4 LT |
6517 | } |
6518 | ||
21f581a5 MC |
6519 | static void tg3_rx_prodring_fini(struct tg3 *tp, |
6520 | struct tg3_rx_prodring_set *tpr) | |
1da177e4 | 6521 | { |
21f581a5 MC |
6522 | kfree(tpr->rx_std_buffers); |
6523 | tpr->rx_std_buffers = NULL; | |
6524 | kfree(tpr->rx_jmb_buffers); | |
6525 | tpr->rx_jmb_buffers = NULL; | |
6526 | if (tpr->rx_std) { | |
4bae65c8 MC |
6527 | dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp), |
6528 | tpr->rx_std, tpr->rx_std_mapping); | |
21f581a5 | 6529 | tpr->rx_std = NULL; |
1da177e4 | 6530 | } |
21f581a5 | 6531 | if (tpr->rx_jmb) { |
4bae65c8 MC |
6532 | dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp), |
6533 | tpr->rx_jmb, tpr->rx_jmb_mapping); | |
21f581a5 | 6534 | tpr->rx_jmb = NULL; |
1da177e4 | 6535 | } |
cf7a7298 MC |
6536 | } |
6537 | ||
21f581a5 MC |
6538 | static int tg3_rx_prodring_init(struct tg3 *tp, |
6539 | struct tg3_rx_prodring_set *tpr) | |
cf7a7298 | 6540 | { |
2c49a44d MC |
6541 | tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp), |
6542 | GFP_KERNEL); | |
21f581a5 | 6543 | if (!tpr->rx_std_buffers) |
cf7a7298 MC |
6544 | return -ENOMEM; |
6545 | ||
4bae65c8 MC |
6546 | tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev, |
6547 | TG3_RX_STD_RING_BYTES(tp), | |
6548 | &tpr->rx_std_mapping, | |
6549 | GFP_KERNEL); | |
21f581a5 | 6550 | if (!tpr->rx_std) |
cf7a7298 MC |
6551 | goto err_out; |
6552 | ||
63c3a66f | 6553 | if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) { |
2c49a44d | 6554 | tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp), |
21f581a5 MC |
6555 | GFP_KERNEL); |
6556 | if (!tpr->rx_jmb_buffers) | |
cf7a7298 MC |
6557 | goto err_out; |
6558 | ||
4bae65c8 MC |
6559 | tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev, |
6560 | TG3_RX_JMB_RING_BYTES(tp), | |
6561 | &tpr->rx_jmb_mapping, | |
6562 | GFP_KERNEL); | |
21f581a5 | 6563 | if (!tpr->rx_jmb) |
cf7a7298 MC |
6564 | goto err_out; |
6565 | } | |
6566 | ||
6567 | return 0; | |
6568 | ||
6569 | err_out: | |
21f581a5 | 6570 | tg3_rx_prodring_fini(tp, tpr); |
cf7a7298 MC |
6571 | return -ENOMEM; |
6572 | } | |
6573 | ||
6574 | /* Free up pending packets in all rx/tx rings. | |
6575 | * | |
6576 | * The chip has been shut down and the driver detached from | |
6577 | * the networking, so no interrupts or new tx packets will | |
6578 | * end up in the driver. tp->{tx,}lock is not held and we are not | |
6579 | * in an interrupt context and thus may sleep. | |
6580 | */ | |
6581 | static void tg3_free_rings(struct tg3 *tp) | |
6582 | { | |
f77a6a8e | 6583 | int i, j; |
cf7a7298 | 6584 | |
f77a6a8e MC |
6585 | for (j = 0; j < tp->irq_cnt; j++) { |
6586 | struct tg3_napi *tnapi = &tp->napi[j]; | |
cf7a7298 | 6587 | |
8fea32b9 | 6588 | tg3_rx_prodring_free(tp, &tnapi->prodring); |
b28f6428 | 6589 | |
0c1d0e2b MC |
6590 | if (!tnapi->tx_buffers) |
6591 | continue; | |
6592 | ||
f77a6a8e | 6593 | for (i = 0; i < TG3_TX_RING_SIZE; ) { |
f4188d8a | 6594 | struct ring_info *txp; |
f77a6a8e | 6595 | struct sk_buff *skb; |
f4188d8a | 6596 | unsigned int k; |
cf7a7298 | 6597 | |
f77a6a8e MC |
6598 | txp = &tnapi->tx_buffers[i]; |
6599 | skb = txp->skb; | |
cf7a7298 | 6600 | |
f77a6a8e MC |
6601 | if (skb == NULL) { |
6602 | i++; | |
6603 | continue; | |
6604 | } | |
cf7a7298 | 6605 | |
f4188d8a | 6606 | pci_unmap_single(tp->pdev, |
4e5e4f0d | 6607 | dma_unmap_addr(txp, mapping), |
f4188d8a AD |
6608 | skb_headlen(skb), |
6609 | PCI_DMA_TODEVICE); | |
f77a6a8e | 6610 | txp->skb = NULL; |
cf7a7298 | 6611 | |
f4188d8a AD |
6612 | i++; |
6613 | ||
6614 | for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) { | |
6615 | txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)]; | |
6616 | pci_unmap_page(tp->pdev, | |
4e5e4f0d | 6617 | dma_unmap_addr(txp, mapping), |
f4188d8a AD |
6618 | skb_shinfo(skb)->frags[k].size, |
6619 | PCI_DMA_TODEVICE); | |
6620 | i++; | |
6621 | } | |
f77a6a8e MC |
6622 | |
6623 | dev_kfree_skb_any(skb); | |
6624 | } | |
2b2cdb65 | 6625 | } |
cf7a7298 MC |
6626 | } |
6627 | ||
6628 | /* Initialize tx/rx rings for packet processing. | |
6629 | * | |
6630 | * The chip has been shut down and the driver detached from | |
6631 | * the networking, so no interrupts or new tx packets will | |
6632 | * end up in the driver. tp->{tx,}lock are held and thus | |
6633 | * we may not sleep. | |
6634 | */ | |
6635 | static int tg3_init_rings(struct tg3 *tp) | |
6636 | { | |
f77a6a8e | 6637 | int i; |
72334482 | 6638 | |
cf7a7298 MC |
6639 | /* Free up all the SKBs. */ |
6640 | tg3_free_rings(tp); | |
6641 | ||
f77a6a8e MC |
6642 | for (i = 0; i < tp->irq_cnt; i++) { |
6643 | struct tg3_napi *tnapi = &tp->napi[i]; | |
6644 | ||
6645 | tnapi->last_tag = 0; | |
6646 | tnapi->last_irq_tag = 0; | |
6647 | tnapi->hw_status->status = 0; | |
6648 | tnapi->hw_status->status_tag = 0; | |
6649 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
cf7a7298 | 6650 | |
f77a6a8e MC |
6651 | tnapi->tx_prod = 0; |
6652 | tnapi->tx_cons = 0; | |
0c1d0e2b MC |
6653 | if (tnapi->tx_ring) |
6654 | memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES); | |
f77a6a8e MC |
6655 | |
6656 | tnapi->rx_rcb_ptr = 0; | |
0c1d0e2b MC |
6657 | if (tnapi->rx_rcb) |
6658 | memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); | |
2b2cdb65 | 6659 | |
8fea32b9 | 6660 | if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) { |
e4af1af9 | 6661 | tg3_free_rings(tp); |
2b2cdb65 | 6662 | return -ENOMEM; |
e4af1af9 | 6663 | } |
f77a6a8e | 6664 | } |
72334482 | 6665 | |
2b2cdb65 | 6666 | return 0; |
cf7a7298 MC |
6667 | } |
6668 | ||
6669 | /* | |
6670 | * Must not be invoked with interrupt sources disabled and | |
6671 | * the hardware shutdown down. | |
6672 | */ | |
6673 | static void tg3_free_consistent(struct tg3 *tp) | |
6674 | { | |
f77a6a8e | 6675 | int i; |
898a56f8 | 6676 | |
f77a6a8e MC |
6677 | for (i = 0; i < tp->irq_cnt; i++) { |
6678 | struct tg3_napi *tnapi = &tp->napi[i]; | |
6679 | ||
6680 | if (tnapi->tx_ring) { | |
4bae65c8 | 6681 | dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES, |
f77a6a8e MC |
6682 | tnapi->tx_ring, tnapi->tx_desc_mapping); |
6683 | tnapi->tx_ring = NULL; | |
6684 | } | |
6685 | ||
6686 | kfree(tnapi->tx_buffers); | |
6687 | tnapi->tx_buffers = NULL; | |
6688 | ||
6689 | if (tnapi->rx_rcb) { | |
4bae65c8 MC |
6690 | dma_free_coherent(&tp->pdev->dev, |
6691 | TG3_RX_RCB_RING_BYTES(tp), | |
6692 | tnapi->rx_rcb, | |
6693 | tnapi->rx_rcb_mapping); | |
f77a6a8e MC |
6694 | tnapi->rx_rcb = NULL; |
6695 | } | |
6696 | ||
8fea32b9 MC |
6697 | tg3_rx_prodring_fini(tp, &tnapi->prodring); |
6698 | ||
f77a6a8e | 6699 | if (tnapi->hw_status) { |
4bae65c8 MC |
6700 | dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE, |
6701 | tnapi->hw_status, | |
6702 | tnapi->status_mapping); | |
f77a6a8e MC |
6703 | tnapi->hw_status = NULL; |
6704 | } | |
1da177e4 | 6705 | } |
f77a6a8e | 6706 | |
1da177e4 | 6707 | if (tp->hw_stats) { |
4bae65c8 MC |
6708 | dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats), |
6709 | tp->hw_stats, tp->stats_mapping); | |
1da177e4 LT |
6710 | tp->hw_stats = NULL; |
6711 | } | |
6712 | } | |
6713 | ||
6714 | /* | |
6715 | * Must not be invoked with interrupt sources disabled and | |
6716 | * the hardware shutdown down. Can sleep. | |
6717 | */ | |
6718 | static int tg3_alloc_consistent(struct tg3 *tp) | |
6719 | { | |
f77a6a8e | 6720 | int i; |
898a56f8 | 6721 | |
4bae65c8 MC |
6722 | tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev, |
6723 | sizeof(struct tg3_hw_stats), | |
6724 | &tp->stats_mapping, | |
6725 | GFP_KERNEL); | |
f77a6a8e | 6726 | if (!tp->hw_stats) |
1da177e4 LT |
6727 | goto err_out; |
6728 | ||
f77a6a8e | 6729 | memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); |
1da177e4 | 6730 | |
f77a6a8e MC |
6731 | for (i = 0; i < tp->irq_cnt; i++) { |
6732 | struct tg3_napi *tnapi = &tp->napi[i]; | |
8d9d7cfc | 6733 | struct tg3_hw_status *sblk; |
1da177e4 | 6734 | |
4bae65c8 MC |
6735 | tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev, |
6736 | TG3_HW_STATUS_SIZE, | |
6737 | &tnapi->status_mapping, | |
6738 | GFP_KERNEL); | |
f77a6a8e MC |
6739 | if (!tnapi->hw_status) |
6740 | goto err_out; | |
898a56f8 | 6741 | |
f77a6a8e | 6742 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); |
8d9d7cfc MC |
6743 | sblk = tnapi->hw_status; |
6744 | ||
8fea32b9 MC |
6745 | if (tg3_rx_prodring_init(tp, &tnapi->prodring)) |
6746 | goto err_out; | |
6747 | ||
19cfaecc MC |
6748 | /* If multivector TSS is enabled, vector 0 does not handle |
6749 | * tx interrupts. Don't allocate any resources for it. | |
6750 | */ | |
63c3a66f JP |
6751 | if ((!i && !tg3_flag(tp, ENABLE_TSS)) || |
6752 | (i && tg3_flag(tp, ENABLE_TSS))) { | |
19cfaecc MC |
6753 | tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) * |
6754 | TG3_TX_RING_SIZE, | |
6755 | GFP_KERNEL); | |
6756 | if (!tnapi->tx_buffers) | |
6757 | goto err_out; | |
6758 | ||
4bae65c8 MC |
6759 | tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev, |
6760 | TG3_TX_RING_BYTES, | |
6761 | &tnapi->tx_desc_mapping, | |
6762 | GFP_KERNEL); | |
19cfaecc MC |
6763 | if (!tnapi->tx_ring) |
6764 | goto err_out; | |
6765 | } | |
6766 | ||
8d9d7cfc MC |
6767 | /* |
6768 | * When RSS is enabled, the status block format changes | |
6769 | * slightly. The "rx_jumbo_consumer", "reserved", | |
6770 | * and "rx_mini_consumer" members get mapped to the | |
6771 | * other three rx return ring producer indexes. | |
6772 | */ | |
6773 | switch (i) { | |
6774 | default: | |
6775 | tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer; | |
6776 | break; | |
6777 | case 2: | |
6778 | tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer; | |
6779 | break; | |
6780 | case 3: | |
6781 | tnapi->rx_rcb_prod_idx = &sblk->reserved; | |
6782 | break; | |
6783 | case 4: | |
6784 | tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer; | |
6785 | break; | |
6786 | } | |
72334482 | 6787 | |
0c1d0e2b MC |
6788 | /* |
6789 | * If multivector RSS is enabled, vector 0 does not handle | |
6790 | * rx or tx interrupts. Don't allocate any resources for it. | |
6791 | */ | |
63c3a66f | 6792 | if (!i && tg3_flag(tp, ENABLE_RSS)) |
0c1d0e2b MC |
6793 | continue; |
6794 | ||
4bae65c8 MC |
6795 | tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev, |
6796 | TG3_RX_RCB_RING_BYTES(tp), | |
6797 | &tnapi->rx_rcb_mapping, | |
6798 | GFP_KERNEL); | |
f77a6a8e MC |
6799 | if (!tnapi->rx_rcb) |
6800 | goto err_out; | |
72334482 | 6801 | |
f77a6a8e | 6802 | memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); |
f77a6a8e | 6803 | } |
1da177e4 LT |
6804 | |
6805 | return 0; | |
6806 | ||
6807 | err_out: | |
6808 | tg3_free_consistent(tp); | |
6809 | return -ENOMEM; | |
6810 | } | |
6811 | ||
6812 | #define MAX_WAIT_CNT 1000 | |
6813 | ||
6814 | /* To stop a block, clear the enable bit and poll till it | |
6815 | * clears. tp->lock is held. | |
6816 | */ | |
b3b7d6be | 6817 | static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent) |
1da177e4 LT |
6818 | { |
6819 | unsigned int i; | |
6820 | u32 val; | |
6821 | ||
63c3a66f | 6822 | if (tg3_flag(tp, 5705_PLUS)) { |
1da177e4 LT |
6823 | switch (ofs) { |
6824 | case RCVLSC_MODE: | |
6825 | case DMAC_MODE: | |
6826 | case MBFREE_MODE: | |
6827 | case BUFMGR_MODE: | |
6828 | case MEMARB_MODE: | |
6829 | /* We can't enable/disable these bits of the | |
6830 | * 5705/5750, just say success. | |
6831 | */ | |
6832 | return 0; | |
6833 | ||
6834 | default: | |
6835 | break; | |
855e1111 | 6836 | } |
1da177e4 LT |
6837 | } |
6838 | ||
6839 | val = tr32(ofs); | |
6840 | val &= ~enable_bit; | |
6841 | tw32_f(ofs, val); | |
6842 | ||
6843 | for (i = 0; i < MAX_WAIT_CNT; i++) { | |
6844 | udelay(100); | |
6845 | val = tr32(ofs); | |
6846 | if ((val & enable_bit) == 0) | |
6847 | break; | |
6848 | } | |
6849 | ||
b3b7d6be | 6850 | if (i == MAX_WAIT_CNT && !silent) { |
2445e461 MC |
6851 | dev_err(&tp->pdev->dev, |
6852 | "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n", | |
6853 | ofs, enable_bit); | |
1da177e4 LT |
6854 | return -ENODEV; |
6855 | } | |
6856 | ||
6857 | return 0; | |
6858 | } | |
6859 | ||
6860 | /* tp->lock is held. */ | |
b3b7d6be | 6861 | static int tg3_abort_hw(struct tg3 *tp, int silent) |
1da177e4 LT |
6862 | { |
6863 | int i, err; | |
6864 | ||
6865 | tg3_disable_ints(tp); | |
6866 | ||
6867 | tp->rx_mode &= ~RX_MODE_ENABLE; | |
6868 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
6869 | udelay(10); | |
6870 | ||
b3b7d6be DM |
6871 | err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent); |
6872 | err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent); | |
6873 | err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent); | |
6874 | err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent); | |
6875 | err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent); | |
6876 | err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent); | |
6877 | ||
6878 | err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent); | |
6879 | err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent); | |
6880 | err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent); | |
6881 | err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent); | |
6882 | err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent); | |
6883 | err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent); | |
6884 | err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent); | |
1da177e4 LT |
6885 | |
6886 | tp->mac_mode &= ~MAC_MODE_TDE_ENABLE; | |
6887 | tw32_f(MAC_MODE, tp->mac_mode); | |
6888 | udelay(40); | |
6889 | ||
6890 | tp->tx_mode &= ~TX_MODE_ENABLE; | |
6891 | tw32_f(MAC_TX_MODE, tp->tx_mode); | |
6892 | ||
6893 | for (i = 0; i < MAX_WAIT_CNT; i++) { | |
6894 | udelay(100); | |
6895 | if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE)) | |
6896 | break; | |
6897 | } | |
6898 | if (i >= MAX_WAIT_CNT) { | |
ab96b241 MC |
6899 | dev_err(&tp->pdev->dev, |
6900 | "%s timed out, TX_MODE_ENABLE will not clear " | |
6901 | "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE)); | |
e6de8ad1 | 6902 | err |= -ENODEV; |
1da177e4 LT |
6903 | } |
6904 | ||
e6de8ad1 | 6905 | err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent); |
b3b7d6be DM |
6906 | err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent); |
6907 | err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent); | |
1da177e4 LT |
6908 | |
6909 | tw32(FTQ_RESET, 0xffffffff); | |
6910 | tw32(FTQ_RESET, 0x00000000); | |
6911 | ||
b3b7d6be DM |
6912 | err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent); |
6913 | err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent); | |
1da177e4 | 6914 | |
f77a6a8e MC |
6915 | for (i = 0; i < tp->irq_cnt; i++) { |
6916 | struct tg3_napi *tnapi = &tp->napi[i]; | |
6917 | if (tnapi->hw_status) | |
6918 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
6919 | } | |
1da177e4 LT |
6920 | if (tp->hw_stats) |
6921 | memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); | |
6922 | ||
1da177e4 LT |
6923 | return err; |
6924 | } | |
6925 | ||
0d3031d9 MC |
6926 | static void tg3_ape_send_event(struct tg3 *tp, u32 event) |
6927 | { | |
6928 | int i; | |
6929 | u32 apedata; | |
6930 | ||
dc6d0744 | 6931 | /* NCSI does not support APE events */ |
63c3a66f | 6932 | if (tg3_flag(tp, APE_HAS_NCSI)) |
dc6d0744 MC |
6933 | return; |
6934 | ||
0d3031d9 MC |
6935 | apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); |
6936 | if (apedata != APE_SEG_SIG_MAGIC) | |
6937 | return; | |
6938 | ||
6939 | apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); | |
731fd79c | 6940 | if (!(apedata & APE_FW_STATUS_READY)) |
0d3031d9 MC |
6941 | return; |
6942 | ||
6943 | /* Wait for up to 1 millisecond for APE to service previous event. */ | |
6944 | for (i = 0; i < 10; i++) { | |
6945 | if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM)) | |
6946 | return; | |
6947 | ||
6948 | apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS); | |
6949 | ||
6950 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) | |
6951 | tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, | |
6952 | event | APE_EVENT_STATUS_EVENT_PENDING); | |
6953 | ||
6954 | tg3_ape_unlock(tp, TG3_APE_LOCK_MEM); | |
6955 | ||
6956 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) | |
6957 | break; | |
6958 | ||
6959 | udelay(100); | |
6960 | } | |
6961 | ||
6962 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) | |
6963 | tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1); | |
6964 | } | |
6965 | ||
6966 | static void tg3_ape_driver_state_change(struct tg3 *tp, int kind) | |
6967 | { | |
6968 | u32 event; | |
6969 | u32 apedata; | |
6970 | ||
63c3a66f | 6971 | if (!tg3_flag(tp, ENABLE_APE)) |
0d3031d9 MC |
6972 | return; |
6973 | ||
6974 | switch (kind) { | |
33f401ae MC |
6975 | case RESET_KIND_INIT: |
6976 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, | |
6977 | APE_HOST_SEG_SIG_MAGIC); | |
6978 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN, | |
6979 | APE_HOST_SEG_LEN_MAGIC); | |
6980 | apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT); | |
6981 | tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata); | |
6982 | tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID, | |
6867c843 | 6983 | APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM)); |
33f401ae MC |
6984 | tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR, |
6985 | APE_HOST_BEHAV_NO_PHYLOCK); | |
dc6d0744 MC |
6986 | tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, |
6987 | TG3_APE_HOST_DRVR_STATE_START); | |
33f401ae MC |
6988 | |
6989 | event = APE_EVENT_STATUS_STATE_START; | |
6990 | break; | |
6991 | case RESET_KIND_SHUTDOWN: | |
6992 | /* With the interface we are currently using, | |
6993 | * APE does not track driver state. Wiping | |
6994 | * out the HOST SEGMENT SIGNATURE forces | |
6995 | * the APE to assume OS absent status. | |
6996 | */ | |
6997 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0); | |
b2aee154 | 6998 | |
dc6d0744 | 6999 | if (device_may_wakeup(&tp->pdev->dev) && |
63c3a66f | 7000 | tg3_flag(tp, WOL_ENABLE)) { |
dc6d0744 MC |
7001 | tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED, |
7002 | TG3_APE_HOST_WOL_SPEED_AUTO); | |
7003 | apedata = TG3_APE_HOST_DRVR_STATE_WOL; | |
7004 | } else | |
7005 | apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD; | |
7006 | ||
7007 | tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata); | |
7008 | ||
33f401ae MC |
7009 | event = APE_EVENT_STATUS_STATE_UNLOAD; |
7010 | break; | |
7011 | case RESET_KIND_SUSPEND: | |
7012 | event = APE_EVENT_STATUS_STATE_SUSPEND; | |
7013 | break; | |
7014 | default: | |
7015 | return; | |
0d3031d9 MC |
7016 | } |
7017 | ||
7018 | event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE; | |
7019 | ||
7020 | tg3_ape_send_event(tp, event); | |
7021 | } | |
7022 | ||
1da177e4 LT |
7023 | /* tp->lock is held. */ |
7024 | static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind) | |
7025 | { | |
f49639e6 DM |
7026 | tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX, |
7027 | NIC_SRAM_FIRMWARE_MBOX_MAGIC1); | |
1da177e4 | 7028 | |
63c3a66f | 7029 | if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) { |
1da177e4 LT |
7030 | switch (kind) { |
7031 | case RESET_KIND_INIT: | |
7032 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
7033 | DRV_STATE_START); | |
7034 | break; | |
7035 | ||
7036 | case RESET_KIND_SHUTDOWN: | |
7037 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
7038 | DRV_STATE_UNLOAD); | |
7039 | break; | |
7040 | ||
7041 | case RESET_KIND_SUSPEND: | |
7042 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
7043 | DRV_STATE_SUSPEND); | |
7044 | break; | |
7045 | ||
7046 | default: | |
7047 | break; | |
855e1111 | 7048 | } |
1da177e4 | 7049 | } |
0d3031d9 MC |
7050 | |
7051 | if (kind == RESET_KIND_INIT || | |
7052 | kind == RESET_KIND_SUSPEND) | |
7053 | tg3_ape_driver_state_change(tp, kind); | |
1da177e4 LT |
7054 | } |
7055 | ||
7056 | /* tp->lock is held. */ | |
7057 | static void tg3_write_sig_post_reset(struct tg3 *tp, int kind) | |
7058 | { | |
63c3a66f | 7059 | if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) { |
1da177e4 LT |
7060 | switch (kind) { |
7061 | case RESET_KIND_INIT: | |
7062 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
7063 | DRV_STATE_START_DONE); | |
7064 | break; | |
7065 | ||
7066 | case RESET_KIND_SHUTDOWN: | |
7067 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
7068 | DRV_STATE_UNLOAD_DONE); | |
7069 | break; | |
7070 | ||
7071 | default: | |
7072 | break; | |
855e1111 | 7073 | } |
1da177e4 | 7074 | } |
0d3031d9 MC |
7075 | |
7076 | if (kind == RESET_KIND_SHUTDOWN) | |
7077 | tg3_ape_driver_state_change(tp, kind); | |
1da177e4 LT |
7078 | } |
7079 | ||
7080 | /* tp->lock is held. */ | |
7081 | static void tg3_write_sig_legacy(struct tg3 *tp, int kind) | |
7082 | { | |
63c3a66f | 7083 | if (tg3_flag(tp, ENABLE_ASF)) { |
1da177e4 LT |
7084 | switch (kind) { |
7085 | case RESET_KIND_INIT: | |
7086 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
7087 | DRV_STATE_START); | |
7088 | break; | |
7089 | ||
7090 | case RESET_KIND_SHUTDOWN: | |
7091 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
7092 | DRV_STATE_UNLOAD); | |
7093 | break; | |
7094 | ||
7095 | case RESET_KIND_SUSPEND: | |
7096 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
7097 | DRV_STATE_SUSPEND); | |
7098 | break; | |
7099 | ||
7100 | default: | |
7101 | break; | |
855e1111 | 7102 | } |
1da177e4 LT |
7103 | } |
7104 | } | |
7105 | ||
7a6f4369 MC |
7106 | static int tg3_poll_fw(struct tg3 *tp) |
7107 | { | |
7108 | int i; | |
7109 | u32 val; | |
7110 | ||
b5d3772c | 7111 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
0ccead18 GZ |
7112 | /* Wait up to 20ms for init done. */ |
7113 | for (i = 0; i < 200; i++) { | |
b5d3772c MC |
7114 | if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE) |
7115 | return 0; | |
0ccead18 | 7116 | udelay(100); |
b5d3772c MC |
7117 | } |
7118 | return -ENODEV; | |
7119 | } | |
7120 | ||
7a6f4369 MC |
7121 | /* Wait for firmware initialization to complete. */ |
7122 | for (i = 0; i < 100000; i++) { | |
7123 | tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val); | |
7124 | if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1) | |
7125 | break; | |
7126 | udelay(10); | |
7127 | } | |
7128 | ||
7129 | /* Chip might not be fitted with firmware. Some Sun onboard | |
7130 | * parts are configured like that. So don't signal the timeout | |
7131 | * of the above loop as an error, but do report the lack of | |
7132 | * running firmware once. | |
7133 | */ | |
63c3a66f JP |
7134 | if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) { |
7135 | tg3_flag_set(tp, NO_FWARE_REPORTED); | |
7a6f4369 | 7136 | |
05dbe005 | 7137 | netdev_info(tp->dev, "No firmware running\n"); |
7a6f4369 MC |
7138 | } |
7139 | ||
6b10c165 MC |
7140 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) { |
7141 | /* The 57765 A0 needs a little more | |
7142 | * time to do some important work. | |
7143 | */ | |
7144 | mdelay(10); | |
7145 | } | |
7146 | ||
7a6f4369 MC |
7147 | return 0; |
7148 | } | |
7149 | ||
ee6a99b5 MC |
7150 | /* Save PCI command register before chip reset */ |
7151 | static void tg3_save_pci_state(struct tg3 *tp) | |
7152 | { | |
8a6eac90 | 7153 | pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd); |
ee6a99b5 MC |
7154 | } |
7155 | ||
7156 | /* Restore PCI state after chip reset */ | |
7157 | static void tg3_restore_pci_state(struct tg3 *tp) | |
7158 | { | |
7159 | u32 val; | |
7160 | ||
7161 | /* Re-enable indirect register accesses. */ | |
7162 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
7163 | tp->misc_host_ctrl); | |
7164 | ||
7165 | /* Set MAX PCI retry to zero. */ | |
7166 | val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE); | |
7167 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 && | |
63c3a66f | 7168 | tg3_flag(tp, PCIX_MODE)) |
ee6a99b5 | 7169 | val |= PCISTATE_RETRY_SAME_DMA; |
0d3031d9 | 7170 | /* Allow reads and writes to the APE register and memory space. */ |
63c3a66f | 7171 | if (tg3_flag(tp, ENABLE_APE)) |
0d3031d9 | 7172 | val |= PCISTATE_ALLOW_APE_CTLSPC_WR | |
f92d9dc1 MC |
7173 | PCISTATE_ALLOW_APE_SHMEM_WR | |
7174 | PCISTATE_ALLOW_APE_PSPACE_WR; | |
ee6a99b5 MC |
7175 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val); |
7176 | ||
8a6eac90 | 7177 | pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd); |
ee6a99b5 | 7178 | |
fcb389df | 7179 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) { |
63c3a66f | 7180 | if (tg3_flag(tp, PCI_EXPRESS)) |
cf79003d | 7181 | pcie_set_readrq(tp->pdev, tp->pcie_readrq); |
fcb389df MC |
7182 | else { |
7183 | pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, | |
7184 | tp->pci_cacheline_sz); | |
7185 | pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, | |
7186 | tp->pci_lat_timer); | |
7187 | } | |
114342f2 | 7188 | } |
5f5c51e3 | 7189 | |
ee6a99b5 | 7190 | /* Make sure PCI-X relaxed ordering bit is clear. */ |
63c3a66f | 7191 | if (tg3_flag(tp, PCIX_MODE)) { |
9974a356 MC |
7192 | u16 pcix_cmd; |
7193 | ||
7194 | pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
7195 | &pcix_cmd); | |
7196 | pcix_cmd &= ~PCI_X_CMD_ERO; | |
7197 | pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
7198 | pcix_cmd); | |
7199 | } | |
ee6a99b5 | 7200 | |
63c3a66f | 7201 | if (tg3_flag(tp, 5780_CLASS)) { |
ee6a99b5 MC |
7202 | |
7203 | /* Chip reset on 5780 will reset MSI enable bit, | |
7204 | * so need to restore it. | |
7205 | */ | |
63c3a66f | 7206 | if (tg3_flag(tp, USING_MSI)) { |
ee6a99b5 MC |
7207 | u16 ctrl; |
7208 | ||
7209 | pci_read_config_word(tp->pdev, | |
7210 | tp->msi_cap + PCI_MSI_FLAGS, | |
7211 | &ctrl); | |
7212 | pci_write_config_word(tp->pdev, | |
7213 | tp->msi_cap + PCI_MSI_FLAGS, | |
7214 | ctrl | PCI_MSI_FLAGS_ENABLE); | |
7215 | val = tr32(MSGINT_MODE); | |
7216 | tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE); | |
7217 | } | |
7218 | } | |
7219 | } | |
7220 | ||
1da177e4 LT |
7221 | static void tg3_stop_fw(struct tg3 *); |
7222 | ||
7223 | /* tp->lock is held. */ | |
7224 | static int tg3_chip_reset(struct tg3 *tp) | |
7225 | { | |
7226 | u32 val; | |
1ee582d8 | 7227 | void (*write_op)(struct tg3 *, u32, u32); |
4f125f42 | 7228 | int i, err; |
1da177e4 | 7229 | |
f49639e6 DM |
7230 | tg3_nvram_lock(tp); |
7231 | ||
77b483f1 MC |
7232 | tg3_ape_lock(tp, TG3_APE_LOCK_GRC); |
7233 | ||
f49639e6 DM |
7234 | /* No matching tg3_nvram_unlock() after this because |
7235 | * chip reset below will undo the nvram lock. | |
7236 | */ | |
7237 | tp->nvram_lock_cnt = 0; | |
1da177e4 | 7238 | |
ee6a99b5 MC |
7239 | /* GRC_MISC_CFG core clock reset will clear the memory |
7240 | * enable bit in PCI register 4 and the MSI enable bit | |
7241 | * on some chips, so we save relevant registers here. | |
7242 | */ | |
7243 | tg3_save_pci_state(tp); | |
7244 | ||
d9ab5ad1 | 7245 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || |
63c3a66f | 7246 | tg3_flag(tp, 5755_PLUS)) |
d9ab5ad1 MC |
7247 | tw32(GRC_FASTBOOT_PC, 0); |
7248 | ||
1da177e4 LT |
7249 | /* |
7250 | * We must avoid the readl() that normally takes place. | |
7251 | * It locks machines, causes machine checks, and other | |
7252 | * fun things. So, temporarily disable the 5701 | |
7253 | * hardware workaround, while we do the reset. | |
7254 | */ | |
1ee582d8 MC |
7255 | write_op = tp->write32; |
7256 | if (write_op == tg3_write_flush_reg32) | |
7257 | tp->write32 = tg3_write32; | |
1da177e4 | 7258 | |
d18edcb2 MC |
7259 | /* Prevent the irq handler from reading or writing PCI registers |
7260 | * during chip reset when the memory enable bit in the PCI command | |
7261 | * register may be cleared. The chip does not generate interrupt | |
7262 | * at this time, but the irq handler may still be called due to irq | |
7263 | * sharing or irqpoll. | |
7264 | */ | |
63c3a66f | 7265 | tg3_flag_set(tp, CHIP_RESETTING); |
f77a6a8e MC |
7266 | for (i = 0; i < tp->irq_cnt; i++) { |
7267 | struct tg3_napi *tnapi = &tp->napi[i]; | |
7268 | if (tnapi->hw_status) { | |
7269 | tnapi->hw_status->status = 0; | |
7270 | tnapi->hw_status->status_tag = 0; | |
7271 | } | |
7272 | tnapi->last_tag = 0; | |
7273 | tnapi->last_irq_tag = 0; | |
b8fa2f3a | 7274 | } |
d18edcb2 | 7275 | smp_mb(); |
4f125f42 MC |
7276 | |
7277 | for (i = 0; i < tp->irq_cnt; i++) | |
7278 | synchronize_irq(tp->napi[i].irq_vec); | |
d18edcb2 | 7279 | |
255ca311 MC |
7280 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { |
7281 | val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN; | |
7282 | tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS); | |
7283 | } | |
7284 | ||
1da177e4 LT |
7285 | /* do the reset */ |
7286 | val = GRC_MISC_CFG_CORECLK_RESET; | |
7287 | ||
63c3a66f | 7288 | if (tg3_flag(tp, PCI_EXPRESS)) { |
88075d91 MC |
7289 | /* Force PCIe 1.0a mode */ |
7290 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && | |
63c3a66f | 7291 | !tg3_flag(tp, 57765_PLUS) && |
88075d91 MC |
7292 | tr32(TG3_PCIE_PHY_TSTCTL) == |
7293 | (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM)) | |
7294 | tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM); | |
7295 | ||
1da177e4 LT |
7296 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) { |
7297 | tw32(GRC_MISC_CFG, (1 << 29)); | |
7298 | val |= (1 << 29); | |
7299 | } | |
7300 | } | |
7301 | ||
b5d3772c MC |
7302 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
7303 | tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET); | |
7304 | tw32(GRC_VCPU_EXT_CTRL, | |
7305 | tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU); | |
7306 | } | |
7307 | ||
f37500d3 | 7308 | /* Manage gphy power for all CPMU absent PCIe devices. */ |
63c3a66f | 7309 | if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT)) |
1da177e4 | 7310 | val |= GRC_MISC_CFG_KEEP_GPHY_POWER; |
f37500d3 | 7311 | |
1da177e4 LT |
7312 | tw32(GRC_MISC_CFG, val); |
7313 | ||
1ee582d8 MC |
7314 | /* restore 5701 hardware bug workaround write method */ |
7315 | tp->write32 = write_op; | |
1da177e4 LT |
7316 | |
7317 | /* Unfortunately, we have to delay before the PCI read back. | |
7318 | * Some 575X chips even will not respond to a PCI cfg access | |
7319 | * when the reset command is given to the chip. | |
7320 | * | |
7321 | * How do these hardware designers expect things to work | |
7322 | * properly if the PCI write is posted for a long period | |
7323 | * of time? It is always necessary to have some method by | |
7324 | * which a register read back can occur to push the write | |
7325 | * out which does the reset. | |
7326 | * | |
7327 | * For most tg3 variants the trick below was working. | |
7328 | * Ho hum... | |
7329 | */ | |
7330 | udelay(120); | |
7331 | ||
7332 | /* Flush PCI posted writes. The normal MMIO registers | |
7333 | * are inaccessible at this time so this is the only | |
7334 | * way to make this reliably (actually, this is no longer | |
7335 | * the case, see above). I tried to use indirect | |
7336 | * register read/write but this upset some 5701 variants. | |
7337 | */ | |
7338 | pci_read_config_dword(tp->pdev, PCI_COMMAND, &val); | |
7339 | ||
7340 | udelay(120); | |
7341 | ||
708ebb3a | 7342 | if (tg3_flag(tp, PCI_EXPRESS) && pci_pcie_cap(tp->pdev)) { |
e7126997 MC |
7343 | u16 val16; |
7344 | ||
1da177e4 LT |
7345 | if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) { |
7346 | int i; | |
7347 | u32 cfg_val; | |
7348 | ||
7349 | /* Wait for link training to complete. */ | |
7350 | for (i = 0; i < 5000; i++) | |
7351 | udelay(100); | |
7352 | ||
7353 | pci_read_config_dword(tp->pdev, 0xc4, &cfg_val); | |
7354 | pci_write_config_dword(tp->pdev, 0xc4, | |
7355 | cfg_val | (1 << 15)); | |
7356 | } | |
5e7dfd0f | 7357 | |
e7126997 MC |
7358 | /* Clear the "no snoop" and "relaxed ordering" bits. */ |
7359 | pci_read_config_word(tp->pdev, | |
708ebb3a | 7360 | pci_pcie_cap(tp->pdev) + PCI_EXP_DEVCTL, |
e7126997 MC |
7361 | &val16); |
7362 | val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN | | |
7363 | PCI_EXP_DEVCTL_NOSNOOP_EN); | |
7364 | /* | |
7365 | * Older PCIe devices only support the 128 byte | |
7366 | * MPS setting. Enforce the restriction. | |
5e7dfd0f | 7367 | */ |
63c3a66f | 7368 | if (!tg3_flag(tp, CPMU_PRESENT)) |
e7126997 | 7369 | val16 &= ~PCI_EXP_DEVCTL_PAYLOAD; |
5e7dfd0f | 7370 | pci_write_config_word(tp->pdev, |
708ebb3a | 7371 | pci_pcie_cap(tp->pdev) + PCI_EXP_DEVCTL, |
e7126997 | 7372 | val16); |
5e7dfd0f | 7373 | |
cf79003d | 7374 | pcie_set_readrq(tp->pdev, tp->pcie_readrq); |
5e7dfd0f MC |
7375 | |
7376 | /* Clear error status */ | |
7377 | pci_write_config_word(tp->pdev, | |
708ebb3a | 7378 | pci_pcie_cap(tp->pdev) + PCI_EXP_DEVSTA, |
5e7dfd0f MC |
7379 | PCI_EXP_DEVSTA_CED | |
7380 | PCI_EXP_DEVSTA_NFED | | |
7381 | PCI_EXP_DEVSTA_FED | | |
7382 | PCI_EXP_DEVSTA_URD); | |
1da177e4 LT |
7383 | } |
7384 | ||
ee6a99b5 | 7385 | tg3_restore_pci_state(tp); |
1da177e4 | 7386 | |
63c3a66f JP |
7387 | tg3_flag_clear(tp, CHIP_RESETTING); |
7388 | tg3_flag_clear(tp, ERROR_PROCESSED); | |
d18edcb2 | 7389 | |
ee6a99b5 | 7390 | val = 0; |
63c3a66f | 7391 | if (tg3_flag(tp, 5780_CLASS)) |
4cf78e4f | 7392 | val = tr32(MEMARB_MODE); |
ee6a99b5 | 7393 | tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE); |
1da177e4 LT |
7394 | |
7395 | if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) { | |
7396 | tg3_stop_fw(tp); | |
7397 | tw32(0x5000, 0x400); | |
7398 | } | |
7399 | ||
7400 | tw32(GRC_MODE, tp->grc_mode); | |
7401 | ||
7402 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) { | |
ab0049b4 | 7403 | val = tr32(0xc4); |
1da177e4 LT |
7404 | |
7405 | tw32(0xc4, val | (1 << 15)); | |
7406 | } | |
7407 | ||
7408 | if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 && | |
7409 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
7410 | tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE; | |
7411 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) | |
7412 | tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN; | |
7413 | tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); | |
7414 | } | |
7415 | ||
f07e9af3 | 7416 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
9e975cc2 | 7417 | tp->mac_mode = MAC_MODE_PORT_MODE_TBI; |
d2394e6b | 7418 | val = tp->mac_mode; |
f07e9af3 | 7419 | } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { |
9e975cc2 | 7420 | tp->mac_mode = MAC_MODE_PORT_MODE_GMII; |
d2394e6b | 7421 | val = tp->mac_mode; |
1da177e4 | 7422 | } else |
d2394e6b MC |
7423 | val = 0; |
7424 | ||
7425 | tw32_f(MAC_MODE, val); | |
1da177e4 LT |
7426 | udelay(40); |
7427 | ||
77b483f1 MC |
7428 | tg3_ape_unlock(tp, TG3_APE_LOCK_GRC); |
7429 | ||
7a6f4369 MC |
7430 | err = tg3_poll_fw(tp); |
7431 | if (err) | |
7432 | return err; | |
1da177e4 | 7433 | |
0a9140cf MC |
7434 | tg3_mdio_start(tp); |
7435 | ||
63c3a66f | 7436 | if (tg3_flag(tp, PCI_EXPRESS) && |
f6eb9b1f MC |
7437 | tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 && |
7438 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && | |
63c3a66f | 7439 | !tg3_flag(tp, 57765_PLUS)) { |
ab0049b4 | 7440 | val = tr32(0x7c00); |
1da177e4 LT |
7441 | |
7442 | tw32(0x7c00, val | (1 << 25)); | |
7443 | } | |
7444 | ||
d78b59f5 MC |
7445 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { |
7446 | val = tr32(TG3_CPMU_CLCK_ORIDE); | |
7447 | tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN); | |
7448 | } | |
7449 | ||
1da177e4 | 7450 | /* Reprobe ASF enable state. */ |
63c3a66f JP |
7451 | tg3_flag_clear(tp, ENABLE_ASF); |
7452 | tg3_flag_clear(tp, ASF_NEW_HANDSHAKE); | |
1da177e4 LT |
7453 | tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); |
7454 | if (val == NIC_SRAM_DATA_SIG_MAGIC) { | |
7455 | u32 nic_cfg; | |
7456 | ||
7457 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); | |
7458 | if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) { | |
63c3a66f | 7459 | tg3_flag_set(tp, ENABLE_ASF); |
4ba526ce | 7460 | tp->last_event_jiffies = jiffies; |
63c3a66f JP |
7461 | if (tg3_flag(tp, 5750_PLUS)) |
7462 | tg3_flag_set(tp, ASF_NEW_HANDSHAKE); | |
1da177e4 LT |
7463 | } |
7464 | } | |
7465 | ||
7466 | return 0; | |
7467 | } | |
7468 | ||
7469 | /* tp->lock is held. */ | |
7470 | static void tg3_stop_fw(struct tg3 *tp) | |
7471 | { | |
63c3a66f | 7472 | if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) { |
7c5026aa MC |
7473 | /* Wait for RX cpu to ACK the previous event. */ |
7474 | tg3_wait_for_event_ack(tp); | |
1da177e4 LT |
7475 | |
7476 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW); | |
4ba526ce MC |
7477 | |
7478 | tg3_generate_fw_event(tp); | |
1da177e4 | 7479 | |
7c5026aa MC |
7480 | /* Wait for RX cpu to ACK this event. */ |
7481 | tg3_wait_for_event_ack(tp); | |
1da177e4 LT |
7482 | } |
7483 | } | |
7484 | ||
7485 | /* tp->lock is held. */ | |
944d980e | 7486 | static int tg3_halt(struct tg3 *tp, int kind, int silent) |
1da177e4 LT |
7487 | { |
7488 | int err; | |
7489 | ||
7490 | tg3_stop_fw(tp); | |
7491 | ||
944d980e | 7492 | tg3_write_sig_pre_reset(tp, kind); |
1da177e4 | 7493 | |
b3b7d6be | 7494 | tg3_abort_hw(tp, silent); |
1da177e4 LT |
7495 | err = tg3_chip_reset(tp); |
7496 | ||
daba2a63 MC |
7497 | __tg3_set_mac_addr(tp, 0); |
7498 | ||
944d980e MC |
7499 | tg3_write_sig_legacy(tp, kind); |
7500 | tg3_write_sig_post_reset(tp, kind); | |
1da177e4 LT |
7501 | |
7502 | if (err) | |
7503 | return err; | |
7504 | ||
7505 | return 0; | |
7506 | } | |
7507 | ||
1da177e4 LT |
7508 | #define RX_CPU_SCRATCH_BASE 0x30000 |
7509 | #define RX_CPU_SCRATCH_SIZE 0x04000 | |
7510 | #define TX_CPU_SCRATCH_BASE 0x34000 | |
7511 | #define TX_CPU_SCRATCH_SIZE 0x04000 | |
7512 | ||
7513 | /* tp->lock is held. */ | |
7514 | static int tg3_halt_cpu(struct tg3 *tp, u32 offset) | |
7515 | { | |
7516 | int i; | |
7517 | ||
63c3a66f | 7518 | BUG_ON(offset == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)); |
1da177e4 | 7519 | |
b5d3772c MC |
7520 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
7521 | u32 val = tr32(GRC_VCPU_EXT_CTRL); | |
7522 | ||
7523 | tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU); | |
7524 | return 0; | |
7525 | } | |
1da177e4 LT |
7526 | if (offset == RX_CPU_BASE) { |
7527 | for (i = 0; i < 10000; i++) { | |
7528 | tw32(offset + CPU_STATE, 0xffffffff); | |
7529 | tw32(offset + CPU_MODE, CPU_MODE_HALT); | |
7530 | if (tr32(offset + CPU_MODE) & CPU_MODE_HALT) | |
7531 | break; | |
7532 | } | |
7533 | ||
7534 | tw32(offset + CPU_STATE, 0xffffffff); | |
7535 | tw32_f(offset + CPU_MODE, CPU_MODE_HALT); | |
7536 | udelay(10); | |
7537 | } else { | |
7538 | for (i = 0; i < 10000; i++) { | |
7539 | tw32(offset + CPU_STATE, 0xffffffff); | |
7540 | tw32(offset + CPU_MODE, CPU_MODE_HALT); | |
7541 | if (tr32(offset + CPU_MODE) & CPU_MODE_HALT) | |
7542 | break; | |
7543 | } | |
7544 | } | |
7545 | ||
7546 | if (i >= 10000) { | |
05dbe005 JP |
7547 | netdev_err(tp->dev, "%s timed out, %s CPU\n", |
7548 | __func__, offset == RX_CPU_BASE ? "RX" : "TX"); | |
1da177e4 LT |
7549 | return -ENODEV; |
7550 | } | |
ec41c7df MC |
7551 | |
7552 | /* Clear firmware's nvram arbitration. */ | |
63c3a66f | 7553 | if (tg3_flag(tp, NVRAM)) |
ec41c7df | 7554 | tw32(NVRAM_SWARB, SWARB_REQ_CLR0); |
1da177e4 LT |
7555 | return 0; |
7556 | } | |
7557 | ||
7558 | struct fw_info { | |
077f849d JSR |
7559 | unsigned int fw_base; |
7560 | unsigned int fw_len; | |
7561 | const __be32 *fw_data; | |
1da177e4 LT |
7562 | }; |
7563 | ||
7564 | /* tp->lock is held. */ | |
7565 | static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base, | |
7566 | int cpu_scratch_size, struct fw_info *info) | |
7567 | { | |
ec41c7df | 7568 | int err, lock_err, i; |
1da177e4 LT |
7569 | void (*write_op)(struct tg3 *, u32, u32); |
7570 | ||
63c3a66f | 7571 | if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) { |
5129c3a3 MC |
7572 | netdev_err(tp->dev, |
7573 | "%s: Trying to load TX cpu firmware which is 5705\n", | |
05dbe005 | 7574 | __func__); |
1da177e4 LT |
7575 | return -EINVAL; |
7576 | } | |
7577 | ||
63c3a66f | 7578 | if (tg3_flag(tp, 5705_PLUS)) |
1da177e4 LT |
7579 | write_op = tg3_write_mem; |
7580 | else | |
7581 | write_op = tg3_write_indirect_reg32; | |
7582 | ||
1b628151 MC |
7583 | /* It is possible that bootcode is still loading at this point. |
7584 | * Get the nvram lock first before halting the cpu. | |
7585 | */ | |
ec41c7df | 7586 | lock_err = tg3_nvram_lock(tp); |
1da177e4 | 7587 | err = tg3_halt_cpu(tp, cpu_base); |
ec41c7df MC |
7588 | if (!lock_err) |
7589 | tg3_nvram_unlock(tp); | |
1da177e4 LT |
7590 | if (err) |
7591 | goto out; | |
7592 | ||
7593 | for (i = 0; i < cpu_scratch_size; i += sizeof(u32)) | |
7594 | write_op(tp, cpu_scratch_base + i, 0); | |
7595 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
7596 | tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT); | |
077f849d | 7597 | for (i = 0; i < (info->fw_len / sizeof(u32)); i++) |
1da177e4 | 7598 | write_op(tp, (cpu_scratch_base + |
077f849d | 7599 | (info->fw_base & 0xffff) + |
1da177e4 | 7600 | (i * sizeof(u32))), |
077f849d | 7601 | be32_to_cpu(info->fw_data[i])); |
1da177e4 LT |
7602 | |
7603 | err = 0; | |
7604 | ||
7605 | out: | |
1da177e4 LT |
7606 | return err; |
7607 | } | |
7608 | ||
7609 | /* tp->lock is held. */ | |
7610 | static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp) | |
7611 | { | |
7612 | struct fw_info info; | |
077f849d | 7613 | const __be32 *fw_data; |
1da177e4 LT |
7614 | int err, i; |
7615 | ||
077f849d JSR |
7616 | fw_data = (void *)tp->fw->data; |
7617 | ||
7618 | /* Firmware blob starts with version numbers, followed by | |
7619 | start address and length. We are setting complete length. | |
7620 | length = end_address_of_bss - start_address_of_text. | |
7621 | Remainder is the blob to be loaded contiguously | |
7622 | from start address. */ | |
7623 | ||
7624 | info.fw_base = be32_to_cpu(fw_data[1]); | |
7625 | info.fw_len = tp->fw->size - 12; | |
7626 | info.fw_data = &fw_data[3]; | |
1da177e4 LT |
7627 | |
7628 | err = tg3_load_firmware_cpu(tp, RX_CPU_BASE, | |
7629 | RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE, | |
7630 | &info); | |
7631 | if (err) | |
7632 | return err; | |
7633 | ||
7634 | err = tg3_load_firmware_cpu(tp, TX_CPU_BASE, | |
7635 | TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE, | |
7636 | &info); | |
7637 | if (err) | |
7638 | return err; | |
7639 | ||
7640 | /* Now startup only the RX cpu. */ | |
7641 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
077f849d | 7642 | tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base); |
1da177e4 LT |
7643 | |
7644 | for (i = 0; i < 5; i++) { | |
077f849d | 7645 | if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base) |
1da177e4 LT |
7646 | break; |
7647 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
7648 | tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT); | |
077f849d | 7649 | tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base); |
1da177e4 LT |
7650 | udelay(1000); |
7651 | } | |
7652 | if (i >= 5) { | |
5129c3a3 MC |
7653 | netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x " |
7654 | "should be %08x\n", __func__, | |
05dbe005 | 7655 | tr32(RX_CPU_BASE + CPU_PC), info.fw_base); |
1da177e4 LT |
7656 | return -ENODEV; |
7657 | } | |
7658 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
7659 | tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000); | |
7660 | ||
7661 | return 0; | |
7662 | } | |
7663 | ||
1da177e4 LT |
7664 | /* tp->lock is held. */ |
7665 | static int tg3_load_tso_firmware(struct tg3 *tp) | |
7666 | { | |
7667 | struct fw_info info; | |
077f849d | 7668 | const __be32 *fw_data; |
1da177e4 LT |
7669 | unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size; |
7670 | int err, i; | |
7671 | ||
63c3a66f JP |
7672 | if (tg3_flag(tp, HW_TSO_1) || |
7673 | tg3_flag(tp, HW_TSO_2) || | |
7674 | tg3_flag(tp, HW_TSO_3)) | |
1da177e4 LT |
7675 | return 0; |
7676 | ||
077f849d JSR |
7677 | fw_data = (void *)tp->fw->data; |
7678 | ||
7679 | /* Firmware blob starts with version numbers, followed by | |
7680 | start address and length. We are setting complete length. | |
7681 | length = end_address_of_bss - start_address_of_text. | |
7682 | Remainder is the blob to be loaded contiguously | |
7683 | from start address. */ | |
7684 | ||
7685 | info.fw_base = be32_to_cpu(fw_data[1]); | |
7686 | cpu_scratch_size = tp->fw_len; | |
7687 | info.fw_len = tp->fw->size - 12; | |
7688 | info.fw_data = &fw_data[3]; | |
7689 | ||
1da177e4 | 7690 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { |
1da177e4 LT |
7691 | cpu_base = RX_CPU_BASE; |
7692 | cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705; | |
1da177e4 | 7693 | } else { |
1da177e4 LT |
7694 | cpu_base = TX_CPU_BASE; |
7695 | cpu_scratch_base = TX_CPU_SCRATCH_BASE; | |
7696 | cpu_scratch_size = TX_CPU_SCRATCH_SIZE; | |
7697 | } | |
7698 | ||
7699 | err = tg3_load_firmware_cpu(tp, cpu_base, | |
7700 | cpu_scratch_base, cpu_scratch_size, | |
7701 | &info); | |
7702 | if (err) | |
7703 | return err; | |
7704 | ||
7705 | /* Now startup the cpu. */ | |
7706 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
077f849d | 7707 | tw32_f(cpu_base + CPU_PC, info.fw_base); |
1da177e4 LT |
7708 | |
7709 | for (i = 0; i < 5; i++) { | |
077f849d | 7710 | if (tr32(cpu_base + CPU_PC) == info.fw_base) |
1da177e4 LT |
7711 | break; |
7712 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
7713 | tw32(cpu_base + CPU_MODE, CPU_MODE_HALT); | |
077f849d | 7714 | tw32_f(cpu_base + CPU_PC, info.fw_base); |
1da177e4 LT |
7715 | udelay(1000); |
7716 | } | |
7717 | if (i >= 5) { | |
5129c3a3 MC |
7718 | netdev_err(tp->dev, |
7719 | "%s fails to set CPU PC, is %08x should be %08x\n", | |
05dbe005 | 7720 | __func__, tr32(cpu_base + CPU_PC), info.fw_base); |
1da177e4 LT |
7721 | return -ENODEV; |
7722 | } | |
7723 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
7724 | tw32_f(cpu_base + CPU_MODE, 0x00000000); | |
7725 | return 0; | |
7726 | } | |
7727 | ||
1da177e4 | 7728 | |
1da177e4 LT |
7729 | static int tg3_set_mac_addr(struct net_device *dev, void *p) |
7730 | { | |
7731 | struct tg3 *tp = netdev_priv(dev); | |
7732 | struct sockaddr *addr = p; | |
986e0aeb | 7733 | int err = 0, skip_mac_1 = 0; |
1da177e4 | 7734 | |
f9804ddb MC |
7735 | if (!is_valid_ether_addr(addr->sa_data)) |
7736 | return -EINVAL; | |
7737 | ||
1da177e4 LT |
7738 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); |
7739 | ||
e75f7c90 MC |
7740 | if (!netif_running(dev)) |
7741 | return 0; | |
7742 | ||
63c3a66f | 7743 | if (tg3_flag(tp, ENABLE_ASF)) { |
986e0aeb | 7744 | u32 addr0_high, addr0_low, addr1_high, addr1_low; |
58712ef9 | 7745 | |
986e0aeb MC |
7746 | addr0_high = tr32(MAC_ADDR_0_HIGH); |
7747 | addr0_low = tr32(MAC_ADDR_0_LOW); | |
7748 | addr1_high = tr32(MAC_ADDR_1_HIGH); | |
7749 | addr1_low = tr32(MAC_ADDR_1_LOW); | |
7750 | ||
7751 | /* Skip MAC addr 1 if ASF is using it. */ | |
7752 | if ((addr0_high != addr1_high || addr0_low != addr1_low) && | |
7753 | !(addr1_high == 0 && addr1_low == 0)) | |
7754 | skip_mac_1 = 1; | |
58712ef9 | 7755 | } |
986e0aeb MC |
7756 | spin_lock_bh(&tp->lock); |
7757 | __tg3_set_mac_addr(tp, skip_mac_1); | |
7758 | spin_unlock_bh(&tp->lock); | |
1da177e4 | 7759 | |
b9ec6c1b | 7760 | return err; |
1da177e4 LT |
7761 | } |
7762 | ||
7763 | /* tp->lock is held. */ | |
7764 | static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr, | |
7765 | dma_addr_t mapping, u32 maxlen_flags, | |
7766 | u32 nic_addr) | |
7767 | { | |
7768 | tg3_write_mem(tp, | |
7769 | (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH), | |
7770 | ((u64) mapping >> 32)); | |
7771 | tg3_write_mem(tp, | |
7772 | (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW), | |
7773 | ((u64) mapping & 0xffffffff)); | |
7774 | tg3_write_mem(tp, | |
7775 | (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS), | |
7776 | maxlen_flags); | |
7777 | ||
63c3a66f | 7778 | if (!tg3_flag(tp, 5705_PLUS)) |
1da177e4 LT |
7779 | tg3_write_mem(tp, |
7780 | (bdinfo_addr + TG3_BDINFO_NIC_ADDR), | |
7781 | nic_addr); | |
7782 | } | |
7783 | ||
7784 | static void __tg3_set_rx_mode(struct net_device *); | |
d244c892 | 7785 | static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec) |
15f9850d | 7786 | { |
b6080e12 MC |
7787 | int i; |
7788 | ||
63c3a66f | 7789 | if (!tg3_flag(tp, ENABLE_TSS)) { |
b6080e12 MC |
7790 | tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs); |
7791 | tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames); | |
7792 | tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq); | |
b6080e12 MC |
7793 | } else { |
7794 | tw32(HOSTCC_TXCOL_TICKS, 0); | |
7795 | tw32(HOSTCC_TXMAX_FRAMES, 0); | |
7796 | tw32(HOSTCC_TXCOAL_MAXF_INT, 0); | |
19cfaecc | 7797 | } |
b6080e12 | 7798 | |
63c3a66f | 7799 | if (!tg3_flag(tp, ENABLE_RSS)) { |
19cfaecc MC |
7800 | tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs); |
7801 | tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames); | |
7802 | tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq); | |
7803 | } else { | |
b6080e12 MC |
7804 | tw32(HOSTCC_RXCOL_TICKS, 0); |
7805 | tw32(HOSTCC_RXMAX_FRAMES, 0); | |
7806 | tw32(HOSTCC_RXCOAL_MAXF_INT, 0); | |
15f9850d | 7807 | } |
b6080e12 | 7808 | |
63c3a66f | 7809 | if (!tg3_flag(tp, 5705_PLUS)) { |
15f9850d DM |
7810 | u32 val = ec->stats_block_coalesce_usecs; |
7811 | ||
b6080e12 MC |
7812 | tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq); |
7813 | tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq); | |
7814 | ||
15f9850d DM |
7815 | if (!netif_carrier_ok(tp->dev)) |
7816 | val = 0; | |
7817 | ||
7818 | tw32(HOSTCC_STAT_COAL_TICKS, val); | |
7819 | } | |
b6080e12 MC |
7820 | |
7821 | for (i = 0; i < tp->irq_cnt - 1; i++) { | |
7822 | u32 reg; | |
7823 | ||
7824 | reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18; | |
7825 | tw32(reg, ec->rx_coalesce_usecs); | |
b6080e12 MC |
7826 | reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18; |
7827 | tw32(reg, ec->rx_max_coalesced_frames); | |
b6080e12 MC |
7828 | reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18; |
7829 | tw32(reg, ec->rx_max_coalesced_frames_irq); | |
19cfaecc | 7830 | |
63c3a66f | 7831 | if (tg3_flag(tp, ENABLE_TSS)) { |
19cfaecc MC |
7832 | reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18; |
7833 | tw32(reg, ec->tx_coalesce_usecs); | |
7834 | reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18; | |
7835 | tw32(reg, ec->tx_max_coalesced_frames); | |
7836 | reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18; | |
7837 | tw32(reg, ec->tx_max_coalesced_frames_irq); | |
7838 | } | |
b6080e12 MC |
7839 | } |
7840 | ||
7841 | for (; i < tp->irq_max - 1; i++) { | |
7842 | tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0); | |
b6080e12 | 7843 | tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0); |
b6080e12 | 7844 | tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0); |
19cfaecc | 7845 | |
63c3a66f | 7846 | if (tg3_flag(tp, ENABLE_TSS)) { |
19cfaecc MC |
7847 | tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0); |
7848 | tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0); | |
7849 | tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0); | |
7850 | } | |
b6080e12 | 7851 | } |
15f9850d | 7852 | } |
1da177e4 | 7853 | |
2d31ecaf MC |
7854 | /* tp->lock is held. */ |
7855 | static void tg3_rings_reset(struct tg3 *tp) | |
7856 | { | |
7857 | int i; | |
f77a6a8e | 7858 | u32 stblk, txrcb, rxrcb, limit; |
2d31ecaf MC |
7859 | struct tg3_napi *tnapi = &tp->napi[0]; |
7860 | ||
7861 | /* Disable all transmit rings but the first. */ | |
63c3a66f | 7862 | if (!tg3_flag(tp, 5705_PLUS)) |
2d31ecaf | 7863 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16; |
63c3a66f | 7864 | else if (tg3_flag(tp, 5717_PLUS)) |
3d37728b | 7865 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4; |
b703df6f MC |
7866 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) |
7867 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2; | |
2d31ecaf MC |
7868 | else |
7869 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; | |
7870 | ||
7871 | for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; | |
7872 | txrcb < limit; txrcb += TG3_BDINFO_SIZE) | |
7873 | tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS, | |
7874 | BDINFO_FLAGS_DISABLED); | |
7875 | ||
7876 | ||
7877 | /* Disable all receive return rings but the first. */ | |
63c3a66f | 7878 | if (tg3_flag(tp, 5717_PLUS)) |
f6eb9b1f | 7879 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17; |
63c3a66f | 7880 | else if (!tg3_flag(tp, 5705_PLUS)) |
2d31ecaf | 7881 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16; |
b703df6f MC |
7882 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || |
7883 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
2d31ecaf MC |
7884 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4; |
7885 | else | |
7886 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; | |
7887 | ||
7888 | for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; | |
7889 | rxrcb < limit; rxrcb += TG3_BDINFO_SIZE) | |
7890 | tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS, | |
7891 | BDINFO_FLAGS_DISABLED); | |
7892 | ||
7893 | /* Disable interrupts */ | |
7894 | tw32_mailbox_f(tp->napi[0].int_mbox, 1); | |
0e6cf6a9 MC |
7895 | tp->napi[0].chk_msi_cnt = 0; |
7896 | tp->napi[0].last_rx_cons = 0; | |
7897 | tp->napi[0].last_tx_cons = 0; | |
2d31ecaf MC |
7898 | |
7899 | /* Zero mailbox registers. */ | |
63c3a66f | 7900 | if (tg3_flag(tp, SUPPORT_MSIX)) { |
6fd45cb8 | 7901 | for (i = 1; i < tp->irq_max; i++) { |
f77a6a8e MC |
7902 | tp->napi[i].tx_prod = 0; |
7903 | tp->napi[i].tx_cons = 0; | |
63c3a66f | 7904 | if (tg3_flag(tp, ENABLE_TSS)) |
c2353a32 | 7905 | tw32_mailbox(tp->napi[i].prodmbox, 0); |
f77a6a8e MC |
7906 | tw32_rx_mbox(tp->napi[i].consmbox, 0); |
7907 | tw32_mailbox_f(tp->napi[i].int_mbox, 1); | |
0e6cf6a9 MC |
7908 | tp->napi[0].chk_msi_cnt = 0; |
7909 | tp->napi[i].last_rx_cons = 0; | |
7910 | tp->napi[i].last_tx_cons = 0; | |
f77a6a8e | 7911 | } |
63c3a66f | 7912 | if (!tg3_flag(tp, ENABLE_TSS)) |
c2353a32 | 7913 | tw32_mailbox(tp->napi[0].prodmbox, 0); |
f77a6a8e MC |
7914 | } else { |
7915 | tp->napi[0].tx_prod = 0; | |
7916 | tp->napi[0].tx_cons = 0; | |
7917 | tw32_mailbox(tp->napi[0].prodmbox, 0); | |
7918 | tw32_rx_mbox(tp->napi[0].consmbox, 0); | |
7919 | } | |
2d31ecaf MC |
7920 | |
7921 | /* Make sure the NIC-based send BD rings are disabled. */ | |
63c3a66f | 7922 | if (!tg3_flag(tp, 5705_PLUS)) { |
2d31ecaf MC |
7923 | u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW; |
7924 | for (i = 0; i < 16; i++) | |
7925 | tw32_tx_mbox(mbox + i * 8, 0); | |
7926 | } | |
7927 | ||
7928 | txrcb = NIC_SRAM_SEND_RCB; | |
7929 | rxrcb = NIC_SRAM_RCV_RET_RCB; | |
7930 | ||
7931 | /* Clear status block in ram. */ | |
7932 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
7933 | ||
7934 | /* Set status block DMA address */ | |
7935 | tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, | |
7936 | ((u64) tnapi->status_mapping >> 32)); | |
7937 | tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, | |
7938 | ((u64) tnapi->status_mapping & 0xffffffff)); | |
7939 | ||
f77a6a8e MC |
7940 | if (tnapi->tx_ring) { |
7941 | tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping, | |
7942 | (TG3_TX_RING_SIZE << | |
7943 | BDINFO_FLAGS_MAXLEN_SHIFT), | |
7944 | NIC_SRAM_TX_BUFFER_DESC); | |
7945 | txrcb += TG3_BDINFO_SIZE; | |
7946 | } | |
7947 | ||
7948 | if (tnapi->rx_rcb) { | |
7949 | tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping, | |
7cb32cf2 MC |
7950 | (tp->rx_ret_ring_mask + 1) << |
7951 | BDINFO_FLAGS_MAXLEN_SHIFT, 0); | |
f77a6a8e MC |
7952 | rxrcb += TG3_BDINFO_SIZE; |
7953 | } | |
7954 | ||
7955 | stblk = HOSTCC_STATBLCK_RING1; | |
2d31ecaf | 7956 | |
f77a6a8e MC |
7957 | for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) { |
7958 | u64 mapping = (u64)tnapi->status_mapping; | |
7959 | tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32); | |
7960 | tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff); | |
7961 | ||
7962 | /* Clear status block in ram. */ | |
7963 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
7964 | ||
19cfaecc MC |
7965 | if (tnapi->tx_ring) { |
7966 | tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping, | |
7967 | (TG3_TX_RING_SIZE << | |
7968 | BDINFO_FLAGS_MAXLEN_SHIFT), | |
7969 | NIC_SRAM_TX_BUFFER_DESC); | |
7970 | txrcb += TG3_BDINFO_SIZE; | |
7971 | } | |
f77a6a8e MC |
7972 | |
7973 | tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping, | |
7cb32cf2 | 7974 | ((tp->rx_ret_ring_mask + 1) << |
f77a6a8e MC |
7975 | BDINFO_FLAGS_MAXLEN_SHIFT), 0); |
7976 | ||
7977 | stblk += 8; | |
f77a6a8e MC |
7978 | rxrcb += TG3_BDINFO_SIZE; |
7979 | } | |
2d31ecaf MC |
7980 | } |
7981 | ||
eb07a940 MC |
7982 | static void tg3_setup_rxbd_thresholds(struct tg3 *tp) |
7983 | { | |
7984 | u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh; | |
7985 | ||
63c3a66f JP |
7986 | if (!tg3_flag(tp, 5750_PLUS) || |
7987 | tg3_flag(tp, 5780_CLASS) || | |
eb07a940 MC |
7988 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || |
7989 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) | |
7990 | bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700; | |
7991 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || | |
7992 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) | |
7993 | bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755; | |
7994 | else | |
7995 | bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906; | |
7996 | ||
7997 | nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post); | |
7998 | host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1); | |
7999 | ||
8000 | val = min(nic_rep_thresh, host_rep_thresh); | |
8001 | tw32(RCVBDI_STD_THRESH, val); | |
8002 | ||
63c3a66f | 8003 | if (tg3_flag(tp, 57765_PLUS)) |
eb07a940 MC |
8004 | tw32(STD_REPLENISH_LWM, bdcache_maxcnt); |
8005 | ||
63c3a66f | 8006 | if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS)) |
eb07a940 MC |
8007 | return; |
8008 | ||
63c3a66f | 8009 | if (!tg3_flag(tp, 5705_PLUS)) |
eb07a940 MC |
8010 | bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700; |
8011 | else | |
8012 | bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5717; | |
8013 | ||
8014 | host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1); | |
8015 | ||
8016 | val = min(bdcache_maxcnt / 2, host_rep_thresh); | |
8017 | tw32(RCVBDI_JUMBO_THRESH, val); | |
8018 | ||
63c3a66f | 8019 | if (tg3_flag(tp, 57765_PLUS)) |
eb07a940 MC |
8020 | tw32(JMB_REPLENISH_LWM, bdcache_maxcnt); |
8021 | } | |
8022 | ||
1da177e4 | 8023 | /* tp->lock is held. */ |
8e7a22e3 | 8024 | static int tg3_reset_hw(struct tg3 *tp, int reset_phy) |
1da177e4 LT |
8025 | { |
8026 | u32 val, rdmac_mode; | |
8027 | int i, err, limit; | |
8fea32b9 | 8028 | struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; |
1da177e4 LT |
8029 | |
8030 | tg3_disable_ints(tp); | |
8031 | ||
8032 | tg3_stop_fw(tp); | |
8033 | ||
8034 | tg3_write_sig_pre_reset(tp, RESET_KIND_INIT); | |
8035 | ||
63c3a66f | 8036 | if (tg3_flag(tp, INIT_COMPLETE)) |
e6de8ad1 | 8037 | tg3_abort_hw(tp, 1); |
1da177e4 | 8038 | |
699c0193 MC |
8039 | /* Enable MAC control of LPI */ |
8040 | if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) { | |
8041 | tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, | |
8042 | TG3_CPMU_EEE_LNKIDL_PCIE_NL0 | | |
8043 | TG3_CPMU_EEE_LNKIDL_UART_IDL); | |
8044 | ||
8045 | tw32_f(TG3_CPMU_EEE_CTRL, | |
8046 | TG3_CPMU_EEE_CTRL_EXIT_20_1_US); | |
8047 | ||
a386b901 MC |
8048 | val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET | |
8049 | TG3_CPMU_EEEMD_LPI_IN_TX | | |
8050 | TG3_CPMU_EEEMD_LPI_IN_RX | | |
8051 | TG3_CPMU_EEEMD_EEE_ENABLE; | |
8052 | ||
8053 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) | |
8054 | val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN; | |
8055 | ||
63c3a66f | 8056 | if (tg3_flag(tp, ENABLE_APE)) |
a386b901 MC |
8057 | val |= TG3_CPMU_EEEMD_APE_TX_DET_EN; |
8058 | ||
8059 | tw32_f(TG3_CPMU_EEE_MODE, val); | |
8060 | ||
8061 | tw32_f(TG3_CPMU_EEE_DBTMR1, | |
8062 | TG3_CPMU_DBTMR1_PCIEXIT_2047US | | |
8063 | TG3_CPMU_DBTMR1_LNKIDLE_2047US); | |
8064 | ||
8065 | tw32_f(TG3_CPMU_EEE_DBTMR2, | |
d7f2ab20 | 8066 | TG3_CPMU_DBTMR2_APE_TX_2047US | |
a386b901 | 8067 | TG3_CPMU_DBTMR2_TXIDXEQ_2047US); |
699c0193 MC |
8068 | } |
8069 | ||
603f1173 | 8070 | if (reset_phy) |
d4d2c558 MC |
8071 | tg3_phy_reset(tp); |
8072 | ||
1da177e4 LT |
8073 | err = tg3_chip_reset(tp); |
8074 | if (err) | |
8075 | return err; | |
8076 | ||
8077 | tg3_write_sig_legacy(tp, RESET_KIND_INIT); | |
8078 | ||
bcb37f6c | 8079 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) { |
d30cdd28 MC |
8080 | val = tr32(TG3_CPMU_CTRL); |
8081 | val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE); | |
8082 | tw32(TG3_CPMU_CTRL, val); | |
9acb961e MC |
8083 | |
8084 | val = tr32(TG3_CPMU_LSPD_10MB_CLK); | |
8085 | val &= ~CPMU_LSPD_10MB_MACCLK_MASK; | |
8086 | val |= CPMU_LSPD_10MB_MACCLK_6_25; | |
8087 | tw32(TG3_CPMU_LSPD_10MB_CLK, val); | |
8088 | ||
8089 | val = tr32(TG3_CPMU_LNK_AWARE_PWRMD); | |
8090 | val &= ~CPMU_LNK_AWARE_MACCLK_MASK; | |
8091 | val |= CPMU_LNK_AWARE_MACCLK_6_25; | |
8092 | tw32(TG3_CPMU_LNK_AWARE_PWRMD, val); | |
8093 | ||
8094 | val = tr32(TG3_CPMU_HST_ACC); | |
8095 | val &= ~CPMU_HST_ACC_MACCLK_MASK; | |
8096 | val |= CPMU_HST_ACC_MACCLK_6_25; | |
8097 | tw32(TG3_CPMU_HST_ACC, val); | |
d30cdd28 MC |
8098 | } |
8099 | ||
33466d93 MC |
8100 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { |
8101 | val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK; | |
8102 | val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN | | |
8103 | PCIE_PWR_MGMT_L1_THRESH_4MS; | |
8104 | tw32(PCIE_PWR_MGMT_THRESH, val); | |
521e6b90 MC |
8105 | |
8106 | val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK; | |
8107 | tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS); | |
8108 | ||
8109 | tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR); | |
33466d93 | 8110 | |
f40386c8 MC |
8111 | val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN; |
8112 | tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS); | |
255ca311 MC |
8113 | } |
8114 | ||
63c3a66f | 8115 | if (tg3_flag(tp, L1PLLPD_EN)) { |
614b0590 MC |
8116 | u32 grc_mode = tr32(GRC_MODE); |
8117 | ||
8118 | /* Access the lower 1K of PL PCIE block registers. */ | |
8119 | val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK; | |
8120 | tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL); | |
8121 | ||
8122 | val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1); | |
8123 | tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1, | |
8124 | val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN); | |
8125 | ||
8126 | tw32(GRC_MODE, grc_mode); | |
8127 | } | |
8128 | ||
5093eedc MC |
8129 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) { |
8130 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) { | |
8131 | u32 grc_mode = tr32(GRC_MODE); | |
cea46462 | 8132 | |
5093eedc MC |
8133 | /* Access the lower 1K of PL PCIE block registers. */ |
8134 | val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK; | |
8135 | tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL); | |
cea46462 | 8136 | |
5093eedc MC |
8137 | val = tr32(TG3_PCIE_TLDLPL_PORT + |
8138 | TG3_PCIE_PL_LO_PHYCTL5); | |
8139 | tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5, | |
8140 | val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ); | |
cea46462 | 8141 | |
5093eedc MC |
8142 | tw32(GRC_MODE, grc_mode); |
8143 | } | |
a977dbe8 | 8144 | |
1ff30a59 MC |
8145 | if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_57765_AX) { |
8146 | u32 grc_mode = tr32(GRC_MODE); | |
8147 | ||
8148 | /* Access the lower 1K of DL PCIE block registers. */ | |
8149 | val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK; | |
8150 | tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL); | |
8151 | ||
8152 | val = tr32(TG3_PCIE_TLDLPL_PORT + | |
8153 | TG3_PCIE_DL_LO_FTSMAX); | |
8154 | val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK; | |
8155 | tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX, | |
8156 | val | TG3_PCIE_DL_LO_FTSMAX_VAL); | |
8157 | ||
8158 | tw32(GRC_MODE, grc_mode); | |
8159 | } | |
8160 | ||
a977dbe8 MC |
8161 | val = tr32(TG3_CPMU_LSPD_10MB_CLK); |
8162 | val &= ~CPMU_LSPD_10MB_MACCLK_MASK; | |
8163 | val |= CPMU_LSPD_10MB_MACCLK_6_25; | |
8164 | tw32(TG3_CPMU_LSPD_10MB_CLK, val); | |
cea46462 MC |
8165 | } |
8166 | ||
1da177e4 LT |
8167 | /* This works around an issue with Athlon chipsets on |
8168 | * B3 tigon3 silicon. This bit has no effect on any | |
8169 | * other revision. But do not set this on PCI Express | |
795d01c5 | 8170 | * chips and don't even touch the clocks if the CPMU is present. |
1da177e4 | 8171 | */ |
63c3a66f JP |
8172 | if (!tg3_flag(tp, CPMU_PRESENT)) { |
8173 | if (!tg3_flag(tp, PCI_EXPRESS)) | |
795d01c5 MC |
8174 | tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT; |
8175 | tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); | |
8176 | } | |
1da177e4 LT |
8177 | |
8178 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 && | |
63c3a66f | 8179 | tg3_flag(tp, PCIX_MODE)) { |
1da177e4 LT |
8180 | val = tr32(TG3PCI_PCISTATE); |
8181 | val |= PCISTATE_RETRY_SAME_DMA; | |
8182 | tw32(TG3PCI_PCISTATE, val); | |
8183 | } | |
8184 | ||
63c3a66f | 8185 | if (tg3_flag(tp, ENABLE_APE)) { |
0d3031d9 MC |
8186 | /* Allow reads and writes to the |
8187 | * APE register and memory space. | |
8188 | */ | |
8189 | val = tr32(TG3PCI_PCISTATE); | |
8190 | val |= PCISTATE_ALLOW_APE_CTLSPC_WR | | |
f92d9dc1 MC |
8191 | PCISTATE_ALLOW_APE_SHMEM_WR | |
8192 | PCISTATE_ALLOW_APE_PSPACE_WR; | |
0d3031d9 MC |
8193 | tw32(TG3PCI_PCISTATE, val); |
8194 | } | |
8195 | ||
1da177e4 LT |
8196 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) { |
8197 | /* Enable some hw fixes. */ | |
8198 | val = tr32(TG3PCI_MSI_DATA); | |
8199 | val |= (1 << 26) | (1 << 28) | (1 << 29); | |
8200 | tw32(TG3PCI_MSI_DATA, val); | |
8201 | } | |
8202 | ||
8203 | /* Descriptor ring init may make accesses to the | |
8204 | * NIC SRAM area to setup the TX descriptors, so we | |
8205 | * can only do this after the hardware has been | |
8206 | * successfully reset. | |
8207 | */ | |
32d8c572 MC |
8208 | err = tg3_init_rings(tp); |
8209 | if (err) | |
8210 | return err; | |
1da177e4 | 8211 | |
63c3a66f | 8212 | if (tg3_flag(tp, 57765_PLUS)) { |
cbf9ca6c MC |
8213 | val = tr32(TG3PCI_DMA_RW_CTRL) & |
8214 | ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT; | |
1a319025 MC |
8215 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) |
8216 | val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK; | |
0aebff48 MC |
8217 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 && |
8218 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) | |
8219 | val |= DMA_RWCTRL_TAGGED_STAT_WA; | |
cbf9ca6c MC |
8220 | tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl); |
8221 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 && | |
8222 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) { | |
d30cdd28 MC |
8223 | /* This value is determined during the probe time DMA |
8224 | * engine test, tg3_test_dma. | |
8225 | */ | |
8226 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
8227 | } | |
1da177e4 LT |
8228 | |
8229 | tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS | | |
8230 | GRC_MODE_4X_NIC_SEND_RINGS | | |
8231 | GRC_MODE_NO_TX_PHDR_CSUM | | |
8232 | GRC_MODE_NO_RX_PHDR_CSUM); | |
8233 | tp->grc_mode |= GRC_MODE_HOST_SENDBDS; | |
d2d746f8 MC |
8234 | |
8235 | /* Pseudo-header checksum is done by hardware logic and not | |
8236 | * the offload processers, so make the chip do the pseudo- | |
8237 | * header checksums on receive. For transmit it is more | |
8238 | * convenient to do the pseudo-header checksum in software | |
8239 | * as Linux does that on transmit for us in all cases. | |
8240 | */ | |
8241 | tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM; | |
1da177e4 LT |
8242 | |
8243 | tw32(GRC_MODE, | |
8244 | tp->grc_mode | | |
8245 | (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP)); | |
8246 | ||
8247 | /* Setup the timer prescalar register. Clock is always 66Mhz. */ | |
8248 | val = tr32(GRC_MISC_CFG); | |
8249 | val &= ~0xff; | |
8250 | val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT); | |
8251 | tw32(GRC_MISC_CFG, val); | |
8252 | ||
8253 | /* Initialize MBUF/DESC pool. */ | |
63c3a66f | 8254 | if (tg3_flag(tp, 5750_PLUS)) { |
1da177e4 LT |
8255 | /* Do nothing. */ |
8256 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) { | |
8257 | tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE); | |
8258 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) | |
8259 | tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64); | |
8260 | else | |
8261 | tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96); | |
8262 | tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE); | |
8263 | tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE); | |
63c3a66f | 8264 | } else if (tg3_flag(tp, TSO_CAPABLE)) { |
1da177e4 LT |
8265 | int fw_len; |
8266 | ||
077f849d | 8267 | fw_len = tp->fw_len; |
1da177e4 LT |
8268 | fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1); |
8269 | tw32(BUFMGR_MB_POOL_ADDR, | |
8270 | NIC_SRAM_MBUF_POOL_BASE5705 + fw_len); | |
8271 | tw32(BUFMGR_MB_POOL_SIZE, | |
8272 | NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00); | |
8273 | } | |
1da177e4 | 8274 | |
0f893dc6 | 8275 | if (tp->dev->mtu <= ETH_DATA_LEN) { |
1da177e4 LT |
8276 | tw32(BUFMGR_MB_RDMA_LOW_WATER, |
8277 | tp->bufmgr_config.mbuf_read_dma_low_water); | |
8278 | tw32(BUFMGR_MB_MACRX_LOW_WATER, | |
8279 | tp->bufmgr_config.mbuf_mac_rx_low_water); | |
8280 | tw32(BUFMGR_MB_HIGH_WATER, | |
8281 | tp->bufmgr_config.mbuf_high_water); | |
8282 | } else { | |
8283 | tw32(BUFMGR_MB_RDMA_LOW_WATER, | |
8284 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo); | |
8285 | tw32(BUFMGR_MB_MACRX_LOW_WATER, | |
8286 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo); | |
8287 | tw32(BUFMGR_MB_HIGH_WATER, | |
8288 | tp->bufmgr_config.mbuf_high_water_jumbo); | |
8289 | } | |
8290 | tw32(BUFMGR_DMA_LOW_WATER, | |
8291 | tp->bufmgr_config.dma_low_water); | |
8292 | tw32(BUFMGR_DMA_HIGH_WATER, | |
8293 | tp->bufmgr_config.dma_high_water); | |
8294 | ||
d309a46e MC |
8295 | val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE; |
8296 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | |
8297 | val |= BUFMGR_MODE_NO_TX_UNDERRUN; | |
4d958473 MC |
8298 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
8299 | tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 || | |
8300 | tp->pci_chip_rev_id == CHIPREV_ID_5720_A0) | |
8301 | val |= BUFMGR_MODE_MBLOW_ATTN_ENAB; | |
d309a46e | 8302 | tw32(BUFMGR_MODE, val); |
1da177e4 LT |
8303 | for (i = 0; i < 2000; i++) { |
8304 | if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE) | |
8305 | break; | |
8306 | udelay(10); | |
8307 | } | |
8308 | if (i >= 2000) { | |
05dbe005 | 8309 | netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__); |
1da177e4 LT |
8310 | return -ENODEV; |
8311 | } | |
8312 | ||
eb07a940 MC |
8313 | if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1) |
8314 | tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2); | |
b5d3772c | 8315 | |
eb07a940 | 8316 | tg3_setup_rxbd_thresholds(tp); |
1da177e4 LT |
8317 | |
8318 | /* Initialize TG3_BDINFO's at: | |
8319 | * RCVDBDI_STD_BD: standard eth size rx ring | |
8320 | * RCVDBDI_JUMBO_BD: jumbo frame rx ring | |
8321 | * RCVDBDI_MINI_BD: small frame rx ring (??? does not work) | |
8322 | * | |
8323 | * like so: | |
8324 | * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring | |
8325 | * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) | | |
8326 | * ring attribute flags | |
8327 | * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM | |
8328 | * | |
8329 | * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries. | |
8330 | * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries. | |
8331 | * | |
8332 | * The size of each ring is fixed in the firmware, but the location is | |
8333 | * configurable. | |
8334 | */ | |
8335 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, | |
21f581a5 | 8336 | ((u64) tpr->rx_std_mapping >> 32)); |
1da177e4 | 8337 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, |
21f581a5 | 8338 | ((u64) tpr->rx_std_mapping & 0xffffffff)); |
63c3a66f | 8339 | if (!tg3_flag(tp, 5717_PLUS)) |
87668d35 MC |
8340 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR, |
8341 | NIC_SRAM_RX_BUFFER_DESC); | |
1da177e4 | 8342 | |
fdb72b38 | 8343 | /* Disable the mini ring */ |
63c3a66f | 8344 | if (!tg3_flag(tp, 5705_PLUS)) |
1da177e4 LT |
8345 | tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS, |
8346 | BDINFO_FLAGS_DISABLED); | |
8347 | ||
fdb72b38 MC |
8348 | /* Program the jumbo buffer descriptor ring control |
8349 | * blocks on those devices that have them. | |
8350 | */ | |
bb18bb94 | 8351 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
63c3a66f | 8352 | (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) { |
1da177e4 | 8353 | |
63c3a66f | 8354 | if (tg3_flag(tp, JUMBO_RING_ENABLE)) { |
1da177e4 | 8355 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, |
21f581a5 | 8356 | ((u64) tpr->rx_jmb_mapping >> 32)); |
1da177e4 | 8357 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, |
21f581a5 | 8358 | ((u64) tpr->rx_jmb_mapping & 0xffffffff)); |
de9f5230 MC |
8359 | val = TG3_RX_JMB_RING_SIZE(tp) << |
8360 | BDINFO_FLAGS_MAXLEN_SHIFT; | |
1da177e4 | 8361 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS, |
de9f5230 | 8362 | val | BDINFO_FLAGS_USE_EXT_RECV); |
63c3a66f | 8363 | if (!tg3_flag(tp, USE_JUMBO_BDFLAG) || |
a50d0796 | 8364 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) |
87668d35 MC |
8365 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR, |
8366 | NIC_SRAM_RX_JUMBO_BUFFER_DESC); | |
1da177e4 LT |
8367 | } else { |
8368 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS, | |
8369 | BDINFO_FLAGS_DISABLED); | |
8370 | } | |
8371 | ||
63c3a66f | 8372 | if (tg3_flag(tp, 57765_PLUS)) { |
7cb32cf2 | 8373 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) |
de9f5230 | 8374 | val = TG3_RX_STD_MAX_SIZE_5700; |
7cb32cf2 | 8375 | else |
de9f5230 | 8376 | val = TG3_RX_STD_MAX_SIZE_5717; |
7cb32cf2 MC |
8377 | val <<= BDINFO_FLAGS_MAXLEN_SHIFT; |
8378 | val |= (TG3_RX_STD_DMA_SZ << 2); | |
8379 | } else | |
04380d40 | 8380 | val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT; |
fdb72b38 | 8381 | } else |
de9f5230 | 8382 | val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT; |
fdb72b38 MC |
8383 | |
8384 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val); | |
1da177e4 | 8385 | |
411da640 | 8386 | tpr->rx_std_prod_idx = tp->rx_pending; |
66711e66 | 8387 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx); |
1da177e4 | 8388 | |
63c3a66f JP |
8389 | tpr->rx_jmb_prod_idx = |
8390 | tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0; | |
66711e66 | 8391 | tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx); |
1da177e4 | 8392 | |
2d31ecaf MC |
8393 | tg3_rings_reset(tp); |
8394 | ||
1da177e4 | 8395 | /* Initialize MAC address and backoff seed. */ |
986e0aeb | 8396 | __tg3_set_mac_addr(tp, 0); |
1da177e4 LT |
8397 | |
8398 | /* MTU + ethernet header + FCS + optional VLAN tag */ | |
f7b493e0 MC |
8399 | tw32(MAC_RX_MTU_SIZE, |
8400 | tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN); | |
1da177e4 LT |
8401 | |
8402 | /* The slot time is changed by tg3_setup_phy if we | |
8403 | * run at gigabit with half duplex. | |
8404 | */ | |
f2096f94 MC |
8405 | val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) | |
8406 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
8407 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT); | |
8408 | ||
8409 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
8410 | val |= tr32(MAC_TX_LENGTHS) & | |
8411 | (TX_LENGTHS_JMB_FRM_LEN_MSK | | |
8412 | TX_LENGTHS_CNT_DWN_VAL_MSK); | |
8413 | ||
8414 | tw32(MAC_TX_LENGTHS, val); | |
1da177e4 LT |
8415 | |
8416 | /* Receive rules. */ | |
8417 | tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS); | |
8418 | tw32(RCVLPC_CONFIG, 0x0181); | |
8419 | ||
8420 | /* Calculate RDMAC_MODE setting early, we need it to determine | |
8421 | * the RCVLPC_STATE_ENABLE mask. | |
8422 | */ | |
8423 | rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB | | |
8424 | RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB | | |
8425 | RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB | | |
8426 | RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB | | |
8427 | RDMAC_MODE_LNGREAD_ENAB); | |
85e94ced | 8428 | |
deabaac8 | 8429 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) |
0339e4e3 MC |
8430 | rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS; |
8431 | ||
57e6983c | 8432 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
321d32a0 MC |
8433 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
8434 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
d30cdd28 MC |
8435 | rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB | |
8436 | RDMAC_MODE_MBUF_RBD_CRPT_ENAB | | |
8437 | RDMAC_MODE_MBUF_SBD_CRPT_ENAB; | |
8438 | ||
c5908939 MC |
8439 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && |
8440 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { | |
63c3a66f | 8441 | if (tg3_flag(tp, TSO_CAPABLE) && |
c13e3713 | 8442 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { |
1da177e4 LT |
8443 | rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128; |
8444 | } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && | |
63c3a66f | 8445 | !tg3_flag(tp, IS_5788)) { |
1da177e4 LT |
8446 | rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST; |
8447 | } | |
8448 | } | |
8449 | ||
63c3a66f | 8450 | if (tg3_flag(tp, PCI_EXPRESS)) |
85e94ced MC |
8451 | rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST; |
8452 | ||
63c3a66f JP |
8453 | if (tg3_flag(tp, HW_TSO_1) || |
8454 | tg3_flag(tp, HW_TSO_2) || | |
8455 | tg3_flag(tp, HW_TSO_3)) | |
027455ad MC |
8456 | rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN; |
8457 | ||
108a6c16 | 8458 | if (tg3_flag(tp, 57765_PLUS) || |
e849cdc3 | 8459 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
027455ad MC |
8460 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) |
8461 | rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN; | |
1da177e4 | 8462 | |
f2096f94 MC |
8463 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) |
8464 | rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET; | |
8465 | ||
41a8a7ee MC |
8466 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
8467 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || | |
8468 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || | |
8469 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || | |
63c3a66f | 8470 | tg3_flag(tp, 57765_PLUS)) { |
41a8a7ee | 8471 | val = tr32(TG3_RDMA_RSRVCTRL_REG); |
d78b59f5 MC |
8472 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
8473 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
b4495ed8 MC |
8474 | val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK | |
8475 | TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK | | |
8476 | TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK); | |
8477 | val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B | | |
8478 | TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K | | |
8479 | TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K; | |
b75cc0e4 | 8480 | } |
41a8a7ee MC |
8481 | tw32(TG3_RDMA_RSRVCTRL_REG, |
8482 | val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX); | |
8483 | } | |
8484 | ||
d78b59f5 MC |
8485 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
8486 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
d309a46e MC |
8487 | val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL); |
8488 | tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val | | |
8489 | TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K | | |
8490 | TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K); | |
8491 | } | |
8492 | ||
1da177e4 | 8493 | /* Receive/send statistics. */ |
63c3a66f | 8494 | if (tg3_flag(tp, 5750_PLUS)) { |
1661394e MC |
8495 | val = tr32(RCVLPC_STATS_ENABLE); |
8496 | val &= ~RCVLPC_STATSENAB_DACK_FIX; | |
8497 | tw32(RCVLPC_STATS_ENABLE, val); | |
8498 | } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) && | |
63c3a66f | 8499 | tg3_flag(tp, TSO_CAPABLE)) { |
1da177e4 LT |
8500 | val = tr32(RCVLPC_STATS_ENABLE); |
8501 | val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX; | |
8502 | tw32(RCVLPC_STATS_ENABLE, val); | |
8503 | } else { | |
8504 | tw32(RCVLPC_STATS_ENABLE, 0xffffff); | |
8505 | } | |
8506 | tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE); | |
8507 | tw32(SNDDATAI_STATSENAB, 0xffffff); | |
8508 | tw32(SNDDATAI_STATSCTRL, | |
8509 | (SNDDATAI_SCTRL_ENABLE | | |
8510 | SNDDATAI_SCTRL_FASTUPD)); | |
8511 | ||
8512 | /* Setup host coalescing engine. */ | |
8513 | tw32(HOSTCC_MODE, 0); | |
8514 | for (i = 0; i < 2000; i++) { | |
8515 | if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE)) | |
8516 | break; | |
8517 | udelay(10); | |
8518 | } | |
8519 | ||
d244c892 | 8520 | __tg3_set_coalesce(tp, &tp->coal); |
1da177e4 | 8521 | |
63c3a66f | 8522 | if (!tg3_flag(tp, 5705_PLUS)) { |
1da177e4 LT |
8523 | /* Status/statistics block address. See tg3_timer, |
8524 | * the tg3_periodic_fetch_stats call there, and | |
8525 | * tg3_get_stats to see how this works for 5705/5750 chips. | |
8526 | */ | |
1da177e4 LT |
8527 | tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, |
8528 | ((u64) tp->stats_mapping >> 32)); | |
8529 | tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, | |
8530 | ((u64) tp->stats_mapping & 0xffffffff)); | |
8531 | tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK); | |
2d31ecaf | 8532 | |
1da177e4 | 8533 | tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK); |
2d31ecaf MC |
8534 | |
8535 | /* Clear statistics and status block memory areas */ | |
8536 | for (i = NIC_SRAM_STATS_BLK; | |
8537 | i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE; | |
8538 | i += sizeof(u32)) { | |
8539 | tg3_write_mem(tp, i, 0); | |
8540 | udelay(40); | |
8541 | } | |
1da177e4 LT |
8542 | } |
8543 | ||
8544 | tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode); | |
8545 | ||
8546 | tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE); | |
8547 | tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE); | |
63c3a66f | 8548 | if (!tg3_flag(tp, 5705_PLUS)) |
1da177e4 LT |
8549 | tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE); |
8550 | ||
f07e9af3 MC |
8551 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { |
8552 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; | |
c94e3941 MC |
8553 | /* reset to prevent losing 1st rx packet intermittently */ |
8554 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); | |
8555 | udelay(10); | |
8556 | } | |
8557 | ||
3bda1258 | 8558 | tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE | |
9e975cc2 MC |
8559 | MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | |
8560 | MAC_MODE_FHDE_ENABLE; | |
8561 | if (tg3_flag(tp, ENABLE_APE)) | |
8562 | tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; | |
63c3a66f | 8563 | if (!tg3_flag(tp, 5705_PLUS) && |
f07e9af3 | 8564 | !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
e8f3f6ca MC |
8565 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) |
8566 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; | |
1da177e4 LT |
8567 | tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR); |
8568 | udelay(40); | |
8569 | ||
314fba34 | 8570 | /* tp->grc_local_ctrl is partially set up during tg3_get_invariants(). |
63c3a66f | 8571 | * If TG3_FLAG_IS_NIC is zero, we should read the |
314fba34 MC |
8572 | * register to preserve the GPIO settings for LOMs. The GPIOs, |
8573 | * whether used as inputs or outputs, are set by boot code after | |
8574 | * reset. | |
8575 | */ | |
63c3a66f | 8576 | if (!tg3_flag(tp, IS_NIC)) { |
314fba34 MC |
8577 | u32 gpio_mask; |
8578 | ||
9d26e213 MC |
8579 | gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 | |
8580 | GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
8581 | GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2; | |
3e7d83bc MC |
8582 | |
8583 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) | |
8584 | gpio_mask |= GRC_LCLCTRL_GPIO_OE3 | | |
8585 | GRC_LCLCTRL_GPIO_OUTPUT3; | |
8586 | ||
af36e6b6 MC |
8587 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) |
8588 | gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL; | |
8589 | ||
aaf84465 | 8590 | tp->grc_local_ctrl &= ~gpio_mask; |
314fba34 MC |
8591 | tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask; |
8592 | ||
8593 | /* GPIO1 must be driven high for eeprom write protect */ | |
63c3a66f | 8594 | if (tg3_flag(tp, EEPROM_WRITE_PROT)) |
9d26e213 MC |
8595 | tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | |
8596 | GRC_LCLCTRL_GPIO_OUTPUT1); | |
314fba34 | 8597 | } |
1da177e4 LT |
8598 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); |
8599 | udelay(100); | |
8600 | ||
63c3a66f | 8601 | if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1) { |
baf8a94a MC |
8602 | val = tr32(MSGINT_MODE); |
8603 | val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE; | |
8604 | tw32(MSGINT_MODE, val); | |
8605 | } | |
8606 | ||
63c3a66f | 8607 | if (!tg3_flag(tp, 5705_PLUS)) { |
1da177e4 LT |
8608 | tw32_f(DMAC_MODE, DMAC_MODE_ENABLE); |
8609 | udelay(40); | |
8610 | } | |
8611 | ||
8612 | val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB | | |
8613 | WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB | | |
8614 | WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB | | |
8615 | WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB | | |
8616 | WDMAC_MODE_LNGREAD_ENAB); | |
8617 | ||
c5908939 MC |
8618 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && |
8619 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { | |
63c3a66f | 8620 | if (tg3_flag(tp, TSO_CAPABLE) && |
1da177e4 LT |
8621 | (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 || |
8622 | tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) { | |
8623 | /* nothing */ | |
8624 | } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && | |
63c3a66f | 8625 | !tg3_flag(tp, IS_5788)) { |
1da177e4 LT |
8626 | val |= WDMAC_MODE_RX_ACCEL; |
8627 | } | |
8628 | } | |
8629 | ||
d9ab5ad1 | 8630 | /* Enable host coalescing bug fix */ |
63c3a66f | 8631 | if (tg3_flag(tp, 5755_PLUS)) |
f51f3562 | 8632 | val |= WDMAC_MODE_STATUS_TAG_FIX; |
d9ab5ad1 | 8633 | |
788a035e MC |
8634 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) |
8635 | val |= WDMAC_MODE_BURST_ALL_DATA; | |
8636 | ||
1da177e4 LT |
8637 | tw32_f(WDMAC_MODE, val); |
8638 | udelay(40); | |
8639 | ||
63c3a66f | 8640 | if (tg3_flag(tp, PCIX_MODE)) { |
9974a356 MC |
8641 | u16 pcix_cmd; |
8642 | ||
8643 | pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
8644 | &pcix_cmd); | |
1da177e4 | 8645 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) { |
9974a356 MC |
8646 | pcix_cmd &= ~PCI_X_CMD_MAX_READ; |
8647 | pcix_cmd |= PCI_X_CMD_READ_2K; | |
1da177e4 | 8648 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { |
9974a356 MC |
8649 | pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ); |
8650 | pcix_cmd |= PCI_X_CMD_READ_2K; | |
1da177e4 | 8651 | } |
9974a356 MC |
8652 | pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, |
8653 | pcix_cmd); | |
1da177e4 LT |
8654 | } |
8655 | ||
8656 | tw32_f(RDMAC_MODE, rdmac_mode); | |
8657 | udelay(40); | |
8658 | ||
8659 | tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE); | |
63c3a66f | 8660 | if (!tg3_flag(tp, 5705_PLUS)) |
1da177e4 | 8661 | tw32(MBFREE_MODE, MBFREE_MODE_ENABLE); |
9936bcf6 MC |
8662 | |
8663 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | |
8664 | tw32(SNDDATAC_MODE, | |
8665 | SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY); | |
8666 | else | |
8667 | tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE); | |
8668 | ||
1da177e4 LT |
8669 | tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE); |
8670 | tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB); | |
7cb32cf2 | 8671 | val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ; |
63c3a66f | 8672 | if (tg3_flag(tp, LRG_PROD_RING_CAP)) |
7cb32cf2 MC |
8673 | val |= RCVDBDI_MODE_LRG_RING_SZ; |
8674 | tw32(RCVDBDI_MODE, val); | |
1da177e4 | 8675 | tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE); |
63c3a66f JP |
8676 | if (tg3_flag(tp, HW_TSO_1) || |
8677 | tg3_flag(tp, HW_TSO_2) || | |
8678 | tg3_flag(tp, HW_TSO_3)) | |
1da177e4 | 8679 | tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8); |
baf8a94a | 8680 | val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE; |
63c3a66f | 8681 | if (tg3_flag(tp, ENABLE_TSS)) |
baf8a94a MC |
8682 | val |= SNDBDI_MODE_MULTI_TXQ_EN; |
8683 | tw32(SNDBDI_MODE, val); | |
1da177e4 LT |
8684 | tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE); |
8685 | ||
8686 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) { | |
8687 | err = tg3_load_5701_a0_firmware_fix(tp); | |
8688 | if (err) | |
8689 | return err; | |
8690 | } | |
8691 | ||
63c3a66f | 8692 | if (tg3_flag(tp, TSO_CAPABLE)) { |
1da177e4 LT |
8693 | err = tg3_load_tso_firmware(tp); |
8694 | if (err) | |
8695 | return err; | |
8696 | } | |
1da177e4 LT |
8697 | |
8698 | tp->tx_mode = TX_MODE_ENABLE; | |
f2096f94 | 8699 | |
63c3a66f | 8700 | if (tg3_flag(tp, 5755_PLUS) || |
b1d05210 MC |
8701 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
8702 | tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX; | |
f2096f94 MC |
8703 | |
8704 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
8705 | val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE; | |
8706 | tp->tx_mode &= ~val; | |
8707 | tp->tx_mode |= tr32(MAC_TX_MODE) & val; | |
8708 | } | |
8709 | ||
1da177e4 LT |
8710 | tw32_f(MAC_TX_MODE, tp->tx_mode); |
8711 | udelay(100); | |
8712 | ||
63c3a66f | 8713 | if (tg3_flag(tp, ENABLE_RSS)) { |
baf8a94a MC |
8714 | u32 reg = MAC_RSS_INDIR_TBL_0; |
8715 | u8 *ent = (u8 *)&val; | |
8716 | ||
8717 | /* Setup the indirection table */ | |
8718 | for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) { | |
8719 | int idx = i % sizeof(val); | |
8720 | ||
5efeeea1 | 8721 | ent[idx] = i % (tp->irq_cnt - 1); |
baf8a94a MC |
8722 | if (idx == sizeof(val) - 1) { |
8723 | tw32(reg, val); | |
8724 | reg += 4; | |
8725 | } | |
8726 | } | |
8727 | ||
8728 | /* Setup the "secret" hash key. */ | |
8729 | tw32(MAC_RSS_HASH_KEY_0, 0x5f865437); | |
8730 | tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc); | |
8731 | tw32(MAC_RSS_HASH_KEY_2, 0x50103a45); | |
8732 | tw32(MAC_RSS_HASH_KEY_3, 0x36621985); | |
8733 | tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8); | |
8734 | tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e); | |
8735 | tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556); | |
8736 | tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe); | |
8737 | tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7); | |
8738 | tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481); | |
8739 | } | |
8740 | ||
1da177e4 | 8741 | tp->rx_mode = RX_MODE_ENABLE; |
63c3a66f | 8742 | if (tg3_flag(tp, 5755_PLUS)) |
af36e6b6 MC |
8743 | tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE; |
8744 | ||
63c3a66f | 8745 | if (tg3_flag(tp, ENABLE_RSS)) |
baf8a94a MC |
8746 | tp->rx_mode |= RX_MODE_RSS_ENABLE | |
8747 | RX_MODE_RSS_ITBL_HASH_BITS_7 | | |
8748 | RX_MODE_RSS_IPV6_HASH_EN | | |
8749 | RX_MODE_RSS_TCP_IPV6_HASH_EN | | |
8750 | RX_MODE_RSS_IPV4_HASH_EN | | |
8751 | RX_MODE_RSS_TCP_IPV4_HASH_EN; | |
8752 | ||
1da177e4 LT |
8753 | tw32_f(MAC_RX_MODE, tp->rx_mode); |
8754 | udelay(10); | |
8755 | ||
1da177e4 LT |
8756 | tw32(MAC_LED_CTRL, tp->led_ctrl); |
8757 | ||
8758 | tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
f07e9af3 | 8759 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
1da177e4 LT |
8760 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); |
8761 | udelay(10); | |
8762 | } | |
8763 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
8764 | udelay(10); | |
8765 | ||
f07e9af3 | 8766 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
1da177e4 | 8767 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) && |
f07e9af3 | 8768 | !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) { |
1da177e4 LT |
8769 | /* Set drive transmission level to 1.2V */ |
8770 | /* only if the signal pre-emphasis bit is not set */ | |
8771 | val = tr32(MAC_SERDES_CFG); | |
8772 | val &= 0xfffff000; | |
8773 | val |= 0x880; | |
8774 | tw32(MAC_SERDES_CFG, val); | |
8775 | } | |
8776 | if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) | |
8777 | tw32(MAC_SERDES_CFG, 0x616000); | |
8778 | } | |
8779 | ||
8780 | /* Prevent chip from dropping frames when flow control | |
8781 | * is enabled. | |
8782 | */ | |
666bc831 MC |
8783 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) |
8784 | val = 1; | |
8785 | else | |
8786 | val = 2; | |
8787 | tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val); | |
1da177e4 LT |
8788 | |
8789 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 && | |
f07e9af3 | 8790 | (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { |
1da177e4 | 8791 | /* Use hardware link auto-negotiation */ |
63c3a66f | 8792 | tg3_flag_set(tp, HW_AUTONEG); |
1da177e4 LT |
8793 | } |
8794 | ||
f07e9af3 | 8795 | if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && |
6ff6f81d | 8796 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { |
d4d2c558 MC |
8797 | u32 tmp; |
8798 | ||
8799 | tmp = tr32(SERDES_RX_CTRL); | |
8800 | tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT); | |
8801 | tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT; | |
8802 | tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT; | |
8803 | tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl); | |
8804 | } | |
8805 | ||
63c3a66f | 8806 | if (!tg3_flag(tp, USE_PHYLIB)) { |
80096068 MC |
8807 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { |
8808 | tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; | |
dd477003 MC |
8809 | tp->link_config.speed = tp->link_config.orig_speed; |
8810 | tp->link_config.duplex = tp->link_config.orig_duplex; | |
8811 | tp->link_config.autoneg = tp->link_config.orig_autoneg; | |
8812 | } | |
1da177e4 | 8813 | |
dd477003 MC |
8814 | err = tg3_setup_phy(tp, 0); |
8815 | if (err) | |
8816 | return err; | |
1da177e4 | 8817 | |
f07e9af3 MC |
8818 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
8819 | !(tp->phy_flags & TG3_PHYFLG_IS_FET)) { | |
dd477003 MC |
8820 | u32 tmp; |
8821 | ||
8822 | /* Clear CRC stats. */ | |
8823 | if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) { | |
8824 | tg3_writephy(tp, MII_TG3_TEST1, | |
8825 | tmp | MII_TG3_TEST1_CRC_EN); | |
f08aa1a8 | 8826 | tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp); |
dd477003 | 8827 | } |
1da177e4 LT |
8828 | } |
8829 | } | |
8830 | ||
8831 | __tg3_set_rx_mode(tp->dev); | |
8832 | ||
8833 | /* Initialize receive rules. */ | |
8834 | tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK); | |
8835 | tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK); | |
8836 | tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK); | |
8837 | tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK); | |
8838 | ||
63c3a66f | 8839 | if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) |
1da177e4 LT |
8840 | limit = 8; |
8841 | else | |
8842 | limit = 16; | |
63c3a66f | 8843 | if (tg3_flag(tp, ENABLE_ASF)) |
1da177e4 LT |
8844 | limit -= 4; |
8845 | switch (limit) { | |
8846 | case 16: | |
8847 | tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0); | |
8848 | case 15: | |
8849 | tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0); | |
8850 | case 14: | |
8851 | tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0); | |
8852 | case 13: | |
8853 | tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0); | |
8854 | case 12: | |
8855 | tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0); | |
8856 | case 11: | |
8857 | tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0); | |
8858 | case 10: | |
8859 | tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0); | |
8860 | case 9: | |
8861 | tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0); | |
8862 | case 8: | |
8863 | tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0); | |
8864 | case 7: | |
8865 | tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0); | |
8866 | case 6: | |
8867 | tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0); | |
8868 | case 5: | |
8869 | tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0); | |
8870 | case 4: | |
8871 | /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */ | |
8872 | case 3: | |
8873 | /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */ | |
8874 | case 2: | |
8875 | case 1: | |
8876 | ||
8877 | default: | |
8878 | break; | |
855e1111 | 8879 | } |
1da177e4 | 8880 | |
63c3a66f | 8881 | if (tg3_flag(tp, ENABLE_APE)) |
9ce768ea MC |
8882 | /* Write our heartbeat update interval to APE. */ |
8883 | tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS, | |
8884 | APE_HOST_HEARTBEAT_INT_DISABLE); | |
0d3031d9 | 8885 | |
1da177e4 LT |
8886 | tg3_write_sig_post_reset(tp, RESET_KIND_INIT); |
8887 | ||
1da177e4 LT |
8888 | return 0; |
8889 | } | |
8890 | ||
8891 | /* Called at device open time to get the chip ready for | |
8892 | * packet processing. Invoked with tp->lock held. | |
8893 | */ | |
8e7a22e3 | 8894 | static int tg3_init_hw(struct tg3 *tp, int reset_phy) |
1da177e4 | 8895 | { |
1da177e4 LT |
8896 | tg3_switch_clocks(tp); |
8897 | ||
8898 | tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
8899 | ||
2f751b67 | 8900 | return tg3_reset_hw(tp, reset_phy); |
1da177e4 LT |
8901 | } |
8902 | ||
8903 | #define TG3_STAT_ADD32(PSTAT, REG) \ | |
8904 | do { u32 __val = tr32(REG); \ | |
8905 | (PSTAT)->low += __val; \ | |
8906 | if ((PSTAT)->low < __val) \ | |
8907 | (PSTAT)->high += 1; \ | |
8908 | } while (0) | |
8909 | ||
8910 | static void tg3_periodic_fetch_stats(struct tg3 *tp) | |
8911 | { | |
8912 | struct tg3_hw_stats *sp = tp->hw_stats; | |
8913 | ||
8914 | if (!netif_carrier_ok(tp->dev)) | |
8915 | return; | |
8916 | ||
8917 | TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS); | |
8918 | TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS); | |
8919 | TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT); | |
8920 | TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT); | |
8921 | TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS); | |
8922 | TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS); | |
8923 | TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS); | |
8924 | TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED); | |
8925 | TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL); | |
8926 | TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL); | |
8927 | TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST); | |
8928 | TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST); | |
8929 | TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST); | |
8930 | ||
8931 | TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS); | |
8932 | TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS); | |
8933 | TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST); | |
8934 | TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST); | |
8935 | TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST); | |
8936 | TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS); | |
8937 | TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS); | |
8938 | TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD); | |
8939 | TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD); | |
8940 | TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD); | |
8941 | TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED); | |
8942 | TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG); | |
8943 | TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS); | |
8944 | TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE); | |
463d305b MC |
8945 | |
8946 | TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT); | |
310050fa MC |
8947 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 && |
8948 | tp->pci_chip_rev_id != CHIPREV_ID_5719_A0 && | |
8949 | tp->pci_chip_rev_id != CHIPREV_ID_5720_A0) { | |
4d958473 MC |
8950 | TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT); |
8951 | } else { | |
8952 | u32 val = tr32(HOSTCC_FLOW_ATTN); | |
8953 | val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0; | |
8954 | if (val) { | |
8955 | tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM); | |
8956 | sp->rx_discards.low += val; | |
8957 | if (sp->rx_discards.low < val) | |
8958 | sp->rx_discards.high += 1; | |
8959 | } | |
8960 | sp->mbuf_lwm_thresh_hit = sp->rx_discards; | |
8961 | } | |
463d305b | 8962 | TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT); |
1da177e4 LT |
8963 | } |
8964 | ||
0e6cf6a9 MC |
8965 | static void tg3_chk_missed_msi(struct tg3 *tp) |
8966 | { | |
8967 | u32 i; | |
8968 | ||
8969 | for (i = 0; i < tp->irq_cnt; i++) { | |
8970 | struct tg3_napi *tnapi = &tp->napi[i]; | |
8971 | ||
8972 | if (tg3_has_work(tnapi)) { | |
8973 | if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr && | |
8974 | tnapi->last_tx_cons == tnapi->tx_cons) { | |
8975 | if (tnapi->chk_msi_cnt < 1) { | |
8976 | tnapi->chk_msi_cnt++; | |
8977 | return; | |
8978 | } | |
8979 | tw32_mailbox(tnapi->int_mbox, | |
8980 | tnapi->last_tag << 24); | |
8981 | } | |
8982 | } | |
8983 | tnapi->chk_msi_cnt = 0; | |
8984 | tnapi->last_rx_cons = tnapi->rx_rcb_ptr; | |
8985 | tnapi->last_tx_cons = tnapi->tx_cons; | |
8986 | } | |
8987 | } | |
8988 | ||
1da177e4 LT |
8989 | static void tg3_timer(unsigned long __opaque) |
8990 | { | |
8991 | struct tg3 *tp = (struct tg3 *) __opaque; | |
1da177e4 | 8992 | |
f475f163 MC |
8993 | if (tp->irq_sync) |
8994 | goto restart_timer; | |
8995 | ||
f47c11ee | 8996 | spin_lock(&tp->lock); |
1da177e4 | 8997 | |
0e6cf6a9 MC |
8998 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
8999 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
9000 | tg3_chk_missed_msi(tp); | |
9001 | ||
63c3a66f | 9002 | if (!tg3_flag(tp, TAGGED_STATUS)) { |
fac9b83e DM |
9003 | /* All of this garbage is because when using non-tagged |
9004 | * IRQ status the mailbox/status_block protocol the chip | |
9005 | * uses with the cpu is race prone. | |
9006 | */ | |
898a56f8 | 9007 | if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) { |
fac9b83e DM |
9008 | tw32(GRC_LOCAL_CTRL, |
9009 | tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); | |
9010 | } else { | |
9011 | tw32(HOSTCC_MODE, tp->coalesce_mode | | |
fd2ce37f | 9012 | HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW); |
fac9b83e | 9013 | } |
1da177e4 | 9014 | |
fac9b83e | 9015 | if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { |
63c3a66f | 9016 | tg3_flag_set(tp, RESTART_TIMER); |
f47c11ee | 9017 | spin_unlock(&tp->lock); |
fac9b83e DM |
9018 | schedule_work(&tp->reset_task); |
9019 | return; | |
9020 | } | |
1da177e4 LT |
9021 | } |
9022 | ||
1da177e4 LT |
9023 | /* This part only runs once per second. */ |
9024 | if (!--tp->timer_counter) { | |
63c3a66f | 9025 | if (tg3_flag(tp, 5705_PLUS)) |
fac9b83e DM |
9026 | tg3_periodic_fetch_stats(tp); |
9027 | ||
b0c5943f MC |
9028 | if (tp->setlpicnt && !--tp->setlpicnt) |
9029 | tg3_phy_eee_enable(tp); | |
52b02d04 | 9030 | |
63c3a66f | 9031 | if (tg3_flag(tp, USE_LINKCHG_REG)) { |
1da177e4 LT |
9032 | u32 mac_stat; |
9033 | int phy_event; | |
9034 | ||
9035 | mac_stat = tr32(MAC_STATUS); | |
9036 | ||
9037 | phy_event = 0; | |
f07e9af3 | 9038 | if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) { |
1da177e4 LT |
9039 | if (mac_stat & MAC_STATUS_MI_INTERRUPT) |
9040 | phy_event = 1; | |
9041 | } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED) | |
9042 | phy_event = 1; | |
9043 | ||
9044 | if (phy_event) | |
9045 | tg3_setup_phy(tp, 0); | |
63c3a66f | 9046 | } else if (tg3_flag(tp, POLL_SERDES)) { |
1da177e4 LT |
9047 | u32 mac_stat = tr32(MAC_STATUS); |
9048 | int need_setup = 0; | |
9049 | ||
9050 | if (netif_carrier_ok(tp->dev) && | |
9051 | (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) { | |
9052 | need_setup = 1; | |
9053 | } | |
be98da6a | 9054 | if (!netif_carrier_ok(tp->dev) && |
1da177e4 LT |
9055 | (mac_stat & (MAC_STATUS_PCS_SYNCED | |
9056 | MAC_STATUS_SIGNAL_DET))) { | |
9057 | need_setup = 1; | |
9058 | } | |
9059 | if (need_setup) { | |
3d3ebe74 MC |
9060 | if (!tp->serdes_counter) { |
9061 | tw32_f(MAC_MODE, | |
9062 | (tp->mac_mode & | |
9063 | ~MAC_MODE_PORT_MODE_MASK)); | |
9064 | udelay(40); | |
9065 | tw32_f(MAC_MODE, tp->mac_mode); | |
9066 | udelay(40); | |
9067 | } | |
1da177e4 LT |
9068 | tg3_setup_phy(tp, 0); |
9069 | } | |
f07e9af3 | 9070 | } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && |
63c3a66f | 9071 | tg3_flag(tp, 5780_CLASS)) { |
747e8f8b | 9072 | tg3_serdes_parallel_detect(tp); |
57d8b880 | 9073 | } |
1da177e4 LT |
9074 | |
9075 | tp->timer_counter = tp->timer_multiplier; | |
9076 | } | |
9077 | ||
130b8e4d MC |
9078 | /* Heartbeat is only sent once every 2 seconds. |
9079 | * | |
9080 | * The heartbeat is to tell the ASF firmware that the host | |
9081 | * driver is still alive. In the event that the OS crashes, | |
9082 | * ASF needs to reset the hardware to free up the FIFO space | |
9083 | * that may be filled with rx packets destined for the host. | |
9084 | * If the FIFO is full, ASF will no longer function properly. | |
9085 | * | |
9086 | * Unintended resets have been reported on real time kernels | |
9087 | * where the timer doesn't run on time. Netpoll will also have | |
9088 | * same problem. | |
9089 | * | |
9090 | * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware | |
9091 | * to check the ring condition when the heartbeat is expiring | |
9092 | * before doing the reset. This will prevent most unintended | |
9093 | * resets. | |
9094 | */ | |
1da177e4 | 9095 | if (!--tp->asf_counter) { |
63c3a66f | 9096 | if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) { |
7c5026aa MC |
9097 | tg3_wait_for_event_ack(tp); |
9098 | ||
bbadf503 | 9099 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, |
130b8e4d | 9100 | FWCMD_NICDRV_ALIVE3); |
bbadf503 | 9101 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4); |
c6cdf436 MC |
9102 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, |
9103 | TG3_FW_UPDATE_TIMEOUT_SEC); | |
4ba526ce MC |
9104 | |
9105 | tg3_generate_fw_event(tp); | |
1da177e4 LT |
9106 | } |
9107 | tp->asf_counter = tp->asf_multiplier; | |
9108 | } | |
9109 | ||
f47c11ee | 9110 | spin_unlock(&tp->lock); |
1da177e4 | 9111 | |
f475f163 | 9112 | restart_timer: |
1da177e4 LT |
9113 | tp->timer.expires = jiffies + tp->timer_offset; |
9114 | add_timer(&tp->timer); | |
9115 | } | |
9116 | ||
4f125f42 | 9117 | static int tg3_request_irq(struct tg3 *tp, int irq_num) |
fcfa0a32 | 9118 | { |
7d12e780 | 9119 | irq_handler_t fn; |
fcfa0a32 | 9120 | unsigned long flags; |
4f125f42 MC |
9121 | char *name; |
9122 | struct tg3_napi *tnapi = &tp->napi[irq_num]; | |
9123 | ||
9124 | if (tp->irq_cnt == 1) | |
9125 | name = tp->dev->name; | |
9126 | else { | |
9127 | name = &tnapi->irq_lbl[0]; | |
9128 | snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num); | |
9129 | name[IFNAMSIZ-1] = 0; | |
9130 | } | |
fcfa0a32 | 9131 | |
63c3a66f | 9132 | if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) { |
fcfa0a32 | 9133 | fn = tg3_msi; |
63c3a66f | 9134 | if (tg3_flag(tp, 1SHOT_MSI)) |
fcfa0a32 | 9135 | fn = tg3_msi_1shot; |
ab392d2d | 9136 | flags = 0; |
fcfa0a32 MC |
9137 | } else { |
9138 | fn = tg3_interrupt; | |
63c3a66f | 9139 | if (tg3_flag(tp, TAGGED_STATUS)) |
fcfa0a32 | 9140 | fn = tg3_interrupt_tagged; |
ab392d2d | 9141 | flags = IRQF_SHARED; |
fcfa0a32 | 9142 | } |
4f125f42 MC |
9143 | |
9144 | return request_irq(tnapi->irq_vec, fn, flags, name, tnapi); | |
fcfa0a32 MC |
9145 | } |
9146 | ||
7938109f MC |
9147 | static int tg3_test_interrupt(struct tg3 *tp) |
9148 | { | |
09943a18 | 9149 | struct tg3_napi *tnapi = &tp->napi[0]; |
7938109f | 9150 | struct net_device *dev = tp->dev; |
b16250e3 | 9151 | int err, i, intr_ok = 0; |
f6eb9b1f | 9152 | u32 val; |
7938109f | 9153 | |
d4bc3927 MC |
9154 | if (!netif_running(dev)) |
9155 | return -ENODEV; | |
9156 | ||
7938109f MC |
9157 | tg3_disable_ints(tp); |
9158 | ||
4f125f42 | 9159 | free_irq(tnapi->irq_vec, tnapi); |
7938109f | 9160 | |
f6eb9b1f MC |
9161 | /* |
9162 | * Turn off MSI one shot mode. Otherwise this test has no | |
9163 | * observable way to know whether the interrupt was delivered. | |
9164 | */ | |
63c3a66f | 9165 | if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) { |
f6eb9b1f MC |
9166 | val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE; |
9167 | tw32(MSGINT_MODE, val); | |
9168 | } | |
9169 | ||
4f125f42 | 9170 | err = request_irq(tnapi->irq_vec, tg3_test_isr, |
09943a18 | 9171 | IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi); |
7938109f MC |
9172 | if (err) |
9173 | return err; | |
9174 | ||
898a56f8 | 9175 | tnapi->hw_status->status &= ~SD_STATUS_UPDATED; |
7938109f MC |
9176 | tg3_enable_ints(tp); |
9177 | ||
9178 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | | |
fd2ce37f | 9179 | tnapi->coal_now); |
7938109f MC |
9180 | |
9181 | for (i = 0; i < 5; i++) { | |
b16250e3 MC |
9182 | u32 int_mbox, misc_host_ctrl; |
9183 | ||
898a56f8 | 9184 | int_mbox = tr32_mailbox(tnapi->int_mbox); |
b16250e3 MC |
9185 | misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL); |
9186 | ||
9187 | if ((int_mbox != 0) || | |
9188 | (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) { | |
9189 | intr_ok = 1; | |
7938109f | 9190 | break; |
b16250e3 MC |
9191 | } |
9192 | ||
7938109f MC |
9193 | msleep(10); |
9194 | } | |
9195 | ||
9196 | tg3_disable_ints(tp); | |
9197 | ||
4f125f42 | 9198 | free_irq(tnapi->irq_vec, tnapi); |
6aa20a22 | 9199 | |
4f125f42 | 9200 | err = tg3_request_irq(tp, 0); |
7938109f MC |
9201 | |
9202 | if (err) | |
9203 | return err; | |
9204 | ||
f6eb9b1f MC |
9205 | if (intr_ok) { |
9206 | /* Reenable MSI one shot mode. */ | |
63c3a66f | 9207 | if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) { |
f6eb9b1f MC |
9208 | val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE; |
9209 | tw32(MSGINT_MODE, val); | |
9210 | } | |
7938109f | 9211 | return 0; |
f6eb9b1f | 9212 | } |
7938109f MC |
9213 | |
9214 | return -EIO; | |
9215 | } | |
9216 | ||
9217 | /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is | |
9218 | * successfully restored | |
9219 | */ | |
9220 | static int tg3_test_msi(struct tg3 *tp) | |
9221 | { | |
7938109f MC |
9222 | int err; |
9223 | u16 pci_cmd; | |
9224 | ||
63c3a66f | 9225 | if (!tg3_flag(tp, USING_MSI)) |
7938109f MC |
9226 | return 0; |
9227 | ||
9228 | /* Turn off SERR reporting in case MSI terminates with Master | |
9229 | * Abort. | |
9230 | */ | |
9231 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
9232 | pci_write_config_word(tp->pdev, PCI_COMMAND, | |
9233 | pci_cmd & ~PCI_COMMAND_SERR); | |
9234 | ||
9235 | err = tg3_test_interrupt(tp); | |
9236 | ||
9237 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
9238 | ||
9239 | if (!err) | |
9240 | return 0; | |
9241 | ||
9242 | /* other failures */ | |
9243 | if (err != -EIO) | |
9244 | return err; | |
9245 | ||
9246 | /* MSI test failed, go back to INTx mode */ | |
5129c3a3 MC |
9247 | netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching " |
9248 | "to INTx mode. Please report this failure to the PCI " | |
9249 | "maintainer and include system chipset information\n"); | |
7938109f | 9250 | |
4f125f42 | 9251 | free_irq(tp->napi[0].irq_vec, &tp->napi[0]); |
09943a18 | 9252 | |
7938109f MC |
9253 | pci_disable_msi(tp->pdev); |
9254 | ||
63c3a66f | 9255 | tg3_flag_clear(tp, USING_MSI); |
dc8bf1b1 | 9256 | tp->napi[0].irq_vec = tp->pdev->irq; |
7938109f | 9257 | |
4f125f42 | 9258 | err = tg3_request_irq(tp, 0); |
7938109f MC |
9259 | if (err) |
9260 | return err; | |
9261 | ||
9262 | /* Need to reset the chip because the MSI cycle may have terminated | |
9263 | * with Master Abort. | |
9264 | */ | |
f47c11ee | 9265 | tg3_full_lock(tp, 1); |
7938109f | 9266 | |
944d980e | 9267 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
8e7a22e3 | 9268 | err = tg3_init_hw(tp, 1); |
7938109f | 9269 | |
f47c11ee | 9270 | tg3_full_unlock(tp); |
7938109f MC |
9271 | |
9272 | if (err) | |
4f125f42 | 9273 | free_irq(tp->napi[0].irq_vec, &tp->napi[0]); |
7938109f MC |
9274 | |
9275 | return err; | |
9276 | } | |
9277 | ||
9e9fd12d MC |
9278 | static int tg3_request_firmware(struct tg3 *tp) |
9279 | { | |
9280 | const __be32 *fw_data; | |
9281 | ||
9282 | if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) { | |
05dbe005 JP |
9283 | netdev_err(tp->dev, "Failed to load firmware \"%s\"\n", |
9284 | tp->fw_needed); | |
9e9fd12d MC |
9285 | return -ENOENT; |
9286 | } | |
9287 | ||
9288 | fw_data = (void *)tp->fw->data; | |
9289 | ||
9290 | /* Firmware blob starts with version numbers, followed by | |
9291 | * start address and _full_ length including BSS sections | |
9292 | * (which must be longer than the actual data, of course | |
9293 | */ | |
9294 | ||
9295 | tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */ | |
9296 | if (tp->fw_len < (tp->fw->size - 12)) { | |
05dbe005 JP |
9297 | netdev_err(tp->dev, "bogus length %d in \"%s\"\n", |
9298 | tp->fw_len, tp->fw_needed); | |
9e9fd12d MC |
9299 | release_firmware(tp->fw); |
9300 | tp->fw = NULL; | |
9301 | return -EINVAL; | |
9302 | } | |
9303 | ||
9304 | /* We no longer need firmware; we have it. */ | |
9305 | tp->fw_needed = NULL; | |
9306 | return 0; | |
9307 | } | |
9308 | ||
679563f4 MC |
9309 | static bool tg3_enable_msix(struct tg3 *tp) |
9310 | { | |
9311 | int i, rc, cpus = num_online_cpus(); | |
9312 | struct msix_entry msix_ent[tp->irq_max]; | |
9313 | ||
9314 | if (cpus == 1) | |
9315 | /* Just fallback to the simpler MSI mode. */ | |
9316 | return false; | |
9317 | ||
9318 | /* | |
9319 | * We want as many rx rings enabled as there are cpus. | |
9320 | * The first MSIX vector only deals with link interrupts, etc, | |
9321 | * so we add one to the number of vectors we are requesting. | |
9322 | */ | |
9323 | tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max); | |
9324 | ||
9325 | for (i = 0; i < tp->irq_max; i++) { | |
9326 | msix_ent[i].entry = i; | |
9327 | msix_ent[i].vector = 0; | |
9328 | } | |
9329 | ||
9330 | rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt); | |
2430b031 MC |
9331 | if (rc < 0) { |
9332 | return false; | |
9333 | } else if (rc != 0) { | |
679563f4 MC |
9334 | if (pci_enable_msix(tp->pdev, msix_ent, rc)) |
9335 | return false; | |
05dbe005 JP |
9336 | netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n", |
9337 | tp->irq_cnt, rc); | |
679563f4 MC |
9338 | tp->irq_cnt = rc; |
9339 | } | |
9340 | ||
9341 | for (i = 0; i < tp->irq_max; i++) | |
9342 | tp->napi[i].irq_vec = msix_ent[i].vector; | |
9343 | ||
2ddaad39 BH |
9344 | netif_set_real_num_tx_queues(tp->dev, 1); |
9345 | rc = tp->irq_cnt > 1 ? tp->irq_cnt - 1 : 1; | |
9346 | if (netif_set_real_num_rx_queues(tp->dev, rc)) { | |
9347 | pci_disable_msix(tp->pdev); | |
9348 | return false; | |
9349 | } | |
b92b9040 MC |
9350 | |
9351 | if (tp->irq_cnt > 1) { | |
63c3a66f | 9352 | tg3_flag_set(tp, ENABLE_RSS); |
d78b59f5 MC |
9353 | |
9354 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
9355 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
63c3a66f | 9356 | tg3_flag_set(tp, ENABLE_TSS); |
b92b9040 MC |
9357 | netif_set_real_num_tx_queues(tp->dev, tp->irq_cnt - 1); |
9358 | } | |
9359 | } | |
2430b031 | 9360 | |
679563f4 MC |
9361 | return true; |
9362 | } | |
9363 | ||
07b0173c MC |
9364 | static void tg3_ints_init(struct tg3 *tp) |
9365 | { | |
63c3a66f JP |
9366 | if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) && |
9367 | !tg3_flag(tp, TAGGED_STATUS)) { | |
07b0173c MC |
9368 | /* All MSI supporting chips should support tagged |
9369 | * status. Assert that this is the case. | |
9370 | */ | |
5129c3a3 MC |
9371 | netdev_warn(tp->dev, |
9372 | "MSI without TAGGED_STATUS? Not using MSI\n"); | |
679563f4 | 9373 | goto defcfg; |
07b0173c | 9374 | } |
4f125f42 | 9375 | |
63c3a66f JP |
9376 | if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp)) |
9377 | tg3_flag_set(tp, USING_MSIX); | |
9378 | else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0) | |
9379 | tg3_flag_set(tp, USING_MSI); | |
679563f4 | 9380 | |
63c3a66f | 9381 | if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) { |
679563f4 | 9382 | u32 msi_mode = tr32(MSGINT_MODE); |
63c3a66f | 9383 | if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1) |
baf8a94a | 9384 | msi_mode |= MSGINT_MODE_MULTIVEC_EN; |
679563f4 MC |
9385 | tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE); |
9386 | } | |
9387 | defcfg: | |
63c3a66f | 9388 | if (!tg3_flag(tp, USING_MSIX)) { |
679563f4 MC |
9389 | tp->irq_cnt = 1; |
9390 | tp->napi[0].irq_vec = tp->pdev->irq; | |
2ddaad39 | 9391 | netif_set_real_num_tx_queues(tp->dev, 1); |
85407885 | 9392 | netif_set_real_num_rx_queues(tp->dev, 1); |
679563f4 | 9393 | } |
07b0173c MC |
9394 | } |
9395 | ||
9396 | static void tg3_ints_fini(struct tg3 *tp) | |
9397 | { | |
63c3a66f | 9398 | if (tg3_flag(tp, USING_MSIX)) |
679563f4 | 9399 | pci_disable_msix(tp->pdev); |
63c3a66f | 9400 | else if (tg3_flag(tp, USING_MSI)) |
679563f4 | 9401 | pci_disable_msi(tp->pdev); |
63c3a66f JP |
9402 | tg3_flag_clear(tp, USING_MSI); |
9403 | tg3_flag_clear(tp, USING_MSIX); | |
9404 | tg3_flag_clear(tp, ENABLE_RSS); | |
9405 | tg3_flag_clear(tp, ENABLE_TSS); | |
07b0173c MC |
9406 | } |
9407 | ||
1da177e4 LT |
9408 | static int tg3_open(struct net_device *dev) |
9409 | { | |
9410 | struct tg3 *tp = netdev_priv(dev); | |
4f125f42 | 9411 | int i, err; |
1da177e4 | 9412 | |
9e9fd12d MC |
9413 | if (tp->fw_needed) { |
9414 | err = tg3_request_firmware(tp); | |
9415 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) { | |
9416 | if (err) | |
9417 | return err; | |
9418 | } else if (err) { | |
05dbe005 | 9419 | netdev_warn(tp->dev, "TSO capability disabled\n"); |
63c3a66f JP |
9420 | tg3_flag_clear(tp, TSO_CAPABLE); |
9421 | } else if (!tg3_flag(tp, TSO_CAPABLE)) { | |
05dbe005 | 9422 | netdev_notice(tp->dev, "TSO capability restored\n"); |
63c3a66f | 9423 | tg3_flag_set(tp, TSO_CAPABLE); |
9e9fd12d MC |
9424 | } |
9425 | } | |
9426 | ||
c49a1561 MC |
9427 | netif_carrier_off(tp->dev); |
9428 | ||
c866b7ea | 9429 | err = tg3_power_up(tp); |
2f751b67 | 9430 | if (err) |
bc1c7567 | 9431 | return err; |
2f751b67 MC |
9432 | |
9433 | tg3_full_lock(tp, 0); | |
bc1c7567 | 9434 | |
1da177e4 | 9435 | tg3_disable_ints(tp); |
63c3a66f | 9436 | tg3_flag_clear(tp, INIT_COMPLETE); |
1da177e4 | 9437 | |
f47c11ee | 9438 | tg3_full_unlock(tp); |
1da177e4 | 9439 | |
679563f4 MC |
9440 | /* |
9441 | * Setup interrupts first so we know how | |
9442 | * many NAPI resources to allocate | |
9443 | */ | |
9444 | tg3_ints_init(tp); | |
9445 | ||
1da177e4 LT |
9446 | /* The placement of this call is tied |
9447 | * to the setup and use of Host TX descriptors. | |
9448 | */ | |
9449 | err = tg3_alloc_consistent(tp); | |
9450 | if (err) | |
679563f4 | 9451 | goto err_out1; |
88b06bc2 | 9452 | |
66cfd1bd MC |
9453 | tg3_napi_init(tp); |
9454 | ||
fed97810 | 9455 | tg3_napi_enable(tp); |
1da177e4 | 9456 | |
4f125f42 MC |
9457 | for (i = 0; i < tp->irq_cnt; i++) { |
9458 | struct tg3_napi *tnapi = &tp->napi[i]; | |
9459 | err = tg3_request_irq(tp, i); | |
9460 | if (err) { | |
9461 | for (i--; i >= 0; i--) | |
9462 | free_irq(tnapi->irq_vec, tnapi); | |
9463 | break; | |
9464 | } | |
9465 | } | |
1da177e4 | 9466 | |
07b0173c | 9467 | if (err) |
679563f4 | 9468 | goto err_out2; |
bea3348e | 9469 | |
f47c11ee | 9470 | tg3_full_lock(tp, 0); |
1da177e4 | 9471 | |
8e7a22e3 | 9472 | err = tg3_init_hw(tp, 1); |
1da177e4 | 9473 | if (err) { |
944d980e | 9474 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 LT |
9475 | tg3_free_rings(tp); |
9476 | } else { | |
0e6cf6a9 MC |
9477 | if (tg3_flag(tp, TAGGED_STATUS) && |
9478 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 && | |
9479 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) | |
fac9b83e DM |
9480 | tp->timer_offset = HZ; |
9481 | else | |
9482 | tp->timer_offset = HZ / 10; | |
9483 | ||
9484 | BUG_ON(tp->timer_offset > HZ); | |
9485 | tp->timer_counter = tp->timer_multiplier = | |
9486 | (HZ / tp->timer_offset); | |
9487 | tp->asf_counter = tp->asf_multiplier = | |
28fbef78 | 9488 | ((HZ / tp->timer_offset) * 2); |
1da177e4 LT |
9489 | |
9490 | init_timer(&tp->timer); | |
9491 | tp->timer.expires = jiffies + tp->timer_offset; | |
9492 | tp->timer.data = (unsigned long) tp; | |
9493 | tp->timer.function = tg3_timer; | |
1da177e4 LT |
9494 | } |
9495 | ||
f47c11ee | 9496 | tg3_full_unlock(tp); |
1da177e4 | 9497 | |
07b0173c | 9498 | if (err) |
679563f4 | 9499 | goto err_out3; |
1da177e4 | 9500 | |
63c3a66f | 9501 | if (tg3_flag(tp, USING_MSI)) { |
7938109f | 9502 | err = tg3_test_msi(tp); |
fac9b83e | 9503 | |
7938109f | 9504 | if (err) { |
f47c11ee | 9505 | tg3_full_lock(tp, 0); |
944d980e | 9506 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
7938109f | 9507 | tg3_free_rings(tp); |
f47c11ee | 9508 | tg3_full_unlock(tp); |
7938109f | 9509 | |
679563f4 | 9510 | goto err_out2; |
7938109f | 9511 | } |
fcfa0a32 | 9512 | |
63c3a66f | 9513 | if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) { |
f6eb9b1f | 9514 | u32 val = tr32(PCIE_TRANSACTION_CFG); |
fcfa0a32 | 9515 | |
f6eb9b1f MC |
9516 | tw32(PCIE_TRANSACTION_CFG, |
9517 | val | PCIE_TRANS_CFG_1SHOT_MSI); | |
fcfa0a32 | 9518 | } |
7938109f MC |
9519 | } |
9520 | ||
b02fd9e3 MC |
9521 | tg3_phy_start(tp); |
9522 | ||
f47c11ee | 9523 | tg3_full_lock(tp, 0); |
1da177e4 | 9524 | |
7938109f | 9525 | add_timer(&tp->timer); |
63c3a66f | 9526 | tg3_flag_set(tp, INIT_COMPLETE); |
1da177e4 LT |
9527 | tg3_enable_ints(tp); |
9528 | ||
f47c11ee | 9529 | tg3_full_unlock(tp); |
1da177e4 | 9530 | |
fe5f5787 | 9531 | netif_tx_start_all_queues(dev); |
1da177e4 | 9532 | |
06c03c02 MB |
9533 | /* |
9534 | * Reset loopback feature if it was turned on while the device was down | |
9535 | * make sure that it's installed properly now. | |
9536 | */ | |
9537 | if (dev->features & NETIF_F_LOOPBACK) | |
9538 | tg3_set_loopback(dev, dev->features); | |
9539 | ||
1da177e4 | 9540 | return 0; |
07b0173c | 9541 | |
679563f4 | 9542 | err_out3: |
4f125f42 MC |
9543 | for (i = tp->irq_cnt - 1; i >= 0; i--) { |
9544 | struct tg3_napi *tnapi = &tp->napi[i]; | |
9545 | free_irq(tnapi->irq_vec, tnapi); | |
9546 | } | |
07b0173c | 9547 | |
679563f4 | 9548 | err_out2: |
fed97810 | 9549 | tg3_napi_disable(tp); |
66cfd1bd | 9550 | tg3_napi_fini(tp); |
07b0173c | 9551 | tg3_free_consistent(tp); |
679563f4 MC |
9552 | |
9553 | err_out1: | |
9554 | tg3_ints_fini(tp); | |
cd0d7228 MC |
9555 | tg3_frob_aux_power(tp, false); |
9556 | pci_set_power_state(tp->pdev, PCI_D3hot); | |
07b0173c | 9557 | return err; |
1da177e4 LT |
9558 | } |
9559 | ||
511d2224 ED |
9560 | static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *, |
9561 | struct rtnl_link_stats64 *); | |
1da177e4 LT |
9562 | static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *); |
9563 | ||
9564 | static int tg3_close(struct net_device *dev) | |
9565 | { | |
4f125f42 | 9566 | int i; |
1da177e4 LT |
9567 | struct tg3 *tp = netdev_priv(dev); |
9568 | ||
fed97810 | 9569 | tg3_napi_disable(tp); |
28e53bdd | 9570 | cancel_work_sync(&tp->reset_task); |
7faa006f | 9571 | |
fe5f5787 | 9572 | netif_tx_stop_all_queues(dev); |
1da177e4 LT |
9573 | |
9574 | del_timer_sync(&tp->timer); | |
9575 | ||
24bb4fb6 MC |
9576 | tg3_phy_stop(tp); |
9577 | ||
f47c11ee | 9578 | tg3_full_lock(tp, 1); |
1da177e4 LT |
9579 | |
9580 | tg3_disable_ints(tp); | |
9581 | ||
944d980e | 9582 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 | 9583 | tg3_free_rings(tp); |
63c3a66f | 9584 | tg3_flag_clear(tp, INIT_COMPLETE); |
1da177e4 | 9585 | |
f47c11ee | 9586 | tg3_full_unlock(tp); |
1da177e4 | 9587 | |
4f125f42 MC |
9588 | for (i = tp->irq_cnt - 1; i >= 0; i--) { |
9589 | struct tg3_napi *tnapi = &tp->napi[i]; | |
9590 | free_irq(tnapi->irq_vec, tnapi); | |
9591 | } | |
07b0173c MC |
9592 | |
9593 | tg3_ints_fini(tp); | |
1da177e4 | 9594 | |
511d2224 ED |
9595 | tg3_get_stats64(tp->dev, &tp->net_stats_prev); |
9596 | ||
1da177e4 LT |
9597 | memcpy(&tp->estats_prev, tg3_get_estats(tp), |
9598 | sizeof(tp->estats_prev)); | |
9599 | ||
66cfd1bd MC |
9600 | tg3_napi_fini(tp); |
9601 | ||
1da177e4 LT |
9602 | tg3_free_consistent(tp); |
9603 | ||
c866b7ea | 9604 | tg3_power_down(tp); |
bc1c7567 MC |
9605 | |
9606 | netif_carrier_off(tp->dev); | |
9607 | ||
1da177e4 LT |
9608 | return 0; |
9609 | } | |
9610 | ||
511d2224 | 9611 | static inline u64 get_stat64(tg3_stat64_t *val) |
816f8b86 SB |
9612 | { |
9613 | return ((u64)val->high << 32) | ((u64)val->low); | |
9614 | } | |
9615 | ||
511d2224 | 9616 | static u64 calc_crc_errors(struct tg3 *tp) |
1da177e4 LT |
9617 | { |
9618 | struct tg3_hw_stats *hw_stats = tp->hw_stats; | |
9619 | ||
f07e9af3 | 9620 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
1da177e4 LT |
9621 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
9622 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) { | |
1da177e4 LT |
9623 | u32 val; |
9624 | ||
f47c11ee | 9625 | spin_lock_bh(&tp->lock); |
569a5df8 MC |
9626 | if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) { |
9627 | tg3_writephy(tp, MII_TG3_TEST1, | |
9628 | val | MII_TG3_TEST1_CRC_EN); | |
f08aa1a8 | 9629 | tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val); |
1da177e4 LT |
9630 | } else |
9631 | val = 0; | |
f47c11ee | 9632 | spin_unlock_bh(&tp->lock); |
1da177e4 LT |
9633 | |
9634 | tp->phy_crc_errors += val; | |
9635 | ||
9636 | return tp->phy_crc_errors; | |
9637 | } | |
9638 | ||
9639 | return get_stat64(&hw_stats->rx_fcs_errors); | |
9640 | } | |
9641 | ||
9642 | #define ESTAT_ADD(member) \ | |
9643 | estats->member = old_estats->member + \ | |
511d2224 | 9644 | get_stat64(&hw_stats->member) |
1da177e4 LT |
9645 | |
9646 | static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp) | |
9647 | { | |
9648 | struct tg3_ethtool_stats *estats = &tp->estats; | |
9649 | struct tg3_ethtool_stats *old_estats = &tp->estats_prev; | |
9650 | struct tg3_hw_stats *hw_stats = tp->hw_stats; | |
9651 | ||
9652 | if (!hw_stats) | |
9653 | return old_estats; | |
9654 | ||
9655 | ESTAT_ADD(rx_octets); | |
9656 | ESTAT_ADD(rx_fragments); | |
9657 | ESTAT_ADD(rx_ucast_packets); | |
9658 | ESTAT_ADD(rx_mcast_packets); | |
9659 | ESTAT_ADD(rx_bcast_packets); | |
9660 | ESTAT_ADD(rx_fcs_errors); | |
9661 | ESTAT_ADD(rx_align_errors); | |
9662 | ESTAT_ADD(rx_xon_pause_rcvd); | |
9663 | ESTAT_ADD(rx_xoff_pause_rcvd); | |
9664 | ESTAT_ADD(rx_mac_ctrl_rcvd); | |
9665 | ESTAT_ADD(rx_xoff_entered); | |
9666 | ESTAT_ADD(rx_frame_too_long_errors); | |
9667 | ESTAT_ADD(rx_jabbers); | |
9668 | ESTAT_ADD(rx_undersize_packets); | |
9669 | ESTAT_ADD(rx_in_length_errors); | |
9670 | ESTAT_ADD(rx_out_length_errors); | |
9671 | ESTAT_ADD(rx_64_or_less_octet_packets); | |
9672 | ESTAT_ADD(rx_65_to_127_octet_packets); | |
9673 | ESTAT_ADD(rx_128_to_255_octet_packets); | |
9674 | ESTAT_ADD(rx_256_to_511_octet_packets); | |
9675 | ESTAT_ADD(rx_512_to_1023_octet_packets); | |
9676 | ESTAT_ADD(rx_1024_to_1522_octet_packets); | |
9677 | ESTAT_ADD(rx_1523_to_2047_octet_packets); | |
9678 | ESTAT_ADD(rx_2048_to_4095_octet_packets); | |
9679 | ESTAT_ADD(rx_4096_to_8191_octet_packets); | |
9680 | ESTAT_ADD(rx_8192_to_9022_octet_packets); | |
9681 | ||
9682 | ESTAT_ADD(tx_octets); | |
9683 | ESTAT_ADD(tx_collisions); | |
9684 | ESTAT_ADD(tx_xon_sent); | |
9685 | ESTAT_ADD(tx_xoff_sent); | |
9686 | ESTAT_ADD(tx_flow_control); | |
9687 | ESTAT_ADD(tx_mac_errors); | |
9688 | ESTAT_ADD(tx_single_collisions); | |
9689 | ESTAT_ADD(tx_mult_collisions); | |
9690 | ESTAT_ADD(tx_deferred); | |
9691 | ESTAT_ADD(tx_excessive_collisions); | |
9692 | ESTAT_ADD(tx_late_collisions); | |
9693 | ESTAT_ADD(tx_collide_2times); | |
9694 | ESTAT_ADD(tx_collide_3times); | |
9695 | ESTAT_ADD(tx_collide_4times); | |
9696 | ESTAT_ADD(tx_collide_5times); | |
9697 | ESTAT_ADD(tx_collide_6times); | |
9698 | ESTAT_ADD(tx_collide_7times); | |
9699 | ESTAT_ADD(tx_collide_8times); | |
9700 | ESTAT_ADD(tx_collide_9times); | |
9701 | ESTAT_ADD(tx_collide_10times); | |
9702 | ESTAT_ADD(tx_collide_11times); | |
9703 | ESTAT_ADD(tx_collide_12times); | |
9704 | ESTAT_ADD(tx_collide_13times); | |
9705 | ESTAT_ADD(tx_collide_14times); | |
9706 | ESTAT_ADD(tx_collide_15times); | |
9707 | ESTAT_ADD(tx_ucast_packets); | |
9708 | ESTAT_ADD(tx_mcast_packets); | |
9709 | ESTAT_ADD(tx_bcast_packets); | |
9710 | ESTAT_ADD(tx_carrier_sense_errors); | |
9711 | ESTAT_ADD(tx_discards); | |
9712 | ESTAT_ADD(tx_errors); | |
9713 | ||
9714 | ESTAT_ADD(dma_writeq_full); | |
9715 | ESTAT_ADD(dma_write_prioq_full); | |
9716 | ESTAT_ADD(rxbds_empty); | |
9717 | ESTAT_ADD(rx_discards); | |
9718 | ESTAT_ADD(rx_errors); | |
9719 | ESTAT_ADD(rx_threshold_hit); | |
9720 | ||
9721 | ESTAT_ADD(dma_readq_full); | |
9722 | ESTAT_ADD(dma_read_prioq_full); | |
9723 | ESTAT_ADD(tx_comp_queue_full); | |
9724 | ||
9725 | ESTAT_ADD(ring_set_send_prod_index); | |
9726 | ESTAT_ADD(ring_status_update); | |
9727 | ESTAT_ADD(nic_irqs); | |
9728 | ESTAT_ADD(nic_avoided_irqs); | |
9729 | ESTAT_ADD(nic_tx_threshold_hit); | |
9730 | ||
4452d099 MC |
9731 | ESTAT_ADD(mbuf_lwm_thresh_hit); |
9732 | ||
1da177e4 LT |
9733 | return estats; |
9734 | } | |
9735 | ||
511d2224 ED |
9736 | static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev, |
9737 | struct rtnl_link_stats64 *stats) | |
1da177e4 LT |
9738 | { |
9739 | struct tg3 *tp = netdev_priv(dev); | |
511d2224 | 9740 | struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev; |
1da177e4 LT |
9741 | struct tg3_hw_stats *hw_stats = tp->hw_stats; |
9742 | ||
9743 | if (!hw_stats) | |
9744 | return old_stats; | |
9745 | ||
9746 | stats->rx_packets = old_stats->rx_packets + | |
9747 | get_stat64(&hw_stats->rx_ucast_packets) + | |
9748 | get_stat64(&hw_stats->rx_mcast_packets) + | |
9749 | get_stat64(&hw_stats->rx_bcast_packets); | |
6aa20a22 | 9750 | |
1da177e4 LT |
9751 | stats->tx_packets = old_stats->tx_packets + |
9752 | get_stat64(&hw_stats->tx_ucast_packets) + | |
9753 | get_stat64(&hw_stats->tx_mcast_packets) + | |
9754 | get_stat64(&hw_stats->tx_bcast_packets); | |
9755 | ||
9756 | stats->rx_bytes = old_stats->rx_bytes + | |
9757 | get_stat64(&hw_stats->rx_octets); | |
9758 | stats->tx_bytes = old_stats->tx_bytes + | |
9759 | get_stat64(&hw_stats->tx_octets); | |
9760 | ||
9761 | stats->rx_errors = old_stats->rx_errors + | |
4f63b877 | 9762 | get_stat64(&hw_stats->rx_errors); |
1da177e4 LT |
9763 | stats->tx_errors = old_stats->tx_errors + |
9764 | get_stat64(&hw_stats->tx_errors) + | |
9765 | get_stat64(&hw_stats->tx_mac_errors) + | |
9766 | get_stat64(&hw_stats->tx_carrier_sense_errors) + | |
9767 | get_stat64(&hw_stats->tx_discards); | |
9768 | ||
9769 | stats->multicast = old_stats->multicast + | |
9770 | get_stat64(&hw_stats->rx_mcast_packets); | |
9771 | stats->collisions = old_stats->collisions + | |
9772 | get_stat64(&hw_stats->tx_collisions); | |
9773 | ||
9774 | stats->rx_length_errors = old_stats->rx_length_errors + | |
9775 | get_stat64(&hw_stats->rx_frame_too_long_errors) + | |
9776 | get_stat64(&hw_stats->rx_undersize_packets); | |
9777 | ||
9778 | stats->rx_over_errors = old_stats->rx_over_errors + | |
9779 | get_stat64(&hw_stats->rxbds_empty); | |
9780 | stats->rx_frame_errors = old_stats->rx_frame_errors + | |
9781 | get_stat64(&hw_stats->rx_align_errors); | |
9782 | stats->tx_aborted_errors = old_stats->tx_aborted_errors + | |
9783 | get_stat64(&hw_stats->tx_discards); | |
9784 | stats->tx_carrier_errors = old_stats->tx_carrier_errors + | |
9785 | get_stat64(&hw_stats->tx_carrier_sense_errors); | |
9786 | ||
9787 | stats->rx_crc_errors = old_stats->rx_crc_errors + | |
9788 | calc_crc_errors(tp); | |
9789 | ||
4f63b877 JL |
9790 | stats->rx_missed_errors = old_stats->rx_missed_errors + |
9791 | get_stat64(&hw_stats->rx_discards); | |
9792 | ||
b0057c51 ED |
9793 | stats->rx_dropped = tp->rx_dropped; |
9794 | ||
1da177e4 LT |
9795 | return stats; |
9796 | } | |
9797 | ||
9798 | static inline u32 calc_crc(unsigned char *buf, int len) | |
9799 | { | |
9800 | u32 reg; | |
9801 | u32 tmp; | |
9802 | int j, k; | |
9803 | ||
9804 | reg = 0xffffffff; | |
9805 | ||
9806 | for (j = 0; j < len; j++) { | |
9807 | reg ^= buf[j]; | |
9808 | ||
9809 | for (k = 0; k < 8; k++) { | |
9810 | tmp = reg & 0x01; | |
9811 | ||
9812 | reg >>= 1; | |
9813 | ||
859a5887 | 9814 | if (tmp) |
1da177e4 | 9815 | reg ^= 0xedb88320; |
1da177e4 LT |
9816 | } |
9817 | } | |
9818 | ||
9819 | return ~reg; | |
9820 | } | |
9821 | ||
9822 | static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all) | |
9823 | { | |
9824 | /* accept or reject all multicast frames */ | |
9825 | tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0); | |
9826 | tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0); | |
9827 | tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0); | |
9828 | tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0); | |
9829 | } | |
9830 | ||
9831 | static void __tg3_set_rx_mode(struct net_device *dev) | |
9832 | { | |
9833 | struct tg3 *tp = netdev_priv(dev); | |
9834 | u32 rx_mode; | |
9835 | ||
9836 | rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC | | |
9837 | RX_MODE_KEEP_VLAN_TAG); | |
9838 | ||
bf933c80 | 9839 | #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE) |
1da177e4 LT |
9840 | /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG |
9841 | * flag clear. | |
9842 | */ | |
63c3a66f | 9843 | if (!tg3_flag(tp, ENABLE_ASF)) |
1da177e4 LT |
9844 | rx_mode |= RX_MODE_KEEP_VLAN_TAG; |
9845 | #endif | |
9846 | ||
9847 | if (dev->flags & IFF_PROMISC) { | |
9848 | /* Promiscuous mode. */ | |
9849 | rx_mode |= RX_MODE_PROMISC; | |
9850 | } else if (dev->flags & IFF_ALLMULTI) { | |
9851 | /* Accept all multicast. */ | |
de6f31eb | 9852 | tg3_set_multi(tp, 1); |
4cd24eaf | 9853 | } else if (netdev_mc_empty(dev)) { |
1da177e4 | 9854 | /* Reject all multicast. */ |
de6f31eb | 9855 | tg3_set_multi(tp, 0); |
1da177e4 LT |
9856 | } else { |
9857 | /* Accept one or more multicast(s). */ | |
22bedad3 | 9858 | struct netdev_hw_addr *ha; |
1da177e4 LT |
9859 | u32 mc_filter[4] = { 0, }; |
9860 | u32 regidx; | |
9861 | u32 bit; | |
9862 | u32 crc; | |
9863 | ||
22bedad3 JP |
9864 | netdev_for_each_mc_addr(ha, dev) { |
9865 | crc = calc_crc(ha->addr, ETH_ALEN); | |
1da177e4 LT |
9866 | bit = ~crc & 0x7f; |
9867 | regidx = (bit & 0x60) >> 5; | |
9868 | bit &= 0x1f; | |
9869 | mc_filter[regidx] |= (1 << bit); | |
9870 | } | |
9871 | ||
9872 | tw32(MAC_HASH_REG_0, mc_filter[0]); | |
9873 | tw32(MAC_HASH_REG_1, mc_filter[1]); | |
9874 | tw32(MAC_HASH_REG_2, mc_filter[2]); | |
9875 | tw32(MAC_HASH_REG_3, mc_filter[3]); | |
9876 | } | |
9877 | ||
9878 | if (rx_mode != tp->rx_mode) { | |
9879 | tp->rx_mode = rx_mode; | |
9880 | tw32_f(MAC_RX_MODE, rx_mode); | |
9881 | udelay(10); | |
9882 | } | |
9883 | } | |
9884 | ||
9885 | static void tg3_set_rx_mode(struct net_device *dev) | |
9886 | { | |
9887 | struct tg3 *tp = netdev_priv(dev); | |
9888 | ||
e75f7c90 MC |
9889 | if (!netif_running(dev)) |
9890 | return; | |
9891 | ||
f47c11ee | 9892 | tg3_full_lock(tp, 0); |
1da177e4 | 9893 | __tg3_set_rx_mode(dev); |
f47c11ee | 9894 | tg3_full_unlock(tp); |
1da177e4 LT |
9895 | } |
9896 | ||
1da177e4 LT |
9897 | static int tg3_get_regs_len(struct net_device *dev) |
9898 | { | |
97bd8e49 | 9899 | return TG3_REG_BLK_SIZE; |
1da177e4 LT |
9900 | } |
9901 | ||
9902 | static void tg3_get_regs(struct net_device *dev, | |
9903 | struct ethtool_regs *regs, void *_p) | |
9904 | { | |
1da177e4 | 9905 | struct tg3 *tp = netdev_priv(dev); |
1da177e4 LT |
9906 | |
9907 | regs->version = 0; | |
9908 | ||
97bd8e49 | 9909 | memset(_p, 0, TG3_REG_BLK_SIZE); |
1da177e4 | 9910 | |
80096068 | 9911 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
bc1c7567 MC |
9912 | return; |
9913 | ||
f47c11ee | 9914 | tg3_full_lock(tp, 0); |
1da177e4 | 9915 | |
97bd8e49 | 9916 | tg3_dump_legacy_regs(tp, (u32 *)_p); |
1da177e4 | 9917 | |
f47c11ee | 9918 | tg3_full_unlock(tp); |
1da177e4 LT |
9919 | } |
9920 | ||
9921 | static int tg3_get_eeprom_len(struct net_device *dev) | |
9922 | { | |
9923 | struct tg3 *tp = netdev_priv(dev); | |
9924 | ||
9925 | return tp->nvram_size; | |
9926 | } | |
9927 | ||
1da177e4 LT |
9928 | static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data) |
9929 | { | |
9930 | struct tg3 *tp = netdev_priv(dev); | |
9931 | int ret; | |
9932 | u8 *pd; | |
b9fc7dc5 | 9933 | u32 i, offset, len, b_offset, b_count; |
a9dc529d | 9934 | __be32 val; |
1da177e4 | 9935 | |
63c3a66f | 9936 | if (tg3_flag(tp, NO_NVRAM)) |
df259d8c MC |
9937 | return -EINVAL; |
9938 | ||
80096068 | 9939 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
bc1c7567 MC |
9940 | return -EAGAIN; |
9941 | ||
1da177e4 LT |
9942 | offset = eeprom->offset; |
9943 | len = eeprom->len; | |
9944 | eeprom->len = 0; | |
9945 | ||
9946 | eeprom->magic = TG3_EEPROM_MAGIC; | |
9947 | ||
9948 | if (offset & 3) { | |
9949 | /* adjustments to start on required 4 byte boundary */ | |
9950 | b_offset = offset & 3; | |
9951 | b_count = 4 - b_offset; | |
9952 | if (b_count > len) { | |
9953 | /* i.e. offset=1 len=2 */ | |
9954 | b_count = len; | |
9955 | } | |
a9dc529d | 9956 | ret = tg3_nvram_read_be32(tp, offset-b_offset, &val); |
1da177e4 LT |
9957 | if (ret) |
9958 | return ret; | |
be98da6a | 9959 | memcpy(data, ((char *)&val) + b_offset, b_count); |
1da177e4 LT |
9960 | len -= b_count; |
9961 | offset += b_count; | |
c6cdf436 | 9962 | eeprom->len += b_count; |
1da177e4 LT |
9963 | } |
9964 | ||
25985edc | 9965 | /* read bytes up to the last 4 byte boundary */ |
1da177e4 LT |
9966 | pd = &data[eeprom->len]; |
9967 | for (i = 0; i < (len - (len & 3)); i += 4) { | |
a9dc529d | 9968 | ret = tg3_nvram_read_be32(tp, offset + i, &val); |
1da177e4 LT |
9969 | if (ret) { |
9970 | eeprom->len += i; | |
9971 | return ret; | |
9972 | } | |
1da177e4 LT |
9973 | memcpy(pd + i, &val, 4); |
9974 | } | |
9975 | eeprom->len += i; | |
9976 | ||
9977 | if (len & 3) { | |
9978 | /* read last bytes not ending on 4 byte boundary */ | |
9979 | pd = &data[eeprom->len]; | |
9980 | b_count = len & 3; | |
9981 | b_offset = offset + len - b_count; | |
a9dc529d | 9982 | ret = tg3_nvram_read_be32(tp, b_offset, &val); |
1da177e4 LT |
9983 | if (ret) |
9984 | return ret; | |
b9fc7dc5 | 9985 | memcpy(pd, &val, b_count); |
1da177e4 LT |
9986 | eeprom->len += b_count; |
9987 | } | |
9988 | return 0; | |
9989 | } | |
9990 | ||
6aa20a22 | 9991 | static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf); |
1da177e4 LT |
9992 | |
9993 | static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data) | |
9994 | { | |
9995 | struct tg3 *tp = netdev_priv(dev); | |
9996 | int ret; | |
b9fc7dc5 | 9997 | u32 offset, len, b_offset, odd_len; |
1da177e4 | 9998 | u8 *buf; |
a9dc529d | 9999 | __be32 start, end; |
1da177e4 | 10000 | |
80096068 | 10001 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
bc1c7567 MC |
10002 | return -EAGAIN; |
10003 | ||
63c3a66f | 10004 | if (tg3_flag(tp, NO_NVRAM) || |
df259d8c | 10005 | eeprom->magic != TG3_EEPROM_MAGIC) |
1da177e4 LT |
10006 | return -EINVAL; |
10007 | ||
10008 | offset = eeprom->offset; | |
10009 | len = eeprom->len; | |
10010 | ||
10011 | if ((b_offset = (offset & 3))) { | |
10012 | /* adjustments to start on required 4 byte boundary */ | |
a9dc529d | 10013 | ret = tg3_nvram_read_be32(tp, offset-b_offset, &start); |
1da177e4 LT |
10014 | if (ret) |
10015 | return ret; | |
1da177e4 LT |
10016 | len += b_offset; |
10017 | offset &= ~3; | |
1c8594b4 MC |
10018 | if (len < 4) |
10019 | len = 4; | |
1da177e4 LT |
10020 | } |
10021 | ||
10022 | odd_len = 0; | |
1c8594b4 | 10023 | if (len & 3) { |
1da177e4 LT |
10024 | /* adjustments to end on required 4 byte boundary */ |
10025 | odd_len = 1; | |
10026 | len = (len + 3) & ~3; | |
a9dc529d | 10027 | ret = tg3_nvram_read_be32(tp, offset+len-4, &end); |
1da177e4 LT |
10028 | if (ret) |
10029 | return ret; | |
1da177e4 LT |
10030 | } |
10031 | ||
10032 | buf = data; | |
10033 | if (b_offset || odd_len) { | |
10034 | buf = kmalloc(len, GFP_KERNEL); | |
ab0049b4 | 10035 | if (!buf) |
1da177e4 LT |
10036 | return -ENOMEM; |
10037 | if (b_offset) | |
10038 | memcpy(buf, &start, 4); | |
10039 | if (odd_len) | |
10040 | memcpy(buf+len-4, &end, 4); | |
10041 | memcpy(buf + b_offset, data, eeprom->len); | |
10042 | } | |
10043 | ||
10044 | ret = tg3_nvram_write_block(tp, offset, len, buf); | |
10045 | ||
10046 | if (buf != data) | |
10047 | kfree(buf); | |
10048 | ||
10049 | return ret; | |
10050 | } | |
10051 | ||
10052 | static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
10053 | { | |
b02fd9e3 MC |
10054 | struct tg3 *tp = netdev_priv(dev); |
10055 | ||
63c3a66f | 10056 | if (tg3_flag(tp, USE_PHYLIB)) { |
3f0e3ad7 | 10057 | struct phy_device *phydev; |
f07e9af3 | 10058 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 | 10059 | return -EAGAIN; |
3f0e3ad7 MC |
10060 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
10061 | return phy_ethtool_gset(phydev, cmd); | |
b02fd9e3 | 10062 | } |
6aa20a22 | 10063 | |
1da177e4 LT |
10064 | cmd->supported = (SUPPORTED_Autoneg); |
10065 | ||
f07e9af3 | 10066 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) |
1da177e4 LT |
10067 | cmd->supported |= (SUPPORTED_1000baseT_Half | |
10068 | SUPPORTED_1000baseT_Full); | |
10069 | ||
f07e9af3 | 10070 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { |
1da177e4 LT |
10071 | cmd->supported |= (SUPPORTED_100baseT_Half | |
10072 | SUPPORTED_100baseT_Full | | |
10073 | SUPPORTED_10baseT_Half | | |
10074 | SUPPORTED_10baseT_Full | | |
3bebab59 | 10075 | SUPPORTED_TP); |
ef348144 KK |
10076 | cmd->port = PORT_TP; |
10077 | } else { | |
1da177e4 | 10078 | cmd->supported |= SUPPORTED_FIBRE; |
ef348144 KK |
10079 | cmd->port = PORT_FIBRE; |
10080 | } | |
6aa20a22 | 10081 | |
1da177e4 | 10082 | cmd->advertising = tp->link_config.advertising; |
5bb09778 MC |
10083 | if (tg3_flag(tp, PAUSE_AUTONEG)) { |
10084 | if (tp->link_config.flowctrl & FLOW_CTRL_RX) { | |
10085 | if (tp->link_config.flowctrl & FLOW_CTRL_TX) { | |
10086 | cmd->advertising |= ADVERTISED_Pause; | |
10087 | } else { | |
10088 | cmd->advertising |= ADVERTISED_Pause | | |
10089 | ADVERTISED_Asym_Pause; | |
10090 | } | |
10091 | } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) { | |
10092 | cmd->advertising |= ADVERTISED_Asym_Pause; | |
10093 | } | |
10094 | } | |
1da177e4 | 10095 | if (netif_running(dev)) { |
70739497 | 10096 | ethtool_cmd_speed_set(cmd, tp->link_config.active_speed); |
1da177e4 | 10097 | cmd->duplex = tp->link_config.active_duplex; |
64c22182 | 10098 | } else { |
70739497 | 10099 | ethtool_cmd_speed_set(cmd, SPEED_INVALID); |
64c22182 | 10100 | cmd->duplex = DUPLEX_INVALID; |
1da177e4 | 10101 | } |
882e9793 | 10102 | cmd->phy_address = tp->phy_addr; |
7e5856bd | 10103 | cmd->transceiver = XCVR_INTERNAL; |
1da177e4 LT |
10104 | cmd->autoneg = tp->link_config.autoneg; |
10105 | cmd->maxtxpkt = 0; | |
10106 | cmd->maxrxpkt = 0; | |
10107 | return 0; | |
10108 | } | |
6aa20a22 | 10109 | |
1da177e4 LT |
10110 | static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
10111 | { | |
10112 | struct tg3 *tp = netdev_priv(dev); | |
25db0338 | 10113 | u32 speed = ethtool_cmd_speed(cmd); |
6aa20a22 | 10114 | |
63c3a66f | 10115 | if (tg3_flag(tp, USE_PHYLIB)) { |
3f0e3ad7 | 10116 | struct phy_device *phydev; |
f07e9af3 | 10117 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 | 10118 | return -EAGAIN; |
3f0e3ad7 MC |
10119 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
10120 | return phy_ethtool_sset(phydev, cmd); | |
b02fd9e3 MC |
10121 | } |
10122 | ||
7e5856bd MC |
10123 | if (cmd->autoneg != AUTONEG_ENABLE && |
10124 | cmd->autoneg != AUTONEG_DISABLE) | |
37ff238d | 10125 | return -EINVAL; |
7e5856bd MC |
10126 | |
10127 | if (cmd->autoneg == AUTONEG_DISABLE && | |
10128 | cmd->duplex != DUPLEX_FULL && | |
10129 | cmd->duplex != DUPLEX_HALF) | |
37ff238d | 10130 | return -EINVAL; |
1da177e4 | 10131 | |
7e5856bd MC |
10132 | if (cmd->autoneg == AUTONEG_ENABLE) { |
10133 | u32 mask = ADVERTISED_Autoneg | | |
10134 | ADVERTISED_Pause | | |
10135 | ADVERTISED_Asym_Pause; | |
10136 | ||
f07e9af3 | 10137 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) |
7e5856bd MC |
10138 | mask |= ADVERTISED_1000baseT_Half | |
10139 | ADVERTISED_1000baseT_Full; | |
10140 | ||
f07e9af3 | 10141 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) |
7e5856bd MC |
10142 | mask |= ADVERTISED_100baseT_Half | |
10143 | ADVERTISED_100baseT_Full | | |
10144 | ADVERTISED_10baseT_Half | | |
10145 | ADVERTISED_10baseT_Full | | |
10146 | ADVERTISED_TP; | |
10147 | else | |
10148 | mask |= ADVERTISED_FIBRE; | |
10149 | ||
10150 | if (cmd->advertising & ~mask) | |
10151 | return -EINVAL; | |
10152 | ||
10153 | mask &= (ADVERTISED_1000baseT_Half | | |
10154 | ADVERTISED_1000baseT_Full | | |
10155 | ADVERTISED_100baseT_Half | | |
10156 | ADVERTISED_100baseT_Full | | |
10157 | ADVERTISED_10baseT_Half | | |
10158 | ADVERTISED_10baseT_Full); | |
10159 | ||
10160 | cmd->advertising &= mask; | |
10161 | } else { | |
f07e9af3 | 10162 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) { |
25db0338 | 10163 | if (speed != SPEED_1000) |
7e5856bd MC |
10164 | return -EINVAL; |
10165 | ||
10166 | if (cmd->duplex != DUPLEX_FULL) | |
10167 | return -EINVAL; | |
10168 | } else { | |
25db0338 DD |
10169 | if (speed != SPEED_100 && |
10170 | speed != SPEED_10) | |
7e5856bd MC |
10171 | return -EINVAL; |
10172 | } | |
10173 | } | |
10174 | ||
f47c11ee | 10175 | tg3_full_lock(tp, 0); |
1da177e4 LT |
10176 | |
10177 | tp->link_config.autoneg = cmd->autoneg; | |
10178 | if (cmd->autoneg == AUTONEG_ENABLE) { | |
405d8e5c AG |
10179 | tp->link_config.advertising = (cmd->advertising | |
10180 | ADVERTISED_Autoneg); | |
1da177e4 LT |
10181 | tp->link_config.speed = SPEED_INVALID; |
10182 | tp->link_config.duplex = DUPLEX_INVALID; | |
10183 | } else { | |
10184 | tp->link_config.advertising = 0; | |
25db0338 | 10185 | tp->link_config.speed = speed; |
1da177e4 | 10186 | tp->link_config.duplex = cmd->duplex; |
b02fd9e3 | 10187 | } |
6aa20a22 | 10188 | |
24fcad6b MC |
10189 | tp->link_config.orig_speed = tp->link_config.speed; |
10190 | tp->link_config.orig_duplex = tp->link_config.duplex; | |
10191 | tp->link_config.orig_autoneg = tp->link_config.autoneg; | |
10192 | ||
1da177e4 LT |
10193 | if (netif_running(dev)) |
10194 | tg3_setup_phy(tp, 1); | |
10195 | ||
f47c11ee | 10196 | tg3_full_unlock(tp); |
6aa20a22 | 10197 | |
1da177e4 LT |
10198 | return 0; |
10199 | } | |
6aa20a22 | 10200 | |
1da177e4 LT |
10201 | static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) |
10202 | { | |
10203 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 10204 | |
1da177e4 LT |
10205 | strcpy(info->driver, DRV_MODULE_NAME); |
10206 | strcpy(info->version, DRV_MODULE_VERSION); | |
c4e6575c | 10207 | strcpy(info->fw_version, tp->fw_ver); |
1da177e4 LT |
10208 | strcpy(info->bus_info, pci_name(tp->pdev)); |
10209 | } | |
6aa20a22 | 10210 | |
1da177e4 LT |
10211 | static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
10212 | { | |
10213 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 10214 | |
63c3a66f | 10215 | if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev)) |
a85feb8c GZ |
10216 | wol->supported = WAKE_MAGIC; |
10217 | else | |
10218 | wol->supported = 0; | |
1da177e4 | 10219 | wol->wolopts = 0; |
63c3a66f | 10220 | if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev)) |
1da177e4 LT |
10221 | wol->wolopts = WAKE_MAGIC; |
10222 | memset(&wol->sopass, 0, sizeof(wol->sopass)); | |
10223 | } | |
6aa20a22 | 10224 | |
1da177e4 LT |
10225 | static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
10226 | { | |
10227 | struct tg3 *tp = netdev_priv(dev); | |
12dac075 | 10228 | struct device *dp = &tp->pdev->dev; |
6aa20a22 | 10229 | |
1da177e4 LT |
10230 | if (wol->wolopts & ~WAKE_MAGIC) |
10231 | return -EINVAL; | |
10232 | if ((wol->wolopts & WAKE_MAGIC) && | |
63c3a66f | 10233 | !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp))) |
1da177e4 | 10234 | return -EINVAL; |
6aa20a22 | 10235 | |
f2dc0d18 RW |
10236 | device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC); |
10237 | ||
f47c11ee | 10238 | spin_lock_bh(&tp->lock); |
f2dc0d18 | 10239 | if (device_may_wakeup(dp)) |
63c3a66f | 10240 | tg3_flag_set(tp, WOL_ENABLE); |
f2dc0d18 | 10241 | else |
63c3a66f | 10242 | tg3_flag_clear(tp, WOL_ENABLE); |
f47c11ee | 10243 | spin_unlock_bh(&tp->lock); |
6aa20a22 | 10244 | |
1da177e4 LT |
10245 | return 0; |
10246 | } | |
6aa20a22 | 10247 | |
1da177e4 LT |
10248 | static u32 tg3_get_msglevel(struct net_device *dev) |
10249 | { | |
10250 | struct tg3 *tp = netdev_priv(dev); | |
10251 | return tp->msg_enable; | |
10252 | } | |
6aa20a22 | 10253 | |
1da177e4 LT |
10254 | static void tg3_set_msglevel(struct net_device *dev, u32 value) |
10255 | { | |
10256 | struct tg3 *tp = netdev_priv(dev); | |
10257 | tp->msg_enable = value; | |
10258 | } | |
6aa20a22 | 10259 | |
1da177e4 LT |
10260 | static int tg3_nway_reset(struct net_device *dev) |
10261 | { | |
10262 | struct tg3 *tp = netdev_priv(dev); | |
1da177e4 | 10263 | int r; |
6aa20a22 | 10264 | |
1da177e4 LT |
10265 | if (!netif_running(dev)) |
10266 | return -EAGAIN; | |
10267 | ||
f07e9af3 | 10268 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
c94e3941 MC |
10269 | return -EINVAL; |
10270 | ||
63c3a66f | 10271 | if (tg3_flag(tp, USE_PHYLIB)) { |
f07e9af3 | 10272 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 | 10273 | return -EAGAIN; |
3f0e3ad7 | 10274 | r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
b02fd9e3 MC |
10275 | } else { |
10276 | u32 bmcr; | |
10277 | ||
10278 | spin_lock_bh(&tp->lock); | |
10279 | r = -EINVAL; | |
10280 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
10281 | if (!tg3_readphy(tp, MII_BMCR, &bmcr) && | |
10282 | ((bmcr & BMCR_ANENABLE) || | |
f07e9af3 | 10283 | (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) { |
b02fd9e3 MC |
10284 | tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART | |
10285 | BMCR_ANENABLE); | |
10286 | r = 0; | |
10287 | } | |
10288 | spin_unlock_bh(&tp->lock); | |
1da177e4 | 10289 | } |
6aa20a22 | 10290 | |
1da177e4 LT |
10291 | return r; |
10292 | } | |
6aa20a22 | 10293 | |
1da177e4 LT |
10294 | static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) |
10295 | { | |
10296 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 10297 | |
2c49a44d | 10298 | ering->rx_max_pending = tp->rx_std_ring_mask; |
1da177e4 | 10299 | ering->rx_mini_max_pending = 0; |
63c3a66f | 10300 | if (tg3_flag(tp, JUMBO_RING_ENABLE)) |
2c49a44d | 10301 | ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask; |
4f81c32b MC |
10302 | else |
10303 | ering->rx_jumbo_max_pending = 0; | |
10304 | ||
10305 | ering->tx_max_pending = TG3_TX_RING_SIZE - 1; | |
1da177e4 LT |
10306 | |
10307 | ering->rx_pending = tp->rx_pending; | |
10308 | ering->rx_mini_pending = 0; | |
63c3a66f | 10309 | if (tg3_flag(tp, JUMBO_RING_ENABLE)) |
4f81c32b MC |
10310 | ering->rx_jumbo_pending = tp->rx_jumbo_pending; |
10311 | else | |
10312 | ering->rx_jumbo_pending = 0; | |
10313 | ||
f3f3f27e | 10314 | ering->tx_pending = tp->napi[0].tx_pending; |
1da177e4 | 10315 | } |
6aa20a22 | 10316 | |
1da177e4 LT |
10317 | static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) |
10318 | { | |
10319 | struct tg3 *tp = netdev_priv(dev); | |
646c9edd | 10320 | int i, irq_sync = 0, err = 0; |
6aa20a22 | 10321 | |
2c49a44d MC |
10322 | if ((ering->rx_pending > tp->rx_std_ring_mask) || |
10323 | (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) || | |
bc3a9254 MC |
10324 | (ering->tx_pending > TG3_TX_RING_SIZE - 1) || |
10325 | (ering->tx_pending <= MAX_SKB_FRAGS) || | |
63c3a66f | 10326 | (tg3_flag(tp, TSO_BUG) && |
bc3a9254 | 10327 | (ering->tx_pending <= (MAX_SKB_FRAGS * 3)))) |
1da177e4 | 10328 | return -EINVAL; |
6aa20a22 | 10329 | |
bbe832c0 | 10330 | if (netif_running(dev)) { |
b02fd9e3 | 10331 | tg3_phy_stop(tp); |
1da177e4 | 10332 | tg3_netif_stop(tp); |
bbe832c0 MC |
10333 | irq_sync = 1; |
10334 | } | |
1da177e4 | 10335 | |
bbe832c0 | 10336 | tg3_full_lock(tp, irq_sync); |
6aa20a22 | 10337 | |
1da177e4 LT |
10338 | tp->rx_pending = ering->rx_pending; |
10339 | ||
63c3a66f | 10340 | if (tg3_flag(tp, MAX_RXPEND_64) && |
1da177e4 LT |
10341 | tp->rx_pending > 63) |
10342 | tp->rx_pending = 63; | |
10343 | tp->rx_jumbo_pending = ering->rx_jumbo_pending; | |
646c9edd | 10344 | |
6fd45cb8 | 10345 | for (i = 0; i < tp->irq_max; i++) |
646c9edd | 10346 | tp->napi[i].tx_pending = ering->tx_pending; |
1da177e4 LT |
10347 | |
10348 | if (netif_running(dev)) { | |
944d980e | 10349 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
b9ec6c1b MC |
10350 | err = tg3_restart_hw(tp, 1); |
10351 | if (!err) | |
10352 | tg3_netif_start(tp); | |
1da177e4 LT |
10353 | } |
10354 | ||
f47c11ee | 10355 | tg3_full_unlock(tp); |
6aa20a22 | 10356 | |
b02fd9e3 MC |
10357 | if (irq_sync && !err) |
10358 | tg3_phy_start(tp); | |
10359 | ||
b9ec6c1b | 10360 | return err; |
1da177e4 | 10361 | } |
6aa20a22 | 10362 | |
1da177e4 LT |
10363 | static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) |
10364 | { | |
10365 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 10366 | |
63c3a66f | 10367 | epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG); |
8d018621 | 10368 | |
e18ce346 | 10369 | if (tp->link_config.active_flowctrl & FLOW_CTRL_RX) |
8d018621 MC |
10370 | epause->rx_pause = 1; |
10371 | else | |
10372 | epause->rx_pause = 0; | |
10373 | ||
e18ce346 | 10374 | if (tp->link_config.active_flowctrl & FLOW_CTRL_TX) |
8d018621 MC |
10375 | epause->tx_pause = 1; |
10376 | else | |
10377 | epause->tx_pause = 0; | |
1da177e4 | 10378 | } |
6aa20a22 | 10379 | |
1da177e4 LT |
10380 | static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) |
10381 | { | |
10382 | struct tg3 *tp = netdev_priv(dev); | |
b02fd9e3 | 10383 | int err = 0; |
6aa20a22 | 10384 | |
63c3a66f | 10385 | if (tg3_flag(tp, USE_PHYLIB)) { |
2712168f MC |
10386 | u32 newadv; |
10387 | struct phy_device *phydev; | |
1da177e4 | 10388 | |
2712168f | 10389 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
f47c11ee | 10390 | |
2712168f MC |
10391 | if (!(phydev->supported & SUPPORTED_Pause) || |
10392 | (!(phydev->supported & SUPPORTED_Asym_Pause) && | |
2259dca3 | 10393 | (epause->rx_pause != epause->tx_pause))) |
2712168f | 10394 | return -EINVAL; |
1da177e4 | 10395 | |
2712168f MC |
10396 | tp->link_config.flowctrl = 0; |
10397 | if (epause->rx_pause) { | |
10398 | tp->link_config.flowctrl |= FLOW_CTRL_RX; | |
10399 | ||
10400 | if (epause->tx_pause) { | |
10401 | tp->link_config.flowctrl |= FLOW_CTRL_TX; | |
10402 | newadv = ADVERTISED_Pause; | |
b02fd9e3 | 10403 | } else |
2712168f MC |
10404 | newadv = ADVERTISED_Pause | |
10405 | ADVERTISED_Asym_Pause; | |
10406 | } else if (epause->tx_pause) { | |
10407 | tp->link_config.flowctrl |= FLOW_CTRL_TX; | |
10408 | newadv = ADVERTISED_Asym_Pause; | |
10409 | } else | |
10410 | newadv = 0; | |
10411 | ||
10412 | if (epause->autoneg) | |
63c3a66f | 10413 | tg3_flag_set(tp, PAUSE_AUTONEG); |
2712168f | 10414 | else |
63c3a66f | 10415 | tg3_flag_clear(tp, PAUSE_AUTONEG); |
2712168f | 10416 | |
f07e9af3 | 10417 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { |
2712168f MC |
10418 | u32 oldadv = phydev->advertising & |
10419 | (ADVERTISED_Pause | ADVERTISED_Asym_Pause); | |
10420 | if (oldadv != newadv) { | |
10421 | phydev->advertising &= | |
10422 | ~(ADVERTISED_Pause | | |
10423 | ADVERTISED_Asym_Pause); | |
10424 | phydev->advertising |= newadv; | |
10425 | if (phydev->autoneg) { | |
10426 | /* | |
10427 | * Always renegotiate the link to | |
10428 | * inform our link partner of our | |
10429 | * flow control settings, even if the | |
10430 | * flow control is forced. Let | |
10431 | * tg3_adjust_link() do the final | |
10432 | * flow control setup. | |
10433 | */ | |
10434 | return phy_start_aneg(phydev); | |
b02fd9e3 | 10435 | } |
b02fd9e3 | 10436 | } |
b02fd9e3 | 10437 | |
2712168f | 10438 | if (!epause->autoneg) |
b02fd9e3 | 10439 | tg3_setup_flow_control(tp, 0, 0); |
2712168f MC |
10440 | } else { |
10441 | tp->link_config.orig_advertising &= | |
10442 | ~(ADVERTISED_Pause | | |
10443 | ADVERTISED_Asym_Pause); | |
10444 | tp->link_config.orig_advertising |= newadv; | |
b02fd9e3 MC |
10445 | } |
10446 | } else { | |
10447 | int irq_sync = 0; | |
10448 | ||
10449 | if (netif_running(dev)) { | |
10450 | tg3_netif_stop(tp); | |
10451 | irq_sync = 1; | |
10452 | } | |
10453 | ||
10454 | tg3_full_lock(tp, irq_sync); | |
10455 | ||
10456 | if (epause->autoneg) | |
63c3a66f | 10457 | tg3_flag_set(tp, PAUSE_AUTONEG); |
b02fd9e3 | 10458 | else |
63c3a66f | 10459 | tg3_flag_clear(tp, PAUSE_AUTONEG); |
b02fd9e3 | 10460 | if (epause->rx_pause) |
e18ce346 | 10461 | tp->link_config.flowctrl |= FLOW_CTRL_RX; |
b02fd9e3 | 10462 | else |
e18ce346 | 10463 | tp->link_config.flowctrl &= ~FLOW_CTRL_RX; |
b02fd9e3 | 10464 | if (epause->tx_pause) |
e18ce346 | 10465 | tp->link_config.flowctrl |= FLOW_CTRL_TX; |
b02fd9e3 | 10466 | else |
e18ce346 | 10467 | tp->link_config.flowctrl &= ~FLOW_CTRL_TX; |
b02fd9e3 MC |
10468 | |
10469 | if (netif_running(dev)) { | |
10470 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
10471 | err = tg3_restart_hw(tp, 1); | |
10472 | if (!err) | |
10473 | tg3_netif_start(tp); | |
10474 | } | |
10475 | ||
10476 | tg3_full_unlock(tp); | |
10477 | } | |
6aa20a22 | 10478 | |
b9ec6c1b | 10479 | return err; |
1da177e4 | 10480 | } |
6aa20a22 | 10481 | |
de6f31eb | 10482 | static int tg3_get_sset_count(struct net_device *dev, int sset) |
1da177e4 | 10483 | { |
b9f2c044 JG |
10484 | switch (sset) { |
10485 | case ETH_SS_TEST: | |
10486 | return TG3_NUM_TEST; | |
10487 | case ETH_SS_STATS: | |
10488 | return TG3_NUM_STATS; | |
10489 | default: | |
10490 | return -EOPNOTSUPP; | |
10491 | } | |
4cafd3f5 MC |
10492 | } |
10493 | ||
de6f31eb | 10494 | static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf) |
1da177e4 LT |
10495 | { |
10496 | switch (stringset) { | |
10497 | case ETH_SS_STATS: | |
10498 | memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys)); | |
10499 | break; | |
4cafd3f5 MC |
10500 | case ETH_SS_TEST: |
10501 | memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys)); | |
10502 | break; | |
1da177e4 LT |
10503 | default: |
10504 | WARN_ON(1); /* we need a WARN() */ | |
10505 | break; | |
10506 | } | |
10507 | } | |
10508 | ||
81b8709c | 10509 | static int tg3_set_phys_id(struct net_device *dev, |
10510 | enum ethtool_phys_id_state state) | |
4009a93d MC |
10511 | { |
10512 | struct tg3 *tp = netdev_priv(dev); | |
4009a93d MC |
10513 | |
10514 | if (!netif_running(tp->dev)) | |
10515 | return -EAGAIN; | |
10516 | ||
81b8709c | 10517 | switch (state) { |
10518 | case ETHTOOL_ID_ACTIVE: | |
fce55922 | 10519 | return 1; /* cycle on/off once per second */ |
4009a93d | 10520 | |
81b8709c | 10521 | case ETHTOOL_ID_ON: |
10522 | tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE | | |
10523 | LED_CTRL_1000MBPS_ON | | |
10524 | LED_CTRL_100MBPS_ON | | |
10525 | LED_CTRL_10MBPS_ON | | |
10526 | LED_CTRL_TRAFFIC_OVERRIDE | | |
10527 | LED_CTRL_TRAFFIC_BLINK | | |
10528 | LED_CTRL_TRAFFIC_LED); | |
10529 | break; | |
6aa20a22 | 10530 | |
81b8709c | 10531 | case ETHTOOL_ID_OFF: |
10532 | tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE | | |
10533 | LED_CTRL_TRAFFIC_OVERRIDE); | |
10534 | break; | |
4009a93d | 10535 | |
81b8709c | 10536 | case ETHTOOL_ID_INACTIVE: |
10537 | tw32(MAC_LED_CTRL, tp->led_ctrl); | |
10538 | break; | |
4009a93d | 10539 | } |
81b8709c | 10540 | |
4009a93d MC |
10541 | return 0; |
10542 | } | |
10543 | ||
de6f31eb | 10544 | static void tg3_get_ethtool_stats(struct net_device *dev, |
1da177e4 LT |
10545 | struct ethtool_stats *estats, u64 *tmp_stats) |
10546 | { | |
10547 | struct tg3 *tp = netdev_priv(dev); | |
10548 | memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats)); | |
10549 | } | |
10550 | ||
c3e94500 MC |
10551 | static __be32 * tg3_vpd_readblock(struct tg3 *tp) |
10552 | { | |
10553 | int i; | |
10554 | __be32 *buf; | |
10555 | u32 offset = 0, len = 0; | |
10556 | u32 magic, val; | |
10557 | ||
63c3a66f | 10558 | if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic)) |
c3e94500 MC |
10559 | return NULL; |
10560 | ||
10561 | if (magic == TG3_EEPROM_MAGIC) { | |
10562 | for (offset = TG3_NVM_DIR_START; | |
10563 | offset < TG3_NVM_DIR_END; | |
10564 | offset += TG3_NVM_DIRENT_SIZE) { | |
10565 | if (tg3_nvram_read(tp, offset, &val)) | |
10566 | return NULL; | |
10567 | ||
10568 | if ((val >> TG3_NVM_DIRTYPE_SHIFT) == | |
10569 | TG3_NVM_DIRTYPE_EXTVPD) | |
10570 | break; | |
10571 | } | |
10572 | ||
10573 | if (offset != TG3_NVM_DIR_END) { | |
10574 | len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4; | |
10575 | if (tg3_nvram_read(tp, offset + 4, &offset)) | |
10576 | return NULL; | |
10577 | ||
10578 | offset = tg3_nvram_logical_addr(tp, offset); | |
10579 | } | |
10580 | } | |
10581 | ||
10582 | if (!offset || !len) { | |
10583 | offset = TG3_NVM_VPD_OFF; | |
10584 | len = TG3_NVM_VPD_LEN; | |
10585 | } | |
10586 | ||
10587 | buf = kmalloc(len, GFP_KERNEL); | |
10588 | if (buf == NULL) | |
10589 | return NULL; | |
10590 | ||
10591 | if (magic == TG3_EEPROM_MAGIC) { | |
10592 | for (i = 0; i < len; i += 4) { | |
10593 | /* The data is in little-endian format in NVRAM. | |
10594 | * Use the big-endian read routines to preserve | |
10595 | * the byte order as it exists in NVRAM. | |
10596 | */ | |
10597 | if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4])) | |
10598 | goto error; | |
10599 | } | |
10600 | } else { | |
10601 | u8 *ptr; | |
10602 | ssize_t cnt; | |
10603 | unsigned int pos = 0; | |
10604 | ||
10605 | ptr = (u8 *)&buf[0]; | |
10606 | for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) { | |
10607 | cnt = pci_read_vpd(tp->pdev, pos, | |
10608 | len - pos, ptr); | |
10609 | if (cnt == -ETIMEDOUT || cnt == -EINTR) | |
10610 | cnt = 0; | |
10611 | else if (cnt < 0) | |
10612 | goto error; | |
10613 | } | |
10614 | if (pos != len) | |
10615 | goto error; | |
10616 | } | |
10617 | ||
10618 | return buf; | |
10619 | ||
10620 | error: | |
10621 | kfree(buf); | |
10622 | return NULL; | |
10623 | } | |
10624 | ||
566f86ad | 10625 | #define NVRAM_TEST_SIZE 0x100 |
a5767dec MC |
10626 | #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14 |
10627 | #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18 | |
10628 | #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c | |
727a6d9f MC |
10629 | #define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20 |
10630 | #define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24 | |
10631 | #define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x4c | |
b16250e3 MC |
10632 | #define NVRAM_SELFBOOT_HW_SIZE 0x20 |
10633 | #define NVRAM_SELFBOOT_DATA_SIZE 0x1c | |
566f86ad MC |
10634 | |
10635 | static int tg3_test_nvram(struct tg3 *tp) | |
10636 | { | |
b9fc7dc5 | 10637 | u32 csum, magic; |
a9dc529d | 10638 | __be32 *buf; |
ab0049b4 | 10639 | int i, j, k, err = 0, size; |
566f86ad | 10640 | |
63c3a66f | 10641 | if (tg3_flag(tp, NO_NVRAM)) |
df259d8c MC |
10642 | return 0; |
10643 | ||
e4f34110 | 10644 | if (tg3_nvram_read(tp, 0, &magic) != 0) |
1b27777a MC |
10645 | return -EIO; |
10646 | ||
1b27777a MC |
10647 | if (magic == TG3_EEPROM_MAGIC) |
10648 | size = NVRAM_TEST_SIZE; | |
b16250e3 | 10649 | else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) { |
a5767dec MC |
10650 | if ((magic & TG3_EEPROM_SB_FORMAT_MASK) == |
10651 | TG3_EEPROM_SB_FORMAT_1) { | |
10652 | switch (magic & TG3_EEPROM_SB_REVISION_MASK) { | |
10653 | case TG3_EEPROM_SB_REVISION_0: | |
10654 | size = NVRAM_SELFBOOT_FORMAT1_0_SIZE; | |
10655 | break; | |
10656 | case TG3_EEPROM_SB_REVISION_2: | |
10657 | size = NVRAM_SELFBOOT_FORMAT1_2_SIZE; | |
10658 | break; | |
10659 | case TG3_EEPROM_SB_REVISION_3: | |
10660 | size = NVRAM_SELFBOOT_FORMAT1_3_SIZE; | |
10661 | break; | |
727a6d9f MC |
10662 | case TG3_EEPROM_SB_REVISION_4: |
10663 | size = NVRAM_SELFBOOT_FORMAT1_4_SIZE; | |
10664 | break; | |
10665 | case TG3_EEPROM_SB_REVISION_5: | |
10666 | size = NVRAM_SELFBOOT_FORMAT1_5_SIZE; | |
10667 | break; | |
10668 | case TG3_EEPROM_SB_REVISION_6: | |
10669 | size = NVRAM_SELFBOOT_FORMAT1_6_SIZE; | |
10670 | break; | |
a5767dec | 10671 | default: |
727a6d9f | 10672 | return -EIO; |
a5767dec MC |
10673 | } |
10674 | } else | |
1b27777a | 10675 | return 0; |
b16250e3 MC |
10676 | } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW) |
10677 | size = NVRAM_SELFBOOT_HW_SIZE; | |
10678 | else | |
1b27777a MC |
10679 | return -EIO; |
10680 | ||
10681 | buf = kmalloc(size, GFP_KERNEL); | |
566f86ad MC |
10682 | if (buf == NULL) |
10683 | return -ENOMEM; | |
10684 | ||
1b27777a MC |
10685 | err = -EIO; |
10686 | for (i = 0, j = 0; i < size; i += 4, j++) { | |
a9dc529d MC |
10687 | err = tg3_nvram_read_be32(tp, i, &buf[j]); |
10688 | if (err) | |
566f86ad | 10689 | break; |
566f86ad | 10690 | } |
1b27777a | 10691 | if (i < size) |
566f86ad MC |
10692 | goto out; |
10693 | ||
1b27777a | 10694 | /* Selfboot format */ |
a9dc529d | 10695 | magic = be32_to_cpu(buf[0]); |
b9fc7dc5 | 10696 | if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == |
b16250e3 | 10697 | TG3_EEPROM_MAGIC_FW) { |
1b27777a MC |
10698 | u8 *buf8 = (u8 *) buf, csum8 = 0; |
10699 | ||
b9fc7dc5 | 10700 | if ((magic & TG3_EEPROM_SB_REVISION_MASK) == |
a5767dec MC |
10701 | TG3_EEPROM_SB_REVISION_2) { |
10702 | /* For rev 2, the csum doesn't include the MBA. */ | |
10703 | for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++) | |
10704 | csum8 += buf8[i]; | |
10705 | for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++) | |
10706 | csum8 += buf8[i]; | |
10707 | } else { | |
10708 | for (i = 0; i < size; i++) | |
10709 | csum8 += buf8[i]; | |
10710 | } | |
1b27777a | 10711 | |
ad96b485 AB |
10712 | if (csum8 == 0) { |
10713 | err = 0; | |
10714 | goto out; | |
10715 | } | |
10716 | ||
10717 | err = -EIO; | |
10718 | goto out; | |
1b27777a | 10719 | } |
566f86ad | 10720 | |
b9fc7dc5 | 10721 | if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == |
b16250e3 MC |
10722 | TG3_EEPROM_MAGIC_HW) { |
10723 | u8 data[NVRAM_SELFBOOT_DATA_SIZE]; | |
a9dc529d | 10724 | u8 parity[NVRAM_SELFBOOT_DATA_SIZE]; |
b16250e3 | 10725 | u8 *buf8 = (u8 *) buf; |
b16250e3 MC |
10726 | |
10727 | /* Separate the parity bits and the data bytes. */ | |
10728 | for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) { | |
10729 | if ((i == 0) || (i == 8)) { | |
10730 | int l; | |
10731 | u8 msk; | |
10732 | ||
10733 | for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1) | |
10734 | parity[k++] = buf8[i] & msk; | |
10735 | i++; | |
859a5887 | 10736 | } else if (i == 16) { |
b16250e3 MC |
10737 | int l; |
10738 | u8 msk; | |
10739 | ||
10740 | for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1) | |
10741 | parity[k++] = buf8[i] & msk; | |
10742 | i++; | |
10743 | ||
10744 | for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1) | |
10745 | parity[k++] = buf8[i] & msk; | |
10746 | i++; | |
10747 | } | |
10748 | data[j++] = buf8[i]; | |
10749 | } | |
10750 | ||
10751 | err = -EIO; | |
10752 | for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) { | |
10753 | u8 hw8 = hweight8(data[i]); | |
10754 | ||
10755 | if ((hw8 & 0x1) && parity[i]) | |
10756 | goto out; | |
10757 | else if (!(hw8 & 0x1) && !parity[i]) | |
10758 | goto out; | |
10759 | } | |
10760 | err = 0; | |
10761 | goto out; | |
10762 | } | |
10763 | ||
01c3a392 MC |
10764 | err = -EIO; |
10765 | ||
566f86ad MC |
10766 | /* Bootstrap checksum at offset 0x10 */ |
10767 | csum = calc_crc((unsigned char *) buf, 0x10); | |
01c3a392 | 10768 | if (csum != le32_to_cpu(buf[0x10/4])) |
566f86ad MC |
10769 | goto out; |
10770 | ||
10771 | /* Manufacturing block starts at offset 0x74, checksum at 0xfc */ | |
10772 | csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88); | |
01c3a392 | 10773 | if (csum != le32_to_cpu(buf[0xfc/4])) |
a9dc529d | 10774 | goto out; |
566f86ad | 10775 | |
c3e94500 MC |
10776 | kfree(buf); |
10777 | ||
10778 | buf = tg3_vpd_readblock(tp); | |
10779 | if (!buf) | |
10780 | return -ENOMEM; | |
d4894f3e MC |
10781 | |
10782 | i = pci_vpd_find_tag((u8 *)buf, 0, TG3_NVM_VPD_LEN, | |
10783 | PCI_VPD_LRDT_RO_DATA); | |
10784 | if (i > 0) { | |
10785 | j = pci_vpd_lrdt_size(&((u8 *)buf)[i]); | |
10786 | if (j < 0) | |
10787 | goto out; | |
10788 | ||
10789 | if (i + PCI_VPD_LRDT_TAG_SIZE + j > TG3_NVM_VPD_LEN) | |
10790 | goto out; | |
10791 | ||
10792 | i += PCI_VPD_LRDT_TAG_SIZE; | |
10793 | j = pci_vpd_find_info_keyword((u8 *)buf, i, j, | |
10794 | PCI_VPD_RO_KEYWORD_CHKSUM); | |
10795 | if (j > 0) { | |
10796 | u8 csum8 = 0; | |
10797 | ||
10798 | j += PCI_VPD_INFO_FLD_HDR_SIZE; | |
10799 | ||
10800 | for (i = 0; i <= j; i++) | |
10801 | csum8 += ((u8 *)buf)[i]; | |
10802 | ||
10803 | if (csum8) | |
10804 | goto out; | |
10805 | } | |
10806 | } | |
10807 | ||
566f86ad MC |
10808 | err = 0; |
10809 | ||
10810 | out: | |
10811 | kfree(buf); | |
10812 | return err; | |
10813 | } | |
10814 | ||
ca43007a MC |
10815 | #define TG3_SERDES_TIMEOUT_SEC 2 |
10816 | #define TG3_COPPER_TIMEOUT_SEC 6 | |
10817 | ||
10818 | static int tg3_test_link(struct tg3 *tp) | |
10819 | { | |
10820 | int i, max; | |
10821 | ||
10822 | if (!netif_running(tp->dev)) | |
10823 | return -ENODEV; | |
10824 | ||
f07e9af3 | 10825 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) |
ca43007a MC |
10826 | max = TG3_SERDES_TIMEOUT_SEC; |
10827 | else | |
10828 | max = TG3_COPPER_TIMEOUT_SEC; | |
10829 | ||
10830 | for (i = 0; i < max; i++) { | |
10831 | if (netif_carrier_ok(tp->dev)) | |
10832 | return 0; | |
10833 | ||
10834 | if (msleep_interruptible(1000)) | |
10835 | break; | |
10836 | } | |
10837 | ||
10838 | return -EIO; | |
10839 | } | |
10840 | ||
a71116d1 | 10841 | /* Only test the commonly used registers */ |
30ca3e37 | 10842 | static int tg3_test_registers(struct tg3 *tp) |
a71116d1 | 10843 | { |
b16250e3 | 10844 | int i, is_5705, is_5750; |
a71116d1 MC |
10845 | u32 offset, read_mask, write_mask, val, save_val, read_val; |
10846 | static struct { | |
10847 | u16 offset; | |
10848 | u16 flags; | |
10849 | #define TG3_FL_5705 0x1 | |
10850 | #define TG3_FL_NOT_5705 0x2 | |
10851 | #define TG3_FL_NOT_5788 0x4 | |
b16250e3 | 10852 | #define TG3_FL_NOT_5750 0x8 |
a71116d1 MC |
10853 | u32 read_mask; |
10854 | u32 write_mask; | |
10855 | } reg_tbl[] = { | |
10856 | /* MAC Control Registers */ | |
10857 | { MAC_MODE, TG3_FL_NOT_5705, | |
10858 | 0x00000000, 0x00ef6f8c }, | |
10859 | { MAC_MODE, TG3_FL_5705, | |
10860 | 0x00000000, 0x01ef6b8c }, | |
10861 | { MAC_STATUS, TG3_FL_NOT_5705, | |
10862 | 0x03800107, 0x00000000 }, | |
10863 | { MAC_STATUS, TG3_FL_5705, | |
10864 | 0x03800100, 0x00000000 }, | |
10865 | { MAC_ADDR_0_HIGH, 0x0000, | |
10866 | 0x00000000, 0x0000ffff }, | |
10867 | { MAC_ADDR_0_LOW, 0x0000, | |
c6cdf436 | 10868 | 0x00000000, 0xffffffff }, |
a71116d1 MC |
10869 | { MAC_RX_MTU_SIZE, 0x0000, |
10870 | 0x00000000, 0x0000ffff }, | |
10871 | { MAC_TX_MODE, 0x0000, | |
10872 | 0x00000000, 0x00000070 }, | |
10873 | { MAC_TX_LENGTHS, 0x0000, | |
10874 | 0x00000000, 0x00003fff }, | |
10875 | { MAC_RX_MODE, TG3_FL_NOT_5705, | |
10876 | 0x00000000, 0x000007fc }, | |
10877 | { MAC_RX_MODE, TG3_FL_5705, | |
10878 | 0x00000000, 0x000007dc }, | |
10879 | { MAC_HASH_REG_0, 0x0000, | |
10880 | 0x00000000, 0xffffffff }, | |
10881 | { MAC_HASH_REG_1, 0x0000, | |
10882 | 0x00000000, 0xffffffff }, | |
10883 | { MAC_HASH_REG_2, 0x0000, | |
10884 | 0x00000000, 0xffffffff }, | |
10885 | { MAC_HASH_REG_3, 0x0000, | |
10886 | 0x00000000, 0xffffffff }, | |
10887 | ||
10888 | /* Receive Data and Receive BD Initiator Control Registers. */ | |
10889 | { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705, | |
10890 | 0x00000000, 0xffffffff }, | |
10891 | { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705, | |
10892 | 0x00000000, 0xffffffff }, | |
10893 | { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705, | |
10894 | 0x00000000, 0x00000003 }, | |
10895 | { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705, | |
10896 | 0x00000000, 0xffffffff }, | |
10897 | { RCVDBDI_STD_BD+0, 0x0000, | |
10898 | 0x00000000, 0xffffffff }, | |
10899 | { RCVDBDI_STD_BD+4, 0x0000, | |
10900 | 0x00000000, 0xffffffff }, | |
10901 | { RCVDBDI_STD_BD+8, 0x0000, | |
10902 | 0x00000000, 0xffff0002 }, | |
10903 | { RCVDBDI_STD_BD+0xc, 0x0000, | |
10904 | 0x00000000, 0xffffffff }, | |
6aa20a22 | 10905 | |
a71116d1 MC |
10906 | /* Receive BD Initiator Control Registers. */ |
10907 | { RCVBDI_STD_THRESH, TG3_FL_NOT_5705, | |
10908 | 0x00000000, 0xffffffff }, | |
10909 | { RCVBDI_STD_THRESH, TG3_FL_5705, | |
10910 | 0x00000000, 0x000003ff }, | |
10911 | { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705, | |
10912 | 0x00000000, 0xffffffff }, | |
6aa20a22 | 10913 | |
a71116d1 MC |
10914 | /* Host Coalescing Control Registers. */ |
10915 | { HOSTCC_MODE, TG3_FL_NOT_5705, | |
10916 | 0x00000000, 0x00000004 }, | |
10917 | { HOSTCC_MODE, TG3_FL_5705, | |
10918 | 0x00000000, 0x000000f6 }, | |
10919 | { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705, | |
10920 | 0x00000000, 0xffffffff }, | |
10921 | { HOSTCC_RXCOL_TICKS, TG3_FL_5705, | |
10922 | 0x00000000, 0x000003ff }, | |
10923 | { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705, | |
10924 | 0x00000000, 0xffffffff }, | |
10925 | { HOSTCC_TXCOL_TICKS, TG3_FL_5705, | |
10926 | 0x00000000, 0x000003ff }, | |
10927 | { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705, | |
10928 | 0x00000000, 0xffffffff }, | |
10929 | { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788, | |
10930 | 0x00000000, 0x000000ff }, | |
10931 | { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705, | |
10932 | 0x00000000, 0xffffffff }, | |
10933 | { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788, | |
10934 | 0x00000000, 0x000000ff }, | |
10935 | { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705, | |
10936 | 0x00000000, 0xffffffff }, | |
10937 | { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705, | |
10938 | 0x00000000, 0xffffffff }, | |
10939 | { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705, | |
10940 | 0x00000000, 0xffffffff }, | |
10941 | { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788, | |
10942 | 0x00000000, 0x000000ff }, | |
10943 | { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705, | |
10944 | 0x00000000, 0xffffffff }, | |
10945 | { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788, | |
10946 | 0x00000000, 0x000000ff }, | |
10947 | { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705, | |
10948 | 0x00000000, 0xffffffff }, | |
10949 | { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705, | |
10950 | 0x00000000, 0xffffffff }, | |
10951 | { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705, | |
10952 | 0x00000000, 0xffffffff }, | |
10953 | { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000, | |
10954 | 0x00000000, 0xffffffff }, | |
10955 | { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000, | |
10956 | 0x00000000, 0xffffffff }, | |
10957 | { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000, | |
10958 | 0xffffffff, 0x00000000 }, | |
10959 | { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000, | |
10960 | 0xffffffff, 0x00000000 }, | |
10961 | ||
10962 | /* Buffer Manager Control Registers. */ | |
b16250e3 | 10963 | { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750, |
a71116d1 | 10964 | 0x00000000, 0x007fff80 }, |
b16250e3 | 10965 | { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750, |
a71116d1 MC |
10966 | 0x00000000, 0x007fffff }, |
10967 | { BUFMGR_MB_RDMA_LOW_WATER, 0x0000, | |
10968 | 0x00000000, 0x0000003f }, | |
10969 | { BUFMGR_MB_MACRX_LOW_WATER, 0x0000, | |
10970 | 0x00000000, 0x000001ff }, | |
10971 | { BUFMGR_MB_HIGH_WATER, 0x0000, | |
10972 | 0x00000000, 0x000001ff }, | |
10973 | { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705, | |
10974 | 0xffffffff, 0x00000000 }, | |
10975 | { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705, | |
10976 | 0xffffffff, 0x00000000 }, | |
6aa20a22 | 10977 | |
a71116d1 MC |
10978 | /* Mailbox Registers */ |
10979 | { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000, | |
10980 | 0x00000000, 0x000001ff }, | |
10981 | { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705, | |
10982 | 0x00000000, 0x000001ff }, | |
10983 | { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000, | |
10984 | 0x00000000, 0x000007ff }, | |
10985 | { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000, | |
10986 | 0x00000000, 0x000001ff }, | |
10987 | ||
10988 | { 0xffff, 0x0000, 0x00000000, 0x00000000 }, | |
10989 | }; | |
10990 | ||
b16250e3 | 10991 | is_5705 = is_5750 = 0; |
63c3a66f | 10992 | if (tg3_flag(tp, 5705_PLUS)) { |
a71116d1 | 10993 | is_5705 = 1; |
63c3a66f | 10994 | if (tg3_flag(tp, 5750_PLUS)) |
b16250e3 MC |
10995 | is_5750 = 1; |
10996 | } | |
a71116d1 MC |
10997 | |
10998 | for (i = 0; reg_tbl[i].offset != 0xffff; i++) { | |
10999 | if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705)) | |
11000 | continue; | |
11001 | ||
11002 | if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705)) | |
11003 | continue; | |
11004 | ||
63c3a66f | 11005 | if (tg3_flag(tp, IS_5788) && |
a71116d1 MC |
11006 | (reg_tbl[i].flags & TG3_FL_NOT_5788)) |
11007 | continue; | |
11008 | ||
b16250e3 MC |
11009 | if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750)) |
11010 | continue; | |
11011 | ||
a71116d1 MC |
11012 | offset = (u32) reg_tbl[i].offset; |
11013 | read_mask = reg_tbl[i].read_mask; | |
11014 | write_mask = reg_tbl[i].write_mask; | |
11015 | ||
11016 | /* Save the original register content */ | |
11017 | save_val = tr32(offset); | |
11018 | ||
11019 | /* Determine the read-only value. */ | |
11020 | read_val = save_val & read_mask; | |
11021 | ||
11022 | /* Write zero to the register, then make sure the read-only bits | |
11023 | * are not changed and the read/write bits are all zeros. | |
11024 | */ | |
11025 | tw32(offset, 0); | |
11026 | ||
11027 | val = tr32(offset); | |
11028 | ||
11029 | /* Test the read-only and read/write bits. */ | |
11030 | if (((val & read_mask) != read_val) || (val & write_mask)) | |
11031 | goto out; | |
11032 | ||
11033 | /* Write ones to all the bits defined by RdMask and WrMask, then | |
11034 | * make sure the read-only bits are not changed and the | |
11035 | * read/write bits are all ones. | |
11036 | */ | |
11037 | tw32(offset, read_mask | write_mask); | |
11038 | ||
11039 | val = tr32(offset); | |
11040 | ||
11041 | /* Test the read-only bits. */ | |
11042 | if ((val & read_mask) != read_val) | |
11043 | goto out; | |
11044 | ||
11045 | /* Test the read/write bits. */ | |
11046 | if ((val & write_mask) != write_mask) | |
11047 | goto out; | |
11048 | ||
11049 | tw32(offset, save_val); | |
11050 | } | |
11051 | ||
11052 | return 0; | |
11053 | ||
11054 | out: | |
9f88f29f | 11055 | if (netif_msg_hw(tp)) |
2445e461 MC |
11056 | netdev_err(tp->dev, |
11057 | "Register test failed at offset %x\n", offset); | |
a71116d1 MC |
11058 | tw32(offset, save_val); |
11059 | return -EIO; | |
11060 | } | |
11061 | ||
7942e1db MC |
11062 | static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len) |
11063 | { | |
f71e1309 | 11064 | static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a }; |
7942e1db MC |
11065 | int i; |
11066 | u32 j; | |
11067 | ||
e9edda69 | 11068 | for (i = 0; i < ARRAY_SIZE(test_pattern); i++) { |
7942e1db MC |
11069 | for (j = 0; j < len; j += 4) { |
11070 | u32 val; | |
11071 | ||
11072 | tg3_write_mem(tp, offset + j, test_pattern[i]); | |
11073 | tg3_read_mem(tp, offset + j, &val); | |
11074 | if (val != test_pattern[i]) | |
11075 | return -EIO; | |
11076 | } | |
11077 | } | |
11078 | return 0; | |
11079 | } | |
11080 | ||
11081 | static int tg3_test_memory(struct tg3 *tp) | |
11082 | { | |
11083 | static struct mem_entry { | |
11084 | u32 offset; | |
11085 | u32 len; | |
11086 | } mem_tbl_570x[] = { | |
38690194 | 11087 | { 0x00000000, 0x00b50}, |
7942e1db MC |
11088 | { 0x00002000, 0x1c000}, |
11089 | { 0xffffffff, 0x00000} | |
11090 | }, mem_tbl_5705[] = { | |
11091 | { 0x00000100, 0x0000c}, | |
11092 | { 0x00000200, 0x00008}, | |
7942e1db MC |
11093 | { 0x00004000, 0x00800}, |
11094 | { 0x00006000, 0x01000}, | |
11095 | { 0x00008000, 0x02000}, | |
11096 | { 0x00010000, 0x0e000}, | |
11097 | { 0xffffffff, 0x00000} | |
79f4d13a MC |
11098 | }, mem_tbl_5755[] = { |
11099 | { 0x00000200, 0x00008}, | |
11100 | { 0x00004000, 0x00800}, | |
11101 | { 0x00006000, 0x00800}, | |
11102 | { 0x00008000, 0x02000}, | |
11103 | { 0x00010000, 0x0c000}, | |
11104 | { 0xffffffff, 0x00000} | |
b16250e3 MC |
11105 | }, mem_tbl_5906[] = { |
11106 | { 0x00000200, 0x00008}, | |
11107 | { 0x00004000, 0x00400}, | |
11108 | { 0x00006000, 0x00400}, | |
11109 | { 0x00008000, 0x01000}, | |
11110 | { 0x00010000, 0x01000}, | |
11111 | { 0xffffffff, 0x00000} | |
8b5a6c42 MC |
11112 | }, mem_tbl_5717[] = { |
11113 | { 0x00000200, 0x00008}, | |
11114 | { 0x00010000, 0x0a000}, | |
11115 | { 0x00020000, 0x13c00}, | |
11116 | { 0xffffffff, 0x00000} | |
11117 | }, mem_tbl_57765[] = { | |
11118 | { 0x00000200, 0x00008}, | |
11119 | { 0x00004000, 0x00800}, | |
11120 | { 0x00006000, 0x09800}, | |
11121 | { 0x00010000, 0x0a000}, | |
11122 | { 0xffffffff, 0x00000} | |
7942e1db MC |
11123 | }; |
11124 | struct mem_entry *mem_tbl; | |
11125 | int err = 0; | |
11126 | int i; | |
11127 | ||
63c3a66f | 11128 | if (tg3_flag(tp, 5717_PLUS)) |
8b5a6c42 MC |
11129 | mem_tbl = mem_tbl_5717; |
11130 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
11131 | mem_tbl = mem_tbl_57765; | |
63c3a66f | 11132 | else if (tg3_flag(tp, 5755_PLUS)) |
321d32a0 MC |
11133 | mem_tbl = mem_tbl_5755; |
11134 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
11135 | mem_tbl = mem_tbl_5906; | |
63c3a66f | 11136 | else if (tg3_flag(tp, 5705_PLUS)) |
321d32a0 MC |
11137 | mem_tbl = mem_tbl_5705; |
11138 | else | |
7942e1db MC |
11139 | mem_tbl = mem_tbl_570x; |
11140 | ||
11141 | for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) { | |
be98da6a MC |
11142 | err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len); |
11143 | if (err) | |
7942e1db MC |
11144 | break; |
11145 | } | |
6aa20a22 | 11146 | |
7942e1db MC |
11147 | return err; |
11148 | } | |
11149 | ||
9f40dead MC |
11150 | #define TG3_MAC_LOOPBACK 0 |
11151 | #define TG3_PHY_LOOPBACK 1 | |
bb158d69 MC |
11152 | #define TG3_TSO_LOOPBACK 2 |
11153 | ||
11154 | #define TG3_TSO_MSS 500 | |
11155 | ||
11156 | #define TG3_TSO_IP_HDR_LEN 20 | |
11157 | #define TG3_TSO_TCP_HDR_LEN 20 | |
11158 | #define TG3_TSO_TCP_OPT_LEN 12 | |
11159 | ||
11160 | static const u8 tg3_tso_header[] = { | |
11161 | 0x08, 0x00, | |
11162 | 0x45, 0x00, 0x00, 0x00, | |
11163 | 0x00, 0x00, 0x40, 0x00, | |
11164 | 0x40, 0x06, 0x00, 0x00, | |
11165 | 0x0a, 0x00, 0x00, 0x01, | |
11166 | 0x0a, 0x00, 0x00, 0x02, | |
11167 | 0x0d, 0x00, 0xe0, 0x00, | |
11168 | 0x00, 0x00, 0x01, 0x00, | |
11169 | 0x00, 0x00, 0x02, 0x00, | |
11170 | 0x80, 0x10, 0x10, 0x00, | |
11171 | 0x14, 0x09, 0x00, 0x00, | |
11172 | 0x01, 0x01, 0x08, 0x0a, | |
11173 | 0x11, 0x11, 0x11, 0x11, | |
11174 | 0x11, 0x11, 0x11, 0x11, | |
11175 | }; | |
9f40dead | 11176 | |
4852a861 | 11177 | static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, int loopback_mode) |
c76949a6 | 11178 | { |
9f40dead | 11179 | u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key; |
bb158d69 | 11180 | u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val; |
c76949a6 MC |
11181 | struct sk_buff *skb, *rx_skb; |
11182 | u8 *tx_data; | |
11183 | dma_addr_t map; | |
11184 | int num_pkts, tx_len, rx_len, i, err; | |
11185 | struct tg3_rx_buffer_desc *desc; | |
898a56f8 | 11186 | struct tg3_napi *tnapi, *rnapi; |
8fea32b9 | 11187 | struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; |
c76949a6 | 11188 | |
c8873405 MC |
11189 | tnapi = &tp->napi[0]; |
11190 | rnapi = &tp->napi[0]; | |
0c1d0e2b | 11191 | if (tp->irq_cnt > 1) { |
63c3a66f | 11192 | if (tg3_flag(tp, ENABLE_RSS)) |
1da85aa3 | 11193 | rnapi = &tp->napi[1]; |
63c3a66f | 11194 | if (tg3_flag(tp, ENABLE_TSS)) |
c8873405 | 11195 | tnapi = &tp->napi[1]; |
0c1d0e2b | 11196 | } |
fd2ce37f | 11197 | coal_now = tnapi->coal_now | rnapi->coal_now; |
898a56f8 | 11198 | |
9f40dead | 11199 | if (loopback_mode == TG3_MAC_LOOPBACK) { |
c94e3941 MC |
11200 | /* HW errata - mac loopback fails in some cases on 5780. |
11201 | * Normal traffic and PHY loopback are not affected by | |
aba49f24 MC |
11202 | * errata. Also, the MAC loopback test is deprecated for |
11203 | * all newer ASIC revisions. | |
c94e3941 | 11204 | */ |
aba49f24 | 11205 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 || |
63c3a66f | 11206 | tg3_flag(tp, CPMU_PRESENT)) |
c94e3941 MC |
11207 | return 0; |
11208 | ||
49692ca1 MC |
11209 | mac_mode = tp->mac_mode & |
11210 | ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); | |
11211 | mac_mode |= MAC_MODE_PORT_INT_LPBACK; | |
63c3a66f | 11212 | if (!tg3_flag(tp, 5705_PLUS)) |
e8f3f6ca | 11213 | mac_mode |= MAC_MODE_LINK_POLARITY; |
f07e9af3 | 11214 | if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) |
3f7045c1 MC |
11215 | mac_mode |= MAC_MODE_PORT_MODE_MII; |
11216 | else | |
11217 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
9f40dead | 11218 | tw32(MAC_MODE, mac_mode); |
bb158d69 | 11219 | } else { |
f07e9af3 | 11220 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
7f97a4bd | 11221 | tg3_phy_fet_toggle_apd(tp, false); |
5d64ad34 MC |
11222 | val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100; |
11223 | } else | |
11224 | val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000; | |
3f7045c1 | 11225 | |
9ef8ca99 MC |
11226 | tg3_phy_toggle_automdix(tp, 0); |
11227 | ||
3f7045c1 | 11228 | tg3_writephy(tp, MII_BMCR, val); |
c94e3941 | 11229 | udelay(40); |
5d64ad34 | 11230 | |
49692ca1 MC |
11231 | mac_mode = tp->mac_mode & |
11232 | ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); | |
f07e9af3 | 11233 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
1061b7c5 MC |
11234 | tg3_writephy(tp, MII_TG3_FET_PTEST, |
11235 | MII_TG3_FET_PTEST_FRC_TX_LINK | | |
11236 | MII_TG3_FET_PTEST_FRC_TX_LOCK); | |
11237 | /* The write needs to be flushed for the AC131 */ | |
11238 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
11239 | tg3_readphy(tp, MII_TG3_FET_PTEST, &val); | |
5d64ad34 MC |
11240 | mac_mode |= MAC_MODE_PORT_MODE_MII; |
11241 | } else | |
11242 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
b16250e3 | 11243 | |
c94e3941 | 11244 | /* reset to prevent losing 1st rx packet intermittently */ |
f07e9af3 | 11245 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { |
c94e3941 MC |
11246 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); |
11247 | udelay(10); | |
11248 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
11249 | } | |
e8f3f6ca | 11250 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) { |
79eb6904 MC |
11251 | u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK; |
11252 | if (masked_phy_id == TG3_PHY_ID_BCM5401) | |
e8f3f6ca | 11253 | mac_mode &= ~MAC_MODE_LINK_POLARITY; |
79eb6904 | 11254 | else if (masked_phy_id == TG3_PHY_ID_BCM5411) |
e8f3f6ca | 11255 | mac_mode |= MAC_MODE_LINK_POLARITY; |
ff18ff02 MC |
11256 | tg3_writephy(tp, MII_TG3_EXT_CTRL, |
11257 | MII_TG3_EXT_CTRL_LNK3_LED_MODE); | |
11258 | } | |
9f40dead | 11259 | tw32(MAC_MODE, mac_mode); |
49692ca1 MC |
11260 | |
11261 | /* Wait for link */ | |
11262 | for (i = 0; i < 100; i++) { | |
11263 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) | |
11264 | break; | |
11265 | mdelay(1); | |
11266 | } | |
859a5887 | 11267 | } |
c76949a6 MC |
11268 | |
11269 | err = -EIO; | |
11270 | ||
4852a861 | 11271 | tx_len = pktsz; |
a20e9c62 | 11272 | skb = netdev_alloc_skb(tp->dev, tx_len); |
a50bb7b9 JJ |
11273 | if (!skb) |
11274 | return -ENOMEM; | |
11275 | ||
c76949a6 MC |
11276 | tx_data = skb_put(skb, tx_len); |
11277 | memcpy(tx_data, tp->dev->dev_addr, 6); | |
11278 | memset(tx_data + 6, 0x0, 8); | |
11279 | ||
4852a861 | 11280 | tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN); |
c76949a6 | 11281 | |
bb158d69 MC |
11282 | if (loopback_mode == TG3_TSO_LOOPBACK) { |
11283 | struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN]; | |
11284 | ||
11285 | u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN + | |
11286 | TG3_TSO_TCP_OPT_LEN; | |
11287 | ||
11288 | memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header, | |
11289 | sizeof(tg3_tso_header)); | |
11290 | mss = TG3_TSO_MSS; | |
11291 | ||
11292 | val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header); | |
11293 | num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS); | |
11294 | ||
11295 | /* Set the total length field in the IP header */ | |
11296 | iph->tot_len = htons((u16)(mss + hdr_len)); | |
11297 | ||
11298 | base_flags = (TXD_FLAG_CPU_PRE_DMA | | |
11299 | TXD_FLAG_CPU_POST_DMA); | |
11300 | ||
63c3a66f JP |
11301 | if (tg3_flag(tp, HW_TSO_1) || |
11302 | tg3_flag(tp, HW_TSO_2) || | |
11303 | tg3_flag(tp, HW_TSO_3)) { | |
bb158d69 MC |
11304 | struct tcphdr *th; |
11305 | val = ETH_HLEN + TG3_TSO_IP_HDR_LEN; | |
11306 | th = (struct tcphdr *)&tx_data[val]; | |
11307 | th->check = 0; | |
11308 | } else | |
11309 | base_flags |= TXD_FLAG_TCPUDP_CSUM; | |
11310 | ||
63c3a66f | 11311 | if (tg3_flag(tp, HW_TSO_3)) { |
bb158d69 MC |
11312 | mss |= (hdr_len & 0xc) << 12; |
11313 | if (hdr_len & 0x10) | |
11314 | base_flags |= 0x00000010; | |
11315 | base_flags |= (hdr_len & 0x3e0) << 5; | |
63c3a66f | 11316 | } else if (tg3_flag(tp, HW_TSO_2)) |
bb158d69 | 11317 | mss |= hdr_len << 9; |
63c3a66f | 11318 | else if (tg3_flag(tp, HW_TSO_1) || |
bb158d69 MC |
11319 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { |
11320 | mss |= (TG3_TSO_TCP_OPT_LEN << 9); | |
11321 | } else { | |
11322 | base_flags |= (TG3_TSO_TCP_OPT_LEN << 10); | |
11323 | } | |
11324 | ||
11325 | data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header); | |
11326 | } else { | |
11327 | num_pkts = 1; | |
11328 | data_off = ETH_HLEN; | |
11329 | } | |
11330 | ||
11331 | for (i = data_off; i < tx_len; i++) | |
c76949a6 MC |
11332 | tx_data[i] = (u8) (i & 0xff); |
11333 | ||
f4188d8a AD |
11334 | map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE); |
11335 | if (pci_dma_mapping_error(tp->pdev, map)) { | |
a21771dd MC |
11336 | dev_kfree_skb(skb); |
11337 | return -EIO; | |
11338 | } | |
c76949a6 MC |
11339 | |
11340 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | | |
fd2ce37f | 11341 | rnapi->coal_now); |
c76949a6 MC |
11342 | |
11343 | udelay(10); | |
11344 | ||
898a56f8 | 11345 | rx_start_idx = rnapi->hw_status->idx[0].rx_producer; |
c76949a6 | 11346 | |
bb158d69 MC |
11347 | tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, |
11348 | base_flags, (mss << 1) | 1); | |
c76949a6 | 11349 | |
f3f3f27e | 11350 | tnapi->tx_prod++; |
c76949a6 | 11351 | |
f3f3f27e MC |
11352 | tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod); |
11353 | tr32_mailbox(tnapi->prodmbox); | |
c76949a6 MC |
11354 | |
11355 | udelay(10); | |
11356 | ||
303fc921 MC |
11357 | /* 350 usec to allow enough time on some 10/100 Mbps devices. */ |
11358 | for (i = 0; i < 35; i++) { | |
c76949a6 | 11359 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | |
fd2ce37f | 11360 | coal_now); |
c76949a6 MC |
11361 | |
11362 | udelay(10); | |
11363 | ||
898a56f8 MC |
11364 | tx_idx = tnapi->hw_status->idx[0].tx_consumer; |
11365 | rx_idx = rnapi->hw_status->idx[0].rx_producer; | |
f3f3f27e | 11366 | if ((tx_idx == tnapi->tx_prod) && |
c76949a6 MC |
11367 | (rx_idx == (rx_start_idx + num_pkts))) |
11368 | break; | |
11369 | } | |
11370 | ||
f4188d8a | 11371 | pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE); |
c76949a6 MC |
11372 | dev_kfree_skb(skb); |
11373 | ||
f3f3f27e | 11374 | if (tx_idx != tnapi->tx_prod) |
c76949a6 MC |
11375 | goto out; |
11376 | ||
11377 | if (rx_idx != rx_start_idx + num_pkts) | |
11378 | goto out; | |
11379 | ||
bb158d69 MC |
11380 | val = data_off; |
11381 | while (rx_idx != rx_start_idx) { | |
11382 | desc = &rnapi->rx_rcb[rx_start_idx++]; | |
11383 | desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; | |
11384 | opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; | |
c76949a6 | 11385 | |
bb158d69 MC |
11386 | if ((desc->err_vlan & RXD_ERR_MASK) != 0 && |
11387 | (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) | |
11388 | goto out; | |
c76949a6 | 11389 | |
bb158d69 MC |
11390 | rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) |
11391 | - ETH_FCS_LEN; | |
c76949a6 | 11392 | |
bb158d69 MC |
11393 | if (loopback_mode != TG3_TSO_LOOPBACK) { |
11394 | if (rx_len != tx_len) | |
11395 | goto out; | |
4852a861 | 11396 | |
bb158d69 MC |
11397 | if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) { |
11398 | if (opaque_key != RXD_OPAQUE_RING_STD) | |
11399 | goto out; | |
11400 | } else { | |
11401 | if (opaque_key != RXD_OPAQUE_RING_JUMBO) | |
11402 | goto out; | |
11403 | } | |
11404 | } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) && | |
11405 | (desc->ip_tcp_csum & RXD_TCPCSUM_MASK) | |
54e0a67f | 11406 | >> RXD_TCPCSUM_SHIFT != 0xffff) { |
4852a861 | 11407 | goto out; |
bb158d69 | 11408 | } |
4852a861 | 11409 | |
bb158d69 MC |
11410 | if (opaque_key == RXD_OPAQUE_RING_STD) { |
11411 | rx_skb = tpr->rx_std_buffers[desc_idx].skb; | |
11412 | map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], | |
11413 | mapping); | |
11414 | } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) { | |
11415 | rx_skb = tpr->rx_jmb_buffers[desc_idx].skb; | |
11416 | map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx], | |
11417 | mapping); | |
11418 | } else | |
11419 | goto out; | |
c76949a6 | 11420 | |
bb158d69 MC |
11421 | pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, |
11422 | PCI_DMA_FROMDEVICE); | |
c76949a6 | 11423 | |
bb158d69 MC |
11424 | for (i = data_off; i < rx_len; i++, val++) { |
11425 | if (*(rx_skb->data + i) != (u8) (val & 0xff)) | |
11426 | goto out; | |
11427 | } | |
c76949a6 | 11428 | } |
bb158d69 | 11429 | |
c76949a6 | 11430 | err = 0; |
6aa20a22 | 11431 | |
c76949a6 MC |
11432 | /* tg3_free_rings will unmap and free the rx_skb */ |
11433 | out: | |
11434 | return err; | |
11435 | } | |
11436 | ||
00c266b7 MC |
11437 | #define TG3_STD_LOOPBACK_FAILED 1 |
11438 | #define TG3_JMB_LOOPBACK_FAILED 2 | |
bb158d69 | 11439 | #define TG3_TSO_LOOPBACK_FAILED 4 |
00c266b7 MC |
11440 | |
11441 | #define TG3_MAC_LOOPBACK_SHIFT 0 | |
11442 | #define TG3_PHY_LOOPBACK_SHIFT 4 | |
bb158d69 | 11443 | #define TG3_LOOPBACK_FAILED 0x00000077 |
9f40dead MC |
11444 | |
11445 | static int tg3_test_loopback(struct tg3 *tp) | |
11446 | { | |
11447 | int err = 0; | |
ab789046 | 11448 | u32 eee_cap, cpmuctrl = 0; |
9f40dead MC |
11449 | |
11450 | if (!netif_running(tp->dev)) | |
11451 | return TG3_LOOPBACK_FAILED; | |
11452 | ||
ab789046 MC |
11453 | eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP; |
11454 | tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP; | |
11455 | ||
b9ec6c1b | 11456 | err = tg3_reset_hw(tp, 1); |
ab789046 MC |
11457 | if (err) { |
11458 | err = TG3_LOOPBACK_FAILED; | |
11459 | goto done; | |
11460 | } | |
9f40dead | 11461 | |
63c3a66f | 11462 | if (tg3_flag(tp, ENABLE_RSS)) { |
4a85f098 MC |
11463 | int i; |
11464 | ||
11465 | /* Reroute all rx packets to the 1st queue */ | |
11466 | for (i = MAC_RSS_INDIR_TBL_0; | |
11467 | i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4) | |
11468 | tw32(i, 0x0); | |
11469 | } | |
11470 | ||
6833c043 | 11471 | /* Turn off gphy autopowerdown. */ |
f07e9af3 | 11472 | if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) |
6833c043 MC |
11473 | tg3_phy_toggle_apd(tp, false); |
11474 | ||
63c3a66f | 11475 | if (tg3_flag(tp, CPMU_PRESENT)) { |
9936bcf6 MC |
11476 | int i; |
11477 | u32 status; | |
11478 | ||
11479 | tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER); | |
11480 | ||
11481 | /* Wait for up to 40 microseconds to acquire lock. */ | |
11482 | for (i = 0; i < 4; i++) { | |
11483 | status = tr32(TG3_CPMU_MUTEX_GNT); | |
11484 | if (status == CPMU_MUTEX_GNT_DRIVER) | |
11485 | break; | |
11486 | udelay(10); | |
11487 | } | |
11488 | ||
ab789046 MC |
11489 | if (status != CPMU_MUTEX_GNT_DRIVER) { |
11490 | err = TG3_LOOPBACK_FAILED; | |
11491 | goto done; | |
11492 | } | |
9936bcf6 | 11493 | |
b2a5c19c | 11494 | /* Turn off link-based power management. */ |
e875093c | 11495 | cpmuctrl = tr32(TG3_CPMU_CTRL); |
109115e1 MC |
11496 | tw32(TG3_CPMU_CTRL, |
11497 | cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE | | |
11498 | CPMU_CTRL_LINK_AWARE_MODE)); | |
9936bcf6 MC |
11499 | } |
11500 | ||
4852a861 | 11501 | if (tg3_run_loopback(tp, ETH_FRAME_LEN, TG3_MAC_LOOPBACK)) |
00c266b7 | 11502 | err |= TG3_STD_LOOPBACK_FAILED << TG3_MAC_LOOPBACK_SHIFT; |
9936bcf6 | 11503 | |
63c3a66f | 11504 | if (tg3_flag(tp, JUMBO_RING_ENABLE) && |
4852a861 | 11505 | tg3_run_loopback(tp, 9000 + ETH_HLEN, TG3_MAC_LOOPBACK)) |
00c266b7 | 11506 | err |= TG3_JMB_LOOPBACK_FAILED << TG3_MAC_LOOPBACK_SHIFT; |
4852a861 | 11507 | |
63c3a66f | 11508 | if (tg3_flag(tp, CPMU_PRESENT)) { |
9936bcf6 MC |
11509 | tw32(TG3_CPMU_CTRL, cpmuctrl); |
11510 | ||
11511 | /* Release the mutex */ | |
11512 | tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER); | |
11513 | } | |
11514 | ||
f07e9af3 | 11515 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
63c3a66f | 11516 | !tg3_flag(tp, USE_PHYLIB)) { |
4852a861 | 11517 | if (tg3_run_loopback(tp, ETH_FRAME_LEN, TG3_PHY_LOOPBACK)) |
00c266b7 MC |
11518 | err |= TG3_STD_LOOPBACK_FAILED << |
11519 | TG3_PHY_LOOPBACK_SHIFT; | |
63c3a66f | 11520 | if (tg3_flag(tp, TSO_CAPABLE) && |
bb158d69 MC |
11521 | tg3_run_loopback(tp, ETH_FRAME_LEN, TG3_TSO_LOOPBACK)) |
11522 | err |= TG3_TSO_LOOPBACK_FAILED << | |
11523 | TG3_PHY_LOOPBACK_SHIFT; | |
63c3a66f | 11524 | if (tg3_flag(tp, JUMBO_RING_ENABLE) && |
4852a861 | 11525 | tg3_run_loopback(tp, 9000 + ETH_HLEN, TG3_PHY_LOOPBACK)) |
00c266b7 MC |
11526 | err |= TG3_JMB_LOOPBACK_FAILED << |
11527 | TG3_PHY_LOOPBACK_SHIFT; | |
9f40dead MC |
11528 | } |
11529 | ||
6833c043 | 11530 | /* Re-enable gphy autopowerdown. */ |
f07e9af3 | 11531 | if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) |
6833c043 MC |
11532 | tg3_phy_toggle_apd(tp, true); |
11533 | ||
ab789046 MC |
11534 | done: |
11535 | tp->phy_flags |= eee_cap; | |
11536 | ||
9f40dead MC |
11537 | return err; |
11538 | } | |
11539 | ||
4cafd3f5 MC |
11540 | static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest, |
11541 | u64 *data) | |
11542 | { | |
566f86ad MC |
11543 | struct tg3 *tp = netdev_priv(dev); |
11544 | ||
bed9829f MC |
11545 | if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) && |
11546 | tg3_power_up(tp)) { | |
11547 | etest->flags |= ETH_TEST_FL_FAILED; | |
11548 | memset(data, 1, sizeof(u64) * TG3_NUM_TEST); | |
11549 | return; | |
11550 | } | |
bc1c7567 | 11551 | |
566f86ad MC |
11552 | memset(data, 0, sizeof(u64) * TG3_NUM_TEST); |
11553 | ||
11554 | if (tg3_test_nvram(tp) != 0) { | |
11555 | etest->flags |= ETH_TEST_FL_FAILED; | |
11556 | data[0] = 1; | |
11557 | } | |
ca43007a MC |
11558 | if (tg3_test_link(tp) != 0) { |
11559 | etest->flags |= ETH_TEST_FL_FAILED; | |
11560 | data[1] = 1; | |
11561 | } | |
a71116d1 | 11562 | if (etest->flags & ETH_TEST_FL_OFFLINE) { |
b02fd9e3 | 11563 | int err, err2 = 0, irq_sync = 0; |
bbe832c0 MC |
11564 | |
11565 | if (netif_running(dev)) { | |
b02fd9e3 | 11566 | tg3_phy_stop(tp); |
a71116d1 | 11567 | tg3_netif_stop(tp); |
bbe832c0 MC |
11568 | irq_sync = 1; |
11569 | } | |
a71116d1 | 11570 | |
bbe832c0 | 11571 | tg3_full_lock(tp, irq_sync); |
a71116d1 MC |
11572 | |
11573 | tg3_halt(tp, RESET_KIND_SUSPEND, 1); | |
ec41c7df | 11574 | err = tg3_nvram_lock(tp); |
a71116d1 | 11575 | tg3_halt_cpu(tp, RX_CPU_BASE); |
63c3a66f | 11576 | if (!tg3_flag(tp, 5705_PLUS)) |
a71116d1 | 11577 | tg3_halt_cpu(tp, TX_CPU_BASE); |
ec41c7df MC |
11578 | if (!err) |
11579 | tg3_nvram_unlock(tp); | |
a71116d1 | 11580 | |
f07e9af3 | 11581 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) |
d9ab5ad1 MC |
11582 | tg3_phy_reset(tp); |
11583 | ||
a71116d1 MC |
11584 | if (tg3_test_registers(tp) != 0) { |
11585 | etest->flags |= ETH_TEST_FL_FAILED; | |
11586 | data[2] = 1; | |
11587 | } | |
7942e1db MC |
11588 | if (tg3_test_memory(tp) != 0) { |
11589 | etest->flags |= ETH_TEST_FL_FAILED; | |
11590 | data[3] = 1; | |
11591 | } | |
9f40dead | 11592 | if ((data[4] = tg3_test_loopback(tp)) != 0) |
c76949a6 | 11593 | etest->flags |= ETH_TEST_FL_FAILED; |
a71116d1 | 11594 | |
f47c11ee DM |
11595 | tg3_full_unlock(tp); |
11596 | ||
d4bc3927 MC |
11597 | if (tg3_test_interrupt(tp) != 0) { |
11598 | etest->flags |= ETH_TEST_FL_FAILED; | |
11599 | data[5] = 1; | |
11600 | } | |
f47c11ee DM |
11601 | |
11602 | tg3_full_lock(tp, 0); | |
d4bc3927 | 11603 | |
a71116d1 MC |
11604 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
11605 | if (netif_running(dev)) { | |
63c3a66f | 11606 | tg3_flag_set(tp, INIT_COMPLETE); |
b02fd9e3 MC |
11607 | err2 = tg3_restart_hw(tp, 1); |
11608 | if (!err2) | |
b9ec6c1b | 11609 | tg3_netif_start(tp); |
a71116d1 | 11610 | } |
f47c11ee DM |
11611 | |
11612 | tg3_full_unlock(tp); | |
b02fd9e3 MC |
11613 | |
11614 | if (irq_sync && !err2) | |
11615 | tg3_phy_start(tp); | |
a71116d1 | 11616 | } |
80096068 | 11617 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
c866b7ea | 11618 | tg3_power_down(tp); |
bc1c7567 | 11619 | |
4cafd3f5 MC |
11620 | } |
11621 | ||
1da177e4 LT |
11622 | static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
11623 | { | |
11624 | struct mii_ioctl_data *data = if_mii(ifr); | |
11625 | struct tg3 *tp = netdev_priv(dev); | |
11626 | int err; | |
11627 | ||
63c3a66f | 11628 | if (tg3_flag(tp, USE_PHYLIB)) { |
3f0e3ad7 | 11629 | struct phy_device *phydev; |
f07e9af3 | 11630 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 | 11631 | return -EAGAIN; |
3f0e3ad7 | 11632 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
28b04113 | 11633 | return phy_mii_ioctl(phydev, ifr, cmd); |
b02fd9e3 MC |
11634 | } |
11635 | ||
33f401ae | 11636 | switch (cmd) { |
1da177e4 | 11637 | case SIOCGMIIPHY: |
882e9793 | 11638 | data->phy_id = tp->phy_addr; |
1da177e4 LT |
11639 | |
11640 | /* fallthru */ | |
11641 | case SIOCGMIIREG: { | |
11642 | u32 mii_regval; | |
11643 | ||
f07e9af3 | 11644 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
1da177e4 LT |
11645 | break; /* We have no PHY */ |
11646 | ||
34eea5ac | 11647 | if (!netif_running(dev)) |
bc1c7567 MC |
11648 | return -EAGAIN; |
11649 | ||
f47c11ee | 11650 | spin_lock_bh(&tp->lock); |
1da177e4 | 11651 | err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval); |
f47c11ee | 11652 | spin_unlock_bh(&tp->lock); |
1da177e4 LT |
11653 | |
11654 | data->val_out = mii_regval; | |
11655 | ||
11656 | return err; | |
11657 | } | |
11658 | ||
11659 | case SIOCSMIIREG: | |
f07e9af3 | 11660 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
1da177e4 LT |
11661 | break; /* We have no PHY */ |
11662 | ||
34eea5ac | 11663 | if (!netif_running(dev)) |
bc1c7567 MC |
11664 | return -EAGAIN; |
11665 | ||
f47c11ee | 11666 | spin_lock_bh(&tp->lock); |
1da177e4 | 11667 | err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in); |
f47c11ee | 11668 | spin_unlock_bh(&tp->lock); |
1da177e4 LT |
11669 | |
11670 | return err; | |
11671 | ||
11672 | default: | |
11673 | /* do nothing */ | |
11674 | break; | |
11675 | } | |
11676 | return -EOPNOTSUPP; | |
11677 | } | |
11678 | ||
15f9850d DM |
11679 | static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) |
11680 | { | |
11681 | struct tg3 *tp = netdev_priv(dev); | |
11682 | ||
11683 | memcpy(ec, &tp->coal, sizeof(*ec)); | |
11684 | return 0; | |
11685 | } | |
11686 | ||
d244c892 MC |
11687 | static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) |
11688 | { | |
11689 | struct tg3 *tp = netdev_priv(dev); | |
11690 | u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0; | |
11691 | u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0; | |
11692 | ||
63c3a66f | 11693 | if (!tg3_flag(tp, 5705_PLUS)) { |
d244c892 MC |
11694 | max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT; |
11695 | max_txcoal_tick_int = MAX_TXCOAL_TICK_INT; | |
11696 | max_stat_coal_ticks = MAX_STAT_COAL_TICKS; | |
11697 | min_stat_coal_ticks = MIN_STAT_COAL_TICKS; | |
11698 | } | |
11699 | ||
11700 | if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) || | |
11701 | (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) || | |
11702 | (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) || | |
11703 | (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) || | |
11704 | (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) || | |
11705 | (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) || | |
11706 | (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) || | |
11707 | (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) || | |
11708 | (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) || | |
11709 | (ec->stats_block_coalesce_usecs < min_stat_coal_ticks)) | |
11710 | return -EINVAL; | |
11711 | ||
11712 | /* No rx interrupts will be generated if both are zero */ | |
11713 | if ((ec->rx_coalesce_usecs == 0) && | |
11714 | (ec->rx_max_coalesced_frames == 0)) | |
11715 | return -EINVAL; | |
11716 | ||
11717 | /* No tx interrupts will be generated if both are zero */ | |
11718 | if ((ec->tx_coalesce_usecs == 0) && | |
11719 | (ec->tx_max_coalesced_frames == 0)) | |
11720 | return -EINVAL; | |
11721 | ||
11722 | /* Only copy relevant parameters, ignore all others. */ | |
11723 | tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs; | |
11724 | tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs; | |
11725 | tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames; | |
11726 | tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames; | |
11727 | tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq; | |
11728 | tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq; | |
11729 | tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq; | |
11730 | tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq; | |
11731 | tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs; | |
11732 | ||
11733 | if (netif_running(dev)) { | |
11734 | tg3_full_lock(tp, 0); | |
11735 | __tg3_set_coalesce(tp, &tp->coal); | |
11736 | tg3_full_unlock(tp); | |
11737 | } | |
11738 | return 0; | |
11739 | } | |
11740 | ||
7282d491 | 11741 | static const struct ethtool_ops tg3_ethtool_ops = { |
1da177e4 LT |
11742 | .get_settings = tg3_get_settings, |
11743 | .set_settings = tg3_set_settings, | |
11744 | .get_drvinfo = tg3_get_drvinfo, | |
11745 | .get_regs_len = tg3_get_regs_len, | |
11746 | .get_regs = tg3_get_regs, | |
11747 | .get_wol = tg3_get_wol, | |
11748 | .set_wol = tg3_set_wol, | |
11749 | .get_msglevel = tg3_get_msglevel, | |
11750 | .set_msglevel = tg3_set_msglevel, | |
11751 | .nway_reset = tg3_nway_reset, | |
11752 | .get_link = ethtool_op_get_link, | |
11753 | .get_eeprom_len = tg3_get_eeprom_len, | |
11754 | .get_eeprom = tg3_get_eeprom, | |
11755 | .set_eeprom = tg3_set_eeprom, | |
11756 | .get_ringparam = tg3_get_ringparam, | |
11757 | .set_ringparam = tg3_set_ringparam, | |
11758 | .get_pauseparam = tg3_get_pauseparam, | |
11759 | .set_pauseparam = tg3_set_pauseparam, | |
4cafd3f5 | 11760 | .self_test = tg3_self_test, |
1da177e4 | 11761 | .get_strings = tg3_get_strings, |
81b8709c | 11762 | .set_phys_id = tg3_set_phys_id, |
1da177e4 | 11763 | .get_ethtool_stats = tg3_get_ethtool_stats, |
15f9850d | 11764 | .get_coalesce = tg3_get_coalesce, |
d244c892 | 11765 | .set_coalesce = tg3_set_coalesce, |
b9f2c044 | 11766 | .get_sset_count = tg3_get_sset_count, |
1da177e4 LT |
11767 | }; |
11768 | ||
11769 | static void __devinit tg3_get_eeprom_size(struct tg3 *tp) | |
11770 | { | |
1b27777a | 11771 | u32 cursize, val, magic; |
1da177e4 LT |
11772 | |
11773 | tp->nvram_size = EEPROM_CHIP_SIZE; | |
11774 | ||
e4f34110 | 11775 | if (tg3_nvram_read(tp, 0, &magic) != 0) |
1da177e4 LT |
11776 | return; |
11777 | ||
b16250e3 MC |
11778 | if ((magic != TG3_EEPROM_MAGIC) && |
11779 | ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) && | |
11780 | ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW)) | |
1da177e4 LT |
11781 | return; |
11782 | ||
11783 | /* | |
11784 | * Size the chip by reading offsets at increasing powers of two. | |
11785 | * When we encounter our validation signature, we know the addressing | |
11786 | * has wrapped around, and thus have our chip size. | |
11787 | */ | |
1b27777a | 11788 | cursize = 0x10; |
1da177e4 LT |
11789 | |
11790 | while (cursize < tp->nvram_size) { | |
e4f34110 | 11791 | if (tg3_nvram_read(tp, cursize, &val) != 0) |
1da177e4 LT |
11792 | return; |
11793 | ||
1820180b | 11794 | if (val == magic) |
1da177e4 LT |
11795 | break; |
11796 | ||
11797 | cursize <<= 1; | |
11798 | } | |
11799 | ||
11800 | tp->nvram_size = cursize; | |
11801 | } | |
6aa20a22 | 11802 | |
1da177e4 LT |
11803 | static void __devinit tg3_get_nvram_size(struct tg3 *tp) |
11804 | { | |
11805 | u32 val; | |
11806 | ||
63c3a66f | 11807 | if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0) |
1b27777a MC |
11808 | return; |
11809 | ||
11810 | /* Selfboot format */ | |
1820180b | 11811 | if (val != TG3_EEPROM_MAGIC) { |
1b27777a MC |
11812 | tg3_get_eeprom_size(tp); |
11813 | return; | |
11814 | } | |
11815 | ||
6d348f2c | 11816 | if (tg3_nvram_read(tp, 0xf0, &val) == 0) { |
1da177e4 | 11817 | if (val != 0) { |
6d348f2c MC |
11818 | /* This is confusing. We want to operate on the |
11819 | * 16-bit value at offset 0xf2. The tg3_nvram_read() | |
11820 | * call will read from NVRAM and byteswap the data | |
11821 | * according to the byteswapping settings for all | |
11822 | * other register accesses. This ensures the data we | |
11823 | * want will always reside in the lower 16-bits. | |
11824 | * However, the data in NVRAM is in LE format, which | |
11825 | * means the data from the NVRAM read will always be | |
11826 | * opposite the endianness of the CPU. The 16-bit | |
11827 | * byteswap then brings the data to CPU endianness. | |
11828 | */ | |
11829 | tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024; | |
1da177e4 LT |
11830 | return; |
11831 | } | |
11832 | } | |
fd1122a2 | 11833 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; |
1da177e4 LT |
11834 | } |
11835 | ||
11836 | static void __devinit tg3_get_nvram_info(struct tg3 *tp) | |
11837 | { | |
11838 | u32 nvcfg1; | |
11839 | ||
11840 | nvcfg1 = tr32(NVRAM_CFG1); | |
11841 | if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) { | |
63c3a66f | 11842 | tg3_flag_set(tp, FLASH); |
8590a603 | 11843 | } else { |
1da177e4 LT |
11844 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; |
11845 | tw32(NVRAM_CFG1, nvcfg1); | |
11846 | } | |
11847 | ||
6ff6f81d | 11848 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || |
63c3a66f | 11849 | tg3_flag(tp, 5780_CLASS)) { |
1da177e4 | 11850 | switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) { |
8590a603 MC |
11851 | case FLASH_VENDOR_ATMEL_FLASH_BUFFERED: |
11852 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11853 | tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; | |
63c3a66f | 11854 | tg3_flag_set(tp, NVRAM_BUFFERED); |
8590a603 MC |
11855 | break; |
11856 | case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED: | |
11857 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11858 | tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE; | |
11859 | break; | |
11860 | case FLASH_VENDOR_ATMEL_EEPROM: | |
11861 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11862 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
63c3a66f | 11863 | tg3_flag_set(tp, NVRAM_BUFFERED); |
8590a603 MC |
11864 | break; |
11865 | case FLASH_VENDOR_ST: | |
11866 | tp->nvram_jedecnum = JEDEC_ST; | |
11867 | tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE; | |
63c3a66f | 11868 | tg3_flag_set(tp, NVRAM_BUFFERED); |
8590a603 MC |
11869 | break; |
11870 | case FLASH_VENDOR_SAIFUN: | |
11871 | tp->nvram_jedecnum = JEDEC_SAIFUN; | |
11872 | tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE; | |
11873 | break; | |
11874 | case FLASH_VENDOR_SST_SMALL: | |
11875 | case FLASH_VENDOR_SST_LARGE: | |
11876 | tp->nvram_jedecnum = JEDEC_SST; | |
11877 | tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE; | |
11878 | break; | |
1da177e4 | 11879 | } |
8590a603 | 11880 | } else { |
1da177e4 LT |
11881 | tp->nvram_jedecnum = JEDEC_ATMEL; |
11882 | tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; | |
63c3a66f | 11883 | tg3_flag_set(tp, NVRAM_BUFFERED); |
1da177e4 LT |
11884 | } |
11885 | } | |
11886 | ||
a1b950d5 MC |
11887 | static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1) |
11888 | { | |
11889 | switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) { | |
11890 | case FLASH_5752PAGE_SIZE_256: | |
11891 | tp->nvram_pagesize = 256; | |
11892 | break; | |
11893 | case FLASH_5752PAGE_SIZE_512: | |
11894 | tp->nvram_pagesize = 512; | |
11895 | break; | |
11896 | case FLASH_5752PAGE_SIZE_1K: | |
11897 | tp->nvram_pagesize = 1024; | |
11898 | break; | |
11899 | case FLASH_5752PAGE_SIZE_2K: | |
11900 | tp->nvram_pagesize = 2048; | |
11901 | break; | |
11902 | case FLASH_5752PAGE_SIZE_4K: | |
11903 | tp->nvram_pagesize = 4096; | |
11904 | break; | |
11905 | case FLASH_5752PAGE_SIZE_264: | |
11906 | tp->nvram_pagesize = 264; | |
11907 | break; | |
11908 | case FLASH_5752PAGE_SIZE_528: | |
11909 | tp->nvram_pagesize = 528; | |
11910 | break; | |
11911 | } | |
11912 | } | |
11913 | ||
361b4ac2 MC |
11914 | static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp) |
11915 | { | |
11916 | u32 nvcfg1; | |
11917 | ||
11918 | nvcfg1 = tr32(NVRAM_CFG1); | |
11919 | ||
e6af301b MC |
11920 | /* NVRAM protection for TPM */ |
11921 | if (nvcfg1 & (1 << 27)) | |
63c3a66f | 11922 | tg3_flag_set(tp, PROTECTED_NVRAM); |
e6af301b | 11923 | |
361b4ac2 | 11924 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { |
8590a603 MC |
11925 | case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ: |
11926 | case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ: | |
11927 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f | 11928 | tg3_flag_set(tp, NVRAM_BUFFERED); |
8590a603 MC |
11929 | break; |
11930 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
11931 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
11932 | tg3_flag_set(tp, NVRAM_BUFFERED); |
11933 | tg3_flag_set(tp, FLASH); | |
8590a603 MC |
11934 | break; |
11935 | case FLASH_5752VENDOR_ST_M45PE10: | |
11936 | case FLASH_5752VENDOR_ST_M45PE20: | |
11937 | case FLASH_5752VENDOR_ST_M45PE40: | |
11938 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
11939 | tg3_flag_set(tp, NVRAM_BUFFERED); |
11940 | tg3_flag_set(tp, FLASH); | |
8590a603 | 11941 | break; |
361b4ac2 MC |
11942 | } |
11943 | ||
63c3a66f | 11944 | if (tg3_flag(tp, FLASH)) { |
a1b950d5 | 11945 | tg3_nvram_get_pagesize(tp, nvcfg1); |
8590a603 | 11946 | } else { |
361b4ac2 MC |
11947 | /* For eeprom, set pagesize to maximum eeprom size */ |
11948 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
11949 | ||
11950 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
11951 | tw32(NVRAM_CFG1, nvcfg1); | |
11952 | } | |
11953 | } | |
11954 | ||
d3c7b886 MC |
11955 | static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp) |
11956 | { | |
989a9d23 | 11957 | u32 nvcfg1, protect = 0; |
d3c7b886 MC |
11958 | |
11959 | nvcfg1 = tr32(NVRAM_CFG1); | |
11960 | ||
11961 | /* NVRAM protection for TPM */ | |
989a9d23 | 11962 | if (nvcfg1 & (1 << 27)) { |
63c3a66f | 11963 | tg3_flag_set(tp, PROTECTED_NVRAM); |
989a9d23 MC |
11964 | protect = 1; |
11965 | } | |
d3c7b886 | 11966 | |
989a9d23 MC |
11967 | nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK; |
11968 | switch (nvcfg1) { | |
8590a603 MC |
11969 | case FLASH_5755VENDOR_ATMEL_FLASH_1: |
11970 | case FLASH_5755VENDOR_ATMEL_FLASH_2: | |
11971 | case FLASH_5755VENDOR_ATMEL_FLASH_3: | |
11972 | case FLASH_5755VENDOR_ATMEL_FLASH_5: | |
11973 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
11974 | tg3_flag_set(tp, NVRAM_BUFFERED); |
11975 | tg3_flag_set(tp, FLASH); | |
8590a603 MC |
11976 | tp->nvram_pagesize = 264; |
11977 | if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 || | |
11978 | nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5) | |
11979 | tp->nvram_size = (protect ? 0x3e200 : | |
11980 | TG3_NVRAM_SIZE_512KB); | |
11981 | else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2) | |
11982 | tp->nvram_size = (protect ? 0x1f200 : | |
11983 | TG3_NVRAM_SIZE_256KB); | |
11984 | else | |
11985 | tp->nvram_size = (protect ? 0x1f200 : | |
11986 | TG3_NVRAM_SIZE_128KB); | |
11987 | break; | |
11988 | case FLASH_5752VENDOR_ST_M45PE10: | |
11989 | case FLASH_5752VENDOR_ST_M45PE20: | |
11990 | case FLASH_5752VENDOR_ST_M45PE40: | |
11991 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
11992 | tg3_flag_set(tp, NVRAM_BUFFERED); |
11993 | tg3_flag_set(tp, FLASH); | |
8590a603 MC |
11994 | tp->nvram_pagesize = 256; |
11995 | if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10) | |
11996 | tp->nvram_size = (protect ? | |
11997 | TG3_NVRAM_SIZE_64KB : | |
11998 | TG3_NVRAM_SIZE_128KB); | |
11999 | else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20) | |
12000 | tp->nvram_size = (protect ? | |
12001 | TG3_NVRAM_SIZE_64KB : | |
12002 | TG3_NVRAM_SIZE_256KB); | |
12003 | else | |
12004 | tp->nvram_size = (protect ? | |
12005 | TG3_NVRAM_SIZE_128KB : | |
12006 | TG3_NVRAM_SIZE_512KB); | |
12007 | break; | |
d3c7b886 MC |
12008 | } |
12009 | } | |
12010 | ||
1b27777a MC |
12011 | static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp) |
12012 | { | |
12013 | u32 nvcfg1; | |
12014 | ||
12015 | nvcfg1 = tr32(NVRAM_CFG1); | |
12016 | ||
12017 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
8590a603 MC |
12018 | case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ: |
12019 | case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ: | |
12020 | case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ: | |
12021 | case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ: | |
12022 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f | 12023 | tg3_flag_set(tp, NVRAM_BUFFERED); |
8590a603 | 12024 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; |
1b27777a | 12025 | |
8590a603 MC |
12026 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; |
12027 | tw32(NVRAM_CFG1, nvcfg1); | |
12028 | break; | |
12029 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
12030 | case FLASH_5755VENDOR_ATMEL_FLASH_1: | |
12031 | case FLASH_5755VENDOR_ATMEL_FLASH_2: | |
12032 | case FLASH_5755VENDOR_ATMEL_FLASH_3: | |
12033 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
12034 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12035 | tg3_flag_set(tp, FLASH); | |
8590a603 MC |
12036 | tp->nvram_pagesize = 264; |
12037 | break; | |
12038 | case FLASH_5752VENDOR_ST_M45PE10: | |
12039 | case FLASH_5752VENDOR_ST_M45PE20: | |
12040 | case FLASH_5752VENDOR_ST_M45PE40: | |
12041 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
12042 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12043 | tg3_flag_set(tp, FLASH); | |
8590a603 MC |
12044 | tp->nvram_pagesize = 256; |
12045 | break; | |
1b27777a MC |
12046 | } |
12047 | } | |
12048 | ||
6b91fa02 MC |
12049 | static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp) |
12050 | { | |
12051 | u32 nvcfg1, protect = 0; | |
12052 | ||
12053 | nvcfg1 = tr32(NVRAM_CFG1); | |
12054 | ||
12055 | /* NVRAM protection for TPM */ | |
12056 | if (nvcfg1 & (1 << 27)) { | |
63c3a66f | 12057 | tg3_flag_set(tp, PROTECTED_NVRAM); |
6b91fa02 MC |
12058 | protect = 1; |
12059 | } | |
12060 | ||
12061 | nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK; | |
12062 | switch (nvcfg1) { | |
8590a603 MC |
12063 | case FLASH_5761VENDOR_ATMEL_ADB021D: |
12064 | case FLASH_5761VENDOR_ATMEL_ADB041D: | |
12065 | case FLASH_5761VENDOR_ATMEL_ADB081D: | |
12066 | case FLASH_5761VENDOR_ATMEL_ADB161D: | |
12067 | case FLASH_5761VENDOR_ATMEL_MDB021D: | |
12068 | case FLASH_5761VENDOR_ATMEL_MDB041D: | |
12069 | case FLASH_5761VENDOR_ATMEL_MDB081D: | |
12070 | case FLASH_5761VENDOR_ATMEL_MDB161D: | |
12071 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
12072 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12073 | tg3_flag_set(tp, FLASH); | |
12074 | tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); | |
8590a603 MC |
12075 | tp->nvram_pagesize = 256; |
12076 | break; | |
12077 | case FLASH_5761VENDOR_ST_A_M45PE20: | |
12078 | case FLASH_5761VENDOR_ST_A_M45PE40: | |
12079 | case FLASH_5761VENDOR_ST_A_M45PE80: | |
12080 | case FLASH_5761VENDOR_ST_A_M45PE16: | |
12081 | case FLASH_5761VENDOR_ST_M_M45PE20: | |
12082 | case FLASH_5761VENDOR_ST_M_M45PE40: | |
12083 | case FLASH_5761VENDOR_ST_M_M45PE80: | |
12084 | case FLASH_5761VENDOR_ST_M_M45PE16: | |
12085 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
12086 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12087 | tg3_flag_set(tp, FLASH); | |
8590a603 MC |
12088 | tp->nvram_pagesize = 256; |
12089 | break; | |
6b91fa02 MC |
12090 | } |
12091 | ||
12092 | if (protect) { | |
12093 | tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT); | |
12094 | } else { | |
12095 | switch (nvcfg1) { | |
8590a603 MC |
12096 | case FLASH_5761VENDOR_ATMEL_ADB161D: |
12097 | case FLASH_5761VENDOR_ATMEL_MDB161D: | |
12098 | case FLASH_5761VENDOR_ST_A_M45PE16: | |
12099 | case FLASH_5761VENDOR_ST_M_M45PE16: | |
12100 | tp->nvram_size = TG3_NVRAM_SIZE_2MB; | |
12101 | break; | |
12102 | case FLASH_5761VENDOR_ATMEL_ADB081D: | |
12103 | case FLASH_5761VENDOR_ATMEL_MDB081D: | |
12104 | case FLASH_5761VENDOR_ST_A_M45PE80: | |
12105 | case FLASH_5761VENDOR_ST_M_M45PE80: | |
12106 | tp->nvram_size = TG3_NVRAM_SIZE_1MB; | |
12107 | break; | |
12108 | case FLASH_5761VENDOR_ATMEL_ADB041D: | |
12109 | case FLASH_5761VENDOR_ATMEL_MDB041D: | |
12110 | case FLASH_5761VENDOR_ST_A_M45PE40: | |
12111 | case FLASH_5761VENDOR_ST_M_M45PE40: | |
12112 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
12113 | break; | |
12114 | case FLASH_5761VENDOR_ATMEL_ADB021D: | |
12115 | case FLASH_5761VENDOR_ATMEL_MDB021D: | |
12116 | case FLASH_5761VENDOR_ST_A_M45PE20: | |
12117 | case FLASH_5761VENDOR_ST_M_M45PE20: | |
12118 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12119 | break; | |
6b91fa02 MC |
12120 | } |
12121 | } | |
12122 | } | |
12123 | ||
b5d3772c MC |
12124 | static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp) |
12125 | { | |
12126 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f | 12127 | tg3_flag_set(tp, NVRAM_BUFFERED); |
b5d3772c MC |
12128 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; |
12129 | } | |
12130 | ||
321d32a0 MC |
12131 | static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp) |
12132 | { | |
12133 | u32 nvcfg1; | |
12134 | ||
12135 | nvcfg1 = tr32(NVRAM_CFG1); | |
12136 | ||
12137 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
12138 | case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ: | |
12139 | case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ: | |
12140 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f | 12141 | tg3_flag_set(tp, NVRAM_BUFFERED); |
321d32a0 MC |
12142 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; |
12143 | ||
12144 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
12145 | tw32(NVRAM_CFG1, nvcfg1); | |
12146 | return; | |
12147 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
12148 | case FLASH_57780VENDOR_ATMEL_AT45DB011D: | |
12149 | case FLASH_57780VENDOR_ATMEL_AT45DB011B: | |
12150 | case FLASH_57780VENDOR_ATMEL_AT45DB021D: | |
12151 | case FLASH_57780VENDOR_ATMEL_AT45DB021B: | |
12152 | case FLASH_57780VENDOR_ATMEL_AT45DB041D: | |
12153 | case FLASH_57780VENDOR_ATMEL_AT45DB041B: | |
12154 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
12155 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12156 | tg3_flag_set(tp, FLASH); | |
321d32a0 MC |
12157 | |
12158 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
12159 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
12160 | case FLASH_57780VENDOR_ATMEL_AT45DB011D: | |
12161 | case FLASH_57780VENDOR_ATMEL_AT45DB011B: | |
12162 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
12163 | break; | |
12164 | case FLASH_57780VENDOR_ATMEL_AT45DB021D: | |
12165 | case FLASH_57780VENDOR_ATMEL_AT45DB021B: | |
12166 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12167 | break; | |
12168 | case FLASH_57780VENDOR_ATMEL_AT45DB041D: | |
12169 | case FLASH_57780VENDOR_ATMEL_AT45DB041B: | |
12170 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
12171 | break; | |
12172 | } | |
12173 | break; | |
12174 | case FLASH_5752VENDOR_ST_M45PE10: | |
12175 | case FLASH_5752VENDOR_ST_M45PE20: | |
12176 | case FLASH_5752VENDOR_ST_M45PE40: | |
12177 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
12178 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12179 | tg3_flag_set(tp, FLASH); | |
321d32a0 MC |
12180 | |
12181 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
12182 | case FLASH_5752VENDOR_ST_M45PE10: | |
12183 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
12184 | break; | |
12185 | case FLASH_5752VENDOR_ST_M45PE20: | |
12186 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12187 | break; | |
12188 | case FLASH_5752VENDOR_ST_M45PE40: | |
12189 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
12190 | break; | |
12191 | } | |
12192 | break; | |
12193 | default: | |
63c3a66f | 12194 | tg3_flag_set(tp, NO_NVRAM); |
321d32a0 MC |
12195 | return; |
12196 | } | |
12197 | ||
a1b950d5 MC |
12198 | tg3_nvram_get_pagesize(tp, nvcfg1); |
12199 | if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) | |
63c3a66f | 12200 | tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); |
a1b950d5 MC |
12201 | } |
12202 | ||
12203 | ||
12204 | static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp) | |
12205 | { | |
12206 | u32 nvcfg1; | |
12207 | ||
12208 | nvcfg1 = tr32(NVRAM_CFG1); | |
12209 | ||
12210 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
12211 | case FLASH_5717VENDOR_ATMEL_EEPROM: | |
12212 | case FLASH_5717VENDOR_MICRO_EEPROM: | |
12213 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f | 12214 | tg3_flag_set(tp, NVRAM_BUFFERED); |
a1b950d5 MC |
12215 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; |
12216 | ||
12217 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
12218 | tw32(NVRAM_CFG1, nvcfg1); | |
12219 | return; | |
12220 | case FLASH_5717VENDOR_ATMEL_MDB011D: | |
12221 | case FLASH_5717VENDOR_ATMEL_ADB011B: | |
12222 | case FLASH_5717VENDOR_ATMEL_ADB011D: | |
12223 | case FLASH_5717VENDOR_ATMEL_MDB021D: | |
12224 | case FLASH_5717VENDOR_ATMEL_ADB021B: | |
12225 | case FLASH_5717VENDOR_ATMEL_ADB021D: | |
12226 | case FLASH_5717VENDOR_ATMEL_45USPT: | |
12227 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
12228 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12229 | tg3_flag_set(tp, FLASH); | |
a1b950d5 MC |
12230 | |
12231 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
12232 | case FLASH_5717VENDOR_ATMEL_MDB021D: | |
66ee33bf MC |
12233 | /* Detect size with tg3_nvram_get_size() */ |
12234 | break; | |
a1b950d5 MC |
12235 | case FLASH_5717VENDOR_ATMEL_ADB021B: |
12236 | case FLASH_5717VENDOR_ATMEL_ADB021D: | |
12237 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12238 | break; | |
12239 | default: | |
12240 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
12241 | break; | |
12242 | } | |
321d32a0 | 12243 | break; |
a1b950d5 MC |
12244 | case FLASH_5717VENDOR_ST_M_M25PE10: |
12245 | case FLASH_5717VENDOR_ST_A_M25PE10: | |
12246 | case FLASH_5717VENDOR_ST_M_M45PE10: | |
12247 | case FLASH_5717VENDOR_ST_A_M45PE10: | |
12248 | case FLASH_5717VENDOR_ST_M_M25PE20: | |
12249 | case FLASH_5717VENDOR_ST_A_M25PE20: | |
12250 | case FLASH_5717VENDOR_ST_M_M45PE20: | |
12251 | case FLASH_5717VENDOR_ST_A_M45PE20: | |
12252 | case FLASH_5717VENDOR_ST_25USPT: | |
12253 | case FLASH_5717VENDOR_ST_45USPT: | |
12254 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
12255 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12256 | tg3_flag_set(tp, FLASH); | |
a1b950d5 MC |
12257 | |
12258 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
12259 | case FLASH_5717VENDOR_ST_M_M25PE20: | |
a1b950d5 | 12260 | case FLASH_5717VENDOR_ST_M_M45PE20: |
66ee33bf MC |
12261 | /* Detect size with tg3_nvram_get_size() */ |
12262 | break; | |
12263 | case FLASH_5717VENDOR_ST_A_M25PE20: | |
a1b950d5 MC |
12264 | case FLASH_5717VENDOR_ST_A_M45PE20: |
12265 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12266 | break; | |
12267 | default: | |
12268 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
12269 | break; | |
12270 | } | |
321d32a0 | 12271 | break; |
a1b950d5 | 12272 | default: |
63c3a66f | 12273 | tg3_flag_set(tp, NO_NVRAM); |
a1b950d5 | 12274 | return; |
321d32a0 | 12275 | } |
a1b950d5 MC |
12276 | |
12277 | tg3_nvram_get_pagesize(tp, nvcfg1); | |
12278 | if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) | |
63c3a66f | 12279 | tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); |
321d32a0 MC |
12280 | } |
12281 | ||
9b91b5f1 MC |
12282 | static void __devinit tg3_get_5720_nvram_info(struct tg3 *tp) |
12283 | { | |
12284 | u32 nvcfg1, nvmpinstrp; | |
12285 | ||
12286 | nvcfg1 = tr32(NVRAM_CFG1); | |
12287 | nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK; | |
12288 | ||
12289 | switch (nvmpinstrp) { | |
12290 | case FLASH_5720_EEPROM_HD: | |
12291 | case FLASH_5720_EEPROM_LD: | |
12292 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f | 12293 | tg3_flag_set(tp, NVRAM_BUFFERED); |
9b91b5f1 MC |
12294 | |
12295 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
12296 | tw32(NVRAM_CFG1, nvcfg1); | |
12297 | if (nvmpinstrp == FLASH_5720_EEPROM_HD) | |
12298 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
12299 | else | |
12300 | tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE; | |
12301 | return; | |
12302 | case FLASH_5720VENDOR_M_ATMEL_DB011D: | |
12303 | case FLASH_5720VENDOR_A_ATMEL_DB011B: | |
12304 | case FLASH_5720VENDOR_A_ATMEL_DB011D: | |
12305 | case FLASH_5720VENDOR_M_ATMEL_DB021D: | |
12306 | case FLASH_5720VENDOR_A_ATMEL_DB021B: | |
12307 | case FLASH_5720VENDOR_A_ATMEL_DB021D: | |
12308 | case FLASH_5720VENDOR_M_ATMEL_DB041D: | |
12309 | case FLASH_5720VENDOR_A_ATMEL_DB041B: | |
12310 | case FLASH_5720VENDOR_A_ATMEL_DB041D: | |
12311 | case FLASH_5720VENDOR_M_ATMEL_DB081D: | |
12312 | case FLASH_5720VENDOR_A_ATMEL_DB081D: | |
12313 | case FLASH_5720VENDOR_ATMEL_45USPT: | |
12314 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
12315 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12316 | tg3_flag_set(tp, FLASH); | |
9b91b5f1 MC |
12317 | |
12318 | switch (nvmpinstrp) { | |
12319 | case FLASH_5720VENDOR_M_ATMEL_DB021D: | |
12320 | case FLASH_5720VENDOR_A_ATMEL_DB021B: | |
12321 | case FLASH_5720VENDOR_A_ATMEL_DB021D: | |
12322 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12323 | break; | |
12324 | case FLASH_5720VENDOR_M_ATMEL_DB041D: | |
12325 | case FLASH_5720VENDOR_A_ATMEL_DB041B: | |
12326 | case FLASH_5720VENDOR_A_ATMEL_DB041D: | |
12327 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
12328 | break; | |
12329 | case FLASH_5720VENDOR_M_ATMEL_DB081D: | |
12330 | case FLASH_5720VENDOR_A_ATMEL_DB081D: | |
12331 | tp->nvram_size = TG3_NVRAM_SIZE_1MB; | |
12332 | break; | |
12333 | default: | |
12334 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
12335 | break; | |
12336 | } | |
12337 | break; | |
12338 | case FLASH_5720VENDOR_M_ST_M25PE10: | |
12339 | case FLASH_5720VENDOR_M_ST_M45PE10: | |
12340 | case FLASH_5720VENDOR_A_ST_M25PE10: | |
12341 | case FLASH_5720VENDOR_A_ST_M45PE10: | |
12342 | case FLASH_5720VENDOR_M_ST_M25PE20: | |
12343 | case FLASH_5720VENDOR_M_ST_M45PE20: | |
12344 | case FLASH_5720VENDOR_A_ST_M25PE20: | |
12345 | case FLASH_5720VENDOR_A_ST_M45PE20: | |
12346 | case FLASH_5720VENDOR_M_ST_M25PE40: | |
12347 | case FLASH_5720VENDOR_M_ST_M45PE40: | |
12348 | case FLASH_5720VENDOR_A_ST_M25PE40: | |
12349 | case FLASH_5720VENDOR_A_ST_M45PE40: | |
12350 | case FLASH_5720VENDOR_M_ST_M25PE80: | |
12351 | case FLASH_5720VENDOR_M_ST_M45PE80: | |
12352 | case FLASH_5720VENDOR_A_ST_M25PE80: | |
12353 | case FLASH_5720VENDOR_A_ST_M45PE80: | |
12354 | case FLASH_5720VENDOR_ST_25USPT: | |
12355 | case FLASH_5720VENDOR_ST_45USPT: | |
12356 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
12357 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12358 | tg3_flag_set(tp, FLASH); | |
9b91b5f1 MC |
12359 | |
12360 | switch (nvmpinstrp) { | |
12361 | case FLASH_5720VENDOR_M_ST_M25PE20: | |
12362 | case FLASH_5720VENDOR_M_ST_M45PE20: | |
12363 | case FLASH_5720VENDOR_A_ST_M25PE20: | |
12364 | case FLASH_5720VENDOR_A_ST_M45PE20: | |
12365 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12366 | break; | |
12367 | case FLASH_5720VENDOR_M_ST_M25PE40: | |
12368 | case FLASH_5720VENDOR_M_ST_M45PE40: | |
12369 | case FLASH_5720VENDOR_A_ST_M25PE40: | |
12370 | case FLASH_5720VENDOR_A_ST_M45PE40: | |
12371 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
12372 | break; | |
12373 | case FLASH_5720VENDOR_M_ST_M25PE80: | |
12374 | case FLASH_5720VENDOR_M_ST_M45PE80: | |
12375 | case FLASH_5720VENDOR_A_ST_M25PE80: | |
12376 | case FLASH_5720VENDOR_A_ST_M45PE80: | |
12377 | tp->nvram_size = TG3_NVRAM_SIZE_1MB; | |
12378 | break; | |
12379 | default: | |
12380 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
12381 | break; | |
12382 | } | |
12383 | break; | |
12384 | default: | |
63c3a66f | 12385 | tg3_flag_set(tp, NO_NVRAM); |
9b91b5f1 MC |
12386 | return; |
12387 | } | |
12388 | ||
12389 | tg3_nvram_get_pagesize(tp, nvcfg1); | |
12390 | if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) | |
63c3a66f | 12391 | tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); |
9b91b5f1 MC |
12392 | } |
12393 | ||
1da177e4 LT |
12394 | /* Chips other than 5700/5701 use the NVRAM for fetching info. */ |
12395 | static void __devinit tg3_nvram_init(struct tg3 *tp) | |
12396 | { | |
1da177e4 LT |
12397 | tw32_f(GRC_EEPROM_ADDR, |
12398 | (EEPROM_ADDR_FSM_RESET | | |
12399 | (EEPROM_DEFAULT_CLOCK_PERIOD << | |
12400 | EEPROM_ADDR_CLKPERD_SHIFT))); | |
12401 | ||
9d57f01c | 12402 | msleep(1); |
1da177e4 LT |
12403 | |
12404 | /* Enable seeprom accesses. */ | |
12405 | tw32_f(GRC_LOCAL_CTRL, | |
12406 | tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM); | |
12407 | udelay(100); | |
12408 | ||
12409 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
12410 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) { | |
63c3a66f | 12411 | tg3_flag_set(tp, NVRAM); |
1da177e4 | 12412 | |
ec41c7df | 12413 | if (tg3_nvram_lock(tp)) { |
5129c3a3 MC |
12414 | netdev_warn(tp->dev, |
12415 | "Cannot get nvram lock, %s failed\n", | |
05dbe005 | 12416 | __func__); |
ec41c7df MC |
12417 | return; |
12418 | } | |
e6af301b | 12419 | tg3_enable_nvram_access(tp); |
1da177e4 | 12420 | |
989a9d23 MC |
12421 | tp->nvram_size = 0; |
12422 | ||
361b4ac2 MC |
12423 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) |
12424 | tg3_get_5752_nvram_info(tp); | |
d3c7b886 MC |
12425 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) |
12426 | tg3_get_5755_nvram_info(tp); | |
d30cdd28 | 12427 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || |
57e6983c MC |
12428 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
12429 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
1b27777a | 12430 | tg3_get_5787_nvram_info(tp); |
6b91fa02 MC |
12431 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) |
12432 | tg3_get_5761_nvram_info(tp); | |
b5d3772c MC |
12433 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
12434 | tg3_get_5906_nvram_info(tp); | |
b703df6f MC |
12435 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
12436 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
321d32a0 | 12437 | tg3_get_57780_nvram_info(tp); |
9b91b5f1 MC |
12438 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
12439 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | |
a1b950d5 | 12440 | tg3_get_5717_nvram_info(tp); |
9b91b5f1 MC |
12441 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) |
12442 | tg3_get_5720_nvram_info(tp); | |
361b4ac2 MC |
12443 | else |
12444 | tg3_get_nvram_info(tp); | |
12445 | ||
989a9d23 MC |
12446 | if (tp->nvram_size == 0) |
12447 | tg3_get_nvram_size(tp); | |
1da177e4 | 12448 | |
e6af301b | 12449 | tg3_disable_nvram_access(tp); |
381291b7 | 12450 | tg3_nvram_unlock(tp); |
1da177e4 LT |
12451 | |
12452 | } else { | |
63c3a66f JP |
12453 | tg3_flag_clear(tp, NVRAM); |
12454 | tg3_flag_clear(tp, NVRAM_BUFFERED); | |
1da177e4 LT |
12455 | |
12456 | tg3_get_eeprom_size(tp); | |
12457 | } | |
12458 | } | |
12459 | ||
1da177e4 LT |
12460 | static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp, |
12461 | u32 offset, u32 len, u8 *buf) | |
12462 | { | |
12463 | int i, j, rc = 0; | |
12464 | u32 val; | |
12465 | ||
12466 | for (i = 0; i < len; i += 4) { | |
b9fc7dc5 | 12467 | u32 addr; |
a9dc529d | 12468 | __be32 data; |
1da177e4 LT |
12469 | |
12470 | addr = offset + i; | |
12471 | ||
12472 | memcpy(&data, buf + i, 4); | |
12473 | ||
62cedd11 MC |
12474 | /* |
12475 | * The SEEPROM interface expects the data to always be opposite | |
12476 | * the native endian format. We accomplish this by reversing | |
12477 | * all the operations that would have been performed on the | |
12478 | * data from a call to tg3_nvram_read_be32(). | |
12479 | */ | |
12480 | tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data))); | |
1da177e4 LT |
12481 | |
12482 | val = tr32(GRC_EEPROM_ADDR); | |
12483 | tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE); | |
12484 | ||
12485 | val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK | | |
12486 | EEPROM_ADDR_READ); | |
12487 | tw32(GRC_EEPROM_ADDR, val | | |
12488 | (0 << EEPROM_ADDR_DEVID_SHIFT) | | |
12489 | (addr & EEPROM_ADDR_ADDR_MASK) | | |
12490 | EEPROM_ADDR_START | | |
12491 | EEPROM_ADDR_WRITE); | |
6aa20a22 | 12492 | |
9d57f01c | 12493 | for (j = 0; j < 1000; j++) { |
1da177e4 LT |
12494 | val = tr32(GRC_EEPROM_ADDR); |
12495 | ||
12496 | if (val & EEPROM_ADDR_COMPLETE) | |
12497 | break; | |
9d57f01c | 12498 | msleep(1); |
1da177e4 LT |
12499 | } |
12500 | if (!(val & EEPROM_ADDR_COMPLETE)) { | |
12501 | rc = -EBUSY; | |
12502 | break; | |
12503 | } | |
12504 | } | |
12505 | ||
12506 | return rc; | |
12507 | } | |
12508 | ||
12509 | /* offset and length are dword aligned */ | |
12510 | static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len, | |
12511 | u8 *buf) | |
12512 | { | |
12513 | int ret = 0; | |
12514 | u32 pagesize = tp->nvram_pagesize; | |
12515 | u32 pagemask = pagesize - 1; | |
12516 | u32 nvram_cmd; | |
12517 | u8 *tmp; | |
12518 | ||
12519 | tmp = kmalloc(pagesize, GFP_KERNEL); | |
12520 | if (tmp == NULL) | |
12521 | return -ENOMEM; | |
12522 | ||
12523 | while (len) { | |
12524 | int j; | |
e6af301b | 12525 | u32 phy_addr, page_off, size; |
1da177e4 LT |
12526 | |
12527 | phy_addr = offset & ~pagemask; | |
6aa20a22 | 12528 | |
1da177e4 | 12529 | for (j = 0; j < pagesize; j += 4) { |
a9dc529d MC |
12530 | ret = tg3_nvram_read_be32(tp, phy_addr + j, |
12531 | (__be32 *) (tmp + j)); | |
12532 | if (ret) | |
1da177e4 LT |
12533 | break; |
12534 | } | |
12535 | if (ret) | |
12536 | break; | |
12537 | ||
c6cdf436 | 12538 | page_off = offset & pagemask; |
1da177e4 LT |
12539 | size = pagesize; |
12540 | if (len < size) | |
12541 | size = len; | |
12542 | ||
12543 | len -= size; | |
12544 | ||
12545 | memcpy(tmp + page_off, buf, size); | |
12546 | ||
12547 | offset = offset + (pagesize - page_off); | |
12548 | ||
e6af301b | 12549 | tg3_enable_nvram_access(tp); |
1da177e4 LT |
12550 | |
12551 | /* | |
12552 | * Before we can erase the flash page, we need | |
12553 | * to issue a special "write enable" command. | |
12554 | */ | |
12555 | nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
12556 | ||
12557 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) | |
12558 | break; | |
12559 | ||
12560 | /* Erase the target page */ | |
12561 | tw32(NVRAM_ADDR, phy_addr); | |
12562 | ||
12563 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR | | |
12564 | NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE; | |
12565 | ||
c6cdf436 | 12566 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) |
1da177e4 LT |
12567 | break; |
12568 | ||
12569 | /* Issue another write enable to start the write. */ | |
12570 | nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
12571 | ||
12572 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) | |
12573 | break; | |
12574 | ||
12575 | for (j = 0; j < pagesize; j += 4) { | |
b9fc7dc5 | 12576 | __be32 data; |
1da177e4 | 12577 | |
b9fc7dc5 | 12578 | data = *((__be32 *) (tmp + j)); |
a9dc529d | 12579 | |
b9fc7dc5 | 12580 | tw32(NVRAM_WRDATA, be32_to_cpu(data)); |
1da177e4 LT |
12581 | |
12582 | tw32(NVRAM_ADDR, phy_addr + j); | |
12583 | ||
12584 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | | |
12585 | NVRAM_CMD_WR; | |
12586 | ||
12587 | if (j == 0) | |
12588 | nvram_cmd |= NVRAM_CMD_FIRST; | |
12589 | else if (j == (pagesize - 4)) | |
12590 | nvram_cmd |= NVRAM_CMD_LAST; | |
12591 | ||
12592 | if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd))) | |
12593 | break; | |
12594 | } | |
12595 | if (ret) | |
12596 | break; | |
12597 | } | |
12598 | ||
12599 | nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
12600 | tg3_nvram_exec_cmd(tp, nvram_cmd); | |
12601 | ||
12602 | kfree(tmp); | |
12603 | ||
12604 | return ret; | |
12605 | } | |
12606 | ||
12607 | /* offset and length are dword aligned */ | |
12608 | static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len, | |
12609 | u8 *buf) | |
12610 | { | |
12611 | int i, ret = 0; | |
12612 | ||
12613 | for (i = 0; i < len; i += 4, offset += 4) { | |
b9fc7dc5 AV |
12614 | u32 page_off, phy_addr, nvram_cmd; |
12615 | __be32 data; | |
1da177e4 LT |
12616 | |
12617 | memcpy(&data, buf + i, 4); | |
b9fc7dc5 | 12618 | tw32(NVRAM_WRDATA, be32_to_cpu(data)); |
1da177e4 | 12619 | |
c6cdf436 | 12620 | page_off = offset % tp->nvram_pagesize; |
1da177e4 | 12621 | |
1820180b | 12622 | phy_addr = tg3_nvram_phys_addr(tp, offset); |
1da177e4 LT |
12623 | |
12624 | tw32(NVRAM_ADDR, phy_addr); | |
12625 | ||
12626 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR; | |
12627 | ||
c6cdf436 | 12628 | if (page_off == 0 || i == 0) |
1da177e4 | 12629 | nvram_cmd |= NVRAM_CMD_FIRST; |
f6d9a256 | 12630 | if (page_off == (tp->nvram_pagesize - 4)) |
1da177e4 LT |
12631 | nvram_cmd |= NVRAM_CMD_LAST; |
12632 | ||
12633 | if (i == (len - 4)) | |
12634 | nvram_cmd |= NVRAM_CMD_LAST; | |
12635 | ||
321d32a0 | 12636 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 && |
63c3a66f | 12637 | !tg3_flag(tp, 5755_PLUS) && |
4c987487 MC |
12638 | (tp->nvram_jedecnum == JEDEC_ST) && |
12639 | (nvram_cmd & NVRAM_CMD_FIRST)) { | |
1da177e4 LT |
12640 | |
12641 | if ((ret = tg3_nvram_exec_cmd(tp, | |
12642 | NVRAM_CMD_WREN | NVRAM_CMD_GO | | |
12643 | NVRAM_CMD_DONE))) | |
12644 | ||
12645 | break; | |
12646 | } | |
63c3a66f | 12647 | if (!tg3_flag(tp, FLASH)) { |
1da177e4 LT |
12648 | /* We always do complete word writes to eeprom. */ |
12649 | nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST); | |
12650 | } | |
12651 | ||
12652 | if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd))) | |
12653 | break; | |
12654 | } | |
12655 | return ret; | |
12656 | } | |
12657 | ||
12658 | /* offset and length are dword aligned */ | |
12659 | static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf) | |
12660 | { | |
12661 | int ret; | |
12662 | ||
63c3a66f | 12663 | if (tg3_flag(tp, EEPROM_WRITE_PROT)) { |
314fba34 MC |
12664 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl & |
12665 | ~GRC_LCLCTRL_GPIO_OUTPUT1); | |
1da177e4 LT |
12666 | udelay(40); |
12667 | } | |
12668 | ||
63c3a66f | 12669 | if (!tg3_flag(tp, NVRAM)) { |
1da177e4 | 12670 | ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf); |
859a5887 | 12671 | } else { |
1da177e4 LT |
12672 | u32 grc_mode; |
12673 | ||
ec41c7df MC |
12674 | ret = tg3_nvram_lock(tp); |
12675 | if (ret) | |
12676 | return ret; | |
1da177e4 | 12677 | |
e6af301b | 12678 | tg3_enable_nvram_access(tp); |
63c3a66f | 12679 | if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) |
1da177e4 | 12680 | tw32(NVRAM_WRITE1, 0x406); |
1da177e4 LT |
12681 | |
12682 | grc_mode = tr32(GRC_MODE); | |
12683 | tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE); | |
12684 | ||
63c3a66f | 12685 | if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) { |
1da177e4 LT |
12686 | ret = tg3_nvram_write_block_buffered(tp, offset, len, |
12687 | buf); | |
859a5887 | 12688 | } else { |
1da177e4 LT |
12689 | ret = tg3_nvram_write_block_unbuffered(tp, offset, len, |
12690 | buf); | |
12691 | } | |
12692 | ||
12693 | grc_mode = tr32(GRC_MODE); | |
12694 | tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE); | |
12695 | ||
e6af301b | 12696 | tg3_disable_nvram_access(tp); |
1da177e4 LT |
12697 | tg3_nvram_unlock(tp); |
12698 | } | |
12699 | ||
63c3a66f | 12700 | if (tg3_flag(tp, EEPROM_WRITE_PROT)) { |
314fba34 | 12701 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); |
1da177e4 LT |
12702 | udelay(40); |
12703 | } | |
12704 | ||
12705 | return ret; | |
12706 | } | |
12707 | ||
12708 | struct subsys_tbl_ent { | |
12709 | u16 subsys_vendor, subsys_devid; | |
12710 | u32 phy_id; | |
12711 | }; | |
12712 | ||
24daf2b0 | 12713 | static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = { |
1da177e4 | 12714 | /* Broadcom boards. */ |
24daf2b0 | 12715 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12716 | TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 }, |
24daf2b0 | 12717 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12718 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12719 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12720 | TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 }, |
24daf2b0 MC |
12721 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
12722 | TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 }, | |
12723 | { TG3PCI_SUBVENDOR_ID_BROADCOM, | |
79eb6904 | 12724 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12725 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12726 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 }, |
24daf2b0 MC |
12727 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
12728 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 }, | |
12729 | { TG3PCI_SUBVENDOR_ID_BROADCOM, | |
79eb6904 | 12730 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12731 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12732 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12733 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12734 | TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 }, |
24daf2b0 | 12735 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12736 | TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 }, |
1da177e4 LT |
12737 | |
12738 | /* 3com boards. */ | |
24daf2b0 | 12739 | { TG3PCI_SUBVENDOR_ID_3COM, |
79eb6904 | 12740 | TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 }, |
24daf2b0 | 12741 | { TG3PCI_SUBVENDOR_ID_3COM, |
79eb6904 | 12742 | TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 }, |
24daf2b0 MC |
12743 | { TG3PCI_SUBVENDOR_ID_3COM, |
12744 | TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 }, | |
12745 | { TG3PCI_SUBVENDOR_ID_3COM, | |
79eb6904 | 12746 | TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12747 | { TG3PCI_SUBVENDOR_ID_3COM, |
79eb6904 | 12748 | TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 }, |
1da177e4 LT |
12749 | |
12750 | /* DELL boards. */ | |
24daf2b0 | 12751 | { TG3PCI_SUBVENDOR_ID_DELL, |
79eb6904 | 12752 | TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 }, |
24daf2b0 | 12753 | { TG3PCI_SUBVENDOR_ID_DELL, |
79eb6904 | 12754 | TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 }, |
24daf2b0 | 12755 | { TG3PCI_SUBVENDOR_ID_DELL, |
79eb6904 | 12756 | TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 }, |
24daf2b0 | 12757 | { TG3PCI_SUBVENDOR_ID_DELL, |
79eb6904 | 12758 | TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 }, |
1da177e4 LT |
12759 | |
12760 | /* Compaq boards. */ | |
24daf2b0 | 12761 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
79eb6904 | 12762 | TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12763 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
79eb6904 | 12764 | TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 }, |
24daf2b0 MC |
12765 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
12766 | TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 }, | |
12767 | { TG3PCI_SUBVENDOR_ID_COMPAQ, | |
79eb6904 | 12768 | TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12769 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
79eb6904 | 12770 | TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 }, |
1da177e4 LT |
12771 | |
12772 | /* IBM boards. */ | |
24daf2b0 MC |
12773 | { TG3PCI_SUBVENDOR_ID_IBM, |
12774 | TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 } | |
1da177e4 LT |
12775 | }; |
12776 | ||
24daf2b0 | 12777 | static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp) |
1da177e4 LT |
12778 | { |
12779 | int i; | |
12780 | ||
12781 | for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) { | |
12782 | if ((subsys_id_to_phy_id[i].subsys_vendor == | |
12783 | tp->pdev->subsystem_vendor) && | |
12784 | (subsys_id_to_phy_id[i].subsys_devid == | |
12785 | tp->pdev->subsystem_device)) | |
12786 | return &subsys_id_to_phy_id[i]; | |
12787 | } | |
12788 | return NULL; | |
12789 | } | |
12790 | ||
7d0c41ef | 12791 | static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp) |
1da177e4 | 12792 | { |
1da177e4 | 12793 | u32 val; |
f49639e6 | 12794 | |
79eb6904 | 12795 | tp->phy_id = TG3_PHY_ID_INVALID; |
7d0c41ef MC |
12796 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; |
12797 | ||
a85feb8c | 12798 | /* Assume an onboard device and WOL capable by default. */ |
63c3a66f JP |
12799 | tg3_flag_set(tp, EEPROM_WRITE_PROT); |
12800 | tg3_flag_set(tp, WOL_CAP); | |
72b845e0 | 12801 | |
b5d3772c | 12802 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
9d26e213 | 12803 | if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) { |
63c3a66f JP |
12804 | tg3_flag_clear(tp, EEPROM_WRITE_PROT); |
12805 | tg3_flag_set(tp, IS_NIC); | |
9d26e213 | 12806 | } |
0527ba35 MC |
12807 | val = tr32(VCPU_CFGSHDW); |
12808 | if (val & VCPU_CFGSHDW_ASPM_DBNC) | |
63c3a66f | 12809 | tg3_flag_set(tp, ASPM_WORKAROUND); |
0527ba35 | 12810 | if ((val & VCPU_CFGSHDW_WOL_ENABLE) && |
6fdbab9d | 12811 | (val & VCPU_CFGSHDW_WOL_MAGPKT)) { |
63c3a66f | 12812 | tg3_flag_set(tp, WOL_ENABLE); |
6fdbab9d RW |
12813 | device_set_wakeup_enable(&tp->pdev->dev, true); |
12814 | } | |
05ac4cb7 | 12815 | goto done; |
b5d3772c MC |
12816 | } |
12817 | ||
1da177e4 LT |
12818 | tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); |
12819 | if (val == NIC_SRAM_DATA_SIG_MAGIC) { | |
12820 | u32 nic_cfg, led_cfg; | |
a9daf367 | 12821 | u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id; |
7d0c41ef | 12822 | int eeprom_phy_serdes = 0; |
1da177e4 LT |
12823 | |
12824 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); | |
12825 | tp->nic_sram_data_cfg = nic_cfg; | |
12826 | ||
12827 | tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver); | |
12828 | ver >>= NIC_SRAM_DATA_VER_SHIFT; | |
6ff6f81d MC |
12829 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && |
12830 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 && | |
12831 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703 && | |
1da177e4 LT |
12832 | (ver > 0) && (ver < 0x100)) |
12833 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2); | |
12834 | ||
a9daf367 MC |
12835 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) |
12836 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4); | |
12837 | ||
1da177e4 LT |
12838 | if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) == |
12839 | NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER) | |
12840 | eeprom_phy_serdes = 1; | |
12841 | ||
12842 | tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id); | |
12843 | if (nic_phy_id != 0) { | |
12844 | u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK; | |
12845 | u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK; | |
12846 | ||
12847 | eeprom_phy_id = (id1 >> 16) << 10; | |
12848 | eeprom_phy_id |= (id2 & 0xfc00) << 16; | |
12849 | eeprom_phy_id |= (id2 & 0x03ff) << 0; | |
12850 | } else | |
12851 | eeprom_phy_id = 0; | |
12852 | ||
7d0c41ef | 12853 | tp->phy_id = eeprom_phy_id; |
747e8f8b | 12854 | if (eeprom_phy_serdes) { |
63c3a66f | 12855 | if (!tg3_flag(tp, 5705_PLUS)) |
f07e9af3 | 12856 | tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; |
a50d0796 | 12857 | else |
f07e9af3 | 12858 | tp->phy_flags |= TG3_PHYFLG_MII_SERDES; |
747e8f8b | 12859 | } |
7d0c41ef | 12860 | |
63c3a66f | 12861 | if (tg3_flag(tp, 5750_PLUS)) |
1da177e4 LT |
12862 | led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK | |
12863 | SHASTA_EXT_LED_MODE_MASK); | |
cbf46853 | 12864 | else |
1da177e4 LT |
12865 | led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK; |
12866 | ||
12867 | switch (led_cfg) { | |
12868 | default: | |
12869 | case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1: | |
12870 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
12871 | break; | |
12872 | ||
12873 | case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2: | |
12874 | tp->led_ctrl = LED_CTRL_MODE_PHY_2; | |
12875 | break; | |
12876 | ||
12877 | case NIC_SRAM_DATA_CFG_LED_MODE_MAC: | |
12878 | tp->led_ctrl = LED_CTRL_MODE_MAC; | |
9ba27794 MC |
12879 | |
12880 | /* Default to PHY_1_MODE if 0 (MAC_MODE) is | |
12881 | * read on some older 5700/5701 bootcode. | |
12882 | */ | |
12883 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | |
12884 | ASIC_REV_5700 || | |
12885 | GET_ASIC_REV(tp->pci_chip_rev_id) == | |
12886 | ASIC_REV_5701) | |
12887 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
12888 | ||
1da177e4 LT |
12889 | break; |
12890 | ||
12891 | case SHASTA_EXT_LED_SHARED: | |
12892 | tp->led_ctrl = LED_CTRL_MODE_SHARED; | |
12893 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 && | |
12894 | tp->pci_chip_rev_id != CHIPREV_ID_5750_A1) | |
12895 | tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | | |
12896 | LED_CTRL_MODE_PHY_2); | |
12897 | break; | |
12898 | ||
12899 | case SHASTA_EXT_LED_MAC: | |
12900 | tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC; | |
12901 | break; | |
12902 | ||
12903 | case SHASTA_EXT_LED_COMBO: | |
12904 | tp->led_ctrl = LED_CTRL_MODE_COMBO; | |
12905 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) | |
12906 | tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | | |
12907 | LED_CTRL_MODE_PHY_2); | |
12908 | break; | |
12909 | ||
855e1111 | 12910 | } |
1da177e4 LT |
12911 | |
12912 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
12913 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) && | |
12914 | tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL) | |
12915 | tp->led_ctrl = LED_CTRL_MODE_PHY_2; | |
12916 | ||
b2a5c19c MC |
12917 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) |
12918 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
5f60891b | 12919 | |
9d26e213 | 12920 | if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) { |
63c3a66f | 12921 | tg3_flag_set(tp, EEPROM_WRITE_PROT); |
9d26e213 MC |
12922 | if ((tp->pdev->subsystem_vendor == |
12923 | PCI_VENDOR_ID_ARIMA) && | |
12924 | (tp->pdev->subsystem_device == 0x205a || | |
12925 | tp->pdev->subsystem_device == 0x2063)) | |
63c3a66f | 12926 | tg3_flag_clear(tp, EEPROM_WRITE_PROT); |
9d26e213 | 12927 | } else { |
63c3a66f JP |
12928 | tg3_flag_clear(tp, EEPROM_WRITE_PROT); |
12929 | tg3_flag_set(tp, IS_NIC); | |
9d26e213 | 12930 | } |
1da177e4 LT |
12931 | |
12932 | if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) { | |
63c3a66f JP |
12933 | tg3_flag_set(tp, ENABLE_ASF); |
12934 | if (tg3_flag(tp, 5750_PLUS)) | |
12935 | tg3_flag_set(tp, ASF_NEW_HANDSHAKE); | |
1da177e4 | 12936 | } |
b2b98d4a MC |
12937 | |
12938 | if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) && | |
63c3a66f JP |
12939 | tg3_flag(tp, 5750_PLUS)) |
12940 | tg3_flag_set(tp, ENABLE_APE); | |
b2b98d4a | 12941 | |
f07e9af3 | 12942 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES && |
a85feb8c | 12943 | !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)) |
63c3a66f | 12944 | tg3_flag_clear(tp, WOL_CAP); |
1da177e4 | 12945 | |
63c3a66f | 12946 | if (tg3_flag(tp, WOL_CAP) && |
6fdbab9d | 12947 | (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) { |
63c3a66f | 12948 | tg3_flag_set(tp, WOL_ENABLE); |
6fdbab9d RW |
12949 | device_set_wakeup_enable(&tp->pdev->dev, true); |
12950 | } | |
0527ba35 | 12951 | |
1da177e4 | 12952 | if (cfg2 & (1 << 17)) |
f07e9af3 | 12953 | tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING; |
1da177e4 LT |
12954 | |
12955 | /* serdes signal pre-emphasis in register 0x590 set by */ | |
12956 | /* bootcode if bit 18 is set */ | |
12957 | if (cfg2 & (1 << 18)) | |
f07e9af3 | 12958 | tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS; |
8ed5d97e | 12959 | |
63c3a66f JP |
12960 | if ((tg3_flag(tp, 57765_PLUS) || |
12961 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && | |
12962 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) && | |
6833c043 | 12963 | (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN)) |
f07e9af3 | 12964 | tp->phy_flags |= TG3_PHYFLG_ENABLE_APD; |
6833c043 | 12965 | |
63c3a66f | 12966 | if (tg3_flag(tp, PCI_EXPRESS) && |
8c69b1e7 | 12967 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && |
63c3a66f | 12968 | !tg3_flag(tp, 57765_PLUS)) { |
8ed5d97e MC |
12969 | u32 cfg3; |
12970 | ||
12971 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3); | |
12972 | if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE) | |
63c3a66f | 12973 | tg3_flag_set(tp, ASPM_WORKAROUND); |
8ed5d97e | 12974 | } |
a9daf367 | 12975 | |
14417063 | 12976 | if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE) |
63c3a66f | 12977 | tg3_flag_set(tp, RGMII_INBAND_DISABLE); |
a9daf367 | 12978 | if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN) |
63c3a66f | 12979 | tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN); |
a9daf367 | 12980 | if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN) |
63c3a66f | 12981 | tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN); |
1da177e4 | 12982 | } |
05ac4cb7 | 12983 | done: |
63c3a66f | 12984 | if (tg3_flag(tp, WOL_CAP)) |
43067ed8 | 12985 | device_set_wakeup_enable(&tp->pdev->dev, |
63c3a66f | 12986 | tg3_flag(tp, WOL_ENABLE)); |
43067ed8 RW |
12987 | else |
12988 | device_set_wakeup_capable(&tp->pdev->dev, false); | |
7d0c41ef MC |
12989 | } |
12990 | ||
b2a5c19c MC |
12991 | static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd) |
12992 | { | |
12993 | int i; | |
12994 | u32 val; | |
12995 | ||
12996 | tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START); | |
12997 | tw32(OTP_CTRL, cmd); | |
12998 | ||
12999 | /* Wait for up to 1 ms for command to execute. */ | |
13000 | for (i = 0; i < 100; i++) { | |
13001 | val = tr32(OTP_STATUS); | |
13002 | if (val & OTP_STATUS_CMD_DONE) | |
13003 | break; | |
13004 | udelay(10); | |
13005 | } | |
13006 | ||
13007 | return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY; | |
13008 | } | |
13009 | ||
13010 | /* Read the gphy configuration from the OTP region of the chip. The gphy | |
13011 | * configuration is a 32-bit value that straddles the alignment boundary. | |
13012 | * We do two 32-bit reads and then shift and merge the results. | |
13013 | */ | |
13014 | static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp) | |
13015 | { | |
13016 | u32 bhalf_otp, thalf_otp; | |
13017 | ||
13018 | tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC); | |
13019 | ||
13020 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT)) | |
13021 | return 0; | |
13022 | ||
13023 | tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1); | |
13024 | ||
13025 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) | |
13026 | return 0; | |
13027 | ||
13028 | thalf_otp = tr32(OTP_READ_DATA); | |
13029 | ||
13030 | tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2); | |
13031 | ||
13032 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) | |
13033 | return 0; | |
13034 | ||
13035 | bhalf_otp = tr32(OTP_READ_DATA); | |
13036 | ||
13037 | return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16); | |
13038 | } | |
13039 | ||
e256f8a3 MC |
13040 | static void __devinit tg3_phy_init_link_config(struct tg3 *tp) |
13041 | { | |
13042 | u32 adv = ADVERTISED_Autoneg | | |
13043 | ADVERTISED_Pause; | |
13044 | ||
13045 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) | |
13046 | adv |= ADVERTISED_1000baseT_Half | | |
13047 | ADVERTISED_1000baseT_Full; | |
13048 | ||
13049 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) | |
13050 | adv |= ADVERTISED_100baseT_Half | | |
13051 | ADVERTISED_100baseT_Full | | |
13052 | ADVERTISED_10baseT_Half | | |
13053 | ADVERTISED_10baseT_Full | | |
13054 | ADVERTISED_TP; | |
13055 | else | |
13056 | adv |= ADVERTISED_FIBRE; | |
13057 | ||
13058 | tp->link_config.advertising = adv; | |
13059 | tp->link_config.speed = SPEED_INVALID; | |
13060 | tp->link_config.duplex = DUPLEX_INVALID; | |
13061 | tp->link_config.autoneg = AUTONEG_ENABLE; | |
13062 | tp->link_config.active_speed = SPEED_INVALID; | |
13063 | tp->link_config.active_duplex = DUPLEX_INVALID; | |
13064 | tp->link_config.orig_speed = SPEED_INVALID; | |
13065 | tp->link_config.orig_duplex = DUPLEX_INVALID; | |
13066 | tp->link_config.orig_autoneg = AUTONEG_INVALID; | |
13067 | } | |
13068 | ||
7d0c41ef MC |
13069 | static int __devinit tg3_phy_probe(struct tg3 *tp) |
13070 | { | |
13071 | u32 hw_phy_id_1, hw_phy_id_2; | |
13072 | u32 hw_phy_id, hw_phy_id_masked; | |
13073 | int err; | |
1da177e4 | 13074 | |
e256f8a3 | 13075 | /* flow control autonegotiation is default behavior */ |
63c3a66f | 13076 | tg3_flag_set(tp, PAUSE_AUTONEG); |
e256f8a3 MC |
13077 | tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; |
13078 | ||
63c3a66f | 13079 | if (tg3_flag(tp, USE_PHYLIB)) |
b02fd9e3 MC |
13080 | return tg3_phy_init(tp); |
13081 | ||
1da177e4 | 13082 | /* Reading the PHY ID register can conflict with ASF |
877d0310 | 13083 | * firmware access to the PHY hardware. |
1da177e4 LT |
13084 | */ |
13085 | err = 0; | |
63c3a66f | 13086 | if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) { |
79eb6904 | 13087 | hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID; |
1da177e4 LT |
13088 | } else { |
13089 | /* Now read the physical PHY_ID from the chip and verify | |
13090 | * that it is sane. If it doesn't look good, we fall back | |
13091 | * to either the hard-coded table based PHY_ID and failing | |
13092 | * that the value found in the eeprom area. | |
13093 | */ | |
13094 | err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1); | |
13095 | err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2); | |
13096 | ||
13097 | hw_phy_id = (hw_phy_id_1 & 0xffff) << 10; | |
13098 | hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16; | |
13099 | hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0; | |
13100 | ||
79eb6904 | 13101 | hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK; |
1da177e4 LT |
13102 | } |
13103 | ||
79eb6904 | 13104 | if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) { |
1da177e4 | 13105 | tp->phy_id = hw_phy_id; |
79eb6904 | 13106 | if (hw_phy_id_masked == TG3_PHY_ID_BCM8002) |
f07e9af3 | 13107 | tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; |
da6b2d01 | 13108 | else |
f07e9af3 | 13109 | tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES; |
1da177e4 | 13110 | } else { |
79eb6904 | 13111 | if (tp->phy_id != TG3_PHY_ID_INVALID) { |
7d0c41ef MC |
13112 | /* Do nothing, phy ID already set up in |
13113 | * tg3_get_eeprom_hw_cfg(). | |
13114 | */ | |
1da177e4 LT |
13115 | } else { |
13116 | struct subsys_tbl_ent *p; | |
13117 | ||
13118 | /* No eeprom signature? Try the hardcoded | |
13119 | * subsys device table. | |
13120 | */ | |
24daf2b0 | 13121 | p = tg3_lookup_by_subsys(tp); |
1da177e4 LT |
13122 | if (!p) |
13123 | return -ENODEV; | |
13124 | ||
13125 | tp->phy_id = p->phy_id; | |
13126 | if (!tp->phy_id || | |
79eb6904 | 13127 | tp->phy_id == TG3_PHY_ID_BCM8002) |
f07e9af3 | 13128 | tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; |
1da177e4 LT |
13129 | } |
13130 | } | |
13131 | ||
a6b68dab MC |
13132 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && |
13133 | ((tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 && | |
13134 | tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) || | |
13135 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 && | |
13136 | tp->pci_chip_rev_id != CHIPREV_ID_57765_A0))) | |
52b02d04 MC |
13137 | tp->phy_flags |= TG3_PHYFLG_EEE_CAP; |
13138 | ||
e256f8a3 MC |
13139 | tg3_phy_init_link_config(tp); |
13140 | ||
f07e9af3 | 13141 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && |
63c3a66f JP |
13142 | !tg3_flag(tp, ENABLE_APE) && |
13143 | !tg3_flag(tp, ENABLE_ASF)) { | |
42b64a45 | 13144 | u32 bmsr, mask; |
1da177e4 LT |
13145 | |
13146 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
13147 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
13148 | (bmsr & BMSR_LSTATUS)) | |
13149 | goto skip_phy_reset; | |
6aa20a22 | 13150 | |
1da177e4 LT |
13151 | err = tg3_phy_reset(tp); |
13152 | if (err) | |
13153 | return err; | |
13154 | ||
42b64a45 | 13155 | tg3_phy_set_wirespeed(tp); |
1da177e4 | 13156 | |
3600d918 MC |
13157 | mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | |
13158 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | | |
13159 | ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full); | |
13160 | if (!tg3_copper_is_advertising_all(tp, mask)) { | |
42b64a45 MC |
13161 | tg3_phy_autoneg_cfg(tp, tp->link_config.advertising, |
13162 | tp->link_config.flowctrl); | |
1da177e4 LT |
13163 | |
13164 | tg3_writephy(tp, MII_BMCR, | |
13165 | BMCR_ANENABLE | BMCR_ANRESTART); | |
13166 | } | |
1da177e4 LT |
13167 | } |
13168 | ||
13169 | skip_phy_reset: | |
79eb6904 | 13170 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { |
1da177e4 LT |
13171 | err = tg3_init_5401phy_dsp(tp); |
13172 | if (err) | |
13173 | return err; | |
1da177e4 | 13174 | |
1da177e4 LT |
13175 | err = tg3_init_5401phy_dsp(tp); |
13176 | } | |
13177 | ||
1da177e4 LT |
13178 | return err; |
13179 | } | |
13180 | ||
184b8904 | 13181 | static void __devinit tg3_read_vpd(struct tg3 *tp) |
1da177e4 | 13182 | { |
a4a8bb15 | 13183 | u8 *vpd_data; |
4181b2c8 | 13184 | unsigned int block_end, rosize, len; |
184b8904 | 13185 | int j, i = 0; |
a4a8bb15 | 13186 | |
c3e94500 | 13187 | vpd_data = (u8 *)tg3_vpd_readblock(tp); |
a4a8bb15 MC |
13188 | if (!vpd_data) |
13189 | goto out_no_vpd; | |
1da177e4 | 13190 | |
4181b2c8 MC |
13191 | i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN, |
13192 | PCI_VPD_LRDT_RO_DATA); | |
13193 | if (i < 0) | |
13194 | goto out_not_found; | |
1da177e4 | 13195 | |
4181b2c8 MC |
13196 | rosize = pci_vpd_lrdt_size(&vpd_data[i]); |
13197 | block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize; | |
13198 | i += PCI_VPD_LRDT_TAG_SIZE; | |
1da177e4 | 13199 | |
4181b2c8 MC |
13200 | if (block_end > TG3_NVM_VPD_LEN) |
13201 | goto out_not_found; | |
af2c6a4a | 13202 | |
184b8904 MC |
13203 | j = pci_vpd_find_info_keyword(vpd_data, i, rosize, |
13204 | PCI_VPD_RO_KEYWORD_MFR_ID); | |
13205 | if (j > 0) { | |
13206 | len = pci_vpd_info_field_size(&vpd_data[j]); | |
13207 | ||
13208 | j += PCI_VPD_INFO_FLD_HDR_SIZE; | |
13209 | if (j + len > block_end || len != 4 || | |
13210 | memcmp(&vpd_data[j], "1028", 4)) | |
13211 | goto partno; | |
13212 | ||
13213 | j = pci_vpd_find_info_keyword(vpd_data, i, rosize, | |
13214 | PCI_VPD_RO_KEYWORD_VENDOR0); | |
13215 | if (j < 0) | |
13216 | goto partno; | |
13217 | ||
13218 | len = pci_vpd_info_field_size(&vpd_data[j]); | |
13219 | ||
13220 | j += PCI_VPD_INFO_FLD_HDR_SIZE; | |
13221 | if (j + len > block_end) | |
13222 | goto partno; | |
13223 | ||
13224 | memcpy(tp->fw_ver, &vpd_data[j], len); | |
13225 | strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1); | |
13226 | } | |
13227 | ||
13228 | partno: | |
4181b2c8 MC |
13229 | i = pci_vpd_find_info_keyword(vpd_data, i, rosize, |
13230 | PCI_VPD_RO_KEYWORD_PARTNO); | |
13231 | if (i < 0) | |
13232 | goto out_not_found; | |
af2c6a4a | 13233 | |
4181b2c8 | 13234 | len = pci_vpd_info_field_size(&vpd_data[i]); |
1da177e4 | 13235 | |
4181b2c8 MC |
13236 | i += PCI_VPD_INFO_FLD_HDR_SIZE; |
13237 | if (len > TG3_BPN_SIZE || | |
13238 | (len + i) > TG3_NVM_VPD_LEN) | |
13239 | goto out_not_found; | |
1da177e4 | 13240 | |
4181b2c8 | 13241 | memcpy(tp->board_part_number, &vpd_data[i], len); |
1da177e4 | 13242 | |
1da177e4 | 13243 | out_not_found: |
a4a8bb15 | 13244 | kfree(vpd_data); |
37a949c5 | 13245 | if (tp->board_part_number[0]) |
a4a8bb15 MC |
13246 | return; |
13247 | ||
13248 | out_no_vpd: | |
37a949c5 MC |
13249 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) { |
13250 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717) | |
13251 | strcpy(tp->board_part_number, "BCM5717"); | |
13252 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718) | |
13253 | strcpy(tp->board_part_number, "BCM5718"); | |
13254 | else | |
13255 | goto nomatch; | |
13256 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { | |
13257 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780) | |
13258 | strcpy(tp->board_part_number, "BCM57780"); | |
13259 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760) | |
13260 | strcpy(tp->board_part_number, "BCM57760"); | |
13261 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790) | |
13262 | strcpy(tp->board_part_number, "BCM57790"); | |
13263 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788) | |
13264 | strcpy(tp->board_part_number, "BCM57788"); | |
13265 | else | |
13266 | goto nomatch; | |
13267 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) { | |
13268 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761) | |
13269 | strcpy(tp->board_part_number, "BCM57761"); | |
13270 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765) | |
13271 | strcpy(tp->board_part_number, "BCM57765"); | |
13272 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781) | |
13273 | strcpy(tp->board_part_number, "BCM57781"); | |
13274 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785) | |
13275 | strcpy(tp->board_part_number, "BCM57785"); | |
13276 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791) | |
13277 | strcpy(tp->board_part_number, "BCM57791"); | |
13278 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795) | |
13279 | strcpy(tp->board_part_number, "BCM57795"); | |
13280 | else | |
13281 | goto nomatch; | |
13282 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
b5d3772c | 13283 | strcpy(tp->board_part_number, "BCM95906"); |
37a949c5 MC |
13284 | } else { |
13285 | nomatch: | |
b5d3772c | 13286 | strcpy(tp->board_part_number, "none"); |
37a949c5 | 13287 | } |
1da177e4 LT |
13288 | } |
13289 | ||
9c8a620e MC |
13290 | static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset) |
13291 | { | |
13292 | u32 val; | |
13293 | ||
e4f34110 | 13294 | if (tg3_nvram_read(tp, offset, &val) || |
9c8a620e | 13295 | (val & 0xfc000000) != 0x0c000000 || |
e4f34110 | 13296 | tg3_nvram_read(tp, offset + 4, &val) || |
9c8a620e MC |
13297 | val != 0) |
13298 | return 0; | |
13299 | ||
13300 | return 1; | |
13301 | } | |
13302 | ||
acd9c119 MC |
13303 | static void __devinit tg3_read_bc_ver(struct tg3 *tp) |
13304 | { | |
ff3a7cb2 | 13305 | u32 val, offset, start, ver_offset; |
75f9936e | 13306 | int i, dst_off; |
ff3a7cb2 | 13307 | bool newver = false; |
acd9c119 MC |
13308 | |
13309 | if (tg3_nvram_read(tp, 0xc, &offset) || | |
13310 | tg3_nvram_read(tp, 0x4, &start)) | |
13311 | return; | |
13312 | ||
13313 | offset = tg3_nvram_logical_addr(tp, offset); | |
13314 | ||
ff3a7cb2 | 13315 | if (tg3_nvram_read(tp, offset, &val)) |
acd9c119 MC |
13316 | return; |
13317 | ||
ff3a7cb2 MC |
13318 | if ((val & 0xfc000000) == 0x0c000000) { |
13319 | if (tg3_nvram_read(tp, offset + 4, &val)) | |
acd9c119 MC |
13320 | return; |
13321 | ||
ff3a7cb2 MC |
13322 | if (val == 0) |
13323 | newver = true; | |
13324 | } | |
13325 | ||
75f9936e MC |
13326 | dst_off = strlen(tp->fw_ver); |
13327 | ||
ff3a7cb2 | 13328 | if (newver) { |
75f9936e MC |
13329 | if (TG3_VER_SIZE - dst_off < 16 || |
13330 | tg3_nvram_read(tp, offset + 8, &ver_offset)) | |
ff3a7cb2 MC |
13331 | return; |
13332 | ||
13333 | offset = offset + ver_offset - start; | |
13334 | for (i = 0; i < 16; i += 4) { | |
13335 | __be32 v; | |
13336 | if (tg3_nvram_read_be32(tp, offset + i, &v)) | |
13337 | return; | |
13338 | ||
75f9936e | 13339 | memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v)); |
ff3a7cb2 MC |
13340 | } |
13341 | } else { | |
13342 | u32 major, minor; | |
13343 | ||
13344 | if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset)) | |
13345 | return; | |
13346 | ||
13347 | major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >> | |
13348 | TG3_NVM_BCVER_MAJSFT; | |
13349 | minor = ver_offset & TG3_NVM_BCVER_MINMSK; | |
75f9936e MC |
13350 | snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off, |
13351 | "v%d.%02d", major, minor); | |
acd9c119 MC |
13352 | } |
13353 | } | |
13354 | ||
a6f6cb1c MC |
13355 | static void __devinit tg3_read_hwsb_ver(struct tg3 *tp) |
13356 | { | |
13357 | u32 val, major, minor; | |
13358 | ||
13359 | /* Use native endian representation */ | |
13360 | if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val)) | |
13361 | return; | |
13362 | ||
13363 | major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >> | |
13364 | TG3_NVM_HWSB_CFG1_MAJSFT; | |
13365 | minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >> | |
13366 | TG3_NVM_HWSB_CFG1_MINSFT; | |
13367 | ||
13368 | snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor); | |
13369 | } | |
13370 | ||
dfe00d7d MC |
13371 | static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val) |
13372 | { | |
13373 | u32 offset, major, minor, build; | |
13374 | ||
75f9936e | 13375 | strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1); |
dfe00d7d MC |
13376 | |
13377 | if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1) | |
13378 | return; | |
13379 | ||
13380 | switch (val & TG3_EEPROM_SB_REVISION_MASK) { | |
13381 | case TG3_EEPROM_SB_REVISION_0: | |
13382 | offset = TG3_EEPROM_SB_F1R0_EDH_OFF; | |
13383 | break; | |
13384 | case TG3_EEPROM_SB_REVISION_2: | |
13385 | offset = TG3_EEPROM_SB_F1R2_EDH_OFF; | |
13386 | break; | |
13387 | case TG3_EEPROM_SB_REVISION_3: | |
13388 | offset = TG3_EEPROM_SB_F1R3_EDH_OFF; | |
13389 | break; | |
a4153d40 MC |
13390 | case TG3_EEPROM_SB_REVISION_4: |
13391 | offset = TG3_EEPROM_SB_F1R4_EDH_OFF; | |
13392 | break; | |
13393 | case TG3_EEPROM_SB_REVISION_5: | |
13394 | offset = TG3_EEPROM_SB_F1R5_EDH_OFF; | |
13395 | break; | |
bba226ac MC |
13396 | case TG3_EEPROM_SB_REVISION_6: |
13397 | offset = TG3_EEPROM_SB_F1R6_EDH_OFF; | |
13398 | break; | |
dfe00d7d MC |
13399 | default: |
13400 | return; | |
13401 | } | |
13402 | ||
e4f34110 | 13403 | if (tg3_nvram_read(tp, offset, &val)) |
dfe00d7d MC |
13404 | return; |
13405 | ||
13406 | build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >> | |
13407 | TG3_EEPROM_SB_EDH_BLD_SHFT; | |
13408 | major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >> | |
13409 | TG3_EEPROM_SB_EDH_MAJ_SHFT; | |
13410 | minor = val & TG3_EEPROM_SB_EDH_MIN_MASK; | |
13411 | ||
13412 | if (minor > 99 || build > 26) | |
13413 | return; | |
13414 | ||
75f9936e MC |
13415 | offset = strlen(tp->fw_ver); |
13416 | snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset, | |
13417 | " v%d.%02d", major, minor); | |
dfe00d7d MC |
13418 | |
13419 | if (build > 0) { | |
75f9936e MC |
13420 | offset = strlen(tp->fw_ver); |
13421 | if (offset < TG3_VER_SIZE - 1) | |
13422 | tp->fw_ver[offset] = 'a' + build - 1; | |
dfe00d7d MC |
13423 | } |
13424 | } | |
13425 | ||
acd9c119 | 13426 | static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp) |
c4e6575c MC |
13427 | { |
13428 | u32 val, offset, start; | |
acd9c119 | 13429 | int i, vlen; |
9c8a620e MC |
13430 | |
13431 | for (offset = TG3_NVM_DIR_START; | |
13432 | offset < TG3_NVM_DIR_END; | |
13433 | offset += TG3_NVM_DIRENT_SIZE) { | |
e4f34110 | 13434 | if (tg3_nvram_read(tp, offset, &val)) |
c4e6575c MC |
13435 | return; |
13436 | ||
9c8a620e MC |
13437 | if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI) |
13438 | break; | |
13439 | } | |
13440 | ||
13441 | if (offset == TG3_NVM_DIR_END) | |
13442 | return; | |
13443 | ||
63c3a66f | 13444 | if (!tg3_flag(tp, 5705_PLUS)) |
9c8a620e | 13445 | start = 0x08000000; |
e4f34110 | 13446 | else if (tg3_nvram_read(tp, offset - 4, &start)) |
9c8a620e MC |
13447 | return; |
13448 | ||
e4f34110 | 13449 | if (tg3_nvram_read(tp, offset + 4, &offset) || |
9c8a620e | 13450 | !tg3_fw_img_is_valid(tp, offset) || |
e4f34110 | 13451 | tg3_nvram_read(tp, offset + 8, &val)) |
9c8a620e MC |
13452 | return; |
13453 | ||
13454 | offset += val - start; | |
13455 | ||
acd9c119 | 13456 | vlen = strlen(tp->fw_ver); |
9c8a620e | 13457 | |
acd9c119 MC |
13458 | tp->fw_ver[vlen++] = ','; |
13459 | tp->fw_ver[vlen++] = ' '; | |
9c8a620e MC |
13460 | |
13461 | for (i = 0; i < 4; i++) { | |
a9dc529d MC |
13462 | __be32 v; |
13463 | if (tg3_nvram_read_be32(tp, offset, &v)) | |
c4e6575c MC |
13464 | return; |
13465 | ||
b9fc7dc5 | 13466 | offset += sizeof(v); |
c4e6575c | 13467 | |
acd9c119 MC |
13468 | if (vlen > TG3_VER_SIZE - sizeof(v)) { |
13469 | memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen); | |
9c8a620e | 13470 | break; |
c4e6575c | 13471 | } |
9c8a620e | 13472 | |
acd9c119 MC |
13473 | memcpy(&tp->fw_ver[vlen], &v, sizeof(v)); |
13474 | vlen += sizeof(v); | |
c4e6575c | 13475 | } |
acd9c119 MC |
13476 | } |
13477 | ||
7fd76445 MC |
13478 | static void __devinit tg3_read_dash_ver(struct tg3 *tp) |
13479 | { | |
13480 | int vlen; | |
13481 | u32 apedata; | |
ecc79648 | 13482 | char *fwtype; |
7fd76445 | 13483 | |
63c3a66f | 13484 | if (!tg3_flag(tp, ENABLE_APE) || !tg3_flag(tp, ENABLE_ASF)) |
7fd76445 MC |
13485 | return; |
13486 | ||
13487 | apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); | |
13488 | if (apedata != APE_SEG_SIG_MAGIC) | |
13489 | return; | |
13490 | ||
13491 | apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); | |
13492 | if (!(apedata & APE_FW_STATUS_READY)) | |
13493 | return; | |
13494 | ||
13495 | apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION); | |
13496 | ||
dc6d0744 | 13497 | if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) { |
63c3a66f | 13498 | tg3_flag_set(tp, APE_HAS_NCSI); |
ecc79648 | 13499 | fwtype = "NCSI"; |
dc6d0744 | 13500 | } else { |
ecc79648 | 13501 | fwtype = "DASH"; |
dc6d0744 | 13502 | } |
ecc79648 | 13503 | |
7fd76445 MC |
13504 | vlen = strlen(tp->fw_ver); |
13505 | ||
ecc79648 MC |
13506 | snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d", |
13507 | fwtype, | |
7fd76445 MC |
13508 | (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT, |
13509 | (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT, | |
13510 | (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT, | |
13511 | (apedata & APE_FW_VERSION_BLDMSK)); | |
13512 | } | |
13513 | ||
acd9c119 MC |
13514 | static void __devinit tg3_read_fw_ver(struct tg3 *tp) |
13515 | { | |
13516 | u32 val; | |
75f9936e | 13517 | bool vpd_vers = false; |
acd9c119 | 13518 | |
75f9936e MC |
13519 | if (tp->fw_ver[0] != 0) |
13520 | vpd_vers = true; | |
df259d8c | 13521 | |
63c3a66f | 13522 | if (tg3_flag(tp, NO_NVRAM)) { |
75f9936e | 13523 | strcat(tp->fw_ver, "sb"); |
df259d8c MC |
13524 | return; |
13525 | } | |
13526 | ||
acd9c119 MC |
13527 | if (tg3_nvram_read(tp, 0, &val)) |
13528 | return; | |
13529 | ||
13530 | if (val == TG3_EEPROM_MAGIC) | |
13531 | tg3_read_bc_ver(tp); | |
13532 | else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) | |
13533 | tg3_read_sb_ver(tp, val); | |
a6f6cb1c MC |
13534 | else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW) |
13535 | tg3_read_hwsb_ver(tp); | |
acd9c119 MC |
13536 | else |
13537 | return; | |
13538 | ||
c9cab24e | 13539 | if (vpd_vers) |
75f9936e | 13540 | goto done; |
acd9c119 | 13541 | |
c9cab24e MC |
13542 | if (tg3_flag(tp, ENABLE_APE)) { |
13543 | if (tg3_flag(tp, ENABLE_ASF)) | |
13544 | tg3_read_dash_ver(tp); | |
13545 | } else if (tg3_flag(tp, ENABLE_ASF)) { | |
13546 | tg3_read_mgmtfw_ver(tp); | |
13547 | } | |
9c8a620e | 13548 | |
75f9936e | 13549 | done: |
9c8a620e | 13550 | tp->fw_ver[TG3_VER_SIZE - 1] = 0; |
c4e6575c MC |
13551 | } |
13552 | ||
7544b097 MC |
13553 | static struct pci_dev * __devinit tg3_find_peer(struct tg3 *); |
13554 | ||
7cb32cf2 MC |
13555 | static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp) |
13556 | { | |
63c3a66f | 13557 | if (tg3_flag(tp, LRG_PROD_RING_CAP)) |
de9f5230 | 13558 | return TG3_RX_RET_MAX_SIZE_5717; |
63c3a66f | 13559 | else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) |
de9f5230 | 13560 | return TG3_RX_RET_MAX_SIZE_5700; |
7cb32cf2 | 13561 | else |
de9f5230 | 13562 | return TG3_RX_RET_MAX_SIZE_5705; |
7cb32cf2 MC |
13563 | } |
13564 | ||
4143470c | 13565 | static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = { |
895950c2 JP |
13566 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) }, |
13567 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) }, | |
13568 | { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) }, | |
13569 | { }, | |
13570 | }; | |
13571 | ||
1da177e4 LT |
13572 | static int __devinit tg3_get_invariants(struct tg3 *tp) |
13573 | { | |
1da177e4 | 13574 | u32 misc_ctrl_reg; |
1da177e4 LT |
13575 | u32 pci_state_reg, grc_misc_cfg; |
13576 | u32 val; | |
13577 | u16 pci_cmd; | |
5e7dfd0f | 13578 | int err; |
1da177e4 | 13579 | |
1da177e4 LT |
13580 | /* Force memory write invalidate off. If we leave it on, |
13581 | * then on 5700_BX chips we have to enable a workaround. | |
13582 | * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary | |
13583 | * to match the cacheline size. The Broadcom driver have this | |
13584 | * workaround but turns MWI off all the times so never uses | |
13585 | * it. This seems to suggest that the workaround is insufficient. | |
13586 | */ | |
13587 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
13588 | pci_cmd &= ~PCI_COMMAND_INVALIDATE; | |
13589 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
13590 | ||
16821285 MC |
13591 | /* Important! -- Make sure register accesses are byteswapped |
13592 | * correctly. Also, for those chips that require it, make | |
13593 | * sure that indirect register accesses are enabled before | |
13594 | * the first operation. | |
1da177e4 LT |
13595 | */ |
13596 | pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
13597 | &misc_ctrl_reg); | |
16821285 MC |
13598 | tp->misc_host_ctrl |= (misc_ctrl_reg & |
13599 | MISC_HOST_CTRL_CHIPREV); | |
13600 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
13601 | tp->misc_host_ctrl); | |
1da177e4 LT |
13602 | |
13603 | tp->pci_chip_rev_id = (misc_ctrl_reg >> | |
13604 | MISC_HOST_CTRL_CHIPREV_SHIFT); | |
795d01c5 MC |
13605 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) { |
13606 | u32 prod_id_asic_rev; | |
13607 | ||
5001e2f6 MC |
13608 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || |
13609 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 || | |
d78b59f5 MC |
13610 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 || |
13611 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720) | |
f6eb9b1f MC |
13612 | pci_read_config_dword(tp->pdev, |
13613 | TG3PCI_GEN2_PRODID_ASICREV, | |
13614 | &prod_id_asic_rev); | |
b703df6f MC |
13615 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 || |
13616 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 || | |
13617 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 || | |
13618 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 || | |
13619 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 || | |
13620 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795) | |
13621 | pci_read_config_dword(tp->pdev, | |
13622 | TG3PCI_GEN15_PRODID_ASICREV, | |
13623 | &prod_id_asic_rev); | |
f6eb9b1f MC |
13624 | else |
13625 | pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV, | |
13626 | &prod_id_asic_rev); | |
13627 | ||
321d32a0 | 13628 | tp->pci_chip_rev_id = prod_id_asic_rev; |
795d01c5 | 13629 | } |
1da177e4 | 13630 | |
ff645bec MC |
13631 | /* Wrong chip ID in 5752 A0. This code can be removed later |
13632 | * as A0 is not in production. | |
13633 | */ | |
13634 | if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW) | |
13635 | tp->pci_chip_rev_id = CHIPREV_ID_5752_A0; | |
13636 | ||
6892914f MC |
13637 | /* If we have 5702/03 A1 or A2 on certain ICH chipsets, |
13638 | * we need to disable memory and use config. cycles | |
13639 | * only to access all registers. The 5702/03 chips | |
13640 | * can mistakenly decode the special cycles from the | |
13641 | * ICH chipsets as memory write cycles, causing corruption | |
13642 | * of register and memory space. Only certain ICH bridges | |
13643 | * will drive special cycles with non-zero data during the | |
13644 | * address phase which can fall within the 5703's address | |
13645 | * range. This is not an ICH bug as the PCI spec allows | |
13646 | * non-zero address during special cycles. However, only | |
13647 | * these ICH bridges are known to drive non-zero addresses | |
13648 | * during special cycles. | |
13649 | * | |
13650 | * Since special cycles do not cross PCI bridges, we only | |
13651 | * enable this workaround if the 5703 is on the secondary | |
13652 | * bus of these ICH bridges. | |
13653 | */ | |
13654 | if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) || | |
13655 | (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) { | |
13656 | static struct tg3_dev_id { | |
13657 | u32 vendor; | |
13658 | u32 device; | |
13659 | u32 rev; | |
13660 | } ich_chipsets[] = { | |
13661 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8, | |
13662 | PCI_ANY_ID }, | |
13663 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8, | |
13664 | PCI_ANY_ID }, | |
13665 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11, | |
13666 | 0xa }, | |
13667 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6, | |
13668 | PCI_ANY_ID }, | |
13669 | { }, | |
13670 | }; | |
13671 | struct tg3_dev_id *pci_id = &ich_chipsets[0]; | |
13672 | struct pci_dev *bridge = NULL; | |
13673 | ||
13674 | while (pci_id->vendor != 0) { | |
13675 | bridge = pci_get_device(pci_id->vendor, pci_id->device, | |
13676 | bridge); | |
13677 | if (!bridge) { | |
13678 | pci_id++; | |
13679 | continue; | |
13680 | } | |
13681 | if (pci_id->rev != PCI_ANY_ID) { | |
44c10138 | 13682 | if (bridge->revision > pci_id->rev) |
6892914f MC |
13683 | continue; |
13684 | } | |
13685 | if (bridge->subordinate && | |
13686 | (bridge->subordinate->number == | |
13687 | tp->pdev->bus->number)) { | |
63c3a66f | 13688 | tg3_flag_set(tp, ICH_WORKAROUND); |
6892914f MC |
13689 | pci_dev_put(bridge); |
13690 | break; | |
13691 | } | |
13692 | } | |
13693 | } | |
13694 | ||
6ff6f81d | 13695 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { |
41588ba1 MC |
13696 | static struct tg3_dev_id { |
13697 | u32 vendor; | |
13698 | u32 device; | |
13699 | } bridge_chipsets[] = { | |
13700 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 }, | |
13701 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 }, | |
13702 | { }, | |
13703 | }; | |
13704 | struct tg3_dev_id *pci_id = &bridge_chipsets[0]; | |
13705 | struct pci_dev *bridge = NULL; | |
13706 | ||
13707 | while (pci_id->vendor != 0) { | |
13708 | bridge = pci_get_device(pci_id->vendor, | |
13709 | pci_id->device, | |
13710 | bridge); | |
13711 | if (!bridge) { | |
13712 | pci_id++; | |
13713 | continue; | |
13714 | } | |
13715 | if (bridge->subordinate && | |
13716 | (bridge->subordinate->number <= | |
13717 | tp->pdev->bus->number) && | |
13718 | (bridge->subordinate->subordinate >= | |
13719 | tp->pdev->bus->number)) { | |
63c3a66f | 13720 | tg3_flag_set(tp, 5701_DMA_BUG); |
41588ba1 MC |
13721 | pci_dev_put(bridge); |
13722 | break; | |
13723 | } | |
13724 | } | |
13725 | } | |
13726 | ||
4a29cc2e MC |
13727 | /* The EPB bridge inside 5714, 5715, and 5780 cannot support |
13728 | * DMA addresses > 40-bit. This bridge may have other additional | |
13729 | * 57xx devices behind it in some 4-port NIC designs for example. | |
13730 | * Any tg3 device found behind the bridge will also need the 40-bit | |
13731 | * DMA workaround. | |
13732 | */ | |
a4e2b347 MC |
13733 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 || |
13734 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { | |
63c3a66f JP |
13735 | tg3_flag_set(tp, 5780_CLASS); |
13736 | tg3_flag_set(tp, 40BIT_DMA_BUG); | |
4cf78e4f | 13737 | tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI); |
859a5887 | 13738 | } else { |
4a29cc2e MC |
13739 | struct pci_dev *bridge = NULL; |
13740 | ||
13741 | do { | |
13742 | bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, | |
13743 | PCI_DEVICE_ID_SERVERWORKS_EPB, | |
13744 | bridge); | |
13745 | if (bridge && bridge->subordinate && | |
13746 | (bridge->subordinate->number <= | |
13747 | tp->pdev->bus->number) && | |
13748 | (bridge->subordinate->subordinate >= | |
13749 | tp->pdev->bus->number)) { | |
63c3a66f | 13750 | tg3_flag_set(tp, 40BIT_DMA_BUG); |
4a29cc2e MC |
13751 | pci_dev_put(bridge); |
13752 | break; | |
13753 | } | |
13754 | } while (bridge); | |
13755 | } | |
4cf78e4f | 13756 | |
f6eb9b1f | 13757 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || |
3a1e19d3 | 13758 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) |
7544b097 MC |
13759 | tp->pdev_peer = tg3_find_peer(tp); |
13760 | ||
c885e824 | 13761 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
d78b59f5 MC |
13762 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
13763 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
63c3a66f | 13764 | tg3_flag_set(tp, 5717_PLUS); |
0a58d668 MC |
13765 | |
13766 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 || | |
63c3a66f JP |
13767 | tg3_flag(tp, 5717_PLUS)) |
13768 | tg3_flag_set(tp, 57765_PLUS); | |
c885e824 | 13769 | |
321d32a0 MC |
13770 | /* Intentionally exclude ASIC_REV_5906 */ |
13771 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || | |
d9ab5ad1 | 13772 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || |
d30cdd28 | 13773 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
9936bcf6 | 13774 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
57e6983c | 13775 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
f6eb9b1f | 13776 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
63c3a66f JP |
13777 | tg3_flag(tp, 57765_PLUS)) |
13778 | tg3_flag_set(tp, 5755_PLUS); | |
321d32a0 MC |
13779 | |
13780 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || | |
13781 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || | |
b5d3772c | 13782 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 || |
63c3a66f JP |
13783 | tg3_flag(tp, 5755_PLUS) || |
13784 | tg3_flag(tp, 5780_CLASS)) | |
13785 | tg3_flag_set(tp, 5750_PLUS); | |
6708e5cc | 13786 | |
6ff6f81d | 13787 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 || |
63c3a66f JP |
13788 | tg3_flag(tp, 5750_PLUS)) |
13789 | tg3_flag_set(tp, 5705_PLUS); | |
1b440c56 | 13790 | |
507399f1 | 13791 | /* Determine TSO capabilities */ |
2866d956 | 13792 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) |
4d163b75 | 13793 | ; /* Do nothing. HW bug. */ |
63c3a66f JP |
13794 | else if (tg3_flag(tp, 57765_PLUS)) |
13795 | tg3_flag_set(tp, HW_TSO_3); | |
13796 | else if (tg3_flag(tp, 5755_PLUS) || | |
e849cdc3 | 13797 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
63c3a66f JP |
13798 | tg3_flag_set(tp, HW_TSO_2); |
13799 | else if (tg3_flag(tp, 5750_PLUS)) { | |
13800 | tg3_flag_set(tp, HW_TSO_1); | |
13801 | tg3_flag_set(tp, TSO_BUG); | |
507399f1 MC |
13802 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 && |
13803 | tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2) | |
63c3a66f | 13804 | tg3_flag_clear(tp, TSO_BUG); |
507399f1 MC |
13805 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && |
13806 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 && | |
13807 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { | |
63c3a66f | 13808 | tg3_flag_set(tp, TSO_BUG); |
507399f1 MC |
13809 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) |
13810 | tp->fw_needed = FIRMWARE_TG3TSO5; | |
13811 | else | |
13812 | tp->fw_needed = FIRMWARE_TG3TSO; | |
13813 | } | |
13814 | ||
dabc5c67 | 13815 | /* Selectively allow TSO based on operating conditions */ |
6ff6f81d MC |
13816 | if (tg3_flag(tp, HW_TSO_1) || |
13817 | tg3_flag(tp, HW_TSO_2) || | |
13818 | tg3_flag(tp, HW_TSO_3) || | |
dabc5c67 MC |
13819 | (tp->fw_needed && !tg3_flag(tp, ENABLE_ASF))) |
13820 | tg3_flag_set(tp, TSO_CAPABLE); | |
13821 | else { | |
13822 | tg3_flag_clear(tp, TSO_CAPABLE); | |
13823 | tg3_flag_clear(tp, TSO_BUG); | |
13824 | tp->fw_needed = NULL; | |
13825 | } | |
13826 | ||
13827 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) | |
13828 | tp->fw_needed = FIRMWARE_TG3; | |
13829 | ||
507399f1 MC |
13830 | tp->irq_max = 1; |
13831 | ||
63c3a66f JP |
13832 | if (tg3_flag(tp, 5750_PLUS)) { |
13833 | tg3_flag_set(tp, SUPPORT_MSI); | |
7544b097 MC |
13834 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX || |
13835 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX || | |
13836 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 && | |
13837 | tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 && | |
13838 | tp->pdev_peer == tp->pdev)) | |
63c3a66f | 13839 | tg3_flag_clear(tp, SUPPORT_MSI); |
7544b097 | 13840 | |
63c3a66f | 13841 | if (tg3_flag(tp, 5755_PLUS) || |
b5d3772c | 13842 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
63c3a66f | 13843 | tg3_flag_set(tp, 1SHOT_MSI); |
52c0fd83 | 13844 | } |
4f125f42 | 13845 | |
63c3a66f JP |
13846 | if (tg3_flag(tp, 57765_PLUS)) { |
13847 | tg3_flag_set(tp, SUPPORT_MSIX); | |
507399f1 MC |
13848 | tp->irq_max = TG3_IRQ_MAX_VECS; |
13849 | } | |
f6eb9b1f | 13850 | } |
0e1406dd | 13851 | |
2ffcc981 | 13852 | if (tg3_flag(tp, 5755_PLUS)) |
63c3a66f | 13853 | tg3_flag_set(tp, SHORT_DMA_BUG); |
f6eb9b1f | 13854 | |
63c3a66f JP |
13855 | if (tg3_flag(tp, 5717_PLUS)) |
13856 | tg3_flag_set(tp, LRG_PROD_RING_CAP); | |
de9f5230 | 13857 | |
63c3a66f | 13858 | if (tg3_flag(tp, 57765_PLUS) && |
2866d956 | 13859 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719) |
63c3a66f | 13860 | tg3_flag_set(tp, USE_JUMBO_BDFLAG); |
b703df6f | 13861 | |
63c3a66f JP |
13862 | if (!tg3_flag(tp, 5705_PLUS) || |
13863 | tg3_flag(tp, 5780_CLASS) || | |
13864 | tg3_flag(tp, USE_JUMBO_BDFLAG)) | |
13865 | tg3_flag_set(tp, JUMBO_CAPABLE); | |
0f893dc6 | 13866 | |
52f4490c MC |
13867 | pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, |
13868 | &pci_state_reg); | |
13869 | ||
708ebb3a | 13870 | if (pci_is_pcie(tp->pdev)) { |
5e7dfd0f MC |
13871 | u16 lnkctl; |
13872 | ||
63c3a66f | 13873 | tg3_flag_set(tp, PCI_EXPRESS); |
5f5c51e3 | 13874 | |
cf79003d | 13875 | tp->pcie_readrq = 4096; |
d78b59f5 MC |
13876 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
13877 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
b4495ed8 | 13878 | tp->pcie_readrq = 2048; |
cf79003d MC |
13879 | |
13880 | pcie_set_readrq(tp->pdev, tp->pcie_readrq); | |
5f5c51e3 | 13881 | |
5e7dfd0f | 13882 | pci_read_config_word(tp->pdev, |
708ebb3a | 13883 | pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL, |
5e7dfd0f MC |
13884 | &lnkctl); |
13885 | if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) { | |
7196cd6c MC |
13886 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == |
13887 | ASIC_REV_5906) { | |
63c3a66f | 13888 | tg3_flag_clear(tp, HW_TSO_2); |
dabc5c67 | 13889 | tg3_flag_clear(tp, TSO_CAPABLE); |
7196cd6c | 13890 | } |
5e7dfd0f | 13891 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
321d32a0 | 13892 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
9cf74ebb MC |
13893 | tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 || |
13894 | tp->pci_chip_rev_id == CHIPREV_ID_57780_A1) | |
63c3a66f | 13895 | tg3_flag_set(tp, CLKREQ_BUG); |
614b0590 | 13896 | } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) { |
63c3a66f | 13897 | tg3_flag_set(tp, L1PLLPD_EN); |
c7835a77 | 13898 | } |
52f4490c | 13899 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { |
708ebb3a JM |
13900 | /* BCM5785 devices are effectively PCIe devices, and should |
13901 | * follow PCIe codepaths, but do not have a PCIe capabilities | |
13902 | * section. | |
13903 | */ | |
63c3a66f JP |
13904 | tg3_flag_set(tp, PCI_EXPRESS); |
13905 | } else if (!tg3_flag(tp, 5705_PLUS) || | |
13906 | tg3_flag(tp, 5780_CLASS)) { | |
52f4490c MC |
13907 | tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX); |
13908 | if (!tp->pcix_cap) { | |
2445e461 MC |
13909 | dev_err(&tp->pdev->dev, |
13910 | "Cannot find PCI-X capability, aborting\n"); | |
52f4490c MC |
13911 | return -EIO; |
13912 | } | |
13913 | ||
13914 | if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE)) | |
63c3a66f | 13915 | tg3_flag_set(tp, PCIX_MODE); |
52f4490c | 13916 | } |
1da177e4 | 13917 | |
399de50b MC |
13918 | /* If we have an AMD 762 or VIA K8T800 chipset, write |
13919 | * reordering to the mailbox registers done by the host | |
13920 | * controller can cause major troubles. We read back from | |
13921 | * every mailbox register write to force the writes to be | |
13922 | * posted to the chip in order. | |
13923 | */ | |
4143470c | 13924 | if (pci_dev_present(tg3_write_reorder_chipsets) && |
63c3a66f JP |
13925 | !tg3_flag(tp, PCI_EXPRESS)) |
13926 | tg3_flag_set(tp, MBOX_WRITE_REORDER); | |
399de50b | 13927 | |
69fc4053 MC |
13928 | pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, |
13929 | &tp->pci_cacheline_sz); | |
13930 | pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER, | |
13931 | &tp->pci_lat_timer); | |
1da177e4 LT |
13932 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && |
13933 | tp->pci_lat_timer < 64) { | |
13934 | tp->pci_lat_timer = 64; | |
69fc4053 MC |
13935 | pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, |
13936 | tp->pci_lat_timer); | |
1da177e4 LT |
13937 | } |
13938 | ||
16821285 MC |
13939 | /* Important! -- It is critical that the PCI-X hw workaround |
13940 | * situation is decided before the first MMIO register access. | |
13941 | */ | |
52f4490c MC |
13942 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) { |
13943 | /* 5700 BX chips need to have their TX producer index | |
13944 | * mailboxes written twice to workaround a bug. | |
13945 | */ | |
63c3a66f | 13946 | tg3_flag_set(tp, TXD_MBOX_HWBUG); |
1da177e4 | 13947 | |
52f4490c | 13948 | /* If we are in PCI-X mode, enable register write workaround. |
1da177e4 LT |
13949 | * |
13950 | * The workaround is to use indirect register accesses | |
13951 | * for all chip writes not to mailbox registers. | |
13952 | */ | |
63c3a66f | 13953 | if (tg3_flag(tp, PCIX_MODE)) { |
1da177e4 | 13954 | u32 pm_reg; |
1da177e4 | 13955 | |
63c3a66f | 13956 | tg3_flag_set(tp, PCIX_TARGET_HWBUG); |
1da177e4 LT |
13957 | |
13958 | /* The chip can have it's power management PCI config | |
13959 | * space registers clobbered due to this bug. | |
13960 | * So explicitly force the chip into D0 here. | |
13961 | */ | |
9974a356 MC |
13962 | pci_read_config_dword(tp->pdev, |
13963 | tp->pm_cap + PCI_PM_CTRL, | |
1da177e4 LT |
13964 | &pm_reg); |
13965 | pm_reg &= ~PCI_PM_CTRL_STATE_MASK; | |
13966 | pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */; | |
9974a356 MC |
13967 | pci_write_config_dword(tp->pdev, |
13968 | tp->pm_cap + PCI_PM_CTRL, | |
1da177e4 LT |
13969 | pm_reg); |
13970 | ||
13971 | /* Also, force SERR#/PERR# in PCI command. */ | |
13972 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
13973 | pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR; | |
13974 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
13975 | } | |
13976 | } | |
13977 | ||
1da177e4 | 13978 | if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0) |
63c3a66f | 13979 | tg3_flag_set(tp, PCI_HIGH_SPEED); |
1da177e4 | 13980 | if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0) |
63c3a66f | 13981 | tg3_flag_set(tp, PCI_32BIT); |
1da177e4 LT |
13982 | |
13983 | /* Chip-specific fixup from Broadcom driver */ | |
13984 | if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) && | |
13985 | (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) { | |
13986 | pci_state_reg |= PCISTATE_RETRY_SAME_DMA; | |
13987 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg); | |
13988 | } | |
13989 | ||
1ee582d8 | 13990 | /* Default fast path register access methods */ |
20094930 | 13991 | tp->read32 = tg3_read32; |
1ee582d8 | 13992 | tp->write32 = tg3_write32; |
09ee929c | 13993 | tp->read32_mbox = tg3_read32; |
20094930 | 13994 | tp->write32_mbox = tg3_write32; |
1ee582d8 MC |
13995 | tp->write32_tx_mbox = tg3_write32; |
13996 | tp->write32_rx_mbox = tg3_write32; | |
13997 | ||
13998 | /* Various workaround register access methods */ | |
63c3a66f | 13999 | if (tg3_flag(tp, PCIX_TARGET_HWBUG)) |
1ee582d8 | 14000 | tp->write32 = tg3_write_indirect_reg32; |
98efd8a6 | 14001 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 || |
63c3a66f | 14002 | (tg3_flag(tp, PCI_EXPRESS) && |
98efd8a6 MC |
14003 | tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) { |
14004 | /* | |
14005 | * Back to back register writes can cause problems on these | |
14006 | * chips, the workaround is to read back all reg writes | |
14007 | * except those to mailbox regs. | |
14008 | * | |
14009 | * See tg3_write_indirect_reg32(). | |
14010 | */ | |
1ee582d8 | 14011 | tp->write32 = tg3_write_flush_reg32; |
98efd8a6 MC |
14012 | } |
14013 | ||
63c3a66f | 14014 | if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) { |
1ee582d8 | 14015 | tp->write32_tx_mbox = tg3_write32_tx_mbox; |
63c3a66f | 14016 | if (tg3_flag(tp, MBOX_WRITE_REORDER)) |
1ee582d8 MC |
14017 | tp->write32_rx_mbox = tg3_write_flush_reg32; |
14018 | } | |
20094930 | 14019 | |
63c3a66f | 14020 | if (tg3_flag(tp, ICH_WORKAROUND)) { |
6892914f MC |
14021 | tp->read32 = tg3_read_indirect_reg32; |
14022 | tp->write32 = tg3_write_indirect_reg32; | |
14023 | tp->read32_mbox = tg3_read_indirect_mbox; | |
14024 | tp->write32_mbox = tg3_write_indirect_mbox; | |
14025 | tp->write32_tx_mbox = tg3_write_indirect_mbox; | |
14026 | tp->write32_rx_mbox = tg3_write_indirect_mbox; | |
14027 | ||
14028 | iounmap(tp->regs); | |
22abe310 | 14029 | tp->regs = NULL; |
6892914f MC |
14030 | |
14031 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
14032 | pci_cmd &= ~PCI_COMMAND_MEMORY; | |
14033 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
14034 | } | |
b5d3772c MC |
14035 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
14036 | tp->read32_mbox = tg3_read32_mbox_5906; | |
14037 | tp->write32_mbox = tg3_write32_mbox_5906; | |
14038 | tp->write32_tx_mbox = tg3_write32_mbox_5906; | |
14039 | tp->write32_rx_mbox = tg3_write32_mbox_5906; | |
14040 | } | |
6892914f | 14041 | |
bbadf503 | 14042 | if (tp->write32 == tg3_write_indirect_reg32 || |
63c3a66f | 14043 | (tg3_flag(tp, PCIX_MODE) && |
bbadf503 | 14044 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
f49639e6 | 14045 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701))) |
63c3a66f | 14046 | tg3_flag_set(tp, SRAM_USE_CONFIG); |
bbadf503 | 14047 | |
16821285 MC |
14048 | /* The memory arbiter has to be enabled in order for SRAM accesses |
14049 | * to succeed. Normally on powerup the tg3 chip firmware will make | |
14050 | * sure it is enabled, but other entities such as system netboot | |
14051 | * code might disable it. | |
14052 | */ | |
14053 | val = tr32(MEMARB_MODE); | |
14054 | tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE); | |
14055 | ||
69f11c99 MC |
14056 | if (tg3_flag(tp, PCIX_MODE)) { |
14057 | pci_read_config_dword(tp->pdev, | |
14058 | tp->pcix_cap + PCI_X_STATUS, &val); | |
14059 | tp->pci_fn = val & 0x7; | |
14060 | } else { | |
14061 | tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3; | |
14062 | } | |
14063 | ||
7d0c41ef | 14064 | /* Get eeprom hw config before calling tg3_set_power_state(). |
63c3a66f | 14065 | * In particular, the TG3_FLAG_IS_NIC flag must be |
7d0c41ef MC |
14066 | * determined before calling tg3_set_power_state() so that |
14067 | * we know whether or not to switch out of Vaux power. | |
14068 | * When the flag is set, it means that GPIO1 is used for eeprom | |
14069 | * write protect and also implies that it is a LOM where GPIOs | |
14070 | * are not used to switch power. | |
6aa20a22 | 14071 | */ |
7d0c41ef MC |
14072 | tg3_get_eeprom_hw_cfg(tp); |
14073 | ||
63c3a66f | 14074 | if (tg3_flag(tp, ENABLE_APE)) { |
0d3031d9 MC |
14075 | /* Allow reads and writes to the |
14076 | * APE register and memory space. | |
14077 | */ | |
14078 | pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR | | |
f92d9dc1 MC |
14079 | PCISTATE_ALLOW_APE_SHMEM_WR | |
14080 | PCISTATE_ALLOW_APE_PSPACE_WR; | |
0d3031d9 MC |
14081 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, |
14082 | pci_state_reg); | |
c9cab24e MC |
14083 | |
14084 | tg3_ape_lock_init(tp); | |
0d3031d9 MC |
14085 | } |
14086 | ||
9936bcf6 | 14087 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
57e6983c | 14088 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
321d32a0 | 14089 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
f6eb9b1f | 14090 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
63c3a66f JP |
14091 | tg3_flag(tp, 57765_PLUS)) |
14092 | tg3_flag_set(tp, CPMU_PRESENT); | |
d30cdd28 | 14093 | |
16821285 MC |
14094 | /* Set up tp->grc_local_ctrl before calling |
14095 | * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high | |
14096 | * will bring 5700's external PHY out of reset. | |
314fba34 MC |
14097 | * It is also used as eeprom write protect on LOMs. |
14098 | */ | |
14099 | tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM; | |
6ff6f81d | 14100 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
63c3a66f | 14101 | tg3_flag(tp, EEPROM_WRITE_PROT)) |
314fba34 MC |
14102 | tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | |
14103 | GRC_LCLCTRL_GPIO_OUTPUT1); | |
3e7d83bc MC |
14104 | /* Unused GPIO3 must be driven as output on 5752 because there |
14105 | * are no pull-up resistors on unused GPIO pins. | |
14106 | */ | |
14107 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) | |
14108 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; | |
314fba34 | 14109 | |
321d32a0 | 14110 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || |
cb4ed1fd MC |
14111 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
14112 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
af36e6b6 MC |
14113 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; |
14114 | ||
8d519ab2 MC |
14115 | if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || |
14116 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { | |
5f0c4a3c MC |
14117 | /* Turn off the debug UART. */ |
14118 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; | |
63c3a66f | 14119 | if (tg3_flag(tp, IS_NIC)) |
5f0c4a3c MC |
14120 | /* Keep VMain power. */ |
14121 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 | | |
14122 | GRC_LCLCTRL_GPIO_OUTPUT0; | |
14123 | } | |
14124 | ||
16821285 MC |
14125 | /* Switch out of Vaux if it is a NIC */ |
14126 | tg3_pwrsrc_switch_to_vmain(tp); | |
1da177e4 | 14127 | |
1da177e4 LT |
14128 | /* Derive initial jumbo mode from MTU assigned in |
14129 | * ether_setup() via the alloc_etherdev() call | |
14130 | */ | |
63c3a66f JP |
14131 | if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS)) |
14132 | tg3_flag_set(tp, JUMBO_RING_ENABLE); | |
1da177e4 LT |
14133 | |
14134 | /* Determine WakeOnLan speed to use. */ | |
14135 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
14136 | tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
14137 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 || | |
14138 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) { | |
63c3a66f | 14139 | tg3_flag_clear(tp, WOL_SPEED_100MB); |
1da177e4 | 14140 | } else { |
63c3a66f | 14141 | tg3_flag_set(tp, WOL_SPEED_100MB); |
1da177e4 LT |
14142 | } |
14143 | ||
7f97a4bd | 14144 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
f07e9af3 | 14145 | tp->phy_flags |= TG3_PHYFLG_IS_FET; |
7f97a4bd | 14146 | |
1da177e4 | 14147 | /* A few boards don't want Ethernet@WireSpeed phy feature */ |
6ff6f81d MC |
14148 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
14149 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && | |
1da177e4 | 14150 | (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) && |
747e8f8b | 14151 | (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) || |
f07e9af3 MC |
14152 | (tp->phy_flags & TG3_PHYFLG_IS_FET) || |
14153 | (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) | |
14154 | tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED; | |
1da177e4 LT |
14155 | |
14156 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX || | |
14157 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX) | |
f07e9af3 | 14158 | tp->phy_flags |= TG3_PHYFLG_ADC_BUG; |
1da177e4 | 14159 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) |
f07e9af3 | 14160 | tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG; |
1da177e4 | 14161 | |
63c3a66f | 14162 | if (tg3_flag(tp, 5705_PLUS) && |
f07e9af3 | 14163 | !(tp->phy_flags & TG3_PHYFLG_IS_FET) && |
321d32a0 | 14164 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && |
f6eb9b1f | 14165 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 && |
63c3a66f | 14166 | !tg3_flag(tp, 57765_PLUS)) { |
c424cb24 | 14167 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || |
d30cdd28 | 14168 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || |
9936bcf6 MC |
14169 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
14170 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) { | |
d4011ada MC |
14171 | if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 && |
14172 | tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722) | |
f07e9af3 | 14173 | tp->phy_flags |= TG3_PHYFLG_JITTER_BUG; |
c1d2a196 | 14174 | if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M) |
f07e9af3 | 14175 | tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM; |
321d32a0 | 14176 | } else |
f07e9af3 | 14177 | tp->phy_flags |= TG3_PHYFLG_BER_BUG; |
c424cb24 | 14178 | } |
1da177e4 | 14179 | |
b2a5c19c MC |
14180 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && |
14181 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) { | |
14182 | tp->phy_otp = tg3_read_otp_phycfg(tp); | |
14183 | if (tp->phy_otp == 0) | |
14184 | tp->phy_otp = TG3_OTP_DEFAULT; | |
14185 | } | |
14186 | ||
63c3a66f | 14187 | if (tg3_flag(tp, CPMU_PRESENT)) |
8ef21428 MC |
14188 | tp->mi_mode = MAC_MI_MODE_500KHZ_CONST; |
14189 | else | |
14190 | tp->mi_mode = MAC_MI_MODE_BASE; | |
14191 | ||
1da177e4 | 14192 | tp->coalesce_mode = 0; |
1da177e4 LT |
14193 | if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX && |
14194 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX) | |
14195 | tp->coalesce_mode |= HOSTCC_MODE_32BYTE; | |
14196 | ||
4d958473 MC |
14197 | /* Set these bits to enable statistics workaround. */ |
14198 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
14199 | tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 || | |
14200 | tp->pci_chip_rev_id == CHIPREV_ID_5720_A0) { | |
14201 | tp->coalesce_mode |= HOSTCC_MODE_ATTN; | |
14202 | tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN; | |
14203 | } | |
14204 | ||
321d32a0 MC |
14205 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
14206 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
63c3a66f | 14207 | tg3_flag_set(tp, USE_PHYLIB); |
57e6983c | 14208 | |
158d7abd MC |
14209 | err = tg3_mdio_init(tp); |
14210 | if (err) | |
14211 | return err; | |
1da177e4 LT |
14212 | |
14213 | /* Initialize data/descriptor byte/word swapping. */ | |
14214 | val = tr32(GRC_MODE); | |
f2096f94 MC |
14215 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) |
14216 | val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA | | |
14217 | GRC_MODE_WORD_SWAP_B2HRX_DATA | | |
14218 | GRC_MODE_B2HRX_ENABLE | | |
14219 | GRC_MODE_HTX2B_ENABLE | | |
14220 | GRC_MODE_HOST_STACKUP); | |
14221 | else | |
14222 | val &= GRC_MODE_HOST_STACKUP; | |
14223 | ||
1da177e4 LT |
14224 | tw32(GRC_MODE, val | tp->grc_mode); |
14225 | ||
14226 | tg3_switch_clocks(tp); | |
14227 | ||
14228 | /* Clear this out for sanity. */ | |
14229 | tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
14230 | ||
14231 | pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, | |
14232 | &pci_state_reg); | |
14233 | if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 && | |
63c3a66f | 14234 | !tg3_flag(tp, PCIX_TARGET_HWBUG)) { |
1da177e4 LT |
14235 | u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl); |
14236 | ||
14237 | if (chiprevid == CHIPREV_ID_5701_A0 || | |
14238 | chiprevid == CHIPREV_ID_5701_B0 || | |
14239 | chiprevid == CHIPREV_ID_5701_B2 || | |
14240 | chiprevid == CHIPREV_ID_5701_B5) { | |
14241 | void __iomem *sram_base; | |
14242 | ||
14243 | /* Write some dummy words into the SRAM status block | |
14244 | * area, see if it reads back correctly. If the return | |
14245 | * value is bad, force enable the PCIX workaround. | |
14246 | */ | |
14247 | sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK; | |
14248 | ||
14249 | writel(0x00000000, sram_base); | |
14250 | writel(0x00000000, sram_base + 4); | |
14251 | writel(0xffffffff, sram_base + 4); | |
14252 | if (readl(sram_base) != 0x00000000) | |
63c3a66f | 14253 | tg3_flag_set(tp, PCIX_TARGET_HWBUG); |
1da177e4 LT |
14254 | } |
14255 | } | |
14256 | ||
14257 | udelay(50); | |
14258 | tg3_nvram_init(tp); | |
14259 | ||
14260 | grc_misc_cfg = tr32(GRC_MISC_CFG); | |
14261 | grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK; | |
14262 | ||
1da177e4 LT |
14263 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && |
14264 | (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 || | |
14265 | grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M)) | |
63c3a66f | 14266 | tg3_flag_set(tp, IS_5788); |
1da177e4 | 14267 | |
63c3a66f | 14268 | if (!tg3_flag(tp, IS_5788) && |
6ff6f81d | 14269 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) |
63c3a66f JP |
14270 | tg3_flag_set(tp, TAGGED_STATUS); |
14271 | if (tg3_flag(tp, TAGGED_STATUS)) { | |
fac9b83e DM |
14272 | tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD | |
14273 | HOSTCC_MODE_CLRTICK_TXBD); | |
14274 | ||
14275 | tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS; | |
14276 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
14277 | tp->misc_host_ctrl); | |
14278 | } | |
14279 | ||
3bda1258 | 14280 | /* Preserve the APE MAC_MODE bits */ |
63c3a66f | 14281 | if (tg3_flag(tp, ENABLE_APE)) |
d2394e6b | 14282 | tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; |
3bda1258 MC |
14283 | else |
14284 | tp->mac_mode = TG3_DEF_MAC_MODE; | |
14285 | ||
1da177e4 LT |
14286 | /* these are limited to 10/100 only */ |
14287 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && | |
14288 | (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) || | |
14289 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && | |
14290 | tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM && | |
14291 | (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 || | |
14292 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 || | |
14293 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) || | |
14294 | (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM && | |
14295 | (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F || | |
676917d4 MC |
14296 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F || |
14297 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) || | |
321d32a0 | 14298 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 || |
d1101142 MC |
14299 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 || |
14300 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 || | |
f07e9af3 MC |
14301 | (tp->phy_flags & TG3_PHYFLG_IS_FET)) |
14302 | tp->phy_flags |= TG3_PHYFLG_10_100_ONLY; | |
1da177e4 LT |
14303 | |
14304 | err = tg3_phy_probe(tp); | |
14305 | if (err) { | |
2445e461 | 14306 | dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err); |
1da177e4 | 14307 | /* ... but do not return immediately ... */ |
b02fd9e3 | 14308 | tg3_mdio_fini(tp); |
1da177e4 LT |
14309 | } |
14310 | ||
184b8904 | 14311 | tg3_read_vpd(tp); |
c4e6575c | 14312 | tg3_read_fw_ver(tp); |
1da177e4 | 14313 | |
f07e9af3 MC |
14314 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
14315 | tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; | |
1da177e4 LT |
14316 | } else { |
14317 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) | |
f07e9af3 | 14318 | tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; |
1da177e4 | 14319 | else |
f07e9af3 | 14320 | tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; |
1da177e4 LT |
14321 | } |
14322 | ||
14323 | /* 5700 {AX,BX} chips have a broken status block link | |
14324 | * change bit implementation, so we must use the | |
14325 | * status register in those cases. | |
14326 | */ | |
14327 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) | |
63c3a66f | 14328 | tg3_flag_set(tp, USE_LINKCHG_REG); |
1da177e4 | 14329 | else |
63c3a66f | 14330 | tg3_flag_clear(tp, USE_LINKCHG_REG); |
1da177e4 LT |
14331 | |
14332 | /* The led_ctrl is set during tg3_phy_probe, here we might | |
14333 | * have to force the link status polling mechanism based | |
14334 | * upon subsystem IDs. | |
14335 | */ | |
14336 | if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL && | |
007a880d | 14337 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 && |
f07e9af3 MC |
14338 | !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { |
14339 | tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; | |
63c3a66f | 14340 | tg3_flag_set(tp, USE_LINKCHG_REG); |
1da177e4 LT |
14341 | } |
14342 | ||
14343 | /* For all SERDES we poll the MAC status register. */ | |
f07e9af3 | 14344 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
63c3a66f | 14345 | tg3_flag_set(tp, POLL_SERDES); |
1da177e4 | 14346 | else |
63c3a66f | 14347 | tg3_flag_clear(tp, POLL_SERDES); |
1da177e4 | 14348 | |
bf933c80 | 14349 | tp->rx_offset = NET_IP_ALIGN; |
d2757fc4 | 14350 | tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD; |
1da177e4 | 14351 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 && |
63c3a66f | 14352 | tg3_flag(tp, PCIX_MODE)) { |
bf933c80 | 14353 | tp->rx_offset = 0; |
d2757fc4 | 14354 | #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS |
9dc7a113 | 14355 | tp->rx_copy_thresh = ~(u16)0; |
d2757fc4 MC |
14356 | #endif |
14357 | } | |
1da177e4 | 14358 | |
2c49a44d MC |
14359 | tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1; |
14360 | tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1; | |
7cb32cf2 MC |
14361 | tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1; |
14362 | ||
2c49a44d | 14363 | tp->rx_std_max_post = tp->rx_std_ring_mask + 1; |
f92905de MC |
14364 | |
14365 | /* Increment the rx prod index on the rx std ring by at most | |
14366 | * 8 for these chips to workaround hw errata. | |
14367 | */ | |
14368 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || | |
14369 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || | |
14370 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) | |
14371 | tp->rx_std_max_post = 8; | |
14372 | ||
63c3a66f | 14373 | if (tg3_flag(tp, ASPM_WORKAROUND)) |
8ed5d97e MC |
14374 | tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) & |
14375 | PCIE_PWR_MGMT_L1_THRESH_MSK; | |
14376 | ||
1da177e4 LT |
14377 | return err; |
14378 | } | |
14379 | ||
49b6e95f | 14380 | #ifdef CONFIG_SPARC |
1da177e4 LT |
14381 | static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp) |
14382 | { | |
14383 | struct net_device *dev = tp->dev; | |
14384 | struct pci_dev *pdev = tp->pdev; | |
49b6e95f | 14385 | struct device_node *dp = pci_device_to_OF_node(pdev); |
374d4cac | 14386 | const unsigned char *addr; |
49b6e95f DM |
14387 | int len; |
14388 | ||
14389 | addr = of_get_property(dp, "local-mac-address", &len); | |
14390 | if (addr && len == 6) { | |
14391 | memcpy(dev->dev_addr, addr, 6); | |
14392 | memcpy(dev->perm_addr, dev->dev_addr, 6); | |
14393 | return 0; | |
1da177e4 LT |
14394 | } |
14395 | return -ENODEV; | |
14396 | } | |
14397 | ||
14398 | static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp) | |
14399 | { | |
14400 | struct net_device *dev = tp->dev; | |
14401 | ||
14402 | memcpy(dev->dev_addr, idprom->id_ethaddr, 6); | |
2ff43697 | 14403 | memcpy(dev->perm_addr, idprom->id_ethaddr, 6); |
1da177e4 LT |
14404 | return 0; |
14405 | } | |
14406 | #endif | |
14407 | ||
14408 | static int __devinit tg3_get_device_address(struct tg3 *tp) | |
14409 | { | |
14410 | struct net_device *dev = tp->dev; | |
14411 | u32 hi, lo, mac_offset; | |
008652b3 | 14412 | int addr_ok = 0; |
1da177e4 | 14413 | |
49b6e95f | 14414 | #ifdef CONFIG_SPARC |
1da177e4 LT |
14415 | if (!tg3_get_macaddr_sparc(tp)) |
14416 | return 0; | |
14417 | #endif | |
14418 | ||
14419 | mac_offset = 0x7c; | |
6ff6f81d | 14420 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || |
63c3a66f | 14421 | tg3_flag(tp, 5780_CLASS)) { |
1da177e4 LT |
14422 | if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) |
14423 | mac_offset = 0xcc; | |
14424 | if (tg3_nvram_lock(tp)) | |
14425 | tw32_f(NVRAM_CMD, NVRAM_CMD_RESET); | |
14426 | else | |
14427 | tg3_nvram_unlock(tp); | |
63c3a66f | 14428 | } else if (tg3_flag(tp, 5717_PLUS)) { |
69f11c99 | 14429 | if (tp->pci_fn & 1) |
a1b950d5 | 14430 | mac_offset = 0xcc; |
69f11c99 | 14431 | if (tp->pci_fn > 1) |
a50d0796 | 14432 | mac_offset += 0x18c; |
a1b950d5 | 14433 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
b5d3772c | 14434 | mac_offset = 0x10; |
1da177e4 LT |
14435 | |
14436 | /* First try to get it from MAC address mailbox. */ | |
14437 | tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi); | |
14438 | if ((hi >> 16) == 0x484b) { | |
14439 | dev->dev_addr[0] = (hi >> 8) & 0xff; | |
14440 | dev->dev_addr[1] = (hi >> 0) & 0xff; | |
14441 | ||
14442 | tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo); | |
14443 | dev->dev_addr[2] = (lo >> 24) & 0xff; | |
14444 | dev->dev_addr[3] = (lo >> 16) & 0xff; | |
14445 | dev->dev_addr[4] = (lo >> 8) & 0xff; | |
14446 | dev->dev_addr[5] = (lo >> 0) & 0xff; | |
1da177e4 | 14447 | |
008652b3 MC |
14448 | /* Some old bootcode may report a 0 MAC address in SRAM */ |
14449 | addr_ok = is_valid_ether_addr(&dev->dev_addr[0]); | |
14450 | } | |
14451 | if (!addr_ok) { | |
14452 | /* Next, try NVRAM. */ | |
63c3a66f | 14453 | if (!tg3_flag(tp, NO_NVRAM) && |
df259d8c | 14454 | !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) && |
6d348f2c | 14455 | !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) { |
62cedd11 MC |
14456 | memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2); |
14457 | memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo)); | |
008652b3 MC |
14458 | } |
14459 | /* Finally just fetch it out of the MAC control regs. */ | |
14460 | else { | |
14461 | hi = tr32(MAC_ADDR_0_HIGH); | |
14462 | lo = tr32(MAC_ADDR_0_LOW); | |
14463 | ||
14464 | dev->dev_addr[5] = lo & 0xff; | |
14465 | dev->dev_addr[4] = (lo >> 8) & 0xff; | |
14466 | dev->dev_addr[3] = (lo >> 16) & 0xff; | |
14467 | dev->dev_addr[2] = (lo >> 24) & 0xff; | |
14468 | dev->dev_addr[1] = hi & 0xff; | |
14469 | dev->dev_addr[0] = (hi >> 8) & 0xff; | |
14470 | } | |
1da177e4 LT |
14471 | } |
14472 | ||
14473 | if (!is_valid_ether_addr(&dev->dev_addr[0])) { | |
7582a335 | 14474 | #ifdef CONFIG_SPARC |
1da177e4 LT |
14475 | if (!tg3_get_default_macaddr_sparc(tp)) |
14476 | return 0; | |
14477 | #endif | |
14478 | return -EINVAL; | |
14479 | } | |
2ff43697 | 14480 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
1da177e4 LT |
14481 | return 0; |
14482 | } | |
14483 | ||
59e6b434 DM |
14484 | #define BOUNDARY_SINGLE_CACHELINE 1 |
14485 | #define BOUNDARY_MULTI_CACHELINE 2 | |
14486 | ||
14487 | static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val) | |
14488 | { | |
14489 | int cacheline_size; | |
14490 | u8 byte; | |
14491 | int goal; | |
14492 | ||
14493 | pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte); | |
14494 | if (byte == 0) | |
14495 | cacheline_size = 1024; | |
14496 | else | |
14497 | cacheline_size = (int) byte * 4; | |
14498 | ||
14499 | /* On 5703 and later chips, the boundary bits have no | |
14500 | * effect. | |
14501 | */ | |
14502 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
14503 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 && | |
63c3a66f | 14504 | !tg3_flag(tp, PCI_EXPRESS)) |
59e6b434 DM |
14505 | goto out; |
14506 | ||
14507 | #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC) | |
14508 | goal = BOUNDARY_MULTI_CACHELINE; | |
14509 | #else | |
14510 | #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA) | |
14511 | goal = BOUNDARY_SINGLE_CACHELINE; | |
14512 | #else | |
14513 | goal = 0; | |
14514 | #endif | |
14515 | #endif | |
14516 | ||
63c3a66f | 14517 | if (tg3_flag(tp, 57765_PLUS)) { |
cbf9ca6c MC |
14518 | val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT; |
14519 | goto out; | |
14520 | } | |
14521 | ||
59e6b434 DM |
14522 | if (!goal) |
14523 | goto out; | |
14524 | ||
14525 | /* PCI controllers on most RISC systems tend to disconnect | |
14526 | * when a device tries to burst across a cache-line boundary. | |
14527 | * Therefore, letting tg3 do so just wastes PCI bandwidth. | |
14528 | * | |
14529 | * Unfortunately, for PCI-E there are only limited | |
14530 | * write-side controls for this, and thus for reads | |
14531 | * we will still get the disconnects. We'll also waste | |
14532 | * these PCI cycles for both read and write for chips | |
14533 | * other than 5700 and 5701 which do not implement the | |
14534 | * boundary bits. | |
14535 | */ | |
63c3a66f | 14536 | if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) { |
59e6b434 DM |
14537 | switch (cacheline_size) { |
14538 | case 16: | |
14539 | case 32: | |
14540 | case 64: | |
14541 | case 128: | |
14542 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14543 | val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX | | |
14544 | DMA_RWCTRL_WRITE_BNDRY_128_PCIX); | |
14545 | } else { | |
14546 | val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX | | |
14547 | DMA_RWCTRL_WRITE_BNDRY_384_PCIX); | |
14548 | } | |
14549 | break; | |
14550 | ||
14551 | case 256: | |
14552 | val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX | | |
14553 | DMA_RWCTRL_WRITE_BNDRY_256_PCIX); | |
14554 | break; | |
14555 | ||
14556 | default: | |
14557 | val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX | | |
14558 | DMA_RWCTRL_WRITE_BNDRY_384_PCIX); | |
14559 | break; | |
855e1111 | 14560 | } |
63c3a66f | 14561 | } else if (tg3_flag(tp, PCI_EXPRESS)) { |
59e6b434 DM |
14562 | switch (cacheline_size) { |
14563 | case 16: | |
14564 | case 32: | |
14565 | case 64: | |
14566 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14567 | val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE; | |
14568 | val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE; | |
14569 | break; | |
14570 | } | |
14571 | /* fallthrough */ | |
14572 | case 128: | |
14573 | default: | |
14574 | val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE; | |
14575 | val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE; | |
14576 | break; | |
855e1111 | 14577 | } |
59e6b434 DM |
14578 | } else { |
14579 | switch (cacheline_size) { | |
14580 | case 16: | |
14581 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14582 | val |= (DMA_RWCTRL_READ_BNDRY_16 | | |
14583 | DMA_RWCTRL_WRITE_BNDRY_16); | |
14584 | break; | |
14585 | } | |
14586 | /* fallthrough */ | |
14587 | case 32: | |
14588 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14589 | val |= (DMA_RWCTRL_READ_BNDRY_32 | | |
14590 | DMA_RWCTRL_WRITE_BNDRY_32); | |
14591 | break; | |
14592 | } | |
14593 | /* fallthrough */ | |
14594 | case 64: | |
14595 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14596 | val |= (DMA_RWCTRL_READ_BNDRY_64 | | |
14597 | DMA_RWCTRL_WRITE_BNDRY_64); | |
14598 | break; | |
14599 | } | |
14600 | /* fallthrough */ | |
14601 | case 128: | |
14602 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14603 | val |= (DMA_RWCTRL_READ_BNDRY_128 | | |
14604 | DMA_RWCTRL_WRITE_BNDRY_128); | |
14605 | break; | |
14606 | } | |
14607 | /* fallthrough */ | |
14608 | case 256: | |
14609 | val |= (DMA_RWCTRL_READ_BNDRY_256 | | |
14610 | DMA_RWCTRL_WRITE_BNDRY_256); | |
14611 | break; | |
14612 | case 512: | |
14613 | val |= (DMA_RWCTRL_READ_BNDRY_512 | | |
14614 | DMA_RWCTRL_WRITE_BNDRY_512); | |
14615 | break; | |
14616 | case 1024: | |
14617 | default: | |
14618 | val |= (DMA_RWCTRL_READ_BNDRY_1024 | | |
14619 | DMA_RWCTRL_WRITE_BNDRY_1024); | |
14620 | break; | |
855e1111 | 14621 | } |
59e6b434 DM |
14622 | } |
14623 | ||
14624 | out: | |
14625 | return val; | |
14626 | } | |
14627 | ||
1da177e4 LT |
14628 | static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device) |
14629 | { | |
14630 | struct tg3_internal_buffer_desc test_desc; | |
14631 | u32 sram_dma_descs; | |
14632 | int i, ret; | |
14633 | ||
14634 | sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE; | |
14635 | ||
14636 | tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0); | |
14637 | tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0); | |
14638 | tw32(RDMAC_STATUS, 0); | |
14639 | tw32(WDMAC_STATUS, 0); | |
14640 | ||
14641 | tw32(BUFMGR_MODE, 0); | |
14642 | tw32(FTQ_RESET, 0); | |
14643 | ||
14644 | test_desc.addr_hi = ((u64) buf_dma) >> 32; | |
14645 | test_desc.addr_lo = buf_dma & 0xffffffff; | |
14646 | test_desc.nic_mbuf = 0x00002100; | |
14647 | test_desc.len = size; | |
14648 | ||
14649 | /* | |
14650 | * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz | |
14651 | * the *second* time the tg3 driver was getting loaded after an | |
14652 | * initial scan. | |
14653 | * | |
14654 | * Broadcom tells me: | |
14655 | * ...the DMA engine is connected to the GRC block and a DMA | |
14656 | * reset may affect the GRC block in some unpredictable way... | |
14657 | * The behavior of resets to individual blocks has not been tested. | |
14658 | * | |
14659 | * Broadcom noted the GRC reset will also reset all sub-components. | |
14660 | */ | |
14661 | if (to_device) { | |
14662 | test_desc.cqid_sqid = (13 << 8) | 2; | |
14663 | ||
14664 | tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE); | |
14665 | udelay(40); | |
14666 | } else { | |
14667 | test_desc.cqid_sqid = (16 << 8) | 7; | |
14668 | ||
14669 | tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE); | |
14670 | udelay(40); | |
14671 | } | |
14672 | test_desc.flags = 0x00000005; | |
14673 | ||
14674 | for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) { | |
14675 | u32 val; | |
14676 | ||
14677 | val = *(((u32 *)&test_desc) + i); | |
14678 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, | |
14679 | sram_dma_descs + (i * sizeof(u32))); | |
14680 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
14681 | } | |
14682 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
14683 | ||
859a5887 | 14684 | if (to_device) |
1da177e4 | 14685 | tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs); |
859a5887 | 14686 | else |
1da177e4 | 14687 | tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs); |
1da177e4 LT |
14688 | |
14689 | ret = -ENODEV; | |
14690 | for (i = 0; i < 40; i++) { | |
14691 | u32 val; | |
14692 | ||
14693 | if (to_device) | |
14694 | val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ); | |
14695 | else | |
14696 | val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ); | |
14697 | if ((val & 0xffff) == sram_dma_descs) { | |
14698 | ret = 0; | |
14699 | break; | |
14700 | } | |
14701 | ||
14702 | udelay(100); | |
14703 | } | |
14704 | ||
14705 | return ret; | |
14706 | } | |
14707 | ||
ded7340d | 14708 | #define TEST_BUFFER_SIZE 0x2000 |
1da177e4 | 14709 | |
4143470c | 14710 | static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = { |
895950c2 JP |
14711 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) }, |
14712 | { }, | |
14713 | }; | |
14714 | ||
1da177e4 LT |
14715 | static int __devinit tg3_test_dma(struct tg3 *tp) |
14716 | { | |
14717 | dma_addr_t buf_dma; | |
59e6b434 | 14718 | u32 *buf, saved_dma_rwctrl; |
cbf9ca6c | 14719 | int ret = 0; |
1da177e4 | 14720 | |
4bae65c8 MC |
14721 | buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, |
14722 | &buf_dma, GFP_KERNEL); | |
1da177e4 LT |
14723 | if (!buf) { |
14724 | ret = -ENOMEM; | |
14725 | goto out_nofree; | |
14726 | } | |
14727 | ||
14728 | tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) | | |
14729 | (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT)); | |
14730 | ||
59e6b434 | 14731 | tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl); |
1da177e4 | 14732 | |
63c3a66f | 14733 | if (tg3_flag(tp, 57765_PLUS)) |
cbf9ca6c MC |
14734 | goto out; |
14735 | ||
63c3a66f | 14736 | if (tg3_flag(tp, PCI_EXPRESS)) { |
1da177e4 LT |
14737 | /* DMA read watermark not used on PCIE */ |
14738 | tp->dma_rwctrl |= 0x00180000; | |
63c3a66f | 14739 | } else if (!tg3_flag(tp, PCIX_MODE)) { |
85e94ced MC |
14740 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 || |
14741 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) | |
1da177e4 LT |
14742 | tp->dma_rwctrl |= 0x003f0000; |
14743 | else | |
14744 | tp->dma_rwctrl |= 0x003f000f; | |
14745 | } else { | |
14746 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
14747 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
14748 | u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f); | |
49afdeb6 | 14749 | u32 read_water = 0x7; |
1da177e4 | 14750 | |
4a29cc2e MC |
14751 | /* If the 5704 is behind the EPB bridge, we can |
14752 | * do the less restrictive ONE_DMA workaround for | |
14753 | * better performance. | |
14754 | */ | |
63c3a66f | 14755 | if (tg3_flag(tp, 40BIT_DMA_BUG) && |
4a29cc2e MC |
14756 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) |
14757 | tp->dma_rwctrl |= 0x8000; | |
14758 | else if (ccval == 0x6 || ccval == 0x7) | |
1da177e4 LT |
14759 | tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; |
14760 | ||
49afdeb6 MC |
14761 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) |
14762 | read_water = 4; | |
59e6b434 | 14763 | /* Set bit 23 to enable PCIX hw bug fix */ |
49afdeb6 MC |
14764 | tp->dma_rwctrl |= |
14765 | (read_water << DMA_RWCTRL_READ_WATER_SHIFT) | | |
14766 | (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) | | |
14767 | (1 << 23); | |
4cf78e4f MC |
14768 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) { |
14769 | /* 5780 always in PCIX mode */ | |
14770 | tp->dma_rwctrl |= 0x00144000; | |
a4e2b347 MC |
14771 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { |
14772 | /* 5714 always in PCIX mode */ | |
14773 | tp->dma_rwctrl |= 0x00148000; | |
1da177e4 LT |
14774 | } else { |
14775 | tp->dma_rwctrl |= 0x001b000f; | |
14776 | } | |
14777 | } | |
14778 | ||
14779 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
14780 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) | |
14781 | tp->dma_rwctrl &= 0xfffffff0; | |
14782 | ||
14783 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
14784 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
14785 | /* Remove this if it causes problems for some boards. */ | |
14786 | tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT; | |
14787 | ||
14788 | /* On 5700/5701 chips, we need to set this bit. | |
14789 | * Otherwise the chip will issue cacheline transactions | |
14790 | * to streamable DMA memory with not all the byte | |
14791 | * enables turned on. This is an error on several | |
14792 | * RISC PCI controllers, in particular sparc64. | |
14793 | * | |
14794 | * On 5703/5704 chips, this bit has been reassigned | |
14795 | * a different meaning. In particular, it is used | |
14796 | * on those chips to enable a PCI-X workaround. | |
14797 | */ | |
14798 | tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE; | |
14799 | } | |
14800 | ||
14801 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
14802 | ||
14803 | #if 0 | |
14804 | /* Unneeded, already done by tg3_get_invariants. */ | |
14805 | tg3_switch_clocks(tp); | |
14806 | #endif | |
14807 | ||
1da177e4 LT |
14808 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && |
14809 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) | |
14810 | goto out; | |
14811 | ||
59e6b434 DM |
14812 | /* It is best to perform DMA test with maximum write burst size |
14813 | * to expose the 5700/5701 write DMA bug. | |
14814 | */ | |
14815 | saved_dma_rwctrl = tp->dma_rwctrl; | |
14816 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; | |
14817 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
14818 | ||
1da177e4 LT |
14819 | while (1) { |
14820 | u32 *p = buf, i; | |
14821 | ||
14822 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) | |
14823 | p[i] = i; | |
14824 | ||
14825 | /* Send the buffer to the chip. */ | |
14826 | ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1); | |
14827 | if (ret) { | |
2445e461 MC |
14828 | dev_err(&tp->pdev->dev, |
14829 | "%s: Buffer write failed. err = %d\n", | |
14830 | __func__, ret); | |
1da177e4 LT |
14831 | break; |
14832 | } | |
14833 | ||
14834 | #if 0 | |
14835 | /* validate data reached card RAM correctly. */ | |
14836 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) { | |
14837 | u32 val; | |
14838 | tg3_read_mem(tp, 0x2100 + (i*4), &val); | |
14839 | if (le32_to_cpu(val) != p[i]) { | |
2445e461 MC |
14840 | dev_err(&tp->pdev->dev, |
14841 | "%s: Buffer corrupted on device! " | |
14842 | "(%d != %d)\n", __func__, val, i); | |
1da177e4 LT |
14843 | /* ret = -ENODEV here? */ |
14844 | } | |
14845 | p[i] = 0; | |
14846 | } | |
14847 | #endif | |
14848 | /* Now read it back. */ | |
14849 | ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0); | |
14850 | if (ret) { | |
5129c3a3 MC |
14851 | dev_err(&tp->pdev->dev, "%s: Buffer read failed. " |
14852 | "err = %d\n", __func__, ret); | |
1da177e4 LT |
14853 | break; |
14854 | } | |
14855 | ||
14856 | /* Verify it. */ | |
14857 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) { | |
14858 | if (p[i] == i) | |
14859 | continue; | |
14860 | ||
59e6b434 DM |
14861 | if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != |
14862 | DMA_RWCTRL_WRITE_BNDRY_16) { | |
14863 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; | |
1da177e4 LT |
14864 | tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; |
14865 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
14866 | break; | |
14867 | } else { | |
2445e461 MC |
14868 | dev_err(&tp->pdev->dev, |
14869 | "%s: Buffer corrupted on read back! " | |
14870 | "(%d != %d)\n", __func__, p[i], i); | |
1da177e4 LT |
14871 | ret = -ENODEV; |
14872 | goto out; | |
14873 | } | |
14874 | } | |
14875 | ||
14876 | if (i == (TEST_BUFFER_SIZE / sizeof(u32))) { | |
14877 | /* Success. */ | |
14878 | ret = 0; | |
14879 | break; | |
14880 | } | |
14881 | } | |
59e6b434 DM |
14882 | if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != |
14883 | DMA_RWCTRL_WRITE_BNDRY_16) { | |
14884 | /* DMA test passed without adjusting DMA boundary, | |
6d1cfbab MC |
14885 | * now look for chipsets that are known to expose the |
14886 | * DMA bug without failing the test. | |
59e6b434 | 14887 | */ |
4143470c | 14888 | if (pci_dev_present(tg3_dma_wait_state_chipsets)) { |
6d1cfbab MC |
14889 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; |
14890 | tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; | |
859a5887 | 14891 | } else { |
6d1cfbab MC |
14892 | /* Safe to use the calculated DMA boundary. */ |
14893 | tp->dma_rwctrl = saved_dma_rwctrl; | |
859a5887 | 14894 | } |
6d1cfbab | 14895 | |
59e6b434 DM |
14896 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); |
14897 | } | |
1da177e4 LT |
14898 | |
14899 | out: | |
4bae65c8 | 14900 | dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma); |
1da177e4 LT |
14901 | out_nofree: |
14902 | return ret; | |
14903 | } | |
14904 | ||
1da177e4 LT |
14905 | static void __devinit tg3_init_bufmgr_config(struct tg3 *tp) |
14906 | { | |
63c3a66f | 14907 | if (tg3_flag(tp, 57765_PLUS)) { |
666bc831 MC |
14908 | tp->bufmgr_config.mbuf_read_dma_low_water = |
14909 | DEFAULT_MB_RDMA_LOW_WATER_5705; | |
14910 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
14911 | DEFAULT_MB_MACRX_LOW_WATER_57765; | |
14912 | tp->bufmgr_config.mbuf_high_water = | |
14913 | DEFAULT_MB_HIGH_WATER_57765; | |
14914 | ||
14915 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = | |
14916 | DEFAULT_MB_RDMA_LOW_WATER_5705; | |
14917 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = | |
14918 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765; | |
14919 | tp->bufmgr_config.mbuf_high_water_jumbo = | |
14920 | DEFAULT_MB_HIGH_WATER_JUMBO_57765; | |
63c3a66f | 14921 | } else if (tg3_flag(tp, 5705_PLUS)) { |
fdfec172 MC |
14922 | tp->bufmgr_config.mbuf_read_dma_low_water = |
14923 | DEFAULT_MB_RDMA_LOW_WATER_5705; | |
14924 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
14925 | DEFAULT_MB_MACRX_LOW_WATER_5705; | |
14926 | tp->bufmgr_config.mbuf_high_water = | |
14927 | DEFAULT_MB_HIGH_WATER_5705; | |
b5d3772c MC |
14928 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
14929 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
14930 | DEFAULT_MB_MACRX_LOW_WATER_5906; | |
14931 | tp->bufmgr_config.mbuf_high_water = | |
14932 | DEFAULT_MB_HIGH_WATER_5906; | |
14933 | } | |
fdfec172 MC |
14934 | |
14935 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = | |
14936 | DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780; | |
14937 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = | |
14938 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780; | |
14939 | tp->bufmgr_config.mbuf_high_water_jumbo = | |
14940 | DEFAULT_MB_HIGH_WATER_JUMBO_5780; | |
14941 | } else { | |
14942 | tp->bufmgr_config.mbuf_read_dma_low_water = | |
14943 | DEFAULT_MB_RDMA_LOW_WATER; | |
14944 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
14945 | DEFAULT_MB_MACRX_LOW_WATER; | |
14946 | tp->bufmgr_config.mbuf_high_water = | |
14947 | DEFAULT_MB_HIGH_WATER; | |
14948 | ||
14949 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = | |
14950 | DEFAULT_MB_RDMA_LOW_WATER_JUMBO; | |
14951 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = | |
14952 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO; | |
14953 | tp->bufmgr_config.mbuf_high_water_jumbo = | |
14954 | DEFAULT_MB_HIGH_WATER_JUMBO; | |
14955 | } | |
1da177e4 LT |
14956 | |
14957 | tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER; | |
14958 | tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER; | |
14959 | } | |
14960 | ||
14961 | static char * __devinit tg3_phy_string(struct tg3 *tp) | |
14962 | { | |
79eb6904 MC |
14963 | switch (tp->phy_id & TG3_PHY_ID_MASK) { |
14964 | case TG3_PHY_ID_BCM5400: return "5400"; | |
14965 | case TG3_PHY_ID_BCM5401: return "5401"; | |
14966 | case TG3_PHY_ID_BCM5411: return "5411"; | |
14967 | case TG3_PHY_ID_BCM5701: return "5701"; | |
14968 | case TG3_PHY_ID_BCM5703: return "5703"; | |
14969 | case TG3_PHY_ID_BCM5704: return "5704"; | |
14970 | case TG3_PHY_ID_BCM5705: return "5705"; | |
14971 | case TG3_PHY_ID_BCM5750: return "5750"; | |
14972 | case TG3_PHY_ID_BCM5752: return "5752"; | |
14973 | case TG3_PHY_ID_BCM5714: return "5714"; | |
14974 | case TG3_PHY_ID_BCM5780: return "5780"; | |
14975 | case TG3_PHY_ID_BCM5755: return "5755"; | |
14976 | case TG3_PHY_ID_BCM5787: return "5787"; | |
14977 | case TG3_PHY_ID_BCM5784: return "5784"; | |
14978 | case TG3_PHY_ID_BCM5756: return "5722/5756"; | |
14979 | case TG3_PHY_ID_BCM5906: return "5906"; | |
14980 | case TG3_PHY_ID_BCM5761: return "5761"; | |
14981 | case TG3_PHY_ID_BCM5718C: return "5718C"; | |
14982 | case TG3_PHY_ID_BCM5718S: return "5718S"; | |
14983 | case TG3_PHY_ID_BCM57765: return "57765"; | |
302b500b | 14984 | case TG3_PHY_ID_BCM5719C: return "5719C"; |
6418f2c1 | 14985 | case TG3_PHY_ID_BCM5720C: return "5720C"; |
79eb6904 | 14986 | case TG3_PHY_ID_BCM8002: return "8002/serdes"; |
1da177e4 LT |
14987 | case 0: return "serdes"; |
14988 | default: return "unknown"; | |
855e1111 | 14989 | } |
1da177e4 LT |
14990 | } |
14991 | ||
f9804ddb MC |
14992 | static char * __devinit tg3_bus_string(struct tg3 *tp, char *str) |
14993 | { | |
63c3a66f | 14994 | if (tg3_flag(tp, PCI_EXPRESS)) { |
f9804ddb MC |
14995 | strcpy(str, "PCI Express"); |
14996 | return str; | |
63c3a66f | 14997 | } else if (tg3_flag(tp, PCIX_MODE)) { |
f9804ddb MC |
14998 | u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f; |
14999 | ||
15000 | strcpy(str, "PCIX:"); | |
15001 | ||
15002 | if ((clock_ctrl == 7) || | |
15003 | ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) == | |
15004 | GRC_MISC_CFG_BOARD_ID_5704CIOBE)) | |
15005 | strcat(str, "133MHz"); | |
15006 | else if (clock_ctrl == 0) | |
15007 | strcat(str, "33MHz"); | |
15008 | else if (clock_ctrl == 2) | |
15009 | strcat(str, "50MHz"); | |
15010 | else if (clock_ctrl == 4) | |
15011 | strcat(str, "66MHz"); | |
15012 | else if (clock_ctrl == 6) | |
15013 | strcat(str, "100MHz"); | |
f9804ddb MC |
15014 | } else { |
15015 | strcpy(str, "PCI:"); | |
63c3a66f | 15016 | if (tg3_flag(tp, PCI_HIGH_SPEED)) |
f9804ddb MC |
15017 | strcat(str, "66MHz"); |
15018 | else | |
15019 | strcat(str, "33MHz"); | |
15020 | } | |
63c3a66f | 15021 | if (tg3_flag(tp, PCI_32BIT)) |
f9804ddb MC |
15022 | strcat(str, ":32-bit"); |
15023 | else | |
15024 | strcat(str, ":64-bit"); | |
15025 | return str; | |
15026 | } | |
15027 | ||
8c2dc7e1 | 15028 | static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp) |
1da177e4 LT |
15029 | { |
15030 | struct pci_dev *peer; | |
15031 | unsigned int func, devnr = tp->pdev->devfn & ~7; | |
15032 | ||
15033 | for (func = 0; func < 8; func++) { | |
15034 | peer = pci_get_slot(tp->pdev->bus, devnr | func); | |
15035 | if (peer && peer != tp->pdev) | |
15036 | break; | |
15037 | pci_dev_put(peer); | |
15038 | } | |
16fe9d74 MC |
15039 | /* 5704 can be configured in single-port mode, set peer to |
15040 | * tp->pdev in that case. | |
15041 | */ | |
15042 | if (!peer) { | |
15043 | peer = tp->pdev; | |
15044 | return peer; | |
15045 | } | |
1da177e4 LT |
15046 | |
15047 | /* | |
15048 | * We don't need to keep the refcount elevated; there's no way | |
15049 | * to remove one half of this device without removing the other | |
15050 | */ | |
15051 | pci_dev_put(peer); | |
15052 | ||
15053 | return peer; | |
15054 | } | |
15055 | ||
15f9850d DM |
15056 | static void __devinit tg3_init_coal(struct tg3 *tp) |
15057 | { | |
15058 | struct ethtool_coalesce *ec = &tp->coal; | |
15059 | ||
15060 | memset(ec, 0, sizeof(*ec)); | |
15061 | ec->cmd = ETHTOOL_GCOALESCE; | |
15062 | ec->rx_coalesce_usecs = LOW_RXCOL_TICKS; | |
15063 | ec->tx_coalesce_usecs = LOW_TXCOL_TICKS; | |
15064 | ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES; | |
15065 | ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES; | |
15066 | ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT; | |
15067 | ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT; | |
15068 | ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT; | |
15069 | ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT; | |
15070 | ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS; | |
15071 | ||
15072 | if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD | | |
15073 | HOSTCC_MODE_CLRTICK_TXBD)) { | |
15074 | ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS; | |
15075 | ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS; | |
15076 | ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS; | |
15077 | ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS; | |
15078 | } | |
d244c892 | 15079 | |
63c3a66f | 15080 | if (tg3_flag(tp, 5705_PLUS)) { |
d244c892 MC |
15081 | ec->rx_coalesce_usecs_irq = 0; |
15082 | ec->tx_coalesce_usecs_irq = 0; | |
15083 | ec->stats_block_coalesce_usecs = 0; | |
15084 | } | |
15f9850d DM |
15085 | } |
15086 | ||
7c7d64b8 SH |
15087 | static const struct net_device_ops tg3_netdev_ops = { |
15088 | .ndo_open = tg3_open, | |
15089 | .ndo_stop = tg3_close, | |
00829823 | 15090 | .ndo_start_xmit = tg3_start_xmit, |
511d2224 | 15091 | .ndo_get_stats64 = tg3_get_stats64, |
00829823 SH |
15092 | .ndo_validate_addr = eth_validate_addr, |
15093 | .ndo_set_multicast_list = tg3_set_rx_mode, | |
15094 | .ndo_set_mac_address = tg3_set_mac_addr, | |
15095 | .ndo_do_ioctl = tg3_ioctl, | |
15096 | .ndo_tx_timeout = tg3_tx_timeout, | |
15097 | .ndo_change_mtu = tg3_change_mtu, | |
dc668910 | 15098 | .ndo_fix_features = tg3_fix_features, |
06c03c02 | 15099 | .ndo_set_features = tg3_set_features, |
00829823 SH |
15100 | #ifdef CONFIG_NET_POLL_CONTROLLER |
15101 | .ndo_poll_controller = tg3_poll_controller, | |
15102 | #endif | |
15103 | }; | |
15104 | ||
1da177e4 LT |
15105 | static int __devinit tg3_init_one(struct pci_dev *pdev, |
15106 | const struct pci_device_id *ent) | |
15107 | { | |
1da177e4 LT |
15108 | struct net_device *dev; |
15109 | struct tg3 *tp; | |
646c9edd MC |
15110 | int i, err, pm_cap; |
15111 | u32 sndmbx, rcvmbx, intmbx; | |
f9804ddb | 15112 | char str[40]; |
72f2afb8 | 15113 | u64 dma_mask, persist_dma_mask; |
0da0606f | 15114 | u32 features = 0; |
1da177e4 | 15115 | |
05dbe005 | 15116 | printk_once(KERN_INFO "%s\n", version); |
1da177e4 LT |
15117 | |
15118 | err = pci_enable_device(pdev); | |
15119 | if (err) { | |
2445e461 | 15120 | dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); |
1da177e4 LT |
15121 | return err; |
15122 | } | |
15123 | ||
1da177e4 LT |
15124 | err = pci_request_regions(pdev, DRV_MODULE_NAME); |
15125 | if (err) { | |
2445e461 | 15126 | dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); |
1da177e4 LT |
15127 | goto err_out_disable_pdev; |
15128 | } | |
15129 | ||
15130 | pci_set_master(pdev); | |
15131 | ||
15132 | /* Find power-management capability. */ | |
15133 | pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); | |
15134 | if (pm_cap == 0) { | |
2445e461 MC |
15135 | dev_err(&pdev->dev, |
15136 | "Cannot find Power Management capability, aborting\n"); | |
1da177e4 LT |
15137 | err = -EIO; |
15138 | goto err_out_free_res; | |
15139 | } | |
15140 | ||
16821285 MC |
15141 | err = pci_set_power_state(pdev, PCI_D0); |
15142 | if (err) { | |
15143 | dev_err(&pdev->dev, "Transition to D0 failed, aborting\n"); | |
15144 | goto err_out_free_res; | |
15145 | } | |
15146 | ||
fe5f5787 | 15147 | dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS); |
1da177e4 | 15148 | if (!dev) { |
2445e461 | 15149 | dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n"); |
1da177e4 | 15150 | err = -ENOMEM; |
16821285 | 15151 | goto err_out_power_down; |
1da177e4 LT |
15152 | } |
15153 | ||
1da177e4 LT |
15154 | SET_NETDEV_DEV(dev, &pdev->dev); |
15155 | ||
1da177e4 LT |
15156 | tp = netdev_priv(dev); |
15157 | tp->pdev = pdev; | |
15158 | tp->dev = dev; | |
15159 | tp->pm_cap = pm_cap; | |
1da177e4 LT |
15160 | tp->rx_mode = TG3_DEF_RX_MODE; |
15161 | tp->tx_mode = TG3_DEF_TX_MODE; | |
8ef21428 | 15162 | |
1da177e4 LT |
15163 | if (tg3_debug > 0) |
15164 | tp->msg_enable = tg3_debug; | |
15165 | else | |
15166 | tp->msg_enable = TG3_DEF_MSG_ENABLE; | |
15167 | ||
15168 | /* The word/byte swap controls here control register access byte | |
15169 | * swapping. DMA data byte swapping is controlled in the GRC_MODE | |
15170 | * setting below. | |
15171 | */ | |
15172 | tp->misc_host_ctrl = | |
15173 | MISC_HOST_CTRL_MASK_PCI_INT | | |
15174 | MISC_HOST_CTRL_WORD_SWAP | | |
15175 | MISC_HOST_CTRL_INDIR_ACCESS | | |
15176 | MISC_HOST_CTRL_PCISTATE_RW; | |
15177 | ||
15178 | /* The NONFRM (non-frame) byte/word swap controls take effect | |
15179 | * on descriptor entries, anything which isn't packet data. | |
15180 | * | |
15181 | * The StrongARM chips on the board (one for tx, one for rx) | |
15182 | * are running in big-endian mode. | |
15183 | */ | |
15184 | tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA | | |
15185 | GRC_MODE_WSWAP_NONFRM_DATA); | |
15186 | #ifdef __BIG_ENDIAN | |
15187 | tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA; | |
15188 | #endif | |
15189 | spin_lock_init(&tp->lock); | |
1da177e4 | 15190 | spin_lock_init(&tp->indirect_lock); |
c4028958 | 15191 | INIT_WORK(&tp->reset_task, tg3_reset_task); |
1da177e4 | 15192 | |
d5fe488a | 15193 | tp->regs = pci_ioremap_bar(pdev, BAR_0); |
ab0049b4 | 15194 | if (!tp->regs) { |
ab96b241 | 15195 | dev_err(&pdev->dev, "Cannot map device registers, aborting\n"); |
1da177e4 LT |
15196 | err = -ENOMEM; |
15197 | goto err_out_free_dev; | |
15198 | } | |
15199 | ||
c9cab24e MC |
15200 | if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || |
15201 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E || | |
15202 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S || | |
15203 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE || | |
15204 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || | |
15205 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 || | |
15206 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 || | |
15207 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720) { | |
15208 | tg3_flag_set(tp, ENABLE_APE); | |
15209 | tp->aperegs = pci_ioremap_bar(pdev, BAR_2); | |
15210 | if (!tp->aperegs) { | |
15211 | dev_err(&pdev->dev, | |
15212 | "Cannot map APE registers, aborting\n"); | |
15213 | err = -ENOMEM; | |
15214 | goto err_out_iounmap; | |
15215 | } | |
15216 | } | |
15217 | ||
1da177e4 LT |
15218 | tp->rx_pending = TG3_DEF_RX_RING_PENDING; |
15219 | tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING; | |
1da177e4 | 15220 | |
1da177e4 | 15221 | dev->ethtool_ops = &tg3_ethtool_ops; |
1da177e4 | 15222 | dev->watchdog_timeo = TG3_TX_TIMEOUT; |
2ffcc981 | 15223 | dev->netdev_ops = &tg3_netdev_ops; |
1da177e4 | 15224 | dev->irq = pdev->irq; |
1da177e4 LT |
15225 | |
15226 | err = tg3_get_invariants(tp); | |
15227 | if (err) { | |
ab96b241 MC |
15228 | dev_err(&pdev->dev, |
15229 | "Problem fetching invariants of chip, aborting\n"); | |
c9cab24e | 15230 | goto err_out_apeunmap; |
1da177e4 LT |
15231 | } |
15232 | ||
4a29cc2e MC |
15233 | /* The EPB bridge inside 5714, 5715, and 5780 and any |
15234 | * device behind the EPB cannot support DMA addresses > 40-bit. | |
72f2afb8 MC |
15235 | * On 64-bit systems with IOMMU, use 40-bit dma_mask. |
15236 | * On 64-bit systems without IOMMU, use 64-bit dma_mask and | |
15237 | * do DMA address check in tg3_start_xmit(). | |
15238 | */ | |
63c3a66f | 15239 | if (tg3_flag(tp, IS_5788)) |
284901a9 | 15240 | persist_dma_mask = dma_mask = DMA_BIT_MASK(32); |
63c3a66f | 15241 | else if (tg3_flag(tp, 40BIT_DMA_BUG)) { |
50cf156a | 15242 | persist_dma_mask = dma_mask = DMA_BIT_MASK(40); |
72f2afb8 | 15243 | #ifdef CONFIG_HIGHMEM |
6a35528a | 15244 | dma_mask = DMA_BIT_MASK(64); |
72f2afb8 | 15245 | #endif |
4a29cc2e | 15246 | } else |
6a35528a | 15247 | persist_dma_mask = dma_mask = DMA_BIT_MASK(64); |
72f2afb8 MC |
15248 | |
15249 | /* Configure DMA attributes. */ | |
284901a9 | 15250 | if (dma_mask > DMA_BIT_MASK(32)) { |
72f2afb8 MC |
15251 | err = pci_set_dma_mask(pdev, dma_mask); |
15252 | if (!err) { | |
0da0606f | 15253 | features |= NETIF_F_HIGHDMA; |
72f2afb8 MC |
15254 | err = pci_set_consistent_dma_mask(pdev, |
15255 | persist_dma_mask); | |
15256 | if (err < 0) { | |
ab96b241 MC |
15257 | dev_err(&pdev->dev, "Unable to obtain 64 bit " |
15258 | "DMA for consistent allocations\n"); | |
c9cab24e | 15259 | goto err_out_apeunmap; |
72f2afb8 MC |
15260 | } |
15261 | } | |
15262 | } | |
284901a9 YH |
15263 | if (err || dma_mask == DMA_BIT_MASK(32)) { |
15264 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
72f2afb8 | 15265 | if (err) { |
ab96b241 MC |
15266 | dev_err(&pdev->dev, |
15267 | "No usable DMA configuration, aborting\n"); | |
c9cab24e | 15268 | goto err_out_apeunmap; |
72f2afb8 MC |
15269 | } |
15270 | } | |
15271 | ||
fdfec172 | 15272 | tg3_init_bufmgr_config(tp); |
1da177e4 | 15273 | |
0da0606f MC |
15274 | features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; |
15275 | ||
15276 | /* 5700 B0 chips do not support checksumming correctly due | |
15277 | * to hardware bugs. | |
15278 | */ | |
15279 | if (tp->pci_chip_rev_id != CHIPREV_ID_5700_B0) { | |
15280 | features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM; | |
15281 | ||
15282 | if (tg3_flag(tp, 5755_PLUS)) | |
15283 | features |= NETIF_F_IPV6_CSUM; | |
15284 | } | |
15285 | ||
4e3a7aaa MC |
15286 | /* TSO is on by default on chips that support hardware TSO. |
15287 | * Firmware TSO on older chips gives lower performance, so it | |
15288 | * is off by default, but can be enabled using ethtool. | |
15289 | */ | |
63c3a66f JP |
15290 | if ((tg3_flag(tp, HW_TSO_1) || |
15291 | tg3_flag(tp, HW_TSO_2) || | |
15292 | tg3_flag(tp, HW_TSO_3)) && | |
0da0606f MC |
15293 | (features & NETIF_F_IP_CSUM)) |
15294 | features |= NETIF_F_TSO; | |
63c3a66f | 15295 | if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) { |
0da0606f MC |
15296 | if (features & NETIF_F_IPV6_CSUM) |
15297 | features |= NETIF_F_TSO6; | |
63c3a66f | 15298 | if (tg3_flag(tp, HW_TSO_3) || |
e849cdc3 | 15299 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
57e6983c MC |
15300 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && |
15301 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) || | |
63c3a66f | 15302 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
dc668910 | 15303 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) |
0da0606f | 15304 | features |= NETIF_F_TSO_ECN; |
b0026624 | 15305 | } |
1da177e4 | 15306 | |
d542fe27 MC |
15307 | dev->features |= features; |
15308 | dev->vlan_features |= features; | |
15309 | ||
06c03c02 MB |
15310 | /* |
15311 | * Add loopback capability only for a subset of devices that support | |
15312 | * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY | |
15313 | * loopback for the remaining devices. | |
15314 | */ | |
15315 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780 && | |
15316 | !tg3_flag(tp, CPMU_PRESENT)) | |
15317 | /* Add the loopback capability */ | |
0da0606f MC |
15318 | features |= NETIF_F_LOOPBACK; |
15319 | ||
0da0606f | 15320 | dev->hw_features |= features; |
06c03c02 | 15321 | |
1da177e4 | 15322 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 && |
63c3a66f | 15323 | !tg3_flag(tp, TSO_CAPABLE) && |
1da177e4 | 15324 | !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) { |
63c3a66f | 15325 | tg3_flag_set(tp, MAX_RXPEND_64); |
1da177e4 LT |
15326 | tp->rx_pending = 63; |
15327 | } | |
15328 | ||
1da177e4 LT |
15329 | err = tg3_get_device_address(tp); |
15330 | if (err) { | |
ab96b241 MC |
15331 | dev_err(&pdev->dev, |
15332 | "Could not obtain valid ethernet address, aborting\n"); | |
c9cab24e | 15333 | goto err_out_apeunmap; |
c88864df MC |
15334 | } |
15335 | ||
1da177e4 LT |
15336 | /* |
15337 | * Reset chip in case UNDI or EFI driver did not shutdown | |
15338 | * DMA self test will enable WDMAC and we'll see (spurious) | |
15339 | * pending DMA on the PCI bus at that point. | |
15340 | */ | |
15341 | if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) || | |
15342 | (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { | |
1da177e4 | 15343 | tw32(MEMARB_MODE, MEMARB_MODE_ENABLE); |
944d980e | 15344 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 LT |
15345 | } |
15346 | ||
15347 | err = tg3_test_dma(tp); | |
15348 | if (err) { | |
ab96b241 | 15349 | dev_err(&pdev->dev, "DMA engine test failed, aborting\n"); |
c88864df | 15350 | goto err_out_apeunmap; |
1da177e4 LT |
15351 | } |
15352 | ||
78f90dcf MC |
15353 | intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW; |
15354 | rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW; | |
15355 | sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW; | |
6fd45cb8 | 15356 | for (i = 0; i < tp->irq_max; i++) { |
78f90dcf MC |
15357 | struct tg3_napi *tnapi = &tp->napi[i]; |
15358 | ||
15359 | tnapi->tp = tp; | |
15360 | tnapi->tx_pending = TG3_DEF_TX_RING_PENDING; | |
15361 | ||
15362 | tnapi->int_mbox = intmbx; | |
15363 | if (i < 4) | |
15364 | intmbx += 0x8; | |
15365 | else | |
15366 | intmbx += 0x4; | |
15367 | ||
15368 | tnapi->consmbox = rcvmbx; | |
15369 | tnapi->prodmbox = sndmbx; | |
15370 | ||
66cfd1bd | 15371 | if (i) |
78f90dcf | 15372 | tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1); |
66cfd1bd | 15373 | else |
78f90dcf | 15374 | tnapi->coal_now = HOSTCC_MODE_NOW; |
78f90dcf | 15375 | |
63c3a66f | 15376 | if (!tg3_flag(tp, SUPPORT_MSIX)) |
78f90dcf MC |
15377 | break; |
15378 | ||
15379 | /* | |
15380 | * If we support MSIX, we'll be using RSS. If we're using | |
15381 | * RSS, the first vector only handles link interrupts and the | |
15382 | * remaining vectors handle rx and tx interrupts. Reuse the | |
15383 | * mailbox values for the next iteration. The values we setup | |
15384 | * above are still useful for the single vectored mode. | |
15385 | */ | |
15386 | if (!i) | |
15387 | continue; | |
15388 | ||
15389 | rcvmbx += 0x8; | |
15390 | ||
15391 | if (sndmbx & 0x4) | |
15392 | sndmbx -= 0x4; | |
15393 | else | |
15394 | sndmbx += 0xc; | |
15395 | } | |
15396 | ||
15f9850d DM |
15397 | tg3_init_coal(tp); |
15398 | ||
c49a1561 MC |
15399 | pci_set_drvdata(pdev, dev); |
15400 | ||
cd0d7228 MC |
15401 | if (tg3_flag(tp, 5717_PLUS)) { |
15402 | /* Resume a low-power mode */ | |
15403 | tg3_frob_aux_power(tp, false); | |
15404 | } | |
15405 | ||
1da177e4 LT |
15406 | err = register_netdev(dev); |
15407 | if (err) { | |
ab96b241 | 15408 | dev_err(&pdev->dev, "Cannot register net device, aborting\n"); |
0d3031d9 | 15409 | goto err_out_apeunmap; |
1da177e4 LT |
15410 | } |
15411 | ||
05dbe005 JP |
15412 | netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n", |
15413 | tp->board_part_number, | |
15414 | tp->pci_chip_rev_id, | |
15415 | tg3_bus_string(tp, str), | |
15416 | dev->dev_addr); | |
1da177e4 | 15417 | |
f07e9af3 | 15418 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { |
3f0e3ad7 MC |
15419 | struct phy_device *phydev; |
15420 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; | |
5129c3a3 MC |
15421 | netdev_info(dev, |
15422 | "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n", | |
05dbe005 | 15423 | phydev->drv->name, dev_name(&phydev->dev)); |
f07e9af3 MC |
15424 | } else { |
15425 | char *ethtype; | |
15426 | ||
15427 | if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) | |
15428 | ethtype = "10/100Base-TX"; | |
15429 | else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) | |
15430 | ethtype = "1000Base-SX"; | |
15431 | else | |
15432 | ethtype = "10/100/1000Base-T"; | |
15433 | ||
5129c3a3 | 15434 | netdev_info(dev, "attached PHY is %s (%s Ethernet) " |
47007831 MC |
15435 | "(WireSpeed[%d], EEE[%d])\n", |
15436 | tg3_phy_string(tp), ethtype, | |
15437 | (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0, | |
15438 | (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0); | |
f07e9af3 | 15439 | } |
05dbe005 JP |
15440 | |
15441 | netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n", | |
dc668910 | 15442 | (dev->features & NETIF_F_RXCSUM) != 0, |
63c3a66f | 15443 | tg3_flag(tp, USE_LINKCHG_REG) != 0, |
f07e9af3 | 15444 | (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0, |
63c3a66f JP |
15445 | tg3_flag(tp, ENABLE_ASF) != 0, |
15446 | tg3_flag(tp, TSO_CAPABLE) != 0); | |
05dbe005 JP |
15447 | netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n", |
15448 | tp->dma_rwctrl, | |
15449 | pdev->dma_mask == DMA_BIT_MASK(32) ? 32 : | |
15450 | ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64); | |
1da177e4 | 15451 | |
b45aa2f6 MC |
15452 | pci_save_state(pdev); |
15453 | ||
1da177e4 LT |
15454 | return 0; |
15455 | ||
0d3031d9 MC |
15456 | err_out_apeunmap: |
15457 | if (tp->aperegs) { | |
15458 | iounmap(tp->aperegs); | |
15459 | tp->aperegs = NULL; | |
15460 | } | |
15461 | ||
1da177e4 | 15462 | err_out_iounmap: |
6892914f MC |
15463 | if (tp->regs) { |
15464 | iounmap(tp->regs); | |
22abe310 | 15465 | tp->regs = NULL; |
6892914f | 15466 | } |
1da177e4 LT |
15467 | |
15468 | err_out_free_dev: | |
15469 | free_netdev(dev); | |
15470 | ||
16821285 MC |
15471 | err_out_power_down: |
15472 | pci_set_power_state(pdev, PCI_D3hot); | |
15473 | ||
1da177e4 LT |
15474 | err_out_free_res: |
15475 | pci_release_regions(pdev); | |
15476 | ||
15477 | err_out_disable_pdev: | |
15478 | pci_disable_device(pdev); | |
15479 | pci_set_drvdata(pdev, NULL); | |
15480 | return err; | |
15481 | } | |
15482 | ||
15483 | static void __devexit tg3_remove_one(struct pci_dev *pdev) | |
15484 | { | |
15485 | struct net_device *dev = pci_get_drvdata(pdev); | |
15486 | ||
15487 | if (dev) { | |
15488 | struct tg3 *tp = netdev_priv(dev); | |
15489 | ||
077f849d JSR |
15490 | if (tp->fw) |
15491 | release_firmware(tp->fw); | |
15492 | ||
23f333a2 | 15493 | cancel_work_sync(&tp->reset_task); |
158d7abd | 15494 | |
63c3a66f | 15495 | if (!tg3_flag(tp, USE_PHYLIB)) { |
b02fd9e3 | 15496 | tg3_phy_fini(tp); |
158d7abd | 15497 | tg3_mdio_fini(tp); |
b02fd9e3 | 15498 | } |
158d7abd | 15499 | |
1da177e4 | 15500 | unregister_netdev(dev); |
0d3031d9 MC |
15501 | if (tp->aperegs) { |
15502 | iounmap(tp->aperegs); | |
15503 | tp->aperegs = NULL; | |
15504 | } | |
6892914f MC |
15505 | if (tp->regs) { |
15506 | iounmap(tp->regs); | |
22abe310 | 15507 | tp->regs = NULL; |
6892914f | 15508 | } |
1da177e4 LT |
15509 | free_netdev(dev); |
15510 | pci_release_regions(pdev); | |
15511 | pci_disable_device(pdev); | |
15512 | pci_set_drvdata(pdev, NULL); | |
15513 | } | |
15514 | } | |
15515 | ||
aa6027ca | 15516 | #ifdef CONFIG_PM_SLEEP |
c866b7ea | 15517 | static int tg3_suspend(struct device *device) |
1da177e4 | 15518 | { |
c866b7ea | 15519 | struct pci_dev *pdev = to_pci_dev(device); |
1da177e4 LT |
15520 | struct net_device *dev = pci_get_drvdata(pdev); |
15521 | struct tg3 *tp = netdev_priv(dev); | |
15522 | int err; | |
15523 | ||
15524 | if (!netif_running(dev)) | |
15525 | return 0; | |
15526 | ||
23f333a2 | 15527 | flush_work_sync(&tp->reset_task); |
b02fd9e3 | 15528 | tg3_phy_stop(tp); |
1da177e4 LT |
15529 | tg3_netif_stop(tp); |
15530 | ||
15531 | del_timer_sync(&tp->timer); | |
15532 | ||
f47c11ee | 15533 | tg3_full_lock(tp, 1); |
1da177e4 | 15534 | tg3_disable_ints(tp); |
f47c11ee | 15535 | tg3_full_unlock(tp); |
1da177e4 LT |
15536 | |
15537 | netif_device_detach(dev); | |
15538 | ||
f47c11ee | 15539 | tg3_full_lock(tp, 0); |
944d980e | 15540 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
63c3a66f | 15541 | tg3_flag_clear(tp, INIT_COMPLETE); |
f47c11ee | 15542 | tg3_full_unlock(tp); |
1da177e4 | 15543 | |
c866b7ea | 15544 | err = tg3_power_down_prepare(tp); |
1da177e4 | 15545 | if (err) { |
b02fd9e3 MC |
15546 | int err2; |
15547 | ||
f47c11ee | 15548 | tg3_full_lock(tp, 0); |
1da177e4 | 15549 | |
63c3a66f | 15550 | tg3_flag_set(tp, INIT_COMPLETE); |
b02fd9e3 MC |
15551 | err2 = tg3_restart_hw(tp, 1); |
15552 | if (err2) | |
b9ec6c1b | 15553 | goto out; |
1da177e4 LT |
15554 | |
15555 | tp->timer.expires = jiffies + tp->timer_offset; | |
15556 | add_timer(&tp->timer); | |
15557 | ||
15558 | netif_device_attach(dev); | |
15559 | tg3_netif_start(tp); | |
15560 | ||
b9ec6c1b | 15561 | out: |
f47c11ee | 15562 | tg3_full_unlock(tp); |
b02fd9e3 MC |
15563 | |
15564 | if (!err2) | |
15565 | tg3_phy_start(tp); | |
1da177e4 LT |
15566 | } |
15567 | ||
15568 | return err; | |
15569 | } | |
15570 | ||
c866b7ea | 15571 | static int tg3_resume(struct device *device) |
1da177e4 | 15572 | { |
c866b7ea | 15573 | struct pci_dev *pdev = to_pci_dev(device); |
1da177e4 LT |
15574 | struct net_device *dev = pci_get_drvdata(pdev); |
15575 | struct tg3 *tp = netdev_priv(dev); | |
15576 | int err; | |
15577 | ||
15578 | if (!netif_running(dev)) | |
15579 | return 0; | |
15580 | ||
1da177e4 LT |
15581 | netif_device_attach(dev); |
15582 | ||
f47c11ee | 15583 | tg3_full_lock(tp, 0); |
1da177e4 | 15584 | |
63c3a66f | 15585 | tg3_flag_set(tp, INIT_COMPLETE); |
b9ec6c1b MC |
15586 | err = tg3_restart_hw(tp, 1); |
15587 | if (err) | |
15588 | goto out; | |
1da177e4 LT |
15589 | |
15590 | tp->timer.expires = jiffies + tp->timer_offset; | |
15591 | add_timer(&tp->timer); | |
15592 | ||
1da177e4 LT |
15593 | tg3_netif_start(tp); |
15594 | ||
b9ec6c1b | 15595 | out: |
f47c11ee | 15596 | tg3_full_unlock(tp); |
1da177e4 | 15597 | |
b02fd9e3 MC |
15598 | if (!err) |
15599 | tg3_phy_start(tp); | |
15600 | ||
b9ec6c1b | 15601 | return err; |
1da177e4 LT |
15602 | } |
15603 | ||
c866b7ea | 15604 | static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume); |
aa6027ca ED |
15605 | #define TG3_PM_OPS (&tg3_pm_ops) |
15606 | ||
15607 | #else | |
15608 | ||
15609 | #define TG3_PM_OPS NULL | |
15610 | ||
15611 | #endif /* CONFIG_PM_SLEEP */ | |
c866b7ea | 15612 | |
b45aa2f6 MC |
15613 | /** |
15614 | * tg3_io_error_detected - called when PCI error is detected | |
15615 | * @pdev: Pointer to PCI device | |
15616 | * @state: The current pci connection state | |
15617 | * | |
15618 | * This function is called after a PCI bus error affecting | |
15619 | * this device has been detected. | |
15620 | */ | |
15621 | static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev, | |
15622 | pci_channel_state_t state) | |
15623 | { | |
15624 | struct net_device *netdev = pci_get_drvdata(pdev); | |
15625 | struct tg3 *tp = netdev_priv(netdev); | |
15626 | pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET; | |
15627 | ||
15628 | netdev_info(netdev, "PCI I/O error detected\n"); | |
15629 | ||
15630 | rtnl_lock(); | |
15631 | ||
15632 | if (!netif_running(netdev)) | |
15633 | goto done; | |
15634 | ||
15635 | tg3_phy_stop(tp); | |
15636 | ||
15637 | tg3_netif_stop(tp); | |
15638 | ||
15639 | del_timer_sync(&tp->timer); | |
63c3a66f | 15640 | tg3_flag_clear(tp, RESTART_TIMER); |
b45aa2f6 MC |
15641 | |
15642 | /* Want to make sure that the reset task doesn't run */ | |
15643 | cancel_work_sync(&tp->reset_task); | |
63c3a66f JP |
15644 | tg3_flag_clear(tp, TX_RECOVERY_PENDING); |
15645 | tg3_flag_clear(tp, RESTART_TIMER); | |
b45aa2f6 MC |
15646 | |
15647 | netif_device_detach(netdev); | |
15648 | ||
15649 | /* Clean up software state, even if MMIO is blocked */ | |
15650 | tg3_full_lock(tp, 0); | |
15651 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); | |
15652 | tg3_full_unlock(tp); | |
15653 | ||
15654 | done: | |
15655 | if (state == pci_channel_io_perm_failure) | |
15656 | err = PCI_ERS_RESULT_DISCONNECT; | |
15657 | else | |
15658 | pci_disable_device(pdev); | |
15659 | ||
15660 | rtnl_unlock(); | |
15661 | ||
15662 | return err; | |
15663 | } | |
15664 | ||
15665 | /** | |
15666 | * tg3_io_slot_reset - called after the pci bus has been reset. | |
15667 | * @pdev: Pointer to PCI device | |
15668 | * | |
15669 | * Restart the card from scratch, as if from a cold-boot. | |
15670 | * At this point, the card has exprienced a hard reset, | |
15671 | * followed by fixups by BIOS, and has its config space | |
15672 | * set up identically to what it was at cold boot. | |
15673 | */ | |
15674 | static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev) | |
15675 | { | |
15676 | struct net_device *netdev = pci_get_drvdata(pdev); | |
15677 | struct tg3 *tp = netdev_priv(netdev); | |
15678 | pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT; | |
15679 | int err; | |
15680 | ||
15681 | rtnl_lock(); | |
15682 | ||
15683 | if (pci_enable_device(pdev)) { | |
15684 | netdev_err(netdev, "Cannot re-enable PCI device after reset.\n"); | |
15685 | goto done; | |
15686 | } | |
15687 | ||
15688 | pci_set_master(pdev); | |
15689 | pci_restore_state(pdev); | |
15690 | pci_save_state(pdev); | |
15691 | ||
15692 | if (!netif_running(netdev)) { | |
15693 | rc = PCI_ERS_RESULT_RECOVERED; | |
15694 | goto done; | |
15695 | } | |
15696 | ||
15697 | err = tg3_power_up(tp); | |
bed9829f | 15698 | if (err) |
b45aa2f6 | 15699 | goto done; |
b45aa2f6 MC |
15700 | |
15701 | rc = PCI_ERS_RESULT_RECOVERED; | |
15702 | ||
15703 | done: | |
15704 | rtnl_unlock(); | |
15705 | ||
15706 | return rc; | |
15707 | } | |
15708 | ||
15709 | /** | |
15710 | * tg3_io_resume - called when traffic can start flowing again. | |
15711 | * @pdev: Pointer to PCI device | |
15712 | * | |
15713 | * This callback is called when the error recovery driver tells | |
15714 | * us that its OK to resume normal operation. | |
15715 | */ | |
15716 | static void tg3_io_resume(struct pci_dev *pdev) | |
15717 | { | |
15718 | struct net_device *netdev = pci_get_drvdata(pdev); | |
15719 | struct tg3 *tp = netdev_priv(netdev); | |
15720 | int err; | |
15721 | ||
15722 | rtnl_lock(); | |
15723 | ||
15724 | if (!netif_running(netdev)) | |
15725 | goto done; | |
15726 | ||
15727 | tg3_full_lock(tp, 0); | |
63c3a66f | 15728 | tg3_flag_set(tp, INIT_COMPLETE); |
b45aa2f6 MC |
15729 | err = tg3_restart_hw(tp, 1); |
15730 | tg3_full_unlock(tp); | |
15731 | if (err) { | |
15732 | netdev_err(netdev, "Cannot restart hardware after reset.\n"); | |
15733 | goto done; | |
15734 | } | |
15735 | ||
15736 | netif_device_attach(netdev); | |
15737 | ||
15738 | tp->timer.expires = jiffies + tp->timer_offset; | |
15739 | add_timer(&tp->timer); | |
15740 | ||
15741 | tg3_netif_start(tp); | |
15742 | ||
15743 | tg3_phy_start(tp); | |
15744 | ||
15745 | done: | |
15746 | rtnl_unlock(); | |
15747 | } | |
15748 | ||
15749 | static struct pci_error_handlers tg3_err_handler = { | |
15750 | .error_detected = tg3_io_error_detected, | |
15751 | .slot_reset = tg3_io_slot_reset, | |
15752 | .resume = tg3_io_resume | |
15753 | }; | |
15754 | ||
1da177e4 LT |
15755 | static struct pci_driver tg3_driver = { |
15756 | .name = DRV_MODULE_NAME, | |
15757 | .id_table = tg3_pci_tbl, | |
15758 | .probe = tg3_init_one, | |
15759 | .remove = __devexit_p(tg3_remove_one), | |
b45aa2f6 | 15760 | .err_handler = &tg3_err_handler, |
aa6027ca | 15761 | .driver.pm = TG3_PM_OPS, |
1da177e4 LT |
15762 | }; |
15763 | ||
15764 | static int __init tg3_init(void) | |
15765 | { | |
29917620 | 15766 | return pci_register_driver(&tg3_driver); |
1da177e4 LT |
15767 | } |
15768 | ||
15769 | static void __exit tg3_cleanup(void) | |
15770 | { | |
15771 | pci_unregister_driver(&tg3_driver); | |
15772 | } | |
15773 | ||
15774 | module_init(tg3_init); | |
15775 | module_exit(tg3_cleanup); |