Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * tg3.c: Broadcom Tigon3 ethernet driver. | |
3 | * | |
4 | * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com) | |
5 | * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com) | |
6 | * Copyright (C) 2004 Sun Microsystems Inc. | |
b86fb2cf | 7 | * Copyright (C) 2005-2011 Broadcom Corporation. |
1da177e4 LT |
8 | * |
9 | * Firmware is: | |
49cabf49 MC |
10 | * Derived from proprietary unpublished source code, |
11 | * Copyright (C) 2000-2003 Broadcom Corporation. | |
12 | * | |
13 | * Permission is hereby granted for the distribution of this firmware | |
14 | * data in hexadecimal or equivalent format, provided this copyright | |
15 | * notice is accompanying it. | |
1da177e4 LT |
16 | */ |
17 | ||
1da177e4 LT |
18 | |
19 | #include <linux/module.h> | |
20 | #include <linux/moduleparam.h> | |
6867c843 | 21 | #include <linux/stringify.h> |
1da177e4 LT |
22 | #include <linux/kernel.h> |
23 | #include <linux/types.h> | |
24 | #include <linux/compiler.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/delay.h> | |
14c85021 | 27 | #include <linux/in.h> |
1da177e4 | 28 | #include <linux/init.h> |
a6b7a407 | 29 | #include <linux/interrupt.h> |
1da177e4 LT |
30 | #include <linux/ioport.h> |
31 | #include <linux/pci.h> | |
32 | #include <linux/netdevice.h> | |
33 | #include <linux/etherdevice.h> | |
34 | #include <linux/skbuff.h> | |
35 | #include <linux/ethtool.h> | |
3110f5f5 | 36 | #include <linux/mdio.h> |
1da177e4 | 37 | #include <linux/mii.h> |
158d7abd | 38 | #include <linux/phy.h> |
a9daf367 | 39 | #include <linux/brcmphy.h> |
1da177e4 LT |
40 | #include <linux/if_vlan.h> |
41 | #include <linux/ip.h> | |
42 | #include <linux/tcp.h> | |
43 | #include <linux/workqueue.h> | |
61487480 | 44 | #include <linux/prefetch.h> |
f9a5f7d3 | 45 | #include <linux/dma-mapping.h> |
077f849d | 46 | #include <linux/firmware.h> |
1da177e4 LT |
47 | |
48 | #include <net/checksum.h> | |
c9bdd4b5 | 49 | #include <net/ip.h> |
1da177e4 LT |
50 | |
51 | #include <asm/system.h> | |
27fd9de8 | 52 | #include <linux/io.h> |
1da177e4 | 53 | #include <asm/byteorder.h> |
27fd9de8 | 54 | #include <linux/uaccess.h> |
1da177e4 | 55 | |
49b6e95f | 56 | #ifdef CONFIG_SPARC |
1da177e4 | 57 | #include <asm/idprom.h> |
49b6e95f | 58 | #include <asm/prom.h> |
1da177e4 LT |
59 | #endif |
60 | ||
63532394 MC |
61 | #define BAR_0 0 |
62 | #define BAR_2 2 | |
63 | ||
1da177e4 LT |
64 | #include "tg3.h" |
65 | ||
63c3a66f JP |
66 | /* Functions & macros to verify TG3_FLAGS types */ |
67 | ||
68 | static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits) | |
69 | { | |
70 | return test_bit(flag, bits); | |
71 | } | |
72 | ||
73 | static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits) | |
74 | { | |
75 | set_bit(flag, bits); | |
76 | } | |
77 | ||
78 | static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits) | |
79 | { | |
80 | clear_bit(flag, bits); | |
81 | } | |
82 | ||
83 | #define tg3_flag(tp, flag) \ | |
84 | _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags) | |
85 | #define tg3_flag_set(tp, flag) \ | |
86 | _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags) | |
87 | #define tg3_flag_clear(tp, flag) \ | |
88 | _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags) | |
89 | ||
1da177e4 | 90 | #define DRV_MODULE_NAME "tg3" |
6867c843 | 91 | #define TG3_MAJ_NUM 3 |
43a5f002 | 92 | #define TG3_MIN_NUM 119 |
6867c843 MC |
93 | #define DRV_MODULE_VERSION \ |
94 | __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM) | |
43a5f002 | 95 | #define DRV_MODULE_RELDATE "May 18, 2011" |
1da177e4 LT |
96 | |
97 | #define TG3_DEF_MAC_MODE 0 | |
98 | #define TG3_DEF_RX_MODE 0 | |
99 | #define TG3_DEF_TX_MODE 0 | |
100 | #define TG3_DEF_MSG_ENABLE \ | |
101 | (NETIF_MSG_DRV | \ | |
102 | NETIF_MSG_PROBE | \ | |
103 | NETIF_MSG_LINK | \ | |
104 | NETIF_MSG_TIMER | \ | |
105 | NETIF_MSG_IFDOWN | \ | |
106 | NETIF_MSG_IFUP | \ | |
107 | NETIF_MSG_RX_ERR | \ | |
108 | NETIF_MSG_TX_ERR) | |
109 | ||
520b2756 MC |
110 | #define TG3_GRC_LCLCTL_PWRSW_DELAY 100 |
111 | ||
1da177e4 LT |
112 | /* length of time before we decide the hardware is borked, |
113 | * and dev->tx_timeout() should be called to fix the problem | |
114 | */ | |
63c3a66f | 115 | |
1da177e4 LT |
116 | #define TG3_TX_TIMEOUT (5 * HZ) |
117 | ||
118 | /* hardware minimum and maximum for a single frame's data payload */ | |
119 | #define TG3_MIN_MTU 60 | |
120 | #define TG3_MAX_MTU(tp) \ | |
63c3a66f | 121 | (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500) |
1da177e4 LT |
122 | |
123 | /* These numbers seem to be hard coded in the NIC firmware somehow. | |
124 | * You can't change the ring sizes, but you can change where you place | |
125 | * them in the NIC onboard memory. | |
126 | */ | |
7cb32cf2 | 127 | #define TG3_RX_STD_RING_SIZE(tp) \ |
63c3a66f | 128 | (tg3_flag(tp, LRG_PROD_RING_CAP) ? \ |
de9f5230 | 129 | TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700) |
1da177e4 | 130 | #define TG3_DEF_RX_RING_PENDING 200 |
7cb32cf2 | 131 | #define TG3_RX_JMB_RING_SIZE(tp) \ |
63c3a66f | 132 | (tg3_flag(tp, LRG_PROD_RING_CAP) ? \ |
de9f5230 | 133 | TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700) |
1da177e4 | 134 | #define TG3_DEF_RX_JUMBO_RING_PENDING 100 |
c6cdf436 | 135 | #define TG3_RSS_INDIR_TBL_SIZE 128 |
1da177e4 LT |
136 | |
137 | /* Do not place this n-ring entries value into the tp struct itself, | |
138 | * we really want to expose these constants to GCC so that modulo et | |
139 | * al. operations are done with shifts and masks instead of with | |
140 | * hw multiply/modulo instructions. Another solution would be to | |
141 | * replace things like '% foo' with '& (foo - 1)'. | |
142 | */ | |
1da177e4 LT |
143 | |
144 | #define TG3_TX_RING_SIZE 512 | |
145 | #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1) | |
146 | ||
2c49a44d MC |
147 | #define TG3_RX_STD_RING_BYTES(tp) \ |
148 | (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp)) | |
149 | #define TG3_RX_JMB_RING_BYTES(tp) \ | |
150 | (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp)) | |
151 | #define TG3_RX_RCB_RING_BYTES(tp) \ | |
7cb32cf2 | 152 | (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1)) |
1da177e4 LT |
153 | #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \ |
154 | TG3_TX_RING_SIZE) | |
1da177e4 LT |
155 | #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1)) |
156 | ||
287be12e MC |
157 | #define TG3_DMA_BYTE_ENAB 64 |
158 | ||
159 | #define TG3_RX_STD_DMA_SZ 1536 | |
160 | #define TG3_RX_JMB_DMA_SZ 9046 | |
161 | ||
162 | #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB) | |
163 | ||
164 | #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ) | |
165 | #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ) | |
1da177e4 | 166 | |
2c49a44d MC |
167 | #define TG3_RX_STD_BUFF_RING_SIZE(tp) \ |
168 | (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp)) | |
2b2cdb65 | 169 | |
2c49a44d MC |
170 | #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \ |
171 | (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp)) | |
2b2cdb65 | 172 | |
d2757fc4 MC |
173 | /* Due to a hardware bug, the 5701 can only DMA to memory addresses |
174 | * that are at least dword aligned when used in PCIX mode. The driver | |
175 | * works around this bug by double copying the packet. This workaround | |
176 | * is built into the normal double copy length check for efficiency. | |
177 | * | |
178 | * However, the double copy is only necessary on those architectures | |
179 | * where unaligned memory accesses are inefficient. For those architectures | |
180 | * where unaligned memory accesses incur little penalty, we can reintegrate | |
181 | * the 5701 in the normal rx path. Doing so saves a device structure | |
182 | * dereference by hardcoding the double copy threshold in place. | |
183 | */ | |
184 | #define TG3_RX_COPY_THRESHOLD 256 | |
185 | #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS) | |
186 | #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD | |
187 | #else | |
188 | #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh) | |
189 | #endif | |
190 | ||
1da177e4 | 191 | /* minimum number of free TX descriptors required to wake up TX process */ |
f3f3f27e | 192 | #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4) |
1da177e4 | 193 | |
ad829268 MC |
194 | #define TG3_RAW_IP_ALIGN 2 |
195 | ||
c6cdf436 MC |
196 | #define TG3_FW_UPDATE_TIMEOUT_SEC 5 |
197 | ||
077f849d JSR |
198 | #define FIRMWARE_TG3 "tigon/tg3.bin" |
199 | #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin" | |
200 | #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin" | |
201 | ||
1da177e4 | 202 | static char version[] __devinitdata = |
05dbe005 | 203 | DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")"; |
1da177e4 LT |
204 | |
205 | MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)"); | |
206 | MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver"); | |
207 | MODULE_LICENSE("GPL"); | |
208 | MODULE_VERSION(DRV_MODULE_VERSION); | |
077f849d JSR |
209 | MODULE_FIRMWARE(FIRMWARE_TG3); |
210 | MODULE_FIRMWARE(FIRMWARE_TG3TSO); | |
211 | MODULE_FIRMWARE(FIRMWARE_TG3TSO5); | |
212 | ||
1da177e4 LT |
213 | static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */ |
214 | module_param(tg3_debug, int, 0); | |
215 | MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value"); | |
216 | ||
a3aa1884 | 217 | static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = { |
13185217 HK |
218 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)}, |
219 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)}, | |
220 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)}, | |
221 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)}, | |
222 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)}, | |
223 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)}, | |
224 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)}, | |
225 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)}, | |
226 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)}, | |
227 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)}, | |
228 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)}, | |
229 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)}, | |
230 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)}, | |
231 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)}, | |
232 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)}, | |
233 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)}, | |
234 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)}, | |
235 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)}, | |
236 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)}, | |
237 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)}, | |
238 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)}, | |
239 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)}, | |
13185217 | 240 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)}, |
126a3368 | 241 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)}, |
13185217 | 242 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)}, |
13185217 HK |
243 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)}, |
244 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)}, | |
245 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)}, | |
246 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)}, | |
247 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)}, | |
248 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)}, | |
249 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)}, | |
250 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)}, | |
251 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)}, | |
252 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)}, | |
253 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)}, | |
126a3368 | 254 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)}, |
13185217 HK |
255 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)}, |
256 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)}, | |
257 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)}, | |
676917d4 | 258 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)}, |
13185217 HK |
259 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)}, |
260 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)}, | |
261 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)}, | |
262 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)}, | |
263 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)}, | |
264 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)}, | |
265 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)}, | |
b5d3772c MC |
266 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)}, |
267 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)}, | |
d30cdd28 MC |
268 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)}, |
269 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)}, | |
6c7af27c | 270 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)}, |
9936bcf6 MC |
271 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)}, |
272 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)}, | |
c88e668b MC |
273 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)}, |
274 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)}, | |
2befdcea MC |
275 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)}, |
276 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)}, | |
321d32a0 MC |
277 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)}, |
278 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)}, | |
279 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)}, | |
5e7ccf20 | 280 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)}, |
5001e2f6 MC |
281 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)}, |
282 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)}, | |
b0f75221 MC |
283 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)}, |
284 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)}, | |
285 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)}, | |
286 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)}, | |
287 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)}, | |
288 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)}, | |
302b500b | 289 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)}, |
ba1f3c76 | 290 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)}, |
13185217 HK |
291 | {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)}, |
292 | {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)}, | |
293 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)}, | |
294 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)}, | |
295 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)}, | |
296 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)}, | |
297 | {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)}, | |
1dcb14d9 | 298 | {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */ |
13185217 | 299 | {} |
1da177e4 LT |
300 | }; |
301 | ||
302 | MODULE_DEVICE_TABLE(pci, tg3_pci_tbl); | |
303 | ||
50da859d | 304 | static const struct { |
1da177e4 | 305 | const char string[ETH_GSTRING_LEN]; |
48fa55a0 | 306 | } ethtool_stats_keys[] = { |
1da177e4 LT |
307 | { "rx_octets" }, |
308 | { "rx_fragments" }, | |
309 | { "rx_ucast_packets" }, | |
310 | { "rx_mcast_packets" }, | |
311 | { "rx_bcast_packets" }, | |
312 | { "rx_fcs_errors" }, | |
313 | { "rx_align_errors" }, | |
314 | { "rx_xon_pause_rcvd" }, | |
315 | { "rx_xoff_pause_rcvd" }, | |
316 | { "rx_mac_ctrl_rcvd" }, | |
317 | { "rx_xoff_entered" }, | |
318 | { "rx_frame_too_long_errors" }, | |
319 | { "rx_jabbers" }, | |
320 | { "rx_undersize_packets" }, | |
321 | { "rx_in_length_errors" }, | |
322 | { "rx_out_length_errors" }, | |
323 | { "rx_64_or_less_octet_packets" }, | |
324 | { "rx_65_to_127_octet_packets" }, | |
325 | { "rx_128_to_255_octet_packets" }, | |
326 | { "rx_256_to_511_octet_packets" }, | |
327 | { "rx_512_to_1023_octet_packets" }, | |
328 | { "rx_1024_to_1522_octet_packets" }, | |
329 | { "rx_1523_to_2047_octet_packets" }, | |
330 | { "rx_2048_to_4095_octet_packets" }, | |
331 | { "rx_4096_to_8191_octet_packets" }, | |
332 | { "rx_8192_to_9022_octet_packets" }, | |
333 | ||
334 | { "tx_octets" }, | |
335 | { "tx_collisions" }, | |
336 | ||
337 | { "tx_xon_sent" }, | |
338 | { "tx_xoff_sent" }, | |
339 | { "tx_flow_control" }, | |
340 | { "tx_mac_errors" }, | |
341 | { "tx_single_collisions" }, | |
342 | { "tx_mult_collisions" }, | |
343 | { "tx_deferred" }, | |
344 | { "tx_excessive_collisions" }, | |
345 | { "tx_late_collisions" }, | |
346 | { "tx_collide_2times" }, | |
347 | { "tx_collide_3times" }, | |
348 | { "tx_collide_4times" }, | |
349 | { "tx_collide_5times" }, | |
350 | { "tx_collide_6times" }, | |
351 | { "tx_collide_7times" }, | |
352 | { "tx_collide_8times" }, | |
353 | { "tx_collide_9times" }, | |
354 | { "tx_collide_10times" }, | |
355 | { "tx_collide_11times" }, | |
356 | { "tx_collide_12times" }, | |
357 | { "tx_collide_13times" }, | |
358 | { "tx_collide_14times" }, | |
359 | { "tx_collide_15times" }, | |
360 | { "tx_ucast_packets" }, | |
361 | { "tx_mcast_packets" }, | |
362 | { "tx_bcast_packets" }, | |
363 | { "tx_carrier_sense_errors" }, | |
364 | { "tx_discards" }, | |
365 | { "tx_errors" }, | |
366 | ||
367 | { "dma_writeq_full" }, | |
368 | { "dma_write_prioq_full" }, | |
369 | { "rxbds_empty" }, | |
370 | { "rx_discards" }, | |
371 | { "rx_errors" }, | |
372 | { "rx_threshold_hit" }, | |
373 | ||
374 | { "dma_readq_full" }, | |
375 | { "dma_read_prioq_full" }, | |
376 | { "tx_comp_queue_full" }, | |
377 | ||
378 | { "ring_set_send_prod_index" }, | |
379 | { "ring_status_update" }, | |
380 | { "nic_irqs" }, | |
381 | { "nic_avoided_irqs" }, | |
4452d099 MC |
382 | { "nic_tx_threshold_hit" }, |
383 | ||
384 | { "mbuf_lwm_thresh_hit" }, | |
1da177e4 LT |
385 | }; |
386 | ||
48fa55a0 MC |
387 | #define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys) |
388 | ||
389 | ||
50da859d | 390 | static const struct { |
4cafd3f5 | 391 | const char string[ETH_GSTRING_LEN]; |
48fa55a0 | 392 | } ethtool_test_keys[] = { |
4cafd3f5 MC |
393 | { "nvram test (online) " }, |
394 | { "link test (online) " }, | |
395 | { "register test (offline)" }, | |
396 | { "memory test (offline)" }, | |
397 | { "loopback test (offline)" }, | |
398 | { "interrupt test (offline)" }, | |
399 | }; | |
400 | ||
48fa55a0 MC |
401 | #define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys) |
402 | ||
403 | ||
b401e9e2 MC |
404 | static void tg3_write32(struct tg3 *tp, u32 off, u32 val) |
405 | { | |
406 | writel(val, tp->regs + off); | |
407 | } | |
408 | ||
409 | static u32 tg3_read32(struct tg3 *tp, u32 off) | |
410 | { | |
de6f31eb | 411 | return readl(tp->regs + off); |
b401e9e2 MC |
412 | } |
413 | ||
0d3031d9 MC |
414 | static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val) |
415 | { | |
416 | writel(val, tp->aperegs + off); | |
417 | } | |
418 | ||
419 | static u32 tg3_ape_read32(struct tg3 *tp, u32 off) | |
420 | { | |
de6f31eb | 421 | return readl(tp->aperegs + off); |
0d3031d9 MC |
422 | } |
423 | ||
1da177e4 LT |
424 | static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val) |
425 | { | |
6892914f MC |
426 | unsigned long flags; |
427 | ||
428 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
1ee582d8 MC |
429 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); |
430 | pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); | |
6892914f | 431 | spin_unlock_irqrestore(&tp->indirect_lock, flags); |
1ee582d8 MC |
432 | } |
433 | ||
434 | static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val) | |
435 | { | |
436 | writel(val, tp->regs + off); | |
437 | readl(tp->regs + off); | |
1da177e4 LT |
438 | } |
439 | ||
6892914f | 440 | static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off) |
1da177e4 | 441 | { |
6892914f MC |
442 | unsigned long flags; |
443 | u32 val; | |
444 | ||
445 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
446 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); | |
447 | pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); | |
448 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
449 | return val; | |
450 | } | |
451 | ||
452 | static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val) | |
453 | { | |
454 | unsigned long flags; | |
455 | ||
456 | if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) { | |
457 | pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX + | |
458 | TG3_64BIT_REG_LOW, val); | |
459 | return; | |
460 | } | |
66711e66 | 461 | if (off == TG3_RX_STD_PROD_IDX_REG) { |
6892914f MC |
462 | pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX + |
463 | TG3_64BIT_REG_LOW, val); | |
464 | return; | |
1da177e4 | 465 | } |
6892914f MC |
466 | |
467 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
468 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); | |
469 | pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); | |
470 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
471 | ||
472 | /* In indirect mode when disabling interrupts, we also need | |
473 | * to clear the interrupt bit in the GRC local ctrl register. | |
474 | */ | |
475 | if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) && | |
476 | (val == 0x1)) { | |
477 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL, | |
478 | tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT); | |
479 | } | |
480 | } | |
481 | ||
482 | static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off) | |
483 | { | |
484 | unsigned long flags; | |
485 | u32 val; | |
486 | ||
487 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
488 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); | |
489 | pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); | |
490 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
491 | return val; | |
492 | } | |
493 | ||
b401e9e2 MC |
494 | /* usec_wait specifies the wait time in usec when writing to certain registers |
495 | * where it is unsafe to read back the register without some delay. | |
496 | * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power. | |
497 | * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed. | |
498 | */ | |
499 | static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait) | |
6892914f | 500 | { |
63c3a66f | 501 | if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND)) |
b401e9e2 MC |
502 | /* Non-posted methods */ |
503 | tp->write32(tp, off, val); | |
504 | else { | |
505 | /* Posted method */ | |
506 | tg3_write32(tp, off, val); | |
507 | if (usec_wait) | |
508 | udelay(usec_wait); | |
509 | tp->read32(tp, off); | |
510 | } | |
511 | /* Wait again after the read for the posted method to guarantee that | |
512 | * the wait time is met. | |
513 | */ | |
514 | if (usec_wait) | |
515 | udelay(usec_wait); | |
1da177e4 LT |
516 | } |
517 | ||
09ee929c MC |
518 | static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val) |
519 | { | |
520 | tp->write32_mbox(tp, off, val); | |
63c3a66f | 521 | if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND)) |
6892914f | 522 | tp->read32_mbox(tp, off); |
09ee929c MC |
523 | } |
524 | ||
20094930 | 525 | static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val) |
1da177e4 LT |
526 | { |
527 | void __iomem *mbox = tp->regs + off; | |
528 | writel(val, mbox); | |
63c3a66f | 529 | if (tg3_flag(tp, TXD_MBOX_HWBUG)) |
1da177e4 | 530 | writel(val, mbox); |
63c3a66f | 531 | if (tg3_flag(tp, MBOX_WRITE_REORDER)) |
1da177e4 LT |
532 | readl(mbox); |
533 | } | |
534 | ||
b5d3772c MC |
535 | static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off) |
536 | { | |
de6f31eb | 537 | return readl(tp->regs + off + GRCMBOX_BASE); |
b5d3772c MC |
538 | } |
539 | ||
540 | static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val) | |
541 | { | |
542 | writel(val, tp->regs + off + GRCMBOX_BASE); | |
543 | } | |
544 | ||
c6cdf436 | 545 | #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val) |
09ee929c | 546 | #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val)) |
c6cdf436 MC |
547 | #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val) |
548 | #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val) | |
549 | #define tr32_mailbox(reg) tp->read32_mbox(tp, reg) | |
20094930 | 550 | |
c6cdf436 MC |
551 | #define tw32(reg, val) tp->write32(tp, reg, val) |
552 | #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0) | |
553 | #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us)) | |
554 | #define tr32(reg) tp->read32(tp, reg) | |
1da177e4 LT |
555 | |
556 | static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val) | |
557 | { | |
6892914f MC |
558 | unsigned long flags; |
559 | ||
6ff6f81d | 560 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 && |
b5d3772c MC |
561 | (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) |
562 | return; | |
563 | ||
6892914f | 564 | spin_lock_irqsave(&tp->indirect_lock, flags); |
63c3a66f | 565 | if (tg3_flag(tp, SRAM_USE_CONFIG)) { |
bbadf503 MC |
566 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); |
567 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
1da177e4 | 568 | |
bbadf503 MC |
569 | /* Always leave this as zero. */ |
570 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
571 | } else { | |
572 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off); | |
573 | tw32_f(TG3PCI_MEM_WIN_DATA, val); | |
28fbef78 | 574 | |
bbadf503 MC |
575 | /* Always leave this as zero. */ |
576 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
577 | } | |
578 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
758a6139 DM |
579 | } |
580 | ||
1da177e4 LT |
581 | static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val) |
582 | { | |
6892914f MC |
583 | unsigned long flags; |
584 | ||
6ff6f81d | 585 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 && |
b5d3772c MC |
586 | (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) { |
587 | *val = 0; | |
588 | return; | |
589 | } | |
590 | ||
6892914f | 591 | spin_lock_irqsave(&tp->indirect_lock, flags); |
63c3a66f | 592 | if (tg3_flag(tp, SRAM_USE_CONFIG)) { |
bbadf503 MC |
593 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); |
594 | pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
1da177e4 | 595 | |
bbadf503 MC |
596 | /* Always leave this as zero. */ |
597 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
598 | } else { | |
599 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off); | |
600 | *val = tr32(TG3PCI_MEM_WIN_DATA); | |
601 | ||
602 | /* Always leave this as zero. */ | |
603 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
604 | } | |
6892914f | 605 | spin_unlock_irqrestore(&tp->indirect_lock, flags); |
1da177e4 LT |
606 | } |
607 | ||
0d3031d9 MC |
608 | static void tg3_ape_lock_init(struct tg3 *tp) |
609 | { | |
610 | int i; | |
6f5c8f83 | 611 | u32 regbase, bit; |
f92d9dc1 MC |
612 | |
613 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | |
614 | regbase = TG3_APE_LOCK_GRANT; | |
615 | else | |
616 | regbase = TG3_APE_PER_LOCK_GRANT; | |
0d3031d9 MC |
617 | |
618 | /* Make sure the driver hasn't any stale locks. */ | |
6f5c8f83 MC |
619 | for (i = 0; i < 8; i++) { |
620 | if (i == TG3_APE_LOCK_GPIO) | |
621 | continue; | |
f92d9dc1 | 622 | tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER); |
6f5c8f83 MC |
623 | } |
624 | ||
625 | /* Clear the correct bit of the GPIO lock too. */ | |
626 | if (!tp->pci_fn) | |
627 | bit = APE_LOCK_GRANT_DRIVER; | |
628 | else | |
629 | bit = 1 << tp->pci_fn; | |
630 | ||
631 | tg3_ape_write32(tp, regbase + 4 * TG3_APE_LOCK_GPIO, bit); | |
0d3031d9 MC |
632 | } |
633 | ||
634 | static int tg3_ape_lock(struct tg3 *tp, int locknum) | |
635 | { | |
636 | int i, off; | |
637 | int ret = 0; | |
6f5c8f83 | 638 | u32 status, req, gnt, bit; |
0d3031d9 | 639 | |
63c3a66f | 640 | if (!tg3_flag(tp, ENABLE_APE)) |
0d3031d9 MC |
641 | return 0; |
642 | ||
643 | switch (locknum) { | |
6f5c8f83 MC |
644 | case TG3_APE_LOCK_GPIO: |
645 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | |
646 | return 0; | |
33f401ae MC |
647 | case TG3_APE_LOCK_GRC: |
648 | case TG3_APE_LOCK_MEM: | |
649 | break; | |
650 | default: | |
651 | return -EINVAL; | |
0d3031d9 MC |
652 | } |
653 | ||
f92d9dc1 MC |
654 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) { |
655 | req = TG3_APE_LOCK_REQ; | |
656 | gnt = TG3_APE_LOCK_GRANT; | |
657 | } else { | |
658 | req = TG3_APE_PER_LOCK_REQ; | |
659 | gnt = TG3_APE_PER_LOCK_GRANT; | |
660 | } | |
661 | ||
0d3031d9 MC |
662 | off = 4 * locknum; |
663 | ||
6f5c8f83 MC |
664 | if (locknum != TG3_APE_LOCK_GPIO || !tp->pci_fn) |
665 | bit = APE_LOCK_REQ_DRIVER; | |
666 | else | |
667 | bit = 1 << tp->pci_fn; | |
668 | ||
669 | tg3_ape_write32(tp, req + off, bit); | |
0d3031d9 MC |
670 | |
671 | /* Wait for up to 1 millisecond to acquire lock. */ | |
672 | for (i = 0; i < 100; i++) { | |
f92d9dc1 | 673 | status = tg3_ape_read32(tp, gnt + off); |
6f5c8f83 | 674 | if (status == bit) |
0d3031d9 MC |
675 | break; |
676 | udelay(10); | |
677 | } | |
678 | ||
6f5c8f83 | 679 | if (status != bit) { |
0d3031d9 | 680 | /* Revoke the lock request. */ |
6f5c8f83 | 681 | tg3_ape_write32(tp, gnt + off, bit); |
0d3031d9 MC |
682 | ret = -EBUSY; |
683 | } | |
684 | ||
685 | return ret; | |
686 | } | |
687 | ||
688 | static void tg3_ape_unlock(struct tg3 *tp, int locknum) | |
689 | { | |
6f5c8f83 | 690 | u32 gnt, bit; |
0d3031d9 | 691 | |
63c3a66f | 692 | if (!tg3_flag(tp, ENABLE_APE)) |
0d3031d9 MC |
693 | return; |
694 | ||
695 | switch (locknum) { | |
6f5c8f83 MC |
696 | case TG3_APE_LOCK_GPIO: |
697 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | |
698 | return; | |
33f401ae MC |
699 | case TG3_APE_LOCK_GRC: |
700 | case TG3_APE_LOCK_MEM: | |
701 | break; | |
702 | default: | |
703 | return; | |
0d3031d9 MC |
704 | } |
705 | ||
f92d9dc1 MC |
706 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) |
707 | gnt = TG3_APE_LOCK_GRANT; | |
708 | else | |
709 | gnt = TG3_APE_PER_LOCK_GRANT; | |
710 | ||
6f5c8f83 MC |
711 | if (locknum != TG3_APE_LOCK_GPIO || !tp->pci_fn) |
712 | bit = APE_LOCK_GRANT_DRIVER; | |
713 | else | |
714 | bit = 1 << tp->pci_fn; | |
715 | ||
716 | tg3_ape_write32(tp, gnt + 4 * locknum, bit); | |
0d3031d9 MC |
717 | } |
718 | ||
1da177e4 LT |
719 | static void tg3_disable_ints(struct tg3 *tp) |
720 | { | |
89aeb3bc MC |
721 | int i; |
722 | ||
1da177e4 LT |
723 | tw32(TG3PCI_MISC_HOST_CTRL, |
724 | (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT)); | |
89aeb3bc MC |
725 | for (i = 0; i < tp->irq_max; i++) |
726 | tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001); | |
1da177e4 LT |
727 | } |
728 | ||
1da177e4 LT |
729 | static void tg3_enable_ints(struct tg3 *tp) |
730 | { | |
89aeb3bc | 731 | int i; |
89aeb3bc | 732 | |
bbe832c0 MC |
733 | tp->irq_sync = 0; |
734 | wmb(); | |
735 | ||
1da177e4 LT |
736 | tw32(TG3PCI_MISC_HOST_CTRL, |
737 | (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT)); | |
89aeb3bc | 738 | |
f89f38b8 | 739 | tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE; |
89aeb3bc MC |
740 | for (i = 0; i < tp->irq_cnt; i++) { |
741 | struct tg3_napi *tnapi = &tp->napi[i]; | |
c6cdf436 | 742 | |
898a56f8 | 743 | tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); |
63c3a66f | 744 | if (tg3_flag(tp, 1SHOT_MSI)) |
89aeb3bc | 745 | tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); |
f19af9c2 | 746 | |
f89f38b8 | 747 | tp->coal_now |= tnapi->coal_now; |
89aeb3bc | 748 | } |
f19af9c2 MC |
749 | |
750 | /* Force an initial interrupt */ | |
63c3a66f | 751 | if (!tg3_flag(tp, TAGGED_STATUS) && |
f19af9c2 MC |
752 | (tp->napi[0].hw_status->status & SD_STATUS_UPDATED)) |
753 | tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); | |
754 | else | |
f89f38b8 MC |
755 | tw32(HOSTCC_MODE, tp->coal_now); |
756 | ||
757 | tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now); | |
1da177e4 LT |
758 | } |
759 | ||
17375d25 | 760 | static inline unsigned int tg3_has_work(struct tg3_napi *tnapi) |
04237ddd | 761 | { |
17375d25 | 762 | struct tg3 *tp = tnapi->tp; |
898a56f8 | 763 | struct tg3_hw_status *sblk = tnapi->hw_status; |
04237ddd MC |
764 | unsigned int work_exists = 0; |
765 | ||
766 | /* check for phy events */ | |
63c3a66f | 767 | if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) { |
04237ddd MC |
768 | if (sblk->status & SD_STATUS_LINK_CHG) |
769 | work_exists = 1; | |
770 | } | |
771 | /* check for RX/TX work to do */ | |
f3f3f27e | 772 | if (sblk->idx[0].tx_consumer != tnapi->tx_cons || |
8d9d7cfc | 773 | *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr) |
04237ddd MC |
774 | work_exists = 1; |
775 | ||
776 | return work_exists; | |
777 | } | |
778 | ||
17375d25 | 779 | /* tg3_int_reenable |
04237ddd MC |
780 | * similar to tg3_enable_ints, but it accurately determines whether there |
781 | * is new work pending and can return without flushing the PIO write | |
6aa20a22 | 782 | * which reenables interrupts |
1da177e4 | 783 | */ |
17375d25 | 784 | static void tg3_int_reenable(struct tg3_napi *tnapi) |
1da177e4 | 785 | { |
17375d25 MC |
786 | struct tg3 *tp = tnapi->tp; |
787 | ||
898a56f8 | 788 | tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); |
1da177e4 LT |
789 | mmiowb(); |
790 | ||
fac9b83e DM |
791 | /* When doing tagged status, this work check is unnecessary. |
792 | * The last_tag we write above tells the chip which piece of | |
793 | * work we've completed. | |
794 | */ | |
63c3a66f | 795 | if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi)) |
04237ddd | 796 | tw32(HOSTCC_MODE, tp->coalesce_mode | |
fd2ce37f | 797 | HOSTCC_MODE_ENABLE | tnapi->coal_now); |
1da177e4 LT |
798 | } |
799 | ||
1da177e4 LT |
800 | static void tg3_switch_clocks(struct tg3 *tp) |
801 | { | |
f6eb9b1f | 802 | u32 clock_ctrl; |
1da177e4 LT |
803 | u32 orig_clock_ctrl; |
804 | ||
63c3a66f | 805 | if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS)) |
4cf78e4f MC |
806 | return; |
807 | ||
f6eb9b1f MC |
808 | clock_ctrl = tr32(TG3PCI_CLOCK_CTRL); |
809 | ||
1da177e4 LT |
810 | orig_clock_ctrl = clock_ctrl; |
811 | clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN | | |
812 | CLOCK_CTRL_CLKRUN_OENABLE | | |
813 | 0x1f); | |
814 | tp->pci_clock_ctrl = clock_ctrl; | |
815 | ||
63c3a66f | 816 | if (tg3_flag(tp, 5705_PLUS)) { |
1da177e4 | 817 | if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) { |
b401e9e2 MC |
818 | tw32_wait_f(TG3PCI_CLOCK_CTRL, |
819 | clock_ctrl | CLOCK_CTRL_625_CORE, 40); | |
1da177e4 LT |
820 | } |
821 | } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) { | |
b401e9e2 MC |
822 | tw32_wait_f(TG3PCI_CLOCK_CTRL, |
823 | clock_ctrl | | |
824 | (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK), | |
825 | 40); | |
826 | tw32_wait_f(TG3PCI_CLOCK_CTRL, | |
827 | clock_ctrl | (CLOCK_CTRL_ALTCLK), | |
828 | 40); | |
1da177e4 | 829 | } |
b401e9e2 | 830 | tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40); |
1da177e4 LT |
831 | } |
832 | ||
833 | #define PHY_BUSY_LOOPS 5000 | |
834 | ||
835 | static int tg3_readphy(struct tg3 *tp, int reg, u32 *val) | |
836 | { | |
837 | u32 frame_val; | |
838 | unsigned int loops; | |
839 | int ret; | |
840 | ||
841 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
842 | tw32_f(MAC_MI_MODE, | |
843 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
844 | udelay(80); | |
845 | } | |
846 | ||
847 | *val = 0x0; | |
848 | ||
882e9793 | 849 | frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) & |
1da177e4 LT |
850 | MI_COM_PHY_ADDR_MASK); |
851 | frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & | |
852 | MI_COM_REG_ADDR_MASK); | |
853 | frame_val |= (MI_COM_CMD_READ | MI_COM_START); | |
6aa20a22 | 854 | |
1da177e4 LT |
855 | tw32_f(MAC_MI_COM, frame_val); |
856 | ||
857 | loops = PHY_BUSY_LOOPS; | |
858 | while (loops != 0) { | |
859 | udelay(10); | |
860 | frame_val = tr32(MAC_MI_COM); | |
861 | ||
862 | if ((frame_val & MI_COM_BUSY) == 0) { | |
863 | udelay(5); | |
864 | frame_val = tr32(MAC_MI_COM); | |
865 | break; | |
866 | } | |
867 | loops -= 1; | |
868 | } | |
869 | ||
870 | ret = -EBUSY; | |
871 | if (loops != 0) { | |
872 | *val = frame_val & MI_COM_DATA_MASK; | |
873 | ret = 0; | |
874 | } | |
875 | ||
876 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
877 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
878 | udelay(80); | |
879 | } | |
880 | ||
881 | return ret; | |
882 | } | |
883 | ||
884 | static int tg3_writephy(struct tg3 *tp, int reg, u32 val) | |
885 | { | |
886 | u32 frame_val; | |
887 | unsigned int loops; | |
888 | int ret; | |
889 | ||
f07e9af3 | 890 | if ((tp->phy_flags & TG3_PHYFLG_IS_FET) && |
221c5637 | 891 | (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL)) |
b5d3772c MC |
892 | return 0; |
893 | ||
1da177e4 LT |
894 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { |
895 | tw32_f(MAC_MI_MODE, | |
896 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
897 | udelay(80); | |
898 | } | |
899 | ||
882e9793 | 900 | frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) & |
1da177e4 LT |
901 | MI_COM_PHY_ADDR_MASK); |
902 | frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & | |
903 | MI_COM_REG_ADDR_MASK); | |
904 | frame_val |= (val & MI_COM_DATA_MASK); | |
905 | frame_val |= (MI_COM_CMD_WRITE | MI_COM_START); | |
6aa20a22 | 906 | |
1da177e4 LT |
907 | tw32_f(MAC_MI_COM, frame_val); |
908 | ||
909 | loops = PHY_BUSY_LOOPS; | |
910 | while (loops != 0) { | |
911 | udelay(10); | |
912 | frame_val = tr32(MAC_MI_COM); | |
913 | if ((frame_val & MI_COM_BUSY) == 0) { | |
914 | udelay(5); | |
915 | frame_val = tr32(MAC_MI_COM); | |
916 | break; | |
917 | } | |
918 | loops -= 1; | |
919 | } | |
920 | ||
921 | ret = -EBUSY; | |
922 | if (loops != 0) | |
923 | ret = 0; | |
924 | ||
925 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
926 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
927 | udelay(80); | |
928 | } | |
929 | ||
930 | return ret; | |
931 | } | |
932 | ||
b0988c15 MC |
933 | static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val) |
934 | { | |
935 | int err; | |
936 | ||
937 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad); | |
938 | if (err) | |
939 | goto done; | |
940 | ||
941 | err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr); | |
942 | if (err) | |
943 | goto done; | |
944 | ||
945 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, | |
946 | MII_TG3_MMD_CTRL_DATA_NOINC | devad); | |
947 | if (err) | |
948 | goto done; | |
949 | ||
950 | err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val); | |
951 | ||
952 | done: | |
953 | return err; | |
954 | } | |
955 | ||
956 | static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val) | |
957 | { | |
958 | int err; | |
959 | ||
960 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad); | |
961 | if (err) | |
962 | goto done; | |
963 | ||
964 | err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr); | |
965 | if (err) | |
966 | goto done; | |
967 | ||
968 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, | |
969 | MII_TG3_MMD_CTRL_DATA_NOINC | devad); | |
970 | if (err) | |
971 | goto done; | |
972 | ||
973 | err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val); | |
974 | ||
975 | done: | |
976 | return err; | |
977 | } | |
978 | ||
979 | static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val) | |
980 | { | |
981 | int err; | |
982 | ||
983 | err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); | |
984 | if (!err) | |
985 | err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val); | |
986 | ||
987 | return err; | |
988 | } | |
989 | ||
990 | static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val) | |
991 | { | |
992 | int err; | |
993 | ||
994 | err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); | |
995 | if (!err) | |
996 | err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val); | |
997 | ||
998 | return err; | |
999 | } | |
1000 | ||
15ee95c3 MC |
1001 | static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val) |
1002 | { | |
1003 | int err; | |
1004 | ||
1005 | err = tg3_writephy(tp, MII_TG3_AUX_CTRL, | |
1006 | (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) | | |
1007 | MII_TG3_AUXCTL_SHDWSEL_MISC); | |
1008 | if (!err) | |
1009 | err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val); | |
1010 | ||
1011 | return err; | |
1012 | } | |
1013 | ||
b4bd2929 MC |
1014 | static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set) |
1015 | { | |
1016 | if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC) | |
1017 | set |= MII_TG3_AUXCTL_MISC_WREN; | |
1018 | ||
1019 | return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg); | |
1020 | } | |
1021 | ||
1d36ba45 MC |
1022 | #define TG3_PHY_AUXCTL_SMDSP_ENABLE(tp) \ |
1023 | tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \ | |
1024 | MII_TG3_AUXCTL_ACTL_SMDSP_ENA | \ | |
1025 | MII_TG3_AUXCTL_ACTL_TX_6DB) | |
1026 | ||
1027 | #define TG3_PHY_AUXCTL_SMDSP_DISABLE(tp) \ | |
1028 | tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \ | |
1029 | MII_TG3_AUXCTL_ACTL_TX_6DB); | |
1030 | ||
95e2869a MC |
1031 | static int tg3_bmcr_reset(struct tg3 *tp) |
1032 | { | |
1033 | u32 phy_control; | |
1034 | int limit, err; | |
1035 | ||
1036 | /* OK, reset it, and poll the BMCR_RESET bit until it | |
1037 | * clears or we time out. | |
1038 | */ | |
1039 | phy_control = BMCR_RESET; | |
1040 | err = tg3_writephy(tp, MII_BMCR, phy_control); | |
1041 | if (err != 0) | |
1042 | return -EBUSY; | |
1043 | ||
1044 | limit = 5000; | |
1045 | while (limit--) { | |
1046 | err = tg3_readphy(tp, MII_BMCR, &phy_control); | |
1047 | if (err != 0) | |
1048 | return -EBUSY; | |
1049 | ||
1050 | if ((phy_control & BMCR_RESET) == 0) { | |
1051 | udelay(40); | |
1052 | break; | |
1053 | } | |
1054 | udelay(10); | |
1055 | } | |
d4675b52 | 1056 | if (limit < 0) |
95e2869a MC |
1057 | return -EBUSY; |
1058 | ||
1059 | return 0; | |
1060 | } | |
1061 | ||
158d7abd MC |
1062 | static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg) |
1063 | { | |
3d16543d | 1064 | struct tg3 *tp = bp->priv; |
158d7abd MC |
1065 | u32 val; |
1066 | ||
24bb4fb6 | 1067 | spin_lock_bh(&tp->lock); |
158d7abd MC |
1068 | |
1069 | if (tg3_readphy(tp, reg, &val)) | |
24bb4fb6 MC |
1070 | val = -EIO; |
1071 | ||
1072 | spin_unlock_bh(&tp->lock); | |
158d7abd MC |
1073 | |
1074 | return val; | |
1075 | } | |
1076 | ||
1077 | static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val) | |
1078 | { | |
3d16543d | 1079 | struct tg3 *tp = bp->priv; |
24bb4fb6 | 1080 | u32 ret = 0; |
158d7abd | 1081 | |
24bb4fb6 | 1082 | spin_lock_bh(&tp->lock); |
158d7abd MC |
1083 | |
1084 | if (tg3_writephy(tp, reg, val)) | |
24bb4fb6 | 1085 | ret = -EIO; |
158d7abd | 1086 | |
24bb4fb6 MC |
1087 | spin_unlock_bh(&tp->lock); |
1088 | ||
1089 | return ret; | |
158d7abd MC |
1090 | } |
1091 | ||
1092 | static int tg3_mdio_reset(struct mii_bus *bp) | |
1093 | { | |
1094 | return 0; | |
1095 | } | |
1096 | ||
9c61d6bc | 1097 | static void tg3_mdio_config_5785(struct tg3 *tp) |
a9daf367 MC |
1098 | { |
1099 | u32 val; | |
fcb389df | 1100 | struct phy_device *phydev; |
a9daf367 | 1101 | |
3f0e3ad7 | 1102 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
fcb389df | 1103 | switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { |
6a443a0f MC |
1104 | case PHY_ID_BCM50610: |
1105 | case PHY_ID_BCM50610M: | |
fcb389df MC |
1106 | val = MAC_PHYCFG2_50610_LED_MODES; |
1107 | break; | |
6a443a0f | 1108 | case PHY_ID_BCMAC131: |
fcb389df MC |
1109 | val = MAC_PHYCFG2_AC131_LED_MODES; |
1110 | break; | |
6a443a0f | 1111 | case PHY_ID_RTL8211C: |
fcb389df MC |
1112 | val = MAC_PHYCFG2_RTL8211C_LED_MODES; |
1113 | break; | |
6a443a0f | 1114 | case PHY_ID_RTL8201E: |
fcb389df MC |
1115 | val = MAC_PHYCFG2_RTL8201E_LED_MODES; |
1116 | break; | |
1117 | default: | |
a9daf367 | 1118 | return; |
fcb389df MC |
1119 | } |
1120 | ||
1121 | if (phydev->interface != PHY_INTERFACE_MODE_RGMII) { | |
1122 | tw32(MAC_PHYCFG2, val); | |
1123 | ||
1124 | val = tr32(MAC_PHYCFG1); | |
bb85fbb6 MC |
1125 | val &= ~(MAC_PHYCFG1_RGMII_INT | |
1126 | MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK); | |
1127 | val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT; | |
fcb389df MC |
1128 | tw32(MAC_PHYCFG1, val); |
1129 | ||
1130 | return; | |
1131 | } | |
1132 | ||
63c3a66f | 1133 | if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) |
fcb389df MC |
1134 | val |= MAC_PHYCFG2_EMODE_MASK_MASK | |
1135 | MAC_PHYCFG2_FMODE_MASK_MASK | | |
1136 | MAC_PHYCFG2_GMODE_MASK_MASK | | |
1137 | MAC_PHYCFG2_ACT_MASK_MASK | | |
1138 | MAC_PHYCFG2_QUAL_MASK_MASK | | |
1139 | MAC_PHYCFG2_INBAND_ENABLE; | |
1140 | ||
1141 | tw32(MAC_PHYCFG2, val); | |
a9daf367 | 1142 | |
bb85fbb6 MC |
1143 | val = tr32(MAC_PHYCFG1); |
1144 | val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK | | |
1145 | MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN); | |
63c3a66f JP |
1146 | if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) { |
1147 | if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN)) | |
a9daf367 | 1148 | val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC; |
63c3a66f | 1149 | if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN)) |
a9daf367 MC |
1150 | val |= MAC_PHYCFG1_RGMII_SND_STAT_EN; |
1151 | } | |
bb85fbb6 MC |
1152 | val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT | |
1153 | MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV; | |
1154 | tw32(MAC_PHYCFG1, val); | |
a9daf367 | 1155 | |
a9daf367 MC |
1156 | val = tr32(MAC_EXT_RGMII_MODE); |
1157 | val &= ~(MAC_RGMII_MODE_RX_INT_B | | |
1158 | MAC_RGMII_MODE_RX_QUALITY | | |
1159 | MAC_RGMII_MODE_RX_ACTIVITY | | |
1160 | MAC_RGMII_MODE_RX_ENG_DET | | |
1161 | MAC_RGMII_MODE_TX_ENABLE | | |
1162 | MAC_RGMII_MODE_TX_LOWPWR | | |
1163 | MAC_RGMII_MODE_TX_RESET); | |
63c3a66f JP |
1164 | if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) { |
1165 | if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN)) | |
a9daf367 MC |
1166 | val |= MAC_RGMII_MODE_RX_INT_B | |
1167 | MAC_RGMII_MODE_RX_QUALITY | | |
1168 | MAC_RGMII_MODE_RX_ACTIVITY | | |
1169 | MAC_RGMII_MODE_RX_ENG_DET; | |
63c3a66f | 1170 | if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN)) |
a9daf367 MC |
1171 | val |= MAC_RGMII_MODE_TX_ENABLE | |
1172 | MAC_RGMII_MODE_TX_LOWPWR | | |
1173 | MAC_RGMII_MODE_TX_RESET; | |
1174 | } | |
1175 | tw32(MAC_EXT_RGMII_MODE, val); | |
1176 | } | |
1177 | ||
158d7abd MC |
1178 | static void tg3_mdio_start(struct tg3 *tp) |
1179 | { | |
158d7abd MC |
1180 | tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL; |
1181 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
1182 | udelay(80); | |
a9daf367 | 1183 | |
63c3a66f | 1184 | if (tg3_flag(tp, MDIOBUS_INITED) && |
9ea4818d MC |
1185 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) |
1186 | tg3_mdio_config_5785(tp); | |
1187 | } | |
1188 | ||
1189 | static int tg3_mdio_init(struct tg3 *tp) | |
1190 | { | |
1191 | int i; | |
1192 | u32 reg; | |
1193 | struct phy_device *phydev; | |
1194 | ||
63c3a66f | 1195 | if (tg3_flag(tp, 5717_PLUS)) { |
9c7df915 | 1196 | u32 is_serdes; |
882e9793 | 1197 | |
69f11c99 | 1198 | tp->phy_addr = tp->pci_fn + 1; |
882e9793 | 1199 | |
d1ec96af MC |
1200 | if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) |
1201 | is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES; | |
1202 | else | |
1203 | is_serdes = tr32(TG3_CPMU_PHY_STRAP) & | |
1204 | TG3_CPMU_PHY_STRAP_IS_SERDES; | |
882e9793 MC |
1205 | if (is_serdes) |
1206 | tp->phy_addr += 7; | |
1207 | } else | |
3f0e3ad7 | 1208 | tp->phy_addr = TG3_PHY_MII_ADDR; |
882e9793 | 1209 | |
158d7abd MC |
1210 | tg3_mdio_start(tp); |
1211 | ||
63c3a66f | 1212 | if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED)) |
158d7abd MC |
1213 | return 0; |
1214 | ||
298cf9be LB |
1215 | tp->mdio_bus = mdiobus_alloc(); |
1216 | if (tp->mdio_bus == NULL) | |
1217 | return -ENOMEM; | |
158d7abd | 1218 | |
298cf9be LB |
1219 | tp->mdio_bus->name = "tg3 mdio bus"; |
1220 | snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x", | |
158d7abd | 1221 | (tp->pdev->bus->number << 8) | tp->pdev->devfn); |
298cf9be LB |
1222 | tp->mdio_bus->priv = tp; |
1223 | tp->mdio_bus->parent = &tp->pdev->dev; | |
1224 | tp->mdio_bus->read = &tg3_mdio_read; | |
1225 | tp->mdio_bus->write = &tg3_mdio_write; | |
1226 | tp->mdio_bus->reset = &tg3_mdio_reset; | |
3f0e3ad7 | 1227 | tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR); |
298cf9be | 1228 | tp->mdio_bus->irq = &tp->mdio_irq[0]; |
158d7abd MC |
1229 | |
1230 | for (i = 0; i < PHY_MAX_ADDR; i++) | |
298cf9be | 1231 | tp->mdio_bus->irq[i] = PHY_POLL; |
158d7abd MC |
1232 | |
1233 | /* The bus registration will look for all the PHYs on the mdio bus. | |
1234 | * Unfortunately, it does not ensure the PHY is powered up before | |
1235 | * accessing the PHY ID registers. A chip reset is the | |
1236 | * quickest way to bring the device back to an operational state.. | |
1237 | */ | |
1238 | if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN)) | |
1239 | tg3_bmcr_reset(tp); | |
1240 | ||
298cf9be | 1241 | i = mdiobus_register(tp->mdio_bus); |
a9daf367 | 1242 | if (i) { |
ab96b241 | 1243 | dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i); |
9c61d6bc | 1244 | mdiobus_free(tp->mdio_bus); |
a9daf367 MC |
1245 | return i; |
1246 | } | |
158d7abd | 1247 | |
3f0e3ad7 | 1248 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
a9daf367 | 1249 | |
9c61d6bc | 1250 | if (!phydev || !phydev->drv) { |
ab96b241 | 1251 | dev_warn(&tp->pdev->dev, "No PHY devices\n"); |
9c61d6bc MC |
1252 | mdiobus_unregister(tp->mdio_bus); |
1253 | mdiobus_free(tp->mdio_bus); | |
1254 | return -ENODEV; | |
1255 | } | |
1256 | ||
1257 | switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { | |
6a443a0f | 1258 | case PHY_ID_BCM57780: |
321d32a0 | 1259 | phydev->interface = PHY_INTERFACE_MODE_GMII; |
c704dc23 | 1260 | phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE; |
321d32a0 | 1261 | break; |
6a443a0f MC |
1262 | case PHY_ID_BCM50610: |
1263 | case PHY_ID_BCM50610M: | |
32e5a8d6 | 1264 | phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE | |
c704dc23 | 1265 | PHY_BRCM_RX_REFCLK_UNUSED | |
52fae083 | 1266 | PHY_BRCM_DIS_TXCRXC_NOENRGY | |
c704dc23 | 1267 | PHY_BRCM_AUTO_PWRDWN_ENABLE; |
63c3a66f | 1268 | if (tg3_flag(tp, RGMII_INBAND_DISABLE)) |
a9daf367 | 1269 | phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE; |
63c3a66f | 1270 | if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN)) |
a9daf367 | 1271 | phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE; |
63c3a66f | 1272 | if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN)) |
a9daf367 | 1273 | phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE; |
fcb389df | 1274 | /* fallthru */ |
6a443a0f | 1275 | case PHY_ID_RTL8211C: |
fcb389df | 1276 | phydev->interface = PHY_INTERFACE_MODE_RGMII; |
a9daf367 | 1277 | break; |
6a443a0f MC |
1278 | case PHY_ID_RTL8201E: |
1279 | case PHY_ID_BCMAC131: | |
a9daf367 | 1280 | phydev->interface = PHY_INTERFACE_MODE_MII; |
cdd4e09d | 1281 | phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE; |
f07e9af3 | 1282 | tp->phy_flags |= TG3_PHYFLG_IS_FET; |
a9daf367 MC |
1283 | break; |
1284 | } | |
1285 | ||
63c3a66f | 1286 | tg3_flag_set(tp, MDIOBUS_INITED); |
9c61d6bc MC |
1287 | |
1288 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
1289 | tg3_mdio_config_5785(tp); | |
a9daf367 MC |
1290 | |
1291 | return 0; | |
158d7abd MC |
1292 | } |
1293 | ||
1294 | static void tg3_mdio_fini(struct tg3 *tp) | |
1295 | { | |
63c3a66f JP |
1296 | if (tg3_flag(tp, MDIOBUS_INITED)) { |
1297 | tg3_flag_clear(tp, MDIOBUS_INITED); | |
298cf9be LB |
1298 | mdiobus_unregister(tp->mdio_bus); |
1299 | mdiobus_free(tp->mdio_bus); | |
158d7abd MC |
1300 | } |
1301 | } | |
1302 | ||
4ba526ce MC |
1303 | /* tp->lock is held. */ |
1304 | static inline void tg3_generate_fw_event(struct tg3 *tp) | |
1305 | { | |
1306 | u32 val; | |
1307 | ||
1308 | val = tr32(GRC_RX_CPU_EVENT); | |
1309 | val |= GRC_RX_CPU_DRIVER_EVENT; | |
1310 | tw32_f(GRC_RX_CPU_EVENT, val); | |
1311 | ||
1312 | tp->last_event_jiffies = jiffies; | |
1313 | } | |
1314 | ||
1315 | #define TG3_FW_EVENT_TIMEOUT_USEC 2500 | |
1316 | ||
95e2869a MC |
1317 | /* tp->lock is held. */ |
1318 | static void tg3_wait_for_event_ack(struct tg3 *tp) | |
1319 | { | |
1320 | int i; | |
4ba526ce MC |
1321 | unsigned int delay_cnt; |
1322 | long time_remain; | |
1323 | ||
1324 | /* If enough time has passed, no wait is necessary. */ | |
1325 | time_remain = (long)(tp->last_event_jiffies + 1 + | |
1326 | usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) - | |
1327 | (long)jiffies; | |
1328 | if (time_remain < 0) | |
1329 | return; | |
1330 | ||
1331 | /* Check if we can shorten the wait time. */ | |
1332 | delay_cnt = jiffies_to_usecs(time_remain); | |
1333 | if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC) | |
1334 | delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC; | |
1335 | delay_cnt = (delay_cnt >> 3) + 1; | |
95e2869a | 1336 | |
4ba526ce | 1337 | for (i = 0; i < delay_cnt; i++) { |
95e2869a MC |
1338 | if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT)) |
1339 | break; | |
4ba526ce | 1340 | udelay(8); |
95e2869a MC |
1341 | } |
1342 | } | |
1343 | ||
1344 | /* tp->lock is held. */ | |
1345 | static void tg3_ump_link_report(struct tg3 *tp) | |
1346 | { | |
1347 | u32 reg; | |
1348 | u32 val; | |
1349 | ||
63c3a66f | 1350 | if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF)) |
95e2869a MC |
1351 | return; |
1352 | ||
1353 | tg3_wait_for_event_ack(tp); | |
1354 | ||
1355 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE); | |
1356 | ||
1357 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14); | |
1358 | ||
1359 | val = 0; | |
1360 | if (!tg3_readphy(tp, MII_BMCR, ®)) | |
1361 | val = reg << 16; | |
1362 | if (!tg3_readphy(tp, MII_BMSR, ®)) | |
1363 | val |= (reg & 0xffff); | |
1364 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val); | |
1365 | ||
1366 | val = 0; | |
1367 | if (!tg3_readphy(tp, MII_ADVERTISE, ®)) | |
1368 | val = reg << 16; | |
1369 | if (!tg3_readphy(tp, MII_LPA, ®)) | |
1370 | val |= (reg & 0xffff); | |
1371 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val); | |
1372 | ||
1373 | val = 0; | |
f07e9af3 | 1374 | if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) { |
95e2869a MC |
1375 | if (!tg3_readphy(tp, MII_CTRL1000, ®)) |
1376 | val = reg << 16; | |
1377 | if (!tg3_readphy(tp, MII_STAT1000, ®)) | |
1378 | val |= (reg & 0xffff); | |
1379 | } | |
1380 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val); | |
1381 | ||
1382 | if (!tg3_readphy(tp, MII_PHYADDR, ®)) | |
1383 | val = reg << 16; | |
1384 | else | |
1385 | val = 0; | |
1386 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val); | |
1387 | ||
4ba526ce | 1388 | tg3_generate_fw_event(tp); |
95e2869a MC |
1389 | } |
1390 | ||
1391 | static void tg3_link_report(struct tg3 *tp) | |
1392 | { | |
1393 | if (!netif_carrier_ok(tp->dev)) { | |
05dbe005 | 1394 | netif_info(tp, link, tp->dev, "Link is down\n"); |
95e2869a MC |
1395 | tg3_ump_link_report(tp); |
1396 | } else if (netif_msg_link(tp)) { | |
05dbe005 JP |
1397 | netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n", |
1398 | (tp->link_config.active_speed == SPEED_1000 ? | |
1399 | 1000 : | |
1400 | (tp->link_config.active_speed == SPEED_100 ? | |
1401 | 100 : 10)), | |
1402 | (tp->link_config.active_duplex == DUPLEX_FULL ? | |
1403 | "full" : "half")); | |
1404 | ||
1405 | netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n", | |
1406 | (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ? | |
1407 | "on" : "off", | |
1408 | (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ? | |
1409 | "on" : "off"); | |
47007831 MC |
1410 | |
1411 | if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) | |
1412 | netdev_info(tp->dev, "EEE is %s\n", | |
1413 | tp->setlpicnt ? "enabled" : "disabled"); | |
1414 | ||
95e2869a MC |
1415 | tg3_ump_link_report(tp); |
1416 | } | |
1417 | } | |
1418 | ||
1419 | static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl) | |
1420 | { | |
1421 | u16 miireg; | |
1422 | ||
e18ce346 | 1423 | if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX)) |
95e2869a | 1424 | miireg = ADVERTISE_PAUSE_CAP; |
e18ce346 | 1425 | else if (flow_ctrl & FLOW_CTRL_TX) |
95e2869a | 1426 | miireg = ADVERTISE_PAUSE_ASYM; |
e18ce346 | 1427 | else if (flow_ctrl & FLOW_CTRL_RX) |
95e2869a MC |
1428 | miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
1429 | else | |
1430 | miireg = 0; | |
1431 | ||
1432 | return miireg; | |
1433 | } | |
1434 | ||
1435 | static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl) | |
1436 | { | |
1437 | u16 miireg; | |
1438 | ||
e18ce346 | 1439 | if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX)) |
95e2869a | 1440 | miireg = ADVERTISE_1000XPAUSE; |
e18ce346 | 1441 | else if (flow_ctrl & FLOW_CTRL_TX) |
95e2869a | 1442 | miireg = ADVERTISE_1000XPSE_ASYM; |
e18ce346 | 1443 | else if (flow_ctrl & FLOW_CTRL_RX) |
95e2869a MC |
1444 | miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM; |
1445 | else | |
1446 | miireg = 0; | |
1447 | ||
1448 | return miireg; | |
1449 | } | |
1450 | ||
95e2869a MC |
1451 | static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv) |
1452 | { | |
1453 | u8 cap = 0; | |
1454 | ||
1455 | if (lcladv & ADVERTISE_1000XPAUSE) { | |
1456 | if (lcladv & ADVERTISE_1000XPSE_ASYM) { | |
1457 | if (rmtadv & LPA_1000XPAUSE) | |
e18ce346 | 1458 | cap = FLOW_CTRL_TX | FLOW_CTRL_RX; |
95e2869a | 1459 | else if (rmtadv & LPA_1000XPAUSE_ASYM) |
e18ce346 | 1460 | cap = FLOW_CTRL_RX; |
95e2869a MC |
1461 | } else { |
1462 | if (rmtadv & LPA_1000XPAUSE) | |
e18ce346 | 1463 | cap = FLOW_CTRL_TX | FLOW_CTRL_RX; |
95e2869a MC |
1464 | } |
1465 | } else if (lcladv & ADVERTISE_1000XPSE_ASYM) { | |
1466 | if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM)) | |
e18ce346 | 1467 | cap = FLOW_CTRL_TX; |
95e2869a MC |
1468 | } |
1469 | ||
1470 | return cap; | |
1471 | } | |
1472 | ||
f51f3562 | 1473 | static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv) |
95e2869a | 1474 | { |
b02fd9e3 | 1475 | u8 autoneg; |
f51f3562 | 1476 | u8 flowctrl = 0; |
95e2869a MC |
1477 | u32 old_rx_mode = tp->rx_mode; |
1478 | u32 old_tx_mode = tp->tx_mode; | |
1479 | ||
63c3a66f | 1480 | if (tg3_flag(tp, USE_PHYLIB)) |
3f0e3ad7 | 1481 | autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg; |
b02fd9e3 MC |
1482 | else |
1483 | autoneg = tp->link_config.autoneg; | |
1484 | ||
63c3a66f | 1485 | if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) { |
f07e9af3 | 1486 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) |
f51f3562 | 1487 | flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv); |
95e2869a | 1488 | else |
bc02ff95 | 1489 | flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv); |
f51f3562 MC |
1490 | } else |
1491 | flowctrl = tp->link_config.flowctrl; | |
95e2869a | 1492 | |
f51f3562 | 1493 | tp->link_config.active_flowctrl = flowctrl; |
95e2869a | 1494 | |
e18ce346 | 1495 | if (flowctrl & FLOW_CTRL_RX) |
95e2869a MC |
1496 | tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE; |
1497 | else | |
1498 | tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE; | |
1499 | ||
f51f3562 | 1500 | if (old_rx_mode != tp->rx_mode) |
95e2869a | 1501 | tw32_f(MAC_RX_MODE, tp->rx_mode); |
95e2869a | 1502 | |
e18ce346 | 1503 | if (flowctrl & FLOW_CTRL_TX) |
95e2869a MC |
1504 | tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE; |
1505 | else | |
1506 | tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE; | |
1507 | ||
f51f3562 | 1508 | if (old_tx_mode != tp->tx_mode) |
95e2869a | 1509 | tw32_f(MAC_TX_MODE, tp->tx_mode); |
95e2869a MC |
1510 | } |
1511 | ||
b02fd9e3 MC |
1512 | static void tg3_adjust_link(struct net_device *dev) |
1513 | { | |
1514 | u8 oldflowctrl, linkmesg = 0; | |
1515 | u32 mac_mode, lcl_adv, rmt_adv; | |
1516 | struct tg3 *tp = netdev_priv(dev); | |
3f0e3ad7 | 1517 | struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 | 1518 | |
24bb4fb6 | 1519 | spin_lock_bh(&tp->lock); |
b02fd9e3 MC |
1520 | |
1521 | mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK | | |
1522 | MAC_MODE_HALF_DUPLEX); | |
1523 | ||
1524 | oldflowctrl = tp->link_config.active_flowctrl; | |
1525 | ||
1526 | if (phydev->link) { | |
1527 | lcl_adv = 0; | |
1528 | rmt_adv = 0; | |
1529 | ||
1530 | if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10) | |
1531 | mac_mode |= MAC_MODE_PORT_MODE_MII; | |
c3df0748 MC |
1532 | else if (phydev->speed == SPEED_1000 || |
1533 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) | |
b02fd9e3 | 1534 | mac_mode |= MAC_MODE_PORT_MODE_GMII; |
c3df0748 MC |
1535 | else |
1536 | mac_mode |= MAC_MODE_PORT_MODE_MII; | |
b02fd9e3 MC |
1537 | |
1538 | if (phydev->duplex == DUPLEX_HALF) | |
1539 | mac_mode |= MAC_MODE_HALF_DUPLEX; | |
1540 | else { | |
1541 | lcl_adv = tg3_advert_flowctrl_1000T( | |
1542 | tp->link_config.flowctrl); | |
1543 | ||
1544 | if (phydev->pause) | |
1545 | rmt_adv = LPA_PAUSE_CAP; | |
1546 | if (phydev->asym_pause) | |
1547 | rmt_adv |= LPA_PAUSE_ASYM; | |
1548 | } | |
1549 | ||
1550 | tg3_setup_flow_control(tp, lcl_adv, rmt_adv); | |
1551 | } else | |
1552 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
1553 | ||
1554 | if (mac_mode != tp->mac_mode) { | |
1555 | tp->mac_mode = mac_mode; | |
1556 | tw32_f(MAC_MODE, tp->mac_mode); | |
1557 | udelay(40); | |
1558 | } | |
1559 | ||
fcb389df MC |
1560 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { |
1561 | if (phydev->speed == SPEED_10) | |
1562 | tw32(MAC_MI_STAT, | |
1563 | MAC_MI_STAT_10MBPS_MODE | | |
1564 | MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
1565 | else | |
1566 | tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
1567 | } | |
1568 | ||
b02fd9e3 MC |
1569 | if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF) |
1570 | tw32(MAC_TX_LENGTHS, | |
1571 | ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
1572 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
1573 | (0xff << TX_LENGTHS_SLOT_TIME_SHIFT))); | |
1574 | else | |
1575 | tw32(MAC_TX_LENGTHS, | |
1576 | ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
1577 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
1578 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT))); | |
1579 | ||
1580 | if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) || | |
1581 | (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) || | |
1582 | phydev->speed != tp->link_config.active_speed || | |
1583 | phydev->duplex != tp->link_config.active_duplex || | |
1584 | oldflowctrl != tp->link_config.active_flowctrl) | |
c6cdf436 | 1585 | linkmesg = 1; |
b02fd9e3 MC |
1586 | |
1587 | tp->link_config.active_speed = phydev->speed; | |
1588 | tp->link_config.active_duplex = phydev->duplex; | |
1589 | ||
24bb4fb6 | 1590 | spin_unlock_bh(&tp->lock); |
b02fd9e3 MC |
1591 | |
1592 | if (linkmesg) | |
1593 | tg3_link_report(tp); | |
1594 | } | |
1595 | ||
1596 | static int tg3_phy_init(struct tg3 *tp) | |
1597 | { | |
1598 | struct phy_device *phydev; | |
1599 | ||
f07e9af3 | 1600 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) |
b02fd9e3 MC |
1601 | return 0; |
1602 | ||
1603 | /* Bring the PHY back to a known state. */ | |
1604 | tg3_bmcr_reset(tp); | |
1605 | ||
3f0e3ad7 | 1606 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 MC |
1607 | |
1608 | /* Attach the MAC to the PHY. */ | |
fb28ad35 | 1609 | phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link, |
a9daf367 | 1610 | phydev->dev_flags, phydev->interface); |
b02fd9e3 | 1611 | if (IS_ERR(phydev)) { |
ab96b241 | 1612 | dev_err(&tp->pdev->dev, "Could not attach to PHY\n"); |
b02fd9e3 MC |
1613 | return PTR_ERR(phydev); |
1614 | } | |
1615 | ||
b02fd9e3 | 1616 | /* Mask with MAC supported features. */ |
9c61d6bc MC |
1617 | switch (phydev->interface) { |
1618 | case PHY_INTERFACE_MODE_GMII: | |
1619 | case PHY_INTERFACE_MODE_RGMII: | |
f07e9af3 | 1620 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { |
321d32a0 MC |
1621 | phydev->supported &= (PHY_GBIT_FEATURES | |
1622 | SUPPORTED_Pause | | |
1623 | SUPPORTED_Asym_Pause); | |
1624 | break; | |
1625 | } | |
1626 | /* fallthru */ | |
9c61d6bc MC |
1627 | case PHY_INTERFACE_MODE_MII: |
1628 | phydev->supported &= (PHY_BASIC_FEATURES | | |
1629 | SUPPORTED_Pause | | |
1630 | SUPPORTED_Asym_Pause); | |
1631 | break; | |
1632 | default: | |
3f0e3ad7 | 1633 | phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
9c61d6bc MC |
1634 | return -EINVAL; |
1635 | } | |
1636 | ||
f07e9af3 | 1637 | tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED; |
b02fd9e3 MC |
1638 | |
1639 | phydev->advertising = phydev->supported; | |
1640 | ||
b02fd9e3 MC |
1641 | return 0; |
1642 | } | |
1643 | ||
1644 | static void tg3_phy_start(struct tg3 *tp) | |
1645 | { | |
1646 | struct phy_device *phydev; | |
1647 | ||
f07e9af3 | 1648 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 MC |
1649 | return; |
1650 | ||
3f0e3ad7 | 1651 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 | 1652 | |
80096068 MC |
1653 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { |
1654 | tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; | |
b02fd9e3 MC |
1655 | phydev->speed = tp->link_config.orig_speed; |
1656 | phydev->duplex = tp->link_config.orig_duplex; | |
1657 | phydev->autoneg = tp->link_config.orig_autoneg; | |
1658 | phydev->advertising = tp->link_config.orig_advertising; | |
1659 | } | |
1660 | ||
1661 | phy_start(phydev); | |
1662 | ||
1663 | phy_start_aneg(phydev); | |
1664 | } | |
1665 | ||
1666 | static void tg3_phy_stop(struct tg3 *tp) | |
1667 | { | |
f07e9af3 | 1668 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 MC |
1669 | return; |
1670 | ||
3f0e3ad7 | 1671 | phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
b02fd9e3 MC |
1672 | } |
1673 | ||
1674 | static void tg3_phy_fini(struct tg3 *tp) | |
1675 | { | |
f07e9af3 | 1676 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { |
3f0e3ad7 | 1677 | phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
f07e9af3 | 1678 | tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED; |
b02fd9e3 MC |
1679 | } |
1680 | } | |
1681 | ||
7f97a4bd MC |
1682 | static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable) |
1683 | { | |
1684 | u32 phytest; | |
1685 | ||
1686 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { | |
1687 | u32 phy; | |
1688 | ||
1689 | tg3_writephy(tp, MII_TG3_FET_TEST, | |
1690 | phytest | MII_TG3_FET_SHADOW_EN); | |
1691 | if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) { | |
1692 | if (enable) | |
1693 | phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD; | |
1694 | else | |
1695 | phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD; | |
1696 | tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy); | |
1697 | } | |
1698 | tg3_writephy(tp, MII_TG3_FET_TEST, phytest); | |
1699 | } | |
1700 | } | |
1701 | ||
6833c043 MC |
1702 | static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable) |
1703 | { | |
1704 | u32 reg; | |
1705 | ||
63c3a66f JP |
1706 | if (!tg3_flag(tp, 5705_PLUS) || |
1707 | (tg3_flag(tp, 5717_PLUS) && | |
f07e9af3 | 1708 | (tp->phy_flags & TG3_PHYFLG_MII_SERDES))) |
6833c043 MC |
1709 | return; |
1710 | ||
f07e9af3 | 1711 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
7f97a4bd MC |
1712 | tg3_phy_fet_toggle_apd(tp, enable); |
1713 | return; | |
1714 | } | |
1715 | ||
6833c043 MC |
1716 | reg = MII_TG3_MISC_SHDW_WREN | |
1717 | MII_TG3_MISC_SHDW_SCR5_SEL | | |
1718 | MII_TG3_MISC_SHDW_SCR5_LPED | | |
1719 | MII_TG3_MISC_SHDW_SCR5_DLPTLM | | |
1720 | MII_TG3_MISC_SHDW_SCR5_SDTL | | |
1721 | MII_TG3_MISC_SHDW_SCR5_C125OE; | |
1722 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable) | |
1723 | reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD; | |
1724 | ||
1725 | tg3_writephy(tp, MII_TG3_MISC_SHDW, reg); | |
1726 | ||
1727 | ||
1728 | reg = MII_TG3_MISC_SHDW_WREN | | |
1729 | MII_TG3_MISC_SHDW_APD_SEL | | |
1730 | MII_TG3_MISC_SHDW_APD_WKTM_84MS; | |
1731 | if (enable) | |
1732 | reg |= MII_TG3_MISC_SHDW_APD_ENABLE; | |
1733 | ||
1734 | tg3_writephy(tp, MII_TG3_MISC_SHDW, reg); | |
1735 | } | |
1736 | ||
9ef8ca99 MC |
1737 | static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable) |
1738 | { | |
1739 | u32 phy; | |
1740 | ||
63c3a66f | 1741 | if (!tg3_flag(tp, 5705_PLUS) || |
f07e9af3 | 1742 | (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) |
9ef8ca99 MC |
1743 | return; |
1744 | ||
f07e9af3 | 1745 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
9ef8ca99 MC |
1746 | u32 ephy; |
1747 | ||
535ef6e1 MC |
1748 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) { |
1749 | u32 reg = MII_TG3_FET_SHDW_MISCCTRL; | |
1750 | ||
1751 | tg3_writephy(tp, MII_TG3_FET_TEST, | |
1752 | ephy | MII_TG3_FET_SHADOW_EN); | |
1753 | if (!tg3_readphy(tp, reg, &phy)) { | |
9ef8ca99 | 1754 | if (enable) |
535ef6e1 | 1755 | phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX; |
9ef8ca99 | 1756 | else |
535ef6e1 MC |
1757 | phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX; |
1758 | tg3_writephy(tp, reg, phy); | |
9ef8ca99 | 1759 | } |
535ef6e1 | 1760 | tg3_writephy(tp, MII_TG3_FET_TEST, ephy); |
9ef8ca99 MC |
1761 | } |
1762 | } else { | |
15ee95c3 MC |
1763 | int ret; |
1764 | ||
1765 | ret = tg3_phy_auxctl_read(tp, | |
1766 | MII_TG3_AUXCTL_SHDWSEL_MISC, &phy); | |
1767 | if (!ret) { | |
9ef8ca99 MC |
1768 | if (enable) |
1769 | phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX; | |
1770 | else | |
1771 | phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX; | |
b4bd2929 MC |
1772 | tg3_phy_auxctl_write(tp, |
1773 | MII_TG3_AUXCTL_SHDWSEL_MISC, phy); | |
9ef8ca99 MC |
1774 | } |
1775 | } | |
1776 | } | |
1777 | ||
1da177e4 LT |
1778 | static void tg3_phy_set_wirespeed(struct tg3 *tp) |
1779 | { | |
15ee95c3 | 1780 | int ret; |
1da177e4 LT |
1781 | u32 val; |
1782 | ||
f07e9af3 | 1783 | if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) |
1da177e4 LT |
1784 | return; |
1785 | ||
15ee95c3 MC |
1786 | ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val); |
1787 | if (!ret) | |
b4bd2929 MC |
1788 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, |
1789 | val | MII_TG3_AUXCTL_MISC_WIRESPD_EN); | |
1da177e4 LT |
1790 | } |
1791 | ||
b2a5c19c MC |
1792 | static void tg3_phy_apply_otp(struct tg3 *tp) |
1793 | { | |
1794 | u32 otp, phy; | |
1795 | ||
1796 | if (!tp->phy_otp) | |
1797 | return; | |
1798 | ||
1799 | otp = tp->phy_otp; | |
1800 | ||
1d36ba45 MC |
1801 | if (TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) |
1802 | return; | |
b2a5c19c MC |
1803 | |
1804 | phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT); | |
1805 | phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT; | |
1806 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy); | |
1807 | ||
1808 | phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) | | |
1809 | ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT); | |
1810 | tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy); | |
1811 | ||
1812 | phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT); | |
1813 | phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ; | |
1814 | tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy); | |
1815 | ||
1816 | phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT); | |
1817 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy); | |
1818 | ||
1819 | phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT); | |
1820 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy); | |
1821 | ||
1822 | phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) | | |
1823 | ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT); | |
1824 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy); | |
1825 | ||
1d36ba45 | 1826 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); |
b2a5c19c MC |
1827 | } |
1828 | ||
52b02d04 MC |
1829 | static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up) |
1830 | { | |
1831 | u32 val; | |
1832 | ||
1833 | if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) | |
1834 | return; | |
1835 | ||
1836 | tp->setlpicnt = 0; | |
1837 | ||
1838 | if (tp->link_config.autoneg == AUTONEG_ENABLE && | |
1839 | current_link_up == 1 && | |
a6b68dab MC |
1840 | tp->link_config.active_duplex == DUPLEX_FULL && |
1841 | (tp->link_config.active_speed == SPEED_100 || | |
1842 | tp->link_config.active_speed == SPEED_1000)) { | |
52b02d04 MC |
1843 | u32 eeectl; |
1844 | ||
1845 | if (tp->link_config.active_speed == SPEED_1000) | |
1846 | eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US; | |
1847 | else | |
1848 | eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US; | |
1849 | ||
1850 | tw32(TG3_CPMU_EEE_CTRL, eeectl); | |
1851 | ||
3110f5f5 MC |
1852 | tg3_phy_cl45_read(tp, MDIO_MMD_AN, |
1853 | TG3_CL45_D7_EEERES_STAT, &val); | |
52b02d04 | 1854 | |
b0c5943f MC |
1855 | if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T || |
1856 | val == TG3_CL45_D7_EEERES_STAT_LP_100TX) | |
52b02d04 MC |
1857 | tp->setlpicnt = 2; |
1858 | } | |
1859 | ||
1860 | if (!tp->setlpicnt) { | |
1861 | val = tr32(TG3_CPMU_EEE_MODE); | |
1862 | tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE); | |
1863 | } | |
1864 | } | |
1865 | ||
b0c5943f MC |
1866 | static void tg3_phy_eee_enable(struct tg3 *tp) |
1867 | { | |
1868 | u32 val; | |
1869 | ||
1870 | if (tp->link_config.active_speed == SPEED_1000 && | |
1871 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
1872 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
1873 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) && | |
1874 | !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { | |
1875 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0003); | |
1876 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); | |
1877 | } | |
1878 | ||
1879 | val = tr32(TG3_CPMU_EEE_MODE); | |
1880 | tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE); | |
1881 | } | |
1882 | ||
1da177e4 LT |
1883 | static int tg3_wait_macro_done(struct tg3 *tp) |
1884 | { | |
1885 | int limit = 100; | |
1886 | ||
1887 | while (limit--) { | |
1888 | u32 tmp32; | |
1889 | ||
f08aa1a8 | 1890 | if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) { |
1da177e4 LT |
1891 | if ((tmp32 & 0x1000) == 0) |
1892 | break; | |
1893 | } | |
1894 | } | |
d4675b52 | 1895 | if (limit < 0) |
1da177e4 LT |
1896 | return -EBUSY; |
1897 | ||
1898 | return 0; | |
1899 | } | |
1900 | ||
1901 | static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp) | |
1902 | { | |
1903 | static const u32 test_pat[4][6] = { | |
1904 | { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 }, | |
1905 | { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 }, | |
1906 | { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 }, | |
1907 | { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 } | |
1908 | }; | |
1909 | int chan; | |
1910 | ||
1911 | for (chan = 0; chan < 4; chan++) { | |
1912 | int i; | |
1913 | ||
1914 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
1915 | (chan * 0x2000) | 0x0200); | |
f08aa1a8 | 1916 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); |
1da177e4 LT |
1917 | |
1918 | for (i = 0; i < 6; i++) | |
1919 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, | |
1920 | test_pat[chan][i]); | |
1921 | ||
f08aa1a8 | 1922 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); |
1da177e4 LT |
1923 | if (tg3_wait_macro_done(tp)) { |
1924 | *resetp = 1; | |
1925 | return -EBUSY; | |
1926 | } | |
1927 | ||
1928 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
1929 | (chan * 0x2000) | 0x0200); | |
f08aa1a8 | 1930 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082); |
1da177e4 LT |
1931 | if (tg3_wait_macro_done(tp)) { |
1932 | *resetp = 1; | |
1933 | return -EBUSY; | |
1934 | } | |
1935 | ||
f08aa1a8 | 1936 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802); |
1da177e4 LT |
1937 | if (tg3_wait_macro_done(tp)) { |
1938 | *resetp = 1; | |
1939 | return -EBUSY; | |
1940 | } | |
1941 | ||
1942 | for (i = 0; i < 6; i += 2) { | |
1943 | u32 low, high; | |
1944 | ||
1945 | if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) || | |
1946 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) || | |
1947 | tg3_wait_macro_done(tp)) { | |
1948 | *resetp = 1; | |
1949 | return -EBUSY; | |
1950 | } | |
1951 | low &= 0x7fff; | |
1952 | high &= 0x000f; | |
1953 | if (low != test_pat[chan][i] || | |
1954 | high != test_pat[chan][i+1]) { | |
1955 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b); | |
1956 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001); | |
1957 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005); | |
1958 | ||
1959 | return -EBUSY; | |
1960 | } | |
1961 | } | |
1962 | } | |
1963 | ||
1964 | return 0; | |
1965 | } | |
1966 | ||
1967 | static int tg3_phy_reset_chanpat(struct tg3 *tp) | |
1968 | { | |
1969 | int chan; | |
1970 | ||
1971 | for (chan = 0; chan < 4; chan++) { | |
1972 | int i; | |
1973 | ||
1974 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
1975 | (chan * 0x2000) | 0x0200); | |
f08aa1a8 | 1976 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); |
1da177e4 LT |
1977 | for (i = 0; i < 6; i++) |
1978 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000); | |
f08aa1a8 | 1979 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); |
1da177e4 LT |
1980 | if (tg3_wait_macro_done(tp)) |
1981 | return -EBUSY; | |
1982 | } | |
1983 | ||
1984 | return 0; | |
1985 | } | |
1986 | ||
1987 | static int tg3_phy_reset_5703_4_5(struct tg3 *tp) | |
1988 | { | |
1989 | u32 reg32, phy9_orig; | |
1990 | int retries, do_phy_reset, err; | |
1991 | ||
1992 | retries = 10; | |
1993 | do_phy_reset = 1; | |
1994 | do { | |
1995 | if (do_phy_reset) { | |
1996 | err = tg3_bmcr_reset(tp); | |
1997 | if (err) | |
1998 | return err; | |
1999 | do_phy_reset = 0; | |
2000 | } | |
2001 | ||
2002 | /* Disable transmitter and interrupt. */ | |
2003 | if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) | |
2004 | continue; | |
2005 | ||
2006 | reg32 |= 0x3000; | |
2007 | tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); | |
2008 | ||
2009 | /* Set full-duplex, 1000 mbps. */ | |
2010 | tg3_writephy(tp, MII_BMCR, | |
221c5637 | 2011 | BMCR_FULLDPLX | BMCR_SPEED1000); |
1da177e4 LT |
2012 | |
2013 | /* Set to master mode. */ | |
221c5637 | 2014 | if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig)) |
1da177e4 LT |
2015 | continue; |
2016 | ||
221c5637 MC |
2017 | tg3_writephy(tp, MII_CTRL1000, |
2018 | CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER); | |
1da177e4 | 2019 | |
1d36ba45 MC |
2020 | err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp); |
2021 | if (err) | |
2022 | return err; | |
1da177e4 LT |
2023 | |
2024 | /* Block the PHY control access. */ | |
6ee7c0a0 | 2025 | tg3_phydsp_write(tp, 0x8005, 0x0800); |
1da177e4 LT |
2026 | |
2027 | err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset); | |
2028 | if (!err) | |
2029 | break; | |
2030 | } while (--retries); | |
2031 | ||
2032 | err = tg3_phy_reset_chanpat(tp); | |
2033 | if (err) | |
2034 | return err; | |
2035 | ||
6ee7c0a0 | 2036 | tg3_phydsp_write(tp, 0x8005, 0x0000); |
1da177e4 LT |
2037 | |
2038 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200); | |
f08aa1a8 | 2039 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000); |
1da177e4 | 2040 | |
1d36ba45 | 2041 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); |
1da177e4 | 2042 | |
221c5637 | 2043 | tg3_writephy(tp, MII_CTRL1000, phy9_orig); |
1da177e4 LT |
2044 | |
2045 | if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) { | |
2046 | reg32 &= ~0x3000; | |
2047 | tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); | |
2048 | } else if (!err) | |
2049 | err = -EBUSY; | |
2050 | ||
2051 | return err; | |
2052 | } | |
2053 | ||
2054 | /* This will reset the tigon3 PHY if there is no valid | |
2055 | * link unless the FORCE argument is non-zero. | |
2056 | */ | |
2057 | static int tg3_phy_reset(struct tg3 *tp) | |
2058 | { | |
f833c4c1 | 2059 | u32 val, cpmuctrl; |
1da177e4 LT |
2060 | int err; |
2061 | ||
60189ddf | 2062 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
60189ddf MC |
2063 | val = tr32(GRC_MISC_CFG); |
2064 | tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ); | |
2065 | udelay(40); | |
2066 | } | |
f833c4c1 MC |
2067 | err = tg3_readphy(tp, MII_BMSR, &val); |
2068 | err |= tg3_readphy(tp, MII_BMSR, &val); | |
1da177e4 LT |
2069 | if (err != 0) |
2070 | return -EBUSY; | |
2071 | ||
c8e1e82b MC |
2072 | if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) { |
2073 | netif_carrier_off(tp->dev); | |
2074 | tg3_link_report(tp); | |
2075 | } | |
2076 | ||
1da177e4 LT |
2077 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || |
2078 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
2079 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
2080 | err = tg3_phy_reset_5703_4_5(tp); | |
2081 | if (err) | |
2082 | return err; | |
2083 | goto out; | |
2084 | } | |
2085 | ||
b2a5c19c MC |
2086 | cpmuctrl = 0; |
2087 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && | |
2088 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) { | |
2089 | cpmuctrl = tr32(TG3_CPMU_CTRL); | |
2090 | if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) | |
2091 | tw32(TG3_CPMU_CTRL, | |
2092 | cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY); | |
2093 | } | |
2094 | ||
1da177e4 LT |
2095 | err = tg3_bmcr_reset(tp); |
2096 | if (err) | |
2097 | return err; | |
2098 | ||
b2a5c19c | 2099 | if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) { |
f833c4c1 MC |
2100 | val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz; |
2101 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val); | |
b2a5c19c MC |
2102 | |
2103 | tw32(TG3_CPMU_CTRL, cpmuctrl); | |
2104 | } | |
2105 | ||
bcb37f6c MC |
2106 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX || |
2107 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) { | |
ce057f01 MC |
2108 | val = tr32(TG3_CPMU_LSPD_1000MB_CLK); |
2109 | if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) == | |
2110 | CPMU_LSPD_1000MB_MACCLK_12_5) { | |
2111 | val &= ~CPMU_LSPD_1000MB_MACCLK_MASK; | |
2112 | udelay(40); | |
2113 | tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val); | |
2114 | } | |
2115 | } | |
2116 | ||
63c3a66f | 2117 | if (tg3_flag(tp, 5717_PLUS) && |
f07e9af3 | 2118 | (tp->phy_flags & TG3_PHYFLG_MII_SERDES)) |
ecf1410b MC |
2119 | return 0; |
2120 | ||
b2a5c19c MC |
2121 | tg3_phy_apply_otp(tp); |
2122 | ||
f07e9af3 | 2123 | if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) |
6833c043 MC |
2124 | tg3_phy_toggle_apd(tp, true); |
2125 | else | |
2126 | tg3_phy_toggle_apd(tp, false); | |
2127 | ||
1da177e4 | 2128 | out: |
1d36ba45 MC |
2129 | if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) && |
2130 | !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { | |
6ee7c0a0 MC |
2131 | tg3_phydsp_write(tp, 0x201f, 0x2aaa); |
2132 | tg3_phydsp_write(tp, 0x000a, 0x0323); | |
1d36ba45 | 2133 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); |
1da177e4 | 2134 | } |
1d36ba45 | 2135 | |
f07e9af3 | 2136 | if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) { |
f08aa1a8 MC |
2137 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); |
2138 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); | |
1da177e4 | 2139 | } |
1d36ba45 | 2140 | |
f07e9af3 | 2141 | if (tp->phy_flags & TG3_PHYFLG_BER_BUG) { |
1d36ba45 MC |
2142 | if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { |
2143 | tg3_phydsp_write(tp, 0x000a, 0x310b); | |
2144 | tg3_phydsp_write(tp, 0x201f, 0x9506); | |
2145 | tg3_phydsp_write(tp, 0x401f, 0x14e2); | |
2146 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); | |
2147 | } | |
f07e9af3 | 2148 | } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) { |
1d36ba45 MC |
2149 | if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { |
2150 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a); | |
2151 | if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) { | |
2152 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b); | |
2153 | tg3_writephy(tp, MII_TG3_TEST1, | |
2154 | MII_TG3_TEST1_TRIM_EN | 0x4); | |
2155 | } else | |
2156 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b); | |
2157 | ||
2158 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); | |
2159 | } | |
c424cb24 | 2160 | } |
1d36ba45 | 2161 | |
1da177e4 LT |
2162 | /* Set Extended packet length bit (bit 14) on all chips that */ |
2163 | /* support jumbo frames */ | |
79eb6904 | 2164 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { |
1da177e4 | 2165 | /* Cannot do read-modify-write on 5401 */ |
b4bd2929 | 2166 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20); |
63c3a66f | 2167 | } else if (tg3_flag(tp, JUMBO_CAPABLE)) { |
1da177e4 | 2168 | /* Set bit 14 with read-modify-write to preserve other bits */ |
15ee95c3 MC |
2169 | err = tg3_phy_auxctl_read(tp, |
2170 | MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val); | |
2171 | if (!err) | |
b4bd2929 MC |
2172 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, |
2173 | val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN); | |
1da177e4 LT |
2174 | } |
2175 | ||
2176 | /* Set phy register 0x10 bit 0 to high fifo elasticity to support | |
2177 | * jumbo frames transmission. | |
2178 | */ | |
63c3a66f | 2179 | if (tg3_flag(tp, JUMBO_CAPABLE)) { |
f833c4c1 | 2180 | if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val)) |
c6cdf436 | 2181 | tg3_writephy(tp, MII_TG3_EXT_CTRL, |
f833c4c1 | 2182 | val | MII_TG3_EXT_CTRL_FIFO_ELASTIC); |
1da177e4 LT |
2183 | } |
2184 | ||
715116a1 | 2185 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
715116a1 | 2186 | /* adjust output voltage */ |
535ef6e1 | 2187 | tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12); |
715116a1 MC |
2188 | } |
2189 | ||
9ef8ca99 | 2190 | tg3_phy_toggle_automdix(tp, 1); |
1da177e4 LT |
2191 | tg3_phy_set_wirespeed(tp); |
2192 | return 0; | |
2193 | } | |
2194 | ||
520b2756 MC |
2195 | static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp) |
2196 | { | |
2197 | if (!tg3_flag(tp, IS_NIC)) | |
6f5c8f83 MC |
2198 | return; |
2199 | ||
2200 | if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO)) | |
520b2756 MC |
2201 | return 0; |
2202 | ||
2203 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, | |
2204 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2205 | ||
6f5c8f83 MC |
2206 | tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO); |
2207 | ||
520b2756 MC |
2208 | return 0; |
2209 | } | |
2210 | ||
2211 | static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp) | |
2212 | { | |
2213 | u32 grc_local_ctrl; | |
2214 | ||
2215 | if (!tg3_flag(tp, IS_NIC) || | |
2216 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2217 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) | |
2218 | return; | |
2219 | ||
6f5c8f83 MC |
2220 | |
2221 | if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO)) | |
2222 | return; | |
2223 | ||
520b2756 MC |
2224 | grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1; |
2225 | ||
2226 | tw32_wait_f(GRC_LOCAL_CTRL, | |
2227 | grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1, | |
2228 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2229 | ||
2230 | tw32_wait_f(GRC_LOCAL_CTRL, | |
2231 | grc_local_ctrl, | |
2232 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2233 | ||
2234 | tw32_wait_f(GRC_LOCAL_CTRL, | |
2235 | grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1, | |
2236 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
6f5c8f83 MC |
2237 | |
2238 | tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO); | |
520b2756 MC |
2239 | } |
2240 | ||
2241 | static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp) | |
2242 | { | |
2243 | if (!tg3_flag(tp, IS_NIC)) | |
2244 | return; | |
2245 | ||
6f5c8f83 MC |
2246 | if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO)) |
2247 | return; | |
2248 | ||
520b2756 MC |
2249 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
2250 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
2251 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | | |
2252 | (GRC_LCLCTRL_GPIO_OE0 | | |
2253 | GRC_LCLCTRL_GPIO_OE1 | | |
2254 | GRC_LCLCTRL_GPIO_OE2 | | |
2255 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
2256 | GRC_LCLCTRL_GPIO_OUTPUT1), | |
2257 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2258 | } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || | |
2259 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { | |
2260 | /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */ | |
2261 | u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 | | |
2262 | GRC_LCLCTRL_GPIO_OE1 | | |
2263 | GRC_LCLCTRL_GPIO_OE2 | | |
2264 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
2265 | GRC_LCLCTRL_GPIO_OUTPUT1 | | |
2266 | tp->grc_local_ctrl; | |
2267 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, | |
2268 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2269 | ||
2270 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2; | |
2271 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, | |
2272 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2273 | ||
2274 | grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0; | |
2275 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, | |
2276 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2277 | } else { | |
2278 | u32 no_gpio2; | |
2279 | u32 grc_local_ctrl = 0; | |
2280 | ||
2281 | /* Workaround to prevent overdrawing Amps. */ | |
2282 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { | |
2283 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; | |
2284 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | | |
2285 | grc_local_ctrl, | |
2286 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2287 | } | |
2288 | ||
2289 | /* On 5753 and variants, GPIO2 cannot be used. */ | |
2290 | no_gpio2 = tp->nic_sram_data_cfg & | |
2291 | NIC_SRAM_DATA_CFG_NO_GPIO2; | |
2292 | ||
2293 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 | | |
2294 | GRC_LCLCTRL_GPIO_OE1 | | |
2295 | GRC_LCLCTRL_GPIO_OE2 | | |
2296 | GRC_LCLCTRL_GPIO_OUTPUT1 | | |
2297 | GRC_LCLCTRL_GPIO_OUTPUT2; | |
2298 | if (no_gpio2) { | |
2299 | grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 | | |
2300 | GRC_LCLCTRL_GPIO_OUTPUT2); | |
2301 | } | |
2302 | tw32_wait_f(GRC_LOCAL_CTRL, | |
2303 | tp->grc_local_ctrl | grc_local_ctrl, | |
2304 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2305 | ||
2306 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0; | |
2307 | ||
2308 | tw32_wait_f(GRC_LOCAL_CTRL, | |
2309 | tp->grc_local_ctrl | grc_local_ctrl, | |
2310 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2311 | ||
2312 | if (!no_gpio2) { | |
2313 | grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2; | |
2314 | tw32_wait_f(GRC_LOCAL_CTRL, | |
2315 | tp->grc_local_ctrl | grc_local_ctrl, | |
2316 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2317 | } | |
2318 | } | |
6f5c8f83 MC |
2319 | |
2320 | tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO); | |
520b2756 MC |
2321 | } |
2322 | ||
1da177e4 LT |
2323 | static void tg3_frob_aux_power(struct tg3 *tp) |
2324 | { | |
683644b7 | 2325 | bool need_vaux = false; |
1da177e4 | 2326 | |
334355aa | 2327 | /* The GPIOs do something completely different on 57765. */ |
63c3a66f | 2328 | if (!tg3_flag(tp, IS_NIC) || |
a50d0796 | 2329 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
334355aa | 2330 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) |
1da177e4 LT |
2331 | return; |
2332 | ||
683644b7 MC |
2333 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || |
2334 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 || | |
d78b59f5 MC |
2335 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
2336 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) && | |
683644b7 | 2337 | tp->pdev_peer != tp->pdev) { |
8c2dc7e1 MC |
2338 | struct net_device *dev_peer; |
2339 | ||
2340 | dev_peer = pci_get_drvdata(tp->pdev_peer); | |
683644b7 | 2341 | |
bc1c7567 | 2342 | /* remove_one() may have been run on the peer. */ |
683644b7 MC |
2343 | if (dev_peer) { |
2344 | struct tg3 *tp_peer = netdev_priv(dev_peer); | |
2345 | ||
63c3a66f | 2346 | if (tg3_flag(tp_peer, INIT_COMPLETE)) |
683644b7 MC |
2347 | return; |
2348 | ||
63c3a66f JP |
2349 | if (tg3_flag(tp_peer, WOL_ENABLE) || |
2350 | tg3_flag(tp_peer, ENABLE_ASF)) | |
683644b7 MC |
2351 | need_vaux = true; |
2352 | } | |
1da177e4 LT |
2353 | } |
2354 | ||
63c3a66f | 2355 | if (tg3_flag(tp, WOL_ENABLE) || tg3_flag(tp, ENABLE_ASF)) |
683644b7 MC |
2356 | need_vaux = true; |
2357 | ||
520b2756 MC |
2358 | if (need_vaux) |
2359 | tg3_pwrsrc_switch_to_vaux(tp); | |
2360 | else | |
2361 | tg3_pwrsrc_die_with_vmain(tp); | |
1da177e4 LT |
2362 | } |
2363 | ||
e8f3f6ca MC |
2364 | static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed) |
2365 | { | |
2366 | if (tp->led_ctrl == LED_CTRL_MODE_PHY_2) | |
2367 | return 1; | |
79eb6904 | 2368 | else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) { |
e8f3f6ca MC |
2369 | if (speed != SPEED_10) |
2370 | return 1; | |
2371 | } else if (speed == SPEED_10) | |
2372 | return 1; | |
2373 | ||
2374 | return 0; | |
2375 | } | |
2376 | ||
1da177e4 LT |
2377 | static int tg3_setup_phy(struct tg3 *, int); |
2378 | ||
2379 | #define RESET_KIND_SHUTDOWN 0 | |
2380 | #define RESET_KIND_INIT 1 | |
2381 | #define RESET_KIND_SUSPEND 2 | |
2382 | ||
2383 | static void tg3_write_sig_post_reset(struct tg3 *, int); | |
2384 | static int tg3_halt_cpu(struct tg3 *, u32); | |
2385 | ||
0a459aac | 2386 | static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power) |
15c3b696 | 2387 | { |
ce057f01 MC |
2388 | u32 val; |
2389 | ||
f07e9af3 | 2390 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
5129724a MC |
2391 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { |
2392 | u32 sg_dig_ctrl = tr32(SG_DIG_CTRL); | |
2393 | u32 serdes_cfg = tr32(MAC_SERDES_CFG); | |
2394 | ||
2395 | sg_dig_ctrl |= | |
2396 | SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET; | |
2397 | tw32(SG_DIG_CTRL, sg_dig_ctrl); | |
2398 | tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15)); | |
2399 | } | |
3f7045c1 | 2400 | return; |
5129724a | 2401 | } |
3f7045c1 | 2402 | |
60189ddf | 2403 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
60189ddf MC |
2404 | tg3_bmcr_reset(tp); |
2405 | val = tr32(GRC_MISC_CFG); | |
2406 | tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ); | |
2407 | udelay(40); | |
2408 | return; | |
f07e9af3 | 2409 | } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
0e5f784c MC |
2410 | u32 phytest; |
2411 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { | |
2412 | u32 phy; | |
2413 | ||
2414 | tg3_writephy(tp, MII_ADVERTISE, 0); | |
2415 | tg3_writephy(tp, MII_BMCR, | |
2416 | BMCR_ANENABLE | BMCR_ANRESTART); | |
2417 | ||
2418 | tg3_writephy(tp, MII_TG3_FET_TEST, | |
2419 | phytest | MII_TG3_FET_SHADOW_EN); | |
2420 | if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) { | |
2421 | phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD; | |
2422 | tg3_writephy(tp, | |
2423 | MII_TG3_FET_SHDW_AUXMODE4, | |
2424 | phy); | |
2425 | } | |
2426 | tg3_writephy(tp, MII_TG3_FET_TEST, phytest); | |
2427 | } | |
2428 | return; | |
0a459aac | 2429 | } else if (do_low_power) { |
715116a1 MC |
2430 | tg3_writephy(tp, MII_TG3_EXT_CTRL, |
2431 | MII_TG3_EXT_CTRL_FORCE_LED_OFF); | |
0a459aac | 2432 | |
b4bd2929 MC |
2433 | val = MII_TG3_AUXCTL_PCTL_100TX_LPWR | |
2434 | MII_TG3_AUXCTL_PCTL_SPR_ISOLATE | | |
2435 | MII_TG3_AUXCTL_PCTL_VREG_11V; | |
2436 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val); | |
715116a1 | 2437 | } |
3f7045c1 | 2438 | |
15c3b696 MC |
2439 | /* The PHY should not be powered down on some chips because |
2440 | * of bugs. | |
2441 | */ | |
2442 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2443 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
2444 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 && | |
f07e9af3 | 2445 | (tp->phy_flags & TG3_PHYFLG_MII_SERDES))) |
15c3b696 | 2446 | return; |
ce057f01 | 2447 | |
bcb37f6c MC |
2448 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX || |
2449 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) { | |
ce057f01 MC |
2450 | val = tr32(TG3_CPMU_LSPD_1000MB_CLK); |
2451 | val &= ~CPMU_LSPD_1000MB_MACCLK_MASK; | |
2452 | val |= CPMU_LSPD_1000MB_MACCLK_12_5; | |
2453 | tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val); | |
2454 | } | |
2455 | ||
15c3b696 MC |
2456 | tg3_writephy(tp, MII_BMCR, BMCR_PDOWN); |
2457 | } | |
2458 | ||
ffbcfed4 MC |
2459 | /* tp->lock is held. */ |
2460 | static int tg3_nvram_lock(struct tg3 *tp) | |
2461 | { | |
63c3a66f | 2462 | if (tg3_flag(tp, NVRAM)) { |
ffbcfed4 MC |
2463 | int i; |
2464 | ||
2465 | if (tp->nvram_lock_cnt == 0) { | |
2466 | tw32(NVRAM_SWARB, SWARB_REQ_SET1); | |
2467 | for (i = 0; i < 8000; i++) { | |
2468 | if (tr32(NVRAM_SWARB) & SWARB_GNT1) | |
2469 | break; | |
2470 | udelay(20); | |
2471 | } | |
2472 | if (i == 8000) { | |
2473 | tw32(NVRAM_SWARB, SWARB_REQ_CLR1); | |
2474 | return -ENODEV; | |
2475 | } | |
2476 | } | |
2477 | tp->nvram_lock_cnt++; | |
2478 | } | |
2479 | return 0; | |
2480 | } | |
2481 | ||
2482 | /* tp->lock is held. */ | |
2483 | static void tg3_nvram_unlock(struct tg3 *tp) | |
2484 | { | |
63c3a66f | 2485 | if (tg3_flag(tp, NVRAM)) { |
ffbcfed4 MC |
2486 | if (tp->nvram_lock_cnt > 0) |
2487 | tp->nvram_lock_cnt--; | |
2488 | if (tp->nvram_lock_cnt == 0) | |
2489 | tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1); | |
2490 | } | |
2491 | } | |
2492 | ||
2493 | /* tp->lock is held. */ | |
2494 | static void tg3_enable_nvram_access(struct tg3 *tp) | |
2495 | { | |
63c3a66f | 2496 | if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) { |
ffbcfed4 MC |
2497 | u32 nvaccess = tr32(NVRAM_ACCESS); |
2498 | ||
2499 | tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE); | |
2500 | } | |
2501 | } | |
2502 | ||
2503 | /* tp->lock is held. */ | |
2504 | static void tg3_disable_nvram_access(struct tg3 *tp) | |
2505 | { | |
63c3a66f | 2506 | if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) { |
ffbcfed4 MC |
2507 | u32 nvaccess = tr32(NVRAM_ACCESS); |
2508 | ||
2509 | tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE); | |
2510 | } | |
2511 | } | |
2512 | ||
2513 | static int tg3_nvram_read_using_eeprom(struct tg3 *tp, | |
2514 | u32 offset, u32 *val) | |
2515 | { | |
2516 | u32 tmp; | |
2517 | int i; | |
2518 | ||
2519 | if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0) | |
2520 | return -EINVAL; | |
2521 | ||
2522 | tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK | | |
2523 | EEPROM_ADDR_DEVID_MASK | | |
2524 | EEPROM_ADDR_READ); | |
2525 | tw32(GRC_EEPROM_ADDR, | |
2526 | tmp | | |
2527 | (0 << EEPROM_ADDR_DEVID_SHIFT) | | |
2528 | ((offset << EEPROM_ADDR_ADDR_SHIFT) & | |
2529 | EEPROM_ADDR_ADDR_MASK) | | |
2530 | EEPROM_ADDR_READ | EEPROM_ADDR_START); | |
2531 | ||
2532 | for (i = 0; i < 1000; i++) { | |
2533 | tmp = tr32(GRC_EEPROM_ADDR); | |
2534 | ||
2535 | if (tmp & EEPROM_ADDR_COMPLETE) | |
2536 | break; | |
2537 | msleep(1); | |
2538 | } | |
2539 | if (!(tmp & EEPROM_ADDR_COMPLETE)) | |
2540 | return -EBUSY; | |
2541 | ||
62cedd11 MC |
2542 | tmp = tr32(GRC_EEPROM_DATA); |
2543 | ||
2544 | /* | |
2545 | * The data will always be opposite the native endian | |
2546 | * format. Perform a blind byteswap to compensate. | |
2547 | */ | |
2548 | *val = swab32(tmp); | |
2549 | ||
ffbcfed4 MC |
2550 | return 0; |
2551 | } | |
2552 | ||
2553 | #define NVRAM_CMD_TIMEOUT 10000 | |
2554 | ||
2555 | static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd) | |
2556 | { | |
2557 | int i; | |
2558 | ||
2559 | tw32(NVRAM_CMD, nvram_cmd); | |
2560 | for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) { | |
2561 | udelay(10); | |
2562 | if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) { | |
2563 | udelay(10); | |
2564 | break; | |
2565 | } | |
2566 | } | |
2567 | ||
2568 | if (i == NVRAM_CMD_TIMEOUT) | |
2569 | return -EBUSY; | |
2570 | ||
2571 | return 0; | |
2572 | } | |
2573 | ||
2574 | static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr) | |
2575 | { | |
63c3a66f JP |
2576 | if (tg3_flag(tp, NVRAM) && |
2577 | tg3_flag(tp, NVRAM_BUFFERED) && | |
2578 | tg3_flag(tp, FLASH) && | |
2579 | !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) && | |
ffbcfed4 MC |
2580 | (tp->nvram_jedecnum == JEDEC_ATMEL)) |
2581 | ||
2582 | addr = ((addr / tp->nvram_pagesize) << | |
2583 | ATMEL_AT45DB0X1B_PAGE_POS) + | |
2584 | (addr % tp->nvram_pagesize); | |
2585 | ||
2586 | return addr; | |
2587 | } | |
2588 | ||
2589 | static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr) | |
2590 | { | |
63c3a66f JP |
2591 | if (tg3_flag(tp, NVRAM) && |
2592 | tg3_flag(tp, NVRAM_BUFFERED) && | |
2593 | tg3_flag(tp, FLASH) && | |
2594 | !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) && | |
ffbcfed4 MC |
2595 | (tp->nvram_jedecnum == JEDEC_ATMEL)) |
2596 | ||
2597 | addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) * | |
2598 | tp->nvram_pagesize) + | |
2599 | (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1)); | |
2600 | ||
2601 | return addr; | |
2602 | } | |
2603 | ||
e4f34110 MC |
2604 | /* NOTE: Data read in from NVRAM is byteswapped according to |
2605 | * the byteswapping settings for all other register accesses. | |
2606 | * tg3 devices are BE devices, so on a BE machine, the data | |
2607 | * returned will be exactly as it is seen in NVRAM. On a LE | |
2608 | * machine, the 32-bit value will be byteswapped. | |
2609 | */ | |
ffbcfed4 MC |
2610 | static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val) |
2611 | { | |
2612 | int ret; | |
2613 | ||
63c3a66f | 2614 | if (!tg3_flag(tp, NVRAM)) |
ffbcfed4 MC |
2615 | return tg3_nvram_read_using_eeprom(tp, offset, val); |
2616 | ||
2617 | offset = tg3_nvram_phys_addr(tp, offset); | |
2618 | ||
2619 | if (offset > NVRAM_ADDR_MSK) | |
2620 | return -EINVAL; | |
2621 | ||
2622 | ret = tg3_nvram_lock(tp); | |
2623 | if (ret) | |
2624 | return ret; | |
2625 | ||
2626 | tg3_enable_nvram_access(tp); | |
2627 | ||
2628 | tw32(NVRAM_ADDR, offset); | |
2629 | ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO | | |
2630 | NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE); | |
2631 | ||
2632 | if (ret == 0) | |
e4f34110 | 2633 | *val = tr32(NVRAM_RDDATA); |
ffbcfed4 MC |
2634 | |
2635 | tg3_disable_nvram_access(tp); | |
2636 | ||
2637 | tg3_nvram_unlock(tp); | |
2638 | ||
2639 | return ret; | |
2640 | } | |
2641 | ||
a9dc529d MC |
2642 | /* Ensures NVRAM data is in bytestream format. */ |
2643 | static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val) | |
ffbcfed4 MC |
2644 | { |
2645 | u32 v; | |
a9dc529d | 2646 | int res = tg3_nvram_read(tp, offset, &v); |
ffbcfed4 | 2647 | if (!res) |
a9dc529d | 2648 | *val = cpu_to_be32(v); |
ffbcfed4 MC |
2649 | return res; |
2650 | } | |
2651 | ||
3f007891 MC |
2652 | /* tp->lock is held. */ |
2653 | static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1) | |
2654 | { | |
2655 | u32 addr_high, addr_low; | |
2656 | int i; | |
2657 | ||
2658 | addr_high = ((tp->dev->dev_addr[0] << 8) | | |
2659 | tp->dev->dev_addr[1]); | |
2660 | addr_low = ((tp->dev->dev_addr[2] << 24) | | |
2661 | (tp->dev->dev_addr[3] << 16) | | |
2662 | (tp->dev->dev_addr[4] << 8) | | |
2663 | (tp->dev->dev_addr[5] << 0)); | |
2664 | for (i = 0; i < 4; i++) { | |
2665 | if (i == 1 && skip_mac_1) | |
2666 | continue; | |
2667 | tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high); | |
2668 | tw32(MAC_ADDR_0_LOW + (i * 8), addr_low); | |
2669 | } | |
2670 | ||
2671 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
2672 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
2673 | for (i = 0; i < 12; i++) { | |
2674 | tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high); | |
2675 | tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low); | |
2676 | } | |
2677 | } | |
2678 | ||
2679 | addr_high = (tp->dev->dev_addr[0] + | |
2680 | tp->dev->dev_addr[1] + | |
2681 | tp->dev->dev_addr[2] + | |
2682 | tp->dev->dev_addr[3] + | |
2683 | tp->dev->dev_addr[4] + | |
2684 | tp->dev->dev_addr[5]) & | |
2685 | TX_BACKOFF_SEED_MASK; | |
2686 | tw32(MAC_TX_BACKOFF_SEED, addr_high); | |
2687 | } | |
2688 | ||
c866b7ea | 2689 | static void tg3_enable_register_access(struct tg3 *tp) |
1da177e4 | 2690 | { |
c866b7ea RW |
2691 | /* |
2692 | * Make sure register accesses (indirect or otherwise) will function | |
2693 | * correctly. | |
1da177e4 LT |
2694 | */ |
2695 | pci_write_config_dword(tp->pdev, | |
c866b7ea RW |
2696 | TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl); |
2697 | } | |
1da177e4 | 2698 | |
c866b7ea RW |
2699 | static int tg3_power_up(struct tg3 *tp) |
2700 | { | |
bed9829f | 2701 | int err; |
8c6bda1a | 2702 | |
bed9829f | 2703 | tg3_enable_register_access(tp); |
1da177e4 | 2704 | |
bed9829f MC |
2705 | err = pci_set_power_state(tp->pdev, PCI_D0); |
2706 | if (!err) { | |
2707 | /* Switch out of Vaux if it is a NIC */ | |
2708 | tg3_pwrsrc_switch_to_vmain(tp); | |
2709 | } else { | |
2710 | netdev_err(tp->dev, "Transition to D0 failed\n"); | |
2711 | } | |
1da177e4 | 2712 | |
bed9829f | 2713 | return err; |
c866b7ea | 2714 | } |
1da177e4 | 2715 | |
c866b7ea RW |
2716 | static int tg3_power_down_prepare(struct tg3 *tp) |
2717 | { | |
2718 | u32 misc_host_ctrl; | |
2719 | bool device_should_wake, do_low_power; | |
2720 | ||
2721 | tg3_enable_register_access(tp); | |
5e7dfd0f MC |
2722 | |
2723 | /* Restore the CLKREQ setting. */ | |
63c3a66f | 2724 | if (tg3_flag(tp, CLKREQ_BUG)) { |
5e7dfd0f MC |
2725 | u16 lnkctl; |
2726 | ||
2727 | pci_read_config_word(tp->pdev, | |
708ebb3a | 2728 | pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL, |
5e7dfd0f MC |
2729 | &lnkctl); |
2730 | lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN; | |
2731 | pci_write_config_word(tp->pdev, | |
708ebb3a | 2732 | pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL, |
5e7dfd0f MC |
2733 | lnkctl); |
2734 | } | |
2735 | ||
1da177e4 LT |
2736 | misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL); |
2737 | tw32(TG3PCI_MISC_HOST_CTRL, | |
2738 | misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT); | |
2739 | ||
c866b7ea | 2740 | device_should_wake = device_may_wakeup(&tp->pdev->dev) && |
63c3a66f | 2741 | tg3_flag(tp, WOL_ENABLE); |
05ac4cb7 | 2742 | |
63c3a66f | 2743 | if (tg3_flag(tp, USE_PHYLIB)) { |
0a459aac | 2744 | do_low_power = false; |
f07e9af3 | 2745 | if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) && |
80096068 | 2746 | !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { |
b02fd9e3 | 2747 | struct phy_device *phydev; |
0a459aac | 2748 | u32 phyid, advertising; |
b02fd9e3 | 2749 | |
3f0e3ad7 | 2750 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 | 2751 | |
80096068 | 2752 | tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; |
b02fd9e3 MC |
2753 | |
2754 | tp->link_config.orig_speed = phydev->speed; | |
2755 | tp->link_config.orig_duplex = phydev->duplex; | |
2756 | tp->link_config.orig_autoneg = phydev->autoneg; | |
2757 | tp->link_config.orig_advertising = phydev->advertising; | |
2758 | ||
2759 | advertising = ADVERTISED_TP | | |
2760 | ADVERTISED_Pause | | |
2761 | ADVERTISED_Autoneg | | |
2762 | ADVERTISED_10baseT_Half; | |
2763 | ||
63c3a66f JP |
2764 | if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) { |
2765 | if (tg3_flag(tp, WOL_SPEED_100MB)) | |
b02fd9e3 MC |
2766 | advertising |= |
2767 | ADVERTISED_100baseT_Half | | |
2768 | ADVERTISED_100baseT_Full | | |
2769 | ADVERTISED_10baseT_Full; | |
2770 | else | |
2771 | advertising |= ADVERTISED_10baseT_Full; | |
2772 | } | |
2773 | ||
2774 | phydev->advertising = advertising; | |
2775 | ||
2776 | phy_start_aneg(phydev); | |
0a459aac MC |
2777 | |
2778 | phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask; | |
6a443a0f MC |
2779 | if (phyid != PHY_ID_BCMAC131) { |
2780 | phyid &= PHY_BCM_OUI_MASK; | |
2781 | if (phyid == PHY_BCM_OUI_1 || | |
2782 | phyid == PHY_BCM_OUI_2 || | |
2783 | phyid == PHY_BCM_OUI_3) | |
0a459aac MC |
2784 | do_low_power = true; |
2785 | } | |
b02fd9e3 | 2786 | } |
dd477003 | 2787 | } else { |
2023276e | 2788 | do_low_power = true; |
0a459aac | 2789 | |
80096068 MC |
2790 | if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { |
2791 | tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; | |
dd477003 MC |
2792 | tp->link_config.orig_speed = tp->link_config.speed; |
2793 | tp->link_config.orig_duplex = tp->link_config.duplex; | |
2794 | tp->link_config.orig_autoneg = tp->link_config.autoneg; | |
2795 | } | |
1da177e4 | 2796 | |
f07e9af3 | 2797 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { |
dd477003 MC |
2798 | tp->link_config.speed = SPEED_10; |
2799 | tp->link_config.duplex = DUPLEX_HALF; | |
2800 | tp->link_config.autoneg = AUTONEG_ENABLE; | |
2801 | tg3_setup_phy(tp, 0); | |
2802 | } | |
1da177e4 LT |
2803 | } |
2804 | ||
b5d3772c MC |
2805 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
2806 | u32 val; | |
2807 | ||
2808 | val = tr32(GRC_VCPU_EXT_CTRL); | |
2809 | tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL); | |
63c3a66f | 2810 | } else if (!tg3_flag(tp, ENABLE_ASF)) { |
6921d201 MC |
2811 | int i; |
2812 | u32 val; | |
2813 | ||
2814 | for (i = 0; i < 200; i++) { | |
2815 | tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val); | |
2816 | if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1) | |
2817 | break; | |
2818 | msleep(1); | |
2819 | } | |
2820 | } | |
63c3a66f | 2821 | if (tg3_flag(tp, WOL_CAP)) |
a85feb8c GZ |
2822 | tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE | |
2823 | WOL_DRV_STATE_SHUTDOWN | | |
2824 | WOL_DRV_WOL | | |
2825 | WOL_SET_MAGIC_PKT); | |
6921d201 | 2826 | |
05ac4cb7 | 2827 | if (device_should_wake) { |
1da177e4 LT |
2828 | u32 mac_mode; |
2829 | ||
f07e9af3 | 2830 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { |
b4bd2929 MC |
2831 | if (do_low_power && |
2832 | !(tp->phy_flags & TG3_PHYFLG_IS_FET)) { | |
2833 | tg3_phy_auxctl_write(tp, | |
2834 | MII_TG3_AUXCTL_SHDWSEL_PWRCTL, | |
2835 | MII_TG3_AUXCTL_PCTL_WOL_EN | | |
2836 | MII_TG3_AUXCTL_PCTL_100TX_LPWR | | |
2837 | MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC); | |
dd477003 MC |
2838 | udelay(40); |
2839 | } | |
1da177e4 | 2840 | |
f07e9af3 | 2841 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) |
3f7045c1 MC |
2842 | mac_mode = MAC_MODE_PORT_MODE_GMII; |
2843 | else | |
2844 | mac_mode = MAC_MODE_PORT_MODE_MII; | |
1da177e4 | 2845 | |
e8f3f6ca MC |
2846 | mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY; |
2847 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | |
2848 | ASIC_REV_5700) { | |
63c3a66f | 2849 | u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ? |
e8f3f6ca MC |
2850 | SPEED_100 : SPEED_10; |
2851 | if (tg3_5700_link_polarity(tp, speed)) | |
2852 | mac_mode |= MAC_MODE_LINK_POLARITY; | |
2853 | else | |
2854 | mac_mode &= ~MAC_MODE_LINK_POLARITY; | |
2855 | } | |
1da177e4 LT |
2856 | } else { |
2857 | mac_mode = MAC_MODE_PORT_MODE_TBI; | |
2858 | } | |
2859 | ||
63c3a66f | 2860 | if (!tg3_flag(tp, 5750_PLUS)) |
1da177e4 LT |
2861 | tw32(MAC_LED_CTRL, tp->led_ctrl); |
2862 | ||
05ac4cb7 | 2863 | mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE; |
63c3a66f JP |
2864 | if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) && |
2865 | (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE))) | |
05ac4cb7 | 2866 | mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL; |
1da177e4 | 2867 | |
63c3a66f | 2868 | if (tg3_flag(tp, ENABLE_APE)) |
d2394e6b MC |
2869 | mac_mode |= MAC_MODE_APE_TX_EN | |
2870 | MAC_MODE_APE_RX_EN | | |
2871 | MAC_MODE_TDE_ENABLE; | |
3bda1258 | 2872 | |
1da177e4 LT |
2873 | tw32_f(MAC_MODE, mac_mode); |
2874 | udelay(100); | |
2875 | ||
2876 | tw32_f(MAC_RX_MODE, RX_MODE_ENABLE); | |
2877 | udelay(10); | |
2878 | } | |
2879 | ||
63c3a66f | 2880 | if (!tg3_flag(tp, WOL_SPEED_100MB) && |
1da177e4 LT |
2881 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
2882 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) { | |
2883 | u32 base_val; | |
2884 | ||
2885 | base_val = tp->pci_clock_ctrl; | |
2886 | base_val |= (CLOCK_CTRL_RXCLK_DISABLE | | |
2887 | CLOCK_CTRL_TXCLK_DISABLE); | |
2888 | ||
b401e9e2 MC |
2889 | tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK | |
2890 | CLOCK_CTRL_PWRDOWN_PLL133, 40); | |
63c3a66f JP |
2891 | } else if (tg3_flag(tp, 5780_CLASS) || |
2892 | tg3_flag(tp, CPMU_PRESENT) || | |
6ff6f81d | 2893 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
4cf78e4f | 2894 | /* do nothing */ |
63c3a66f | 2895 | } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) { |
1da177e4 LT |
2896 | u32 newbits1, newbits2; |
2897 | ||
2898 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2899 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
2900 | newbits1 = (CLOCK_CTRL_RXCLK_DISABLE | | |
2901 | CLOCK_CTRL_TXCLK_DISABLE | | |
2902 | CLOCK_CTRL_ALTCLK); | |
2903 | newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE; | |
63c3a66f | 2904 | } else if (tg3_flag(tp, 5705_PLUS)) { |
1da177e4 LT |
2905 | newbits1 = CLOCK_CTRL_625_CORE; |
2906 | newbits2 = newbits1 | CLOCK_CTRL_ALTCLK; | |
2907 | } else { | |
2908 | newbits1 = CLOCK_CTRL_ALTCLK; | |
2909 | newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE; | |
2910 | } | |
2911 | ||
b401e9e2 MC |
2912 | tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1, |
2913 | 40); | |
1da177e4 | 2914 | |
b401e9e2 MC |
2915 | tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2, |
2916 | 40); | |
1da177e4 | 2917 | |
63c3a66f | 2918 | if (!tg3_flag(tp, 5705_PLUS)) { |
1da177e4 LT |
2919 | u32 newbits3; |
2920 | ||
2921 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2922 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
2923 | newbits3 = (CLOCK_CTRL_RXCLK_DISABLE | | |
2924 | CLOCK_CTRL_TXCLK_DISABLE | | |
2925 | CLOCK_CTRL_44MHZ_CORE); | |
2926 | } else { | |
2927 | newbits3 = CLOCK_CTRL_44MHZ_CORE; | |
2928 | } | |
2929 | ||
b401e9e2 MC |
2930 | tw32_wait_f(TG3PCI_CLOCK_CTRL, |
2931 | tp->pci_clock_ctrl | newbits3, 40); | |
1da177e4 LT |
2932 | } |
2933 | } | |
2934 | ||
63c3a66f | 2935 | if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF)) |
0a459aac | 2936 | tg3_power_down_phy(tp, do_low_power); |
6921d201 | 2937 | |
1da177e4 LT |
2938 | tg3_frob_aux_power(tp); |
2939 | ||
2940 | /* Workaround for unstable PLL clock */ | |
2941 | if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) || | |
2942 | (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) { | |
2943 | u32 val = tr32(0x7d00); | |
2944 | ||
2945 | val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1); | |
2946 | tw32(0x7d00, val); | |
63c3a66f | 2947 | if (!tg3_flag(tp, ENABLE_ASF)) { |
ec41c7df MC |
2948 | int err; |
2949 | ||
2950 | err = tg3_nvram_lock(tp); | |
1da177e4 | 2951 | tg3_halt_cpu(tp, RX_CPU_BASE); |
ec41c7df MC |
2952 | if (!err) |
2953 | tg3_nvram_unlock(tp); | |
6921d201 | 2954 | } |
1da177e4 LT |
2955 | } |
2956 | ||
bbadf503 MC |
2957 | tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN); |
2958 | ||
c866b7ea RW |
2959 | return 0; |
2960 | } | |
12dac075 | 2961 | |
c866b7ea RW |
2962 | static void tg3_power_down(struct tg3 *tp) |
2963 | { | |
2964 | tg3_power_down_prepare(tp); | |
1da177e4 | 2965 | |
63c3a66f | 2966 | pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE)); |
c866b7ea | 2967 | pci_set_power_state(tp->pdev, PCI_D3hot); |
1da177e4 LT |
2968 | } |
2969 | ||
1da177e4 LT |
2970 | static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex) |
2971 | { | |
2972 | switch (val & MII_TG3_AUX_STAT_SPDMASK) { | |
2973 | case MII_TG3_AUX_STAT_10HALF: | |
2974 | *speed = SPEED_10; | |
2975 | *duplex = DUPLEX_HALF; | |
2976 | break; | |
2977 | ||
2978 | case MII_TG3_AUX_STAT_10FULL: | |
2979 | *speed = SPEED_10; | |
2980 | *duplex = DUPLEX_FULL; | |
2981 | break; | |
2982 | ||
2983 | case MII_TG3_AUX_STAT_100HALF: | |
2984 | *speed = SPEED_100; | |
2985 | *duplex = DUPLEX_HALF; | |
2986 | break; | |
2987 | ||
2988 | case MII_TG3_AUX_STAT_100FULL: | |
2989 | *speed = SPEED_100; | |
2990 | *duplex = DUPLEX_FULL; | |
2991 | break; | |
2992 | ||
2993 | case MII_TG3_AUX_STAT_1000HALF: | |
2994 | *speed = SPEED_1000; | |
2995 | *duplex = DUPLEX_HALF; | |
2996 | break; | |
2997 | ||
2998 | case MII_TG3_AUX_STAT_1000FULL: | |
2999 | *speed = SPEED_1000; | |
3000 | *duplex = DUPLEX_FULL; | |
3001 | break; | |
3002 | ||
3003 | default: | |
f07e9af3 | 3004 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
715116a1 MC |
3005 | *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 : |
3006 | SPEED_10; | |
3007 | *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL : | |
3008 | DUPLEX_HALF; | |
3009 | break; | |
3010 | } | |
1da177e4 LT |
3011 | *speed = SPEED_INVALID; |
3012 | *duplex = DUPLEX_INVALID; | |
3013 | break; | |
855e1111 | 3014 | } |
1da177e4 LT |
3015 | } |
3016 | ||
42b64a45 | 3017 | static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl) |
1da177e4 | 3018 | { |
42b64a45 MC |
3019 | int err = 0; |
3020 | u32 val, new_adv; | |
1da177e4 | 3021 | |
42b64a45 MC |
3022 | new_adv = ADVERTISE_CSMA; |
3023 | if (advertise & ADVERTISED_10baseT_Half) | |
3024 | new_adv |= ADVERTISE_10HALF; | |
3025 | if (advertise & ADVERTISED_10baseT_Full) | |
3026 | new_adv |= ADVERTISE_10FULL; | |
3027 | if (advertise & ADVERTISED_100baseT_Half) | |
3028 | new_adv |= ADVERTISE_100HALF; | |
3029 | if (advertise & ADVERTISED_100baseT_Full) | |
3030 | new_adv |= ADVERTISE_100FULL; | |
1da177e4 | 3031 | |
42b64a45 | 3032 | new_adv |= tg3_advert_flowctrl_1000T(flowctrl); |
1da177e4 | 3033 | |
42b64a45 MC |
3034 | err = tg3_writephy(tp, MII_ADVERTISE, new_adv); |
3035 | if (err) | |
3036 | goto done; | |
ba4d07a8 | 3037 | |
42b64a45 MC |
3038 | if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) |
3039 | goto done; | |
1da177e4 | 3040 | |
42b64a45 MC |
3041 | new_adv = 0; |
3042 | if (advertise & ADVERTISED_1000baseT_Half) | |
221c5637 | 3043 | new_adv |= ADVERTISE_1000HALF; |
42b64a45 | 3044 | if (advertise & ADVERTISED_1000baseT_Full) |
221c5637 | 3045 | new_adv |= ADVERTISE_1000FULL; |
ba4d07a8 | 3046 | |
42b64a45 MC |
3047 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || |
3048 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) | |
221c5637 | 3049 | new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER; |
ba4d07a8 | 3050 | |
221c5637 | 3051 | err = tg3_writephy(tp, MII_CTRL1000, new_adv); |
42b64a45 MC |
3052 | if (err) |
3053 | goto done; | |
1da177e4 | 3054 | |
42b64a45 MC |
3055 | if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) |
3056 | goto done; | |
52b02d04 | 3057 | |
42b64a45 MC |
3058 | tw32(TG3_CPMU_EEE_MODE, |
3059 | tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE); | |
52b02d04 | 3060 | |
42b64a45 MC |
3061 | err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp); |
3062 | if (!err) { | |
3063 | u32 err2; | |
52b02d04 | 3064 | |
21a00ab2 MC |
3065 | switch (GET_ASIC_REV(tp->pci_chip_rev_id)) { |
3066 | case ASIC_REV_5717: | |
3067 | case ASIC_REV_57765: | |
3068 | if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val)) | |
3069 | tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val | | |
3070 | MII_TG3_DSP_CH34TP2_HIBW01); | |
3071 | /* Fall through */ | |
3072 | case ASIC_REV_5719: | |
3073 | val = MII_TG3_DSP_TAP26_ALNOKO | | |
3074 | MII_TG3_DSP_TAP26_RMRXSTO | | |
3075 | MII_TG3_DSP_TAP26_OPCSINPT; | |
3076 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val); | |
3077 | } | |
52b02d04 | 3078 | |
a6b68dab | 3079 | val = 0; |
42b64a45 MC |
3080 | /* Advertise 100-BaseTX EEE ability */ |
3081 | if (advertise & ADVERTISED_100baseT_Full) | |
3082 | val |= MDIO_AN_EEE_ADV_100TX; | |
3083 | /* Advertise 1000-BaseT EEE ability */ | |
3084 | if (advertise & ADVERTISED_1000baseT_Full) | |
3085 | val |= MDIO_AN_EEE_ADV_1000T; | |
3086 | err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val); | |
3087 | ||
3088 | err2 = TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); | |
3089 | if (!err) | |
3090 | err = err2; | |
3091 | } | |
3092 | ||
3093 | done: | |
3094 | return err; | |
3095 | } | |
3096 | ||
3097 | static void tg3_phy_copper_begin(struct tg3 *tp) | |
3098 | { | |
3099 | u32 new_adv; | |
3100 | int i; | |
3101 | ||
3102 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { | |
3103 | new_adv = ADVERTISED_10baseT_Half | | |
3104 | ADVERTISED_10baseT_Full; | |
3105 | if (tg3_flag(tp, WOL_SPEED_100MB)) | |
3106 | new_adv |= ADVERTISED_100baseT_Half | | |
3107 | ADVERTISED_100baseT_Full; | |
3108 | ||
3109 | tg3_phy_autoneg_cfg(tp, new_adv, | |
3110 | FLOW_CTRL_TX | FLOW_CTRL_RX); | |
3111 | } else if (tp->link_config.speed == SPEED_INVALID) { | |
3112 | if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) | |
3113 | tp->link_config.advertising &= | |
3114 | ~(ADVERTISED_1000baseT_Half | | |
3115 | ADVERTISED_1000baseT_Full); | |
3116 | ||
3117 | tg3_phy_autoneg_cfg(tp, tp->link_config.advertising, | |
3118 | tp->link_config.flowctrl); | |
3119 | } else { | |
3120 | /* Asking for a specific link mode. */ | |
3121 | if (tp->link_config.speed == SPEED_1000) { | |
3122 | if (tp->link_config.duplex == DUPLEX_FULL) | |
3123 | new_adv = ADVERTISED_1000baseT_Full; | |
3124 | else | |
3125 | new_adv = ADVERTISED_1000baseT_Half; | |
3126 | } else if (tp->link_config.speed == SPEED_100) { | |
3127 | if (tp->link_config.duplex == DUPLEX_FULL) | |
3128 | new_adv = ADVERTISED_100baseT_Full; | |
3129 | else | |
3130 | new_adv = ADVERTISED_100baseT_Half; | |
3131 | } else { | |
3132 | if (tp->link_config.duplex == DUPLEX_FULL) | |
3133 | new_adv = ADVERTISED_10baseT_Full; | |
3134 | else | |
3135 | new_adv = ADVERTISED_10baseT_Half; | |
52b02d04 | 3136 | } |
52b02d04 | 3137 | |
42b64a45 MC |
3138 | tg3_phy_autoneg_cfg(tp, new_adv, |
3139 | tp->link_config.flowctrl); | |
52b02d04 MC |
3140 | } |
3141 | ||
1da177e4 LT |
3142 | if (tp->link_config.autoneg == AUTONEG_DISABLE && |
3143 | tp->link_config.speed != SPEED_INVALID) { | |
3144 | u32 bmcr, orig_bmcr; | |
3145 | ||
3146 | tp->link_config.active_speed = tp->link_config.speed; | |
3147 | tp->link_config.active_duplex = tp->link_config.duplex; | |
3148 | ||
3149 | bmcr = 0; | |
3150 | switch (tp->link_config.speed) { | |
3151 | default: | |
3152 | case SPEED_10: | |
3153 | break; | |
3154 | ||
3155 | case SPEED_100: | |
3156 | bmcr |= BMCR_SPEED100; | |
3157 | break; | |
3158 | ||
3159 | case SPEED_1000: | |
221c5637 | 3160 | bmcr |= BMCR_SPEED1000; |
1da177e4 | 3161 | break; |
855e1111 | 3162 | } |
1da177e4 LT |
3163 | |
3164 | if (tp->link_config.duplex == DUPLEX_FULL) | |
3165 | bmcr |= BMCR_FULLDPLX; | |
3166 | ||
3167 | if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) && | |
3168 | (bmcr != orig_bmcr)) { | |
3169 | tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK); | |
3170 | for (i = 0; i < 1500; i++) { | |
3171 | u32 tmp; | |
3172 | ||
3173 | udelay(10); | |
3174 | if (tg3_readphy(tp, MII_BMSR, &tmp) || | |
3175 | tg3_readphy(tp, MII_BMSR, &tmp)) | |
3176 | continue; | |
3177 | if (!(tmp & BMSR_LSTATUS)) { | |
3178 | udelay(40); | |
3179 | break; | |
3180 | } | |
3181 | } | |
3182 | tg3_writephy(tp, MII_BMCR, bmcr); | |
3183 | udelay(40); | |
3184 | } | |
3185 | } else { | |
3186 | tg3_writephy(tp, MII_BMCR, | |
3187 | BMCR_ANENABLE | BMCR_ANRESTART); | |
3188 | } | |
3189 | } | |
3190 | ||
3191 | static int tg3_init_5401phy_dsp(struct tg3 *tp) | |
3192 | { | |
3193 | int err; | |
3194 | ||
3195 | /* Turn off tap power management. */ | |
3196 | /* Set Extended packet length bit */ | |
b4bd2929 | 3197 | err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20); |
1da177e4 | 3198 | |
6ee7c0a0 MC |
3199 | err |= tg3_phydsp_write(tp, 0x0012, 0x1804); |
3200 | err |= tg3_phydsp_write(tp, 0x0013, 0x1204); | |
3201 | err |= tg3_phydsp_write(tp, 0x8006, 0x0132); | |
3202 | err |= tg3_phydsp_write(tp, 0x8006, 0x0232); | |
3203 | err |= tg3_phydsp_write(tp, 0x201f, 0x0a20); | |
1da177e4 LT |
3204 | |
3205 | udelay(40); | |
3206 | ||
3207 | return err; | |
3208 | } | |
3209 | ||
3600d918 | 3210 | static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask) |
1da177e4 | 3211 | { |
3600d918 MC |
3212 | u32 adv_reg, all_mask = 0; |
3213 | ||
3214 | if (mask & ADVERTISED_10baseT_Half) | |
3215 | all_mask |= ADVERTISE_10HALF; | |
3216 | if (mask & ADVERTISED_10baseT_Full) | |
3217 | all_mask |= ADVERTISE_10FULL; | |
3218 | if (mask & ADVERTISED_100baseT_Half) | |
3219 | all_mask |= ADVERTISE_100HALF; | |
3220 | if (mask & ADVERTISED_100baseT_Full) | |
3221 | all_mask |= ADVERTISE_100FULL; | |
1da177e4 LT |
3222 | |
3223 | if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg)) | |
3224 | return 0; | |
3225 | ||
1da177e4 LT |
3226 | if ((adv_reg & all_mask) != all_mask) |
3227 | return 0; | |
f07e9af3 | 3228 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { |
1da177e4 LT |
3229 | u32 tg3_ctrl; |
3230 | ||
3600d918 MC |
3231 | all_mask = 0; |
3232 | if (mask & ADVERTISED_1000baseT_Half) | |
3233 | all_mask |= ADVERTISE_1000HALF; | |
3234 | if (mask & ADVERTISED_1000baseT_Full) | |
3235 | all_mask |= ADVERTISE_1000FULL; | |
3236 | ||
221c5637 | 3237 | if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl)) |
1da177e4 LT |
3238 | return 0; |
3239 | ||
1da177e4 LT |
3240 | if ((tg3_ctrl & all_mask) != all_mask) |
3241 | return 0; | |
3242 | } | |
3243 | return 1; | |
3244 | } | |
3245 | ||
ef167e27 MC |
3246 | static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv) |
3247 | { | |
3248 | u32 curadv, reqadv; | |
3249 | ||
3250 | if (tg3_readphy(tp, MII_ADVERTISE, lcladv)) | |
3251 | return 1; | |
3252 | ||
3253 | curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); | |
3254 | reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl); | |
3255 | ||
3256 | if (tp->link_config.active_duplex == DUPLEX_FULL) { | |
3257 | if (curadv != reqadv) | |
3258 | return 0; | |
3259 | ||
63c3a66f | 3260 | if (tg3_flag(tp, PAUSE_AUTONEG)) |
ef167e27 MC |
3261 | tg3_readphy(tp, MII_LPA, rmtadv); |
3262 | } else { | |
3263 | /* Reprogram the advertisement register, even if it | |
3264 | * does not affect the current link. If the link | |
3265 | * gets renegotiated in the future, we can save an | |
3266 | * additional renegotiation cycle by advertising | |
3267 | * it correctly in the first place. | |
3268 | */ | |
3269 | if (curadv != reqadv) { | |
3270 | *lcladv &= ~(ADVERTISE_PAUSE_CAP | | |
3271 | ADVERTISE_PAUSE_ASYM); | |
3272 | tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv); | |
3273 | } | |
3274 | } | |
3275 | ||
3276 | return 1; | |
3277 | } | |
3278 | ||
1da177e4 LT |
3279 | static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset) |
3280 | { | |
3281 | int current_link_up; | |
f833c4c1 | 3282 | u32 bmsr, val; |
ef167e27 | 3283 | u32 lcl_adv, rmt_adv; |
1da177e4 LT |
3284 | u16 current_speed; |
3285 | u8 current_duplex; | |
3286 | int i, err; | |
3287 | ||
3288 | tw32(MAC_EVENT, 0); | |
3289 | ||
3290 | tw32_f(MAC_STATUS, | |
3291 | (MAC_STATUS_SYNC_CHANGED | | |
3292 | MAC_STATUS_CFG_CHANGED | | |
3293 | MAC_STATUS_MI_COMPLETION | | |
3294 | MAC_STATUS_LNKSTATE_CHANGED)); | |
3295 | udelay(40); | |
3296 | ||
8ef21428 MC |
3297 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { |
3298 | tw32_f(MAC_MI_MODE, | |
3299 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
3300 | udelay(80); | |
3301 | } | |
1da177e4 | 3302 | |
b4bd2929 | 3303 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0); |
1da177e4 LT |
3304 | |
3305 | /* Some third-party PHYs need to be reset on link going | |
3306 | * down. | |
3307 | */ | |
3308 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
3309 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
3310 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) && | |
3311 | netif_carrier_ok(tp->dev)) { | |
3312 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
3313 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
3314 | !(bmsr & BMSR_LSTATUS)) | |
3315 | force_reset = 1; | |
3316 | } | |
3317 | if (force_reset) | |
3318 | tg3_phy_reset(tp); | |
3319 | ||
79eb6904 | 3320 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { |
1da177e4 LT |
3321 | tg3_readphy(tp, MII_BMSR, &bmsr); |
3322 | if (tg3_readphy(tp, MII_BMSR, &bmsr) || | |
63c3a66f | 3323 | !tg3_flag(tp, INIT_COMPLETE)) |
1da177e4 LT |
3324 | bmsr = 0; |
3325 | ||
3326 | if (!(bmsr & BMSR_LSTATUS)) { | |
3327 | err = tg3_init_5401phy_dsp(tp); | |
3328 | if (err) | |
3329 | return err; | |
3330 | ||
3331 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
3332 | for (i = 0; i < 1000; i++) { | |
3333 | udelay(10); | |
3334 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
3335 | (bmsr & BMSR_LSTATUS)) { | |
3336 | udelay(40); | |
3337 | break; | |
3338 | } | |
3339 | } | |
3340 | ||
79eb6904 MC |
3341 | if ((tp->phy_id & TG3_PHY_ID_REV_MASK) == |
3342 | TG3_PHY_REV_BCM5401_B0 && | |
1da177e4 LT |
3343 | !(bmsr & BMSR_LSTATUS) && |
3344 | tp->link_config.active_speed == SPEED_1000) { | |
3345 | err = tg3_phy_reset(tp); | |
3346 | if (!err) | |
3347 | err = tg3_init_5401phy_dsp(tp); | |
3348 | if (err) | |
3349 | return err; | |
3350 | } | |
3351 | } | |
3352 | } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
3353 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) { | |
3354 | /* 5701 {A0,B0} CRC bug workaround */ | |
3355 | tg3_writephy(tp, 0x15, 0x0a75); | |
f08aa1a8 MC |
3356 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68); |
3357 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); | |
3358 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68); | |
1da177e4 LT |
3359 | } |
3360 | ||
3361 | /* Clear pending interrupts... */ | |
f833c4c1 MC |
3362 | tg3_readphy(tp, MII_TG3_ISTAT, &val); |
3363 | tg3_readphy(tp, MII_TG3_ISTAT, &val); | |
1da177e4 | 3364 | |
f07e9af3 | 3365 | if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) |
1da177e4 | 3366 | tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG); |
f07e9af3 | 3367 | else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) |
1da177e4 LT |
3368 | tg3_writephy(tp, MII_TG3_IMASK, ~0); |
3369 | ||
3370 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
3371 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
3372 | if (tp->led_ctrl == LED_CTRL_MODE_PHY_1) | |
3373 | tg3_writephy(tp, MII_TG3_EXT_CTRL, | |
3374 | MII_TG3_EXT_CTRL_LNK3_LED_MODE); | |
3375 | else | |
3376 | tg3_writephy(tp, MII_TG3_EXT_CTRL, 0); | |
3377 | } | |
3378 | ||
3379 | current_link_up = 0; | |
3380 | current_speed = SPEED_INVALID; | |
3381 | current_duplex = DUPLEX_INVALID; | |
3382 | ||
f07e9af3 | 3383 | if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) { |
15ee95c3 MC |
3384 | err = tg3_phy_auxctl_read(tp, |
3385 | MII_TG3_AUXCTL_SHDWSEL_MISCTEST, | |
3386 | &val); | |
3387 | if (!err && !(val & (1 << 10))) { | |
b4bd2929 MC |
3388 | tg3_phy_auxctl_write(tp, |
3389 | MII_TG3_AUXCTL_SHDWSEL_MISCTEST, | |
3390 | val | (1 << 10)); | |
1da177e4 LT |
3391 | goto relink; |
3392 | } | |
3393 | } | |
3394 | ||
3395 | bmsr = 0; | |
3396 | for (i = 0; i < 100; i++) { | |
3397 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
3398 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
3399 | (bmsr & BMSR_LSTATUS)) | |
3400 | break; | |
3401 | udelay(40); | |
3402 | } | |
3403 | ||
3404 | if (bmsr & BMSR_LSTATUS) { | |
3405 | u32 aux_stat, bmcr; | |
3406 | ||
3407 | tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat); | |
3408 | for (i = 0; i < 2000; i++) { | |
3409 | udelay(10); | |
3410 | if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) && | |
3411 | aux_stat) | |
3412 | break; | |
3413 | } | |
3414 | ||
3415 | tg3_aux_stat_to_speed_duplex(tp, aux_stat, | |
3416 | ¤t_speed, | |
3417 | ¤t_duplex); | |
3418 | ||
3419 | bmcr = 0; | |
3420 | for (i = 0; i < 200; i++) { | |
3421 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
3422 | if (tg3_readphy(tp, MII_BMCR, &bmcr)) | |
3423 | continue; | |
3424 | if (bmcr && bmcr != 0x7fff) | |
3425 | break; | |
3426 | udelay(10); | |
3427 | } | |
3428 | ||
ef167e27 MC |
3429 | lcl_adv = 0; |
3430 | rmt_adv = 0; | |
1da177e4 | 3431 | |
ef167e27 MC |
3432 | tp->link_config.active_speed = current_speed; |
3433 | tp->link_config.active_duplex = current_duplex; | |
3434 | ||
3435 | if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
3436 | if ((bmcr & BMCR_ANENABLE) && | |
3437 | tg3_copper_is_advertising_all(tp, | |
3438 | tp->link_config.advertising)) { | |
3439 | if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv, | |
3440 | &rmt_adv)) | |
3441 | current_link_up = 1; | |
1da177e4 LT |
3442 | } |
3443 | } else { | |
3444 | if (!(bmcr & BMCR_ANENABLE) && | |
3445 | tp->link_config.speed == current_speed && | |
ef167e27 MC |
3446 | tp->link_config.duplex == current_duplex && |
3447 | tp->link_config.flowctrl == | |
3448 | tp->link_config.active_flowctrl) { | |
1da177e4 | 3449 | current_link_up = 1; |
1da177e4 LT |
3450 | } |
3451 | } | |
3452 | ||
ef167e27 MC |
3453 | if (current_link_up == 1 && |
3454 | tp->link_config.active_duplex == DUPLEX_FULL) | |
3455 | tg3_setup_flow_control(tp, lcl_adv, rmt_adv); | |
1da177e4 LT |
3456 | } |
3457 | ||
1da177e4 | 3458 | relink: |
80096068 | 3459 | if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { |
1da177e4 LT |
3460 | tg3_phy_copper_begin(tp); |
3461 | ||
f833c4c1 | 3462 | tg3_readphy(tp, MII_BMSR, &bmsr); |
06c03c02 MB |
3463 | if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) || |
3464 | (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) | |
1da177e4 LT |
3465 | current_link_up = 1; |
3466 | } | |
3467 | ||
3468 | tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK; | |
3469 | if (current_link_up == 1) { | |
3470 | if (tp->link_config.active_speed == SPEED_100 || | |
3471 | tp->link_config.active_speed == SPEED_10) | |
3472 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; | |
3473 | else | |
3474 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
f07e9af3 | 3475 | } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) |
7f97a4bd MC |
3476 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; |
3477 | else | |
1da177e4 LT |
3478 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; |
3479 | ||
3480 | tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; | |
3481 | if (tp->link_config.active_duplex == DUPLEX_HALF) | |
3482 | tp->mac_mode |= MAC_MODE_HALF_DUPLEX; | |
3483 | ||
1da177e4 | 3484 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) { |
e8f3f6ca MC |
3485 | if (current_link_up == 1 && |
3486 | tg3_5700_link_polarity(tp, tp->link_config.active_speed)) | |
1da177e4 | 3487 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; |
e8f3f6ca MC |
3488 | else |
3489 | tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; | |
1da177e4 LT |
3490 | } |
3491 | ||
3492 | /* ??? Without this setting Netgear GA302T PHY does not | |
3493 | * ??? send/receive packets... | |
3494 | */ | |
79eb6904 | 3495 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 && |
1da177e4 LT |
3496 | tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) { |
3497 | tp->mi_mode |= MAC_MI_MODE_AUTO_POLL; | |
3498 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
3499 | udelay(80); | |
3500 | } | |
3501 | ||
3502 | tw32_f(MAC_MODE, tp->mac_mode); | |
3503 | udelay(40); | |
3504 | ||
52b02d04 MC |
3505 | tg3_phy_eee_adjust(tp, current_link_up); |
3506 | ||
63c3a66f | 3507 | if (tg3_flag(tp, USE_LINKCHG_REG)) { |
1da177e4 LT |
3508 | /* Polled via timer. */ |
3509 | tw32_f(MAC_EVENT, 0); | |
3510 | } else { | |
3511 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
3512 | } | |
3513 | udelay(40); | |
3514 | ||
3515 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 && | |
3516 | current_link_up == 1 && | |
3517 | tp->link_config.active_speed == SPEED_1000 && | |
63c3a66f | 3518 | (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) { |
1da177e4 LT |
3519 | udelay(120); |
3520 | tw32_f(MAC_STATUS, | |
3521 | (MAC_STATUS_SYNC_CHANGED | | |
3522 | MAC_STATUS_CFG_CHANGED)); | |
3523 | udelay(40); | |
3524 | tg3_write_mem(tp, | |
3525 | NIC_SRAM_FIRMWARE_MBOX, | |
3526 | NIC_SRAM_FIRMWARE_MBOX_MAGIC2); | |
3527 | } | |
3528 | ||
5e7dfd0f | 3529 | /* Prevent send BD corruption. */ |
63c3a66f | 3530 | if (tg3_flag(tp, CLKREQ_BUG)) { |
5e7dfd0f MC |
3531 | u16 oldlnkctl, newlnkctl; |
3532 | ||
3533 | pci_read_config_word(tp->pdev, | |
708ebb3a | 3534 | pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL, |
5e7dfd0f MC |
3535 | &oldlnkctl); |
3536 | if (tp->link_config.active_speed == SPEED_100 || | |
3537 | tp->link_config.active_speed == SPEED_10) | |
3538 | newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN; | |
3539 | else | |
3540 | newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN; | |
3541 | if (newlnkctl != oldlnkctl) | |
3542 | pci_write_config_word(tp->pdev, | |
708ebb3a | 3543 | pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL, |
5e7dfd0f MC |
3544 | newlnkctl); |
3545 | } | |
3546 | ||
1da177e4 LT |
3547 | if (current_link_up != netif_carrier_ok(tp->dev)) { |
3548 | if (current_link_up) | |
3549 | netif_carrier_on(tp->dev); | |
3550 | else | |
3551 | netif_carrier_off(tp->dev); | |
3552 | tg3_link_report(tp); | |
3553 | } | |
3554 | ||
3555 | return 0; | |
3556 | } | |
3557 | ||
3558 | struct tg3_fiber_aneginfo { | |
3559 | int state; | |
3560 | #define ANEG_STATE_UNKNOWN 0 | |
3561 | #define ANEG_STATE_AN_ENABLE 1 | |
3562 | #define ANEG_STATE_RESTART_INIT 2 | |
3563 | #define ANEG_STATE_RESTART 3 | |
3564 | #define ANEG_STATE_DISABLE_LINK_OK 4 | |
3565 | #define ANEG_STATE_ABILITY_DETECT_INIT 5 | |
3566 | #define ANEG_STATE_ABILITY_DETECT 6 | |
3567 | #define ANEG_STATE_ACK_DETECT_INIT 7 | |
3568 | #define ANEG_STATE_ACK_DETECT 8 | |
3569 | #define ANEG_STATE_COMPLETE_ACK_INIT 9 | |
3570 | #define ANEG_STATE_COMPLETE_ACK 10 | |
3571 | #define ANEG_STATE_IDLE_DETECT_INIT 11 | |
3572 | #define ANEG_STATE_IDLE_DETECT 12 | |
3573 | #define ANEG_STATE_LINK_OK 13 | |
3574 | #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14 | |
3575 | #define ANEG_STATE_NEXT_PAGE_WAIT 15 | |
3576 | ||
3577 | u32 flags; | |
3578 | #define MR_AN_ENABLE 0x00000001 | |
3579 | #define MR_RESTART_AN 0x00000002 | |
3580 | #define MR_AN_COMPLETE 0x00000004 | |
3581 | #define MR_PAGE_RX 0x00000008 | |
3582 | #define MR_NP_LOADED 0x00000010 | |
3583 | #define MR_TOGGLE_TX 0x00000020 | |
3584 | #define MR_LP_ADV_FULL_DUPLEX 0x00000040 | |
3585 | #define MR_LP_ADV_HALF_DUPLEX 0x00000080 | |
3586 | #define MR_LP_ADV_SYM_PAUSE 0x00000100 | |
3587 | #define MR_LP_ADV_ASYM_PAUSE 0x00000200 | |
3588 | #define MR_LP_ADV_REMOTE_FAULT1 0x00000400 | |
3589 | #define MR_LP_ADV_REMOTE_FAULT2 0x00000800 | |
3590 | #define MR_LP_ADV_NEXT_PAGE 0x00001000 | |
3591 | #define MR_TOGGLE_RX 0x00002000 | |
3592 | #define MR_NP_RX 0x00004000 | |
3593 | ||
3594 | #define MR_LINK_OK 0x80000000 | |
3595 | ||
3596 | unsigned long link_time, cur_time; | |
3597 | ||
3598 | u32 ability_match_cfg; | |
3599 | int ability_match_count; | |
3600 | ||
3601 | char ability_match, idle_match, ack_match; | |
3602 | ||
3603 | u32 txconfig, rxconfig; | |
3604 | #define ANEG_CFG_NP 0x00000080 | |
3605 | #define ANEG_CFG_ACK 0x00000040 | |
3606 | #define ANEG_CFG_RF2 0x00000020 | |
3607 | #define ANEG_CFG_RF1 0x00000010 | |
3608 | #define ANEG_CFG_PS2 0x00000001 | |
3609 | #define ANEG_CFG_PS1 0x00008000 | |
3610 | #define ANEG_CFG_HD 0x00004000 | |
3611 | #define ANEG_CFG_FD 0x00002000 | |
3612 | #define ANEG_CFG_INVAL 0x00001f06 | |
3613 | ||
3614 | }; | |
3615 | #define ANEG_OK 0 | |
3616 | #define ANEG_DONE 1 | |
3617 | #define ANEG_TIMER_ENAB 2 | |
3618 | #define ANEG_FAILED -1 | |
3619 | ||
3620 | #define ANEG_STATE_SETTLE_TIME 10000 | |
3621 | ||
3622 | static int tg3_fiber_aneg_smachine(struct tg3 *tp, | |
3623 | struct tg3_fiber_aneginfo *ap) | |
3624 | { | |
5be73b47 | 3625 | u16 flowctrl; |
1da177e4 LT |
3626 | unsigned long delta; |
3627 | u32 rx_cfg_reg; | |
3628 | int ret; | |
3629 | ||
3630 | if (ap->state == ANEG_STATE_UNKNOWN) { | |
3631 | ap->rxconfig = 0; | |
3632 | ap->link_time = 0; | |
3633 | ap->cur_time = 0; | |
3634 | ap->ability_match_cfg = 0; | |
3635 | ap->ability_match_count = 0; | |
3636 | ap->ability_match = 0; | |
3637 | ap->idle_match = 0; | |
3638 | ap->ack_match = 0; | |
3639 | } | |
3640 | ap->cur_time++; | |
3641 | ||
3642 | if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) { | |
3643 | rx_cfg_reg = tr32(MAC_RX_AUTO_NEG); | |
3644 | ||
3645 | if (rx_cfg_reg != ap->ability_match_cfg) { | |
3646 | ap->ability_match_cfg = rx_cfg_reg; | |
3647 | ap->ability_match = 0; | |
3648 | ap->ability_match_count = 0; | |
3649 | } else { | |
3650 | if (++ap->ability_match_count > 1) { | |
3651 | ap->ability_match = 1; | |
3652 | ap->ability_match_cfg = rx_cfg_reg; | |
3653 | } | |
3654 | } | |
3655 | if (rx_cfg_reg & ANEG_CFG_ACK) | |
3656 | ap->ack_match = 1; | |
3657 | else | |
3658 | ap->ack_match = 0; | |
3659 | ||
3660 | ap->idle_match = 0; | |
3661 | } else { | |
3662 | ap->idle_match = 1; | |
3663 | ap->ability_match_cfg = 0; | |
3664 | ap->ability_match_count = 0; | |
3665 | ap->ability_match = 0; | |
3666 | ap->ack_match = 0; | |
3667 | ||
3668 | rx_cfg_reg = 0; | |
3669 | } | |
3670 | ||
3671 | ap->rxconfig = rx_cfg_reg; | |
3672 | ret = ANEG_OK; | |
3673 | ||
33f401ae | 3674 | switch (ap->state) { |
1da177e4 LT |
3675 | case ANEG_STATE_UNKNOWN: |
3676 | if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN)) | |
3677 | ap->state = ANEG_STATE_AN_ENABLE; | |
3678 | ||
3679 | /* fallthru */ | |
3680 | case ANEG_STATE_AN_ENABLE: | |
3681 | ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX); | |
3682 | if (ap->flags & MR_AN_ENABLE) { | |
3683 | ap->link_time = 0; | |
3684 | ap->cur_time = 0; | |
3685 | ap->ability_match_cfg = 0; | |
3686 | ap->ability_match_count = 0; | |
3687 | ap->ability_match = 0; | |
3688 | ap->idle_match = 0; | |
3689 | ap->ack_match = 0; | |
3690 | ||
3691 | ap->state = ANEG_STATE_RESTART_INIT; | |
3692 | } else { | |
3693 | ap->state = ANEG_STATE_DISABLE_LINK_OK; | |
3694 | } | |
3695 | break; | |
3696 | ||
3697 | case ANEG_STATE_RESTART_INIT: | |
3698 | ap->link_time = ap->cur_time; | |
3699 | ap->flags &= ~(MR_NP_LOADED); | |
3700 | ap->txconfig = 0; | |
3701 | tw32(MAC_TX_AUTO_NEG, 0); | |
3702 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
3703 | tw32_f(MAC_MODE, tp->mac_mode); | |
3704 | udelay(40); | |
3705 | ||
3706 | ret = ANEG_TIMER_ENAB; | |
3707 | ap->state = ANEG_STATE_RESTART; | |
3708 | ||
3709 | /* fallthru */ | |
3710 | case ANEG_STATE_RESTART: | |
3711 | delta = ap->cur_time - ap->link_time; | |
859a5887 | 3712 | if (delta > ANEG_STATE_SETTLE_TIME) |
1da177e4 | 3713 | ap->state = ANEG_STATE_ABILITY_DETECT_INIT; |
859a5887 | 3714 | else |
1da177e4 | 3715 | ret = ANEG_TIMER_ENAB; |
1da177e4 LT |
3716 | break; |
3717 | ||
3718 | case ANEG_STATE_DISABLE_LINK_OK: | |
3719 | ret = ANEG_DONE; | |
3720 | break; | |
3721 | ||
3722 | case ANEG_STATE_ABILITY_DETECT_INIT: | |
3723 | ap->flags &= ~(MR_TOGGLE_TX); | |
5be73b47 MC |
3724 | ap->txconfig = ANEG_CFG_FD; |
3725 | flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); | |
3726 | if (flowctrl & ADVERTISE_1000XPAUSE) | |
3727 | ap->txconfig |= ANEG_CFG_PS1; | |
3728 | if (flowctrl & ADVERTISE_1000XPSE_ASYM) | |
3729 | ap->txconfig |= ANEG_CFG_PS2; | |
1da177e4 LT |
3730 | tw32(MAC_TX_AUTO_NEG, ap->txconfig); |
3731 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
3732 | tw32_f(MAC_MODE, tp->mac_mode); | |
3733 | udelay(40); | |
3734 | ||
3735 | ap->state = ANEG_STATE_ABILITY_DETECT; | |
3736 | break; | |
3737 | ||
3738 | case ANEG_STATE_ABILITY_DETECT: | |
859a5887 | 3739 | if (ap->ability_match != 0 && ap->rxconfig != 0) |
1da177e4 | 3740 | ap->state = ANEG_STATE_ACK_DETECT_INIT; |
1da177e4 LT |
3741 | break; |
3742 | ||
3743 | case ANEG_STATE_ACK_DETECT_INIT: | |
3744 | ap->txconfig |= ANEG_CFG_ACK; | |
3745 | tw32(MAC_TX_AUTO_NEG, ap->txconfig); | |
3746 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
3747 | tw32_f(MAC_MODE, tp->mac_mode); | |
3748 | udelay(40); | |
3749 | ||
3750 | ap->state = ANEG_STATE_ACK_DETECT; | |
3751 | ||
3752 | /* fallthru */ | |
3753 | case ANEG_STATE_ACK_DETECT: | |
3754 | if (ap->ack_match != 0) { | |
3755 | if ((ap->rxconfig & ~ANEG_CFG_ACK) == | |
3756 | (ap->ability_match_cfg & ~ANEG_CFG_ACK)) { | |
3757 | ap->state = ANEG_STATE_COMPLETE_ACK_INIT; | |
3758 | } else { | |
3759 | ap->state = ANEG_STATE_AN_ENABLE; | |
3760 | } | |
3761 | } else if (ap->ability_match != 0 && | |
3762 | ap->rxconfig == 0) { | |
3763 | ap->state = ANEG_STATE_AN_ENABLE; | |
3764 | } | |
3765 | break; | |
3766 | ||
3767 | case ANEG_STATE_COMPLETE_ACK_INIT: | |
3768 | if (ap->rxconfig & ANEG_CFG_INVAL) { | |
3769 | ret = ANEG_FAILED; | |
3770 | break; | |
3771 | } | |
3772 | ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX | | |
3773 | MR_LP_ADV_HALF_DUPLEX | | |
3774 | MR_LP_ADV_SYM_PAUSE | | |
3775 | MR_LP_ADV_ASYM_PAUSE | | |
3776 | MR_LP_ADV_REMOTE_FAULT1 | | |
3777 | MR_LP_ADV_REMOTE_FAULT2 | | |
3778 | MR_LP_ADV_NEXT_PAGE | | |
3779 | MR_TOGGLE_RX | | |
3780 | MR_NP_RX); | |
3781 | if (ap->rxconfig & ANEG_CFG_FD) | |
3782 | ap->flags |= MR_LP_ADV_FULL_DUPLEX; | |
3783 | if (ap->rxconfig & ANEG_CFG_HD) | |
3784 | ap->flags |= MR_LP_ADV_HALF_DUPLEX; | |
3785 | if (ap->rxconfig & ANEG_CFG_PS1) | |
3786 | ap->flags |= MR_LP_ADV_SYM_PAUSE; | |
3787 | if (ap->rxconfig & ANEG_CFG_PS2) | |
3788 | ap->flags |= MR_LP_ADV_ASYM_PAUSE; | |
3789 | if (ap->rxconfig & ANEG_CFG_RF1) | |
3790 | ap->flags |= MR_LP_ADV_REMOTE_FAULT1; | |
3791 | if (ap->rxconfig & ANEG_CFG_RF2) | |
3792 | ap->flags |= MR_LP_ADV_REMOTE_FAULT2; | |
3793 | if (ap->rxconfig & ANEG_CFG_NP) | |
3794 | ap->flags |= MR_LP_ADV_NEXT_PAGE; | |
3795 | ||
3796 | ap->link_time = ap->cur_time; | |
3797 | ||
3798 | ap->flags ^= (MR_TOGGLE_TX); | |
3799 | if (ap->rxconfig & 0x0008) | |
3800 | ap->flags |= MR_TOGGLE_RX; | |
3801 | if (ap->rxconfig & ANEG_CFG_NP) | |
3802 | ap->flags |= MR_NP_RX; | |
3803 | ap->flags |= MR_PAGE_RX; | |
3804 | ||
3805 | ap->state = ANEG_STATE_COMPLETE_ACK; | |
3806 | ret = ANEG_TIMER_ENAB; | |
3807 | break; | |
3808 | ||
3809 | case ANEG_STATE_COMPLETE_ACK: | |
3810 | if (ap->ability_match != 0 && | |
3811 | ap->rxconfig == 0) { | |
3812 | ap->state = ANEG_STATE_AN_ENABLE; | |
3813 | break; | |
3814 | } | |
3815 | delta = ap->cur_time - ap->link_time; | |
3816 | if (delta > ANEG_STATE_SETTLE_TIME) { | |
3817 | if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) { | |
3818 | ap->state = ANEG_STATE_IDLE_DETECT_INIT; | |
3819 | } else { | |
3820 | if ((ap->txconfig & ANEG_CFG_NP) == 0 && | |
3821 | !(ap->flags & MR_NP_RX)) { | |
3822 | ap->state = ANEG_STATE_IDLE_DETECT_INIT; | |
3823 | } else { | |
3824 | ret = ANEG_FAILED; | |
3825 | } | |
3826 | } | |
3827 | } | |
3828 | break; | |
3829 | ||
3830 | case ANEG_STATE_IDLE_DETECT_INIT: | |
3831 | ap->link_time = ap->cur_time; | |
3832 | tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; | |
3833 | tw32_f(MAC_MODE, tp->mac_mode); | |
3834 | udelay(40); | |
3835 | ||
3836 | ap->state = ANEG_STATE_IDLE_DETECT; | |
3837 | ret = ANEG_TIMER_ENAB; | |
3838 | break; | |
3839 | ||
3840 | case ANEG_STATE_IDLE_DETECT: | |
3841 | if (ap->ability_match != 0 && | |
3842 | ap->rxconfig == 0) { | |
3843 | ap->state = ANEG_STATE_AN_ENABLE; | |
3844 | break; | |
3845 | } | |
3846 | delta = ap->cur_time - ap->link_time; | |
3847 | if (delta > ANEG_STATE_SETTLE_TIME) { | |
3848 | /* XXX another gem from the Broadcom driver :( */ | |
3849 | ap->state = ANEG_STATE_LINK_OK; | |
3850 | } | |
3851 | break; | |
3852 | ||
3853 | case ANEG_STATE_LINK_OK: | |
3854 | ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK); | |
3855 | ret = ANEG_DONE; | |
3856 | break; | |
3857 | ||
3858 | case ANEG_STATE_NEXT_PAGE_WAIT_INIT: | |
3859 | /* ??? unimplemented */ | |
3860 | break; | |
3861 | ||
3862 | case ANEG_STATE_NEXT_PAGE_WAIT: | |
3863 | /* ??? unimplemented */ | |
3864 | break; | |
3865 | ||
3866 | default: | |
3867 | ret = ANEG_FAILED; | |
3868 | break; | |
855e1111 | 3869 | } |
1da177e4 LT |
3870 | |
3871 | return ret; | |
3872 | } | |
3873 | ||
5be73b47 | 3874 | static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags) |
1da177e4 LT |
3875 | { |
3876 | int res = 0; | |
3877 | struct tg3_fiber_aneginfo aninfo; | |
3878 | int status = ANEG_FAILED; | |
3879 | unsigned int tick; | |
3880 | u32 tmp; | |
3881 | ||
3882 | tw32_f(MAC_TX_AUTO_NEG, 0); | |
3883 | ||
3884 | tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK; | |
3885 | tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII); | |
3886 | udelay(40); | |
3887 | ||
3888 | tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS); | |
3889 | udelay(40); | |
3890 | ||
3891 | memset(&aninfo, 0, sizeof(aninfo)); | |
3892 | aninfo.flags |= MR_AN_ENABLE; | |
3893 | aninfo.state = ANEG_STATE_UNKNOWN; | |
3894 | aninfo.cur_time = 0; | |
3895 | tick = 0; | |
3896 | while (++tick < 195000) { | |
3897 | status = tg3_fiber_aneg_smachine(tp, &aninfo); | |
3898 | if (status == ANEG_DONE || status == ANEG_FAILED) | |
3899 | break; | |
3900 | ||
3901 | udelay(1); | |
3902 | } | |
3903 | ||
3904 | tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; | |
3905 | tw32_f(MAC_MODE, tp->mac_mode); | |
3906 | udelay(40); | |
3907 | ||
5be73b47 MC |
3908 | *txflags = aninfo.txconfig; |
3909 | *rxflags = aninfo.flags; | |
1da177e4 LT |
3910 | |
3911 | if (status == ANEG_DONE && | |
3912 | (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK | | |
3913 | MR_LP_ADV_FULL_DUPLEX))) | |
3914 | res = 1; | |
3915 | ||
3916 | return res; | |
3917 | } | |
3918 | ||
3919 | static void tg3_init_bcm8002(struct tg3 *tp) | |
3920 | { | |
3921 | u32 mac_status = tr32(MAC_STATUS); | |
3922 | int i; | |
3923 | ||
3924 | /* Reset when initting first time or we have a link. */ | |
63c3a66f | 3925 | if (tg3_flag(tp, INIT_COMPLETE) && |
1da177e4 LT |
3926 | !(mac_status & MAC_STATUS_PCS_SYNCED)) |
3927 | return; | |
3928 | ||
3929 | /* Set PLL lock range. */ | |
3930 | tg3_writephy(tp, 0x16, 0x8007); | |
3931 | ||
3932 | /* SW reset */ | |
3933 | tg3_writephy(tp, MII_BMCR, BMCR_RESET); | |
3934 | ||
3935 | /* Wait for reset to complete. */ | |
3936 | /* XXX schedule_timeout() ... */ | |
3937 | for (i = 0; i < 500; i++) | |
3938 | udelay(10); | |
3939 | ||
3940 | /* Config mode; select PMA/Ch 1 regs. */ | |
3941 | tg3_writephy(tp, 0x10, 0x8411); | |
3942 | ||
3943 | /* Enable auto-lock and comdet, select txclk for tx. */ | |
3944 | tg3_writephy(tp, 0x11, 0x0a10); | |
3945 | ||
3946 | tg3_writephy(tp, 0x18, 0x00a0); | |
3947 | tg3_writephy(tp, 0x16, 0x41ff); | |
3948 | ||
3949 | /* Assert and deassert POR. */ | |
3950 | tg3_writephy(tp, 0x13, 0x0400); | |
3951 | udelay(40); | |
3952 | tg3_writephy(tp, 0x13, 0x0000); | |
3953 | ||
3954 | tg3_writephy(tp, 0x11, 0x0a50); | |
3955 | udelay(40); | |
3956 | tg3_writephy(tp, 0x11, 0x0a10); | |
3957 | ||
3958 | /* Wait for signal to stabilize */ | |
3959 | /* XXX schedule_timeout() ... */ | |
3960 | for (i = 0; i < 15000; i++) | |
3961 | udelay(10); | |
3962 | ||
3963 | /* Deselect the channel register so we can read the PHYID | |
3964 | * later. | |
3965 | */ | |
3966 | tg3_writephy(tp, 0x10, 0x8011); | |
3967 | } | |
3968 | ||
3969 | static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status) | |
3970 | { | |
82cd3d11 | 3971 | u16 flowctrl; |
1da177e4 LT |
3972 | u32 sg_dig_ctrl, sg_dig_status; |
3973 | u32 serdes_cfg, expected_sg_dig_ctrl; | |
3974 | int workaround, port_a; | |
3975 | int current_link_up; | |
3976 | ||
3977 | serdes_cfg = 0; | |
3978 | expected_sg_dig_ctrl = 0; | |
3979 | workaround = 0; | |
3980 | port_a = 1; | |
3981 | current_link_up = 0; | |
3982 | ||
3983 | if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 && | |
3984 | tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) { | |
3985 | workaround = 1; | |
3986 | if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) | |
3987 | port_a = 0; | |
3988 | ||
3989 | /* preserve bits 0-11,13,14 for signal pre-emphasis */ | |
3990 | /* preserve bits 20-23 for voltage regulator */ | |
3991 | serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff; | |
3992 | } | |
3993 | ||
3994 | sg_dig_ctrl = tr32(SG_DIG_CTRL); | |
3995 | ||
3996 | if (tp->link_config.autoneg != AUTONEG_ENABLE) { | |
c98f6e3b | 3997 | if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) { |
1da177e4 LT |
3998 | if (workaround) { |
3999 | u32 val = serdes_cfg; | |
4000 | ||
4001 | if (port_a) | |
4002 | val |= 0xc010000; | |
4003 | else | |
4004 | val |= 0x4010000; | |
4005 | tw32_f(MAC_SERDES_CFG, val); | |
4006 | } | |
c98f6e3b MC |
4007 | |
4008 | tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP); | |
1da177e4 LT |
4009 | } |
4010 | if (mac_status & MAC_STATUS_PCS_SYNCED) { | |
4011 | tg3_setup_flow_control(tp, 0, 0); | |
4012 | current_link_up = 1; | |
4013 | } | |
4014 | goto out; | |
4015 | } | |
4016 | ||
4017 | /* Want auto-negotiation. */ | |
c98f6e3b | 4018 | expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP; |
1da177e4 | 4019 | |
82cd3d11 MC |
4020 | flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); |
4021 | if (flowctrl & ADVERTISE_1000XPAUSE) | |
4022 | expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP; | |
4023 | if (flowctrl & ADVERTISE_1000XPSE_ASYM) | |
4024 | expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE; | |
1da177e4 LT |
4025 | |
4026 | if (sg_dig_ctrl != expected_sg_dig_ctrl) { | |
f07e9af3 | 4027 | if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) && |
3d3ebe74 MC |
4028 | tp->serdes_counter && |
4029 | ((mac_status & (MAC_STATUS_PCS_SYNCED | | |
4030 | MAC_STATUS_RCVD_CFG)) == | |
4031 | MAC_STATUS_PCS_SYNCED)) { | |
4032 | tp->serdes_counter--; | |
4033 | current_link_up = 1; | |
4034 | goto out; | |
4035 | } | |
4036 | restart_autoneg: | |
1da177e4 LT |
4037 | if (workaround) |
4038 | tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000); | |
c98f6e3b | 4039 | tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET); |
1da177e4 LT |
4040 | udelay(5); |
4041 | tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl); | |
4042 | ||
3d3ebe74 | 4043 | tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; |
f07e9af3 | 4044 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
1da177e4 LT |
4045 | } else if (mac_status & (MAC_STATUS_PCS_SYNCED | |
4046 | MAC_STATUS_SIGNAL_DET)) { | |
3d3ebe74 | 4047 | sg_dig_status = tr32(SG_DIG_STATUS); |
1da177e4 LT |
4048 | mac_status = tr32(MAC_STATUS); |
4049 | ||
c98f6e3b | 4050 | if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) && |
1da177e4 | 4051 | (mac_status & MAC_STATUS_PCS_SYNCED)) { |
82cd3d11 MC |
4052 | u32 local_adv = 0, remote_adv = 0; |
4053 | ||
4054 | if (sg_dig_ctrl & SG_DIG_PAUSE_CAP) | |
4055 | local_adv |= ADVERTISE_1000XPAUSE; | |
4056 | if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE) | |
4057 | local_adv |= ADVERTISE_1000XPSE_ASYM; | |
1da177e4 | 4058 | |
c98f6e3b | 4059 | if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE) |
82cd3d11 | 4060 | remote_adv |= LPA_1000XPAUSE; |
c98f6e3b | 4061 | if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE) |
82cd3d11 | 4062 | remote_adv |= LPA_1000XPAUSE_ASYM; |
1da177e4 LT |
4063 | |
4064 | tg3_setup_flow_control(tp, local_adv, remote_adv); | |
4065 | current_link_up = 1; | |
3d3ebe74 | 4066 | tp->serdes_counter = 0; |
f07e9af3 | 4067 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
c98f6e3b | 4068 | } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) { |
3d3ebe74 MC |
4069 | if (tp->serdes_counter) |
4070 | tp->serdes_counter--; | |
1da177e4 LT |
4071 | else { |
4072 | if (workaround) { | |
4073 | u32 val = serdes_cfg; | |
4074 | ||
4075 | if (port_a) | |
4076 | val |= 0xc010000; | |
4077 | else | |
4078 | val |= 0x4010000; | |
4079 | ||
4080 | tw32_f(MAC_SERDES_CFG, val); | |
4081 | } | |
4082 | ||
c98f6e3b | 4083 | tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP); |
1da177e4 LT |
4084 | udelay(40); |
4085 | ||
4086 | /* Link parallel detection - link is up */ | |
4087 | /* only if we have PCS_SYNC and not */ | |
4088 | /* receiving config code words */ | |
4089 | mac_status = tr32(MAC_STATUS); | |
4090 | if ((mac_status & MAC_STATUS_PCS_SYNCED) && | |
4091 | !(mac_status & MAC_STATUS_RCVD_CFG)) { | |
4092 | tg3_setup_flow_control(tp, 0, 0); | |
4093 | current_link_up = 1; | |
f07e9af3 MC |
4094 | tp->phy_flags |= |
4095 | TG3_PHYFLG_PARALLEL_DETECT; | |
3d3ebe74 MC |
4096 | tp->serdes_counter = |
4097 | SERDES_PARALLEL_DET_TIMEOUT; | |
4098 | } else | |
4099 | goto restart_autoneg; | |
1da177e4 LT |
4100 | } |
4101 | } | |
3d3ebe74 MC |
4102 | } else { |
4103 | tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; | |
f07e9af3 | 4104 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
1da177e4 LT |
4105 | } |
4106 | ||
4107 | out: | |
4108 | return current_link_up; | |
4109 | } | |
4110 | ||
4111 | static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status) | |
4112 | { | |
4113 | int current_link_up = 0; | |
4114 | ||
5cf64b8a | 4115 | if (!(mac_status & MAC_STATUS_PCS_SYNCED)) |
1da177e4 | 4116 | goto out; |
1da177e4 LT |
4117 | |
4118 | if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
5be73b47 | 4119 | u32 txflags, rxflags; |
1da177e4 | 4120 | int i; |
6aa20a22 | 4121 | |
5be73b47 MC |
4122 | if (fiber_autoneg(tp, &txflags, &rxflags)) { |
4123 | u32 local_adv = 0, remote_adv = 0; | |
1da177e4 | 4124 | |
5be73b47 MC |
4125 | if (txflags & ANEG_CFG_PS1) |
4126 | local_adv |= ADVERTISE_1000XPAUSE; | |
4127 | if (txflags & ANEG_CFG_PS2) | |
4128 | local_adv |= ADVERTISE_1000XPSE_ASYM; | |
4129 | ||
4130 | if (rxflags & MR_LP_ADV_SYM_PAUSE) | |
4131 | remote_adv |= LPA_1000XPAUSE; | |
4132 | if (rxflags & MR_LP_ADV_ASYM_PAUSE) | |
4133 | remote_adv |= LPA_1000XPAUSE_ASYM; | |
1da177e4 LT |
4134 | |
4135 | tg3_setup_flow_control(tp, local_adv, remote_adv); | |
4136 | ||
1da177e4 LT |
4137 | current_link_up = 1; |
4138 | } | |
4139 | for (i = 0; i < 30; i++) { | |
4140 | udelay(20); | |
4141 | tw32_f(MAC_STATUS, | |
4142 | (MAC_STATUS_SYNC_CHANGED | | |
4143 | MAC_STATUS_CFG_CHANGED)); | |
4144 | udelay(40); | |
4145 | if ((tr32(MAC_STATUS) & | |
4146 | (MAC_STATUS_SYNC_CHANGED | | |
4147 | MAC_STATUS_CFG_CHANGED)) == 0) | |
4148 | break; | |
4149 | } | |
4150 | ||
4151 | mac_status = tr32(MAC_STATUS); | |
4152 | if (current_link_up == 0 && | |
4153 | (mac_status & MAC_STATUS_PCS_SYNCED) && | |
4154 | !(mac_status & MAC_STATUS_RCVD_CFG)) | |
4155 | current_link_up = 1; | |
4156 | } else { | |
5be73b47 MC |
4157 | tg3_setup_flow_control(tp, 0, 0); |
4158 | ||
1da177e4 LT |
4159 | /* Forcing 1000FD link up. */ |
4160 | current_link_up = 1; | |
1da177e4 LT |
4161 | |
4162 | tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS)); | |
4163 | udelay(40); | |
e8f3f6ca MC |
4164 | |
4165 | tw32_f(MAC_MODE, tp->mac_mode); | |
4166 | udelay(40); | |
1da177e4 LT |
4167 | } |
4168 | ||
4169 | out: | |
4170 | return current_link_up; | |
4171 | } | |
4172 | ||
4173 | static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset) | |
4174 | { | |
4175 | u32 orig_pause_cfg; | |
4176 | u16 orig_active_speed; | |
4177 | u8 orig_active_duplex; | |
4178 | u32 mac_status; | |
4179 | int current_link_up; | |
4180 | int i; | |
4181 | ||
8d018621 | 4182 | orig_pause_cfg = tp->link_config.active_flowctrl; |
1da177e4 LT |
4183 | orig_active_speed = tp->link_config.active_speed; |
4184 | orig_active_duplex = tp->link_config.active_duplex; | |
4185 | ||
63c3a66f | 4186 | if (!tg3_flag(tp, HW_AUTONEG) && |
1da177e4 | 4187 | netif_carrier_ok(tp->dev) && |
63c3a66f | 4188 | tg3_flag(tp, INIT_COMPLETE)) { |
1da177e4 LT |
4189 | mac_status = tr32(MAC_STATUS); |
4190 | mac_status &= (MAC_STATUS_PCS_SYNCED | | |
4191 | MAC_STATUS_SIGNAL_DET | | |
4192 | MAC_STATUS_CFG_CHANGED | | |
4193 | MAC_STATUS_RCVD_CFG); | |
4194 | if (mac_status == (MAC_STATUS_PCS_SYNCED | | |
4195 | MAC_STATUS_SIGNAL_DET)) { | |
4196 | tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED | | |
4197 | MAC_STATUS_CFG_CHANGED)); | |
4198 | return 0; | |
4199 | } | |
4200 | } | |
4201 | ||
4202 | tw32_f(MAC_TX_AUTO_NEG, 0); | |
4203 | ||
4204 | tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); | |
4205 | tp->mac_mode |= MAC_MODE_PORT_MODE_TBI; | |
4206 | tw32_f(MAC_MODE, tp->mac_mode); | |
4207 | udelay(40); | |
4208 | ||
79eb6904 | 4209 | if (tp->phy_id == TG3_PHY_ID_BCM8002) |
1da177e4 LT |
4210 | tg3_init_bcm8002(tp); |
4211 | ||
4212 | /* Enable link change event even when serdes polling. */ | |
4213 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
4214 | udelay(40); | |
4215 | ||
4216 | current_link_up = 0; | |
4217 | mac_status = tr32(MAC_STATUS); | |
4218 | ||
63c3a66f | 4219 | if (tg3_flag(tp, HW_AUTONEG)) |
1da177e4 LT |
4220 | current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status); |
4221 | else | |
4222 | current_link_up = tg3_setup_fiber_by_hand(tp, mac_status); | |
4223 | ||
898a56f8 | 4224 | tp->napi[0].hw_status->status = |
1da177e4 | 4225 | (SD_STATUS_UPDATED | |
898a56f8 | 4226 | (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG)); |
1da177e4 LT |
4227 | |
4228 | for (i = 0; i < 100; i++) { | |
4229 | tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED | | |
4230 | MAC_STATUS_CFG_CHANGED)); | |
4231 | udelay(5); | |
4232 | if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED | | |
3d3ebe74 MC |
4233 | MAC_STATUS_CFG_CHANGED | |
4234 | MAC_STATUS_LNKSTATE_CHANGED)) == 0) | |
1da177e4 LT |
4235 | break; |
4236 | } | |
4237 | ||
4238 | mac_status = tr32(MAC_STATUS); | |
4239 | if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) { | |
4240 | current_link_up = 0; | |
3d3ebe74 MC |
4241 | if (tp->link_config.autoneg == AUTONEG_ENABLE && |
4242 | tp->serdes_counter == 0) { | |
1da177e4 LT |
4243 | tw32_f(MAC_MODE, (tp->mac_mode | |
4244 | MAC_MODE_SEND_CONFIGS)); | |
4245 | udelay(1); | |
4246 | tw32_f(MAC_MODE, tp->mac_mode); | |
4247 | } | |
4248 | } | |
4249 | ||
4250 | if (current_link_up == 1) { | |
4251 | tp->link_config.active_speed = SPEED_1000; | |
4252 | tp->link_config.active_duplex = DUPLEX_FULL; | |
4253 | tw32(MAC_LED_CTRL, (tp->led_ctrl | | |
4254 | LED_CTRL_LNKLED_OVERRIDE | | |
4255 | LED_CTRL_1000MBPS_ON)); | |
4256 | } else { | |
4257 | tp->link_config.active_speed = SPEED_INVALID; | |
4258 | tp->link_config.active_duplex = DUPLEX_INVALID; | |
4259 | tw32(MAC_LED_CTRL, (tp->led_ctrl | | |
4260 | LED_CTRL_LNKLED_OVERRIDE | | |
4261 | LED_CTRL_TRAFFIC_OVERRIDE)); | |
4262 | } | |
4263 | ||
4264 | if (current_link_up != netif_carrier_ok(tp->dev)) { | |
4265 | if (current_link_up) | |
4266 | netif_carrier_on(tp->dev); | |
4267 | else | |
4268 | netif_carrier_off(tp->dev); | |
4269 | tg3_link_report(tp); | |
4270 | } else { | |
8d018621 | 4271 | u32 now_pause_cfg = tp->link_config.active_flowctrl; |
1da177e4 LT |
4272 | if (orig_pause_cfg != now_pause_cfg || |
4273 | orig_active_speed != tp->link_config.active_speed || | |
4274 | orig_active_duplex != tp->link_config.active_duplex) | |
4275 | tg3_link_report(tp); | |
4276 | } | |
4277 | ||
4278 | return 0; | |
4279 | } | |
4280 | ||
747e8f8b MC |
4281 | static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset) |
4282 | { | |
4283 | int current_link_up, err = 0; | |
4284 | u32 bmsr, bmcr; | |
4285 | u16 current_speed; | |
4286 | u8 current_duplex; | |
ef167e27 | 4287 | u32 local_adv, remote_adv; |
747e8f8b MC |
4288 | |
4289 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
4290 | tw32_f(MAC_MODE, tp->mac_mode); | |
4291 | udelay(40); | |
4292 | ||
4293 | tw32(MAC_EVENT, 0); | |
4294 | ||
4295 | tw32_f(MAC_STATUS, | |
4296 | (MAC_STATUS_SYNC_CHANGED | | |
4297 | MAC_STATUS_CFG_CHANGED | | |
4298 | MAC_STATUS_MI_COMPLETION | | |
4299 | MAC_STATUS_LNKSTATE_CHANGED)); | |
4300 | udelay(40); | |
4301 | ||
4302 | if (force_reset) | |
4303 | tg3_phy_reset(tp); | |
4304 | ||
4305 | current_link_up = 0; | |
4306 | current_speed = SPEED_INVALID; | |
4307 | current_duplex = DUPLEX_INVALID; | |
4308 | ||
4309 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
4310 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
d4d2c558 MC |
4311 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { |
4312 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) | |
4313 | bmsr |= BMSR_LSTATUS; | |
4314 | else | |
4315 | bmsr &= ~BMSR_LSTATUS; | |
4316 | } | |
747e8f8b MC |
4317 | |
4318 | err |= tg3_readphy(tp, MII_BMCR, &bmcr); | |
4319 | ||
4320 | if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset && | |
f07e9af3 | 4321 | (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { |
747e8f8b MC |
4322 | /* do nothing, just check for link up at the end */ |
4323 | } else if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
4324 | u32 adv, new_adv; | |
4325 | ||
4326 | err |= tg3_readphy(tp, MII_ADVERTISE, &adv); | |
4327 | new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF | | |
4328 | ADVERTISE_1000XPAUSE | | |
4329 | ADVERTISE_1000XPSE_ASYM | | |
4330 | ADVERTISE_SLCT); | |
4331 | ||
ba4d07a8 | 4332 | new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); |
747e8f8b MC |
4333 | |
4334 | if (tp->link_config.advertising & ADVERTISED_1000baseT_Half) | |
4335 | new_adv |= ADVERTISE_1000XHALF; | |
4336 | if (tp->link_config.advertising & ADVERTISED_1000baseT_Full) | |
4337 | new_adv |= ADVERTISE_1000XFULL; | |
4338 | ||
4339 | if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) { | |
4340 | tg3_writephy(tp, MII_ADVERTISE, new_adv); | |
4341 | bmcr |= BMCR_ANENABLE | BMCR_ANRESTART; | |
4342 | tg3_writephy(tp, MII_BMCR, bmcr); | |
4343 | ||
4344 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
3d3ebe74 | 4345 | tp->serdes_counter = SERDES_AN_TIMEOUT_5714S; |
f07e9af3 | 4346 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
4347 | |
4348 | return err; | |
4349 | } | |
4350 | } else { | |
4351 | u32 new_bmcr; | |
4352 | ||
4353 | bmcr &= ~BMCR_SPEED1000; | |
4354 | new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX); | |
4355 | ||
4356 | if (tp->link_config.duplex == DUPLEX_FULL) | |
4357 | new_bmcr |= BMCR_FULLDPLX; | |
4358 | ||
4359 | if (new_bmcr != bmcr) { | |
4360 | /* BMCR_SPEED1000 is a reserved bit that needs | |
4361 | * to be set on write. | |
4362 | */ | |
4363 | new_bmcr |= BMCR_SPEED1000; | |
4364 | ||
4365 | /* Force a linkdown */ | |
4366 | if (netif_carrier_ok(tp->dev)) { | |
4367 | u32 adv; | |
4368 | ||
4369 | err |= tg3_readphy(tp, MII_ADVERTISE, &adv); | |
4370 | adv &= ~(ADVERTISE_1000XFULL | | |
4371 | ADVERTISE_1000XHALF | | |
4372 | ADVERTISE_SLCT); | |
4373 | tg3_writephy(tp, MII_ADVERTISE, adv); | |
4374 | tg3_writephy(tp, MII_BMCR, bmcr | | |
4375 | BMCR_ANRESTART | | |
4376 | BMCR_ANENABLE); | |
4377 | udelay(10); | |
4378 | netif_carrier_off(tp->dev); | |
4379 | } | |
4380 | tg3_writephy(tp, MII_BMCR, new_bmcr); | |
4381 | bmcr = new_bmcr; | |
4382 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
4383 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
d4d2c558 MC |
4384 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == |
4385 | ASIC_REV_5714) { | |
4386 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) | |
4387 | bmsr |= BMSR_LSTATUS; | |
4388 | else | |
4389 | bmsr &= ~BMSR_LSTATUS; | |
4390 | } | |
f07e9af3 | 4391 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
4392 | } |
4393 | } | |
4394 | ||
4395 | if (bmsr & BMSR_LSTATUS) { | |
4396 | current_speed = SPEED_1000; | |
4397 | current_link_up = 1; | |
4398 | if (bmcr & BMCR_FULLDPLX) | |
4399 | current_duplex = DUPLEX_FULL; | |
4400 | else | |
4401 | current_duplex = DUPLEX_HALF; | |
4402 | ||
ef167e27 MC |
4403 | local_adv = 0; |
4404 | remote_adv = 0; | |
4405 | ||
747e8f8b | 4406 | if (bmcr & BMCR_ANENABLE) { |
ef167e27 | 4407 | u32 common; |
747e8f8b MC |
4408 | |
4409 | err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv); | |
4410 | err |= tg3_readphy(tp, MII_LPA, &remote_adv); | |
4411 | common = local_adv & remote_adv; | |
4412 | if (common & (ADVERTISE_1000XHALF | | |
4413 | ADVERTISE_1000XFULL)) { | |
4414 | if (common & ADVERTISE_1000XFULL) | |
4415 | current_duplex = DUPLEX_FULL; | |
4416 | else | |
4417 | current_duplex = DUPLEX_HALF; | |
63c3a66f | 4418 | } else if (!tg3_flag(tp, 5780_CLASS)) { |
57d8b880 | 4419 | /* Link is up via parallel detect */ |
859a5887 | 4420 | } else { |
747e8f8b | 4421 | current_link_up = 0; |
859a5887 | 4422 | } |
747e8f8b MC |
4423 | } |
4424 | } | |
4425 | ||
ef167e27 MC |
4426 | if (current_link_up == 1 && current_duplex == DUPLEX_FULL) |
4427 | tg3_setup_flow_control(tp, local_adv, remote_adv); | |
4428 | ||
747e8f8b MC |
4429 | tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; |
4430 | if (tp->link_config.active_duplex == DUPLEX_HALF) | |
4431 | tp->mac_mode |= MAC_MODE_HALF_DUPLEX; | |
4432 | ||
4433 | tw32_f(MAC_MODE, tp->mac_mode); | |
4434 | udelay(40); | |
4435 | ||
4436 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
4437 | ||
4438 | tp->link_config.active_speed = current_speed; | |
4439 | tp->link_config.active_duplex = current_duplex; | |
4440 | ||
4441 | if (current_link_up != netif_carrier_ok(tp->dev)) { | |
4442 | if (current_link_up) | |
4443 | netif_carrier_on(tp->dev); | |
4444 | else { | |
4445 | netif_carrier_off(tp->dev); | |
f07e9af3 | 4446 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
4447 | } |
4448 | tg3_link_report(tp); | |
4449 | } | |
4450 | return err; | |
4451 | } | |
4452 | ||
4453 | static void tg3_serdes_parallel_detect(struct tg3 *tp) | |
4454 | { | |
3d3ebe74 | 4455 | if (tp->serdes_counter) { |
747e8f8b | 4456 | /* Give autoneg time to complete. */ |
3d3ebe74 | 4457 | tp->serdes_counter--; |
747e8f8b MC |
4458 | return; |
4459 | } | |
c6cdf436 | 4460 | |
747e8f8b MC |
4461 | if (!netif_carrier_ok(tp->dev) && |
4462 | (tp->link_config.autoneg == AUTONEG_ENABLE)) { | |
4463 | u32 bmcr; | |
4464 | ||
4465 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
4466 | if (bmcr & BMCR_ANENABLE) { | |
4467 | u32 phy1, phy2; | |
4468 | ||
4469 | /* Select shadow register 0x1f */ | |
f08aa1a8 MC |
4470 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00); |
4471 | tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1); | |
747e8f8b MC |
4472 | |
4473 | /* Select expansion interrupt status register */ | |
f08aa1a8 MC |
4474 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, |
4475 | MII_TG3_DSP_EXP1_INT_STAT); | |
4476 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); | |
4477 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); | |
747e8f8b MC |
4478 | |
4479 | if ((phy1 & 0x10) && !(phy2 & 0x20)) { | |
4480 | /* We have signal detect and not receiving | |
4481 | * config code words, link is up by parallel | |
4482 | * detection. | |
4483 | */ | |
4484 | ||
4485 | bmcr &= ~BMCR_ANENABLE; | |
4486 | bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX; | |
4487 | tg3_writephy(tp, MII_BMCR, bmcr); | |
f07e9af3 | 4488 | tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
4489 | } |
4490 | } | |
859a5887 MC |
4491 | } else if (netif_carrier_ok(tp->dev) && |
4492 | (tp->link_config.autoneg == AUTONEG_ENABLE) && | |
f07e9af3 | 4493 | (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { |
747e8f8b MC |
4494 | u32 phy2; |
4495 | ||
4496 | /* Select expansion interrupt status register */ | |
f08aa1a8 MC |
4497 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, |
4498 | MII_TG3_DSP_EXP1_INT_STAT); | |
4499 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); | |
747e8f8b MC |
4500 | if (phy2 & 0x20) { |
4501 | u32 bmcr; | |
4502 | ||
4503 | /* Config code words received, turn on autoneg. */ | |
4504 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
4505 | tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE); | |
4506 | ||
f07e9af3 | 4507 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
4508 | |
4509 | } | |
4510 | } | |
4511 | } | |
4512 | ||
1da177e4 LT |
4513 | static int tg3_setup_phy(struct tg3 *tp, int force_reset) |
4514 | { | |
f2096f94 | 4515 | u32 val; |
1da177e4 LT |
4516 | int err; |
4517 | ||
f07e9af3 | 4518 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
1da177e4 | 4519 | err = tg3_setup_fiber_phy(tp, force_reset); |
f07e9af3 | 4520 | else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) |
747e8f8b | 4521 | err = tg3_setup_fiber_mii_phy(tp, force_reset); |
859a5887 | 4522 | else |
1da177e4 | 4523 | err = tg3_setup_copper_phy(tp, force_reset); |
1da177e4 | 4524 | |
bcb37f6c | 4525 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) { |
f2096f94 | 4526 | u32 scale; |
aa6c91fe MC |
4527 | |
4528 | val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK; | |
4529 | if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5) | |
4530 | scale = 65; | |
4531 | else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25) | |
4532 | scale = 6; | |
4533 | else | |
4534 | scale = 12; | |
4535 | ||
4536 | val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK; | |
4537 | val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT); | |
4538 | tw32(GRC_MISC_CFG, val); | |
4539 | } | |
4540 | ||
f2096f94 MC |
4541 | val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) | |
4542 | (6 << TX_LENGTHS_IPG_SHIFT); | |
4543 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
4544 | val |= tr32(MAC_TX_LENGTHS) & | |
4545 | (TX_LENGTHS_JMB_FRM_LEN_MSK | | |
4546 | TX_LENGTHS_CNT_DWN_VAL_MSK); | |
4547 | ||
1da177e4 LT |
4548 | if (tp->link_config.active_speed == SPEED_1000 && |
4549 | tp->link_config.active_duplex == DUPLEX_HALF) | |
f2096f94 MC |
4550 | tw32(MAC_TX_LENGTHS, val | |
4551 | (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)); | |
1da177e4 | 4552 | else |
f2096f94 MC |
4553 | tw32(MAC_TX_LENGTHS, val | |
4554 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT)); | |
1da177e4 | 4555 | |
63c3a66f | 4556 | if (!tg3_flag(tp, 5705_PLUS)) { |
1da177e4 LT |
4557 | if (netif_carrier_ok(tp->dev)) { |
4558 | tw32(HOSTCC_STAT_COAL_TICKS, | |
15f9850d | 4559 | tp->coal.stats_block_coalesce_usecs); |
1da177e4 LT |
4560 | } else { |
4561 | tw32(HOSTCC_STAT_COAL_TICKS, 0); | |
4562 | } | |
4563 | } | |
4564 | ||
63c3a66f | 4565 | if (tg3_flag(tp, ASPM_WORKAROUND)) { |
f2096f94 | 4566 | val = tr32(PCIE_PWR_MGMT_THRESH); |
8ed5d97e MC |
4567 | if (!netif_carrier_ok(tp->dev)) |
4568 | val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) | | |
4569 | tp->pwrmgmt_thresh; | |
4570 | else | |
4571 | val |= PCIE_PWR_MGMT_L1_THRESH_MSK; | |
4572 | tw32(PCIE_PWR_MGMT_THRESH, val); | |
4573 | } | |
4574 | ||
1da177e4 LT |
4575 | return err; |
4576 | } | |
4577 | ||
66cfd1bd MC |
4578 | static inline int tg3_irq_sync(struct tg3 *tp) |
4579 | { | |
4580 | return tp->irq_sync; | |
4581 | } | |
4582 | ||
97bd8e49 MC |
4583 | static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len) |
4584 | { | |
4585 | int i; | |
4586 | ||
4587 | dst = (u32 *)((u8 *)dst + off); | |
4588 | for (i = 0; i < len; i += sizeof(u32)) | |
4589 | *dst++ = tr32(off + i); | |
4590 | } | |
4591 | ||
4592 | static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs) | |
4593 | { | |
4594 | tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0); | |
4595 | tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200); | |
4596 | tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0); | |
4597 | tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0); | |
4598 | tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04); | |
4599 | tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80); | |
4600 | tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48); | |
4601 | tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04); | |
4602 | tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20); | |
4603 | tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c); | |
4604 | tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c); | |
4605 | tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c); | |
4606 | tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44); | |
4607 | tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04); | |
4608 | tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20); | |
4609 | tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14); | |
4610 | tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08); | |
4611 | tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08); | |
4612 | tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100); | |
4613 | ||
63c3a66f | 4614 | if (tg3_flag(tp, SUPPORT_MSIX)) |
97bd8e49 MC |
4615 | tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180); |
4616 | ||
4617 | tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10); | |
4618 | tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58); | |
4619 | tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08); | |
4620 | tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08); | |
4621 | tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04); | |
4622 | tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04); | |
4623 | tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04); | |
4624 | tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04); | |
4625 | ||
63c3a66f | 4626 | if (!tg3_flag(tp, 5705_PLUS)) { |
97bd8e49 MC |
4627 | tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04); |
4628 | tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04); | |
4629 | tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04); | |
4630 | } | |
4631 | ||
4632 | tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110); | |
4633 | tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120); | |
4634 | tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c); | |
4635 | tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04); | |
4636 | tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c); | |
4637 | ||
63c3a66f | 4638 | if (tg3_flag(tp, NVRAM)) |
97bd8e49 MC |
4639 | tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24); |
4640 | } | |
4641 | ||
4642 | static void tg3_dump_state(struct tg3 *tp) | |
4643 | { | |
4644 | int i; | |
4645 | u32 *regs; | |
4646 | ||
4647 | regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC); | |
4648 | if (!regs) { | |
4649 | netdev_err(tp->dev, "Failed allocating register dump buffer\n"); | |
4650 | return; | |
4651 | } | |
4652 | ||
63c3a66f | 4653 | if (tg3_flag(tp, PCI_EXPRESS)) { |
97bd8e49 MC |
4654 | /* Read up to but not including private PCI registers */ |
4655 | for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32)) | |
4656 | regs[i / sizeof(u32)] = tr32(i); | |
4657 | } else | |
4658 | tg3_dump_legacy_regs(tp, regs); | |
4659 | ||
4660 | for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) { | |
4661 | if (!regs[i + 0] && !regs[i + 1] && | |
4662 | !regs[i + 2] && !regs[i + 3]) | |
4663 | continue; | |
4664 | ||
4665 | netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n", | |
4666 | i * 4, | |
4667 | regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]); | |
4668 | } | |
4669 | ||
4670 | kfree(regs); | |
4671 | ||
4672 | for (i = 0; i < tp->irq_cnt; i++) { | |
4673 | struct tg3_napi *tnapi = &tp->napi[i]; | |
4674 | ||
4675 | /* SW status block */ | |
4676 | netdev_err(tp->dev, | |
4677 | "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n", | |
4678 | i, | |
4679 | tnapi->hw_status->status, | |
4680 | tnapi->hw_status->status_tag, | |
4681 | tnapi->hw_status->rx_jumbo_consumer, | |
4682 | tnapi->hw_status->rx_consumer, | |
4683 | tnapi->hw_status->rx_mini_consumer, | |
4684 | tnapi->hw_status->idx[0].rx_producer, | |
4685 | tnapi->hw_status->idx[0].tx_consumer); | |
4686 | ||
4687 | netdev_err(tp->dev, | |
4688 | "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n", | |
4689 | i, | |
4690 | tnapi->last_tag, tnapi->last_irq_tag, | |
4691 | tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending, | |
4692 | tnapi->rx_rcb_ptr, | |
4693 | tnapi->prodring.rx_std_prod_idx, | |
4694 | tnapi->prodring.rx_std_cons_idx, | |
4695 | tnapi->prodring.rx_jmb_prod_idx, | |
4696 | tnapi->prodring.rx_jmb_cons_idx); | |
4697 | } | |
4698 | } | |
4699 | ||
df3e6548 MC |
4700 | /* This is called whenever we suspect that the system chipset is re- |
4701 | * ordering the sequence of MMIO to the tx send mailbox. The symptom | |
4702 | * is bogus tx completions. We try to recover by setting the | |
4703 | * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later | |
4704 | * in the workqueue. | |
4705 | */ | |
4706 | static void tg3_tx_recover(struct tg3 *tp) | |
4707 | { | |
63c3a66f | 4708 | BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) || |
df3e6548 MC |
4709 | tp->write32_tx_mbox == tg3_write_indirect_mbox); |
4710 | ||
5129c3a3 MC |
4711 | netdev_warn(tp->dev, |
4712 | "The system may be re-ordering memory-mapped I/O " | |
4713 | "cycles to the network device, attempting to recover. " | |
4714 | "Please report the problem to the driver maintainer " | |
4715 | "and include system chipset information.\n"); | |
df3e6548 MC |
4716 | |
4717 | spin_lock(&tp->lock); | |
63c3a66f | 4718 | tg3_flag_set(tp, TX_RECOVERY_PENDING); |
df3e6548 MC |
4719 | spin_unlock(&tp->lock); |
4720 | } | |
4721 | ||
f3f3f27e | 4722 | static inline u32 tg3_tx_avail(struct tg3_napi *tnapi) |
1b2a7205 | 4723 | { |
f65aac16 MC |
4724 | /* Tell compiler to fetch tx indices from memory. */ |
4725 | barrier(); | |
f3f3f27e MC |
4726 | return tnapi->tx_pending - |
4727 | ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1)); | |
1b2a7205 MC |
4728 | } |
4729 | ||
1da177e4 LT |
4730 | /* Tigon3 never reports partial packet sends. So we do not |
4731 | * need special logic to handle SKBs that have not had all | |
4732 | * of their frags sent yet, like SunGEM does. | |
4733 | */ | |
17375d25 | 4734 | static void tg3_tx(struct tg3_napi *tnapi) |
1da177e4 | 4735 | { |
17375d25 | 4736 | struct tg3 *tp = tnapi->tp; |
898a56f8 | 4737 | u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer; |
f3f3f27e | 4738 | u32 sw_idx = tnapi->tx_cons; |
fe5f5787 MC |
4739 | struct netdev_queue *txq; |
4740 | int index = tnapi - tp->napi; | |
4741 | ||
63c3a66f | 4742 | if (tg3_flag(tp, ENABLE_TSS)) |
fe5f5787 MC |
4743 | index--; |
4744 | ||
4745 | txq = netdev_get_tx_queue(tp->dev, index); | |
1da177e4 LT |
4746 | |
4747 | while (sw_idx != hw_idx) { | |
f4188d8a | 4748 | struct ring_info *ri = &tnapi->tx_buffers[sw_idx]; |
1da177e4 | 4749 | struct sk_buff *skb = ri->skb; |
df3e6548 MC |
4750 | int i, tx_bug = 0; |
4751 | ||
4752 | if (unlikely(skb == NULL)) { | |
4753 | tg3_tx_recover(tp); | |
4754 | return; | |
4755 | } | |
1da177e4 | 4756 | |
f4188d8a | 4757 | pci_unmap_single(tp->pdev, |
4e5e4f0d | 4758 | dma_unmap_addr(ri, mapping), |
f4188d8a AD |
4759 | skb_headlen(skb), |
4760 | PCI_DMA_TODEVICE); | |
1da177e4 LT |
4761 | |
4762 | ri->skb = NULL; | |
4763 | ||
4764 | sw_idx = NEXT_TX(sw_idx); | |
4765 | ||
4766 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
f3f3f27e | 4767 | ri = &tnapi->tx_buffers[sw_idx]; |
df3e6548 MC |
4768 | if (unlikely(ri->skb != NULL || sw_idx == hw_idx)) |
4769 | tx_bug = 1; | |
f4188d8a AD |
4770 | |
4771 | pci_unmap_page(tp->pdev, | |
4e5e4f0d | 4772 | dma_unmap_addr(ri, mapping), |
f4188d8a AD |
4773 | skb_shinfo(skb)->frags[i].size, |
4774 | PCI_DMA_TODEVICE); | |
1da177e4 LT |
4775 | sw_idx = NEXT_TX(sw_idx); |
4776 | } | |
4777 | ||
f47c11ee | 4778 | dev_kfree_skb(skb); |
df3e6548 MC |
4779 | |
4780 | if (unlikely(tx_bug)) { | |
4781 | tg3_tx_recover(tp); | |
4782 | return; | |
4783 | } | |
1da177e4 LT |
4784 | } |
4785 | ||
f3f3f27e | 4786 | tnapi->tx_cons = sw_idx; |
1da177e4 | 4787 | |
1b2a7205 MC |
4788 | /* Need to make the tx_cons update visible to tg3_start_xmit() |
4789 | * before checking for netif_queue_stopped(). Without the | |
4790 | * memory barrier, there is a small possibility that tg3_start_xmit() | |
4791 | * will miss it and cause the queue to be stopped forever. | |
4792 | */ | |
4793 | smp_mb(); | |
4794 | ||
fe5f5787 | 4795 | if (unlikely(netif_tx_queue_stopped(txq) && |
f3f3f27e | 4796 | (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) { |
fe5f5787 MC |
4797 | __netif_tx_lock(txq, smp_processor_id()); |
4798 | if (netif_tx_queue_stopped(txq) && | |
f3f3f27e | 4799 | (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))) |
fe5f5787 MC |
4800 | netif_tx_wake_queue(txq); |
4801 | __netif_tx_unlock(txq); | |
51b91468 | 4802 | } |
1da177e4 LT |
4803 | } |
4804 | ||
2b2cdb65 MC |
4805 | static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz) |
4806 | { | |
4807 | if (!ri->skb) | |
4808 | return; | |
4809 | ||
4e5e4f0d | 4810 | pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping), |
2b2cdb65 MC |
4811 | map_sz, PCI_DMA_FROMDEVICE); |
4812 | dev_kfree_skb_any(ri->skb); | |
4813 | ri->skb = NULL; | |
4814 | } | |
4815 | ||
1da177e4 LT |
4816 | /* Returns size of skb allocated or < 0 on error. |
4817 | * | |
4818 | * We only need to fill in the address because the other members | |
4819 | * of the RX descriptor are invariant, see tg3_init_rings. | |
4820 | * | |
4821 | * Note the purposeful assymetry of cpu vs. chip accesses. For | |
4822 | * posting buffers we only dirty the first cache line of the RX | |
4823 | * descriptor (containing the address). Whereas for the RX status | |
4824 | * buffers the cpu only reads the last cacheline of the RX descriptor | |
4825 | * (to fetch the error flags, vlan tag, checksum, and opaque cookie). | |
4826 | */ | |
86b21e59 | 4827 | static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr, |
a3896167 | 4828 | u32 opaque_key, u32 dest_idx_unmasked) |
1da177e4 LT |
4829 | { |
4830 | struct tg3_rx_buffer_desc *desc; | |
f94e290e | 4831 | struct ring_info *map; |
1da177e4 LT |
4832 | struct sk_buff *skb; |
4833 | dma_addr_t mapping; | |
4834 | int skb_size, dest_idx; | |
4835 | ||
1da177e4 LT |
4836 | switch (opaque_key) { |
4837 | case RXD_OPAQUE_RING_STD: | |
2c49a44d | 4838 | dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; |
21f581a5 MC |
4839 | desc = &tpr->rx_std[dest_idx]; |
4840 | map = &tpr->rx_std_buffers[dest_idx]; | |
287be12e | 4841 | skb_size = tp->rx_pkt_map_sz; |
1da177e4 LT |
4842 | break; |
4843 | ||
4844 | case RXD_OPAQUE_RING_JUMBO: | |
2c49a44d | 4845 | dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; |
79ed5ac7 | 4846 | desc = &tpr->rx_jmb[dest_idx].std; |
21f581a5 | 4847 | map = &tpr->rx_jmb_buffers[dest_idx]; |
287be12e | 4848 | skb_size = TG3_RX_JMB_MAP_SZ; |
1da177e4 LT |
4849 | break; |
4850 | ||
4851 | default: | |
4852 | return -EINVAL; | |
855e1111 | 4853 | } |
1da177e4 LT |
4854 | |
4855 | /* Do not overwrite any of the map or rp information | |
4856 | * until we are sure we can commit to a new buffer. | |
4857 | * | |
4858 | * Callers depend upon this behavior and assume that | |
4859 | * we leave everything unchanged if we fail. | |
4860 | */ | |
287be12e | 4861 | skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset); |
1da177e4 LT |
4862 | if (skb == NULL) |
4863 | return -ENOMEM; | |
4864 | ||
1da177e4 LT |
4865 | skb_reserve(skb, tp->rx_offset); |
4866 | ||
287be12e | 4867 | mapping = pci_map_single(tp->pdev, skb->data, skb_size, |
1da177e4 | 4868 | PCI_DMA_FROMDEVICE); |
a21771dd MC |
4869 | if (pci_dma_mapping_error(tp->pdev, mapping)) { |
4870 | dev_kfree_skb(skb); | |
4871 | return -EIO; | |
4872 | } | |
1da177e4 LT |
4873 | |
4874 | map->skb = skb; | |
4e5e4f0d | 4875 | dma_unmap_addr_set(map, mapping, mapping); |
1da177e4 | 4876 | |
1da177e4 LT |
4877 | desc->addr_hi = ((u64)mapping >> 32); |
4878 | desc->addr_lo = ((u64)mapping & 0xffffffff); | |
4879 | ||
4880 | return skb_size; | |
4881 | } | |
4882 | ||
4883 | /* We only need to move over in the address because the other | |
4884 | * members of the RX descriptor are invariant. See notes above | |
4885 | * tg3_alloc_rx_skb for full details. | |
4886 | */ | |
a3896167 MC |
4887 | static void tg3_recycle_rx(struct tg3_napi *tnapi, |
4888 | struct tg3_rx_prodring_set *dpr, | |
4889 | u32 opaque_key, int src_idx, | |
4890 | u32 dest_idx_unmasked) | |
1da177e4 | 4891 | { |
17375d25 | 4892 | struct tg3 *tp = tnapi->tp; |
1da177e4 LT |
4893 | struct tg3_rx_buffer_desc *src_desc, *dest_desc; |
4894 | struct ring_info *src_map, *dest_map; | |
8fea32b9 | 4895 | struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring; |
c6cdf436 | 4896 | int dest_idx; |
1da177e4 LT |
4897 | |
4898 | switch (opaque_key) { | |
4899 | case RXD_OPAQUE_RING_STD: | |
2c49a44d | 4900 | dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; |
a3896167 MC |
4901 | dest_desc = &dpr->rx_std[dest_idx]; |
4902 | dest_map = &dpr->rx_std_buffers[dest_idx]; | |
4903 | src_desc = &spr->rx_std[src_idx]; | |
4904 | src_map = &spr->rx_std_buffers[src_idx]; | |
1da177e4 LT |
4905 | break; |
4906 | ||
4907 | case RXD_OPAQUE_RING_JUMBO: | |
2c49a44d | 4908 | dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; |
a3896167 MC |
4909 | dest_desc = &dpr->rx_jmb[dest_idx].std; |
4910 | dest_map = &dpr->rx_jmb_buffers[dest_idx]; | |
4911 | src_desc = &spr->rx_jmb[src_idx].std; | |
4912 | src_map = &spr->rx_jmb_buffers[src_idx]; | |
1da177e4 LT |
4913 | break; |
4914 | ||
4915 | default: | |
4916 | return; | |
855e1111 | 4917 | } |
1da177e4 LT |
4918 | |
4919 | dest_map->skb = src_map->skb; | |
4e5e4f0d FT |
4920 | dma_unmap_addr_set(dest_map, mapping, |
4921 | dma_unmap_addr(src_map, mapping)); | |
1da177e4 LT |
4922 | dest_desc->addr_hi = src_desc->addr_hi; |
4923 | dest_desc->addr_lo = src_desc->addr_lo; | |
e92967bf MC |
4924 | |
4925 | /* Ensure that the update to the skb happens after the physical | |
4926 | * addresses have been transferred to the new BD location. | |
4927 | */ | |
4928 | smp_wmb(); | |
4929 | ||
1da177e4 LT |
4930 | src_map->skb = NULL; |
4931 | } | |
4932 | ||
1da177e4 LT |
4933 | /* The RX ring scheme is composed of multiple rings which post fresh |
4934 | * buffers to the chip, and one special ring the chip uses to report | |
4935 | * status back to the host. | |
4936 | * | |
4937 | * The special ring reports the status of received packets to the | |
4938 | * host. The chip does not write into the original descriptor the | |
4939 | * RX buffer was obtained from. The chip simply takes the original | |
4940 | * descriptor as provided by the host, updates the status and length | |
4941 | * field, then writes this into the next status ring entry. | |
4942 | * | |
4943 | * Each ring the host uses to post buffers to the chip is described | |
4944 | * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives, | |
4945 | * it is first placed into the on-chip ram. When the packet's length | |
4946 | * is known, it walks down the TG3_BDINFO entries to select the ring. | |
4947 | * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO | |
4948 | * which is within the range of the new packet's length is chosen. | |
4949 | * | |
4950 | * The "separate ring for rx status" scheme may sound queer, but it makes | |
4951 | * sense from a cache coherency perspective. If only the host writes | |
4952 | * to the buffer post rings, and only the chip writes to the rx status | |
4953 | * rings, then cache lines never move beyond shared-modified state. | |
4954 | * If both the host and chip were to write into the same ring, cache line | |
4955 | * eviction could occur since both entities want it in an exclusive state. | |
4956 | */ | |
17375d25 | 4957 | static int tg3_rx(struct tg3_napi *tnapi, int budget) |
1da177e4 | 4958 | { |
17375d25 | 4959 | struct tg3 *tp = tnapi->tp; |
f92905de | 4960 | u32 work_mask, rx_std_posted = 0; |
4361935a | 4961 | u32 std_prod_idx, jmb_prod_idx; |
72334482 | 4962 | u32 sw_idx = tnapi->rx_rcb_ptr; |
483ba50b | 4963 | u16 hw_idx; |
1da177e4 | 4964 | int received; |
8fea32b9 | 4965 | struct tg3_rx_prodring_set *tpr = &tnapi->prodring; |
1da177e4 | 4966 | |
8d9d7cfc | 4967 | hw_idx = *(tnapi->rx_rcb_prod_idx); |
1da177e4 LT |
4968 | /* |
4969 | * We need to order the read of hw_idx and the read of | |
4970 | * the opaque cookie. | |
4971 | */ | |
4972 | rmb(); | |
1da177e4 LT |
4973 | work_mask = 0; |
4974 | received = 0; | |
4361935a MC |
4975 | std_prod_idx = tpr->rx_std_prod_idx; |
4976 | jmb_prod_idx = tpr->rx_jmb_prod_idx; | |
1da177e4 | 4977 | while (sw_idx != hw_idx && budget > 0) { |
afc081f8 | 4978 | struct ring_info *ri; |
72334482 | 4979 | struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx]; |
1da177e4 LT |
4980 | unsigned int len; |
4981 | struct sk_buff *skb; | |
4982 | dma_addr_t dma_addr; | |
4983 | u32 opaque_key, desc_idx, *post_ptr; | |
4984 | ||
4985 | desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; | |
4986 | opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; | |
4987 | if (opaque_key == RXD_OPAQUE_RING_STD) { | |
8fea32b9 | 4988 | ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx]; |
4e5e4f0d | 4989 | dma_addr = dma_unmap_addr(ri, mapping); |
21f581a5 | 4990 | skb = ri->skb; |
4361935a | 4991 | post_ptr = &std_prod_idx; |
f92905de | 4992 | rx_std_posted++; |
1da177e4 | 4993 | } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) { |
8fea32b9 | 4994 | ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx]; |
4e5e4f0d | 4995 | dma_addr = dma_unmap_addr(ri, mapping); |
21f581a5 | 4996 | skb = ri->skb; |
4361935a | 4997 | post_ptr = &jmb_prod_idx; |
21f581a5 | 4998 | } else |
1da177e4 | 4999 | goto next_pkt_nopost; |
1da177e4 LT |
5000 | |
5001 | work_mask |= opaque_key; | |
5002 | ||
5003 | if ((desc->err_vlan & RXD_ERR_MASK) != 0 && | |
5004 | (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) { | |
5005 | drop_it: | |
a3896167 | 5006 | tg3_recycle_rx(tnapi, tpr, opaque_key, |
1da177e4 LT |
5007 | desc_idx, *post_ptr); |
5008 | drop_it_no_recycle: | |
5009 | /* Other statistics kept track of by card. */ | |
b0057c51 | 5010 | tp->rx_dropped++; |
1da177e4 LT |
5011 | goto next_pkt; |
5012 | } | |
5013 | ||
ad829268 MC |
5014 | len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - |
5015 | ETH_FCS_LEN; | |
1da177e4 | 5016 | |
d2757fc4 | 5017 | if (len > TG3_RX_COPY_THRESH(tp)) { |
1da177e4 LT |
5018 | int skb_size; |
5019 | ||
86b21e59 | 5020 | skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key, |
afc081f8 | 5021 | *post_ptr); |
1da177e4 LT |
5022 | if (skb_size < 0) |
5023 | goto drop_it; | |
5024 | ||
287be12e | 5025 | pci_unmap_single(tp->pdev, dma_addr, skb_size, |
1da177e4 LT |
5026 | PCI_DMA_FROMDEVICE); |
5027 | ||
61e800cf MC |
5028 | /* Ensure that the update to the skb happens |
5029 | * after the usage of the old DMA mapping. | |
5030 | */ | |
5031 | smp_wmb(); | |
5032 | ||
5033 | ri->skb = NULL; | |
5034 | ||
1da177e4 LT |
5035 | skb_put(skb, len); |
5036 | } else { | |
5037 | struct sk_buff *copy_skb; | |
5038 | ||
a3896167 | 5039 | tg3_recycle_rx(tnapi, tpr, opaque_key, |
1da177e4 LT |
5040 | desc_idx, *post_ptr); |
5041 | ||
bf933c80 | 5042 | copy_skb = netdev_alloc_skb(tp->dev, len + |
9dc7a113 | 5043 | TG3_RAW_IP_ALIGN); |
1da177e4 LT |
5044 | if (copy_skb == NULL) |
5045 | goto drop_it_no_recycle; | |
5046 | ||
bf933c80 | 5047 | skb_reserve(copy_skb, TG3_RAW_IP_ALIGN); |
1da177e4 LT |
5048 | skb_put(copy_skb, len); |
5049 | pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); | |
d626f62b | 5050 | skb_copy_from_linear_data(skb, copy_skb->data, len); |
1da177e4 LT |
5051 | pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); |
5052 | ||
5053 | /* We'll reuse the original ring buffer. */ | |
5054 | skb = copy_skb; | |
5055 | } | |
5056 | ||
dc668910 | 5057 | if ((tp->dev->features & NETIF_F_RXCSUM) && |
1da177e4 LT |
5058 | (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) && |
5059 | (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK) | |
5060 | >> RXD_TCPCSUM_SHIFT) == 0xffff)) | |
5061 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
5062 | else | |
bc8acf2c | 5063 | skb_checksum_none_assert(skb); |
1da177e4 LT |
5064 | |
5065 | skb->protocol = eth_type_trans(skb, tp->dev); | |
f7b493e0 MC |
5066 | |
5067 | if (len > (tp->dev->mtu + ETH_HLEN) && | |
5068 | skb->protocol != htons(ETH_P_8021Q)) { | |
5069 | dev_kfree_skb(skb); | |
b0057c51 | 5070 | goto drop_it_no_recycle; |
f7b493e0 MC |
5071 | } |
5072 | ||
9dc7a113 | 5073 | if (desc->type_flags & RXD_FLAG_VLAN && |
bf933c80 MC |
5074 | !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) |
5075 | __vlan_hwaccel_put_tag(skb, | |
5076 | desc->err_vlan & RXD_VLAN_MASK); | |
9dc7a113 | 5077 | |
bf933c80 | 5078 | napi_gro_receive(&tnapi->napi, skb); |
1da177e4 | 5079 | |
1da177e4 LT |
5080 | received++; |
5081 | budget--; | |
5082 | ||
5083 | next_pkt: | |
5084 | (*post_ptr)++; | |
f92905de MC |
5085 | |
5086 | if (unlikely(rx_std_posted >= tp->rx_std_max_post)) { | |
2c49a44d MC |
5087 | tpr->rx_std_prod_idx = std_prod_idx & |
5088 | tp->rx_std_ring_mask; | |
86cfe4ff MC |
5089 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, |
5090 | tpr->rx_std_prod_idx); | |
f92905de MC |
5091 | work_mask &= ~RXD_OPAQUE_RING_STD; |
5092 | rx_std_posted = 0; | |
5093 | } | |
1da177e4 | 5094 | next_pkt_nopost: |
483ba50b | 5095 | sw_idx++; |
7cb32cf2 | 5096 | sw_idx &= tp->rx_ret_ring_mask; |
52f6d697 MC |
5097 | |
5098 | /* Refresh hw_idx to see if there is new work */ | |
5099 | if (sw_idx == hw_idx) { | |
8d9d7cfc | 5100 | hw_idx = *(tnapi->rx_rcb_prod_idx); |
52f6d697 MC |
5101 | rmb(); |
5102 | } | |
1da177e4 LT |
5103 | } |
5104 | ||
5105 | /* ACK the status ring. */ | |
72334482 MC |
5106 | tnapi->rx_rcb_ptr = sw_idx; |
5107 | tw32_rx_mbox(tnapi->consmbox, sw_idx); | |
1da177e4 LT |
5108 | |
5109 | /* Refill RX ring(s). */ | |
63c3a66f | 5110 | if (!tg3_flag(tp, ENABLE_RSS)) { |
b196c7e4 | 5111 | if (work_mask & RXD_OPAQUE_RING_STD) { |
2c49a44d MC |
5112 | tpr->rx_std_prod_idx = std_prod_idx & |
5113 | tp->rx_std_ring_mask; | |
b196c7e4 MC |
5114 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, |
5115 | tpr->rx_std_prod_idx); | |
5116 | } | |
5117 | if (work_mask & RXD_OPAQUE_RING_JUMBO) { | |
2c49a44d MC |
5118 | tpr->rx_jmb_prod_idx = jmb_prod_idx & |
5119 | tp->rx_jmb_ring_mask; | |
b196c7e4 MC |
5120 | tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, |
5121 | tpr->rx_jmb_prod_idx); | |
5122 | } | |
5123 | mmiowb(); | |
5124 | } else if (work_mask) { | |
5125 | /* rx_std_buffers[] and rx_jmb_buffers[] entries must be | |
5126 | * updated before the producer indices can be updated. | |
5127 | */ | |
5128 | smp_wmb(); | |
5129 | ||
2c49a44d MC |
5130 | tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask; |
5131 | tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask; | |
b196c7e4 | 5132 | |
e4af1af9 MC |
5133 | if (tnapi != &tp->napi[1]) |
5134 | napi_schedule(&tp->napi[1].napi); | |
1da177e4 | 5135 | } |
1da177e4 LT |
5136 | |
5137 | return received; | |
5138 | } | |
5139 | ||
35f2d7d0 | 5140 | static void tg3_poll_link(struct tg3 *tp) |
1da177e4 | 5141 | { |
1da177e4 | 5142 | /* handle link change and other phy events */ |
63c3a66f | 5143 | if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) { |
35f2d7d0 MC |
5144 | struct tg3_hw_status *sblk = tp->napi[0].hw_status; |
5145 | ||
1da177e4 LT |
5146 | if (sblk->status & SD_STATUS_LINK_CHG) { |
5147 | sblk->status = SD_STATUS_UPDATED | | |
35f2d7d0 | 5148 | (sblk->status & ~SD_STATUS_LINK_CHG); |
f47c11ee | 5149 | spin_lock(&tp->lock); |
63c3a66f | 5150 | if (tg3_flag(tp, USE_PHYLIB)) { |
dd477003 MC |
5151 | tw32_f(MAC_STATUS, |
5152 | (MAC_STATUS_SYNC_CHANGED | | |
5153 | MAC_STATUS_CFG_CHANGED | | |
5154 | MAC_STATUS_MI_COMPLETION | | |
5155 | MAC_STATUS_LNKSTATE_CHANGED)); | |
5156 | udelay(40); | |
5157 | } else | |
5158 | tg3_setup_phy(tp, 0); | |
f47c11ee | 5159 | spin_unlock(&tp->lock); |
1da177e4 LT |
5160 | } |
5161 | } | |
35f2d7d0 MC |
5162 | } |
5163 | ||
f89f38b8 MC |
5164 | static int tg3_rx_prodring_xfer(struct tg3 *tp, |
5165 | struct tg3_rx_prodring_set *dpr, | |
5166 | struct tg3_rx_prodring_set *spr) | |
b196c7e4 MC |
5167 | { |
5168 | u32 si, di, cpycnt, src_prod_idx; | |
f89f38b8 | 5169 | int i, err = 0; |
b196c7e4 MC |
5170 | |
5171 | while (1) { | |
5172 | src_prod_idx = spr->rx_std_prod_idx; | |
5173 | ||
5174 | /* Make sure updates to the rx_std_buffers[] entries and the | |
5175 | * standard producer index are seen in the correct order. | |
5176 | */ | |
5177 | smp_rmb(); | |
5178 | ||
5179 | if (spr->rx_std_cons_idx == src_prod_idx) | |
5180 | break; | |
5181 | ||
5182 | if (spr->rx_std_cons_idx < src_prod_idx) | |
5183 | cpycnt = src_prod_idx - spr->rx_std_cons_idx; | |
5184 | else | |
2c49a44d MC |
5185 | cpycnt = tp->rx_std_ring_mask + 1 - |
5186 | spr->rx_std_cons_idx; | |
b196c7e4 | 5187 | |
2c49a44d MC |
5188 | cpycnt = min(cpycnt, |
5189 | tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx); | |
b196c7e4 MC |
5190 | |
5191 | si = spr->rx_std_cons_idx; | |
5192 | di = dpr->rx_std_prod_idx; | |
5193 | ||
e92967bf MC |
5194 | for (i = di; i < di + cpycnt; i++) { |
5195 | if (dpr->rx_std_buffers[i].skb) { | |
5196 | cpycnt = i - di; | |
f89f38b8 | 5197 | err = -ENOSPC; |
e92967bf MC |
5198 | break; |
5199 | } | |
5200 | } | |
5201 | ||
5202 | if (!cpycnt) | |
5203 | break; | |
5204 | ||
5205 | /* Ensure that updates to the rx_std_buffers ring and the | |
5206 | * shadowed hardware producer ring from tg3_recycle_skb() are | |
5207 | * ordered correctly WRT the skb check above. | |
5208 | */ | |
5209 | smp_rmb(); | |
5210 | ||
b196c7e4 MC |
5211 | memcpy(&dpr->rx_std_buffers[di], |
5212 | &spr->rx_std_buffers[si], | |
5213 | cpycnt * sizeof(struct ring_info)); | |
5214 | ||
5215 | for (i = 0; i < cpycnt; i++, di++, si++) { | |
5216 | struct tg3_rx_buffer_desc *sbd, *dbd; | |
5217 | sbd = &spr->rx_std[si]; | |
5218 | dbd = &dpr->rx_std[di]; | |
5219 | dbd->addr_hi = sbd->addr_hi; | |
5220 | dbd->addr_lo = sbd->addr_lo; | |
5221 | } | |
5222 | ||
2c49a44d MC |
5223 | spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) & |
5224 | tp->rx_std_ring_mask; | |
5225 | dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) & | |
5226 | tp->rx_std_ring_mask; | |
b196c7e4 MC |
5227 | } |
5228 | ||
5229 | while (1) { | |
5230 | src_prod_idx = spr->rx_jmb_prod_idx; | |
5231 | ||
5232 | /* Make sure updates to the rx_jmb_buffers[] entries and | |
5233 | * the jumbo producer index are seen in the correct order. | |
5234 | */ | |
5235 | smp_rmb(); | |
5236 | ||
5237 | if (spr->rx_jmb_cons_idx == src_prod_idx) | |
5238 | break; | |
5239 | ||
5240 | if (spr->rx_jmb_cons_idx < src_prod_idx) | |
5241 | cpycnt = src_prod_idx - spr->rx_jmb_cons_idx; | |
5242 | else | |
2c49a44d MC |
5243 | cpycnt = tp->rx_jmb_ring_mask + 1 - |
5244 | spr->rx_jmb_cons_idx; | |
b196c7e4 MC |
5245 | |
5246 | cpycnt = min(cpycnt, | |
2c49a44d | 5247 | tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx); |
b196c7e4 MC |
5248 | |
5249 | si = spr->rx_jmb_cons_idx; | |
5250 | di = dpr->rx_jmb_prod_idx; | |
5251 | ||
e92967bf MC |
5252 | for (i = di; i < di + cpycnt; i++) { |
5253 | if (dpr->rx_jmb_buffers[i].skb) { | |
5254 | cpycnt = i - di; | |
f89f38b8 | 5255 | err = -ENOSPC; |
e92967bf MC |
5256 | break; |
5257 | } | |
5258 | } | |
5259 | ||
5260 | if (!cpycnt) | |
5261 | break; | |
5262 | ||
5263 | /* Ensure that updates to the rx_jmb_buffers ring and the | |
5264 | * shadowed hardware producer ring from tg3_recycle_skb() are | |
5265 | * ordered correctly WRT the skb check above. | |
5266 | */ | |
5267 | smp_rmb(); | |
5268 | ||
b196c7e4 MC |
5269 | memcpy(&dpr->rx_jmb_buffers[di], |
5270 | &spr->rx_jmb_buffers[si], | |
5271 | cpycnt * sizeof(struct ring_info)); | |
5272 | ||
5273 | for (i = 0; i < cpycnt; i++, di++, si++) { | |
5274 | struct tg3_rx_buffer_desc *sbd, *dbd; | |
5275 | sbd = &spr->rx_jmb[si].std; | |
5276 | dbd = &dpr->rx_jmb[di].std; | |
5277 | dbd->addr_hi = sbd->addr_hi; | |
5278 | dbd->addr_lo = sbd->addr_lo; | |
5279 | } | |
5280 | ||
2c49a44d MC |
5281 | spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) & |
5282 | tp->rx_jmb_ring_mask; | |
5283 | dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) & | |
5284 | tp->rx_jmb_ring_mask; | |
b196c7e4 | 5285 | } |
f89f38b8 MC |
5286 | |
5287 | return err; | |
b196c7e4 MC |
5288 | } |
5289 | ||
35f2d7d0 MC |
5290 | static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget) |
5291 | { | |
5292 | struct tg3 *tp = tnapi->tp; | |
1da177e4 LT |
5293 | |
5294 | /* run TX completion thread */ | |
f3f3f27e | 5295 | if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) { |
17375d25 | 5296 | tg3_tx(tnapi); |
63c3a66f | 5297 | if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) |
4fd7ab59 | 5298 | return work_done; |
1da177e4 LT |
5299 | } |
5300 | ||
1da177e4 LT |
5301 | /* run RX thread, within the bounds set by NAPI. |
5302 | * All RX "locking" is done by ensuring outside | |
bea3348e | 5303 | * code synchronizes with tg3->napi.poll() |
1da177e4 | 5304 | */ |
8d9d7cfc | 5305 | if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr) |
17375d25 | 5306 | work_done += tg3_rx(tnapi, budget - work_done); |
1da177e4 | 5307 | |
63c3a66f | 5308 | if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) { |
8fea32b9 | 5309 | struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring; |
f89f38b8 | 5310 | int i, err = 0; |
e4af1af9 MC |
5311 | u32 std_prod_idx = dpr->rx_std_prod_idx; |
5312 | u32 jmb_prod_idx = dpr->rx_jmb_prod_idx; | |
b196c7e4 | 5313 | |
e4af1af9 | 5314 | for (i = 1; i < tp->irq_cnt; i++) |
f89f38b8 | 5315 | err |= tg3_rx_prodring_xfer(tp, dpr, |
8fea32b9 | 5316 | &tp->napi[i].prodring); |
b196c7e4 MC |
5317 | |
5318 | wmb(); | |
5319 | ||
e4af1af9 MC |
5320 | if (std_prod_idx != dpr->rx_std_prod_idx) |
5321 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, | |
5322 | dpr->rx_std_prod_idx); | |
b196c7e4 | 5323 | |
e4af1af9 MC |
5324 | if (jmb_prod_idx != dpr->rx_jmb_prod_idx) |
5325 | tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, | |
5326 | dpr->rx_jmb_prod_idx); | |
b196c7e4 MC |
5327 | |
5328 | mmiowb(); | |
f89f38b8 MC |
5329 | |
5330 | if (err) | |
5331 | tw32_f(HOSTCC_MODE, tp->coal_now); | |
b196c7e4 MC |
5332 | } |
5333 | ||
6f535763 DM |
5334 | return work_done; |
5335 | } | |
5336 | ||
35f2d7d0 MC |
5337 | static int tg3_poll_msix(struct napi_struct *napi, int budget) |
5338 | { | |
5339 | struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi); | |
5340 | struct tg3 *tp = tnapi->tp; | |
5341 | int work_done = 0; | |
5342 | struct tg3_hw_status *sblk = tnapi->hw_status; | |
5343 | ||
5344 | while (1) { | |
5345 | work_done = tg3_poll_work(tnapi, work_done, budget); | |
5346 | ||
63c3a66f | 5347 | if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) |
35f2d7d0 MC |
5348 | goto tx_recovery; |
5349 | ||
5350 | if (unlikely(work_done >= budget)) | |
5351 | break; | |
5352 | ||
c6cdf436 | 5353 | /* tp->last_tag is used in tg3_int_reenable() below |
35f2d7d0 MC |
5354 | * to tell the hw how much work has been processed, |
5355 | * so we must read it before checking for more work. | |
5356 | */ | |
5357 | tnapi->last_tag = sblk->status_tag; | |
5358 | tnapi->last_irq_tag = tnapi->last_tag; | |
5359 | rmb(); | |
5360 | ||
5361 | /* check for RX/TX work to do */ | |
6d40db7b MC |
5362 | if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons && |
5363 | *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) { | |
35f2d7d0 MC |
5364 | napi_complete(napi); |
5365 | /* Reenable interrupts. */ | |
5366 | tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); | |
5367 | mmiowb(); | |
5368 | break; | |
5369 | } | |
5370 | } | |
5371 | ||
5372 | return work_done; | |
5373 | ||
5374 | tx_recovery: | |
5375 | /* work_done is guaranteed to be less than budget. */ | |
5376 | napi_complete(napi); | |
5377 | schedule_work(&tp->reset_task); | |
5378 | return work_done; | |
5379 | } | |
5380 | ||
e64de4e6 MC |
5381 | static void tg3_process_error(struct tg3 *tp) |
5382 | { | |
5383 | u32 val; | |
5384 | bool real_error = false; | |
5385 | ||
63c3a66f | 5386 | if (tg3_flag(tp, ERROR_PROCESSED)) |
e64de4e6 MC |
5387 | return; |
5388 | ||
5389 | /* Check Flow Attention register */ | |
5390 | val = tr32(HOSTCC_FLOW_ATTN); | |
5391 | if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) { | |
5392 | netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n"); | |
5393 | real_error = true; | |
5394 | } | |
5395 | ||
5396 | if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) { | |
5397 | netdev_err(tp->dev, "MSI Status error. Resetting chip.\n"); | |
5398 | real_error = true; | |
5399 | } | |
5400 | ||
5401 | if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) { | |
5402 | netdev_err(tp->dev, "DMA Status error. Resetting chip.\n"); | |
5403 | real_error = true; | |
5404 | } | |
5405 | ||
5406 | if (!real_error) | |
5407 | return; | |
5408 | ||
5409 | tg3_dump_state(tp); | |
5410 | ||
63c3a66f | 5411 | tg3_flag_set(tp, ERROR_PROCESSED); |
e64de4e6 MC |
5412 | schedule_work(&tp->reset_task); |
5413 | } | |
5414 | ||
6f535763 DM |
5415 | static int tg3_poll(struct napi_struct *napi, int budget) |
5416 | { | |
8ef0442f MC |
5417 | struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi); |
5418 | struct tg3 *tp = tnapi->tp; | |
6f535763 | 5419 | int work_done = 0; |
898a56f8 | 5420 | struct tg3_hw_status *sblk = tnapi->hw_status; |
6f535763 DM |
5421 | |
5422 | while (1) { | |
e64de4e6 MC |
5423 | if (sblk->status & SD_STATUS_ERROR) |
5424 | tg3_process_error(tp); | |
5425 | ||
35f2d7d0 MC |
5426 | tg3_poll_link(tp); |
5427 | ||
17375d25 | 5428 | work_done = tg3_poll_work(tnapi, work_done, budget); |
6f535763 | 5429 | |
63c3a66f | 5430 | if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) |
6f535763 DM |
5431 | goto tx_recovery; |
5432 | ||
5433 | if (unlikely(work_done >= budget)) | |
5434 | break; | |
5435 | ||
63c3a66f | 5436 | if (tg3_flag(tp, TAGGED_STATUS)) { |
17375d25 | 5437 | /* tp->last_tag is used in tg3_int_reenable() below |
4fd7ab59 MC |
5438 | * to tell the hw how much work has been processed, |
5439 | * so we must read it before checking for more work. | |
5440 | */ | |
898a56f8 MC |
5441 | tnapi->last_tag = sblk->status_tag; |
5442 | tnapi->last_irq_tag = tnapi->last_tag; | |
4fd7ab59 MC |
5443 | rmb(); |
5444 | } else | |
5445 | sblk->status &= ~SD_STATUS_UPDATED; | |
6f535763 | 5446 | |
17375d25 | 5447 | if (likely(!tg3_has_work(tnapi))) { |
288379f0 | 5448 | napi_complete(napi); |
17375d25 | 5449 | tg3_int_reenable(tnapi); |
6f535763 DM |
5450 | break; |
5451 | } | |
1da177e4 LT |
5452 | } |
5453 | ||
bea3348e | 5454 | return work_done; |
6f535763 DM |
5455 | |
5456 | tx_recovery: | |
4fd7ab59 | 5457 | /* work_done is guaranteed to be less than budget. */ |
288379f0 | 5458 | napi_complete(napi); |
6f535763 | 5459 | schedule_work(&tp->reset_task); |
4fd7ab59 | 5460 | return work_done; |
1da177e4 LT |
5461 | } |
5462 | ||
66cfd1bd MC |
5463 | static void tg3_napi_disable(struct tg3 *tp) |
5464 | { | |
5465 | int i; | |
5466 | ||
5467 | for (i = tp->irq_cnt - 1; i >= 0; i--) | |
5468 | napi_disable(&tp->napi[i].napi); | |
5469 | } | |
5470 | ||
5471 | static void tg3_napi_enable(struct tg3 *tp) | |
5472 | { | |
5473 | int i; | |
5474 | ||
5475 | for (i = 0; i < tp->irq_cnt; i++) | |
5476 | napi_enable(&tp->napi[i].napi); | |
5477 | } | |
5478 | ||
5479 | static void tg3_napi_init(struct tg3 *tp) | |
5480 | { | |
5481 | int i; | |
5482 | ||
5483 | netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64); | |
5484 | for (i = 1; i < tp->irq_cnt; i++) | |
5485 | netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64); | |
5486 | } | |
5487 | ||
5488 | static void tg3_napi_fini(struct tg3 *tp) | |
5489 | { | |
5490 | int i; | |
5491 | ||
5492 | for (i = 0; i < tp->irq_cnt; i++) | |
5493 | netif_napi_del(&tp->napi[i].napi); | |
5494 | } | |
5495 | ||
5496 | static inline void tg3_netif_stop(struct tg3 *tp) | |
5497 | { | |
5498 | tp->dev->trans_start = jiffies; /* prevent tx timeout */ | |
5499 | tg3_napi_disable(tp); | |
5500 | netif_tx_disable(tp->dev); | |
5501 | } | |
5502 | ||
5503 | static inline void tg3_netif_start(struct tg3 *tp) | |
5504 | { | |
5505 | /* NOTE: unconditional netif_tx_wake_all_queues is only | |
5506 | * appropriate so long as all callers are assured to | |
5507 | * have free tx slots (such as after tg3_init_hw) | |
5508 | */ | |
5509 | netif_tx_wake_all_queues(tp->dev); | |
5510 | ||
5511 | tg3_napi_enable(tp); | |
5512 | tp->napi[0].hw_status->status |= SD_STATUS_UPDATED; | |
5513 | tg3_enable_ints(tp); | |
5514 | } | |
5515 | ||
f47c11ee DM |
5516 | static void tg3_irq_quiesce(struct tg3 *tp) |
5517 | { | |
4f125f42 MC |
5518 | int i; |
5519 | ||
f47c11ee DM |
5520 | BUG_ON(tp->irq_sync); |
5521 | ||
5522 | tp->irq_sync = 1; | |
5523 | smp_mb(); | |
5524 | ||
4f125f42 MC |
5525 | for (i = 0; i < tp->irq_cnt; i++) |
5526 | synchronize_irq(tp->napi[i].irq_vec); | |
f47c11ee DM |
5527 | } |
5528 | ||
f47c11ee DM |
5529 | /* Fully shutdown all tg3 driver activity elsewhere in the system. |
5530 | * If irq_sync is non-zero, then the IRQ handler must be synchronized | |
5531 | * with as well. Most of the time, this is not necessary except when | |
5532 | * shutting down the device. | |
5533 | */ | |
5534 | static inline void tg3_full_lock(struct tg3 *tp, int irq_sync) | |
5535 | { | |
46966545 | 5536 | spin_lock_bh(&tp->lock); |
f47c11ee DM |
5537 | if (irq_sync) |
5538 | tg3_irq_quiesce(tp); | |
f47c11ee DM |
5539 | } |
5540 | ||
5541 | static inline void tg3_full_unlock(struct tg3 *tp) | |
5542 | { | |
f47c11ee DM |
5543 | spin_unlock_bh(&tp->lock); |
5544 | } | |
5545 | ||
fcfa0a32 MC |
5546 | /* One-shot MSI handler - Chip automatically disables interrupt |
5547 | * after sending MSI so driver doesn't have to do it. | |
5548 | */ | |
7d12e780 | 5549 | static irqreturn_t tg3_msi_1shot(int irq, void *dev_id) |
fcfa0a32 | 5550 | { |
09943a18 MC |
5551 | struct tg3_napi *tnapi = dev_id; |
5552 | struct tg3 *tp = tnapi->tp; | |
fcfa0a32 | 5553 | |
898a56f8 | 5554 | prefetch(tnapi->hw_status); |
0c1d0e2b MC |
5555 | if (tnapi->rx_rcb) |
5556 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); | |
fcfa0a32 MC |
5557 | |
5558 | if (likely(!tg3_irq_sync(tp))) | |
09943a18 | 5559 | napi_schedule(&tnapi->napi); |
fcfa0a32 MC |
5560 | |
5561 | return IRQ_HANDLED; | |
5562 | } | |
5563 | ||
88b06bc2 MC |
5564 | /* MSI ISR - No need to check for interrupt sharing and no need to |
5565 | * flush status block and interrupt mailbox. PCI ordering rules | |
5566 | * guarantee that MSI will arrive after the status block. | |
5567 | */ | |
7d12e780 | 5568 | static irqreturn_t tg3_msi(int irq, void *dev_id) |
88b06bc2 | 5569 | { |
09943a18 MC |
5570 | struct tg3_napi *tnapi = dev_id; |
5571 | struct tg3 *tp = tnapi->tp; | |
88b06bc2 | 5572 | |
898a56f8 | 5573 | prefetch(tnapi->hw_status); |
0c1d0e2b MC |
5574 | if (tnapi->rx_rcb) |
5575 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); | |
88b06bc2 | 5576 | /* |
fac9b83e | 5577 | * Writing any value to intr-mbox-0 clears PCI INTA# and |
88b06bc2 | 5578 | * chip-internal interrupt pending events. |
fac9b83e | 5579 | * Writing non-zero to intr-mbox-0 additional tells the |
88b06bc2 MC |
5580 | * NIC to stop sending us irqs, engaging "in-intr-handler" |
5581 | * event coalescing. | |
5582 | */ | |
5583 | tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); | |
61487480 | 5584 | if (likely(!tg3_irq_sync(tp))) |
09943a18 | 5585 | napi_schedule(&tnapi->napi); |
61487480 | 5586 | |
88b06bc2 MC |
5587 | return IRQ_RETVAL(1); |
5588 | } | |
5589 | ||
7d12e780 | 5590 | static irqreturn_t tg3_interrupt(int irq, void *dev_id) |
1da177e4 | 5591 | { |
09943a18 MC |
5592 | struct tg3_napi *tnapi = dev_id; |
5593 | struct tg3 *tp = tnapi->tp; | |
898a56f8 | 5594 | struct tg3_hw_status *sblk = tnapi->hw_status; |
1da177e4 LT |
5595 | unsigned int handled = 1; |
5596 | ||
1da177e4 LT |
5597 | /* In INTx mode, it is possible for the interrupt to arrive at |
5598 | * the CPU before the status block posted prior to the interrupt. | |
5599 | * Reading the PCI State register will confirm whether the | |
5600 | * interrupt is ours and will flush the status block. | |
5601 | */ | |
d18edcb2 | 5602 | if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) { |
63c3a66f | 5603 | if (tg3_flag(tp, CHIP_RESETTING) || |
d18edcb2 MC |
5604 | (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { |
5605 | handled = 0; | |
f47c11ee | 5606 | goto out; |
fac9b83e | 5607 | } |
d18edcb2 MC |
5608 | } |
5609 | ||
5610 | /* | |
5611 | * Writing any value to intr-mbox-0 clears PCI INTA# and | |
5612 | * chip-internal interrupt pending events. | |
5613 | * Writing non-zero to intr-mbox-0 additional tells the | |
5614 | * NIC to stop sending us irqs, engaging "in-intr-handler" | |
5615 | * event coalescing. | |
c04cb347 MC |
5616 | * |
5617 | * Flush the mailbox to de-assert the IRQ immediately to prevent | |
5618 | * spurious interrupts. The flush impacts performance but | |
5619 | * excessive spurious interrupts can be worse in some cases. | |
d18edcb2 | 5620 | */ |
c04cb347 | 5621 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); |
d18edcb2 MC |
5622 | if (tg3_irq_sync(tp)) |
5623 | goto out; | |
5624 | sblk->status &= ~SD_STATUS_UPDATED; | |
17375d25 | 5625 | if (likely(tg3_has_work(tnapi))) { |
72334482 | 5626 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); |
09943a18 | 5627 | napi_schedule(&tnapi->napi); |
d18edcb2 MC |
5628 | } else { |
5629 | /* No work, shared interrupt perhaps? re-enable | |
5630 | * interrupts, and flush that PCI write | |
5631 | */ | |
5632 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, | |
5633 | 0x00000000); | |
fac9b83e | 5634 | } |
f47c11ee | 5635 | out: |
fac9b83e DM |
5636 | return IRQ_RETVAL(handled); |
5637 | } | |
5638 | ||
7d12e780 | 5639 | static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id) |
fac9b83e | 5640 | { |
09943a18 MC |
5641 | struct tg3_napi *tnapi = dev_id; |
5642 | struct tg3 *tp = tnapi->tp; | |
898a56f8 | 5643 | struct tg3_hw_status *sblk = tnapi->hw_status; |
fac9b83e DM |
5644 | unsigned int handled = 1; |
5645 | ||
fac9b83e DM |
5646 | /* In INTx mode, it is possible for the interrupt to arrive at |
5647 | * the CPU before the status block posted prior to the interrupt. | |
5648 | * Reading the PCI State register will confirm whether the | |
5649 | * interrupt is ours and will flush the status block. | |
5650 | */ | |
898a56f8 | 5651 | if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) { |
63c3a66f | 5652 | if (tg3_flag(tp, CHIP_RESETTING) || |
d18edcb2 MC |
5653 | (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { |
5654 | handled = 0; | |
f47c11ee | 5655 | goto out; |
1da177e4 | 5656 | } |
d18edcb2 MC |
5657 | } |
5658 | ||
5659 | /* | |
5660 | * writing any value to intr-mbox-0 clears PCI INTA# and | |
5661 | * chip-internal interrupt pending events. | |
5662 | * writing non-zero to intr-mbox-0 additional tells the | |
5663 | * NIC to stop sending us irqs, engaging "in-intr-handler" | |
5664 | * event coalescing. | |
c04cb347 MC |
5665 | * |
5666 | * Flush the mailbox to de-assert the IRQ immediately to prevent | |
5667 | * spurious interrupts. The flush impacts performance but | |
5668 | * excessive spurious interrupts can be worse in some cases. | |
d18edcb2 | 5669 | */ |
c04cb347 | 5670 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); |
624f8e50 MC |
5671 | |
5672 | /* | |
5673 | * In a shared interrupt configuration, sometimes other devices' | |
5674 | * interrupts will scream. We record the current status tag here | |
5675 | * so that the above check can report that the screaming interrupts | |
5676 | * are unhandled. Eventually they will be silenced. | |
5677 | */ | |
898a56f8 | 5678 | tnapi->last_irq_tag = sblk->status_tag; |
624f8e50 | 5679 | |
d18edcb2 MC |
5680 | if (tg3_irq_sync(tp)) |
5681 | goto out; | |
624f8e50 | 5682 | |
72334482 | 5683 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); |
624f8e50 | 5684 | |
09943a18 | 5685 | napi_schedule(&tnapi->napi); |
624f8e50 | 5686 | |
f47c11ee | 5687 | out: |
1da177e4 LT |
5688 | return IRQ_RETVAL(handled); |
5689 | } | |
5690 | ||
7938109f | 5691 | /* ISR for interrupt test */ |
7d12e780 | 5692 | static irqreturn_t tg3_test_isr(int irq, void *dev_id) |
7938109f | 5693 | { |
09943a18 MC |
5694 | struct tg3_napi *tnapi = dev_id; |
5695 | struct tg3 *tp = tnapi->tp; | |
898a56f8 | 5696 | struct tg3_hw_status *sblk = tnapi->hw_status; |
7938109f | 5697 | |
f9804ddb MC |
5698 | if ((sblk->status & SD_STATUS_UPDATED) || |
5699 | !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { | |
b16250e3 | 5700 | tg3_disable_ints(tp); |
7938109f MC |
5701 | return IRQ_RETVAL(1); |
5702 | } | |
5703 | return IRQ_RETVAL(0); | |
5704 | } | |
5705 | ||
8e7a22e3 | 5706 | static int tg3_init_hw(struct tg3 *, int); |
944d980e | 5707 | static int tg3_halt(struct tg3 *, int, int); |
1da177e4 | 5708 | |
b9ec6c1b MC |
5709 | /* Restart hardware after configuration changes, self-test, etc. |
5710 | * Invoked with tp->lock held. | |
5711 | */ | |
5712 | static int tg3_restart_hw(struct tg3 *tp, int reset_phy) | |
78c6146f ED |
5713 | __releases(tp->lock) |
5714 | __acquires(tp->lock) | |
b9ec6c1b MC |
5715 | { |
5716 | int err; | |
5717 | ||
5718 | err = tg3_init_hw(tp, reset_phy); | |
5719 | if (err) { | |
5129c3a3 MC |
5720 | netdev_err(tp->dev, |
5721 | "Failed to re-initialize device, aborting\n"); | |
b9ec6c1b MC |
5722 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
5723 | tg3_full_unlock(tp); | |
5724 | del_timer_sync(&tp->timer); | |
5725 | tp->irq_sync = 0; | |
fed97810 | 5726 | tg3_napi_enable(tp); |
b9ec6c1b MC |
5727 | dev_close(tp->dev); |
5728 | tg3_full_lock(tp, 0); | |
5729 | } | |
5730 | return err; | |
5731 | } | |
5732 | ||
1da177e4 LT |
5733 | #ifdef CONFIG_NET_POLL_CONTROLLER |
5734 | static void tg3_poll_controller(struct net_device *dev) | |
5735 | { | |
4f125f42 | 5736 | int i; |
88b06bc2 MC |
5737 | struct tg3 *tp = netdev_priv(dev); |
5738 | ||
4f125f42 | 5739 | for (i = 0; i < tp->irq_cnt; i++) |
fe234f0e | 5740 | tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]); |
1da177e4 LT |
5741 | } |
5742 | #endif | |
5743 | ||
c4028958 | 5744 | static void tg3_reset_task(struct work_struct *work) |
1da177e4 | 5745 | { |
c4028958 | 5746 | struct tg3 *tp = container_of(work, struct tg3, reset_task); |
b02fd9e3 | 5747 | int err; |
1da177e4 LT |
5748 | unsigned int restart_timer; |
5749 | ||
7faa006f | 5750 | tg3_full_lock(tp, 0); |
7faa006f MC |
5751 | |
5752 | if (!netif_running(tp->dev)) { | |
7faa006f MC |
5753 | tg3_full_unlock(tp); |
5754 | return; | |
5755 | } | |
5756 | ||
5757 | tg3_full_unlock(tp); | |
5758 | ||
b02fd9e3 MC |
5759 | tg3_phy_stop(tp); |
5760 | ||
1da177e4 LT |
5761 | tg3_netif_stop(tp); |
5762 | ||
f47c11ee | 5763 | tg3_full_lock(tp, 1); |
1da177e4 | 5764 | |
63c3a66f JP |
5765 | restart_timer = tg3_flag(tp, RESTART_TIMER); |
5766 | tg3_flag_clear(tp, RESTART_TIMER); | |
1da177e4 | 5767 | |
63c3a66f | 5768 | if (tg3_flag(tp, TX_RECOVERY_PENDING)) { |
df3e6548 MC |
5769 | tp->write32_tx_mbox = tg3_write32_tx_mbox; |
5770 | tp->write32_rx_mbox = tg3_write_flush_reg32; | |
63c3a66f JP |
5771 | tg3_flag_set(tp, MBOX_WRITE_REORDER); |
5772 | tg3_flag_clear(tp, TX_RECOVERY_PENDING); | |
df3e6548 MC |
5773 | } |
5774 | ||
944d980e | 5775 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); |
b02fd9e3 MC |
5776 | err = tg3_init_hw(tp, 1); |
5777 | if (err) | |
b9ec6c1b | 5778 | goto out; |
1da177e4 LT |
5779 | |
5780 | tg3_netif_start(tp); | |
5781 | ||
1da177e4 LT |
5782 | if (restart_timer) |
5783 | mod_timer(&tp->timer, jiffies + 1); | |
7faa006f | 5784 | |
b9ec6c1b | 5785 | out: |
7faa006f | 5786 | tg3_full_unlock(tp); |
b02fd9e3 MC |
5787 | |
5788 | if (!err) | |
5789 | tg3_phy_start(tp); | |
1da177e4 LT |
5790 | } |
5791 | ||
5792 | static void tg3_tx_timeout(struct net_device *dev) | |
5793 | { | |
5794 | struct tg3 *tp = netdev_priv(dev); | |
5795 | ||
b0408751 | 5796 | if (netif_msg_tx_err(tp)) { |
05dbe005 | 5797 | netdev_err(dev, "transmit timed out, resetting\n"); |
97bd8e49 | 5798 | tg3_dump_state(tp); |
b0408751 | 5799 | } |
1da177e4 LT |
5800 | |
5801 | schedule_work(&tp->reset_task); | |
5802 | } | |
5803 | ||
c58ec932 MC |
5804 | /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */ |
5805 | static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len) | |
5806 | { | |
5807 | u32 base = (u32) mapping & 0xffffffff; | |
5808 | ||
807540ba | 5809 | return (base > 0xffffdcc0) && (base + len + 8 < base); |
c58ec932 MC |
5810 | } |
5811 | ||
72f2afb8 MC |
5812 | /* Test for DMA addresses > 40-bit */ |
5813 | static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping, | |
5814 | int len) | |
5815 | { | |
5816 | #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64) | |
63c3a66f | 5817 | if (tg3_flag(tp, 40BIT_DMA_BUG)) |
807540ba | 5818 | return ((u64) mapping + len) > DMA_BIT_MASK(40); |
72f2afb8 MC |
5819 | return 0; |
5820 | #else | |
5821 | return 0; | |
5822 | #endif | |
5823 | } | |
5824 | ||
2ffcc981 MC |
5825 | static void tg3_set_txd(struct tg3_napi *tnapi, int entry, |
5826 | dma_addr_t mapping, int len, u32 flags, | |
5827 | u32 mss_and_is_end) | |
5828 | { | |
5829 | struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry]; | |
5830 | int is_end = (mss_and_is_end & 0x1); | |
5831 | u32 mss = (mss_and_is_end >> 1); | |
5832 | u32 vlan_tag = 0; | |
5833 | ||
5834 | if (is_end) | |
5835 | flags |= TXD_FLAG_END; | |
5836 | if (flags & TXD_FLAG_VLAN) { | |
5837 | vlan_tag = flags >> 16; | |
5838 | flags &= 0xffff; | |
5839 | } | |
5840 | vlan_tag |= (mss << TXD_MSS_SHIFT); | |
5841 | ||
5842 | txd->addr_hi = ((u64) mapping >> 32); | |
5843 | txd->addr_lo = ((u64) mapping & 0xffffffff); | |
5844 | txd->len_flags = (len << TXD_LEN_SHIFT) | flags; | |
5845 | txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT; | |
5846 | } | |
1da177e4 | 5847 | |
432aa7ed MC |
5848 | static void tg3_skb_error_unmap(struct tg3_napi *tnapi, |
5849 | struct sk_buff *skb, int last) | |
5850 | { | |
5851 | int i; | |
5852 | u32 entry = tnapi->tx_prod; | |
5853 | struct ring_info *txb = &tnapi->tx_buffers[entry]; | |
5854 | ||
5855 | pci_unmap_single(tnapi->tp->pdev, | |
5856 | dma_unmap_addr(txb, mapping), | |
5857 | skb_headlen(skb), | |
5858 | PCI_DMA_TODEVICE); | |
9a2e0fb0 | 5859 | for (i = 0; i < last; i++) { |
432aa7ed MC |
5860 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
5861 | ||
5862 | entry = NEXT_TX(entry); | |
5863 | txb = &tnapi->tx_buffers[entry]; | |
5864 | ||
5865 | pci_unmap_page(tnapi->tp->pdev, | |
5866 | dma_unmap_addr(txb, mapping), | |
5867 | frag->size, PCI_DMA_TODEVICE); | |
5868 | } | |
5869 | } | |
5870 | ||
72f2afb8 | 5871 | /* Workaround 4GB and 40-bit hardware DMA bugs. */ |
24f4efd4 | 5872 | static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi, |
432aa7ed MC |
5873 | struct sk_buff *skb, |
5874 | u32 base_flags, u32 mss) | |
1da177e4 | 5875 | { |
24f4efd4 | 5876 | struct tg3 *tp = tnapi->tp; |
41588ba1 | 5877 | struct sk_buff *new_skb; |
c58ec932 | 5878 | dma_addr_t new_addr = 0; |
432aa7ed MC |
5879 | u32 entry = tnapi->tx_prod; |
5880 | int ret = 0; | |
1da177e4 | 5881 | |
41588ba1 MC |
5882 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) |
5883 | new_skb = skb_copy(skb, GFP_ATOMIC); | |
5884 | else { | |
5885 | int more_headroom = 4 - ((unsigned long)skb->data & 3); | |
5886 | ||
5887 | new_skb = skb_copy_expand(skb, | |
5888 | skb_headroom(skb) + more_headroom, | |
5889 | skb_tailroom(skb), GFP_ATOMIC); | |
5890 | } | |
5891 | ||
1da177e4 | 5892 | if (!new_skb) { |
c58ec932 MC |
5893 | ret = -1; |
5894 | } else { | |
5895 | /* New SKB is guaranteed to be linear. */ | |
f4188d8a AD |
5896 | new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len, |
5897 | PCI_DMA_TODEVICE); | |
5898 | /* Make sure the mapping succeeded */ | |
5899 | if (pci_dma_mapping_error(tp->pdev, new_addr)) { | |
5900 | ret = -1; | |
5901 | dev_kfree_skb(new_skb); | |
90079ce8 | 5902 | |
c58ec932 MC |
5903 | /* Make sure new skb does not cross any 4G boundaries. |
5904 | * Drop the packet if it does. | |
5905 | */ | |
eb69d564 | 5906 | } else if (tg3_4g_overflow_test(new_addr, new_skb->len)) { |
f4188d8a AD |
5907 | pci_unmap_single(tp->pdev, new_addr, new_skb->len, |
5908 | PCI_DMA_TODEVICE); | |
c58ec932 MC |
5909 | ret = -1; |
5910 | dev_kfree_skb(new_skb); | |
c58ec932 | 5911 | } else { |
432aa7ed MC |
5912 | tnapi->tx_buffers[entry].skb = new_skb; |
5913 | dma_unmap_addr_set(&tnapi->tx_buffers[entry], | |
5914 | mapping, new_addr); | |
5915 | ||
f3f3f27e | 5916 | tg3_set_txd(tnapi, entry, new_addr, new_skb->len, |
c58ec932 | 5917 | base_flags, 1 | (mss << 1)); |
f4188d8a | 5918 | } |
1da177e4 LT |
5919 | } |
5920 | ||
5921 | dev_kfree_skb(skb); | |
5922 | ||
c58ec932 | 5923 | return ret; |
1da177e4 LT |
5924 | } |
5925 | ||
2ffcc981 | 5926 | static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *); |
52c0fd83 MC |
5927 | |
5928 | /* Use GSO to workaround a rare TSO bug that may be triggered when the | |
5929 | * TSO header is greater than 80 bytes. | |
5930 | */ | |
5931 | static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb) | |
5932 | { | |
5933 | struct sk_buff *segs, *nskb; | |
f3f3f27e | 5934 | u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3; |
52c0fd83 MC |
5935 | |
5936 | /* Estimate the number of fragments in the worst case */ | |
f3f3f27e | 5937 | if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) { |
52c0fd83 | 5938 | netif_stop_queue(tp->dev); |
f65aac16 MC |
5939 | |
5940 | /* netif_tx_stop_queue() must be done before checking | |
5941 | * checking tx index in tg3_tx_avail() below, because in | |
5942 | * tg3_tx(), we update tx index before checking for | |
5943 | * netif_tx_queue_stopped(). | |
5944 | */ | |
5945 | smp_mb(); | |
f3f3f27e | 5946 | if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est) |
7f62ad5d MC |
5947 | return NETDEV_TX_BUSY; |
5948 | ||
5949 | netif_wake_queue(tp->dev); | |
52c0fd83 MC |
5950 | } |
5951 | ||
5952 | segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO); | |
801678c5 | 5953 | if (IS_ERR(segs)) |
52c0fd83 MC |
5954 | goto tg3_tso_bug_end; |
5955 | ||
5956 | do { | |
5957 | nskb = segs; | |
5958 | segs = segs->next; | |
5959 | nskb->next = NULL; | |
2ffcc981 | 5960 | tg3_start_xmit(nskb, tp->dev); |
52c0fd83 MC |
5961 | } while (segs); |
5962 | ||
5963 | tg3_tso_bug_end: | |
5964 | dev_kfree_skb(skb); | |
5965 | ||
5966 | return NETDEV_TX_OK; | |
5967 | } | |
52c0fd83 | 5968 | |
5a6f3074 | 5969 | /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and |
63c3a66f | 5970 | * support TG3_FLAG_HW_TSO_1 or firmware TSO only. |
5a6f3074 | 5971 | */ |
2ffcc981 | 5972 | static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev) |
1da177e4 LT |
5973 | { |
5974 | struct tg3 *tp = netdev_priv(dev); | |
1da177e4 | 5975 | u32 len, entry, base_flags, mss; |
432aa7ed | 5976 | int i = -1, would_hit_hwbug; |
90079ce8 | 5977 | dma_addr_t mapping; |
24f4efd4 MC |
5978 | struct tg3_napi *tnapi; |
5979 | struct netdev_queue *txq; | |
432aa7ed | 5980 | unsigned int last; |
f4188d8a | 5981 | |
24f4efd4 MC |
5982 | txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb)); |
5983 | tnapi = &tp->napi[skb_get_queue_mapping(skb)]; | |
63c3a66f | 5984 | if (tg3_flag(tp, ENABLE_TSS)) |
24f4efd4 | 5985 | tnapi++; |
1da177e4 | 5986 | |
00b70504 | 5987 | /* We are running in BH disabled context with netif_tx_lock |
bea3348e | 5988 | * and TX reclaim runs via tp->napi.poll inside of a software |
f47c11ee DM |
5989 | * interrupt. Furthermore, IRQ processing runs lockless so we have |
5990 | * no IRQ context deadlocks to worry about either. Rejoice! | |
1da177e4 | 5991 | */ |
f3f3f27e | 5992 | if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) { |
24f4efd4 MC |
5993 | if (!netif_tx_queue_stopped(txq)) { |
5994 | netif_tx_stop_queue(txq); | |
1f064a87 SH |
5995 | |
5996 | /* This is a hard error, log it. */ | |
5129c3a3 MC |
5997 | netdev_err(dev, |
5998 | "BUG! Tx Ring full when queue awake!\n"); | |
1f064a87 | 5999 | } |
1da177e4 LT |
6000 | return NETDEV_TX_BUSY; |
6001 | } | |
6002 | ||
f3f3f27e | 6003 | entry = tnapi->tx_prod; |
1da177e4 | 6004 | base_flags = 0; |
84fa7933 | 6005 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
1da177e4 | 6006 | base_flags |= TXD_FLAG_TCPUDP_CSUM; |
24f4efd4 | 6007 | |
be98da6a MC |
6008 | mss = skb_shinfo(skb)->gso_size; |
6009 | if (mss) { | |
eddc9ec5 | 6010 | struct iphdr *iph; |
34195c3d | 6011 | u32 tcp_opt_len, hdr_len; |
1da177e4 LT |
6012 | |
6013 | if (skb_header_cloned(skb) && | |
6014 | pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) { | |
6015 | dev_kfree_skb(skb); | |
6016 | goto out_unlock; | |
6017 | } | |
6018 | ||
34195c3d | 6019 | iph = ip_hdr(skb); |
ab6a5bb6 | 6020 | tcp_opt_len = tcp_optlen(skb); |
1da177e4 | 6021 | |
02e96080 | 6022 | if (skb_is_gso_v6(skb)) { |
34195c3d MC |
6023 | hdr_len = skb_headlen(skb) - ETH_HLEN; |
6024 | } else { | |
6025 | u32 ip_tcp_len; | |
6026 | ||
6027 | ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr); | |
6028 | hdr_len = ip_tcp_len + tcp_opt_len; | |
6029 | ||
6030 | iph->check = 0; | |
6031 | iph->tot_len = htons(mss + hdr_len); | |
6032 | } | |
6033 | ||
52c0fd83 | 6034 | if (unlikely((ETH_HLEN + hdr_len) > 80) && |
63c3a66f | 6035 | tg3_flag(tp, TSO_BUG)) |
de6f31eb | 6036 | return tg3_tso_bug(tp, skb); |
52c0fd83 | 6037 | |
1da177e4 LT |
6038 | base_flags |= (TXD_FLAG_CPU_PRE_DMA | |
6039 | TXD_FLAG_CPU_POST_DMA); | |
6040 | ||
63c3a66f JP |
6041 | if (tg3_flag(tp, HW_TSO_1) || |
6042 | tg3_flag(tp, HW_TSO_2) || | |
6043 | tg3_flag(tp, HW_TSO_3)) { | |
aa8223c7 | 6044 | tcp_hdr(skb)->check = 0; |
1da177e4 | 6045 | base_flags &= ~TXD_FLAG_TCPUDP_CSUM; |
aa8223c7 ACM |
6046 | } else |
6047 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
6048 | iph->daddr, 0, | |
6049 | IPPROTO_TCP, | |
6050 | 0); | |
1da177e4 | 6051 | |
63c3a66f | 6052 | if (tg3_flag(tp, HW_TSO_3)) { |
615774fe MC |
6053 | mss |= (hdr_len & 0xc) << 12; |
6054 | if (hdr_len & 0x10) | |
6055 | base_flags |= 0x00000010; | |
6056 | base_flags |= (hdr_len & 0x3e0) << 5; | |
63c3a66f | 6057 | } else if (tg3_flag(tp, HW_TSO_2)) |
92c6b8d1 | 6058 | mss |= hdr_len << 9; |
63c3a66f | 6059 | else if (tg3_flag(tp, HW_TSO_1) || |
92c6b8d1 | 6060 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { |
eddc9ec5 | 6061 | if (tcp_opt_len || iph->ihl > 5) { |
1da177e4 LT |
6062 | int tsflags; |
6063 | ||
eddc9ec5 | 6064 | tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); |
1da177e4 LT |
6065 | mss |= (tsflags << 11); |
6066 | } | |
6067 | } else { | |
eddc9ec5 | 6068 | if (tcp_opt_len || iph->ihl > 5) { |
1da177e4 LT |
6069 | int tsflags; |
6070 | ||
eddc9ec5 | 6071 | tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); |
1da177e4 LT |
6072 | base_flags |= tsflags << 12; |
6073 | } | |
6074 | } | |
6075 | } | |
bf933c80 | 6076 | |
eab6d18d | 6077 | if (vlan_tx_tag_present(skb)) |
1da177e4 LT |
6078 | base_flags |= (TXD_FLAG_VLAN | |
6079 | (vlan_tx_tag_get(skb) << 16)); | |
1da177e4 | 6080 | |
63c3a66f | 6081 | if (tg3_flag(tp, USE_JUMBO_BDFLAG) && |
8fc2f995 | 6082 | !mss && skb->len > VLAN_ETH_FRAME_LEN) |
615774fe MC |
6083 | base_flags |= TXD_FLAG_JMB_PKT; |
6084 | ||
f4188d8a AD |
6085 | len = skb_headlen(skb); |
6086 | ||
6087 | mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE); | |
6088 | if (pci_dma_mapping_error(tp->pdev, mapping)) { | |
90079ce8 DM |
6089 | dev_kfree_skb(skb); |
6090 | goto out_unlock; | |
6091 | } | |
6092 | ||
f3f3f27e | 6093 | tnapi->tx_buffers[entry].skb = skb; |
4e5e4f0d | 6094 | dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping); |
1da177e4 LT |
6095 | |
6096 | would_hit_hwbug = 0; | |
6097 | ||
63c3a66f | 6098 | if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8) |
92c6b8d1 MC |
6099 | would_hit_hwbug = 1; |
6100 | ||
eb69d564 | 6101 | if (tg3_4g_overflow_test(mapping, len)) |
0e1406dd MC |
6102 | would_hit_hwbug = 1; |
6103 | ||
daf9a553 | 6104 | if (tg3_40bit_overflow_test(tp, mapping, len)) |
41588ba1 | 6105 | would_hit_hwbug = 1; |
0e1406dd | 6106 | |
63c3a66f | 6107 | if (tg3_flag(tp, 5701_DMA_BUG)) |
c58ec932 | 6108 | would_hit_hwbug = 1; |
1da177e4 | 6109 | |
f3f3f27e | 6110 | tg3_set_txd(tnapi, entry, mapping, len, base_flags, |
1da177e4 LT |
6111 | (skb_shinfo(skb)->nr_frags == 0) | (mss << 1)); |
6112 | ||
6113 | entry = NEXT_TX(entry); | |
6114 | ||
6115 | /* Now loop through additional data fragments, and queue them. */ | |
6116 | if (skb_shinfo(skb)->nr_frags > 0) { | |
1da177e4 LT |
6117 | last = skb_shinfo(skb)->nr_frags - 1; |
6118 | for (i = 0; i <= last; i++) { | |
6119 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
6120 | ||
6121 | len = frag->size; | |
f4188d8a AD |
6122 | mapping = pci_map_page(tp->pdev, |
6123 | frag->page, | |
6124 | frag->page_offset, | |
6125 | len, PCI_DMA_TODEVICE); | |
1da177e4 | 6126 | |
f3f3f27e | 6127 | tnapi->tx_buffers[entry].skb = NULL; |
4e5e4f0d | 6128 | dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, |
f4188d8a AD |
6129 | mapping); |
6130 | if (pci_dma_mapping_error(tp->pdev, mapping)) | |
6131 | goto dma_error; | |
1da177e4 | 6132 | |
63c3a66f | 6133 | if (tg3_flag(tp, SHORT_DMA_BUG) && |
92c6b8d1 MC |
6134 | len <= 8) |
6135 | would_hit_hwbug = 1; | |
6136 | ||
eb69d564 | 6137 | if (tg3_4g_overflow_test(mapping, len)) |
c58ec932 | 6138 | would_hit_hwbug = 1; |
1da177e4 | 6139 | |
daf9a553 | 6140 | if (tg3_40bit_overflow_test(tp, mapping, len)) |
72f2afb8 MC |
6141 | would_hit_hwbug = 1; |
6142 | ||
63c3a66f JP |
6143 | if (tg3_flag(tp, HW_TSO_1) || |
6144 | tg3_flag(tp, HW_TSO_2) || | |
6145 | tg3_flag(tp, HW_TSO_3)) | |
f3f3f27e | 6146 | tg3_set_txd(tnapi, entry, mapping, len, |
1da177e4 LT |
6147 | base_flags, (i == last)|(mss << 1)); |
6148 | else | |
f3f3f27e | 6149 | tg3_set_txd(tnapi, entry, mapping, len, |
1da177e4 LT |
6150 | base_flags, (i == last)); |
6151 | ||
6152 | entry = NEXT_TX(entry); | |
6153 | } | |
6154 | } | |
6155 | ||
6156 | if (would_hit_hwbug) { | |
432aa7ed | 6157 | tg3_skb_error_unmap(tnapi, skb, i); |
1da177e4 LT |
6158 | |
6159 | /* If the workaround fails due to memory/mapping | |
6160 | * failure, silently drop this packet. | |
6161 | */ | |
432aa7ed | 6162 | if (tigon3_dma_hwbug_workaround(tnapi, skb, base_flags, mss)) |
1da177e4 LT |
6163 | goto out_unlock; |
6164 | ||
432aa7ed | 6165 | entry = NEXT_TX(tnapi->tx_prod); |
1da177e4 LT |
6166 | } |
6167 | ||
d515b450 RC |
6168 | skb_tx_timestamp(skb); |
6169 | ||
1da177e4 | 6170 | /* Packets are ready, update Tx producer idx local and on card. */ |
24f4efd4 | 6171 | tw32_tx_mbox(tnapi->prodmbox, entry); |
1da177e4 | 6172 | |
f3f3f27e MC |
6173 | tnapi->tx_prod = entry; |
6174 | if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) { | |
24f4efd4 | 6175 | netif_tx_stop_queue(txq); |
f65aac16 MC |
6176 | |
6177 | /* netif_tx_stop_queue() must be done before checking | |
6178 | * checking tx index in tg3_tx_avail() below, because in | |
6179 | * tg3_tx(), we update tx index before checking for | |
6180 | * netif_tx_queue_stopped(). | |
6181 | */ | |
6182 | smp_mb(); | |
f3f3f27e | 6183 | if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)) |
24f4efd4 | 6184 | netif_tx_wake_queue(txq); |
51b91468 | 6185 | } |
1da177e4 LT |
6186 | |
6187 | out_unlock: | |
cdd0db05 | 6188 | mmiowb(); |
1da177e4 LT |
6189 | |
6190 | return NETDEV_TX_OK; | |
f4188d8a AD |
6191 | |
6192 | dma_error: | |
432aa7ed | 6193 | tg3_skb_error_unmap(tnapi, skb, i); |
f4188d8a | 6194 | dev_kfree_skb(skb); |
432aa7ed | 6195 | tnapi->tx_buffers[tnapi->tx_prod].skb = NULL; |
f4188d8a | 6196 | return NETDEV_TX_OK; |
1da177e4 LT |
6197 | } |
6198 | ||
06c03c02 MB |
6199 | static void tg3_set_loopback(struct net_device *dev, u32 features) |
6200 | { | |
6201 | struct tg3 *tp = netdev_priv(dev); | |
6202 | ||
6203 | if (features & NETIF_F_LOOPBACK) { | |
6204 | if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK) | |
6205 | return; | |
6206 | ||
6207 | /* | |
6208 | * Clear MAC_MODE_HALF_DUPLEX or you won't get packets back in | |
6209 | * loopback mode if Half-Duplex mode was negotiated earlier. | |
6210 | */ | |
6211 | tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; | |
6212 | ||
6213 | /* Enable internal MAC loopback mode */ | |
6214 | tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK; | |
6215 | spin_lock_bh(&tp->lock); | |
6216 | tw32(MAC_MODE, tp->mac_mode); | |
6217 | netif_carrier_on(tp->dev); | |
6218 | spin_unlock_bh(&tp->lock); | |
6219 | netdev_info(dev, "Internal MAC loopback mode enabled.\n"); | |
6220 | } else { | |
6221 | if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) | |
6222 | return; | |
6223 | ||
6224 | /* Disable internal MAC loopback mode */ | |
6225 | tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK; | |
6226 | spin_lock_bh(&tp->lock); | |
6227 | tw32(MAC_MODE, tp->mac_mode); | |
6228 | /* Force link status check */ | |
6229 | tg3_setup_phy(tp, 1); | |
6230 | spin_unlock_bh(&tp->lock); | |
6231 | netdev_info(dev, "Internal MAC loopback mode disabled.\n"); | |
6232 | } | |
6233 | } | |
6234 | ||
dc668910 MM |
6235 | static u32 tg3_fix_features(struct net_device *dev, u32 features) |
6236 | { | |
6237 | struct tg3 *tp = netdev_priv(dev); | |
6238 | ||
63c3a66f | 6239 | if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS)) |
dc668910 MM |
6240 | features &= ~NETIF_F_ALL_TSO; |
6241 | ||
6242 | return features; | |
6243 | } | |
6244 | ||
06c03c02 MB |
6245 | static int tg3_set_features(struct net_device *dev, u32 features) |
6246 | { | |
6247 | u32 changed = dev->features ^ features; | |
6248 | ||
6249 | if ((changed & NETIF_F_LOOPBACK) && netif_running(dev)) | |
6250 | tg3_set_loopback(dev, features); | |
6251 | ||
6252 | return 0; | |
6253 | } | |
6254 | ||
1da177e4 LT |
6255 | static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp, |
6256 | int new_mtu) | |
6257 | { | |
6258 | dev->mtu = new_mtu; | |
6259 | ||
ef7f5ec0 | 6260 | if (new_mtu > ETH_DATA_LEN) { |
63c3a66f | 6261 | if (tg3_flag(tp, 5780_CLASS)) { |
dc668910 | 6262 | netdev_update_features(dev); |
63c3a66f | 6263 | tg3_flag_clear(tp, TSO_CAPABLE); |
859a5887 | 6264 | } else { |
63c3a66f | 6265 | tg3_flag_set(tp, JUMBO_RING_ENABLE); |
859a5887 | 6266 | } |
ef7f5ec0 | 6267 | } else { |
63c3a66f JP |
6268 | if (tg3_flag(tp, 5780_CLASS)) { |
6269 | tg3_flag_set(tp, TSO_CAPABLE); | |
dc668910 MM |
6270 | netdev_update_features(dev); |
6271 | } | |
63c3a66f | 6272 | tg3_flag_clear(tp, JUMBO_RING_ENABLE); |
ef7f5ec0 | 6273 | } |
1da177e4 LT |
6274 | } |
6275 | ||
6276 | static int tg3_change_mtu(struct net_device *dev, int new_mtu) | |
6277 | { | |
6278 | struct tg3 *tp = netdev_priv(dev); | |
b9ec6c1b | 6279 | int err; |
1da177e4 LT |
6280 | |
6281 | if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp)) | |
6282 | return -EINVAL; | |
6283 | ||
6284 | if (!netif_running(dev)) { | |
6285 | /* We'll just catch it later when the | |
6286 | * device is up'd. | |
6287 | */ | |
6288 | tg3_set_mtu(dev, tp, new_mtu); | |
6289 | return 0; | |
6290 | } | |
6291 | ||
b02fd9e3 MC |
6292 | tg3_phy_stop(tp); |
6293 | ||
1da177e4 | 6294 | tg3_netif_stop(tp); |
f47c11ee DM |
6295 | |
6296 | tg3_full_lock(tp, 1); | |
1da177e4 | 6297 | |
944d980e | 6298 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 LT |
6299 | |
6300 | tg3_set_mtu(dev, tp, new_mtu); | |
6301 | ||
b9ec6c1b | 6302 | err = tg3_restart_hw(tp, 0); |
1da177e4 | 6303 | |
b9ec6c1b MC |
6304 | if (!err) |
6305 | tg3_netif_start(tp); | |
1da177e4 | 6306 | |
f47c11ee | 6307 | tg3_full_unlock(tp); |
1da177e4 | 6308 | |
b02fd9e3 MC |
6309 | if (!err) |
6310 | tg3_phy_start(tp); | |
6311 | ||
b9ec6c1b | 6312 | return err; |
1da177e4 LT |
6313 | } |
6314 | ||
21f581a5 MC |
6315 | static void tg3_rx_prodring_free(struct tg3 *tp, |
6316 | struct tg3_rx_prodring_set *tpr) | |
1da177e4 | 6317 | { |
1da177e4 LT |
6318 | int i; |
6319 | ||
8fea32b9 | 6320 | if (tpr != &tp->napi[0].prodring) { |
b196c7e4 | 6321 | for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx; |
2c49a44d | 6322 | i = (i + 1) & tp->rx_std_ring_mask) |
b196c7e4 MC |
6323 | tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i], |
6324 | tp->rx_pkt_map_sz); | |
6325 | ||
63c3a66f | 6326 | if (tg3_flag(tp, JUMBO_CAPABLE)) { |
b196c7e4 MC |
6327 | for (i = tpr->rx_jmb_cons_idx; |
6328 | i != tpr->rx_jmb_prod_idx; | |
2c49a44d | 6329 | i = (i + 1) & tp->rx_jmb_ring_mask) { |
b196c7e4 MC |
6330 | tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i], |
6331 | TG3_RX_JMB_MAP_SZ); | |
6332 | } | |
6333 | } | |
6334 | ||
2b2cdb65 | 6335 | return; |
b196c7e4 | 6336 | } |
1da177e4 | 6337 | |
2c49a44d | 6338 | for (i = 0; i <= tp->rx_std_ring_mask; i++) |
2b2cdb65 MC |
6339 | tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i], |
6340 | tp->rx_pkt_map_sz); | |
1da177e4 | 6341 | |
63c3a66f | 6342 | if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) { |
2c49a44d | 6343 | for (i = 0; i <= tp->rx_jmb_ring_mask; i++) |
2b2cdb65 MC |
6344 | tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i], |
6345 | TG3_RX_JMB_MAP_SZ); | |
1da177e4 LT |
6346 | } |
6347 | } | |
6348 | ||
c6cdf436 | 6349 | /* Initialize rx rings for packet processing. |
1da177e4 LT |
6350 | * |
6351 | * The chip has been shut down and the driver detached from | |
6352 | * the networking, so no interrupts or new tx packets will | |
6353 | * end up in the driver. tp->{tx,}lock are held and thus | |
6354 | * we may not sleep. | |
6355 | */ | |
21f581a5 MC |
6356 | static int tg3_rx_prodring_alloc(struct tg3 *tp, |
6357 | struct tg3_rx_prodring_set *tpr) | |
1da177e4 | 6358 | { |
287be12e | 6359 | u32 i, rx_pkt_dma_sz; |
1da177e4 | 6360 | |
b196c7e4 MC |
6361 | tpr->rx_std_cons_idx = 0; |
6362 | tpr->rx_std_prod_idx = 0; | |
6363 | tpr->rx_jmb_cons_idx = 0; | |
6364 | tpr->rx_jmb_prod_idx = 0; | |
6365 | ||
8fea32b9 | 6366 | if (tpr != &tp->napi[0].prodring) { |
2c49a44d MC |
6367 | memset(&tpr->rx_std_buffers[0], 0, |
6368 | TG3_RX_STD_BUFF_RING_SIZE(tp)); | |
48035728 | 6369 | if (tpr->rx_jmb_buffers) |
2b2cdb65 | 6370 | memset(&tpr->rx_jmb_buffers[0], 0, |
2c49a44d | 6371 | TG3_RX_JMB_BUFF_RING_SIZE(tp)); |
2b2cdb65 MC |
6372 | goto done; |
6373 | } | |
6374 | ||
1da177e4 | 6375 | /* Zero out all descriptors. */ |
2c49a44d | 6376 | memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp)); |
1da177e4 | 6377 | |
287be12e | 6378 | rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ; |
63c3a66f | 6379 | if (tg3_flag(tp, 5780_CLASS) && |
287be12e MC |
6380 | tp->dev->mtu > ETH_DATA_LEN) |
6381 | rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ; | |
6382 | tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz); | |
7e72aad4 | 6383 | |
1da177e4 LT |
6384 | /* Initialize invariants of the rings, we only set this |
6385 | * stuff once. This works because the card does not | |
6386 | * write into the rx buffer posting rings. | |
6387 | */ | |
2c49a44d | 6388 | for (i = 0; i <= tp->rx_std_ring_mask; i++) { |
1da177e4 LT |
6389 | struct tg3_rx_buffer_desc *rxd; |
6390 | ||
21f581a5 | 6391 | rxd = &tpr->rx_std[i]; |
287be12e | 6392 | rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT; |
1da177e4 LT |
6393 | rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT); |
6394 | rxd->opaque = (RXD_OPAQUE_RING_STD | | |
6395 | (i << RXD_OPAQUE_INDEX_SHIFT)); | |
6396 | } | |
6397 | ||
1da177e4 LT |
6398 | /* Now allocate fresh SKBs for each rx ring. */ |
6399 | for (i = 0; i < tp->rx_pending; i++) { | |
86b21e59 | 6400 | if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) { |
5129c3a3 MC |
6401 | netdev_warn(tp->dev, |
6402 | "Using a smaller RX standard ring. Only " | |
6403 | "%d out of %d buffers were allocated " | |
6404 | "successfully\n", i, tp->rx_pending); | |
32d8c572 | 6405 | if (i == 0) |
cf7a7298 | 6406 | goto initfail; |
32d8c572 | 6407 | tp->rx_pending = i; |
1da177e4 | 6408 | break; |
32d8c572 | 6409 | } |
1da177e4 LT |
6410 | } |
6411 | ||
63c3a66f | 6412 | if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS)) |
cf7a7298 MC |
6413 | goto done; |
6414 | ||
2c49a44d | 6415 | memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp)); |
cf7a7298 | 6416 | |
63c3a66f | 6417 | if (!tg3_flag(tp, JUMBO_RING_ENABLE)) |
0d86df80 | 6418 | goto done; |
cf7a7298 | 6419 | |
2c49a44d | 6420 | for (i = 0; i <= tp->rx_jmb_ring_mask; i++) { |
0d86df80 MC |
6421 | struct tg3_rx_buffer_desc *rxd; |
6422 | ||
6423 | rxd = &tpr->rx_jmb[i].std; | |
6424 | rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT; | |
6425 | rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) | | |
6426 | RXD_FLAG_JUMBO; | |
6427 | rxd->opaque = (RXD_OPAQUE_RING_JUMBO | | |
6428 | (i << RXD_OPAQUE_INDEX_SHIFT)); | |
6429 | } | |
6430 | ||
6431 | for (i = 0; i < tp->rx_jumbo_pending; i++) { | |
6432 | if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) { | |
5129c3a3 MC |
6433 | netdev_warn(tp->dev, |
6434 | "Using a smaller RX jumbo ring. Only %d " | |
6435 | "out of %d buffers were allocated " | |
6436 | "successfully\n", i, tp->rx_jumbo_pending); | |
0d86df80 MC |
6437 | if (i == 0) |
6438 | goto initfail; | |
6439 | tp->rx_jumbo_pending = i; | |
6440 | break; | |
1da177e4 LT |
6441 | } |
6442 | } | |
cf7a7298 MC |
6443 | |
6444 | done: | |
32d8c572 | 6445 | return 0; |
cf7a7298 MC |
6446 | |
6447 | initfail: | |
21f581a5 | 6448 | tg3_rx_prodring_free(tp, tpr); |
cf7a7298 | 6449 | return -ENOMEM; |
1da177e4 LT |
6450 | } |
6451 | ||
21f581a5 MC |
6452 | static void tg3_rx_prodring_fini(struct tg3 *tp, |
6453 | struct tg3_rx_prodring_set *tpr) | |
1da177e4 | 6454 | { |
21f581a5 MC |
6455 | kfree(tpr->rx_std_buffers); |
6456 | tpr->rx_std_buffers = NULL; | |
6457 | kfree(tpr->rx_jmb_buffers); | |
6458 | tpr->rx_jmb_buffers = NULL; | |
6459 | if (tpr->rx_std) { | |
4bae65c8 MC |
6460 | dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp), |
6461 | tpr->rx_std, tpr->rx_std_mapping); | |
21f581a5 | 6462 | tpr->rx_std = NULL; |
1da177e4 | 6463 | } |
21f581a5 | 6464 | if (tpr->rx_jmb) { |
4bae65c8 MC |
6465 | dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp), |
6466 | tpr->rx_jmb, tpr->rx_jmb_mapping); | |
21f581a5 | 6467 | tpr->rx_jmb = NULL; |
1da177e4 | 6468 | } |
cf7a7298 MC |
6469 | } |
6470 | ||
21f581a5 MC |
6471 | static int tg3_rx_prodring_init(struct tg3 *tp, |
6472 | struct tg3_rx_prodring_set *tpr) | |
cf7a7298 | 6473 | { |
2c49a44d MC |
6474 | tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp), |
6475 | GFP_KERNEL); | |
21f581a5 | 6476 | if (!tpr->rx_std_buffers) |
cf7a7298 MC |
6477 | return -ENOMEM; |
6478 | ||
4bae65c8 MC |
6479 | tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev, |
6480 | TG3_RX_STD_RING_BYTES(tp), | |
6481 | &tpr->rx_std_mapping, | |
6482 | GFP_KERNEL); | |
21f581a5 | 6483 | if (!tpr->rx_std) |
cf7a7298 MC |
6484 | goto err_out; |
6485 | ||
63c3a66f | 6486 | if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) { |
2c49a44d | 6487 | tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp), |
21f581a5 MC |
6488 | GFP_KERNEL); |
6489 | if (!tpr->rx_jmb_buffers) | |
cf7a7298 MC |
6490 | goto err_out; |
6491 | ||
4bae65c8 MC |
6492 | tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev, |
6493 | TG3_RX_JMB_RING_BYTES(tp), | |
6494 | &tpr->rx_jmb_mapping, | |
6495 | GFP_KERNEL); | |
21f581a5 | 6496 | if (!tpr->rx_jmb) |
cf7a7298 MC |
6497 | goto err_out; |
6498 | } | |
6499 | ||
6500 | return 0; | |
6501 | ||
6502 | err_out: | |
21f581a5 | 6503 | tg3_rx_prodring_fini(tp, tpr); |
cf7a7298 MC |
6504 | return -ENOMEM; |
6505 | } | |
6506 | ||
6507 | /* Free up pending packets in all rx/tx rings. | |
6508 | * | |
6509 | * The chip has been shut down and the driver detached from | |
6510 | * the networking, so no interrupts or new tx packets will | |
6511 | * end up in the driver. tp->{tx,}lock is not held and we are not | |
6512 | * in an interrupt context and thus may sleep. | |
6513 | */ | |
6514 | static void tg3_free_rings(struct tg3 *tp) | |
6515 | { | |
f77a6a8e | 6516 | int i, j; |
cf7a7298 | 6517 | |
f77a6a8e MC |
6518 | for (j = 0; j < tp->irq_cnt; j++) { |
6519 | struct tg3_napi *tnapi = &tp->napi[j]; | |
cf7a7298 | 6520 | |
8fea32b9 | 6521 | tg3_rx_prodring_free(tp, &tnapi->prodring); |
b28f6428 | 6522 | |
0c1d0e2b MC |
6523 | if (!tnapi->tx_buffers) |
6524 | continue; | |
6525 | ||
f77a6a8e | 6526 | for (i = 0; i < TG3_TX_RING_SIZE; ) { |
f4188d8a | 6527 | struct ring_info *txp; |
f77a6a8e | 6528 | struct sk_buff *skb; |
f4188d8a | 6529 | unsigned int k; |
cf7a7298 | 6530 | |
f77a6a8e MC |
6531 | txp = &tnapi->tx_buffers[i]; |
6532 | skb = txp->skb; | |
cf7a7298 | 6533 | |
f77a6a8e MC |
6534 | if (skb == NULL) { |
6535 | i++; | |
6536 | continue; | |
6537 | } | |
cf7a7298 | 6538 | |
f4188d8a | 6539 | pci_unmap_single(tp->pdev, |
4e5e4f0d | 6540 | dma_unmap_addr(txp, mapping), |
f4188d8a AD |
6541 | skb_headlen(skb), |
6542 | PCI_DMA_TODEVICE); | |
f77a6a8e | 6543 | txp->skb = NULL; |
cf7a7298 | 6544 | |
f4188d8a AD |
6545 | i++; |
6546 | ||
6547 | for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) { | |
6548 | txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)]; | |
6549 | pci_unmap_page(tp->pdev, | |
4e5e4f0d | 6550 | dma_unmap_addr(txp, mapping), |
f4188d8a AD |
6551 | skb_shinfo(skb)->frags[k].size, |
6552 | PCI_DMA_TODEVICE); | |
6553 | i++; | |
6554 | } | |
f77a6a8e MC |
6555 | |
6556 | dev_kfree_skb_any(skb); | |
6557 | } | |
2b2cdb65 | 6558 | } |
cf7a7298 MC |
6559 | } |
6560 | ||
6561 | /* Initialize tx/rx rings for packet processing. | |
6562 | * | |
6563 | * The chip has been shut down and the driver detached from | |
6564 | * the networking, so no interrupts or new tx packets will | |
6565 | * end up in the driver. tp->{tx,}lock are held and thus | |
6566 | * we may not sleep. | |
6567 | */ | |
6568 | static int tg3_init_rings(struct tg3 *tp) | |
6569 | { | |
f77a6a8e | 6570 | int i; |
72334482 | 6571 | |
cf7a7298 MC |
6572 | /* Free up all the SKBs. */ |
6573 | tg3_free_rings(tp); | |
6574 | ||
f77a6a8e MC |
6575 | for (i = 0; i < tp->irq_cnt; i++) { |
6576 | struct tg3_napi *tnapi = &tp->napi[i]; | |
6577 | ||
6578 | tnapi->last_tag = 0; | |
6579 | tnapi->last_irq_tag = 0; | |
6580 | tnapi->hw_status->status = 0; | |
6581 | tnapi->hw_status->status_tag = 0; | |
6582 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
cf7a7298 | 6583 | |
f77a6a8e MC |
6584 | tnapi->tx_prod = 0; |
6585 | tnapi->tx_cons = 0; | |
0c1d0e2b MC |
6586 | if (tnapi->tx_ring) |
6587 | memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES); | |
f77a6a8e MC |
6588 | |
6589 | tnapi->rx_rcb_ptr = 0; | |
0c1d0e2b MC |
6590 | if (tnapi->rx_rcb) |
6591 | memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); | |
2b2cdb65 | 6592 | |
8fea32b9 | 6593 | if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) { |
e4af1af9 | 6594 | tg3_free_rings(tp); |
2b2cdb65 | 6595 | return -ENOMEM; |
e4af1af9 | 6596 | } |
f77a6a8e | 6597 | } |
72334482 | 6598 | |
2b2cdb65 | 6599 | return 0; |
cf7a7298 MC |
6600 | } |
6601 | ||
6602 | /* | |
6603 | * Must not be invoked with interrupt sources disabled and | |
6604 | * the hardware shutdown down. | |
6605 | */ | |
6606 | static void tg3_free_consistent(struct tg3 *tp) | |
6607 | { | |
f77a6a8e | 6608 | int i; |
898a56f8 | 6609 | |
f77a6a8e MC |
6610 | for (i = 0; i < tp->irq_cnt; i++) { |
6611 | struct tg3_napi *tnapi = &tp->napi[i]; | |
6612 | ||
6613 | if (tnapi->tx_ring) { | |
4bae65c8 | 6614 | dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES, |
f77a6a8e MC |
6615 | tnapi->tx_ring, tnapi->tx_desc_mapping); |
6616 | tnapi->tx_ring = NULL; | |
6617 | } | |
6618 | ||
6619 | kfree(tnapi->tx_buffers); | |
6620 | tnapi->tx_buffers = NULL; | |
6621 | ||
6622 | if (tnapi->rx_rcb) { | |
4bae65c8 MC |
6623 | dma_free_coherent(&tp->pdev->dev, |
6624 | TG3_RX_RCB_RING_BYTES(tp), | |
6625 | tnapi->rx_rcb, | |
6626 | tnapi->rx_rcb_mapping); | |
f77a6a8e MC |
6627 | tnapi->rx_rcb = NULL; |
6628 | } | |
6629 | ||
8fea32b9 MC |
6630 | tg3_rx_prodring_fini(tp, &tnapi->prodring); |
6631 | ||
f77a6a8e | 6632 | if (tnapi->hw_status) { |
4bae65c8 MC |
6633 | dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE, |
6634 | tnapi->hw_status, | |
6635 | tnapi->status_mapping); | |
f77a6a8e MC |
6636 | tnapi->hw_status = NULL; |
6637 | } | |
1da177e4 | 6638 | } |
f77a6a8e | 6639 | |
1da177e4 | 6640 | if (tp->hw_stats) { |
4bae65c8 MC |
6641 | dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats), |
6642 | tp->hw_stats, tp->stats_mapping); | |
1da177e4 LT |
6643 | tp->hw_stats = NULL; |
6644 | } | |
6645 | } | |
6646 | ||
6647 | /* | |
6648 | * Must not be invoked with interrupt sources disabled and | |
6649 | * the hardware shutdown down. Can sleep. | |
6650 | */ | |
6651 | static int tg3_alloc_consistent(struct tg3 *tp) | |
6652 | { | |
f77a6a8e | 6653 | int i; |
898a56f8 | 6654 | |
4bae65c8 MC |
6655 | tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev, |
6656 | sizeof(struct tg3_hw_stats), | |
6657 | &tp->stats_mapping, | |
6658 | GFP_KERNEL); | |
f77a6a8e | 6659 | if (!tp->hw_stats) |
1da177e4 LT |
6660 | goto err_out; |
6661 | ||
f77a6a8e | 6662 | memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); |
1da177e4 | 6663 | |
f77a6a8e MC |
6664 | for (i = 0; i < tp->irq_cnt; i++) { |
6665 | struct tg3_napi *tnapi = &tp->napi[i]; | |
8d9d7cfc | 6666 | struct tg3_hw_status *sblk; |
1da177e4 | 6667 | |
4bae65c8 MC |
6668 | tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev, |
6669 | TG3_HW_STATUS_SIZE, | |
6670 | &tnapi->status_mapping, | |
6671 | GFP_KERNEL); | |
f77a6a8e MC |
6672 | if (!tnapi->hw_status) |
6673 | goto err_out; | |
898a56f8 | 6674 | |
f77a6a8e | 6675 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); |
8d9d7cfc MC |
6676 | sblk = tnapi->hw_status; |
6677 | ||
8fea32b9 MC |
6678 | if (tg3_rx_prodring_init(tp, &tnapi->prodring)) |
6679 | goto err_out; | |
6680 | ||
19cfaecc MC |
6681 | /* If multivector TSS is enabled, vector 0 does not handle |
6682 | * tx interrupts. Don't allocate any resources for it. | |
6683 | */ | |
63c3a66f JP |
6684 | if ((!i && !tg3_flag(tp, ENABLE_TSS)) || |
6685 | (i && tg3_flag(tp, ENABLE_TSS))) { | |
19cfaecc MC |
6686 | tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) * |
6687 | TG3_TX_RING_SIZE, | |
6688 | GFP_KERNEL); | |
6689 | if (!tnapi->tx_buffers) | |
6690 | goto err_out; | |
6691 | ||
4bae65c8 MC |
6692 | tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev, |
6693 | TG3_TX_RING_BYTES, | |
6694 | &tnapi->tx_desc_mapping, | |
6695 | GFP_KERNEL); | |
19cfaecc MC |
6696 | if (!tnapi->tx_ring) |
6697 | goto err_out; | |
6698 | } | |
6699 | ||
8d9d7cfc MC |
6700 | /* |
6701 | * When RSS is enabled, the status block format changes | |
6702 | * slightly. The "rx_jumbo_consumer", "reserved", | |
6703 | * and "rx_mini_consumer" members get mapped to the | |
6704 | * other three rx return ring producer indexes. | |
6705 | */ | |
6706 | switch (i) { | |
6707 | default: | |
6708 | tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer; | |
6709 | break; | |
6710 | case 2: | |
6711 | tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer; | |
6712 | break; | |
6713 | case 3: | |
6714 | tnapi->rx_rcb_prod_idx = &sblk->reserved; | |
6715 | break; | |
6716 | case 4: | |
6717 | tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer; | |
6718 | break; | |
6719 | } | |
72334482 | 6720 | |
0c1d0e2b MC |
6721 | /* |
6722 | * If multivector RSS is enabled, vector 0 does not handle | |
6723 | * rx or tx interrupts. Don't allocate any resources for it. | |
6724 | */ | |
63c3a66f | 6725 | if (!i && tg3_flag(tp, ENABLE_RSS)) |
0c1d0e2b MC |
6726 | continue; |
6727 | ||
4bae65c8 MC |
6728 | tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev, |
6729 | TG3_RX_RCB_RING_BYTES(tp), | |
6730 | &tnapi->rx_rcb_mapping, | |
6731 | GFP_KERNEL); | |
f77a6a8e MC |
6732 | if (!tnapi->rx_rcb) |
6733 | goto err_out; | |
72334482 | 6734 | |
f77a6a8e | 6735 | memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); |
f77a6a8e | 6736 | } |
1da177e4 LT |
6737 | |
6738 | return 0; | |
6739 | ||
6740 | err_out: | |
6741 | tg3_free_consistent(tp); | |
6742 | return -ENOMEM; | |
6743 | } | |
6744 | ||
6745 | #define MAX_WAIT_CNT 1000 | |
6746 | ||
6747 | /* To stop a block, clear the enable bit and poll till it | |
6748 | * clears. tp->lock is held. | |
6749 | */ | |
b3b7d6be | 6750 | static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent) |
1da177e4 LT |
6751 | { |
6752 | unsigned int i; | |
6753 | u32 val; | |
6754 | ||
63c3a66f | 6755 | if (tg3_flag(tp, 5705_PLUS)) { |
1da177e4 LT |
6756 | switch (ofs) { |
6757 | case RCVLSC_MODE: | |
6758 | case DMAC_MODE: | |
6759 | case MBFREE_MODE: | |
6760 | case BUFMGR_MODE: | |
6761 | case MEMARB_MODE: | |
6762 | /* We can't enable/disable these bits of the | |
6763 | * 5705/5750, just say success. | |
6764 | */ | |
6765 | return 0; | |
6766 | ||
6767 | default: | |
6768 | break; | |
855e1111 | 6769 | } |
1da177e4 LT |
6770 | } |
6771 | ||
6772 | val = tr32(ofs); | |
6773 | val &= ~enable_bit; | |
6774 | tw32_f(ofs, val); | |
6775 | ||
6776 | for (i = 0; i < MAX_WAIT_CNT; i++) { | |
6777 | udelay(100); | |
6778 | val = tr32(ofs); | |
6779 | if ((val & enable_bit) == 0) | |
6780 | break; | |
6781 | } | |
6782 | ||
b3b7d6be | 6783 | if (i == MAX_WAIT_CNT && !silent) { |
2445e461 MC |
6784 | dev_err(&tp->pdev->dev, |
6785 | "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n", | |
6786 | ofs, enable_bit); | |
1da177e4 LT |
6787 | return -ENODEV; |
6788 | } | |
6789 | ||
6790 | return 0; | |
6791 | } | |
6792 | ||
6793 | /* tp->lock is held. */ | |
b3b7d6be | 6794 | static int tg3_abort_hw(struct tg3 *tp, int silent) |
1da177e4 LT |
6795 | { |
6796 | int i, err; | |
6797 | ||
6798 | tg3_disable_ints(tp); | |
6799 | ||
6800 | tp->rx_mode &= ~RX_MODE_ENABLE; | |
6801 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
6802 | udelay(10); | |
6803 | ||
b3b7d6be DM |
6804 | err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent); |
6805 | err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent); | |
6806 | err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent); | |
6807 | err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent); | |
6808 | err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent); | |
6809 | err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent); | |
6810 | ||
6811 | err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent); | |
6812 | err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent); | |
6813 | err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent); | |
6814 | err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent); | |
6815 | err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent); | |
6816 | err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent); | |
6817 | err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent); | |
1da177e4 LT |
6818 | |
6819 | tp->mac_mode &= ~MAC_MODE_TDE_ENABLE; | |
6820 | tw32_f(MAC_MODE, tp->mac_mode); | |
6821 | udelay(40); | |
6822 | ||
6823 | tp->tx_mode &= ~TX_MODE_ENABLE; | |
6824 | tw32_f(MAC_TX_MODE, tp->tx_mode); | |
6825 | ||
6826 | for (i = 0; i < MAX_WAIT_CNT; i++) { | |
6827 | udelay(100); | |
6828 | if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE)) | |
6829 | break; | |
6830 | } | |
6831 | if (i >= MAX_WAIT_CNT) { | |
ab96b241 MC |
6832 | dev_err(&tp->pdev->dev, |
6833 | "%s timed out, TX_MODE_ENABLE will not clear " | |
6834 | "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE)); | |
e6de8ad1 | 6835 | err |= -ENODEV; |
1da177e4 LT |
6836 | } |
6837 | ||
e6de8ad1 | 6838 | err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent); |
b3b7d6be DM |
6839 | err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent); |
6840 | err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent); | |
1da177e4 LT |
6841 | |
6842 | tw32(FTQ_RESET, 0xffffffff); | |
6843 | tw32(FTQ_RESET, 0x00000000); | |
6844 | ||
b3b7d6be DM |
6845 | err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent); |
6846 | err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent); | |
1da177e4 | 6847 | |
f77a6a8e MC |
6848 | for (i = 0; i < tp->irq_cnt; i++) { |
6849 | struct tg3_napi *tnapi = &tp->napi[i]; | |
6850 | if (tnapi->hw_status) | |
6851 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
6852 | } | |
1da177e4 LT |
6853 | if (tp->hw_stats) |
6854 | memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); | |
6855 | ||
1da177e4 LT |
6856 | return err; |
6857 | } | |
6858 | ||
0d3031d9 MC |
6859 | static void tg3_ape_send_event(struct tg3 *tp, u32 event) |
6860 | { | |
6861 | int i; | |
6862 | u32 apedata; | |
6863 | ||
dc6d0744 | 6864 | /* NCSI does not support APE events */ |
63c3a66f | 6865 | if (tg3_flag(tp, APE_HAS_NCSI)) |
dc6d0744 MC |
6866 | return; |
6867 | ||
0d3031d9 MC |
6868 | apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); |
6869 | if (apedata != APE_SEG_SIG_MAGIC) | |
6870 | return; | |
6871 | ||
6872 | apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); | |
731fd79c | 6873 | if (!(apedata & APE_FW_STATUS_READY)) |
0d3031d9 MC |
6874 | return; |
6875 | ||
6876 | /* Wait for up to 1 millisecond for APE to service previous event. */ | |
6877 | for (i = 0; i < 10; i++) { | |
6878 | if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM)) | |
6879 | return; | |
6880 | ||
6881 | apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS); | |
6882 | ||
6883 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) | |
6884 | tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, | |
6885 | event | APE_EVENT_STATUS_EVENT_PENDING); | |
6886 | ||
6887 | tg3_ape_unlock(tp, TG3_APE_LOCK_MEM); | |
6888 | ||
6889 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) | |
6890 | break; | |
6891 | ||
6892 | udelay(100); | |
6893 | } | |
6894 | ||
6895 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) | |
6896 | tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1); | |
6897 | } | |
6898 | ||
6899 | static void tg3_ape_driver_state_change(struct tg3 *tp, int kind) | |
6900 | { | |
6901 | u32 event; | |
6902 | u32 apedata; | |
6903 | ||
63c3a66f | 6904 | if (!tg3_flag(tp, ENABLE_APE)) |
0d3031d9 MC |
6905 | return; |
6906 | ||
6907 | switch (kind) { | |
33f401ae MC |
6908 | case RESET_KIND_INIT: |
6909 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, | |
6910 | APE_HOST_SEG_SIG_MAGIC); | |
6911 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN, | |
6912 | APE_HOST_SEG_LEN_MAGIC); | |
6913 | apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT); | |
6914 | tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata); | |
6915 | tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID, | |
6867c843 | 6916 | APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM)); |
33f401ae MC |
6917 | tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR, |
6918 | APE_HOST_BEHAV_NO_PHYLOCK); | |
dc6d0744 MC |
6919 | tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, |
6920 | TG3_APE_HOST_DRVR_STATE_START); | |
33f401ae MC |
6921 | |
6922 | event = APE_EVENT_STATUS_STATE_START; | |
6923 | break; | |
6924 | case RESET_KIND_SHUTDOWN: | |
6925 | /* With the interface we are currently using, | |
6926 | * APE does not track driver state. Wiping | |
6927 | * out the HOST SEGMENT SIGNATURE forces | |
6928 | * the APE to assume OS absent status. | |
6929 | */ | |
6930 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0); | |
b2aee154 | 6931 | |
dc6d0744 | 6932 | if (device_may_wakeup(&tp->pdev->dev) && |
63c3a66f | 6933 | tg3_flag(tp, WOL_ENABLE)) { |
dc6d0744 MC |
6934 | tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED, |
6935 | TG3_APE_HOST_WOL_SPEED_AUTO); | |
6936 | apedata = TG3_APE_HOST_DRVR_STATE_WOL; | |
6937 | } else | |
6938 | apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD; | |
6939 | ||
6940 | tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata); | |
6941 | ||
33f401ae MC |
6942 | event = APE_EVENT_STATUS_STATE_UNLOAD; |
6943 | break; | |
6944 | case RESET_KIND_SUSPEND: | |
6945 | event = APE_EVENT_STATUS_STATE_SUSPEND; | |
6946 | break; | |
6947 | default: | |
6948 | return; | |
0d3031d9 MC |
6949 | } |
6950 | ||
6951 | event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE; | |
6952 | ||
6953 | tg3_ape_send_event(tp, event); | |
6954 | } | |
6955 | ||
1da177e4 LT |
6956 | /* tp->lock is held. */ |
6957 | static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind) | |
6958 | { | |
f49639e6 DM |
6959 | tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX, |
6960 | NIC_SRAM_FIRMWARE_MBOX_MAGIC1); | |
1da177e4 | 6961 | |
63c3a66f | 6962 | if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) { |
1da177e4 LT |
6963 | switch (kind) { |
6964 | case RESET_KIND_INIT: | |
6965 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6966 | DRV_STATE_START); | |
6967 | break; | |
6968 | ||
6969 | case RESET_KIND_SHUTDOWN: | |
6970 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6971 | DRV_STATE_UNLOAD); | |
6972 | break; | |
6973 | ||
6974 | case RESET_KIND_SUSPEND: | |
6975 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6976 | DRV_STATE_SUSPEND); | |
6977 | break; | |
6978 | ||
6979 | default: | |
6980 | break; | |
855e1111 | 6981 | } |
1da177e4 | 6982 | } |
0d3031d9 MC |
6983 | |
6984 | if (kind == RESET_KIND_INIT || | |
6985 | kind == RESET_KIND_SUSPEND) | |
6986 | tg3_ape_driver_state_change(tp, kind); | |
1da177e4 LT |
6987 | } |
6988 | ||
6989 | /* tp->lock is held. */ | |
6990 | static void tg3_write_sig_post_reset(struct tg3 *tp, int kind) | |
6991 | { | |
63c3a66f | 6992 | if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) { |
1da177e4 LT |
6993 | switch (kind) { |
6994 | case RESET_KIND_INIT: | |
6995 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6996 | DRV_STATE_START_DONE); | |
6997 | break; | |
6998 | ||
6999 | case RESET_KIND_SHUTDOWN: | |
7000 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
7001 | DRV_STATE_UNLOAD_DONE); | |
7002 | break; | |
7003 | ||
7004 | default: | |
7005 | break; | |
855e1111 | 7006 | } |
1da177e4 | 7007 | } |
0d3031d9 MC |
7008 | |
7009 | if (kind == RESET_KIND_SHUTDOWN) | |
7010 | tg3_ape_driver_state_change(tp, kind); | |
1da177e4 LT |
7011 | } |
7012 | ||
7013 | /* tp->lock is held. */ | |
7014 | static void tg3_write_sig_legacy(struct tg3 *tp, int kind) | |
7015 | { | |
63c3a66f | 7016 | if (tg3_flag(tp, ENABLE_ASF)) { |
1da177e4 LT |
7017 | switch (kind) { |
7018 | case RESET_KIND_INIT: | |
7019 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
7020 | DRV_STATE_START); | |
7021 | break; | |
7022 | ||
7023 | case RESET_KIND_SHUTDOWN: | |
7024 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
7025 | DRV_STATE_UNLOAD); | |
7026 | break; | |
7027 | ||
7028 | case RESET_KIND_SUSPEND: | |
7029 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
7030 | DRV_STATE_SUSPEND); | |
7031 | break; | |
7032 | ||
7033 | default: | |
7034 | break; | |
855e1111 | 7035 | } |
1da177e4 LT |
7036 | } |
7037 | } | |
7038 | ||
7a6f4369 MC |
7039 | static int tg3_poll_fw(struct tg3 *tp) |
7040 | { | |
7041 | int i; | |
7042 | u32 val; | |
7043 | ||
b5d3772c | 7044 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
0ccead18 GZ |
7045 | /* Wait up to 20ms for init done. */ |
7046 | for (i = 0; i < 200; i++) { | |
b5d3772c MC |
7047 | if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE) |
7048 | return 0; | |
0ccead18 | 7049 | udelay(100); |
b5d3772c MC |
7050 | } |
7051 | return -ENODEV; | |
7052 | } | |
7053 | ||
7a6f4369 MC |
7054 | /* Wait for firmware initialization to complete. */ |
7055 | for (i = 0; i < 100000; i++) { | |
7056 | tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val); | |
7057 | if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1) | |
7058 | break; | |
7059 | udelay(10); | |
7060 | } | |
7061 | ||
7062 | /* Chip might not be fitted with firmware. Some Sun onboard | |
7063 | * parts are configured like that. So don't signal the timeout | |
7064 | * of the above loop as an error, but do report the lack of | |
7065 | * running firmware once. | |
7066 | */ | |
63c3a66f JP |
7067 | if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) { |
7068 | tg3_flag_set(tp, NO_FWARE_REPORTED); | |
7a6f4369 | 7069 | |
05dbe005 | 7070 | netdev_info(tp->dev, "No firmware running\n"); |
7a6f4369 MC |
7071 | } |
7072 | ||
6b10c165 MC |
7073 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) { |
7074 | /* The 57765 A0 needs a little more | |
7075 | * time to do some important work. | |
7076 | */ | |
7077 | mdelay(10); | |
7078 | } | |
7079 | ||
7a6f4369 MC |
7080 | return 0; |
7081 | } | |
7082 | ||
ee6a99b5 MC |
7083 | /* Save PCI command register before chip reset */ |
7084 | static void tg3_save_pci_state(struct tg3 *tp) | |
7085 | { | |
8a6eac90 | 7086 | pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd); |
ee6a99b5 MC |
7087 | } |
7088 | ||
7089 | /* Restore PCI state after chip reset */ | |
7090 | static void tg3_restore_pci_state(struct tg3 *tp) | |
7091 | { | |
7092 | u32 val; | |
7093 | ||
7094 | /* Re-enable indirect register accesses. */ | |
7095 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
7096 | tp->misc_host_ctrl); | |
7097 | ||
7098 | /* Set MAX PCI retry to zero. */ | |
7099 | val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE); | |
7100 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 && | |
63c3a66f | 7101 | tg3_flag(tp, PCIX_MODE)) |
ee6a99b5 | 7102 | val |= PCISTATE_RETRY_SAME_DMA; |
0d3031d9 | 7103 | /* Allow reads and writes to the APE register and memory space. */ |
63c3a66f | 7104 | if (tg3_flag(tp, ENABLE_APE)) |
0d3031d9 | 7105 | val |= PCISTATE_ALLOW_APE_CTLSPC_WR | |
f92d9dc1 MC |
7106 | PCISTATE_ALLOW_APE_SHMEM_WR | |
7107 | PCISTATE_ALLOW_APE_PSPACE_WR; | |
ee6a99b5 MC |
7108 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val); |
7109 | ||
8a6eac90 | 7110 | pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd); |
ee6a99b5 | 7111 | |
fcb389df | 7112 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) { |
63c3a66f | 7113 | if (tg3_flag(tp, PCI_EXPRESS)) |
cf79003d | 7114 | pcie_set_readrq(tp->pdev, tp->pcie_readrq); |
fcb389df MC |
7115 | else { |
7116 | pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, | |
7117 | tp->pci_cacheline_sz); | |
7118 | pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, | |
7119 | tp->pci_lat_timer); | |
7120 | } | |
114342f2 | 7121 | } |
5f5c51e3 | 7122 | |
ee6a99b5 | 7123 | /* Make sure PCI-X relaxed ordering bit is clear. */ |
63c3a66f | 7124 | if (tg3_flag(tp, PCIX_MODE)) { |
9974a356 MC |
7125 | u16 pcix_cmd; |
7126 | ||
7127 | pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
7128 | &pcix_cmd); | |
7129 | pcix_cmd &= ~PCI_X_CMD_ERO; | |
7130 | pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
7131 | pcix_cmd); | |
7132 | } | |
ee6a99b5 | 7133 | |
63c3a66f | 7134 | if (tg3_flag(tp, 5780_CLASS)) { |
ee6a99b5 MC |
7135 | |
7136 | /* Chip reset on 5780 will reset MSI enable bit, | |
7137 | * so need to restore it. | |
7138 | */ | |
63c3a66f | 7139 | if (tg3_flag(tp, USING_MSI)) { |
ee6a99b5 MC |
7140 | u16 ctrl; |
7141 | ||
7142 | pci_read_config_word(tp->pdev, | |
7143 | tp->msi_cap + PCI_MSI_FLAGS, | |
7144 | &ctrl); | |
7145 | pci_write_config_word(tp->pdev, | |
7146 | tp->msi_cap + PCI_MSI_FLAGS, | |
7147 | ctrl | PCI_MSI_FLAGS_ENABLE); | |
7148 | val = tr32(MSGINT_MODE); | |
7149 | tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE); | |
7150 | } | |
7151 | } | |
7152 | } | |
7153 | ||
1da177e4 LT |
7154 | static void tg3_stop_fw(struct tg3 *); |
7155 | ||
7156 | /* tp->lock is held. */ | |
7157 | static int tg3_chip_reset(struct tg3 *tp) | |
7158 | { | |
7159 | u32 val; | |
1ee582d8 | 7160 | void (*write_op)(struct tg3 *, u32, u32); |
4f125f42 | 7161 | int i, err; |
1da177e4 | 7162 | |
f49639e6 DM |
7163 | tg3_nvram_lock(tp); |
7164 | ||
77b483f1 MC |
7165 | tg3_ape_lock(tp, TG3_APE_LOCK_GRC); |
7166 | ||
f49639e6 DM |
7167 | /* No matching tg3_nvram_unlock() after this because |
7168 | * chip reset below will undo the nvram lock. | |
7169 | */ | |
7170 | tp->nvram_lock_cnt = 0; | |
1da177e4 | 7171 | |
ee6a99b5 MC |
7172 | /* GRC_MISC_CFG core clock reset will clear the memory |
7173 | * enable bit in PCI register 4 and the MSI enable bit | |
7174 | * on some chips, so we save relevant registers here. | |
7175 | */ | |
7176 | tg3_save_pci_state(tp); | |
7177 | ||
d9ab5ad1 | 7178 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || |
63c3a66f | 7179 | tg3_flag(tp, 5755_PLUS)) |
d9ab5ad1 MC |
7180 | tw32(GRC_FASTBOOT_PC, 0); |
7181 | ||
1da177e4 LT |
7182 | /* |
7183 | * We must avoid the readl() that normally takes place. | |
7184 | * It locks machines, causes machine checks, and other | |
7185 | * fun things. So, temporarily disable the 5701 | |
7186 | * hardware workaround, while we do the reset. | |
7187 | */ | |
1ee582d8 MC |
7188 | write_op = tp->write32; |
7189 | if (write_op == tg3_write_flush_reg32) | |
7190 | tp->write32 = tg3_write32; | |
1da177e4 | 7191 | |
d18edcb2 MC |
7192 | /* Prevent the irq handler from reading or writing PCI registers |
7193 | * during chip reset when the memory enable bit in the PCI command | |
7194 | * register may be cleared. The chip does not generate interrupt | |
7195 | * at this time, but the irq handler may still be called due to irq | |
7196 | * sharing or irqpoll. | |
7197 | */ | |
63c3a66f | 7198 | tg3_flag_set(tp, CHIP_RESETTING); |
f77a6a8e MC |
7199 | for (i = 0; i < tp->irq_cnt; i++) { |
7200 | struct tg3_napi *tnapi = &tp->napi[i]; | |
7201 | if (tnapi->hw_status) { | |
7202 | tnapi->hw_status->status = 0; | |
7203 | tnapi->hw_status->status_tag = 0; | |
7204 | } | |
7205 | tnapi->last_tag = 0; | |
7206 | tnapi->last_irq_tag = 0; | |
b8fa2f3a | 7207 | } |
d18edcb2 | 7208 | smp_mb(); |
4f125f42 MC |
7209 | |
7210 | for (i = 0; i < tp->irq_cnt; i++) | |
7211 | synchronize_irq(tp->napi[i].irq_vec); | |
d18edcb2 | 7212 | |
255ca311 MC |
7213 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { |
7214 | val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN; | |
7215 | tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS); | |
7216 | } | |
7217 | ||
1da177e4 LT |
7218 | /* do the reset */ |
7219 | val = GRC_MISC_CFG_CORECLK_RESET; | |
7220 | ||
63c3a66f | 7221 | if (tg3_flag(tp, PCI_EXPRESS)) { |
88075d91 MC |
7222 | /* Force PCIe 1.0a mode */ |
7223 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && | |
63c3a66f | 7224 | !tg3_flag(tp, 57765_PLUS) && |
88075d91 MC |
7225 | tr32(TG3_PCIE_PHY_TSTCTL) == |
7226 | (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM)) | |
7227 | tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM); | |
7228 | ||
1da177e4 LT |
7229 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) { |
7230 | tw32(GRC_MISC_CFG, (1 << 29)); | |
7231 | val |= (1 << 29); | |
7232 | } | |
7233 | } | |
7234 | ||
b5d3772c MC |
7235 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
7236 | tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET); | |
7237 | tw32(GRC_VCPU_EXT_CTRL, | |
7238 | tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU); | |
7239 | } | |
7240 | ||
f37500d3 | 7241 | /* Manage gphy power for all CPMU absent PCIe devices. */ |
63c3a66f | 7242 | if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT)) |
1da177e4 | 7243 | val |= GRC_MISC_CFG_KEEP_GPHY_POWER; |
f37500d3 | 7244 | |
1da177e4 LT |
7245 | tw32(GRC_MISC_CFG, val); |
7246 | ||
1ee582d8 MC |
7247 | /* restore 5701 hardware bug workaround write method */ |
7248 | tp->write32 = write_op; | |
1da177e4 LT |
7249 | |
7250 | /* Unfortunately, we have to delay before the PCI read back. | |
7251 | * Some 575X chips even will not respond to a PCI cfg access | |
7252 | * when the reset command is given to the chip. | |
7253 | * | |
7254 | * How do these hardware designers expect things to work | |
7255 | * properly if the PCI write is posted for a long period | |
7256 | * of time? It is always necessary to have some method by | |
7257 | * which a register read back can occur to push the write | |
7258 | * out which does the reset. | |
7259 | * | |
7260 | * For most tg3 variants the trick below was working. | |
7261 | * Ho hum... | |
7262 | */ | |
7263 | udelay(120); | |
7264 | ||
7265 | /* Flush PCI posted writes. The normal MMIO registers | |
7266 | * are inaccessible at this time so this is the only | |
7267 | * way to make this reliably (actually, this is no longer | |
7268 | * the case, see above). I tried to use indirect | |
7269 | * register read/write but this upset some 5701 variants. | |
7270 | */ | |
7271 | pci_read_config_dword(tp->pdev, PCI_COMMAND, &val); | |
7272 | ||
7273 | udelay(120); | |
7274 | ||
708ebb3a | 7275 | if (tg3_flag(tp, PCI_EXPRESS) && pci_pcie_cap(tp->pdev)) { |
e7126997 MC |
7276 | u16 val16; |
7277 | ||
1da177e4 LT |
7278 | if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) { |
7279 | int i; | |
7280 | u32 cfg_val; | |
7281 | ||
7282 | /* Wait for link training to complete. */ | |
7283 | for (i = 0; i < 5000; i++) | |
7284 | udelay(100); | |
7285 | ||
7286 | pci_read_config_dword(tp->pdev, 0xc4, &cfg_val); | |
7287 | pci_write_config_dword(tp->pdev, 0xc4, | |
7288 | cfg_val | (1 << 15)); | |
7289 | } | |
5e7dfd0f | 7290 | |
e7126997 MC |
7291 | /* Clear the "no snoop" and "relaxed ordering" bits. */ |
7292 | pci_read_config_word(tp->pdev, | |
708ebb3a | 7293 | pci_pcie_cap(tp->pdev) + PCI_EXP_DEVCTL, |
e7126997 MC |
7294 | &val16); |
7295 | val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN | | |
7296 | PCI_EXP_DEVCTL_NOSNOOP_EN); | |
7297 | /* | |
7298 | * Older PCIe devices only support the 128 byte | |
7299 | * MPS setting. Enforce the restriction. | |
5e7dfd0f | 7300 | */ |
63c3a66f | 7301 | if (!tg3_flag(tp, CPMU_PRESENT)) |
e7126997 | 7302 | val16 &= ~PCI_EXP_DEVCTL_PAYLOAD; |
5e7dfd0f | 7303 | pci_write_config_word(tp->pdev, |
708ebb3a | 7304 | pci_pcie_cap(tp->pdev) + PCI_EXP_DEVCTL, |
e7126997 | 7305 | val16); |
5e7dfd0f | 7306 | |
cf79003d | 7307 | pcie_set_readrq(tp->pdev, tp->pcie_readrq); |
5e7dfd0f MC |
7308 | |
7309 | /* Clear error status */ | |
7310 | pci_write_config_word(tp->pdev, | |
708ebb3a | 7311 | pci_pcie_cap(tp->pdev) + PCI_EXP_DEVSTA, |
5e7dfd0f MC |
7312 | PCI_EXP_DEVSTA_CED | |
7313 | PCI_EXP_DEVSTA_NFED | | |
7314 | PCI_EXP_DEVSTA_FED | | |
7315 | PCI_EXP_DEVSTA_URD); | |
1da177e4 LT |
7316 | } |
7317 | ||
ee6a99b5 | 7318 | tg3_restore_pci_state(tp); |
1da177e4 | 7319 | |
63c3a66f JP |
7320 | tg3_flag_clear(tp, CHIP_RESETTING); |
7321 | tg3_flag_clear(tp, ERROR_PROCESSED); | |
d18edcb2 | 7322 | |
ee6a99b5 | 7323 | val = 0; |
63c3a66f | 7324 | if (tg3_flag(tp, 5780_CLASS)) |
4cf78e4f | 7325 | val = tr32(MEMARB_MODE); |
ee6a99b5 | 7326 | tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE); |
1da177e4 LT |
7327 | |
7328 | if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) { | |
7329 | tg3_stop_fw(tp); | |
7330 | tw32(0x5000, 0x400); | |
7331 | } | |
7332 | ||
7333 | tw32(GRC_MODE, tp->grc_mode); | |
7334 | ||
7335 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) { | |
ab0049b4 | 7336 | val = tr32(0xc4); |
1da177e4 LT |
7337 | |
7338 | tw32(0xc4, val | (1 << 15)); | |
7339 | } | |
7340 | ||
7341 | if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 && | |
7342 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
7343 | tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE; | |
7344 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) | |
7345 | tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN; | |
7346 | tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); | |
7347 | } | |
7348 | ||
63c3a66f | 7349 | if (tg3_flag(tp, ENABLE_APE)) |
d2394e6b MC |
7350 | tp->mac_mode = MAC_MODE_APE_TX_EN | |
7351 | MAC_MODE_APE_RX_EN | | |
7352 | MAC_MODE_TDE_ENABLE; | |
7353 | ||
f07e9af3 | 7354 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
d2394e6b MC |
7355 | tp->mac_mode |= MAC_MODE_PORT_MODE_TBI; |
7356 | val = tp->mac_mode; | |
f07e9af3 | 7357 | } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { |
d2394e6b MC |
7358 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; |
7359 | val = tp->mac_mode; | |
1da177e4 | 7360 | } else |
d2394e6b MC |
7361 | val = 0; |
7362 | ||
7363 | tw32_f(MAC_MODE, val); | |
1da177e4 LT |
7364 | udelay(40); |
7365 | ||
77b483f1 MC |
7366 | tg3_ape_unlock(tp, TG3_APE_LOCK_GRC); |
7367 | ||
7a6f4369 MC |
7368 | err = tg3_poll_fw(tp); |
7369 | if (err) | |
7370 | return err; | |
1da177e4 | 7371 | |
0a9140cf MC |
7372 | tg3_mdio_start(tp); |
7373 | ||
63c3a66f | 7374 | if (tg3_flag(tp, PCI_EXPRESS) && |
f6eb9b1f MC |
7375 | tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 && |
7376 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && | |
63c3a66f | 7377 | !tg3_flag(tp, 57765_PLUS)) { |
ab0049b4 | 7378 | val = tr32(0x7c00); |
1da177e4 LT |
7379 | |
7380 | tw32(0x7c00, val | (1 << 25)); | |
7381 | } | |
7382 | ||
d78b59f5 MC |
7383 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { |
7384 | val = tr32(TG3_CPMU_CLCK_ORIDE); | |
7385 | tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN); | |
7386 | } | |
7387 | ||
1da177e4 | 7388 | /* Reprobe ASF enable state. */ |
63c3a66f JP |
7389 | tg3_flag_clear(tp, ENABLE_ASF); |
7390 | tg3_flag_clear(tp, ASF_NEW_HANDSHAKE); | |
1da177e4 LT |
7391 | tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); |
7392 | if (val == NIC_SRAM_DATA_SIG_MAGIC) { | |
7393 | u32 nic_cfg; | |
7394 | ||
7395 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); | |
7396 | if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) { | |
63c3a66f | 7397 | tg3_flag_set(tp, ENABLE_ASF); |
4ba526ce | 7398 | tp->last_event_jiffies = jiffies; |
63c3a66f JP |
7399 | if (tg3_flag(tp, 5750_PLUS)) |
7400 | tg3_flag_set(tp, ASF_NEW_HANDSHAKE); | |
1da177e4 LT |
7401 | } |
7402 | } | |
7403 | ||
7404 | return 0; | |
7405 | } | |
7406 | ||
7407 | /* tp->lock is held. */ | |
7408 | static void tg3_stop_fw(struct tg3 *tp) | |
7409 | { | |
63c3a66f | 7410 | if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) { |
7c5026aa MC |
7411 | /* Wait for RX cpu to ACK the previous event. */ |
7412 | tg3_wait_for_event_ack(tp); | |
1da177e4 LT |
7413 | |
7414 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW); | |
4ba526ce MC |
7415 | |
7416 | tg3_generate_fw_event(tp); | |
1da177e4 | 7417 | |
7c5026aa MC |
7418 | /* Wait for RX cpu to ACK this event. */ |
7419 | tg3_wait_for_event_ack(tp); | |
1da177e4 LT |
7420 | } |
7421 | } | |
7422 | ||
7423 | /* tp->lock is held. */ | |
944d980e | 7424 | static int tg3_halt(struct tg3 *tp, int kind, int silent) |
1da177e4 LT |
7425 | { |
7426 | int err; | |
7427 | ||
7428 | tg3_stop_fw(tp); | |
7429 | ||
944d980e | 7430 | tg3_write_sig_pre_reset(tp, kind); |
1da177e4 | 7431 | |
b3b7d6be | 7432 | tg3_abort_hw(tp, silent); |
1da177e4 LT |
7433 | err = tg3_chip_reset(tp); |
7434 | ||
daba2a63 MC |
7435 | __tg3_set_mac_addr(tp, 0); |
7436 | ||
944d980e MC |
7437 | tg3_write_sig_legacy(tp, kind); |
7438 | tg3_write_sig_post_reset(tp, kind); | |
1da177e4 LT |
7439 | |
7440 | if (err) | |
7441 | return err; | |
7442 | ||
7443 | return 0; | |
7444 | } | |
7445 | ||
1da177e4 LT |
7446 | #define RX_CPU_SCRATCH_BASE 0x30000 |
7447 | #define RX_CPU_SCRATCH_SIZE 0x04000 | |
7448 | #define TX_CPU_SCRATCH_BASE 0x34000 | |
7449 | #define TX_CPU_SCRATCH_SIZE 0x04000 | |
7450 | ||
7451 | /* tp->lock is held. */ | |
7452 | static int tg3_halt_cpu(struct tg3 *tp, u32 offset) | |
7453 | { | |
7454 | int i; | |
7455 | ||
63c3a66f | 7456 | BUG_ON(offset == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)); |
1da177e4 | 7457 | |
b5d3772c MC |
7458 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
7459 | u32 val = tr32(GRC_VCPU_EXT_CTRL); | |
7460 | ||
7461 | tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU); | |
7462 | return 0; | |
7463 | } | |
1da177e4 LT |
7464 | if (offset == RX_CPU_BASE) { |
7465 | for (i = 0; i < 10000; i++) { | |
7466 | tw32(offset + CPU_STATE, 0xffffffff); | |
7467 | tw32(offset + CPU_MODE, CPU_MODE_HALT); | |
7468 | if (tr32(offset + CPU_MODE) & CPU_MODE_HALT) | |
7469 | break; | |
7470 | } | |
7471 | ||
7472 | tw32(offset + CPU_STATE, 0xffffffff); | |
7473 | tw32_f(offset + CPU_MODE, CPU_MODE_HALT); | |
7474 | udelay(10); | |
7475 | } else { | |
7476 | for (i = 0; i < 10000; i++) { | |
7477 | tw32(offset + CPU_STATE, 0xffffffff); | |
7478 | tw32(offset + CPU_MODE, CPU_MODE_HALT); | |
7479 | if (tr32(offset + CPU_MODE) & CPU_MODE_HALT) | |
7480 | break; | |
7481 | } | |
7482 | } | |
7483 | ||
7484 | if (i >= 10000) { | |
05dbe005 JP |
7485 | netdev_err(tp->dev, "%s timed out, %s CPU\n", |
7486 | __func__, offset == RX_CPU_BASE ? "RX" : "TX"); | |
1da177e4 LT |
7487 | return -ENODEV; |
7488 | } | |
ec41c7df MC |
7489 | |
7490 | /* Clear firmware's nvram arbitration. */ | |
63c3a66f | 7491 | if (tg3_flag(tp, NVRAM)) |
ec41c7df | 7492 | tw32(NVRAM_SWARB, SWARB_REQ_CLR0); |
1da177e4 LT |
7493 | return 0; |
7494 | } | |
7495 | ||
7496 | struct fw_info { | |
077f849d JSR |
7497 | unsigned int fw_base; |
7498 | unsigned int fw_len; | |
7499 | const __be32 *fw_data; | |
1da177e4 LT |
7500 | }; |
7501 | ||
7502 | /* tp->lock is held. */ | |
7503 | static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base, | |
7504 | int cpu_scratch_size, struct fw_info *info) | |
7505 | { | |
ec41c7df | 7506 | int err, lock_err, i; |
1da177e4 LT |
7507 | void (*write_op)(struct tg3 *, u32, u32); |
7508 | ||
63c3a66f | 7509 | if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) { |
5129c3a3 MC |
7510 | netdev_err(tp->dev, |
7511 | "%s: Trying to load TX cpu firmware which is 5705\n", | |
05dbe005 | 7512 | __func__); |
1da177e4 LT |
7513 | return -EINVAL; |
7514 | } | |
7515 | ||
63c3a66f | 7516 | if (tg3_flag(tp, 5705_PLUS)) |
1da177e4 LT |
7517 | write_op = tg3_write_mem; |
7518 | else | |
7519 | write_op = tg3_write_indirect_reg32; | |
7520 | ||
1b628151 MC |
7521 | /* It is possible that bootcode is still loading at this point. |
7522 | * Get the nvram lock first before halting the cpu. | |
7523 | */ | |
ec41c7df | 7524 | lock_err = tg3_nvram_lock(tp); |
1da177e4 | 7525 | err = tg3_halt_cpu(tp, cpu_base); |
ec41c7df MC |
7526 | if (!lock_err) |
7527 | tg3_nvram_unlock(tp); | |
1da177e4 LT |
7528 | if (err) |
7529 | goto out; | |
7530 | ||
7531 | for (i = 0; i < cpu_scratch_size; i += sizeof(u32)) | |
7532 | write_op(tp, cpu_scratch_base + i, 0); | |
7533 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
7534 | tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT); | |
077f849d | 7535 | for (i = 0; i < (info->fw_len / sizeof(u32)); i++) |
1da177e4 | 7536 | write_op(tp, (cpu_scratch_base + |
077f849d | 7537 | (info->fw_base & 0xffff) + |
1da177e4 | 7538 | (i * sizeof(u32))), |
077f849d | 7539 | be32_to_cpu(info->fw_data[i])); |
1da177e4 LT |
7540 | |
7541 | err = 0; | |
7542 | ||
7543 | out: | |
1da177e4 LT |
7544 | return err; |
7545 | } | |
7546 | ||
7547 | /* tp->lock is held. */ | |
7548 | static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp) | |
7549 | { | |
7550 | struct fw_info info; | |
077f849d | 7551 | const __be32 *fw_data; |
1da177e4 LT |
7552 | int err, i; |
7553 | ||
077f849d JSR |
7554 | fw_data = (void *)tp->fw->data; |
7555 | ||
7556 | /* Firmware blob starts with version numbers, followed by | |
7557 | start address and length. We are setting complete length. | |
7558 | length = end_address_of_bss - start_address_of_text. | |
7559 | Remainder is the blob to be loaded contiguously | |
7560 | from start address. */ | |
7561 | ||
7562 | info.fw_base = be32_to_cpu(fw_data[1]); | |
7563 | info.fw_len = tp->fw->size - 12; | |
7564 | info.fw_data = &fw_data[3]; | |
1da177e4 LT |
7565 | |
7566 | err = tg3_load_firmware_cpu(tp, RX_CPU_BASE, | |
7567 | RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE, | |
7568 | &info); | |
7569 | if (err) | |
7570 | return err; | |
7571 | ||
7572 | err = tg3_load_firmware_cpu(tp, TX_CPU_BASE, | |
7573 | TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE, | |
7574 | &info); | |
7575 | if (err) | |
7576 | return err; | |
7577 | ||
7578 | /* Now startup only the RX cpu. */ | |
7579 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
077f849d | 7580 | tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base); |
1da177e4 LT |
7581 | |
7582 | for (i = 0; i < 5; i++) { | |
077f849d | 7583 | if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base) |
1da177e4 LT |
7584 | break; |
7585 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
7586 | tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT); | |
077f849d | 7587 | tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base); |
1da177e4 LT |
7588 | udelay(1000); |
7589 | } | |
7590 | if (i >= 5) { | |
5129c3a3 MC |
7591 | netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x " |
7592 | "should be %08x\n", __func__, | |
05dbe005 | 7593 | tr32(RX_CPU_BASE + CPU_PC), info.fw_base); |
1da177e4 LT |
7594 | return -ENODEV; |
7595 | } | |
7596 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
7597 | tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000); | |
7598 | ||
7599 | return 0; | |
7600 | } | |
7601 | ||
1da177e4 LT |
7602 | /* tp->lock is held. */ |
7603 | static int tg3_load_tso_firmware(struct tg3 *tp) | |
7604 | { | |
7605 | struct fw_info info; | |
077f849d | 7606 | const __be32 *fw_data; |
1da177e4 LT |
7607 | unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size; |
7608 | int err, i; | |
7609 | ||
63c3a66f JP |
7610 | if (tg3_flag(tp, HW_TSO_1) || |
7611 | tg3_flag(tp, HW_TSO_2) || | |
7612 | tg3_flag(tp, HW_TSO_3)) | |
1da177e4 LT |
7613 | return 0; |
7614 | ||
077f849d JSR |
7615 | fw_data = (void *)tp->fw->data; |
7616 | ||
7617 | /* Firmware blob starts with version numbers, followed by | |
7618 | start address and length. We are setting complete length. | |
7619 | length = end_address_of_bss - start_address_of_text. | |
7620 | Remainder is the blob to be loaded contiguously | |
7621 | from start address. */ | |
7622 | ||
7623 | info.fw_base = be32_to_cpu(fw_data[1]); | |
7624 | cpu_scratch_size = tp->fw_len; | |
7625 | info.fw_len = tp->fw->size - 12; | |
7626 | info.fw_data = &fw_data[3]; | |
7627 | ||
1da177e4 | 7628 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { |
1da177e4 LT |
7629 | cpu_base = RX_CPU_BASE; |
7630 | cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705; | |
1da177e4 | 7631 | } else { |
1da177e4 LT |
7632 | cpu_base = TX_CPU_BASE; |
7633 | cpu_scratch_base = TX_CPU_SCRATCH_BASE; | |
7634 | cpu_scratch_size = TX_CPU_SCRATCH_SIZE; | |
7635 | } | |
7636 | ||
7637 | err = tg3_load_firmware_cpu(tp, cpu_base, | |
7638 | cpu_scratch_base, cpu_scratch_size, | |
7639 | &info); | |
7640 | if (err) | |
7641 | return err; | |
7642 | ||
7643 | /* Now startup the cpu. */ | |
7644 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
077f849d | 7645 | tw32_f(cpu_base + CPU_PC, info.fw_base); |
1da177e4 LT |
7646 | |
7647 | for (i = 0; i < 5; i++) { | |
077f849d | 7648 | if (tr32(cpu_base + CPU_PC) == info.fw_base) |
1da177e4 LT |
7649 | break; |
7650 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
7651 | tw32(cpu_base + CPU_MODE, CPU_MODE_HALT); | |
077f849d | 7652 | tw32_f(cpu_base + CPU_PC, info.fw_base); |
1da177e4 LT |
7653 | udelay(1000); |
7654 | } | |
7655 | if (i >= 5) { | |
5129c3a3 MC |
7656 | netdev_err(tp->dev, |
7657 | "%s fails to set CPU PC, is %08x should be %08x\n", | |
05dbe005 | 7658 | __func__, tr32(cpu_base + CPU_PC), info.fw_base); |
1da177e4 LT |
7659 | return -ENODEV; |
7660 | } | |
7661 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
7662 | tw32_f(cpu_base + CPU_MODE, 0x00000000); | |
7663 | return 0; | |
7664 | } | |
7665 | ||
1da177e4 | 7666 | |
1da177e4 LT |
7667 | static int tg3_set_mac_addr(struct net_device *dev, void *p) |
7668 | { | |
7669 | struct tg3 *tp = netdev_priv(dev); | |
7670 | struct sockaddr *addr = p; | |
986e0aeb | 7671 | int err = 0, skip_mac_1 = 0; |
1da177e4 | 7672 | |
f9804ddb MC |
7673 | if (!is_valid_ether_addr(addr->sa_data)) |
7674 | return -EINVAL; | |
7675 | ||
1da177e4 LT |
7676 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); |
7677 | ||
e75f7c90 MC |
7678 | if (!netif_running(dev)) |
7679 | return 0; | |
7680 | ||
63c3a66f | 7681 | if (tg3_flag(tp, ENABLE_ASF)) { |
986e0aeb | 7682 | u32 addr0_high, addr0_low, addr1_high, addr1_low; |
58712ef9 | 7683 | |
986e0aeb MC |
7684 | addr0_high = tr32(MAC_ADDR_0_HIGH); |
7685 | addr0_low = tr32(MAC_ADDR_0_LOW); | |
7686 | addr1_high = tr32(MAC_ADDR_1_HIGH); | |
7687 | addr1_low = tr32(MAC_ADDR_1_LOW); | |
7688 | ||
7689 | /* Skip MAC addr 1 if ASF is using it. */ | |
7690 | if ((addr0_high != addr1_high || addr0_low != addr1_low) && | |
7691 | !(addr1_high == 0 && addr1_low == 0)) | |
7692 | skip_mac_1 = 1; | |
58712ef9 | 7693 | } |
986e0aeb MC |
7694 | spin_lock_bh(&tp->lock); |
7695 | __tg3_set_mac_addr(tp, skip_mac_1); | |
7696 | spin_unlock_bh(&tp->lock); | |
1da177e4 | 7697 | |
b9ec6c1b | 7698 | return err; |
1da177e4 LT |
7699 | } |
7700 | ||
7701 | /* tp->lock is held. */ | |
7702 | static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr, | |
7703 | dma_addr_t mapping, u32 maxlen_flags, | |
7704 | u32 nic_addr) | |
7705 | { | |
7706 | tg3_write_mem(tp, | |
7707 | (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH), | |
7708 | ((u64) mapping >> 32)); | |
7709 | tg3_write_mem(tp, | |
7710 | (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW), | |
7711 | ((u64) mapping & 0xffffffff)); | |
7712 | tg3_write_mem(tp, | |
7713 | (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS), | |
7714 | maxlen_flags); | |
7715 | ||
63c3a66f | 7716 | if (!tg3_flag(tp, 5705_PLUS)) |
1da177e4 LT |
7717 | tg3_write_mem(tp, |
7718 | (bdinfo_addr + TG3_BDINFO_NIC_ADDR), | |
7719 | nic_addr); | |
7720 | } | |
7721 | ||
7722 | static void __tg3_set_rx_mode(struct net_device *); | |
d244c892 | 7723 | static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec) |
15f9850d | 7724 | { |
b6080e12 MC |
7725 | int i; |
7726 | ||
63c3a66f | 7727 | if (!tg3_flag(tp, ENABLE_TSS)) { |
b6080e12 MC |
7728 | tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs); |
7729 | tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames); | |
7730 | tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq); | |
b6080e12 MC |
7731 | } else { |
7732 | tw32(HOSTCC_TXCOL_TICKS, 0); | |
7733 | tw32(HOSTCC_TXMAX_FRAMES, 0); | |
7734 | tw32(HOSTCC_TXCOAL_MAXF_INT, 0); | |
19cfaecc | 7735 | } |
b6080e12 | 7736 | |
63c3a66f | 7737 | if (!tg3_flag(tp, ENABLE_RSS)) { |
19cfaecc MC |
7738 | tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs); |
7739 | tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames); | |
7740 | tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq); | |
7741 | } else { | |
b6080e12 MC |
7742 | tw32(HOSTCC_RXCOL_TICKS, 0); |
7743 | tw32(HOSTCC_RXMAX_FRAMES, 0); | |
7744 | tw32(HOSTCC_RXCOAL_MAXF_INT, 0); | |
15f9850d | 7745 | } |
b6080e12 | 7746 | |
63c3a66f | 7747 | if (!tg3_flag(tp, 5705_PLUS)) { |
15f9850d DM |
7748 | u32 val = ec->stats_block_coalesce_usecs; |
7749 | ||
b6080e12 MC |
7750 | tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq); |
7751 | tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq); | |
7752 | ||
15f9850d DM |
7753 | if (!netif_carrier_ok(tp->dev)) |
7754 | val = 0; | |
7755 | ||
7756 | tw32(HOSTCC_STAT_COAL_TICKS, val); | |
7757 | } | |
b6080e12 MC |
7758 | |
7759 | for (i = 0; i < tp->irq_cnt - 1; i++) { | |
7760 | u32 reg; | |
7761 | ||
7762 | reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18; | |
7763 | tw32(reg, ec->rx_coalesce_usecs); | |
b6080e12 MC |
7764 | reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18; |
7765 | tw32(reg, ec->rx_max_coalesced_frames); | |
b6080e12 MC |
7766 | reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18; |
7767 | tw32(reg, ec->rx_max_coalesced_frames_irq); | |
19cfaecc | 7768 | |
63c3a66f | 7769 | if (tg3_flag(tp, ENABLE_TSS)) { |
19cfaecc MC |
7770 | reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18; |
7771 | tw32(reg, ec->tx_coalesce_usecs); | |
7772 | reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18; | |
7773 | tw32(reg, ec->tx_max_coalesced_frames); | |
7774 | reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18; | |
7775 | tw32(reg, ec->tx_max_coalesced_frames_irq); | |
7776 | } | |
b6080e12 MC |
7777 | } |
7778 | ||
7779 | for (; i < tp->irq_max - 1; i++) { | |
7780 | tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0); | |
b6080e12 | 7781 | tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0); |
b6080e12 | 7782 | tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0); |
19cfaecc | 7783 | |
63c3a66f | 7784 | if (tg3_flag(tp, ENABLE_TSS)) { |
19cfaecc MC |
7785 | tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0); |
7786 | tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0); | |
7787 | tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0); | |
7788 | } | |
b6080e12 | 7789 | } |
15f9850d | 7790 | } |
1da177e4 | 7791 | |
2d31ecaf MC |
7792 | /* tp->lock is held. */ |
7793 | static void tg3_rings_reset(struct tg3 *tp) | |
7794 | { | |
7795 | int i; | |
f77a6a8e | 7796 | u32 stblk, txrcb, rxrcb, limit; |
2d31ecaf MC |
7797 | struct tg3_napi *tnapi = &tp->napi[0]; |
7798 | ||
7799 | /* Disable all transmit rings but the first. */ | |
63c3a66f | 7800 | if (!tg3_flag(tp, 5705_PLUS)) |
2d31ecaf | 7801 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16; |
63c3a66f | 7802 | else if (tg3_flag(tp, 5717_PLUS)) |
3d37728b | 7803 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4; |
b703df6f MC |
7804 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) |
7805 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2; | |
2d31ecaf MC |
7806 | else |
7807 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; | |
7808 | ||
7809 | for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; | |
7810 | txrcb < limit; txrcb += TG3_BDINFO_SIZE) | |
7811 | tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS, | |
7812 | BDINFO_FLAGS_DISABLED); | |
7813 | ||
7814 | ||
7815 | /* Disable all receive return rings but the first. */ | |
63c3a66f | 7816 | if (tg3_flag(tp, 5717_PLUS)) |
f6eb9b1f | 7817 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17; |
63c3a66f | 7818 | else if (!tg3_flag(tp, 5705_PLUS)) |
2d31ecaf | 7819 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16; |
b703df6f MC |
7820 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || |
7821 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
2d31ecaf MC |
7822 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4; |
7823 | else | |
7824 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; | |
7825 | ||
7826 | for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; | |
7827 | rxrcb < limit; rxrcb += TG3_BDINFO_SIZE) | |
7828 | tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS, | |
7829 | BDINFO_FLAGS_DISABLED); | |
7830 | ||
7831 | /* Disable interrupts */ | |
7832 | tw32_mailbox_f(tp->napi[0].int_mbox, 1); | |
0e6cf6a9 MC |
7833 | tp->napi[0].chk_msi_cnt = 0; |
7834 | tp->napi[0].last_rx_cons = 0; | |
7835 | tp->napi[0].last_tx_cons = 0; | |
2d31ecaf MC |
7836 | |
7837 | /* Zero mailbox registers. */ | |
63c3a66f | 7838 | if (tg3_flag(tp, SUPPORT_MSIX)) { |
6fd45cb8 | 7839 | for (i = 1; i < tp->irq_max; i++) { |
f77a6a8e MC |
7840 | tp->napi[i].tx_prod = 0; |
7841 | tp->napi[i].tx_cons = 0; | |
63c3a66f | 7842 | if (tg3_flag(tp, ENABLE_TSS)) |
c2353a32 | 7843 | tw32_mailbox(tp->napi[i].prodmbox, 0); |
f77a6a8e MC |
7844 | tw32_rx_mbox(tp->napi[i].consmbox, 0); |
7845 | tw32_mailbox_f(tp->napi[i].int_mbox, 1); | |
0e6cf6a9 MC |
7846 | tp->napi[0].chk_msi_cnt = 0; |
7847 | tp->napi[i].last_rx_cons = 0; | |
7848 | tp->napi[i].last_tx_cons = 0; | |
f77a6a8e | 7849 | } |
63c3a66f | 7850 | if (!tg3_flag(tp, ENABLE_TSS)) |
c2353a32 | 7851 | tw32_mailbox(tp->napi[0].prodmbox, 0); |
f77a6a8e MC |
7852 | } else { |
7853 | tp->napi[0].tx_prod = 0; | |
7854 | tp->napi[0].tx_cons = 0; | |
7855 | tw32_mailbox(tp->napi[0].prodmbox, 0); | |
7856 | tw32_rx_mbox(tp->napi[0].consmbox, 0); | |
7857 | } | |
2d31ecaf MC |
7858 | |
7859 | /* Make sure the NIC-based send BD rings are disabled. */ | |
63c3a66f | 7860 | if (!tg3_flag(tp, 5705_PLUS)) { |
2d31ecaf MC |
7861 | u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW; |
7862 | for (i = 0; i < 16; i++) | |
7863 | tw32_tx_mbox(mbox + i * 8, 0); | |
7864 | } | |
7865 | ||
7866 | txrcb = NIC_SRAM_SEND_RCB; | |
7867 | rxrcb = NIC_SRAM_RCV_RET_RCB; | |
7868 | ||
7869 | /* Clear status block in ram. */ | |
7870 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
7871 | ||
7872 | /* Set status block DMA address */ | |
7873 | tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, | |
7874 | ((u64) tnapi->status_mapping >> 32)); | |
7875 | tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, | |
7876 | ((u64) tnapi->status_mapping & 0xffffffff)); | |
7877 | ||
f77a6a8e MC |
7878 | if (tnapi->tx_ring) { |
7879 | tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping, | |
7880 | (TG3_TX_RING_SIZE << | |
7881 | BDINFO_FLAGS_MAXLEN_SHIFT), | |
7882 | NIC_SRAM_TX_BUFFER_DESC); | |
7883 | txrcb += TG3_BDINFO_SIZE; | |
7884 | } | |
7885 | ||
7886 | if (tnapi->rx_rcb) { | |
7887 | tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping, | |
7cb32cf2 MC |
7888 | (tp->rx_ret_ring_mask + 1) << |
7889 | BDINFO_FLAGS_MAXLEN_SHIFT, 0); | |
f77a6a8e MC |
7890 | rxrcb += TG3_BDINFO_SIZE; |
7891 | } | |
7892 | ||
7893 | stblk = HOSTCC_STATBLCK_RING1; | |
2d31ecaf | 7894 | |
f77a6a8e MC |
7895 | for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) { |
7896 | u64 mapping = (u64)tnapi->status_mapping; | |
7897 | tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32); | |
7898 | tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff); | |
7899 | ||
7900 | /* Clear status block in ram. */ | |
7901 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
7902 | ||
19cfaecc MC |
7903 | if (tnapi->tx_ring) { |
7904 | tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping, | |
7905 | (TG3_TX_RING_SIZE << | |
7906 | BDINFO_FLAGS_MAXLEN_SHIFT), | |
7907 | NIC_SRAM_TX_BUFFER_DESC); | |
7908 | txrcb += TG3_BDINFO_SIZE; | |
7909 | } | |
f77a6a8e MC |
7910 | |
7911 | tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping, | |
7cb32cf2 | 7912 | ((tp->rx_ret_ring_mask + 1) << |
f77a6a8e MC |
7913 | BDINFO_FLAGS_MAXLEN_SHIFT), 0); |
7914 | ||
7915 | stblk += 8; | |
f77a6a8e MC |
7916 | rxrcb += TG3_BDINFO_SIZE; |
7917 | } | |
2d31ecaf MC |
7918 | } |
7919 | ||
eb07a940 MC |
7920 | static void tg3_setup_rxbd_thresholds(struct tg3 *tp) |
7921 | { | |
7922 | u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh; | |
7923 | ||
63c3a66f JP |
7924 | if (!tg3_flag(tp, 5750_PLUS) || |
7925 | tg3_flag(tp, 5780_CLASS) || | |
eb07a940 MC |
7926 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || |
7927 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) | |
7928 | bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700; | |
7929 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || | |
7930 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) | |
7931 | bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755; | |
7932 | else | |
7933 | bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906; | |
7934 | ||
7935 | nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post); | |
7936 | host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1); | |
7937 | ||
7938 | val = min(nic_rep_thresh, host_rep_thresh); | |
7939 | tw32(RCVBDI_STD_THRESH, val); | |
7940 | ||
63c3a66f | 7941 | if (tg3_flag(tp, 57765_PLUS)) |
eb07a940 MC |
7942 | tw32(STD_REPLENISH_LWM, bdcache_maxcnt); |
7943 | ||
63c3a66f | 7944 | if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS)) |
eb07a940 MC |
7945 | return; |
7946 | ||
63c3a66f | 7947 | if (!tg3_flag(tp, 5705_PLUS)) |
eb07a940 MC |
7948 | bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700; |
7949 | else | |
7950 | bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5717; | |
7951 | ||
7952 | host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1); | |
7953 | ||
7954 | val = min(bdcache_maxcnt / 2, host_rep_thresh); | |
7955 | tw32(RCVBDI_JUMBO_THRESH, val); | |
7956 | ||
63c3a66f | 7957 | if (tg3_flag(tp, 57765_PLUS)) |
eb07a940 MC |
7958 | tw32(JMB_REPLENISH_LWM, bdcache_maxcnt); |
7959 | } | |
7960 | ||
1da177e4 | 7961 | /* tp->lock is held. */ |
8e7a22e3 | 7962 | static int tg3_reset_hw(struct tg3 *tp, int reset_phy) |
1da177e4 LT |
7963 | { |
7964 | u32 val, rdmac_mode; | |
7965 | int i, err, limit; | |
8fea32b9 | 7966 | struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; |
1da177e4 LT |
7967 | |
7968 | tg3_disable_ints(tp); | |
7969 | ||
7970 | tg3_stop_fw(tp); | |
7971 | ||
7972 | tg3_write_sig_pre_reset(tp, RESET_KIND_INIT); | |
7973 | ||
63c3a66f | 7974 | if (tg3_flag(tp, INIT_COMPLETE)) |
e6de8ad1 | 7975 | tg3_abort_hw(tp, 1); |
1da177e4 | 7976 | |
699c0193 MC |
7977 | /* Enable MAC control of LPI */ |
7978 | if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) { | |
7979 | tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, | |
7980 | TG3_CPMU_EEE_LNKIDL_PCIE_NL0 | | |
7981 | TG3_CPMU_EEE_LNKIDL_UART_IDL); | |
7982 | ||
7983 | tw32_f(TG3_CPMU_EEE_CTRL, | |
7984 | TG3_CPMU_EEE_CTRL_EXIT_20_1_US); | |
7985 | ||
a386b901 MC |
7986 | val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET | |
7987 | TG3_CPMU_EEEMD_LPI_IN_TX | | |
7988 | TG3_CPMU_EEEMD_LPI_IN_RX | | |
7989 | TG3_CPMU_EEEMD_EEE_ENABLE; | |
7990 | ||
7991 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) | |
7992 | val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN; | |
7993 | ||
63c3a66f | 7994 | if (tg3_flag(tp, ENABLE_APE)) |
a386b901 MC |
7995 | val |= TG3_CPMU_EEEMD_APE_TX_DET_EN; |
7996 | ||
7997 | tw32_f(TG3_CPMU_EEE_MODE, val); | |
7998 | ||
7999 | tw32_f(TG3_CPMU_EEE_DBTMR1, | |
8000 | TG3_CPMU_DBTMR1_PCIEXIT_2047US | | |
8001 | TG3_CPMU_DBTMR1_LNKIDLE_2047US); | |
8002 | ||
8003 | tw32_f(TG3_CPMU_EEE_DBTMR2, | |
d7f2ab20 | 8004 | TG3_CPMU_DBTMR2_APE_TX_2047US | |
a386b901 | 8005 | TG3_CPMU_DBTMR2_TXIDXEQ_2047US); |
699c0193 MC |
8006 | } |
8007 | ||
603f1173 | 8008 | if (reset_phy) |
d4d2c558 MC |
8009 | tg3_phy_reset(tp); |
8010 | ||
1da177e4 LT |
8011 | err = tg3_chip_reset(tp); |
8012 | if (err) | |
8013 | return err; | |
8014 | ||
8015 | tg3_write_sig_legacy(tp, RESET_KIND_INIT); | |
8016 | ||
bcb37f6c | 8017 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) { |
d30cdd28 MC |
8018 | val = tr32(TG3_CPMU_CTRL); |
8019 | val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE); | |
8020 | tw32(TG3_CPMU_CTRL, val); | |
9acb961e MC |
8021 | |
8022 | val = tr32(TG3_CPMU_LSPD_10MB_CLK); | |
8023 | val &= ~CPMU_LSPD_10MB_MACCLK_MASK; | |
8024 | val |= CPMU_LSPD_10MB_MACCLK_6_25; | |
8025 | tw32(TG3_CPMU_LSPD_10MB_CLK, val); | |
8026 | ||
8027 | val = tr32(TG3_CPMU_LNK_AWARE_PWRMD); | |
8028 | val &= ~CPMU_LNK_AWARE_MACCLK_MASK; | |
8029 | val |= CPMU_LNK_AWARE_MACCLK_6_25; | |
8030 | tw32(TG3_CPMU_LNK_AWARE_PWRMD, val); | |
8031 | ||
8032 | val = tr32(TG3_CPMU_HST_ACC); | |
8033 | val &= ~CPMU_HST_ACC_MACCLK_MASK; | |
8034 | val |= CPMU_HST_ACC_MACCLK_6_25; | |
8035 | tw32(TG3_CPMU_HST_ACC, val); | |
d30cdd28 MC |
8036 | } |
8037 | ||
33466d93 MC |
8038 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { |
8039 | val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK; | |
8040 | val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN | | |
8041 | PCIE_PWR_MGMT_L1_THRESH_4MS; | |
8042 | tw32(PCIE_PWR_MGMT_THRESH, val); | |
521e6b90 MC |
8043 | |
8044 | val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK; | |
8045 | tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS); | |
8046 | ||
8047 | tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR); | |
33466d93 | 8048 | |
f40386c8 MC |
8049 | val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN; |
8050 | tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS); | |
255ca311 MC |
8051 | } |
8052 | ||
63c3a66f | 8053 | if (tg3_flag(tp, L1PLLPD_EN)) { |
614b0590 MC |
8054 | u32 grc_mode = tr32(GRC_MODE); |
8055 | ||
8056 | /* Access the lower 1K of PL PCIE block registers. */ | |
8057 | val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK; | |
8058 | tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL); | |
8059 | ||
8060 | val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1); | |
8061 | tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1, | |
8062 | val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN); | |
8063 | ||
8064 | tw32(GRC_MODE, grc_mode); | |
8065 | } | |
8066 | ||
5093eedc MC |
8067 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) { |
8068 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) { | |
8069 | u32 grc_mode = tr32(GRC_MODE); | |
cea46462 | 8070 | |
5093eedc MC |
8071 | /* Access the lower 1K of PL PCIE block registers. */ |
8072 | val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK; | |
8073 | tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL); | |
cea46462 | 8074 | |
5093eedc MC |
8075 | val = tr32(TG3_PCIE_TLDLPL_PORT + |
8076 | TG3_PCIE_PL_LO_PHYCTL5); | |
8077 | tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5, | |
8078 | val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ); | |
cea46462 | 8079 | |
5093eedc MC |
8080 | tw32(GRC_MODE, grc_mode); |
8081 | } | |
a977dbe8 | 8082 | |
1ff30a59 MC |
8083 | if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_57765_AX) { |
8084 | u32 grc_mode = tr32(GRC_MODE); | |
8085 | ||
8086 | /* Access the lower 1K of DL PCIE block registers. */ | |
8087 | val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK; | |
8088 | tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL); | |
8089 | ||
8090 | val = tr32(TG3_PCIE_TLDLPL_PORT + | |
8091 | TG3_PCIE_DL_LO_FTSMAX); | |
8092 | val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK; | |
8093 | tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX, | |
8094 | val | TG3_PCIE_DL_LO_FTSMAX_VAL); | |
8095 | ||
8096 | tw32(GRC_MODE, grc_mode); | |
8097 | } | |
8098 | ||
a977dbe8 MC |
8099 | val = tr32(TG3_CPMU_LSPD_10MB_CLK); |
8100 | val &= ~CPMU_LSPD_10MB_MACCLK_MASK; | |
8101 | val |= CPMU_LSPD_10MB_MACCLK_6_25; | |
8102 | tw32(TG3_CPMU_LSPD_10MB_CLK, val); | |
cea46462 MC |
8103 | } |
8104 | ||
1da177e4 LT |
8105 | /* This works around an issue with Athlon chipsets on |
8106 | * B3 tigon3 silicon. This bit has no effect on any | |
8107 | * other revision. But do not set this on PCI Express | |
795d01c5 | 8108 | * chips and don't even touch the clocks if the CPMU is present. |
1da177e4 | 8109 | */ |
63c3a66f JP |
8110 | if (!tg3_flag(tp, CPMU_PRESENT)) { |
8111 | if (!tg3_flag(tp, PCI_EXPRESS)) | |
795d01c5 MC |
8112 | tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT; |
8113 | tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); | |
8114 | } | |
1da177e4 LT |
8115 | |
8116 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 && | |
63c3a66f | 8117 | tg3_flag(tp, PCIX_MODE)) { |
1da177e4 LT |
8118 | val = tr32(TG3PCI_PCISTATE); |
8119 | val |= PCISTATE_RETRY_SAME_DMA; | |
8120 | tw32(TG3PCI_PCISTATE, val); | |
8121 | } | |
8122 | ||
63c3a66f | 8123 | if (tg3_flag(tp, ENABLE_APE)) { |
0d3031d9 MC |
8124 | /* Allow reads and writes to the |
8125 | * APE register and memory space. | |
8126 | */ | |
8127 | val = tr32(TG3PCI_PCISTATE); | |
8128 | val |= PCISTATE_ALLOW_APE_CTLSPC_WR | | |
f92d9dc1 MC |
8129 | PCISTATE_ALLOW_APE_SHMEM_WR | |
8130 | PCISTATE_ALLOW_APE_PSPACE_WR; | |
0d3031d9 MC |
8131 | tw32(TG3PCI_PCISTATE, val); |
8132 | } | |
8133 | ||
1da177e4 LT |
8134 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) { |
8135 | /* Enable some hw fixes. */ | |
8136 | val = tr32(TG3PCI_MSI_DATA); | |
8137 | val |= (1 << 26) | (1 << 28) | (1 << 29); | |
8138 | tw32(TG3PCI_MSI_DATA, val); | |
8139 | } | |
8140 | ||
8141 | /* Descriptor ring init may make accesses to the | |
8142 | * NIC SRAM area to setup the TX descriptors, so we | |
8143 | * can only do this after the hardware has been | |
8144 | * successfully reset. | |
8145 | */ | |
32d8c572 MC |
8146 | err = tg3_init_rings(tp); |
8147 | if (err) | |
8148 | return err; | |
1da177e4 | 8149 | |
63c3a66f | 8150 | if (tg3_flag(tp, 57765_PLUS)) { |
cbf9ca6c MC |
8151 | val = tr32(TG3PCI_DMA_RW_CTRL) & |
8152 | ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT; | |
1a319025 MC |
8153 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) |
8154 | val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK; | |
0aebff48 MC |
8155 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 && |
8156 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) | |
8157 | val |= DMA_RWCTRL_TAGGED_STAT_WA; | |
cbf9ca6c MC |
8158 | tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl); |
8159 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 && | |
8160 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) { | |
d30cdd28 MC |
8161 | /* This value is determined during the probe time DMA |
8162 | * engine test, tg3_test_dma. | |
8163 | */ | |
8164 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
8165 | } | |
1da177e4 LT |
8166 | |
8167 | tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS | | |
8168 | GRC_MODE_4X_NIC_SEND_RINGS | | |
8169 | GRC_MODE_NO_TX_PHDR_CSUM | | |
8170 | GRC_MODE_NO_RX_PHDR_CSUM); | |
8171 | tp->grc_mode |= GRC_MODE_HOST_SENDBDS; | |
d2d746f8 MC |
8172 | |
8173 | /* Pseudo-header checksum is done by hardware logic and not | |
8174 | * the offload processers, so make the chip do the pseudo- | |
8175 | * header checksums on receive. For transmit it is more | |
8176 | * convenient to do the pseudo-header checksum in software | |
8177 | * as Linux does that on transmit for us in all cases. | |
8178 | */ | |
8179 | tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM; | |
1da177e4 LT |
8180 | |
8181 | tw32(GRC_MODE, | |
8182 | tp->grc_mode | | |
8183 | (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP)); | |
8184 | ||
8185 | /* Setup the timer prescalar register. Clock is always 66Mhz. */ | |
8186 | val = tr32(GRC_MISC_CFG); | |
8187 | val &= ~0xff; | |
8188 | val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT); | |
8189 | tw32(GRC_MISC_CFG, val); | |
8190 | ||
8191 | /* Initialize MBUF/DESC pool. */ | |
63c3a66f | 8192 | if (tg3_flag(tp, 5750_PLUS)) { |
1da177e4 LT |
8193 | /* Do nothing. */ |
8194 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) { | |
8195 | tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE); | |
8196 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) | |
8197 | tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64); | |
8198 | else | |
8199 | tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96); | |
8200 | tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE); | |
8201 | tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE); | |
63c3a66f | 8202 | } else if (tg3_flag(tp, TSO_CAPABLE)) { |
1da177e4 LT |
8203 | int fw_len; |
8204 | ||
077f849d | 8205 | fw_len = tp->fw_len; |
1da177e4 LT |
8206 | fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1); |
8207 | tw32(BUFMGR_MB_POOL_ADDR, | |
8208 | NIC_SRAM_MBUF_POOL_BASE5705 + fw_len); | |
8209 | tw32(BUFMGR_MB_POOL_SIZE, | |
8210 | NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00); | |
8211 | } | |
1da177e4 | 8212 | |
0f893dc6 | 8213 | if (tp->dev->mtu <= ETH_DATA_LEN) { |
1da177e4 LT |
8214 | tw32(BUFMGR_MB_RDMA_LOW_WATER, |
8215 | tp->bufmgr_config.mbuf_read_dma_low_water); | |
8216 | tw32(BUFMGR_MB_MACRX_LOW_WATER, | |
8217 | tp->bufmgr_config.mbuf_mac_rx_low_water); | |
8218 | tw32(BUFMGR_MB_HIGH_WATER, | |
8219 | tp->bufmgr_config.mbuf_high_water); | |
8220 | } else { | |
8221 | tw32(BUFMGR_MB_RDMA_LOW_WATER, | |
8222 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo); | |
8223 | tw32(BUFMGR_MB_MACRX_LOW_WATER, | |
8224 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo); | |
8225 | tw32(BUFMGR_MB_HIGH_WATER, | |
8226 | tp->bufmgr_config.mbuf_high_water_jumbo); | |
8227 | } | |
8228 | tw32(BUFMGR_DMA_LOW_WATER, | |
8229 | tp->bufmgr_config.dma_low_water); | |
8230 | tw32(BUFMGR_DMA_HIGH_WATER, | |
8231 | tp->bufmgr_config.dma_high_water); | |
8232 | ||
d309a46e MC |
8233 | val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE; |
8234 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | |
8235 | val |= BUFMGR_MODE_NO_TX_UNDERRUN; | |
4d958473 MC |
8236 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
8237 | tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 || | |
8238 | tp->pci_chip_rev_id == CHIPREV_ID_5720_A0) | |
8239 | val |= BUFMGR_MODE_MBLOW_ATTN_ENAB; | |
d309a46e | 8240 | tw32(BUFMGR_MODE, val); |
1da177e4 LT |
8241 | for (i = 0; i < 2000; i++) { |
8242 | if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE) | |
8243 | break; | |
8244 | udelay(10); | |
8245 | } | |
8246 | if (i >= 2000) { | |
05dbe005 | 8247 | netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__); |
1da177e4 LT |
8248 | return -ENODEV; |
8249 | } | |
8250 | ||
eb07a940 MC |
8251 | if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1) |
8252 | tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2); | |
b5d3772c | 8253 | |
eb07a940 | 8254 | tg3_setup_rxbd_thresholds(tp); |
1da177e4 LT |
8255 | |
8256 | /* Initialize TG3_BDINFO's at: | |
8257 | * RCVDBDI_STD_BD: standard eth size rx ring | |
8258 | * RCVDBDI_JUMBO_BD: jumbo frame rx ring | |
8259 | * RCVDBDI_MINI_BD: small frame rx ring (??? does not work) | |
8260 | * | |
8261 | * like so: | |
8262 | * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring | |
8263 | * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) | | |
8264 | * ring attribute flags | |
8265 | * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM | |
8266 | * | |
8267 | * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries. | |
8268 | * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries. | |
8269 | * | |
8270 | * The size of each ring is fixed in the firmware, but the location is | |
8271 | * configurable. | |
8272 | */ | |
8273 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, | |
21f581a5 | 8274 | ((u64) tpr->rx_std_mapping >> 32)); |
1da177e4 | 8275 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, |
21f581a5 | 8276 | ((u64) tpr->rx_std_mapping & 0xffffffff)); |
63c3a66f | 8277 | if (!tg3_flag(tp, 5717_PLUS)) |
87668d35 MC |
8278 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR, |
8279 | NIC_SRAM_RX_BUFFER_DESC); | |
1da177e4 | 8280 | |
fdb72b38 | 8281 | /* Disable the mini ring */ |
63c3a66f | 8282 | if (!tg3_flag(tp, 5705_PLUS)) |
1da177e4 LT |
8283 | tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS, |
8284 | BDINFO_FLAGS_DISABLED); | |
8285 | ||
fdb72b38 MC |
8286 | /* Program the jumbo buffer descriptor ring control |
8287 | * blocks on those devices that have them. | |
8288 | */ | |
bb18bb94 | 8289 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
63c3a66f | 8290 | (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) { |
1da177e4 | 8291 | |
63c3a66f | 8292 | if (tg3_flag(tp, JUMBO_RING_ENABLE)) { |
1da177e4 | 8293 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, |
21f581a5 | 8294 | ((u64) tpr->rx_jmb_mapping >> 32)); |
1da177e4 | 8295 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, |
21f581a5 | 8296 | ((u64) tpr->rx_jmb_mapping & 0xffffffff)); |
de9f5230 MC |
8297 | val = TG3_RX_JMB_RING_SIZE(tp) << |
8298 | BDINFO_FLAGS_MAXLEN_SHIFT; | |
1da177e4 | 8299 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS, |
de9f5230 | 8300 | val | BDINFO_FLAGS_USE_EXT_RECV); |
63c3a66f | 8301 | if (!tg3_flag(tp, USE_JUMBO_BDFLAG) || |
a50d0796 | 8302 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) |
87668d35 MC |
8303 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR, |
8304 | NIC_SRAM_RX_JUMBO_BUFFER_DESC); | |
1da177e4 LT |
8305 | } else { |
8306 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS, | |
8307 | BDINFO_FLAGS_DISABLED); | |
8308 | } | |
8309 | ||
63c3a66f | 8310 | if (tg3_flag(tp, 57765_PLUS)) { |
7cb32cf2 | 8311 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) |
de9f5230 | 8312 | val = TG3_RX_STD_MAX_SIZE_5700; |
7cb32cf2 | 8313 | else |
de9f5230 | 8314 | val = TG3_RX_STD_MAX_SIZE_5717; |
7cb32cf2 MC |
8315 | val <<= BDINFO_FLAGS_MAXLEN_SHIFT; |
8316 | val |= (TG3_RX_STD_DMA_SZ << 2); | |
8317 | } else | |
04380d40 | 8318 | val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT; |
fdb72b38 | 8319 | } else |
de9f5230 | 8320 | val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT; |
fdb72b38 MC |
8321 | |
8322 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val); | |
1da177e4 | 8323 | |
411da640 | 8324 | tpr->rx_std_prod_idx = tp->rx_pending; |
66711e66 | 8325 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx); |
1da177e4 | 8326 | |
63c3a66f JP |
8327 | tpr->rx_jmb_prod_idx = |
8328 | tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0; | |
66711e66 | 8329 | tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx); |
1da177e4 | 8330 | |
2d31ecaf MC |
8331 | tg3_rings_reset(tp); |
8332 | ||
1da177e4 | 8333 | /* Initialize MAC address and backoff seed. */ |
986e0aeb | 8334 | __tg3_set_mac_addr(tp, 0); |
1da177e4 LT |
8335 | |
8336 | /* MTU + ethernet header + FCS + optional VLAN tag */ | |
f7b493e0 MC |
8337 | tw32(MAC_RX_MTU_SIZE, |
8338 | tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN); | |
1da177e4 LT |
8339 | |
8340 | /* The slot time is changed by tg3_setup_phy if we | |
8341 | * run at gigabit with half duplex. | |
8342 | */ | |
f2096f94 MC |
8343 | val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) | |
8344 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
8345 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT); | |
8346 | ||
8347 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
8348 | val |= tr32(MAC_TX_LENGTHS) & | |
8349 | (TX_LENGTHS_JMB_FRM_LEN_MSK | | |
8350 | TX_LENGTHS_CNT_DWN_VAL_MSK); | |
8351 | ||
8352 | tw32(MAC_TX_LENGTHS, val); | |
1da177e4 LT |
8353 | |
8354 | /* Receive rules. */ | |
8355 | tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS); | |
8356 | tw32(RCVLPC_CONFIG, 0x0181); | |
8357 | ||
8358 | /* Calculate RDMAC_MODE setting early, we need it to determine | |
8359 | * the RCVLPC_STATE_ENABLE mask. | |
8360 | */ | |
8361 | rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB | | |
8362 | RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB | | |
8363 | RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB | | |
8364 | RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB | | |
8365 | RDMAC_MODE_LNGREAD_ENAB); | |
85e94ced | 8366 | |
deabaac8 | 8367 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) |
0339e4e3 MC |
8368 | rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS; |
8369 | ||
57e6983c | 8370 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
321d32a0 MC |
8371 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
8372 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
d30cdd28 MC |
8373 | rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB | |
8374 | RDMAC_MODE_MBUF_RBD_CRPT_ENAB | | |
8375 | RDMAC_MODE_MBUF_SBD_CRPT_ENAB; | |
8376 | ||
c5908939 MC |
8377 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && |
8378 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { | |
63c3a66f | 8379 | if (tg3_flag(tp, TSO_CAPABLE) && |
c13e3713 | 8380 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { |
1da177e4 LT |
8381 | rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128; |
8382 | } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && | |
63c3a66f | 8383 | !tg3_flag(tp, IS_5788)) { |
1da177e4 LT |
8384 | rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST; |
8385 | } | |
8386 | } | |
8387 | ||
63c3a66f | 8388 | if (tg3_flag(tp, PCI_EXPRESS)) |
85e94ced MC |
8389 | rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST; |
8390 | ||
63c3a66f JP |
8391 | if (tg3_flag(tp, HW_TSO_1) || |
8392 | tg3_flag(tp, HW_TSO_2) || | |
8393 | tg3_flag(tp, HW_TSO_3)) | |
027455ad MC |
8394 | rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN; |
8395 | ||
108a6c16 | 8396 | if (tg3_flag(tp, 57765_PLUS) || |
e849cdc3 | 8397 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
027455ad MC |
8398 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) |
8399 | rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN; | |
1da177e4 | 8400 | |
f2096f94 MC |
8401 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) |
8402 | rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET; | |
8403 | ||
41a8a7ee MC |
8404 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
8405 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || | |
8406 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || | |
8407 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || | |
63c3a66f | 8408 | tg3_flag(tp, 57765_PLUS)) { |
41a8a7ee | 8409 | val = tr32(TG3_RDMA_RSRVCTRL_REG); |
d78b59f5 MC |
8410 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
8411 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
b4495ed8 MC |
8412 | val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK | |
8413 | TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK | | |
8414 | TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK); | |
8415 | val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B | | |
8416 | TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K | | |
8417 | TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K; | |
b75cc0e4 | 8418 | } |
41a8a7ee MC |
8419 | tw32(TG3_RDMA_RSRVCTRL_REG, |
8420 | val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX); | |
8421 | } | |
8422 | ||
d78b59f5 MC |
8423 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
8424 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
d309a46e MC |
8425 | val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL); |
8426 | tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val | | |
8427 | TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K | | |
8428 | TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K); | |
8429 | } | |
8430 | ||
1da177e4 | 8431 | /* Receive/send statistics. */ |
63c3a66f | 8432 | if (tg3_flag(tp, 5750_PLUS)) { |
1661394e MC |
8433 | val = tr32(RCVLPC_STATS_ENABLE); |
8434 | val &= ~RCVLPC_STATSENAB_DACK_FIX; | |
8435 | tw32(RCVLPC_STATS_ENABLE, val); | |
8436 | } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) && | |
63c3a66f | 8437 | tg3_flag(tp, TSO_CAPABLE)) { |
1da177e4 LT |
8438 | val = tr32(RCVLPC_STATS_ENABLE); |
8439 | val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX; | |
8440 | tw32(RCVLPC_STATS_ENABLE, val); | |
8441 | } else { | |
8442 | tw32(RCVLPC_STATS_ENABLE, 0xffffff); | |
8443 | } | |
8444 | tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE); | |
8445 | tw32(SNDDATAI_STATSENAB, 0xffffff); | |
8446 | tw32(SNDDATAI_STATSCTRL, | |
8447 | (SNDDATAI_SCTRL_ENABLE | | |
8448 | SNDDATAI_SCTRL_FASTUPD)); | |
8449 | ||
8450 | /* Setup host coalescing engine. */ | |
8451 | tw32(HOSTCC_MODE, 0); | |
8452 | for (i = 0; i < 2000; i++) { | |
8453 | if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE)) | |
8454 | break; | |
8455 | udelay(10); | |
8456 | } | |
8457 | ||
d244c892 | 8458 | __tg3_set_coalesce(tp, &tp->coal); |
1da177e4 | 8459 | |
63c3a66f | 8460 | if (!tg3_flag(tp, 5705_PLUS)) { |
1da177e4 LT |
8461 | /* Status/statistics block address. See tg3_timer, |
8462 | * the tg3_periodic_fetch_stats call there, and | |
8463 | * tg3_get_stats to see how this works for 5705/5750 chips. | |
8464 | */ | |
1da177e4 LT |
8465 | tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, |
8466 | ((u64) tp->stats_mapping >> 32)); | |
8467 | tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, | |
8468 | ((u64) tp->stats_mapping & 0xffffffff)); | |
8469 | tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK); | |
2d31ecaf | 8470 | |
1da177e4 | 8471 | tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK); |
2d31ecaf MC |
8472 | |
8473 | /* Clear statistics and status block memory areas */ | |
8474 | for (i = NIC_SRAM_STATS_BLK; | |
8475 | i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE; | |
8476 | i += sizeof(u32)) { | |
8477 | tg3_write_mem(tp, i, 0); | |
8478 | udelay(40); | |
8479 | } | |
1da177e4 LT |
8480 | } |
8481 | ||
8482 | tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode); | |
8483 | ||
8484 | tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE); | |
8485 | tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE); | |
63c3a66f | 8486 | if (!tg3_flag(tp, 5705_PLUS)) |
1da177e4 LT |
8487 | tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE); |
8488 | ||
f07e9af3 MC |
8489 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { |
8490 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; | |
c94e3941 MC |
8491 | /* reset to prevent losing 1st rx packet intermittently */ |
8492 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); | |
8493 | udelay(10); | |
8494 | } | |
8495 | ||
63c3a66f | 8496 | if (tg3_flag(tp, ENABLE_APE)) |
d2394e6b | 8497 | tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; |
3bda1258 MC |
8498 | else |
8499 | tp->mac_mode = 0; | |
8500 | tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE | | |
1da177e4 | 8501 | MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE; |
63c3a66f | 8502 | if (!tg3_flag(tp, 5705_PLUS) && |
f07e9af3 | 8503 | !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
e8f3f6ca MC |
8504 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) |
8505 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; | |
1da177e4 LT |
8506 | tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR); |
8507 | udelay(40); | |
8508 | ||
314fba34 | 8509 | /* tp->grc_local_ctrl is partially set up during tg3_get_invariants(). |
63c3a66f | 8510 | * If TG3_FLAG_IS_NIC is zero, we should read the |
314fba34 MC |
8511 | * register to preserve the GPIO settings for LOMs. The GPIOs, |
8512 | * whether used as inputs or outputs, are set by boot code after | |
8513 | * reset. | |
8514 | */ | |
63c3a66f | 8515 | if (!tg3_flag(tp, IS_NIC)) { |
314fba34 MC |
8516 | u32 gpio_mask; |
8517 | ||
9d26e213 MC |
8518 | gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 | |
8519 | GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
8520 | GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2; | |
3e7d83bc MC |
8521 | |
8522 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) | |
8523 | gpio_mask |= GRC_LCLCTRL_GPIO_OE3 | | |
8524 | GRC_LCLCTRL_GPIO_OUTPUT3; | |
8525 | ||
af36e6b6 MC |
8526 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) |
8527 | gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL; | |
8528 | ||
aaf84465 | 8529 | tp->grc_local_ctrl &= ~gpio_mask; |
314fba34 MC |
8530 | tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask; |
8531 | ||
8532 | /* GPIO1 must be driven high for eeprom write protect */ | |
63c3a66f | 8533 | if (tg3_flag(tp, EEPROM_WRITE_PROT)) |
9d26e213 MC |
8534 | tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | |
8535 | GRC_LCLCTRL_GPIO_OUTPUT1); | |
314fba34 | 8536 | } |
1da177e4 LT |
8537 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); |
8538 | udelay(100); | |
8539 | ||
63c3a66f | 8540 | if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1) { |
baf8a94a MC |
8541 | val = tr32(MSGINT_MODE); |
8542 | val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE; | |
8543 | tw32(MSGINT_MODE, val); | |
8544 | } | |
8545 | ||
63c3a66f | 8546 | if (!tg3_flag(tp, 5705_PLUS)) { |
1da177e4 LT |
8547 | tw32_f(DMAC_MODE, DMAC_MODE_ENABLE); |
8548 | udelay(40); | |
8549 | } | |
8550 | ||
8551 | val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB | | |
8552 | WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB | | |
8553 | WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB | | |
8554 | WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB | | |
8555 | WDMAC_MODE_LNGREAD_ENAB); | |
8556 | ||
c5908939 MC |
8557 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && |
8558 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { | |
63c3a66f | 8559 | if (tg3_flag(tp, TSO_CAPABLE) && |
1da177e4 LT |
8560 | (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 || |
8561 | tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) { | |
8562 | /* nothing */ | |
8563 | } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && | |
63c3a66f | 8564 | !tg3_flag(tp, IS_5788)) { |
1da177e4 LT |
8565 | val |= WDMAC_MODE_RX_ACCEL; |
8566 | } | |
8567 | } | |
8568 | ||
d9ab5ad1 | 8569 | /* Enable host coalescing bug fix */ |
63c3a66f | 8570 | if (tg3_flag(tp, 5755_PLUS)) |
f51f3562 | 8571 | val |= WDMAC_MODE_STATUS_TAG_FIX; |
d9ab5ad1 | 8572 | |
788a035e MC |
8573 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) |
8574 | val |= WDMAC_MODE_BURST_ALL_DATA; | |
8575 | ||
1da177e4 LT |
8576 | tw32_f(WDMAC_MODE, val); |
8577 | udelay(40); | |
8578 | ||
63c3a66f | 8579 | if (tg3_flag(tp, PCIX_MODE)) { |
9974a356 MC |
8580 | u16 pcix_cmd; |
8581 | ||
8582 | pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
8583 | &pcix_cmd); | |
1da177e4 | 8584 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) { |
9974a356 MC |
8585 | pcix_cmd &= ~PCI_X_CMD_MAX_READ; |
8586 | pcix_cmd |= PCI_X_CMD_READ_2K; | |
1da177e4 | 8587 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { |
9974a356 MC |
8588 | pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ); |
8589 | pcix_cmd |= PCI_X_CMD_READ_2K; | |
1da177e4 | 8590 | } |
9974a356 MC |
8591 | pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, |
8592 | pcix_cmd); | |
1da177e4 LT |
8593 | } |
8594 | ||
8595 | tw32_f(RDMAC_MODE, rdmac_mode); | |
8596 | udelay(40); | |
8597 | ||
8598 | tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE); | |
63c3a66f | 8599 | if (!tg3_flag(tp, 5705_PLUS)) |
1da177e4 | 8600 | tw32(MBFREE_MODE, MBFREE_MODE_ENABLE); |
9936bcf6 MC |
8601 | |
8602 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | |
8603 | tw32(SNDDATAC_MODE, | |
8604 | SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY); | |
8605 | else | |
8606 | tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE); | |
8607 | ||
1da177e4 LT |
8608 | tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE); |
8609 | tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB); | |
7cb32cf2 | 8610 | val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ; |
63c3a66f | 8611 | if (tg3_flag(tp, LRG_PROD_RING_CAP)) |
7cb32cf2 MC |
8612 | val |= RCVDBDI_MODE_LRG_RING_SZ; |
8613 | tw32(RCVDBDI_MODE, val); | |
1da177e4 | 8614 | tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE); |
63c3a66f JP |
8615 | if (tg3_flag(tp, HW_TSO_1) || |
8616 | tg3_flag(tp, HW_TSO_2) || | |
8617 | tg3_flag(tp, HW_TSO_3)) | |
1da177e4 | 8618 | tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8); |
baf8a94a | 8619 | val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE; |
63c3a66f | 8620 | if (tg3_flag(tp, ENABLE_TSS)) |
baf8a94a MC |
8621 | val |= SNDBDI_MODE_MULTI_TXQ_EN; |
8622 | tw32(SNDBDI_MODE, val); | |
1da177e4 LT |
8623 | tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE); |
8624 | ||
8625 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) { | |
8626 | err = tg3_load_5701_a0_firmware_fix(tp); | |
8627 | if (err) | |
8628 | return err; | |
8629 | } | |
8630 | ||
63c3a66f | 8631 | if (tg3_flag(tp, TSO_CAPABLE)) { |
1da177e4 LT |
8632 | err = tg3_load_tso_firmware(tp); |
8633 | if (err) | |
8634 | return err; | |
8635 | } | |
1da177e4 LT |
8636 | |
8637 | tp->tx_mode = TX_MODE_ENABLE; | |
f2096f94 | 8638 | |
63c3a66f | 8639 | if (tg3_flag(tp, 5755_PLUS) || |
b1d05210 MC |
8640 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
8641 | tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX; | |
f2096f94 MC |
8642 | |
8643 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
8644 | val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE; | |
8645 | tp->tx_mode &= ~val; | |
8646 | tp->tx_mode |= tr32(MAC_TX_MODE) & val; | |
8647 | } | |
8648 | ||
1da177e4 LT |
8649 | tw32_f(MAC_TX_MODE, tp->tx_mode); |
8650 | udelay(100); | |
8651 | ||
63c3a66f | 8652 | if (tg3_flag(tp, ENABLE_RSS)) { |
baf8a94a MC |
8653 | u32 reg = MAC_RSS_INDIR_TBL_0; |
8654 | u8 *ent = (u8 *)&val; | |
8655 | ||
8656 | /* Setup the indirection table */ | |
8657 | for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) { | |
8658 | int idx = i % sizeof(val); | |
8659 | ||
5efeeea1 | 8660 | ent[idx] = i % (tp->irq_cnt - 1); |
baf8a94a MC |
8661 | if (idx == sizeof(val) - 1) { |
8662 | tw32(reg, val); | |
8663 | reg += 4; | |
8664 | } | |
8665 | } | |
8666 | ||
8667 | /* Setup the "secret" hash key. */ | |
8668 | tw32(MAC_RSS_HASH_KEY_0, 0x5f865437); | |
8669 | tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc); | |
8670 | tw32(MAC_RSS_HASH_KEY_2, 0x50103a45); | |
8671 | tw32(MAC_RSS_HASH_KEY_3, 0x36621985); | |
8672 | tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8); | |
8673 | tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e); | |
8674 | tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556); | |
8675 | tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe); | |
8676 | tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7); | |
8677 | tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481); | |
8678 | } | |
8679 | ||
1da177e4 | 8680 | tp->rx_mode = RX_MODE_ENABLE; |
63c3a66f | 8681 | if (tg3_flag(tp, 5755_PLUS)) |
af36e6b6 MC |
8682 | tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE; |
8683 | ||
63c3a66f | 8684 | if (tg3_flag(tp, ENABLE_RSS)) |
baf8a94a MC |
8685 | tp->rx_mode |= RX_MODE_RSS_ENABLE | |
8686 | RX_MODE_RSS_ITBL_HASH_BITS_7 | | |
8687 | RX_MODE_RSS_IPV6_HASH_EN | | |
8688 | RX_MODE_RSS_TCP_IPV6_HASH_EN | | |
8689 | RX_MODE_RSS_IPV4_HASH_EN | | |
8690 | RX_MODE_RSS_TCP_IPV4_HASH_EN; | |
8691 | ||
1da177e4 LT |
8692 | tw32_f(MAC_RX_MODE, tp->rx_mode); |
8693 | udelay(10); | |
8694 | ||
1da177e4 LT |
8695 | tw32(MAC_LED_CTRL, tp->led_ctrl); |
8696 | ||
8697 | tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
f07e9af3 | 8698 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
1da177e4 LT |
8699 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); |
8700 | udelay(10); | |
8701 | } | |
8702 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
8703 | udelay(10); | |
8704 | ||
f07e9af3 | 8705 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
1da177e4 | 8706 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) && |
f07e9af3 | 8707 | !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) { |
1da177e4 LT |
8708 | /* Set drive transmission level to 1.2V */ |
8709 | /* only if the signal pre-emphasis bit is not set */ | |
8710 | val = tr32(MAC_SERDES_CFG); | |
8711 | val &= 0xfffff000; | |
8712 | val |= 0x880; | |
8713 | tw32(MAC_SERDES_CFG, val); | |
8714 | } | |
8715 | if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) | |
8716 | tw32(MAC_SERDES_CFG, 0x616000); | |
8717 | } | |
8718 | ||
8719 | /* Prevent chip from dropping frames when flow control | |
8720 | * is enabled. | |
8721 | */ | |
666bc831 MC |
8722 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) |
8723 | val = 1; | |
8724 | else | |
8725 | val = 2; | |
8726 | tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val); | |
1da177e4 LT |
8727 | |
8728 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 && | |
f07e9af3 | 8729 | (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { |
1da177e4 | 8730 | /* Use hardware link auto-negotiation */ |
63c3a66f | 8731 | tg3_flag_set(tp, HW_AUTONEG); |
1da177e4 LT |
8732 | } |
8733 | ||
f07e9af3 | 8734 | if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && |
6ff6f81d | 8735 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { |
d4d2c558 MC |
8736 | u32 tmp; |
8737 | ||
8738 | tmp = tr32(SERDES_RX_CTRL); | |
8739 | tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT); | |
8740 | tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT; | |
8741 | tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT; | |
8742 | tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl); | |
8743 | } | |
8744 | ||
63c3a66f | 8745 | if (!tg3_flag(tp, USE_PHYLIB)) { |
80096068 MC |
8746 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { |
8747 | tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; | |
dd477003 MC |
8748 | tp->link_config.speed = tp->link_config.orig_speed; |
8749 | tp->link_config.duplex = tp->link_config.orig_duplex; | |
8750 | tp->link_config.autoneg = tp->link_config.orig_autoneg; | |
8751 | } | |
1da177e4 | 8752 | |
dd477003 MC |
8753 | err = tg3_setup_phy(tp, 0); |
8754 | if (err) | |
8755 | return err; | |
1da177e4 | 8756 | |
f07e9af3 MC |
8757 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
8758 | !(tp->phy_flags & TG3_PHYFLG_IS_FET)) { | |
dd477003 MC |
8759 | u32 tmp; |
8760 | ||
8761 | /* Clear CRC stats. */ | |
8762 | if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) { | |
8763 | tg3_writephy(tp, MII_TG3_TEST1, | |
8764 | tmp | MII_TG3_TEST1_CRC_EN); | |
f08aa1a8 | 8765 | tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp); |
dd477003 | 8766 | } |
1da177e4 LT |
8767 | } |
8768 | } | |
8769 | ||
8770 | __tg3_set_rx_mode(tp->dev); | |
8771 | ||
8772 | /* Initialize receive rules. */ | |
8773 | tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK); | |
8774 | tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK); | |
8775 | tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK); | |
8776 | tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK); | |
8777 | ||
63c3a66f | 8778 | if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) |
1da177e4 LT |
8779 | limit = 8; |
8780 | else | |
8781 | limit = 16; | |
63c3a66f | 8782 | if (tg3_flag(tp, ENABLE_ASF)) |
1da177e4 LT |
8783 | limit -= 4; |
8784 | switch (limit) { | |
8785 | case 16: | |
8786 | tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0); | |
8787 | case 15: | |
8788 | tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0); | |
8789 | case 14: | |
8790 | tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0); | |
8791 | case 13: | |
8792 | tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0); | |
8793 | case 12: | |
8794 | tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0); | |
8795 | case 11: | |
8796 | tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0); | |
8797 | case 10: | |
8798 | tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0); | |
8799 | case 9: | |
8800 | tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0); | |
8801 | case 8: | |
8802 | tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0); | |
8803 | case 7: | |
8804 | tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0); | |
8805 | case 6: | |
8806 | tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0); | |
8807 | case 5: | |
8808 | tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0); | |
8809 | case 4: | |
8810 | /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */ | |
8811 | case 3: | |
8812 | /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */ | |
8813 | case 2: | |
8814 | case 1: | |
8815 | ||
8816 | default: | |
8817 | break; | |
855e1111 | 8818 | } |
1da177e4 | 8819 | |
63c3a66f | 8820 | if (tg3_flag(tp, ENABLE_APE)) |
9ce768ea MC |
8821 | /* Write our heartbeat update interval to APE. */ |
8822 | tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS, | |
8823 | APE_HOST_HEARTBEAT_INT_DISABLE); | |
0d3031d9 | 8824 | |
1da177e4 LT |
8825 | tg3_write_sig_post_reset(tp, RESET_KIND_INIT); |
8826 | ||
1da177e4 LT |
8827 | return 0; |
8828 | } | |
8829 | ||
8830 | /* Called at device open time to get the chip ready for | |
8831 | * packet processing. Invoked with tp->lock held. | |
8832 | */ | |
8e7a22e3 | 8833 | static int tg3_init_hw(struct tg3 *tp, int reset_phy) |
1da177e4 | 8834 | { |
1da177e4 LT |
8835 | tg3_switch_clocks(tp); |
8836 | ||
8837 | tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
8838 | ||
2f751b67 | 8839 | return tg3_reset_hw(tp, reset_phy); |
1da177e4 LT |
8840 | } |
8841 | ||
8842 | #define TG3_STAT_ADD32(PSTAT, REG) \ | |
8843 | do { u32 __val = tr32(REG); \ | |
8844 | (PSTAT)->low += __val; \ | |
8845 | if ((PSTAT)->low < __val) \ | |
8846 | (PSTAT)->high += 1; \ | |
8847 | } while (0) | |
8848 | ||
8849 | static void tg3_periodic_fetch_stats(struct tg3 *tp) | |
8850 | { | |
8851 | struct tg3_hw_stats *sp = tp->hw_stats; | |
8852 | ||
8853 | if (!netif_carrier_ok(tp->dev)) | |
8854 | return; | |
8855 | ||
8856 | TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS); | |
8857 | TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS); | |
8858 | TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT); | |
8859 | TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT); | |
8860 | TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS); | |
8861 | TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS); | |
8862 | TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS); | |
8863 | TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED); | |
8864 | TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL); | |
8865 | TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL); | |
8866 | TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST); | |
8867 | TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST); | |
8868 | TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST); | |
8869 | ||
8870 | TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS); | |
8871 | TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS); | |
8872 | TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST); | |
8873 | TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST); | |
8874 | TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST); | |
8875 | TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS); | |
8876 | TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS); | |
8877 | TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD); | |
8878 | TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD); | |
8879 | TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD); | |
8880 | TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED); | |
8881 | TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG); | |
8882 | TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS); | |
8883 | TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE); | |
463d305b MC |
8884 | |
8885 | TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT); | |
310050fa MC |
8886 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 && |
8887 | tp->pci_chip_rev_id != CHIPREV_ID_5719_A0 && | |
8888 | tp->pci_chip_rev_id != CHIPREV_ID_5720_A0) { | |
4d958473 MC |
8889 | TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT); |
8890 | } else { | |
8891 | u32 val = tr32(HOSTCC_FLOW_ATTN); | |
8892 | val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0; | |
8893 | if (val) { | |
8894 | tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM); | |
8895 | sp->rx_discards.low += val; | |
8896 | if (sp->rx_discards.low < val) | |
8897 | sp->rx_discards.high += 1; | |
8898 | } | |
8899 | sp->mbuf_lwm_thresh_hit = sp->rx_discards; | |
8900 | } | |
463d305b | 8901 | TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT); |
1da177e4 LT |
8902 | } |
8903 | ||
0e6cf6a9 MC |
8904 | static void tg3_chk_missed_msi(struct tg3 *tp) |
8905 | { | |
8906 | u32 i; | |
8907 | ||
8908 | for (i = 0; i < tp->irq_cnt; i++) { | |
8909 | struct tg3_napi *tnapi = &tp->napi[i]; | |
8910 | ||
8911 | if (tg3_has_work(tnapi)) { | |
8912 | if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr && | |
8913 | tnapi->last_tx_cons == tnapi->tx_cons) { | |
8914 | if (tnapi->chk_msi_cnt < 1) { | |
8915 | tnapi->chk_msi_cnt++; | |
8916 | return; | |
8917 | } | |
8918 | tw32_mailbox(tnapi->int_mbox, | |
8919 | tnapi->last_tag << 24); | |
8920 | } | |
8921 | } | |
8922 | tnapi->chk_msi_cnt = 0; | |
8923 | tnapi->last_rx_cons = tnapi->rx_rcb_ptr; | |
8924 | tnapi->last_tx_cons = tnapi->tx_cons; | |
8925 | } | |
8926 | } | |
8927 | ||
1da177e4 LT |
8928 | static void tg3_timer(unsigned long __opaque) |
8929 | { | |
8930 | struct tg3 *tp = (struct tg3 *) __opaque; | |
1da177e4 | 8931 | |
f475f163 MC |
8932 | if (tp->irq_sync) |
8933 | goto restart_timer; | |
8934 | ||
f47c11ee | 8935 | spin_lock(&tp->lock); |
1da177e4 | 8936 | |
0e6cf6a9 MC |
8937 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
8938 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
8939 | tg3_chk_missed_msi(tp); | |
8940 | ||
63c3a66f | 8941 | if (!tg3_flag(tp, TAGGED_STATUS)) { |
fac9b83e DM |
8942 | /* All of this garbage is because when using non-tagged |
8943 | * IRQ status the mailbox/status_block protocol the chip | |
8944 | * uses with the cpu is race prone. | |
8945 | */ | |
898a56f8 | 8946 | if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) { |
fac9b83e DM |
8947 | tw32(GRC_LOCAL_CTRL, |
8948 | tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); | |
8949 | } else { | |
8950 | tw32(HOSTCC_MODE, tp->coalesce_mode | | |
fd2ce37f | 8951 | HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW); |
fac9b83e | 8952 | } |
1da177e4 | 8953 | |
fac9b83e | 8954 | if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { |
63c3a66f | 8955 | tg3_flag_set(tp, RESTART_TIMER); |
f47c11ee | 8956 | spin_unlock(&tp->lock); |
fac9b83e DM |
8957 | schedule_work(&tp->reset_task); |
8958 | return; | |
8959 | } | |
1da177e4 LT |
8960 | } |
8961 | ||
1da177e4 LT |
8962 | /* This part only runs once per second. */ |
8963 | if (!--tp->timer_counter) { | |
63c3a66f | 8964 | if (tg3_flag(tp, 5705_PLUS)) |
fac9b83e DM |
8965 | tg3_periodic_fetch_stats(tp); |
8966 | ||
b0c5943f MC |
8967 | if (tp->setlpicnt && !--tp->setlpicnt) |
8968 | tg3_phy_eee_enable(tp); | |
52b02d04 | 8969 | |
63c3a66f | 8970 | if (tg3_flag(tp, USE_LINKCHG_REG)) { |
1da177e4 LT |
8971 | u32 mac_stat; |
8972 | int phy_event; | |
8973 | ||
8974 | mac_stat = tr32(MAC_STATUS); | |
8975 | ||
8976 | phy_event = 0; | |
f07e9af3 | 8977 | if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) { |
1da177e4 LT |
8978 | if (mac_stat & MAC_STATUS_MI_INTERRUPT) |
8979 | phy_event = 1; | |
8980 | } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED) | |
8981 | phy_event = 1; | |
8982 | ||
8983 | if (phy_event) | |
8984 | tg3_setup_phy(tp, 0); | |
63c3a66f | 8985 | } else if (tg3_flag(tp, POLL_SERDES)) { |
1da177e4 LT |
8986 | u32 mac_stat = tr32(MAC_STATUS); |
8987 | int need_setup = 0; | |
8988 | ||
8989 | if (netif_carrier_ok(tp->dev) && | |
8990 | (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) { | |
8991 | need_setup = 1; | |
8992 | } | |
be98da6a | 8993 | if (!netif_carrier_ok(tp->dev) && |
1da177e4 LT |
8994 | (mac_stat & (MAC_STATUS_PCS_SYNCED | |
8995 | MAC_STATUS_SIGNAL_DET))) { | |
8996 | need_setup = 1; | |
8997 | } | |
8998 | if (need_setup) { | |
3d3ebe74 MC |
8999 | if (!tp->serdes_counter) { |
9000 | tw32_f(MAC_MODE, | |
9001 | (tp->mac_mode & | |
9002 | ~MAC_MODE_PORT_MODE_MASK)); | |
9003 | udelay(40); | |
9004 | tw32_f(MAC_MODE, tp->mac_mode); | |
9005 | udelay(40); | |
9006 | } | |
1da177e4 LT |
9007 | tg3_setup_phy(tp, 0); |
9008 | } | |
f07e9af3 | 9009 | } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && |
63c3a66f | 9010 | tg3_flag(tp, 5780_CLASS)) { |
747e8f8b | 9011 | tg3_serdes_parallel_detect(tp); |
57d8b880 | 9012 | } |
1da177e4 LT |
9013 | |
9014 | tp->timer_counter = tp->timer_multiplier; | |
9015 | } | |
9016 | ||
130b8e4d MC |
9017 | /* Heartbeat is only sent once every 2 seconds. |
9018 | * | |
9019 | * The heartbeat is to tell the ASF firmware that the host | |
9020 | * driver is still alive. In the event that the OS crashes, | |
9021 | * ASF needs to reset the hardware to free up the FIFO space | |
9022 | * that may be filled with rx packets destined for the host. | |
9023 | * If the FIFO is full, ASF will no longer function properly. | |
9024 | * | |
9025 | * Unintended resets have been reported on real time kernels | |
9026 | * where the timer doesn't run on time. Netpoll will also have | |
9027 | * same problem. | |
9028 | * | |
9029 | * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware | |
9030 | * to check the ring condition when the heartbeat is expiring | |
9031 | * before doing the reset. This will prevent most unintended | |
9032 | * resets. | |
9033 | */ | |
1da177e4 | 9034 | if (!--tp->asf_counter) { |
63c3a66f | 9035 | if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) { |
7c5026aa MC |
9036 | tg3_wait_for_event_ack(tp); |
9037 | ||
bbadf503 | 9038 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, |
130b8e4d | 9039 | FWCMD_NICDRV_ALIVE3); |
bbadf503 | 9040 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4); |
c6cdf436 MC |
9041 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, |
9042 | TG3_FW_UPDATE_TIMEOUT_SEC); | |
4ba526ce MC |
9043 | |
9044 | tg3_generate_fw_event(tp); | |
1da177e4 LT |
9045 | } |
9046 | tp->asf_counter = tp->asf_multiplier; | |
9047 | } | |
9048 | ||
f47c11ee | 9049 | spin_unlock(&tp->lock); |
1da177e4 | 9050 | |
f475f163 | 9051 | restart_timer: |
1da177e4 LT |
9052 | tp->timer.expires = jiffies + tp->timer_offset; |
9053 | add_timer(&tp->timer); | |
9054 | } | |
9055 | ||
4f125f42 | 9056 | static int tg3_request_irq(struct tg3 *tp, int irq_num) |
fcfa0a32 | 9057 | { |
7d12e780 | 9058 | irq_handler_t fn; |
fcfa0a32 | 9059 | unsigned long flags; |
4f125f42 MC |
9060 | char *name; |
9061 | struct tg3_napi *tnapi = &tp->napi[irq_num]; | |
9062 | ||
9063 | if (tp->irq_cnt == 1) | |
9064 | name = tp->dev->name; | |
9065 | else { | |
9066 | name = &tnapi->irq_lbl[0]; | |
9067 | snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num); | |
9068 | name[IFNAMSIZ-1] = 0; | |
9069 | } | |
fcfa0a32 | 9070 | |
63c3a66f | 9071 | if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) { |
fcfa0a32 | 9072 | fn = tg3_msi; |
63c3a66f | 9073 | if (tg3_flag(tp, 1SHOT_MSI)) |
fcfa0a32 | 9074 | fn = tg3_msi_1shot; |
ab392d2d | 9075 | flags = 0; |
fcfa0a32 MC |
9076 | } else { |
9077 | fn = tg3_interrupt; | |
63c3a66f | 9078 | if (tg3_flag(tp, TAGGED_STATUS)) |
fcfa0a32 | 9079 | fn = tg3_interrupt_tagged; |
ab392d2d | 9080 | flags = IRQF_SHARED; |
fcfa0a32 | 9081 | } |
4f125f42 MC |
9082 | |
9083 | return request_irq(tnapi->irq_vec, fn, flags, name, tnapi); | |
fcfa0a32 MC |
9084 | } |
9085 | ||
7938109f MC |
9086 | static int tg3_test_interrupt(struct tg3 *tp) |
9087 | { | |
09943a18 | 9088 | struct tg3_napi *tnapi = &tp->napi[0]; |
7938109f | 9089 | struct net_device *dev = tp->dev; |
b16250e3 | 9090 | int err, i, intr_ok = 0; |
f6eb9b1f | 9091 | u32 val; |
7938109f | 9092 | |
d4bc3927 MC |
9093 | if (!netif_running(dev)) |
9094 | return -ENODEV; | |
9095 | ||
7938109f MC |
9096 | tg3_disable_ints(tp); |
9097 | ||
4f125f42 | 9098 | free_irq(tnapi->irq_vec, tnapi); |
7938109f | 9099 | |
f6eb9b1f MC |
9100 | /* |
9101 | * Turn off MSI one shot mode. Otherwise this test has no | |
9102 | * observable way to know whether the interrupt was delivered. | |
9103 | */ | |
63c3a66f | 9104 | if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) { |
f6eb9b1f MC |
9105 | val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE; |
9106 | tw32(MSGINT_MODE, val); | |
9107 | } | |
9108 | ||
4f125f42 | 9109 | err = request_irq(tnapi->irq_vec, tg3_test_isr, |
09943a18 | 9110 | IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi); |
7938109f MC |
9111 | if (err) |
9112 | return err; | |
9113 | ||
898a56f8 | 9114 | tnapi->hw_status->status &= ~SD_STATUS_UPDATED; |
7938109f MC |
9115 | tg3_enable_ints(tp); |
9116 | ||
9117 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | | |
fd2ce37f | 9118 | tnapi->coal_now); |
7938109f MC |
9119 | |
9120 | for (i = 0; i < 5; i++) { | |
b16250e3 MC |
9121 | u32 int_mbox, misc_host_ctrl; |
9122 | ||
898a56f8 | 9123 | int_mbox = tr32_mailbox(tnapi->int_mbox); |
b16250e3 MC |
9124 | misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL); |
9125 | ||
9126 | if ((int_mbox != 0) || | |
9127 | (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) { | |
9128 | intr_ok = 1; | |
7938109f | 9129 | break; |
b16250e3 MC |
9130 | } |
9131 | ||
7938109f MC |
9132 | msleep(10); |
9133 | } | |
9134 | ||
9135 | tg3_disable_ints(tp); | |
9136 | ||
4f125f42 | 9137 | free_irq(tnapi->irq_vec, tnapi); |
6aa20a22 | 9138 | |
4f125f42 | 9139 | err = tg3_request_irq(tp, 0); |
7938109f MC |
9140 | |
9141 | if (err) | |
9142 | return err; | |
9143 | ||
f6eb9b1f MC |
9144 | if (intr_ok) { |
9145 | /* Reenable MSI one shot mode. */ | |
63c3a66f | 9146 | if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) { |
f6eb9b1f MC |
9147 | val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE; |
9148 | tw32(MSGINT_MODE, val); | |
9149 | } | |
7938109f | 9150 | return 0; |
f6eb9b1f | 9151 | } |
7938109f MC |
9152 | |
9153 | return -EIO; | |
9154 | } | |
9155 | ||
9156 | /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is | |
9157 | * successfully restored | |
9158 | */ | |
9159 | static int tg3_test_msi(struct tg3 *tp) | |
9160 | { | |
7938109f MC |
9161 | int err; |
9162 | u16 pci_cmd; | |
9163 | ||
63c3a66f | 9164 | if (!tg3_flag(tp, USING_MSI)) |
7938109f MC |
9165 | return 0; |
9166 | ||
9167 | /* Turn off SERR reporting in case MSI terminates with Master | |
9168 | * Abort. | |
9169 | */ | |
9170 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
9171 | pci_write_config_word(tp->pdev, PCI_COMMAND, | |
9172 | pci_cmd & ~PCI_COMMAND_SERR); | |
9173 | ||
9174 | err = tg3_test_interrupt(tp); | |
9175 | ||
9176 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
9177 | ||
9178 | if (!err) | |
9179 | return 0; | |
9180 | ||
9181 | /* other failures */ | |
9182 | if (err != -EIO) | |
9183 | return err; | |
9184 | ||
9185 | /* MSI test failed, go back to INTx mode */ | |
5129c3a3 MC |
9186 | netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching " |
9187 | "to INTx mode. Please report this failure to the PCI " | |
9188 | "maintainer and include system chipset information\n"); | |
7938109f | 9189 | |
4f125f42 | 9190 | free_irq(tp->napi[0].irq_vec, &tp->napi[0]); |
09943a18 | 9191 | |
7938109f MC |
9192 | pci_disable_msi(tp->pdev); |
9193 | ||
63c3a66f | 9194 | tg3_flag_clear(tp, USING_MSI); |
dc8bf1b1 | 9195 | tp->napi[0].irq_vec = tp->pdev->irq; |
7938109f | 9196 | |
4f125f42 | 9197 | err = tg3_request_irq(tp, 0); |
7938109f MC |
9198 | if (err) |
9199 | return err; | |
9200 | ||
9201 | /* Need to reset the chip because the MSI cycle may have terminated | |
9202 | * with Master Abort. | |
9203 | */ | |
f47c11ee | 9204 | tg3_full_lock(tp, 1); |
7938109f | 9205 | |
944d980e | 9206 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
8e7a22e3 | 9207 | err = tg3_init_hw(tp, 1); |
7938109f | 9208 | |
f47c11ee | 9209 | tg3_full_unlock(tp); |
7938109f MC |
9210 | |
9211 | if (err) | |
4f125f42 | 9212 | free_irq(tp->napi[0].irq_vec, &tp->napi[0]); |
7938109f MC |
9213 | |
9214 | return err; | |
9215 | } | |
9216 | ||
9e9fd12d MC |
9217 | static int tg3_request_firmware(struct tg3 *tp) |
9218 | { | |
9219 | const __be32 *fw_data; | |
9220 | ||
9221 | if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) { | |
05dbe005 JP |
9222 | netdev_err(tp->dev, "Failed to load firmware \"%s\"\n", |
9223 | tp->fw_needed); | |
9e9fd12d MC |
9224 | return -ENOENT; |
9225 | } | |
9226 | ||
9227 | fw_data = (void *)tp->fw->data; | |
9228 | ||
9229 | /* Firmware blob starts with version numbers, followed by | |
9230 | * start address and _full_ length including BSS sections | |
9231 | * (which must be longer than the actual data, of course | |
9232 | */ | |
9233 | ||
9234 | tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */ | |
9235 | if (tp->fw_len < (tp->fw->size - 12)) { | |
05dbe005 JP |
9236 | netdev_err(tp->dev, "bogus length %d in \"%s\"\n", |
9237 | tp->fw_len, tp->fw_needed); | |
9e9fd12d MC |
9238 | release_firmware(tp->fw); |
9239 | tp->fw = NULL; | |
9240 | return -EINVAL; | |
9241 | } | |
9242 | ||
9243 | /* We no longer need firmware; we have it. */ | |
9244 | tp->fw_needed = NULL; | |
9245 | return 0; | |
9246 | } | |
9247 | ||
679563f4 MC |
9248 | static bool tg3_enable_msix(struct tg3 *tp) |
9249 | { | |
9250 | int i, rc, cpus = num_online_cpus(); | |
9251 | struct msix_entry msix_ent[tp->irq_max]; | |
9252 | ||
9253 | if (cpus == 1) | |
9254 | /* Just fallback to the simpler MSI mode. */ | |
9255 | return false; | |
9256 | ||
9257 | /* | |
9258 | * We want as many rx rings enabled as there are cpus. | |
9259 | * The first MSIX vector only deals with link interrupts, etc, | |
9260 | * so we add one to the number of vectors we are requesting. | |
9261 | */ | |
9262 | tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max); | |
9263 | ||
9264 | for (i = 0; i < tp->irq_max; i++) { | |
9265 | msix_ent[i].entry = i; | |
9266 | msix_ent[i].vector = 0; | |
9267 | } | |
9268 | ||
9269 | rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt); | |
2430b031 MC |
9270 | if (rc < 0) { |
9271 | return false; | |
9272 | } else if (rc != 0) { | |
679563f4 MC |
9273 | if (pci_enable_msix(tp->pdev, msix_ent, rc)) |
9274 | return false; | |
05dbe005 JP |
9275 | netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n", |
9276 | tp->irq_cnt, rc); | |
679563f4 MC |
9277 | tp->irq_cnt = rc; |
9278 | } | |
9279 | ||
9280 | for (i = 0; i < tp->irq_max; i++) | |
9281 | tp->napi[i].irq_vec = msix_ent[i].vector; | |
9282 | ||
2ddaad39 BH |
9283 | netif_set_real_num_tx_queues(tp->dev, 1); |
9284 | rc = tp->irq_cnt > 1 ? tp->irq_cnt - 1 : 1; | |
9285 | if (netif_set_real_num_rx_queues(tp->dev, rc)) { | |
9286 | pci_disable_msix(tp->pdev); | |
9287 | return false; | |
9288 | } | |
b92b9040 MC |
9289 | |
9290 | if (tp->irq_cnt > 1) { | |
63c3a66f | 9291 | tg3_flag_set(tp, ENABLE_RSS); |
d78b59f5 MC |
9292 | |
9293 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
9294 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
63c3a66f | 9295 | tg3_flag_set(tp, ENABLE_TSS); |
b92b9040 MC |
9296 | netif_set_real_num_tx_queues(tp->dev, tp->irq_cnt - 1); |
9297 | } | |
9298 | } | |
2430b031 | 9299 | |
679563f4 MC |
9300 | return true; |
9301 | } | |
9302 | ||
07b0173c MC |
9303 | static void tg3_ints_init(struct tg3 *tp) |
9304 | { | |
63c3a66f JP |
9305 | if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) && |
9306 | !tg3_flag(tp, TAGGED_STATUS)) { | |
07b0173c MC |
9307 | /* All MSI supporting chips should support tagged |
9308 | * status. Assert that this is the case. | |
9309 | */ | |
5129c3a3 MC |
9310 | netdev_warn(tp->dev, |
9311 | "MSI without TAGGED_STATUS? Not using MSI\n"); | |
679563f4 | 9312 | goto defcfg; |
07b0173c | 9313 | } |
4f125f42 | 9314 | |
63c3a66f JP |
9315 | if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp)) |
9316 | tg3_flag_set(tp, USING_MSIX); | |
9317 | else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0) | |
9318 | tg3_flag_set(tp, USING_MSI); | |
679563f4 | 9319 | |
63c3a66f | 9320 | if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) { |
679563f4 | 9321 | u32 msi_mode = tr32(MSGINT_MODE); |
63c3a66f | 9322 | if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1) |
baf8a94a | 9323 | msi_mode |= MSGINT_MODE_MULTIVEC_EN; |
679563f4 MC |
9324 | tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE); |
9325 | } | |
9326 | defcfg: | |
63c3a66f | 9327 | if (!tg3_flag(tp, USING_MSIX)) { |
679563f4 MC |
9328 | tp->irq_cnt = 1; |
9329 | tp->napi[0].irq_vec = tp->pdev->irq; | |
2ddaad39 | 9330 | netif_set_real_num_tx_queues(tp->dev, 1); |
85407885 | 9331 | netif_set_real_num_rx_queues(tp->dev, 1); |
679563f4 | 9332 | } |
07b0173c MC |
9333 | } |
9334 | ||
9335 | static void tg3_ints_fini(struct tg3 *tp) | |
9336 | { | |
63c3a66f | 9337 | if (tg3_flag(tp, USING_MSIX)) |
679563f4 | 9338 | pci_disable_msix(tp->pdev); |
63c3a66f | 9339 | else if (tg3_flag(tp, USING_MSI)) |
679563f4 | 9340 | pci_disable_msi(tp->pdev); |
63c3a66f JP |
9341 | tg3_flag_clear(tp, USING_MSI); |
9342 | tg3_flag_clear(tp, USING_MSIX); | |
9343 | tg3_flag_clear(tp, ENABLE_RSS); | |
9344 | tg3_flag_clear(tp, ENABLE_TSS); | |
07b0173c MC |
9345 | } |
9346 | ||
1da177e4 LT |
9347 | static int tg3_open(struct net_device *dev) |
9348 | { | |
9349 | struct tg3 *tp = netdev_priv(dev); | |
4f125f42 | 9350 | int i, err; |
1da177e4 | 9351 | |
9e9fd12d MC |
9352 | if (tp->fw_needed) { |
9353 | err = tg3_request_firmware(tp); | |
9354 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) { | |
9355 | if (err) | |
9356 | return err; | |
9357 | } else if (err) { | |
05dbe005 | 9358 | netdev_warn(tp->dev, "TSO capability disabled\n"); |
63c3a66f JP |
9359 | tg3_flag_clear(tp, TSO_CAPABLE); |
9360 | } else if (!tg3_flag(tp, TSO_CAPABLE)) { | |
05dbe005 | 9361 | netdev_notice(tp->dev, "TSO capability restored\n"); |
63c3a66f | 9362 | tg3_flag_set(tp, TSO_CAPABLE); |
9e9fd12d MC |
9363 | } |
9364 | } | |
9365 | ||
c49a1561 MC |
9366 | netif_carrier_off(tp->dev); |
9367 | ||
c866b7ea | 9368 | err = tg3_power_up(tp); |
2f751b67 | 9369 | if (err) |
bc1c7567 | 9370 | return err; |
2f751b67 MC |
9371 | |
9372 | tg3_full_lock(tp, 0); | |
bc1c7567 | 9373 | |
1da177e4 | 9374 | tg3_disable_ints(tp); |
63c3a66f | 9375 | tg3_flag_clear(tp, INIT_COMPLETE); |
1da177e4 | 9376 | |
f47c11ee | 9377 | tg3_full_unlock(tp); |
1da177e4 | 9378 | |
679563f4 MC |
9379 | /* |
9380 | * Setup interrupts first so we know how | |
9381 | * many NAPI resources to allocate | |
9382 | */ | |
9383 | tg3_ints_init(tp); | |
9384 | ||
1da177e4 LT |
9385 | /* The placement of this call is tied |
9386 | * to the setup and use of Host TX descriptors. | |
9387 | */ | |
9388 | err = tg3_alloc_consistent(tp); | |
9389 | if (err) | |
679563f4 | 9390 | goto err_out1; |
88b06bc2 | 9391 | |
66cfd1bd MC |
9392 | tg3_napi_init(tp); |
9393 | ||
fed97810 | 9394 | tg3_napi_enable(tp); |
1da177e4 | 9395 | |
4f125f42 MC |
9396 | for (i = 0; i < tp->irq_cnt; i++) { |
9397 | struct tg3_napi *tnapi = &tp->napi[i]; | |
9398 | err = tg3_request_irq(tp, i); | |
9399 | if (err) { | |
9400 | for (i--; i >= 0; i--) | |
9401 | free_irq(tnapi->irq_vec, tnapi); | |
9402 | break; | |
9403 | } | |
9404 | } | |
1da177e4 | 9405 | |
07b0173c | 9406 | if (err) |
679563f4 | 9407 | goto err_out2; |
bea3348e | 9408 | |
f47c11ee | 9409 | tg3_full_lock(tp, 0); |
1da177e4 | 9410 | |
8e7a22e3 | 9411 | err = tg3_init_hw(tp, 1); |
1da177e4 | 9412 | if (err) { |
944d980e | 9413 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 LT |
9414 | tg3_free_rings(tp); |
9415 | } else { | |
0e6cf6a9 MC |
9416 | if (tg3_flag(tp, TAGGED_STATUS) && |
9417 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 && | |
9418 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) | |
fac9b83e DM |
9419 | tp->timer_offset = HZ; |
9420 | else | |
9421 | tp->timer_offset = HZ / 10; | |
9422 | ||
9423 | BUG_ON(tp->timer_offset > HZ); | |
9424 | tp->timer_counter = tp->timer_multiplier = | |
9425 | (HZ / tp->timer_offset); | |
9426 | tp->asf_counter = tp->asf_multiplier = | |
28fbef78 | 9427 | ((HZ / tp->timer_offset) * 2); |
1da177e4 LT |
9428 | |
9429 | init_timer(&tp->timer); | |
9430 | tp->timer.expires = jiffies + tp->timer_offset; | |
9431 | tp->timer.data = (unsigned long) tp; | |
9432 | tp->timer.function = tg3_timer; | |
1da177e4 LT |
9433 | } |
9434 | ||
f47c11ee | 9435 | tg3_full_unlock(tp); |
1da177e4 | 9436 | |
07b0173c | 9437 | if (err) |
679563f4 | 9438 | goto err_out3; |
1da177e4 | 9439 | |
63c3a66f | 9440 | if (tg3_flag(tp, USING_MSI)) { |
7938109f | 9441 | err = tg3_test_msi(tp); |
fac9b83e | 9442 | |
7938109f | 9443 | if (err) { |
f47c11ee | 9444 | tg3_full_lock(tp, 0); |
944d980e | 9445 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
7938109f | 9446 | tg3_free_rings(tp); |
f47c11ee | 9447 | tg3_full_unlock(tp); |
7938109f | 9448 | |
679563f4 | 9449 | goto err_out2; |
7938109f | 9450 | } |
fcfa0a32 | 9451 | |
63c3a66f | 9452 | if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) { |
f6eb9b1f | 9453 | u32 val = tr32(PCIE_TRANSACTION_CFG); |
fcfa0a32 | 9454 | |
f6eb9b1f MC |
9455 | tw32(PCIE_TRANSACTION_CFG, |
9456 | val | PCIE_TRANS_CFG_1SHOT_MSI); | |
fcfa0a32 | 9457 | } |
7938109f MC |
9458 | } |
9459 | ||
b02fd9e3 MC |
9460 | tg3_phy_start(tp); |
9461 | ||
f47c11ee | 9462 | tg3_full_lock(tp, 0); |
1da177e4 | 9463 | |
7938109f | 9464 | add_timer(&tp->timer); |
63c3a66f | 9465 | tg3_flag_set(tp, INIT_COMPLETE); |
1da177e4 LT |
9466 | tg3_enable_ints(tp); |
9467 | ||
f47c11ee | 9468 | tg3_full_unlock(tp); |
1da177e4 | 9469 | |
fe5f5787 | 9470 | netif_tx_start_all_queues(dev); |
1da177e4 | 9471 | |
06c03c02 MB |
9472 | /* |
9473 | * Reset loopback feature if it was turned on while the device was down | |
9474 | * make sure that it's installed properly now. | |
9475 | */ | |
9476 | if (dev->features & NETIF_F_LOOPBACK) | |
9477 | tg3_set_loopback(dev, dev->features); | |
9478 | ||
1da177e4 | 9479 | return 0; |
07b0173c | 9480 | |
679563f4 | 9481 | err_out3: |
4f125f42 MC |
9482 | for (i = tp->irq_cnt - 1; i >= 0; i--) { |
9483 | struct tg3_napi *tnapi = &tp->napi[i]; | |
9484 | free_irq(tnapi->irq_vec, tnapi); | |
9485 | } | |
07b0173c | 9486 | |
679563f4 | 9487 | err_out2: |
fed97810 | 9488 | tg3_napi_disable(tp); |
66cfd1bd | 9489 | tg3_napi_fini(tp); |
07b0173c | 9490 | tg3_free_consistent(tp); |
679563f4 MC |
9491 | |
9492 | err_out1: | |
9493 | tg3_ints_fini(tp); | |
07b0173c | 9494 | return err; |
1da177e4 LT |
9495 | } |
9496 | ||
511d2224 ED |
9497 | static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *, |
9498 | struct rtnl_link_stats64 *); | |
1da177e4 LT |
9499 | static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *); |
9500 | ||
9501 | static int tg3_close(struct net_device *dev) | |
9502 | { | |
4f125f42 | 9503 | int i; |
1da177e4 LT |
9504 | struct tg3 *tp = netdev_priv(dev); |
9505 | ||
fed97810 | 9506 | tg3_napi_disable(tp); |
28e53bdd | 9507 | cancel_work_sync(&tp->reset_task); |
7faa006f | 9508 | |
fe5f5787 | 9509 | netif_tx_stop_all_queues(dev); |
1da177e4 LT |
9510 | |
9511 | del_timer_sync(&tp->timer); | |
9512 | ||
24bb4fb6 MC |
9513 | tg3_phy_stop(tp); |
9514 | ||
f47c11ee | 9515 | tg3_full_lock(tp, 1); |
1da177e4 LT |
9516 | |
9517 | tg3_disable_ints(tp); | |
9518 | ||
944d980e | 9519 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 | 9520 | tg3_free_rings(tp); |
63c3a66f | 9521 | tg3_flag_clear(tp, INIT_COMPLETE); |
1da177e4 | 9522 | |
f47c11ee | 9523 | tg3_full_unlock(tp); |
1da177e4 | 9524 | |
4f125f42 MC |
9525 | for (i = tp->irq_cnt - 1; i >= 0; i--) { |
9526 | struct tg3_napi *tnapi = &tp->napi[i]; | |
9527 | free_irq(tnapi->irq_vec, tnapi); | |
9528 | } | |
07b0173c MC |
9529 | |
9530 | tg3_ints_fini(tp); | |
1da177e4 | 9531 | |
511d2224 ED |
9532 | tg3_get_stats64(tp->dev, &tp->net_stats_prev); |
9533 | ||
1da177e4 LT |
9534 | memcpy(&tp->estats_prev, tg3_get_estats(tp), |
9535 | sizeof(tp->estats_prev)); | |
9536 | ||
66cfd1bd MC |
9537 | tg3_napi_fini(tp); |
9538 | ||
1da177e4 LT |
9539 | tg3_free_consistent(tp); |
9540 | ||
c866b7ea | 9541 | tg3_power_down(tp); |
bc1c7567 MC |
9542 | |
9543 | netif_carrier_off(tp->dev); | |
9544 | ||
1da177e4 LT |
9545 | return 0; |
9546 | } | |
9547 | ||
511d2224 | 9548 | static inline u64 get_stat64(tg3_stat64_t *val) |
816f8b86 SB |
9549 | { |
9550 | return ((u64)val->high << 32) | ((u64)val->low); | |
9551 | } | |
9552 | ||
511d2224 | 9553 | static u64 calc_crc_errors(struct tg3 *tp) |
1da177e4 LT |
9554 | { |
9555 | struct tg3_hw_stats *hw_stats = tp->hw_stats; | |
9556 | ||
f07e9af3 | 9557 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
1da177e4 LT |
9558 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
9559 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) { | |
1da177e4 LT |
9560 | u32 val; |
9561 | ||
f47c11ee | 9562 | spin_lock_bh(&tp->lock); |
569a5df8 MC |
9563 | if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) { |
9564 | tg3_writephy(tp, MII_TG3_TEST1, | |
9565 | val | MII_TG3_TEST1_CRC_EN); | |
f08aa1a8 | 9566 | tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val); |
1da177e4 LT |
9567 | } else |
9568 | val = 0; | |
f47c11ee | 9569 | spin_unlock_bh(&tp->lock); |
1da177e4 LT |
9570 | |
9571 | tp->phy_crc_errors += val; | |
9572 | ||
9573 | return tp->phy_crc_errors; | |
9574 | } | |
9575 | ||
9576 | return get_stat64(&hw_stats->rx_fcs_errors); | |
9577 | } | |
9578 | ||
9579 | #define ESTAT_ADD(member) \ | |
9580 | estats->member = old_estats->member + \ | |
511d2224 | 9581 | get_stat64(&hw_stats->member) |
1da177e4 LT |
9582 | |
9583 | static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp) | |
9584 | { | |
9585 | struct tg3_ethtool_stats *estats = &tp->estats; | |
9586 | struct tg3_ethtool_stats *old_estats = &tp->estats_prev; | |
9587 | struct tg3_hw_stats *hw_stats = tp->hw_stats; | |
9588 | ||
9589 | if (!hw_stats) | |
9590 | return old_estats; | |
9591 | ||
9592 | ESTAT_ADD(rx_octets); | |
9593 | ESTAT_ADD(rx_fragments); | |
9594 | ESTAT_ADD(rx_ucast_packets); | |
9595 | ESTAT_ADD(rx_mcast_packets); | |
9596 | ESTAT_ADD(rx_bcast_packets); | |
9597 | ESTAT_ADD(rx_fcs_errors); | |
9598 | ESTAT_ADD(rx_align_errors); | |
9599 | ESTAT_ADD(rx_xon_pause_rcvd); | |
9600 | ESTAT_ADD(rx_xoff_pause_rcvd); | |
9601 | ESTAT_ADD(rx_mac_ctrl_rcvd); | |
9602 | ESTAT_ADD(rx_xoff_entered); | |
9603 | ESTAT_ADD(rx_frame_too_long_errors); | |
9604 | ESTAT_ADD(rx_jabbers); | |
9605 | ESTAT_ADD(rx_undersize_packets); | |
9606 | ESTAT_ADD(rx_in_length_errors); | |
9607 | ESTAT_ADD(rx_out_length_errors); | |
9608 | ESTAT_ADD(rx_64_or_less_octet_packets); | |
9609 | ESTAT_ADD(rx_65_to_127_octet_packets); | |
9610 | ESTAT_ADD(rx_128_to_255_octet_packets); | |
9611 | ESTAT_ADD(rx_256_to_511_octet_packets); | |
9612 | ESTAT_ADD(rx_512_to_1023_octet_packets); | |
9613 | ESTAT_ADD(rx_1024_to_1522_octet_packets); | |
9614 | ESTAT_ADD(rx_1523_to_2047_octet_packets); | |
9615 | ESTAT_ADD(rx_2048_to_4095_octet_packets); | |
9616 | ESTAT_ADD(rx_4096_to_8191_octet_packets); | |
9617 | ESTAT_ADD(rx_8192_to_9022_octet_packets); | |
9618 | ||
9619 | ESTAT_ADD(tx_octets); | |
9620 | ESTAT_ADD(tx_collisions); | |
9621 | ESTAT_ADD(tx_xon_sent); | |
9622 | ESTAT_ADD(tx_xoff_sent); | |
9623 | ESTAT_ADD(tx_flow_control); | |
9624 | ESTAT_ADD(tx_mac_errors); | |
9625 | ESTAT_ADD(tx_single_collisions); | |
9626 | ESTAT_ADD(tx_mult_collisions); | |
9627 | ESTAT_ADD(tx_deferred); | |
9628 | ESTAT_ADD(tx_excessive_collisions); | |
9629 | ESTAT_ADD(tx_late_collisions); | |
9630 | ESTAT_ADD(tx_collide_2times); | |
9631 | ESTAT_ADD(tx_collide_3times); | |
9632 | ESTAT_ADD(tx_collide_4times); | |
9633 | ESTAT_ADD(tx_collide_5times); | |
9634 | ESTAT_ADD(tx_collide_6times); | |
9635 | ESTAT_ADD(tx_collide_7times); | |
9636 | ESTAT_ADD(tx_collide_8times); | |
9637 | ESTAT_ADD(tx_collide_9times); | |
9638 | ESTAT_ADD(tx_collide_10times); | |
9639 | ESTAT_ADD(tx_collide_11times); | |
9640 | ESTAT_ADD(tx_collide_12times); | |
9641 | ESTAT_ADD(tx_collide_13times); | |
9642 | ESTAT_ADD(tx_collide_14times); | |
9643 | ESTAT_ADD(tx_collide_15times); | |
9644 | ESTAT_ADD(tx_ucast_packets); | |
9645 | ESTAT_ADD(tx_mcast_packets); | |
9646 | ESTAT_ADD(tx_bcast_packets); | |
9647 | ESTAT_ADD(tx_carrier_sense_errors); | |
9648 | ESTAT_ADD(tx_discards); | |
9649 | ESTAT_ADD(tx_errors); | |
9650 | ||
9651 | ESTAT_ADD(dma_writeq_full); | |
9652 | ESTAT_ADD(dma_write_prioq_full); | |
9653 | ESTAT_ADD(rxbds_empty); | |
9654 | ESTAT_ADD(rx_discards); | |
9655 | ESTAT_ADD(rx_errors); | |
9656 | ESTAT_ADD(rx_threshold_hit); | |
9657 | ||
9658 | ESTAT_ADD(dma_readq_full); | |
9659 | ESTAT_ADD(dma_read_prioq_full); | |
9660 | ESTAT_ADD(tx_comp_queue_full); | |
9661 | ||
9662 | ESTAT_ADD(ring_set_send_prod_index); | |
9663 | ESTAT_ADD(ring_status_update); | |
9664 | ESTAT_ADD(nic_irqs); | |
9665 | ESTAT_ADD(nic_avoided_irqs); | |
9666 | ESTAT_ADD(nic_tx_threshold_hit); | |
9667 | ||
4452d099 MC |
9668 | ESTAT_ADD(mbuf_lwm_thresh_hit); |
9669 | ||
1da177e4 LT |
9670 | return estats; |
9671 | } | |
9672 | ||
511d2224 ED |
9673 | static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev, |
9674 | struct rtnl_link_stats64 *stats) | |
1da177e4 LT |
9675 | { |
9676 | struct tg3 *tp = netdev_priv(dev); | |
511d2224 | 9677 | struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev; |
1da177e4 LT |
9678 | struct tg3_hw_stats *hw_stats = tp->hw_stats; |
9679 | ||
9680 | if (!hw_stats) | |
9681 | return old_stats; | |
9682 | ||
9683 | stats->rx_packets = old_stats->rx_packets + | |
9684 | get_stat64(&hw_stats->rx_ucast_packets) + | |
9685 | get_stat64(&hw_stats->rx_mcast_packets) + | |
9686 | get_stat64(&hw_stats->rx_bcast_packets); | |
6aa20a22 | 9687 | |
1da177e4 LT |
9688 | stats->tx_packets = old_stats->tx_packets + |
9689 | get_stat64(&hw_stats->tx_ucast_packets) + | |
9690 | get_stat64(&hw_stats->tx_mcast_packets) + | |
9691 | get_stat64(&hw_stats->tx_bcast_packets); | |
9692 | ||
9693 | stats->rx_bytes = old_stats->rx_bytes + | |
9694 | get_stat64(&hw_stats->rx_octets); | |
9695 | stats->tx_bytes = old_stats->tx_bytes + | |
9696 | get_stat64(&hw_stats->tx_octets); | |
9697 | ||
9698 | stats->rx_errors = old_stats->rx_errors + | |
4f63b877 | 9699 | get_stat64(&hw_stats->rx_errors); |
1da177e4 LT |
9700 | stats->tx_errors = old_stats->tx_errors + |
9701 | get_stat64(&hw_stats->tx_errors) + | |
9702 | get_stat64(&hw_stats->tx_mac_errors) + | |
9703 | get_stat64(&hw_stats->tx_carrier_sense_errors) + | |
9704 | get_stat64(&hw_stats->tx_discards); | |
9705 | ||
9706 | stats->multicast = old_stats->multicast + | |
9707 | get_stat64(&hw_stats->rx_mcast_packets); | |
9708 | stats->collisions = old_stats->collisions + | |
9709 | get_stat64(&hw_stats->tx_collisions); | |
9710 | ||
9711 | stats->rx_length_errors = old_stats->rx_length_errors + | |
9712 | get_stat64(&hw_stats->rx_frame_too_long_errors) + | |
9713 | get_stat64(&hw_stats->rx_undersize_packets); | |
9714 | ||
9715 | stats->rx_over_errors = old_stats->rx_over_errors + | |
9716 | get_stat64(&hw_stats->rxbds_empty); | |
9717 | stats->rx_frame_errors = old_stats->rx_frame_errors + | |
9718 | get_stat64(&hw_stats->rx_align_errors); | |
9719 | stats->tx_aborted_errors = old_stats->tx_aborted_errors + | |
9720 | get_stat64(&hw_stats->tx_discards); | |
9721 | stats->tx_carrier_errors = old_stats->tx_carrier_errors + | |
9722 | get_stat64(&hw_stats->tx_carrier_sense_errors); | |
9723 | ||
9724 | stats->rx_crc_errors = old_stats->rx_crc_errors + | |
9725 | calc_crc_errors(tp); | |
9726 | ||
4f63b877 JL |
9727 | stats->rx_missed_errors = old_stats->rx_missed_errors + |
9728 | get_stat64(&hw_stats->rx_discards); | |
9729 | ||
b0057c51 ED |
9730 | stats->rx_dropped = tp->rx_dropped; |
9731 | ||
1da177e4 LT |
9732 | return stats; |
9733 | } | |
9734 | ||
9735 | static inline u32 calc_crc(unsigned char *buf, int len) | |
9736 | { | |
9737 | u32 reg; | |
9738 | u32 tmp; | |
9739 | int j, k; | |
9740 | ||
9741 | reg = 0xffffffff; | |
9742 | ||
9743 | for (j = 0; j < len; j++) { | |
9744 | reg ^= buf[j]; | |
9745 | ||
9746 | for (k = 0; k < 8; k++) { | |
9747 | tmp = reg & 0x01; | |
9748 | ||
9749 | reg >>= 1; | |
9750 | ||
859a5887 | 9751 | if (tmp) |
1da177e4 | 9752 | reg ^= 0xedb88320; |
1da177e4 LT |
9753 | } |
9754 | } | |
9755 | ||
9756 | return ~reg; | |
9757 | } | |
9758 | ||
9759 | static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all) | |
9760 | { | |
9761 | /* accept or reject all multicast frames */ | |
9762 | tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0); | |
9763 | tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0); | |
9764 | tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0); | |
9765 | tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0); | |
9766 | } | |
9767 | ||
9768 | static void __tg3_set_rx_mode(struct net_device *dev) | |
9769 | { | |
9770 | struct tg3 *tp = netdev_priv(dev); | |
9771 | u32 rx_mode; | |
9772 | ||
9773 | rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC | | |
9774 | RX_MODE_KEEP_VLAN_TAG); | |
9775 | ||
bf933c80 | 9776 | #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE) |
1da177e4 LT |
9777 | /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG |
9778 | * flag clear. | |
9779 | */ | |
63c3a66f | 9780 | if (!tg3_flag(tp, ENABLE_ASF)) |
1da177e4 LT |
9781 | rx_mode |= RX_MODE_KEEP_VLAN_TAG; |
9782 | #endif | |
9783 | ||
9784 | if (dev->flags & IFF_PROMISC) { | |
9785 | /* Promiscuous mode. */ | |
9786 | rx_mode |= RX_MODE_PROMISC; | |
9787 | } else if (dev->flags & IFF_ALLMULTI) { | |
9788 | /* Accept all multicast. */ | |
de6f31eb | 9789 | tg3_set_multi(tp, 1); |
4cd24eaf | 9790 | } else if (netdev_mc_empty(dev)) { |
1da177e4 | 9791 | /* Reject all multicast. */ |
de6f31eb | 9792 | tg3_set_multi(tp, 0); |
1da177e4 LT |
9793 | } else { |
9794 | /* Accept one or more multicast(s). */ | |
22bedad3 | 9795 | struct netdev_hw_addr *ha; |
1da177e4 LT |
9796 | u32 mc_filter[4] = { 0, }; |
9797 | u32 regidx; | |
9798 | u32 bit; | |
9799 | u32 crc; | |
9800 | ||
22bedad3 JP |
9801 | netdev_for_each_mc_addr(ha, dev) { |
9802 | crc = calc_crc(ha->addr, ETH_ALEN); | |
1da177e4 LT |
9803 | bit = ~crc & 0x7f; |
9804 | regidx = (bit & 0x60) >> 5; | |
9805 | bit &= 0x1f; | |
9806 | mc_filter[regidx] |= (1 << bit); | |
9807 | } | |
9808 | ||
9809 | tw32(MAC_HASH_REG_0, mc_filter[0]); | |
9810 | tw32(MAC_HASH_REG_1, mc_filter[1]); | |
9811 | tw32(MAC_HASH_REG_2, mc_filter[2]); | |
9812 | tw32(MAC_HASH_REG_3, mc_filter[3]); | |
9813 | } | |
9814 | ||
9815 | if (rx_mode != tp->rx_mode) { | |
9816 | tp->rx_mode = rx_mode; | |
9817 | tw32_f(MAC_RX_MODE, rx_mode); | |
9818 | udelay(10); | |
9819 | } | |
9820 | } | |
9821 | ||
9822 | static void tg3_set_rx_mode(struct net_device *dev) | |
9823 | { | |
9824 | struct tg3 *tp = netdev_priv(dev); | |
9825 | ||
e75f7c90 MC |
9826 | if (!netif_running(dev)) |
9827 | return; | |
9828 | ||
f47c11ee | 9829 | tg3_full_lock(tp, 0); |
1da177e4 | 9830 | __tg3_set_rx_mode(dev); |
f47c11ee | 9831 | tg3_full_unlock(tp); |
1da177e4 LT |
9832 | } |
9833 | ||
1da177e4 LT |
9834 | static int tg3_get_regs_len(struct net_device *dev) |
9835 | { | |
97bd8e49 | 9836 | return TG3_REG_BLK_SIZE; |
1da177e4 LT |
9837 | } |
9838 | ||
9839 | static void tg3_get_regs(struct net_device *dev, | |
9840 | struct ethtool_regs *regs, void *_p) | |
9841 | { | |
1da177e4 | 9842 | struct tg3 *tp = netdev_priv(dev); |
1da177e4 LT |
9843 | |
9844 | regs->version = 0; | |
9845 | ||
97bd8e49 | 9846 | memset(_p, 0, TG3_REG_BLK_SIZE); |
1da177e4 | 9847 | |
80096068 | 9848 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
bc1c7567 MC |
9849 | return; |
9850 | ||
f47c11ee | 9851 | tg3_full_lock(tp, 0); |
1da177e4 | 9852 | |
97bd8e49 | 9853 | tg3_dump_legacy_regs(tp, (u32 *)_p); |
1da177e4 | 9854 | |
f47c11ee | 9855 | tg3_full_unlock(tp); |
1da177e4 LT |
9856 | } |
9857 | ||
9858 | static int tg3_get_eeprom_len(struct net_device *dev) | |
9859 | { | |
9860 | struct tg3 *tp = netdev_priv(dev); | |
9861 | ||
9862 | return tp->nvram_size; | |
9863 | } | |
9864 | ||
1da177e4 LT |
9865 | static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data) |
9866 | { | |
9867 | struct tg3 *tp = netdev_priv(dev); | |
9868 | int ret; | |
9869 | u8 *pd; | |
b9fc7dc5 | 9870 | u32 i, offset, len, b_offset, b_count; |
a9dc529d | 9871 | __be32 val; |
1da177e4 | 9872 | |
63c3a66f | 9873 | if (tg3_flag(tp, NO_NVRAM)) |
df259d8c MC |
9874 | return -EINVAL; |
9875 | ||
80096068 | 9876 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
bc1c7567 MC |
9877 | return -EAGAIN; |
9878 | ||
1da177e4 LT |
9879 | offset = eeprom->offset; |
9880 | len = eeprom->len; | |
9881 | eeprom->len = 0; | |
9882 | ||
9883 | eeprom->magic = TG3_EEPROM_MAGIC; | |
9884 | ||
9885 | if (offset & 3) { | |
9886 | /* adjustments to start on required 4 byte boundary */ | |
9887 | b_offset = offset & 3; | |
9888 | b_count = 4 - b_offset; | |
9889 | if (b_count > len) { | |
9890 | /* i.e. offset=1 len=2 */ | |
9891 | b_count = len; | |
9892 | } | |
a9dc529d | 9893 | ret = tg3_nvram_read_be32(tp, offset-b_offset, &val); |
1da177e4 LT |
9894 | if (ret) |
9895 | return ret; | |
be98da6a | 9896 | memcpy(data, ((char *)&val) + b_offset, b_count); |
1da177e4 LT |
9897 | len -= b_count; |
9898 | offset += b_count; | |
c6cdf436 | 9899 | eeprom->len += b_count; |
1da177e4 LT |
9900 | } |
9901 | ||
25985edc | 9902 | /* read bytes up to the last 4 byte boundary */ |
1da177e4 LT |
9903 | pd = &data[eeprom->len]; |
9904 | for (i = 0; i < (len - (len & 3)); i += 4) { | |
a9dc529d | 9905 | ret = tg3_nvram_read_be32(tp, offset + i, &val); |
1da177e4 LT |
9906 | if (ret) { |
9907 | eeprom->len += i; | |
9908 | return ret; | |
9909 | } | |
1da177e4 LT |
9910 | memcpy(pd + i, &val, 4); |
9911 | } | |
9912 | eeprom->len += i; | |
9913 | ||
9914 | if (len & 3) { | |
9915 | /* read last bytes not ending on 4 byte boundary */ | |
9916 | pd = &data[eeprom->len]; | |
9917 | b_count = len & 3; | |
9918 | b_offset = offset + len - b_count; | |
a9dc529d | 9919 | ret = tg3_nvram_read_be32(tp, b_offset, &val); |
1da177e4 LT |
9920 | if (ret) |
9921 | return ret; | |
b9fc7dc5 | 9922 | memcpy(pd, &val, b_count); |
1da177e4 LT |
9923 | eeprom->len += b_count; |
9924 | } | |
9925 | return 0; | |
9926 | } | |
9927 | ||
6aa20a22 | 9928 | static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf); |
1da177e4 LT |
9929 | |
9930 | static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data) | |
9931 | { | |
9932 | struct tg3 *tp = netdev_priv(dev); | |
9933 | int ret; | |
b9fc7dc5 | 9934 | u32 offset, len, b_offset, odd_len; |
1da177e4 | 9935 | u8 *buf; |
a9dc529d | 9936 | __be32 start, end; |
1da177e4 | 9937 | |
80096068 | 9938 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
bc1c7567 MC |
9939 | return -EAGAIN; |
9940 | ||
63c3a66f | 9941 | if (tg3_flag(tp, NO_NVRAM) || |
df259d8c | 9942 | eeprom->magic != TG3_EEPROM_MAGIC) |
1da177e4 LT |
9943 | return -EINVAL; |
9944 | ||
9945 | offset = eeprom->offset; | |
9946 | len = eeprom->len; | |
9947 | ||
9948 | if ((b_offset = (offset & 3))) { | |
9949 | /* adjustments to start on required 4 byte boundary */ | |
a9dc529d | 9950 | ret = tg3_nvram_read_be32(tp, offset-b_offset, &start); |
1da177e4 LT |
9951 | if (ret) |
9952 | return ret; | |
1da177e4 LT |
9953 | len += b_offset; |
9954 | offset &= ~3; | |
1c8594b4 MC |
9955 | if (len < 4) |
9956 | len = 4; | |
1da177e4 LT |
9957 | } |
9958 | ||
9959 | odd_len = 0; | |
1c8594b4 | 9960 | if (len & 3) { |
1da177e4 LT |
9961 | /* adjustments to end on required 4 byte boundary */ |
9962 | odd_len = 1; | |
9963 | len = (len + 3) & ~3; | |
a9dc529d | 9964 | ret = tg3_nvram_read_be32(tp, offset+len-4, &end); |
1da177e4 LT |
9965 | if (ret) |
9966 | return ret; | |
1da177e4 LT |
9967 | } |
9968 | ||
9969 | buf = data; | |
9970 | if (b_offset || odd_len) { | |
9971 | buf = kmalloc(len, GFP_KERNEL); | |
ab0049b4 | 9972 | if (!buf) |
1da177e4 LT |
9973 | return -ENOMEM; |
9974 | if (b_offset) | |
9975 | memcpy(buf, &start, 4); | |
9976 | if (odd_len) | |
9977 | memcpy(buf+len-4, &end, 4); | |
9978 | memcpy(buf + b_offset, data, eeprom->len); | |
9979 | } | |
9980 | ||
9981 | ret = tg3_nvram_write_block(tp, offset, len, buf); | |
9982 | ||
9983 | if (buf != data) | |
9984 | kfree(buf); | |
9985 | ||
9986 | return ret; | |
9987 | } | |
9988 | ||
9989 | static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
9990 | { | |
b02fd9e3 MC |
9991 | struct tg3 *tp = netdev_priv(dev); |
9992 | ||
63c3a66f | 9993 | if (tg3_flag(tp, USE_PHYLIB)) { |
3f0e3ad7 | 9994 | struct phy_device *phydev; |
f07e9af3 | 9995 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 | 9996 | return -EAGAIN; |
3f0e3ad7 MC |
9997 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
9998 | return phy_ethtool_gset(phydev, cmd); | |
b02fd9e3 | 9999 | } |
6aa20a22 | 10000 | |
1da177e4 LT |
10001 | cmd->supported = (SUPPORTED_Autoneg); |
10002 | ||
f07e9af3 | 10003 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) |
1da177e4 LT |
10004 | cmd->supported |= (SUPPORTED_1000baseT_Half | |
10005 | SUPPORTED_1000baseT_Full); | |
10006 | ||
f07e9af3 | 10007 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { |
1da177e4 LT |
10008 | cmd->supported |= (SUPPORTED_100baseT_Half | |
10009 | SUPPORTED_100baseT_Full | | |
10010 | SUPPORTED_10baseT_Half | | |
10011 | SUPPORTED_10baseT_Full | | |
3bebab59 | 10012 | SUPPORTED_TP); |
ef348144 KK |
10013 | cmd->port = PORT_TP; |
10014 | } else { | |
1da177e4 | 10015 | cmd->supported |= SUPPORTED_FIBRE; |
ef348144 KK |
10016 | cmd->port = PORT_FIBRE; |
10017 | } | |
6aa20a22 | 10018 | |
1da177e4 | 10019 | cmd->advertising = tp->link_config.advertising; |
5bb09778 MC |
10020 | if (tg3_flag(tp, PAUSE_AUTONEG)) { |
10021 | if (tp->link_config.flowctrl & FLOW_CTRL_RX) { | |
10022 | if (tp->link_config.flowctrl & FLOW_CTRL_TX) { | |
10023 | cmd->advertising |= ADVERTISED_Pause; | |
10024 | } else { | |
10025 | cmd->advertising |= ADVERTISED_Pause | | |
10026 | ADVERTISED_Asym_Pause; | |
10027 | } | |
10028 | } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) { | |
10029 | cmd->advertising |= ADVERTISED_Asym_Pause; | |
10030 | } | |
10031 | } | |
1da177e4 | 10032 | if (netif_running(dev)) { |
70739497 | 10033 | ethtool_cmd_speed_set(cmd, tp->link_config.active_speed); |
1da177e4 | 10034 | cmd->duplex = tp->link_config.active_duplex; |
64c22182 | 10035 | } else { |
70739497 | 10036 | ethtool_cmd_speed_set(cmd, SPEED_INVALID); |
64c22182 | 10037 | cmd->duplex = DUPLEX_INVALID; |
1da177e4 | 10038 | } |
882e9793 | 10039 | cmd->phy_address = tp->phy_addr; |
7e5856bd | 10040 | cmd->transceiver = XCVR_INTERNAL; |
1da177e4 LT |
10041 | cmd->autoneg = tp->link_config.autoneg; |
10042 | cmd->maxtxpkt = 0; | |
10043 | cmd->maxrxpkt = 0; | |
10044 | return 0; | |
10045 | } | |
6aa20a22 | 10046 | |
1da177e4 LT |
10047 | static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
10048 | { | |
10049 | struct tg3 *tp = netdev_priv(dev); | |
25db0338 | 10050 | u32 speed = ethtool_cmd_speed(cmd); |
6aa20a22 | 10051 | |
63c3a66f | 10052 | if (tg3_flag(tp, USE_PHYLIB)) { |
3f0e3ad7 | 10053 | struct phy_device *phydev; |
f07e9af3 | 10054 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 | 10055 | return -EAGAIN; |
3f0e3ad7 MC |
10056 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
10057 | return phy_ethtool_sset(phydev, cmd); | |
b02fd9e3 MC |
10058 | } |
10059 | ||
7e5856bd MC |
10060 | if (cmd->autoneg != AUTONEG_ENABLE && |
10061 | cmd->autoneg != AUTONEG_DISABLE) | |
37ff238d | 10062 | return -EINVAL; |
7e5856bd MC |
10063 | |
10064 | if (cmd->autoneg == AUTONEG_DISABLE && | |
10065 | cmd->duplex != DUPLEX_FULL && | |
10066 | cmd->duplex != DUPLEX_HALF) | |
37ff238d | 10067 | return -EINVAL; |
1da177e4 | 10068 | |
7e5856bd MC |
10069 | if (cmd->autoneg == AUTONEG_ENABLE) { |
10070 | u32 mask = ADVERTISED_Autoneg | | |
10071 | ADVERTISED_Pause | | |
10072 | ADVERTISED_Asym_Pause; | |
10073 | ||
f07e9af3 | 10074 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) |
7e5856bd MC |
10075 | mask |= ADVERTISED_1000baseT_Half | |
10076 | ADVERTISED_1000baseT_Full; | |
10077 | ||
f07e9af3 | 10078 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) |
7e5856bd MC |
10079 | mask |= ADVERTISED_100baseT_Half | |
10080 | ADVERTISED_100baseT_Full | | |
10081 | ADVERTISED_10baseT_Half | | |
10082 | ADVERTISED_10baseT_Full | | |
10083 | ADVERTISED_TP; | |
10084 | else | |
10085 | mask |= ADVERTISED_FIBRE; | |
10086 | ||
10087 | if (cmd->advertising & ~mask) | |
10088 | return -EINVAL; | |
10089 | ||
10090 | mask &= (ADVERTISED_1000baseT_Half | | |
10091 | ADVERTISED_1000baseT_Full | | |
10092 | ADVERTISED_100baseT_Half | | |
10093 | ADVERTISED_100baseT_Full | | |
10094 | ADVERTISED_10baseT_Half | | |
10095 | ADVERTISED_10baseT_Full); | |
10096 | ||
10097 | cmd->advertising &= mask; | |
10098 | } else { | |
f07e9af3 | 10099 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) { |
25db0338 | 10100 | if (speed != SPEED_1000) |
7e5856bd MC |
10101 | return -EINVAL; |
10102 | ||
10103 | if (cmd->duplex != DUPLEX_FULL) | |
10104 | return -EINVAL; | |
10105 | } else { | |
25db0338 DD |
10106 | if (speed != SPEED_100 && |
10107 | speed != SPEED_10) | |
7e5856bd MC |
10108 | return -EINVAL; |
10109 | } | |
10110 | } | |
10111 | ||
f47c11ee | 10112 | tg3_full_lock(tp, 0); |
1da177e4 LT |
10113 | |
10114 | tp->link_config.autoneg = cmd->autoneg; | |
10115 | if (cmd->autoneg == AUTONEG_ENABLE) { | |
405d8e5c AG |
10116 | tp->link_config.advertising = (cmd->advertising | |
10117 | ADVERTISED_Autoneg); | |
1da177e4 LT |
10118 | tp->link_config.speed = SPEED_INVALID; |
10119 | tp->link_config.duplex = DUPLEX_INVALID; | |
10120 | } else { | |
10121 | tp->link_config.advertising = 0; | |
25db0338 | 10122 | tp->link_config.speed = speed; |
1da177e4 | 10123 | tp->link_config.duplex = cmd->duplex; |
b02fd9e3 | 10124 | } |
6aa20a22 | 10125 | |
24fcad6b MC |
10126 | tp->link_config.orig_speed = tp->link_config.speed; |
10127 | tp->link_config.orig_duplex = tp->link_config.duplex; | |
10128 | tp->link_config.orig_autoneg = tp->link_config.autoneg; | |
10129 | ||
1da177e4 LT |
10130 | if (netif_running(dev)) |
10131 | tg3_setup_phy(tp, 1); | |
10132 | ||
f47c11ee | 10133 | tg3_full_unlock(tp); |
6aa20a22 | 10134 | |
1da177e4 LT |
10135 | return 0; |
10136 | } | |
6aa20a22 | 10137 | |
1da177e4 LT |
10138 | static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) |
10139 | { | |
10140 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 10141 | |
1da177e4 LT |
10142 | strcpy(info->driver, DRV_MODULE_NAME); |
10143 | strcpy(info->version, DRV_MODULE_VERSION); | |
c4e6575c | 10144 | strcpy(info->fw_version, tp->fw_ver); |
1da177e4 LT |
10145 | strcpy(info->bus_info, pci_name(tp->pdev)); |
10146 | } | |
6aa20a22 | 10147 | |
1da177e4 LT |
10148 | static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
10149 | { | |
10150 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 10151 | |
63c3a66f | 10152 | if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev)) |
a85feb8c GZ |
10153 | wol->supported = WAKE_MAGIC; |
10154 | else | |
10155 | wol->supported = 0; | |
1da177e4 | 10156 | wol->wolopts = 0; |
63c3a66f | 10157 | if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev)) |
1da177e4 LT |
10158 | wol->wolopts = WAKE_MAGIC; |
10159 | memset(&wol->sopass, 0, sizeof(wol->sopass)); | |
10160 | } | |
6aa20a22 | 10161 | |
1da177e4 LT |
10162 | static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
10163 | { | |
10164 | struct tg3 *tp = netdev_priv(dev); | |
12dac075 | 10165 | struct device *dp = &tp->pdev->dev; |
6aa20a22 | 10166 | |
1da177e4 LT |
10167 | if (wol->wolopts & ~WAKE_MAGIC) |
10168 | return -EINVAL; | |
10169 | if ((wol->wolopts & WAKE_MAGIC) && | |
63c3a66f | 10170 | !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp))) |
1da177e4 | 10171 | return -EINVAL; |
6aa20a22 | 10172 | |
f2dc0d18 RW |
10173 | device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC); |
10174 | ||
f47c11ee | 10175 | spin_lock_bh(&tp->lock); |
f2dc0d18 | 10176 | if (device_may_wakeup(dp)) |
63c3a66f | 10177 | tg3_flag_set(tp, WOL_ENABLE); |
f2dc0d18 | 10178 | else |
63c3a66f | 10179 | tg3_flag_clear(tp, WOL_ENABLE); |
f47c11ee | 10180 | spin_unlock_bh(&tp->lock); |
6aa20a22 | 10181 | |
1da177e4 LT |
10182 | return 0; |
10183 | } | |
6aa20a22 | 10184 | |
1da177e4 LT |
10185 | static u32 tg3_get_msglevel(struct net_device *dev) |
10186 | { | |
10187 | struct tg3 *tp = netdev_priv(dev); | |
10188 | return tp->msg_enable; | |
10189 | } | |
6aa20a22 | 10190 | |
1da177e4 LT |
10191 | static void tg3_set_msglevel(struct net_device *dev, u32 value) |
10192 | { | |
10193 | struct tg3 *tp = netdev_priv(dev); | |
10194 | tp->msg_enable = value; | |
10195 | } | |
6aa20a22 | 10196 | |
1da177e4 LT |
10197 | static int tg3_nway_reset(struct net_device *dev) |
10198 | { | |
10199 | struct tg3 *tp = netdev_priv(dev); | |
1da177e4 | 10200 | int r; |
6aa20a22 | 10201 | |
1da177e4 LT |
10202 | if (!netif_running(dev)) |
10203 | return -EAGAIN; | |
10204 | ||
f07e9af3 | 10205 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
c94e3941 MC |
10206 | return -EINVAL; |
10207 | ||
63c3a66f | 10208 | if (tg3_flag(tp, USE_PHYLIB)) { |
f07e9af3 | 10209 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 | 10210 | return -EAGAIN; |
3f0e3ad7 | 10211 | r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
b02fd9e3 MC |
10212 | } else { |
10213 | u32 bmcr; | |
10214 | ||
10215 | spin_lock_bh(&tp->lock); | |
10216 | r = -EINVAL; | |
10217 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
10218 | if (!tg3_readphy(tp, MII_BMCR, &bmcr) && | |
10219 | ((bmcr & BMCR_ANENABLE) || | |
f07e9af3 | 10220 | (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) { |
b02fd9e3 MC |
10221 | tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART | |
10222 | BMCR_ANENABLE); | |
10223 | r = 0; | |
10224 | } | |
10225 | spin_unlock_bh(&tp->lock); | |
1da177e4 | 10226 | } |
6aa20a22 | 10227 | |
1da177e4 LT |
10228 | return r; |
10229 | } | |
6aa20a22 | 10230 | |
1da177e4 LT |
10231 | static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) |
10232 | { | |
10233 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 10234 | |
2c49a44d | 10235 | ering->rx_max_pending = tp->rx_std_ring_mask; |
1da177e4 | 10236 | ering->rx_mini_max_pending = 0; |
63c3a66f | 10237 | if (tg3_flag(tp, JUMBO_RING_ENABLE)) |
2c49a44d | 10238 | ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask; |
4f81c32b MC |
10239 | else |
10240 | ering->rx_jumbo_max_pending = 0; | |
10241 | ||
10242 | ering->tx_max_pending = TG3_TX_RING_SIZE - 1; | |
1da177e4 LT |
10243 | |
10244 | ering->rx_pending = tp->rx_pending; | |
10245 | ering->rx_mini_pending = 0; | |
63c3a66f | 10246 | if (tg3_flag(tp, JUMBO_RING_ENABLE)) |
4f81c32b MC |
10247 | ering->rx_jumbo_pending = tp->rx_jumbo_pending; |
10248 | else | |
10249 | ering->rx_jumbo_pending = 0; | |
10250 | ||
f3f3f27e | 10251 | ering->tx_pending = tp->napi[0].tx_pending; |
1da177e4 | 10252 | } |
6aa20a22 | 10253 | |
1da177e4 LT |
10254 | static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) |
10255 | { | |
10256 | struct tg3 *tp = netdev_priv(dev); | |
646c9edd | 10257 | int i, irq_sync = 0, err = 0; |
6aa20a22 | 10258 | |
2c49a44d MC |
10259 | if ((ering->rx_pending > tp->rx_std_ring_mask) || |
10260 | (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) || | |
bc3a9254 MC |
10261 | (ering->tx_pending > TG3_TX_RING_SIZE - 1) || |
10262 | (ering->tx_pending <= MAX_SKB_FRAGS) || | |
63c3a66f | 10263 | (tg3_flag(tp, TSO_BUG) && |
bc3a9254 | 10264 | (ering->tx_pending <= (MAX_SKB_FRAGS * 3)))) |
1da177e4 | 10265 | return -EINVAL; |
6aa20a22 | 10266 | |
bbe832c0 | 10267 | if (netif_running(dev)) { |
b02fd9e3 | 10268 | tg3_phy_stop(tp); |
1da177e4 | 10269 | tg3_netif_stop(tp); |
bbe832c0 MC |
10270 | irq_sync = 1; |
10271 | } | |
1da177e4 | 10272 | |
bbe832c0 | 10273 | tg3_full_lock(tp, irq_sync); |
6aa20a22 | 10274 | |
1da177e4 LT |
10275 | tp->rx_pending = ering->rx_pending; |
10276 | ||
63c3a66f | 10277 | if (tg3_flag(tp, MAX_RXPEND_64) && |
1da177e4 LT |
10278 | tp->rx_pending > 63) |
10279 | tp->rx_pending = 63; | |
10280 | tp->rx_jumbo_pending = ering->rx_jumbo_pending; | |
646c9edd | 10281 | |
6fd45cb8 | 10282 | for (i = 0; i < tp->irq_max; i++) |
646c9edd | 10283 | tp->napi[i].tx_pending = ering->tx_pending; |
1da177e4 LT |
10284 | |
10285 | if (netif_running(dev)) { | |
944d980e | 10286 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
b9ec6c1b MC |
10287 | err = tg3_restart_hw(tp, 1); |
10288 | if (!err) | |
10289 | tg3_netif_start(tp); | |
1da177e4 LT |
10290 | } |
10291 | ||
f47c11ee | 10292 | tg3_full_unlock(tp); |
6aa20a22 | 10293 | |
b02fd9e3 MC |
10294 | if (irq_sync && !err) |
10295 | tg3_phy_start(tp); | |
10296 | ||
b9ec6c1b | 10297 | return err; |
1da177e4 | 10298 | } |
6aa20a22 | 10299 | |
1da177e4 LT |
10300 | static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) |
10301 | { | |
10302 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 10303 | |
63c3a66f | 10304 | epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG); |
8d018621 | 10305 | |
e18ce346 | 10306 | if (tp->link_config.active_flowctrl & FLOW_CTRL_RX) |
8d018621 MC |
10307 | epause->rx_pause = 1; |
10308 | else | |
10309 | epause->rx_pause = 0; | |
10310 | ||
e18ce346 | 10311 | if (tp->link_config.active_flowctrl & FLOW_CTRL_TX) |
8d018621 MC |
10312 | epause->tx_pause = 1; |
10313 | else | |
10314 | epause->tx_pause = 0; | |
1da177e4 | 10315 | } |
6aa20a22 | 10316 | |
1da177e4 LT |
10317 | static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) |
10318 | { | |
10319 | struct tg3 *tp = netdev_priv(dev); | |
b02fd9e3 | 10320 | int err = 0; |
6aa20a22 | 10321 | |
63c3a66f | 10322 | if (tg3_flag(tp, USE_PHYLIB)) { |
2712168f MC |
10323 | u32 newadv; |
10324 | struct phy_device *phydev; | |
1da177e4 | 10325 | |
2712168f | 10326 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
f47c11ee | 10327 | |
2712168f MC |
10328 | if (!(phydev->supported & SUPPORTED_Pause) || |
10329 | (!(phydev->supported & SUPPORTED_Asym_Pause) && | |
2259dca3 | 10330 | (epause->rx_pause != epause->tx_pause))) |
2712168f | 10331 | return -EINVAL; |
1da177e4 | 10332 | |
2712168f MC |
10333 | tp->link_config.flowctrl = 0; |
10334 | if (epause->rx_pause) { | |
10335 | tp->link_config.flowctrl |= FLOW_CTRL_RX; | |
10336 | ||
10337 | if (epause->tx_pause) { | |
10338 | tp->link_config.flowctrl |= FLOW_CTRL_TX; | |
10339 | newadv = ADVERTISED_Pause; | |
b02fd9e3 | 10340 | } else |
2712168f MC |
10341 | newadv = ADVERTISED_Pause | |
10342 | ADVERTISED_Asym_Pause; | |
10343 | } else if (epause->tx_pause) { | |
10344 | tp->link_config.flowctrl |= FLOW_CTRL_TX; | |
10345 | newadv = ADVERTISED_Asym_Pause; | |
10346 | } else | |
10347 | newadv = 0; | |
10348 | ||
10349 | if (epause->autoneg) | |
63c3a66f | 10350 | tg3_flag_set(tp, PAUSE_AUTONEG); |
2712168f | 10351 | else |
63c3a66f | 10352 | tg3_flag_clear(tp, PAUSE_AUTONEG); |
2712168f | 10353 | |
f07e9af3 | 10354 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { |
2712168f MC |
10355 | u32 oldadv = phydev->advertising & |
10356 | (ADVERTISED_Pause | ADVERTISED_Asym_Pause); | |
10357 | if (oldadv != newadv) { | |
10358 | phydev->advertising &= | |
10359 | ~(ADVERTISED_Pause | | |
10360 | ADVERTISED_Asym_Pause); | |
10361 | phydev->advertising |= newadv; | |
10362 | if (phydev->autoneg) { | |
10363 | /* | |
10364 | * Always renegotiate the link to | |
10365 | * inform our link partner of our | |
10366 | * flow control settings, even if the | |
10367 | * flow control is forced. Let | |
10368 | * tg3_adjust_link() do the final | |
10369 | * flow control setup. | |
10370 | */ | |
10371 | return phy_start_aneg(phydev); | |
b02fd9e3 | 10372 | } |
b02fd9e3 | 10373 | } |
b02fd9e3 | 10374 | |
2712168f | 10375 | if (!epause->autoneg) |
b02fd9e3 | 10376 | tg3_setup_flow_control(tp, 0, 0); |
2712168f MC |
10377 | } else { |
10378 | tp->link_config.orig_advertising &= | |
10379 | ~(ADVERTISED_Pause | | |
10380 | ADVERTISED_Asym_Pause); | |
10381 | tp->link_config.orig_advertising |= newadv; | |
b02fd9e3 MC |
10382 | } |
10383 | } else { | |
10384 | int irq_sync = 0; | |
10385 | ||
10386 | if (netif_running(dev)) { | |
10387 | tg3_netif_stop(tp); | |
10388 | irq_sync = 1; | |
10389 | } | |
10390 | ||
10391 | tg3_full_lock(tp, irq_sync); | |
10392 | ||
10393 | if (epause->autoneg) | |
63c3a66f | 10394 | tg3_flag_set(tp, PAUSE_AUTONEG); |
b02fd9e3 | 10395 | else |
63c3a66f | 10396 | tg3_flag_clear(tp, PAUSE_AUTONEG); |
b02fd9e3 | 10397 | if (epause->rx_pause) |
e18ce346 | 10398 | tp->link_config.flowctrl |= FLOW_CTRL_RX; |
b02fd9e3 | 10399 | else |
e18ce346 | 10400 | tp->link_config.flowctrl &= ~FLOW_CTRL_RX; |
b02fd9e3 | 10401 | if (epause->tx_pause) |
e18ce346 | 10402 | tp->link_config.flowctrl |= FLOW_CTRL_TX; |
b02fd9e3 | 10403 | else |
e18ce346 | 10404 | tp->link_config.flowctrl &= ~FLOW_CTRL_TX; |
b02fd9e3 MC |
10405 | |
10406 | if (netif_running(dev)) { | |
10407 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
10408 | err = tg3_restart_hw(tp, 1); | |
10409 | if (!err) | |
10410 | tg3_netif_start(tp); | |
10411 | } | |
10412 | ||
10413 | tg3_full_unlock(tp); | |
10414 | } | |
6aa20a22 | 10415 | |
b9ec6c1b | 10416 | return err; |
1da177e4 | 10417 | } |
6aa20a22 | 10418 | |
de6f31eb | 10419 | static int tg3_get_sset_count(struct net_device *dev, int sset) |
1da177e4 | 10420 | { |
b9f2c044 JG |
10421 | switch (sset) { |
10422 | case ETH_SS_TEST: | |
10423 | return TG3_NUM_TEST; | |
10424 | case ETH_SS_STATS: | |
10425 | return TG3_NUM_STATS; | |
10426 | default: | |
10427 | return -EOPNOTSUPP; | |
10428 | } | |
4cafd3f5 MC |
10429 | } |
10430 | ||
de6f31eb | 10431 | static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf) |
1da177e4 LT |
10432 | { |
10433 | switch (stringset) { | |
10434 | case ETH_SS_STATS: | |
10435 | memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys)); | |
10436 | break; | |
4cafd3f5 MC |
10437 | case ETH_SS_TEST: |
10438 | memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys)); | |
10439 | break; | |
1da177e4 LT |
10440 | default: |
10441 | WARN_ON(1); /* we need a WARN() */ | |
10442 | break; | |
10443 | } | |
10444 | } | |
10445 | ||
81b8709c | 10446 | static int tg3_set_phys_id(struct net_device *dev, |
10447 | enum ethtool_phys_id_state state) | |
4009a93d MC |
10448 | { |
10449 | struct tg3 *tp = netdev_priv(dev); | |
4009a93d MC |
10450 | |
10451 | if (!netif_running(tp->dev)) | |
10452 | return -EAGAIN; | |
10453 | ||
81b8709c | 10454 | switch (state) { |
10455 | case ETHTOOL_ID_ACTIVE: | |
fce55922 | 10456 | return 1; /* cycle on/off once per second */ |
4009a93d | 10457 | |
81b8709c | 10458 | case ETHTOOL_ID_ON: |
10459 | tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE | | |
10460 | LED_CTRL_1000MBPS_ON | | |
10461 | LED_CTRL_100MBPS_ON | | |
10462 | LED_CTRL_10MBPS_ON | | |
10463 | LED_CTRL_TRAFFIC_OVERRIDE | | |
10464 | LED_CTRL_TRAFFIC_BLINK | | |
10465 | LED_CTRL_TRAFFIC_LED); | |
10466 | break; | |
6aa20a22 | 10467 | |
81b8709c | 10468 | case ETHTOOL_ID_OFF: |
10469 | tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE | | |
10470 | LED_CTRL_TRAFFIC_OVERRIDE); | |
10471 | break; | |
4009a93d | 10472 | |
81b8709c | 10473 | case ETHTOOL_ID_INACTIVE: |
10474 | tw32(MAC_LED_CTRL, tp->led_ctrl); | |
10475 | break; | |
4009a93d | 10476 | } |
81b8709c | 10477 | |
4009a93d MC |
10478 | return 0; |
10479 | } | |
10480 | ||
de6f31eb | 10481 | static void tg3_get_ethtool_stats(struct net_device *dev, |
1da177e4 LT |
10482 | struct ethtool_stats *estats, u64 *tmp_stats) |
10483 | { | |
10484 | struct tg3 *tp = netdev_priv(dev); | |
10485 | memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats)); | |
10486 | } | |
10487 | ||
c3e94500 MC |
10488 | static __be32 * tg3_vpd_readblock(struct tg3 *tp) |
10489 | { | |
10490 | int i; | |
10491 | __be32 *buf; | |
10492 | u32 offset = 0, len = 0; | |
10493 | u32 magic, val; | |
10494 | ||
63c3a66f | 10495 | if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic)) |
c3e94500 MC |
10496 | return NULL; |
10497 | ||
10498 | if (magic == TG3_EEPROM_MAGIC) { | |
10499 | for (offset = TG3_NVM_DIR_START; | |
10500 | offset < TG3_NVM_DIR_END; | |
10501 | offset += TG3_NVM_DIRENT_SIZE) { | |
10502 | if (tg3_nvram_read(tp, offset, &val)) | |
10503 | return NULL; | |
10504 | ||
10505 | if ((val >> TG3_NVM_DIRTYPE_SHIFT) == | |
10506 | TG3_NVM_DIRTYPE_EXTVPD) | |
10507 | break; | |
10508 | } | |
10509 | ||
10510 | if (offset != TG3_NVM_DIR_END) { | |
10511 | len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4; | |
10512 | if (tg3_nvram_read(tp, offset + 4, &offset)) | |
10513 | return NULL; | |
10514 | ||
10515 | offset = tg3_nvram_logical_addr(tp, offset); | |
10516 | } | |
10517 | } | |
10518 | ||
10519 | if (!offset || !len) { | |
10520 | offset = TG3_NVM_VPD_OFF; | |
10521 | len = TG3_NVM_VPD_LEN; | |
10522 | } | |
10523 | ||
10524 | buf = kmalloc(len, GFP_KERNEL); | |
10525 | if (buf == NULL) | |
10526 | return NULL; | |
10527 | ||
10528 | if (magic == TG3_EEPROM_MAGIC) { | |
10529 | for (i = 0; i < len; i += 4) { | |
10530 | /* The data is in little-endian format in NVRAM. | |
10531 | * Use the big-endian read routines to preserve | |
10532 | * the byte order as it exists in NVRAM. | |
10533 | */ | |
10534 | if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4])) | |
10535 | goto error; | |
10536 | } | |
10537 | } else { | |
10538 | u8 *ptr; | |
10539 | ssize_t cnt; | |
10540 | unsigned int pos = 0; | |
10541 | ||
10542 | ptr = (u8 *)&buf[0]; | |
10543 | for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) { | |
10544 | cnt = pci_read_vpd(tp->pdev, pos, | |
10545 | len - pos, ptr); | |
10546 | if (cnt == -ETIMEDOUT || cnt == -EINTR) | |
10547 | cnt = 0; | |
10548 | else if (cnt < 0) | |
10549 | goto error; | |
10550 | } | |
10551 | if (pos != len) | |
10552 | goto error; | |
10553 | } | |
10554 | ||
10555 | return buf; | |
10556 | ||
10557 | error: | |
10558 | kfree(buf); | |
10559 | return NULL; | |
10560 | } | |
10561 | ||
566f86ad | 10562 | #define NVRAM_TEST_SIZE 0x100 |
a5767dec MC |
10563 | #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14 |
10564 | #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18 | |
10565 | #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c | |
727a6d9f MC |
10566 | #define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20 |
10567 | #define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24 | |
10568 | #define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x4c | |
b16250e3 MC |
10569 | #define NVRAM_SELFBOOT_HW_SIZE 0x20 |
10570 | #define NVRAM_SELFBOOT_DATA_SIZE 0x1c | |
566f86ad MC |
10571 | |
10572 | static int tg3_test_nvram(struct tg3 *tp) | |
10573 | { | |
b9fc7dc5 | 10574 | u32 csum, magic; |
a9dc529d | 10575 | __be32 *buf; |
ab0049b4 | 10576 | int i, j, k, err = 0, size; |
566f86ad | 10577 | |
63c3a66f | 10578 | if (tg3_flag(tp, NO_NVRAM)) |
df259d8c MC |
10579 | return 0; |
10580 | ||
e4f34110 | 10581 | if (tg3_nvram_read(tp, 0, &magic) != 0) |
1b27777a MC |
10582 | return -EIO; |
10583 | ||
1b27777a MC |
10584 | if (magic == TG3_EEPROM_MAGIC) |
10585 | size = NVRAM_TEST_SIZE; | |
b16250e3 | 10586 | else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) { |
a5767dec MC |
10587 | if ((magic & TG3_EEPROM_SB_FORMAT_MASK) == |
10588 | TG3_EEPROM_SB_FORMAT_1) { | |
10589 | switch (magic & TG3_EEPROM_SB_REVISION_MASK) { | |
10590 | case TG3_EEPROM_SB_REVISION_0: | |
10591 | size = NVRAM_SELFBOOT_FORMAT1_0_SIZE; | |
10592 | break; | |
10593 | case TG3_EEPROM_SB_REVISION_2: | |
10594 | size = NVRAM_SELFBOOT_FORMAT1_2_SIZE; | |
10595 | break; | |
10596 | case TG3_EEPROM_SB_REVISION_3: | |
10597 | size = NVRAM_SELFBOOT_FORMAT1_3_SIZE; | |
10598 | break; | |
727a6d9f MC |
10599 | case TG3_EEPROM_SB_REVISION_4: |
10600 | size = NVRAM_SELFBOOT_FORMAT1_4_SIZE; | |
10601 | break; | |
10602 | case TG3_EEPROM_SB_REVISION_5: | |
10603 | size = NVRAM_SELFBOOT_FORMAT1_5_SIZE; | |
10604 | break; | |
10605 | case TG3_EEPROM_SB_REVISION_6: | |
10606 | size = NVRAM_SELFBOOT_FORMAT1_6_SIZE; | |
10607 | break; | |
a5767dec | 10608 | default: |
727a6d9f | 10609 | return -EIO; |
a5767dec MC |
10610 | } |
10611 | } else | |
1b27777a | 10612 | return 0; |
b16250e3 MC |
10613 | } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW) |
10614 | size = NVRAM_SELFBOOT_HW_SIZE; | |
10615 | else | |
1b27777a MC |
10616 | return -EIO; |
10617 | ||
10618 | buf = kmalloc(size, GFP_KERNEL); | |
566f86ad MC |
10619 | if (buf == NULL) |
10620 | return -ENOMEM; | |
10621 | ||
1b27777a MC |
10622 | err = -EIO; |
10623 | for (i = 0, j = 0; i < size; i += 4, j++) { | |
a9dc529d MC |
10624 | err = tg3_nvram_read_be32(tp, i, &buf[j]); |
10625 | if (err) | |
566f86ad | 10626 | break; |
566f86ad | 10627 | } |
1b27777a | 10628 | if (i < size) |
566f86ad MC |
10629 | goto out; |
10630 | ||
1b27777a | 10631 | /* Selfboot format */ |
a9dc529d | 10632 | magic = be32_to_cpu(buf[0]); |
b9fc7dc5 | 10633 | if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == |
b16250e3 | 10634 | TG3_EEPROM_MAGIC_FW) { |
1b27777a MC |
10635 | u8 *buf8 = (u8 *) buf, csum8 = 0; |
10636 | ||
b9fc7dc5 | 10637 | if ((magic & TG3_EEPROM_SB_REVISION_MASK) == |
a5767dec MC |
10638 | TG3_EEPROM_SB_REVISION_2) { |
10639 | /* For rev 2, the csum doesn't include the MBA. */ | |
10640 | for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++) | |
10641 | csum8 += buf8[i]; | |
10642 | for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++) | |
10643 | csum8 += buf8[i]; | |
10644 | } else { | |
10645 | for (i = 0; i < size; i++) | |
10646 | csum8 += buf8[i]; | |
10647 | } | |
1b27777a | 10648 | |
ad96b485 AB |
10649 | if (csum8 == 0) { |
10650 | err = 0; | |
10651 | goto out; | |
10652 | } | |
10653 | ||
10654 | err = -EIO; | |
10655 | goto out; | |
1b27777a | 10656 | } |
566f86ad | 10657 | |
b9fc7dc5 | 10658 | if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == |
b16250e3 MC |
10659 | TG3_EEPROM_MAGIC_HW) { |
10660 | u8 data[NVRAM_SELFBOOT_DATA_SIZE]; | |
a9dc529d | 10661 | u8 parity[NVRAM_SELFBOOT_DATA_SIZE]; |
b16250e3 | 10662 | u8 *buf8 = (u8 *) buf; |
b16250e3 MC |
10663 | |
10664 | /* Separate the parity bits and the data bytes. */ | |
10665 | for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) { | |
10666 | if ((i == 0) || (i == 8)) { | |
10667 | int l; | |
10668 | u8 msk; | |
10669 | ||
10670 | for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1) | |
10671 | parity[k++] = buf8[i] & msk; | |
10672 | i++; | |
859a5887 | 10673 | } else if (i == 16) { |
b16250e3 MC |
10674 | int l; |
10675 | u8 msk; | |
10676 | ||
10677 | for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1) | |
10678 | parity[k++] = buf8[i] & msk; | |
10679 | i++; | |
10680 | ||
10681 | for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1) | |
10682 | parity[k++] = buf8[i] & msk; | |
10683 | i++; | |
10684 | } | |
10685 | data[j++] = buf8[i]; | |
10686 | } | |
10687 | ||
10688 | err = -EIO; | |
10689 | for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) { | |
10690 | u8 hw8 = hweight8(data[i]); | |
10691 | ||
10692 | if ((hw8 & 0x1) && parity[i]) | |
10693 | goto out; | |
10694 | else if (!(hw8 & 0x1) && !parity[i]) | |
10695 | goto out; | |
10696 | } | |
10697 | err = 0; | |
10698 | goto out; | |
10699 | } | |
10700 | ||
01c3a392 MC |
10701 | err = -EIO; |
10702 | ||
566f86ad MC |
10703 | /* Bootstrap checksum at offset 0x10 */ |
10704 | csum = calc_crc((unsigned char *) buf, 0x10); | |
01c3a392 | 10705 | if (csum != le32_to_cpu(buf[0x10/4])) |
566f86ad MC |
10706 | goto out; |
10707 | ||
10708 | /* Manufacturing block starts at offset 0x74, checksum at 0xfc */ | |
10709 | csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88); | |
01c3a392 | 10710 | if (csum != le32_to_cpu(buf[0xfc/4])) |
a9dc529d | 10711 | goto out; |
566f86ad | 10712 | |
c3e94500 MC |
10713 | kfree(buf); |
10714 | ||
10715 | buf = tg3_vpd_readblock(tp); | |
10716 | if (!buf) | |
10717 | return -ENOMEM; | |
d4894f3e MC |
10718 | |
10719 | i = pci_vpd_find_tag((u8 *)buf, 0, TG3_NVM_VPD_LEN, | |
10720 | PCI_VPD_LRDT_RO_DATA); | |
10721 | if (i > 0) { | |
10722 | j = pci_vpd_lrdt_size(&((u8 *)buf)[i]); | |
10723 | if (j < 0) | |
10724 | goto out; | |
10725 | ||
10726 | if (i + PCI_VPD_LRDT_TAG_SIZE + j > TG3_NVM_VPD_LEN) | |
10727 | goto out; | |
10728 | ||
10729 | i += PCI_VPD_LRDT_TAG_SIZE; | |
10730 | j = pci_vpd_find_info_keyword((u8 *)buf, i, j, | |
10731 | PCI_VPD_RO_KEYWORD_CHKSUM); | |
10732 | if (j > 0) { | |
10733 | u8 csum8 = 0; | |
10734 | ||
10735 | j += PCI_VPD_INFO_FLD_HDR_SIZE; | |
10736 | ||
10737 | for (i = 0; i <= j; i++) | |
10738 | csum8 += ((u8 *)buf)[i]; | |
10739 | ||
10740 | if (csum8) | |
10741 | goto out; | |
10742 | } | |
10743 | } | |
10744 | ||
566f86ad MC |
10745 | err = 0; |
10746 | ||
10747 | out: | |
10748 | kfree(buf); | |
10749 | return err; | |
10750 | } | |
10751 | ||
ca43007a MC |
10752 | #define TG3_SERDES_TIMEOUT_SEC 2 |
10753 | #define TG3_COPPER_TIMEOUT_SEC 6 | |
10754 | ||
10755 | static int tg3_test_link(struct tg3 *tp) | |
10756 | { | |
10757 | int i, max; | |
10758 | ||
10759 | if (!netif_running(tp->dev)) | |
10760 | return -ENODEV; | |
10761 | ||
f07e9af3 | 10762 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) |
ca43007a MC |
10763 | max = TG3_SERDES_TIMEOUT_SEC; |
10764 | else | |
10765 | max = TG3_COPPER_TIMEOUT_SEC; | |
10766 | ||
10767 | for (i = 0; i < max; i++) { | |
10768 | if (netif_carrier_ok(tp->dev)) | |
10769 | return 0; | |
10770 | ||
10771 | if (msleep_interruptible(1000)) | |
10772 | break; | |
10773 | } | |
10774 | ||
10775 | return -EIO; | |
10776 | } | |
10777 | ||
a71116d1 | 10778 | /* Only test the commonly used registers */ |
30ca3e37 | 10779 | static int tg3_test_registers(struct tg3 *tp) |
a71116d1 | 10780 | { |
b16250e3 | 10781 | int i, is_5705, is_5750; |
a71116d1 MC |
10782 | u32 offset, read_mask, write_mask, val, save_val, read_val; |
10783 | static struct { | |
10784 | u16 offset; | |
10785 | u16 flags; | |
10786 | #define TG3_FL_5705 0x1 | |
10787 | #define TG3_FL_NOT_5705 0x2 | |
10788 | #define TG3_FL_NOT_5788 0x4 | |
b16250e3 | 10789 | #define TG3_FL_NOT_5750 0x8 |
a71116d1 MC |
10790 | u32 read_mask; |
10791 | u32 write_mask; | |
10792 | } reg_tbl[] = { | |
10793 | /* MAC Control Registers */ | |
10794 | { MAC_MODE, TG3_FL_NOT_5705, | |
10795 | 0x00000000, 0x00ef6f8c }, | |
10796 | { MAC_MODE, TG3_FL_5705, | |
10797 | 0x00000000, 0x01ef6b8c }, | |
10798 | { MAC_STATUS, TG3_FL_NOT_5705, | |
10799 | 0x03800107, 0x00000000 }, | |
10800 | { MAC_STATUS, TG3_FL_5705, | |
10801 | 0x03800100, 0x00000000 }, | |
10802 | { MAC_ADDR_0_HIGH, 0x0000, | |
10803 | 0x00000000, 0x0000ffff }, | |
10804 | { MAC_ADDR_0_LOW, 0x0000, | |
c6cdf436 | 10805 | 0x00000000, 0xffffffff }, |
a71116d1 MC |
10806 | { MAC_RX_MTU_SIZE, 0x0000, |
10807 | 0x00000000, 0x0000ffff }, | |
10808 | { MAC_TX_MODE, 0x0000, | |
10809 | 0x00000000, 0x00000070 }, | |
10810 | { MAC_TX_LENGTHS, 0x0000, | |
10811 | 0x00000000, 0x00003fff }, | |
10812 | { MAC_RX_MODE, TG3_FL_NOT_5705, | |
10813 | 0x00000000, 0x000007fc }, | |
10814 | { MAC_RX_MODE, TG3_FL_5705, | |
10815 | 0x00000000, 0x000007dc }, | |
10816 | { MAC_HASH_REG_0, 0x0000, | |
10817 | 0x00000000, 0xffffffff }, | |
10818 | { MAC_HASH_REG_1, 0x0000, | |
10819 | 0x00000000, 0xffffffff }, | |
10820 | { MAC_HASH_REG_2, 0x0000, | |
10821 | 0x00000000, 0xffffffff }, | |
10822 | { MAC_HASH_REG_3, 0x0000, | |
10823 | 0x00000000, 0xffffffff }, | |
10824 | ||
10825 | /* Receive Data and Receive BD Initiator Control Registers. */ | |
10826 | { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705, | |
10827 | 0x00000000, 0xffffffff }, | |
10828 | { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705, | |
10829 | 0x00000000, 0xffffffff }, | |
10830 | { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705, | |
10831 | 0x00000000, 0x00000003 }, | |
10832 | { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705, | |
10833 | 0x00000000, 0xffffffff }, | |
10834 | { RCVDBDI_STD_BD+0, 0x0000, | |
10835 | 0x00000000, 0xffffffff }, | |
10836 | { RCVDBDI_STD_BD+4, 0x0000, | |
10837 | 0x00000000, 0xffffffff }, | |
10838 | { RCVDBDI_STD_BD+8, 0x0000, | |
10839 | 0x00000000, 0xffff0002 }, | |
10840 | { RCVDBDI_STD_BD+0xc, 0x0000, | |
10841 | 0x00000000, 0xffffffff }, | |
6aa20a22 | 10842 | |
a71116d1 MC |
10843 | /* Receive BD Initiator Control Registers. */ |
10844 | { RCVBDI_STD_THRESH, TG3_FL_NOT_5705, | |
10845 | 0x00000000, 0xffffffff }, | |
10846 | { RCVBDI_STD_THRESH, TG3_FL_5705, | |
10847 | 0x00000000, 0x000003ff }, | |
10848 | { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705, | |
10849 | 0x00000000, 0xffffffff }, | |
6aa20a22 | 10850 | |
a71116d1 MC |
10851 | /* Host Coalescing Control Registers. */ |
10852 | { HOSTCC_MODE, TG3_FL_NOT_5705, | |
10853 | 0x00000000, 0x00000004 }, | |
10854 | { HOSTCC_MODE, TG3_FL_5705, | |
10855 | 0x00000000, 0x000000f6 }, | |
10856 | { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705, | |
10857 | 0x00000000, 0xffffffff }, | |
10858 | { HOSTCC_RXCOL_TICKS, TG3_FL_5705, | |
10859 | 0x00000000, 0x000003ff }, | |
10860 | { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705, | |
10861 | 0x00000000, 0xffffffff }, | |
10862 | { HOSTCC_TXCOL_TICKS, TG3_FL_5705, | |
10863 | 0x00000000, 0x000003ff }, | |
10864 | { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705, | |
10865 | 0x00000000, 0xffffffff }, | |
10866 | { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788, | |
10867 | 0x00000000, 0x000000ff }, | |
10868 | { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705, | |
10869 | 0x00000000, 0xffffffff }, | |
10870 | { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788, | |
10871 | 0x00000000, 0x000000ff }, | |
10872 | { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705, | |
10873 | 0x00000000, 0xffffffff }, | |
10874 | { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705, | |
10875 | 0x00000000, 0xffffffff }, | |
10876 | { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705, | |
10877 | 0x00000000, 0xffffffff }, | |
10878 | { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788, | |
10879 | 0x00000000, 0x000000ff }, | |
10880 | { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705, | |
10881 | 0x00000000, 0xffffffff }, | |
10882 | { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788, | |
10883 | 0x00000000, 0x000000ff }, | |
10884 | { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705, | |
10885 | 0x00000000, 0xffffffff }, | |
10886 | { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705, | |
10887 | 0x00000000, 0xffffffff }, | |
10888 | { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705, | |
10889 | 0x00000000, 0xffffffff }, | |
10890 | { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000, | |
10891 | 0x00000000, 0xffffffff }, | |
10892 | { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000, | |
10893 | 0x00000000, 0xffffffff }, | |
10894 | { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000, | |
10895 | 0xffffffff, 0x00000000 }, | |
10896 | { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000, | |
10897 | 0xffffffff, 0x00000000 }, | |
10898 | ||
10899 | /* Buffer Manager Control Registers. */ | |
b16250e3 | 10900 | { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750, |
a71116d1 | 10901 | 0x00000000, 0x007fff80 }, |
b16250e3 | 10902 | { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750, |
a71116d1 MC |
10903 | 0x00000000, 0x007fffff }, |
10904 | { BUFMGR_MB_RDMA_LOW_WATER, 0x0000, | |
10905 | 0x00000000, 0x0000003f }, | |
10906 | { BUFMGR_MB_MACRX_LOW_WATER, 0x0000, | |
10907 | 0x00000000, 0x000001ff }, | |
10908 | { BUFMGR_MB_HIGH_WATER, 0x0000, | |
10909 | 0x00000000, 0x000001ff }, | |
10910 | { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705, | |
10911 | 0xffffffff, 0x00000000 }, | |
10912 | { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705, | |
10913 | 0xffffffff, 0x00000000 }, | |
6aa20a22 | 10914 | |
a71116d1 MC |
10915 | /* Mailbox Registers */ |
10916 | { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000, | |
10917 | 0x00000000, 0x000001ff }, | |
10918 | { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705, | |
10919 | 0x00000000, 0x000001ff }, | |
10920 | { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000, | |
10921 | 0x00000000, 0x000007ff }, | |
10922 | { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000, | |
10923 | 0x00000000, 0x000001ff }, | |
10924 | ||
10925 | { 0xffff, 0x0000, 0x00000000, 0x00000000 }, | |
10926 | }; | |
10927 | ||
b16250e3 | 10928 | is_5705 = is_5750 = 0; |
63c3a66f | 10929 | if (tg3_flag(tp, 5705_PLUS)) { |
a71116d1 | 10930 | is_5705 = 1; |
63c3a66f | 10931 | if (tg3_flag(tp, 5750_PLUS)) |
b16250e3 MC |
10932 | is_5750 = 1; |
10933 | } | |
a71116d1 MC |
10934 | |
10935 | for (i = 0; reg_tbl[i].offset != 0xffff; i++) { | |
10936 | if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705)) | |
10937 | continue; | |
10938 | ||
10939 | if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705)) | |
10940 | continue; | |
10941 | ||
63c3a66f | 10942 | if (tg3_flag(tp, IS_5788) && |
a71116d1 MC |
10943 | (reg_tbl[i].flags & TG3_FL_NOT_5788)) |
10944 | continue; | |
10945 | ||
b16250e3 MC |
10946 | if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750)) |
10947 | continue; | |
10948 | ||
a71116d1 MC |
10949 | offset = (u32) reg_tbl[i].offset; |
10950 | read_mask = reg_tbl[i].read_mask; | |
10951 | write_mask = reg_tbl[i].write_mask; | |
10952 | ||
10953 | /* Save the original register content */ | |
10954 | save_val = tr32(offset); | |
10955 | ||
10956 | /* Determine the read-only value. */ | |
10957 | read_val = save_val & read_mask; | |
10958 | ||
10959 | /* Write zero to the register, then make sure the read-only bits | |
10960 | * are not changed and the read/write bits are all zeros. | |
10961 | */ | |
10962 | tw32(offset, 0); | |
10963 | ||
10964 | val = tr32(offset); | |
10965 | ||
10966 | /* Test the read-only and read/write bits. */ | |
10967 | if (((val & read_mask) != read_val) || (val & write_mask)) | |
10968 | goto out; | |
10969 | ||
10970 | /* Write ones to all the bits defined by RdMask and WrMask, then | |
10971 | * make sure the read-only bits are not changed and the | |
10972 | * read/write bits are all ones. | |
10973 | */ | |
10974 | tw32(offset, read_mask | write_mask); | |
10975 | ||
10976 | val = tr32(offset); | |
10977 | ||
10978 | /* Test the read-only bits. */ | |
10979 | if ((val & read_mask) != read_val) | |
10980 | goto out; | |
10981 | ||
10982 | /* Test the read/write bits. */ | |
10983 | if ((val & write_mask) != write_mask) | |
10984 | goto out; | |
10985 | ||
10986 | tw32(offset, save_val); | |
10987 | } | |
10988 | ||
10989 | return 0; | |
10990 | ||
10991 | out: | |
9f88f29f | 10992 | if (netif_msg_hw(tp)) |
2445e461 MC |
10993 | netdev_err(tp->dev, |
10994 | "Register test failed at offset %x\n", offset); | |
a71116d1 MC |
10995 | tw32(offset, save_val); |
10996 | return -EIO; | |
10997 | } | |
10998 | ||
7942e1db MC |
10999 | static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len) |
11000 | { | |
f71e1309 | 11001 | static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a }; |
7942e1db MC |
11002 | int i; |
11003 | u32 j; | |
11004 | ||
e9edda69 | 11005 | for (i = 0; i < ARRAY_SIZE(test_pattern); i++) { |
7942e1db MC |
11006 | for (j = 0; j < len; j += 4) { |
11007 | u32 val; | |
11008 | ||
11009 | tg3_write_mem(tp, offset + j, test_pattern[i]); | |
11010 | tg3_read_mem(tp, offset + j, &val); | |
11011 | if (val != test_pattern[i]) | |
11012 | return -EIO; | |
11013 | } | |
11014 | } | |
11015 | return 0; | |
11016 | } | |
11017 | ||
11018 | static int tg3_test_memory(struct tg3 *tp) | |
11019 | { | |
11020 | static struct mem_entry { | |
11021 | u32 offset; | |
11022 | u32 len; | |
11023 | } mem_tbl_570x[] = { | |
38690194 | 11024 | { 0x00000000, 0x00b50}, |
7942e1db MC |
11025 | { 0x00002000, 0x1c000}, |
11026 | { 0xffffffff, 0x00000} | |
11027 | }, mem_tbl_5705[] = { | |
11028 | { 0x00000100, 0x0000c}, | |
11029 | { 0x00000200, 0x00008}, | |
7942e1db MC |
11030 | { 0x00004000, 0x00800}, |
11031 | { 0x00006000, 0x01000}, | |
11032 | { 0x00008000, 0x02000}, | |
11033 | { 0x00010000, 0x0e000}, | |
11034 | { 0xffffffff, 0x00000} | |
79f4d13a MC |
11035 | }, mem_tbl_5755[] = { |
11036 | { 0x00000200, 0x00008}, | |
11037 | { 0x00004000, 0x00800}, | |
11038 | { 0x00006000, 0x00800}, | |
11039 | { 0x00008000, 0x02000}, | |
11040 | { 0x00010000, 0x0c000}, | |
11041 | { 0xffffffff, 0x00000} | |
b16250e3 MC |
11042 | }, mem_tbl_5906[] = { |
11043 | { 0x00000200, 0x00008}, | |
11044 | { 0x00004000, 0x00400}, | |
11045 | { 0x00006000, 0x00400}, | |
11046 | { 0x00008000, 0x01000}, | |
11047 | { 0x00010000, 0x01000}, | |
11048 | { 0xffffffff, 0x00000} | |
8b5a6c42 MC |
11049 | }, mem_tbl_5717[] = { |
11050 | { 0x00000200, 0x00008}, | |
11051 | { 0x00010000, 0x0a000}, | |
11052 | { 0x00020000, 0x13c00}, | |
11053 | { 0xffffffff, 0x00000} | |
11054 | }, mem_tbl_57765[] = { | |
11055 | { 0x00000200, 0x00008}, | |
11056 | { 0x00004000, 0x00800}, | |
11057 | { 0x00006000, 0x09800}, | |
11058 | { 0x00010000, 0x0a000}, | |
11059 | { 0xffffffff, 0x00000} | |
7942e1db MC |
11060 | }; |
11061 | struct mem_entry *mem_tbl; | |
11062 | int err = 0; | |
11063 | int i; | |
11064 | ||
63c3a66f | 11065 | if (tg3_flag(tp, 5717_PLUS)) |
8b5a6c42 MC |
11066 | mem_tbl = mem_tbl_5717; |
11067 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
11068 | mem_tbl = mem_tbl_57765; | |
63c3a66f | 11069 | else if (tg3_flag(tp, 5755_PLUS)) |
321d32a0 MC |
11070 | mem_tbl = mem_tbl_5755; |
11071 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
11072 | mem_tbl = mem_tbl_5906; | |
63c3a66f | 11073 | else if (tg3_flag(tp, 5705_PLUS)) |
321d32a0 MC |
11074 | mem_tbl = mem_tbl_5705; |
11075 | else | |
7942e1db MC |
11076 | mem_tbl = mem_tbl_570x; |
11077 | ||
11078 | for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) { | |
be98da6a MC |
11079 | err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len); |
11080 | if (err) | |
7942e1db MC |
11081 | break; |
11082 | } | |
6aa20a22 | 11083 | |
7942e1db MC |
11084 | return err; |
11085 | } | |
11086 | ||
9f40dead MC |
11087 | #define TG3_MAC_LOOPBACK 0 |
11088 | #define TG3_PHY_LOOPBACK 1 | |
bb158d69 MC |
11089 | #define TG3_TSO_LOOPBACK 2 |
11090 | ||
11091 | #define TG3_TSO_MSS 500 | |
11092 | ||
11093 | #define TG3_TSO_IP_HDR_LEN 20 | |
11094 | #define TG3_TSO_TCP_HDR_LEN 20 | |
11095 | #define TG3_TSO_TCP_OPT_LEN 12 | |
11096 | ||
11097 | static const u8 tg3_tso_header[] = { | |
11098 | 0x08, 0x00, | |
11099 | 0x45, 0x00, 0x00, 0x00, | |
11100 | 0x00, 0x00, 0x40, 0x00, | |
11101 | 0x40, 0x06, 0x00, 0x00, | |
11102 | 0x0a, 0x00, 0x00, 0x01, | |
11103 | 0x0a, 0x00, 0x00, 0x02, | |
11104 | 0x0d, 0x00, 0xe0, 0x00, | |
11105 | 0x00, 0x00, 0x01, 0x00, | |
11106 | 0x00, 0x00, 0x02, 0x00, | |
11107 | 0x80, 0x10, 0x10, 0x00, | |
11108 | 0x14, 0x09, 0x00, 0x00, | |
11109 | 0x01, 0x01, 0x08, 0x0a, | |
11110 | 0x11, 0x11, 0x11, 0x11, | |
11111 | 0x11, 0x11, 0x11, 0x11, | |
11112 | }; | |
9f40dead | 11113 | |
4852a861 | 11114 | static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, int loopback_mode) |
c76949a6 | 11115 | { |
9f40dead | 11116 | u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key; |
bb158d69 | 11117 | u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val; |
c76949a6 MC |
11118 | struct sk_buff *skb, *rx_skb; |
11119 | u8 *tx_data; | |
11120 | dma_addr_t map; | |
11121 | int num_pkts, tx_len, rx_len, i, err; | |
11122 | struct tg3_rx_buffer_desc *desc; | |
898a56f8 | 11123 | struct tg3_napi *tnapi, *rnapi; |
8fea32b9 | 11124 | struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; |
c76949a6 | 11125 | |
c8873405 MC |
11126 | tnapi = &tp->napi[0]; |
11127 | rnapi = &tp->napi[0]; | |
0c1d0e2b | 11128 | if (tp->irq_cnt > 1) { |
63c3a66f | 11129 | if (tg3_flag(tp, ENABLE_RSS)) |
1da85aa3 | 11130 | rnapi = &tp->napi[1]; |
63c3a66f | 11131 | if (tg3_flag(tp, ENABLE_TSS)) |
c8873405 | 11132 | tnapi = &tp->napi[1]; |
0c1d0e2b | 11133 | } |
fd2ce37f | 11134 | coal_now = tnapi->coal_now | rnapi->coal_now; |
898a56f8 | 11135 | |
9f40dead | 11136 | if (loopback_mode == TG3_MAC_LOOPBACK) { |
c94e3941 MC |
11137 | /* HW errata - mac loopback fails in some cases on 5780. |
11138 | * Normal traffic and PHY loopback are not affected by | |
aba49f24 MC |
11139 | * errata. Also, the MAC loopback test is deprecated for |
11140 | * all newer ASIC revisions. | |
c94e3941 | 11141 | */ |
aba49f24 | 11142 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 || |
63c3a66f | 11143 | tg3_flag(tp, CPMU_PRESENT)) |
c94e3941 MC |
11144 | return 0; |
11145 | ||
49692ca1 MC |
11146 | mac_mode = tp->mac_mode & |
11147 | ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); | |
11148 | mac_mode |= MAC_MODE_PORT_INT_LPBACK; | |
63c3a66f | 11149 | if (!tg3_flag(tp, 5705_PLUS)) |
e8f3f6ca | 11150 | mac_mode |= MAC_MODE_LINK_POLARITY; |
f07e9af3 | 11151 | if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) |
3f7045c1 MC |
11152 | mac_mode |= MAC_MODE_PORT_MODE_MII; |
11153 | else | |
11154 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
9f40dead | 11155 | tw32(MAC_MODE, mac_mode); |
bb158d69 | 11156 | } else { |
f07e9af3 | 11157 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
7f97a4bd | 11158 | tg3_phy_fet_toggle_apd(tp, false); |
5d64ad34 MC |
11159 | val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100; |
11160 | } else | |
11161 | val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000; | |
3f7045c1 | 11162 | |
9ef8ca99 MC |
11163 | tg3_phy_toggle_automdix(tp, 0); |
11164 | ||
3f7045c1 | 11165 | tg3_writephy(tp, MII_BMCR, val); |
c94e3941 | 11166 | udelay(40); |
5d64ad34 | 11167 | |
49692ca1 MC |
11168 | mac_mode = tp->mac_mode & |
11169 | ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); | |
f07e9af3 | 11170 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
1061b7c5 MC |
11171 | tg3_writephy(tp, MII_TG3_FET_PTEST, |
11172 | MII_TG3_FET_PTEST_FRC_TX_LINK | | |
11173 | MII_TG3_FET_PTEST_FRC_TX_LOCK); | |
11174 | /* The write needs to be flushed for the AC131 */ | |
11175 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
11176 | tg3_readphy(tp, MII_TG3_FET_PTEST, &val); | |
5d64ad34 MC |
11177 | mac_mode |= MAC_MODE_PORT_MODE_MII; |
11178 | } else | |
11179 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
b16250e3 | 11180 | |
c94e3941 | 11181 | /* reset to prevent losing 1st rx packet intermittently */ |
f07e9af3 | 11182 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { |
c94e3941 MC |
11183 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); |
11184 | udelay(10); | |
11185 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
11186 | } | |
e8f3f6ca | 11187 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) { |
79eb6904 MC |
11188 | u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK; |
11189 | if (masked_phy_id == TG3_PHY_ID_BCM5401) | |
e8f3f6ca | 11190 | mac_mode &= ~MAC_MODE_LINK_POLARITY; |
79eb6904 | 11191 | else if (masked_phy_id == TG3_PHY_ID_BCM5411) |
e8f3f6ca | 11192 | mac_mode |= MAC_MODE_LINK_POLARITY; |
ff18ff02 MC |
11193 | tg3_writephy(tp, MII_TG3_EXT_CTRL, |
11194 | MII_TG3_EXT_CTRL_LNK3_LED_MODE); | |
11195 | } | |
9f40dead | 11196 | tw32(MAC_MODE, mac_mode); |
49692ca1 MC |
11197 | |
11198 | /* Wait for link */ | |
11199 | for (i = 0; i < 100; i++) { | |
11200 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) | |
11201 | break; | |
11202 | mdelay(1); | |
11203 | } | |
859a5887 | 11204 | } |
c76949a6 MC |
11205 | |
11206 | err = -EIO; | |
11207 | ||
4852a861 | 11208 | tx_len = pktsz; |
a20e9c62 | 11209 | skb = netdev_alloc_skb(tp->dev, tx_len); |
a50bb7b9 JJ |
11210 | if (!skb) |
11211 | return -ENOMEM; | |
11212 | ||
c76949a6 MC |
11213 | tx_data = skb_put(skb, tx_len); |
11214 | memcpy(tx_data, tp->dev->dev_addr, 6); | |
11215 | memset(tx_data + 6, 0x0, 8); | |
11216 | ||
4852a861 | 11217 | tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN); |
c76949a6 | 11218 | |
bb158d69 MC |
11219 | if (loopback_mode == TG3_TSO_LOOPBACK) { |
11220 | struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN]; | |
11221 | ||
11222 | u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN + | |
11223 | TG3_TSO_TCP_OPT_LEN; | |
11224 | ||
11225 | memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header, | |
11226 | sizeof(tg3_tso_header)); | |
11227 | mss = TG3_TSO_MSS; | |
11228 | ||
11229 | val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header); | |
11230 | num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS); | |
11231 | ||
11232 | /* Set the total length field in the IP header */ | |
11233 | iph->tot_len = htons((u16)(mss + hdr_len)); | |
11234 | ||
11235 | base_flags = (TXD_FLAG_CPU_PRE_DMA | | |
11236 | TXD_FLAG_CPU_POST_DMA); | |
11237 | ||
63c3a66f JP |
11238 | if (tg3_flag(tp, HW_TSO_1) || |
11239 | tg3_flag(tp, HW_TSO_2) || | |
11240 | tg3_flag(tp, HW_TSO_3)) { | |
bb158d69 MC |
11241 | struct tcphdr *th; |
11242 | val = ETH_HLEN + TG3_TSO_IP_HDR_LEN; | |
11243 | th = (struct tcphdr *)&tx_data[val]; | |
11244 | th->check = 0; | |
11245 | } else | |
11246 | base_flags |= TXD_FLAG_TCPUDP_CSUM; | |
11247 | ||
63c3a66f | 11248 | if (tg3_flag(tp, HW_TSO_3)) { |
bb158d69 MC |
11249 | mss |= (hdr_len & 0xc) << 12; |
11250 | if (hdr_len & 0x10) | |
11251 | base_flags |= 0x00000010; | |
11252 | base_flags |= (hdr_len & 0x3e0) << 5; | |
63c3a66f | 11253 | } else if (tg3_flag(tp, HW_TSO_2)) |
bb158d69 | 11254 | mss |= hdr_len << 9; |
63c3a66f | 11255 | else if (tg3_flag(tp, HW_TSO_1) || |
bb158d69 MC |
11256 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { |
11257 | mss |= (TG3_TSO_TCP_OPT_LEN << 9); | |
11258 | } else { | |
11259 | base_flags |= (TG3_TSO_TCP_OPT_LEN << 10); | |
11260 | } | |
11261 | ||
11262 | data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header); | |
11263 | } else { | |
11264 | num_pkts = 1; | |
11265 | data_off = ETH_HLEN; | |
11266 | } | |
11267 | ||
11268 | for (i = data_off; i < tx_len; i++) | |
c76949a6 MC |
11269 | tx_data[i] = (u8) (i & 0xff); |
11270 | ||
f4188d8a AD |
11271 | map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE); |
11272 | if (pci_dma_mapping_error(tp->pdev, map)) { | |
a21771dd MC |
11273 | dev_kfree_skb(skb); |
11274 | return -EIO; | |
11275 | } | |
c76949a6 MC |
11276 | |
11277 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | | |
fd2ce37f | 11278 | rnapi->coal_now); |
c76949a6 MC |
11279 | |
11280 | udelay(10); | |
11281 | ||
898a56f8 | 11282 | rx_start_idx = rnapi->hw_status->idx[0].rx_producer; |
c76949a6 | 11283 | |
bb158d69 MC |
11284 | tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, |
11285 | base_flags, (mss << 1) | 1); | |
c76949a6 | 11286 | |
f3f3f27e | 11287 | tnapi->tx_prod++; |
c76949a6 | 11288 | |
f3f3f27e MC |
11289 | tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod); |
11290 | tr32_mailbox(tnapi->prodmbox); | |
c76949a6 MC |
11291 | |
11292 | udelay(10); | |
11293 | ||
303fc921 MC |
11294 | /* 350 usec to allow enough time on some 10/100 Mbps devices. */ |
11295 | for (i = 0; i < 35; i++) { | |
c76949a6 | 11296 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | |
fd2ce37f | 11297 | coal_now); |
c76949a6 MC |
11298 | |
11299 | udelay(10); | |
11300 | ||
898a56f8 MC |
11301 | tx_idx = tnapi->hw_status->idx[0].tx_consumer; |
11302 | rx_idx = rnapi->hw_status->idx[0].rx_producer; | |
f3f3f27e | 11303 | if ((tx_idx == tnapi->tx_prod) && |
c76949a6 MC |
11304 | (rx_idx == (rx_start_idx + num_pkts))) |
11305 | break; | |
11306 | } | |
11307 | ||
f4188d8a | 11308 | pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE); |
c76949a6 MC |
11309 | dev_kfree_skb(skb); |
11310 | ||
f3f3f27e | 11311 | if (tx_idx != tnapi->tx_prod) |
c76949a6 MC |
11312 | goto out; |
11313 | ||
11314 | if (rx_idx != rx_start_idx + num_pkts) | |
11315 | goto out; | |
11316 | ||
bb158d69 MC |
11317 | val = data_off; |
11318 | while (rx_idx != rx_start_idx) { | |
11319 | desc = &rnapi->rx_rcb[rx_start_idx++]; | |
11320 | desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; | |
11321 | opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; | |
c76949a6 | 11322 | |
bb158d69 MC |
11323 | if ((desc->err_vlan & RXD_ERR_MASK) != 0 && |
11324 | (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) | |
11325 | goto out; | |
c76949a6 | 11326 | |
bb158d69 MC |
11327 | rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) |
11328 | - ETH_FCS_LEN; | |
c76949a6 | 11329 | |
bb158d69 MC |
11330 | if (loopback_mode != TG3_TSO_LOOPBACK) { |
11331 | if (rx_len != tx_len) | |
11332 | goto out; | |
4852a861 | 11333 | |
bb158d69 MC |
11334 | if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) { |
11335 | if (opaque_key != RXD_OPAQUE_RING_STD) | |
11336 | goto out; | |
11337 | } else { | |
11338 | if (opaque_key != RXD_OPAQUE_RING_JUMBO) | |
11339 | goto out; | |
11340 | } | |
11341 | } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) && | |
11342 | (desc->ip_tcp_csum & RXD_TCPCSUM_MASK) | |
54e0a67f | 11343 | >> RXD_TCPCSUM_SHIFT != 0xffff) { |
4852a861 | 11344 | goto out; |
bb158d69 | 11345 | } |
4852a861 | 11346 | |
bb158d69 MC |
11347 | if (opaque_key == RXD_OPAQUE_RING_STD) { |
11348 | rx_skb = tpr->rx_std_buffers[desc_idx].skb; | |
11349 | map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], | |
11350 | mapping); | |
11351 | } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) { | |
11352 | rx_skb = tpr->rx_jmb_buffers[desc_idx].skb; | |
11353 | map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx], | |
11354 | mapping); | |
11355 | } else | |
11356 | goto out; | |
c76949a6 | 11357 | |
bb158d69 MC |
11358 | pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, |
11359 | PCI_DMA_FROMDEVICE); | |
c76949a6 | 11360 | |
bb158d69 MC |
11361 | for (i = data_off; i < rx_len; i++, val++) { |
11362 | if (*(rx_skb->data + i) != (u8) (val & 0xff)) | |
11363 | goto out; | |
11364 | } | |
c76949a6 | 11365 | } |
bb158d69 | 11366 | |
c76949a6 | 11367 | err = 0; |
6aa20a22 | 11368 | |
c76949a6 MC |
11369 | /* tg3_free_rings will unmap and free the rx_skb */ |
11370 | out: | |
11371 | return err; | |
11372 | } | |
11373 | ||
00c266b7 MC |
11374 | #define TG3_STD_LOOPBACK_FAILED 1 |
11375 | #define TG3_JMB_LOOPBACK_FAILED 2 | |
bb158d69 | 11376 | #define TG3_TSO_LOOPBACK_FAILED 4 |
00c266b7 MC |
11377 | |
11378 | #define TG3_MAC_LOOPBACK_SHIFT 0 | |
11379 | #define TG3_PHY_LOOPBACK_SHIFT 4 | |
bb158d69 | 11380 | #define TG3_LOOPBACK_FAILED 0x00000077 |
9f40dead MC |
11381 | |
11382 | static int tg3_test_loopback(struct tg3 *tp) | |
11383 | { | |
11384 | int err = 0; | |
ab789046 | 11385 | u32 eee_cap, cpmuctrl = 0; |
9f40dead MC |
11386 | |
11387 | if (!netif_running(tp->dev)) | |
11388 | return TG3_LOOPBACK_FAILED; | |
11389 | ||
ab789046 MC |
11390 | eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP; |
11391 | tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP; | |
11392 | ||
b9ec6c1b | 11393 | err = tg3_reset_hw(tp, 1); |
ab789046 MC |
11394 | if (err) { |
11395 | err = TG3_LOOPBACK_FAILED; | |
11396 | goto done; | |
11397 | } | |
9f40dead | 11398 | |
63c3a66f | 11399 | if (tg3_flag(tp, ENABLE_RSS)) { |
4a85f098 MC |
11400 | int i; |
11401 | ||
11402 | /* Reroute all rx packets to the 1st queue */ | |
11403 | for (i = MAC_RSS_INDIR_TBL_0; | |
11404 | i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4) | |
11405 | tw32(i, 0x0); | |
11406 | } | |
11407 | ||
6833c043 | 11408 | /* Turn off gphy autopowerdown. */ |
f07e9af3 | 11409 | if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) |
6833c043 MC |
11410 | tg3_phy_toggle_apd(tp, false); |
11411 | ||
63c3a66f | 11412 | if (tg3_flag(tp, CPMU_PRESENT)) { |
9936bcf6 MC |
11413 | int i; |
11414 | u32 status; | |
11415 | ||
11416 | tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER); | |
11417 | ||
11418 | /* Wait for up to 40 microseconds to acquire lock. */ | |
11419 | for (i = 0; i < 4; i++) { | |
11420 | status = tr32(TG3_CPMU_MUTEX_GNT); | |
11421 | if (status == CPMU_MUTEX_GNT_DRIVER) | |
11422 | break; | |
11423 | udelay(10); | |
11424 | } | |
11425 | ||
ab789046 MC |
11426 | if (status != CPMU_MUTEX_GNT_DRIVER) { |
11427 | err = TG3_LOOPBACK_FAILED; | |
11428 | goto done; | |
11429 | } | |
9936bcf6 | 11430 | |
b2a5c19c | 11431 | /* Turn off link-based power management. */ |
e875093c | 11432 | cpmuctrl = tr32(TG3_CPMU_CTRL); |
109115e1 MC |
11433 | tw32(TG3_CPMU_CTRL, |
11434 | cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE | | |
11435 | CPMU_CTRL_LINK_AWARE_MODE)); | |
9936bcf6 MC |
11436 | } |
11437 | ||
4852a861 | 11438 | if (tg3_run_loopback(tp, ETH_FRAME_LEN, TG3_MAC_LOOPBACK)) |
00c266b7 | 11439 | err |= TG3_STD_LOOPBACK_FAILED << TG3_MAC_LOOPBACK_SHIFT; |
9936bcf6 | 11440 | |
63c3a66f | 11441 | if (tg3_flag(tp, JUMBO_RING_ENABLE) && |
4852a861 | 11442 | tg3_run_loopback(tp, 9000 + ETH_HLEN, TG3_MAC_LOOPBACK)) |
00c266b7 | 11443 | err |= TG3_JMB_LOOPBACK_FAILED << TG3_MAC_LOOPBACK_SHIFT; |
4852a861 | 11444 | |
63c3a66f | 11445 | if (tg3_flag(tp, CPMU_PRESENT)) { |
9936bcf6 MC |
11446 | tw32(TG3_CPMU_CTRL, cpmuctrl); |
11447 | ||
11448 | /* Release the mutex */ | |
11449 | tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER); | |
11450 | } | |
11451 | ||
f07e9af3 | 11452 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
63c3a66f | 11453 | !tg3_flag(tp, USE_PHYLIB)) { |
4852a861 | 11454 | if (tg3_run_loopback(tp, ETH_FRAME_LEN, TG3_PHY_LOOPBACK)) |
00c266b7 MC |
11455 | err |= TG3_STD_LOOPBACK_FAILED << |
11456 | TG3_PHY_LOOPBACK_SHIFT; | |
63c3a66f | 11457 | if (tg3_flag(tp, TSO_CAPABLE) && |
bb158d69 MC |
11458 | tg3_run_loopback(tp, ETH_FRAME_LEN, TG3_TSO_LOOPBACK)) |
11459 | err |= TG3_TSO_LOOPBACK_FAILED << | |
11460 | TG3_PHY_LOOPBACK_SHIFT; | |
63c3a66f | 11461 | if (tg3_flag(tp, JUMBO_RING_ENABLE) && |
4852a861 | 11462 | tg3_run_loopback(tp, 9000 + ETH_HLEN, TG3_PHY_LOOPBACK)) |
00c266b7 MC |
11463 | err |= TG3_JMB_LOOPBACK_FAILED << |
11464 | TG3_PHY_LOOPBACK_SHIFT; | |
9f40dead MC |
11465 | } |
11466 | ||
6833c043 | 11467 | /* Re-enable gphy autopowerdown. */ |
f07e9af3 | 11468 | if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) |
6833c043 MC |
11469 | tg3_phy_toggle_apd(tp, true); |
11470 | ||
ab789046 MC |
11471 | done: |
11472 | tp->phy_flags |= eee_cap; | |
11473 | ||
9f40dead MC |
11474 | return err; |
11475 | } | |
11476 | ||
4cafd3f5 MC |
11477 | static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest, |
11478 | u64 *data) | |
11479 | { | |
566f86ad MC |
11480 | struct tg3 *tp = netdev_priv(dev); |
11481 | ||
bed9829f MC |
11482 | if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) && |
11483 | tg3_power_up(tp)) { | |
11484 | etest->flags |= ETH_TEST_FL_FAILED; | |
11485 | memset(data, 1, sizeof(u64) * TG3_NUM_TEST); | |
11486 | return; | |
11487 | } | |
bc1c7567 | 11488 | |
566f86ad MC |
11489 | memset(data, 0, sizeof(u64) * TG3_NUM_TEST); |
11490 | ||
11491 | if (tg3_test_nvram(tp) != 0) { | |
11492 | etest->flags |= ETH_TEST_FL_FAILED; | |
11493 | data[0] = 1; | |
11494 | } | |
ca43007a MC |
11495 | if (tg3_test_link(tp) != 0) { |
11496 | etest->flags |= ETH_TEST_FL_FAILED; | |
11497 | data[1] = 1; | |
11498 | } | |
a71116d1 | 11499 | if (etest->flags & ETH_TEST_FL_OFFLINE) { |
b02fd9e3 | 11500 | int err, err2 = 0, irq_sync = 0; |
bbe832c0 MC |
11501 | |
11502 | if (netif_running(dev)) { | |
b02fd9e3 | 11503 | tg3_phy_stop(tp); |
a71116d1 | 11504 | tg3_netif_stop(tp); |
bbe832c0 MC |
11505 | irq_sync = 1; |
11506 | } | |
a71116d1 | 11507 | |
bbe832c0 | 11508 | tg3_full_lock(tp, irq_sync); |
a71116d1 MC |
11509 | |
11510 | tg3_halt(tp, RESET_KIND_SUSPEND, 1); | |
ec41c7df | 11511 | err = tg3_nvram_lock(tp); |
a71116d1 | 11512 | tg3_halt_cpu(tp, RX_CPU_BASE); |
63c3a66f | 11513 | if (!tg3_flag(tp, 5705_PLUS)) |
a71116d1 | 11514 | tg3_halt_cpu(tp, TX_CPU_BASE); |
ec41c7df MC |
11515 | if (!err) |
11516 | tg3_nvram_unlock(tp); | |
a71116d1 | 11517 | |
f07e9af3 | 11518 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) |
d9ab5ad1 MC |
11519 | tg3_phy_reset(tp); |
11520 | ||
a71116d1 MC |
11521 | if (tg3_test_registers(tp) != 0) { |
11522 | etest->flags |= ETH_TEST_FL_FAILED; | |
11523 | data[2] = 1; | |
11524 | } | |
7942e1db MC |
11525 | if (tg3_test_memory(tp) != 0) { |
11526 | etest->flags |= ETH_TEST_FL_FAILED; | |
11527 | data[3] = 1; | |
11528 | } | |
9f40dead | 11529 | if ((data[4] = tg3_test_loopback(tp)) != 0) |
c76949a6 | 11530 | etest->flags |= ETH_TEST_FL_FAILED; |
a71116d1 | 11531 | |
f47c11ee DM |
11532 | tg3_full_unlock(tp); |
11533 | ||
d4bc3927 MC |
11534 | if (tg3_test_interrupt(tp) != 0) { |
11535 | etest->flags |= ETH_TEST_FL_FAILED; | |
11536 | data[5] = 1; | |
11537 | } | |
f47c11ee DM |
11538 | |
11539 | tg3_full_lock(tp, 0); | |
d4bc3927 | 11540 | |
a71116d1 MC |
11541 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
11542 | if (netif_running(dev)) { | |
63c3a66f | 11543 | tg3_flag_set(tp, INIT_COMPLETE); |
b02fd9e3 MC |
11544 | err2 = tg3_restart_hw(tp, 1); |
11545 | if (!err2) | |
b9ec6c1b | 11546 | tg3_netif_start(tp); |
a71116d1 | 11547 | } |
f47c11ee DM |
11548 | |
11549 | tg3_full_unlock(tp); | |
b02fd9e3 MC |
11550 | |
11551 | if (irq_sync && !err2) | |
11552 | tg3_phy_start(tp); | |
a71116d1 | 11553 | } |
80096068 | 11554 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
c866b7ea | 11555 | tg3_power_down(tp); |
bc1c7567 | 11556 | |
4cafd3f5 MC |
11557 | } |
11558 | ||
1da177e4 LT |
11559 | static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
11560 | { | |
11561 | struct mii_ioctl_data *data = if_mii(ifr); | |
11562 | struct tg3 *tp = netdev_priv(dev); | |
11563 | int err; | |
11564 | ||
63c3a66f | 11565 | if (tg3_flag(tp, USE_PHYLIB)) { |
3f0e3ad7 | 11566 | struct phy_device *phydev; |
f07e9af3 | 11567 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 | 11568 | return -EAGAIN; |
3f0e3ad7 | 11569 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
28b04113 | 11570 | return phy_mii_ioctl(phydev, ifr, cmd); |
b02fd9e3 MC |
11571 | } |
11572 | ||
33f401ae | 11573 | switch (cmd) { |
1da177e4 | 11574 | case SIOCGMIIPHY: |
882e9793 | 11575 | data->phy_id = tp->phy_addr; |
1da177e4 LT |
11576 | |
11577 | /* fallthru */ | |
11578 | case SIOCGMIIREG: { | |
11579 | u32 mii_regval; | |
11580 | ||
f07e9af3 | 11581 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
1da177e4 LT |
11582 | break; /* We have no PHY */ |
11583 | ||
34eea5ac | 11584 | if (!netif_running(dev)) |
bc1c7567 MC |
11585 | return -EAGAIN; |
11586 | ||
f47c11ee | 11587 | spin_lock_bh(&tp->lock); |
1da177e4 | 11588 | err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval); |
f47c11ee | 11589 | spin_unlock_bh(&tp->lock); |
1da177e4 LT |
11590 | |
11591 | data->val_out = mii_regval; | |
11592 | ||
11593 | return err; | |
11594 | } | |
11595 | ||
11596 | case SIOCSMIIREG: | |
f07e9af3 | 11597 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
1da177e4 LT |
11598 | break; /* We have no PHY */ |
11599 | ||
34eea5ac | 11600 | if (!netif_running(dev)) |
bc1c7567 MC |
11601 | return -EAGAIN; |
11602 | ||
f47c11ee | 11603 | spin_lock_bh(&tp->lock); |
1da177e4 | 11604 | err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in); |
f47c11ee | 11605 | spin_unlock_bh(&tp->lock); |
1da177e4 LT |
11606 | |
11607 | return err; | |
11608 | ||
11609 | default: | |
11610 | /* do nothing */ | |
11611 | break; | |
11612 | } | |
11613 | return -EOPNOTSUPP; | |
11614 | } | |
11615 | ||
15f9850d DM |
11616 | static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) |
11617 | { | |
11618 | struct tg3 *tp = netdev_priv(dev); | |
11619 | ||
11620 | memcpy(ec, &tp->coal, sizeof(*ec)); | |
11621 | return 0; | |
11622 | } | |
11623 | ||
d244c892 MC |
11624 | static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) |
11625 | { | |
11626 | struct tg3 *tp = netdev_priv(dev); | |
11627 | u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0; | |
11628 | u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0; | |
11629 | ||
63c3a66f | 11630 | if (!tg3_flag(tp, 5705_PLUS)) { |
d244c892 MC |
11631 | max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT; |
11632 | max_txcoal_tick_int = MAX_TXCOAL_TICK_INT; | |
11633 | max_stat_coal_ticks = MAX_STAT_COAL_TICKS; | |
11634 | min_stat_coal_ticks = MIN_STAT_COAL_TICKS; | |
11635 | } | |
11636 | ||
11637 | if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) || | |
11638 | (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) || | |
11639 | (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) || | |
11640 | (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) || | |
11641 | (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) || | |
11642 | (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) || | |
11643 | (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) || | |
11644 | (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) || | |
11645 | (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) || | |
11646 | (ec->stats_block_coalesce_usecs < min_stat_coal_ticks)) | |
11647 | return -EINVAL; | |
11648 | ||
11649 | /* No rx interrupts will be generated if both are zero */ | |
11650 | if ((ec->rx_coalesce_usecs == 0) && | |
11651 | (ec->rx_max_coalesced_frames == 0)) | |
11652 | return -EINVAL; | |
11653 | ||
11654 | /* No tx interrupts will be generated if both are zero */ | |
11655 | if ((ec->tx_coalesce_usecs == 0) && | |
11656 | (ec->tx_max_coalesced_frames == 0)) | |
11657 | return -EINVAL; | |
11658 | ||
11659 | /* Only copy relevant parameters, ignore all others. */ | |
11660 | tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs; | |
11661 | tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs; | |
11662 | tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames; | |
11663 | tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames; | |
11664 | tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq; | |
11665 | tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq; | |
11666 | tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq; | |
11667 | tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq; | |
11668 | tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs; | |
11669 | ||
11670 | if (netif_running(dev)) { | |
11671 | tg3_full_lock(tp, 0); | |
11672 | __tg3_set_coalesce(tp, &tp->coal); | |
11673 | tg3_full_unlock(tp); | |
11674 | } | |
11675 | return 0; | |
11676 | } | |
11677 | ||
7282d491 | 11678 | static const struct ethtool_ops tg3_ethtool_ops = { |
1da177e4 LT |
11679 | .get_settings = tg3_get_settings, |
11680 | .set_settings = tg3_set_settings, | |
11681 | .get_drvinfo = tg3_get_drvinfo, | |
11682 | .get_regs_len = tg3_get_regs_len, | |
11683 | .get_regs = tg3_get_regs, | |
11684 | .get_wol = tg3_get_wol, | |
11685 | .set_wol = tg3_set_wol, | |
11686 | .get_msglevel = tg3_get_msglevel, | |
11687 | .set_msglevel = tg3_set_msglevel, | |
11688 | .nway_reset = tg3_nway_reset, | |
11689 | .get_link = ethtool_op_get_link, | |
11690 | .get_eeprom_len = tg3_get_eeprom_len, | |
11691 | .get_eeprom = tg3_get_eeprom, | |
11692 | .set_eeprom = tg3_set_eeprom, | |
11693 | .get_ringparam = tg3_get_ringparam, | |
11694 | .set_ringparam = tg3_set_ringparam, | |
11695 | .get_pauseparam = tg3_get_pauseparam, | |
11696 | .set_pauseparam = tg3_set_pauseparam, | |
4cafd3f5 | 11697 | .self_test = tg3_self_test, |
1da177e4 | 11698 | .get_strings = tg3_get_strings, |
81b8709c | 11699 | .set_phys_id = tg3_set_phys_id, |
1da177e4 | 11700 | .get_ethtool_stats = tg3_get_ethtool_stats, |
15f9850d | 11701 | .get_coalesce = tg3_get_coalesce, |
d244c892 | 11702 | .set_coalesce = tg3_set_coalesce, |
b9f2c044 | 11703 | .get_sset_count = tg3_get_sset_count, |
1da177e4 LT |
11704 | }; |
11705 | ||
11706 | static void __devinit tg3_get_eeprom_size(struct tg3 *tp) | |
11707 | { | |
1b27777a | 11708 | u32 cursize, val, magic; |
1da177e4 LT |
11709 | |
11710 | tp->nvram_size = EEPROM_CHIP_SIZE; | |
11711 | ||
e4f34110 | 11712 | if (tg3_nvram_read(tp, 0, &magic) != 0) |
1da177e4 LT |
11713 | return; |
11714 | ||
b16250e3 MC |
11715 | if ((magic != TG3_EEPROM_MAGIC) && |
11716 | ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) && | |
11717 | ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW)) | |
1da177e4 LT |
11718 | return; |
11719 | ||
11720 | /* | |
11721 | * Size the chip by reading offsets at increasing powers of two. | |
11722 | * When we encounter our validation signature, we know the addressing | |
11723 | * has wrapped around, and thus have our chip size. | |
11724 | */ | |
1b27777a | 11725 | cursize = 0x10; |
1da177e4 LT |
11726 | |
11727 | while (cursize < tp->nvram_size) { | |
e4f34110 | 11728 | if (tg3_nvram_read(tp, cursize, &val) != 0) |
1da177e4 LT |
11729 | return; |
11730 | ||
1820180b | 11731 | if (val == magic) |
1da177e4 LT |
11732 | break; |
11733 | ||
11734 | cursize <<= 1; | |
11735 | } | |
11736 | ||
11737 | tp->nvram_size = cursize; | |
11738 | } | |
6aa20a22 | 11739 | |
1da177e4 LT |
11740 | static void __devinit tg3_get_nvram_size(struct tg3 *tp) |
11741 | { | |
11742 | u32 val; | |
11743 | ||
63c3a66f | 11744 | if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0) |
1b27777a MC |
11745 | return; |
11746 | ||
11747 | /* Selfboot format */ | |
1820180b | 11748 | if (val != TG3_EEPROM_MAGIC) { |
1b27777a MC |
11749 | tg3_get_eeprom_size(tp); |
11750 | return; | |
11751 | } | |
11752 | ||
6d348f2c | 11753 | if (tg3_nvram_read(tp, 0xf0, &val) == 0) { |
1da177e4 | 11754 | if (val != 0) { |
6d348f2c MC |
11755 | /* This is confusing. We want to operate on the |
11756 | * 16-bit value at offset 0xf2. The tg3_nvram_read() | |
11757 | * call will read from NVRAM and byteswap the data | |
11758 | * according to the byteswapping settings for all | |
11759 | * other register accesses. This ensures the data we | |
11760 | * want will always reside in the lower 16-bits. | |
11761 | * However, the data in NVRAM is in LE format, which | |
11762 | * means the data from the NVRAM read will always be | |
11763 | * opposite the endianness of the CPU. The 16-bit | |
11764 | * byteswap then brings the data to CPU endianness. | |
11765 | */ | |
11766 | tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024; | |
1da177e4 LT |
11767 | return; |
11768 | } | |
11769 | } | |
fd1122a2 | 11770 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; |
1da177e4 LT |
11771 | } |
11772 | ||
11773 | static void __devinit tg3_get_nvram_info(struct tg3 *tp) | |
11774 | { | |
11775 | u32 nvcfg1; | |
11776 | ||
11777 | nvcfg1 = tr32(NVRAM_CFG1); | |
11778 | if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) { | |
63c3a66f | 11779 | tg3_flag_set(tp, FLASH); |
8590a603 | 11780 | } else { |
1da177e4 LT |
11781 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; |
11782 | tw32(NVRAM_CFG1, nvcfg1); | |
11783 | } | |
11784 | ||
6ff6f81d | 11785 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || |
63c3a66f | 11786 | tg3_flag(tp, 5780_CLASS)) { |
1da177e4 | 11787 | switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) { |
8590a603 MC |
11788 | case FLASH_VENDOR_ATMEL_FLASH_BUFFERED: |
11789 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11790 | tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; | |
63c3a66f | 11791 | tg3_flag_set(tp, NVRAM_BUFFERED); |
8590a603 MC |
11792 | break; |
11793 | case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED: | |
11794 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11795 | tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE; | |
11796 | break; | |
11797 | case FLASH_VENDOR_ATMEL_EEPROM: | |
11798 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11799 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
63c3a66f | 11800 | tg3_flag_set(tp, NVRAM_BUFFERED); |
8590a603 MC |
11801 | break; |
11802 | case FLASH_VENDOR_ST: | |
11803 | tp->nvram_jedecnum = JEDEC_ST; | |
11804 | tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE; | |
63c3a66f | 11805 | tg3_flag_set(tp, NVRAM_BUFFERED); |
8590a603 MC |
11806 | break; |
11807 | case FLASH_VENDOR_SAIFUN: | |
11808 | tp->nvram_jedecnum = JEDEC_SAIFUN; | |
11809 | tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE; | |
11810 | break; | |
11811 | case FLASH_VENDOR_SST_SMALL: | |
11812 | case FLASH_VENDOR_SST_LARGE: | |
11813 | tp->nvram_jedecnum = JEDEC_SST; | |
11814 | tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE; | |
11815 | break; | |
1da177e4 | 11816 | } |
8590a603 | 11817 | } else { |
1da177e4 LT |
11818 | tp->nvram_jedecnum = JEDEC_ATMEL; |
11819 | tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; | |
63c3a66f | 11820 | tg3_flag_set(tp, NVRAM_BUFFERED); |
1da177e4 LT |
11821 | } |
11822 | } | |
11823 | ||
a1b950d5 MC |
11824 | static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1) |
11825 | { | |
11826 | switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) { | |
11827 | case FLASH_5752PAGE_SIZE_256: | |
11828 | tp->nvram_pagesize = 256; | |
11829 | break; | |
11830 | case FLASH_5752PAGE_SIZE_512: | |
11831 | tp->nvram_pagesize = 512; | |
11832 | break; | |
11833 | case FLASH_5752PAGE_SIZE_1K: | |
11834 | tp->nvram_pagesize = 1024; | |
11835 | break; | |
11836 | case FLASH_5752PAGE_SIZE_2K: | |
11837 | tp->nvram_pagesize = 2048; | |
11838 | break; | |
11839 | case FLASH_5752PAGE_SIZE_4K: | |
11840 | tp->nvram_pagesize = 4096; | |
11841 | break; | |
11842 | case FLASH_5752PAGE_SIZE_264: | |
11843 | tp->nvram_pagesize = 264; | |
11844 | break; | |
11845 | case FLASH_5752PAGE_SIZE_528: | |
11846 | tp->nvram_pagesize = 528; | |
11847 | break; | |
11848 | } | |
11849 | } | |
11850 | ||
361b4ac2 MC |
11851 | static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp) |
11852 | { | |
11853 | u32 nvcfg1; | |
11854 | ||
11855 | nvcfg1 = tr32(NVRAM_CFG1); | |
11856 | ||
e6af301b MC |
11857 | /* NVRAM protection for TPM */ |
11858 | if (nvcfg1 & (1 << 27)) | |
63c3a66f | 11859 | tg3_flag_set(tp, PROTECTED_NVRAM); |
e6af301b | 11860 | |
361b4ac2 | 11861 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { |
8590a603 MC |
11862 | case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ: |
11863 | case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ: | |
11864 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f | 11865 | tg3_flag_set(tp, NVRAM_BUFFERED); |
8590a603 MC |
11866 | break; |
11867 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
11868 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
11869 | tg3_flag_set(tp, NVRAM_BUFFERED); |
11870 | tg3_flag_set(tp, FLASH); | |
8590a603 MC |
11871 | break; |
11872 | case FLASH_5752VENDOR_ST_M45PE10: | |
11873 | case FLASH_5752VENDOR_ST_M45PE20: | |
11874 | case FLASH_5752VENDOR_ST_M45PE40: | |
11875 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
11876 | tg3_flag_set(tp, NVRAM_BUFFERED); |
11877 | tg3_flag_set(tp, FLASH); | |
8590a603 | 11878 | break; |
361b4ac2 MC |
11879 | } |
11880 | ||
63c3a66f | 11881 | if (tg3_flag(tp, FLASH)) { |
a1b950d5 | 11882 | tg3_nvram_get_pagesize(tp, nvcfg1); |
8590a603 | 11883 | } else { |
361b4ac2 MC |
11884 | /* For eeprom, set pagesize to maximum eeprom size */ |
11885 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
11886 | ||
11887 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
11888 | tw32(NVRAM_CFG1, nvcfg1); | |
11889 | } | |
11890 | } | |
11891 | ||
d3c7b886 MC |
11892 | static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp) |
11893 | { | |
989a9d23 | 11894 | u32 nvcfg1, protect = 0; |
d3c7b886 MC |
11895 | |
11896 | nvcfg1 = tr32(NVRAM_CFG1); | |
11897 | ||
11898 | /* NVRAM protection for TPM */ | |
989a9d23 | 11899 | if (nvcfg1 & (1 << 27)) { |
63c3a66f | 11900 | tg3_flag_set(tp, PROTECTED_NVRAM); |
989a9d23 MC |
11901 | protect = 1; |
11902 | } | |
d3c7b886 | 11903 | |
989a9d23 MC |
11904 | nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK; |
11905 | switch (nvcfg1) { | |
8590a603 MC |
11906 | case FLASH_5755VENDOR_ATMEL_FLASH_1: |
11907 | case FLASH_5755VENDOR_ATMEL_FLASH_2: | |
11908 | case FLASH_5755VENDOR_ATMEL_FLASH_3: | |
11909 | case FLASH_5755VENDOR_ATMEL_FLASH_5: | |
11910 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
11911 | tg3_flag_set(tp, NVRAM_BUFFERED); |
11912 | tg3_flag_set(tp, FLASH); | |
8590a603 MC |
11913 | tp->nvram_pagesize = 264; |
11914 | if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 || | |
11915 | nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5) | |
11916 | tp->nvram_size = (protect ? 0x3e200 : | |
11917 | TG3_NVRAM_SIZE_512KB); | |
11918 | else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2) | |
11919 | tp->nvram_size = (protect ? 0x1f200 : | |
11920 | TG3_NVRAM_SIZE_256KB); | |
11921 | else | |
11922 | tp->nvram_size = (protect ? 0x1f200 : | |
11923 | TG3_NVRAM_SIZE_128KB); | |
11924 | break; | |
11925 | case FLASH_5752VENDOR_ST_M45PE10: | |
11926 | case FLASH_5752VENDOR_ST_M45PE20: | |
11927 | case FLASH_5752VENDOR_ST_M45PE40: | |
11928 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
11929 | tg3_flag_set(tp, NVRAM_BUFFERED); |
11930 | tg3_flag_set(tp, FLASH); | |
8590a603 MC |
11931 | tp->nvram_pagesize = 256; |
11932 | if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10) | |
11933 | tp->nvram_size = (protect ? | |
11934 | TG3_NVRAM_SIZE_64KB : | |
11935 | TG3_NVRAM_SIZE_128KB); | |
11936 | else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20) | |
11937 | tp->nvram_size = (protect ? | |
11938 | TG3_NVRAM_SIZE_64KB : | |
11939 | TG3_NVRAM_SIZE_256KB); | |
11940 | else | |
11941 | tp->nvram_size = (protect ? | |
11942 | TG3_NVRAM_SIZE_128KB : | |
11943 | TG3_NVRAM_SIZE_512KB); | |
11944 | break; | |
d3c7b886 MC |
11945 | } |
11946 | } | |
11947 | ||
1b27777a MC |
11948 | static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp) |
11949 | { | |
11950 | u32 nvcfg1; | |
11951 | ||
11952 | nvcfg1 = tr32(NVRAM_CFG1); | |
11953 | ||
11954 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
8590a603 MC |
11955 | case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ: |
11956 | case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ: | |
11957 | case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ: | |
11958 | case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ: | |
11959 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f | 11960 | tg3_flag_set(tp, NVRAM_BUFFERED); |
8590a603 | 11961 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; |
1b27777a | 11962 | |
8590a603 MC |
11963 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; |
11964 | tw32(NVRAM_CFG1, nvcfg1); | |
11965 | break; | |
11966 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
11967 | case FLASH_5755VENDOR_ATMEL_FLASH_1: | |
11968 | case FLASH_5755VENDOR_ATMEL_FLASH_2: | |
11969 | case FLASH_5755VENDOR_ATMEL_FLASH_3: | |
11970 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
11971 | tg3_flag_set(tp, NVRAM_BUFFERED); |
11972 | tg3_flag_set(tp, FLASH); | |
8590a603 MC |
11973 | tp->nvram_pagesize = 264; |
11974 | break; | |
11975 | case FLASH_5752VENDOR_ST_M45PE10: | |
11976 | case FLASH_5752VENDOR_ST_M45PE20: | |
11977 | case FLASH_5752VENDOR_ST_M45PE40: | |
11978 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
11979 | tg3_flag_set(tp, NVRAM_BUFFERED); |
11980 | tg3_flag_set(tp, FLASH); | |
8590a603 MC |
11981 | tp->nvram_pagesize = 256; |
11982 | break; | |
1b27777a MC |
11983 | } |
11984 | } | |
11985 | ||
6b91fa02 MC |
11986 | static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp) |
11987 | { | |
11988 | u32 nvcfg1, protect = 0; | |
11989 | ||
11990 | nvcfg1 = tr32(NVRAM_CFG1); | |
11991 | ||
11992 | /* NVRAM protection for TPM */ | |
11993 | if (nvcfg1 & (1 << 27)) { | |
63c3a66f | 11994 | tg3_flag_set(tp, PROTECTED_NVRAM); |
6b91fa02 MC |
11995 | protect = 1; |
11996 | } | |
11997 | ||
11998 | nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK; | |
11999 | switch (nvcfg1) { | |
8590a603 MC |
12000 | case FLASH_5761VENDOR_ATMEL_ADB021D: |
12001 | case FLASH_5761VENDOR_ATMEL_ADB041D: | |
12002 | case FLASH_5761VENDOR_ATMEL_ADB081D: | |
12003 | case FLASH_5761VENDOR_ATMEL_ADB161D: | |
12004 | case FLASH_5761VENDOR_ATMEL_MDB021D: | |
12005 | case FLASH_5761VENDOR_ATMEL_MDB041D: | |
12006 | case FLASH_5761VENDOR_ATMEL_MDB081D: | |
12007 | case FLASH_5761VENDOR_ATMEL_MDB161D: | |
12008 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
12009 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12010 | tg3_flag_set(tp, FLASH); | |
12011 | tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); | |
8590a603 MC |
12012 | tp->nvram_pagesize = 256; |
12013 | break; | |
12014 | case FLASH_5761VENDOR_ST_A_M45PE20: | |
12015 | case FLASH_5761VENDOR_ST_A_M45PE40: | |
12016 | case FLASH_5761VENDOR_ST_A_M45PE80: | |
12017 | case FLASH_5761VENDOR_ST_A_M45PE16: | |
12018 | case FLASH_5761VENDOR_ST_M_M45PE20: | |
12019 | case FLASH_5761VENDOR_ST_M_M45PE40: | |
12020 | case FLASH_5761VENDOR_ST_M_M45PE80: | |
12021 | case FLASH_5761VENDOR_ST_M_M45PE16: | |
12022 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
12023 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12024 | tg3_flag_set(tp, FLASH); | |
8590a603 MC |
12025 | tp->nvram_pagesize = 256; |
12026 | break; | |
6b91fa02 MC |
12027 | } |
12028 | ||
12029 | if (protect) { | |
12030 | tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT); | |
12031 | } else { | |
12032 | switch (nvcfg1) { | |
8590a603 MC |
12033 | case FLASH_5761VENDOR_ATMEL_ADB161D: |
12034 | case FLASH_5761VENDOR_ATMEL_MDB161D: | |
12035 | case FLASH_5761VENDOR_ST_A_M45PE16: | |
12036 | case FLASH_5761VENDOR_ST_M_M45PE16: | |
12037 | tp->nvram_size = TG3_NVRAM_SIZE_2MB; | |
12038 | break; | |
12039 | case FLASH_5761VENDOR_ATMEL_ADB081D: | |
12040 | case FLASH_5761VENDOR_ATMEL_MDB081D: | |
12041 | case FLASH_5761VENDOR_ST_A_M45PE80: | |
12042 | case FLASH_5761VENDOR_ST_M_M45PE80: | |
12043 | tp->nvram_size = TG3_NVRAM_SIZE_1MB; | |
12044 | break; | |
12045 | case FLASH_5761VENDOR_ATMEL_ADB041D: | |
12046 | case FLASH_5761VENDOR_ATMEL_MDB041D: | |
12047 | case FLASH_5761VENDOR_ST_A_M45PE40: | |
12048 | case FLASH_5761VENDOR_ST_M_M45PE40: | |
12049 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
12050 | break; | |
12051 | case FLASH_5761VENDOR_ATMEL_ADB021D: | |
12052 | case FLASH_5761VENDOR_ATMEL_MDB021D: | |
12053 | case FLASH_5761VENDOR_ST_A_M45PE20: | |
12054 | case FLASH_5761VENDOR_ST_M_M45PE20: | |
12055 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12056 | break; | |
6b91fa02 MC |
12057 | } |
12058 | } | |
12059 | } | |
12060 | ||
b5d3772c MC |
12061 | static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp) |
12062 | { | |
12063 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f | 12064 | tg3_flag_set(tp, NVRAM_BUFFERED); |
b5d3772c MC |
12065 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; |
12066 | } | |
12067 | ||
321d32a0 MC |
12068 | static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp) |
12069 | { | |
12070 | u32 nvcfg1; | |
12071 | ||
12072 | nvcfg1 = tr32(NVRAM_CFG1); | |
12073 | ||
12074 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
12075 | case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ: | |
12076 | case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ: | |
12077 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f | 12078 | tg3_flag_set(tp, NVRAM_BUFFERED); |
321d32a0 MC |
12079 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; |
12080 | ||
12081 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
12082 | tw32(NVRAM_CFG1, nvcfg1); | |
12083 | return; | |
12084 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
12085 | case FLASH_57780VENDOR_ATMEL_AT45DB011D: | |
12086 | case FLASH_57780VENDOR_ATMEL_AT45DB011B: | |
12087 | case FLASH_57780VENDOR_ATMEL_AT45DB021D: | |
12088 | case FLASH_57780VENDOR_ATMEL_AT45DB021B: | |
12089 | case FLASH_57780VENDOR_ATMEL_AT45DB041D: | |
12090 | case FLASH_57780VENDOR_ATMEL_AT45DB041B: | |
12091 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
12092 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12093 | tg3_flag_set(tp, FLASH); | |
321d32a0 MC |
12094 | |
12095 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
12096 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
12097 | case FLASH_57780VENDOR_ATMEL_AT45DB011D: | |
12098 | case FLASH_57780VENDOR_ATMEL_AT45DB011B: | |
12099 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
12100 | break; | |
12101 | case FLASH_57780VENDOR_ATMEL_AT45DB021D: | |
12102 | case FLASH_57780VENDOR_ATMEL_AT45DB021B: | |
12103 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12104 | break; | |
12105 | case FLASH_57780VENDOR_ATMEL_AT45DB041D: | |
12106 | case FLASH_57780VENDOR_ATMEL_AT45DB041B: | |
12107 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
12108 | break; | |
12109 | } | |
12110 | break; | |
12111 | case FLASH_5752VENDOR_ST_M45PE10: | |
12112 | case FLASH_5752VENDOR_ST_M45PE20: | |
12113 | case FLASH_5752VENDOR_ST_M45PE40: | |
12114 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
12115 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12116 | tg3_flag_set(tp, FLASH); | |
321d32a0 MC |
12117 | |
12118 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
12119 | case FLASH_5752VENDOR_ST_M45PE10: | |
12120 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
12121 | break; | |
12122 | case FLASH_5752VENDOR_ST_M45PE20: | |
12123 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12124 | break; | |
12125 | case FLASH_5752VENDOR_ST_M45PE40: | |
12126 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
12127 | break; | |
12128 | } | |
12129 | break; | |
12130 | default: | |
63c3a66f | 12131 | tg3_flag_set(tp, NO_NVRAM); |
321d32a0 MC |
12132 | return; |
12133 | } | |
12134 | ||
a1b950d5 MC |
12135 | tg3_nvram_get_pagesize(tp, nvcfg1); |
12136 | if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) | |
63c3a66f | 12137 | tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); |
a1b950d5 MC |
12138 | } |
12139 | ||
12140 | ||
12141 | static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp) | |
12142 | { | |
12143 | u32 nvcfg1; | |
12144 | ||
12145 | nvcfg1 = tr32(NVRAM_CFG1); | |
12146 | ||
12147 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
12148 | case FLASH_5717VENDOR_ATMEL_EEPROM: | |
12149 | case FLASH_5717VENDOR_MICRO_EEPROM: | |
12150 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f | 12151 | tg3_flag_set(tp, NVRAM_BUFFERED); |
a1b950d5 MC |
12152 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; |
12153 | ||
12154 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
12155 | tw32(NVRAM_CFG1, nvcfg1); | |
12156 | return; | |
12157 | case FLASH_5717VENDOR_ATMEL_MDB011D: | |
12158 | case FLASH_5717VENDOR_ATMEL_ADB011B: | |
12159 | case FLASH_5717VENDOR_ATMEL_ADB011D: | |
12160 | case FLASH_5717VENDOR_ATMEL_MDB021D: | |
12161 | case FLASH_5717VENDOR_ATMEL_ADB021B: | |
12162 | case FLASH_5717VENDOR_ATMEL_ADB021D: | |
12163 | case FLASH_5717VENDOR_ATMEL_45USPT: | |
12164 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
12165 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12166 | tg3_flag_set(tp, FLASH); | |
a1b950d5 MC |
12167 | |
12168 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
12169 | case FLASH_5717VENDOR_ATMEL_MDB021D: | |
66ee33bf MC |
12170 | /* Detect size with tg3_nvram_get_size() */ |
12171 | break; | |
a1b950d5 MC |
12172 | case FLASH_5717VENDOR_ATMEL_ADB021B: |
12173 | case FLASH_5717VENDOR_ATMEL_ADB021D: | |
12174 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12175 | break; | |
12176 | default: | |
12177 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
12178 | break; | |
12179 | } | |
321d32a0 | 12180 | break; |
a1b950d5 MC |
12181 | case FLASH_5717VENDOR_ST_M_M25PE10: |
12182 | case FLASH_5717VENDOR_ST_A_M25PE10: | |
12183 | case FLASH_5717VENDOR_ST_M_M45PE10: | |
12184 | case FLASH_5717VENDOR_ST_A_M45PE10: | |
12185 | case FLASH_5717VENDOR_ST_M_M25PE20: | |
12186 | case FLASH_5717VENDOR_ST_A_M25PE20: | |
12187 | case FLASH_5717VENDOR_ST_M_M45PE20: | |
12188 | case FLASH_5717VENDOR_ST_A_M45PE20: | |
12189 | case FLASH_5717VENDOR_ST_25USPT: | |
12190 | case FLASH_5717VENDOR_ST_45USPT: | |
12191 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
12192 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12193 | tg3_flag_set(tp, FLASH); | |
a1b950d5 MC |
12194 | |
12195 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
12196 | case FLASH_5717VENDOR_ST_M_M25PE20: | |
a1b950d5 | 12197 | case FLASH_5717VENDOR_ST_M_M45PE20: |
66ee33bf MC |
12198 | /* Detect size with tg3_nvram_get_size() */ |
12199 | break; | |
12200 | case FLASH_5717VENDOR_ST_A_M25PE20: | |
a1b950d5 MC |
12201 | case FLASH_5717VENDOR_ST_A_M45PE20: |
12202 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12203 | break; | |
12204 | default: | |
12205 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
12206 | break; | |
12207 | } | |
321d32a0 | 12208 | break; |
a1b950d5 | 12209 | default: |
63c3a66f | 12210 | tg3_flag_set(tp, NO_NVRAM); |
a1b950d5 | 12211 | return; |
321d32a0 | 12212 | } |
a1b950d5 MC |
12213 | |
12214 | tg3_nvram_get_pagesize(tp, nvcfg1); | |
12215 | if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) | |
63c3a66f | 12216 | tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); |
321d32a0 MC |
12217 | } |
12218 | ||
9b91b5f1 MC |
12219 | static void __devinit tg3_get_5720_nvram_info(struct tg3 *tp) |
12220 | { | |
12221 | u32 nvcfg1, nvmpinstrp; | |
12222 | ||
12223 | nvcfg1 = tr32(NVRAM_CFG1); | |
12224 | nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK; | |
12225 | ||
12226 | switch (nvmpinstrp) { | |
12227 | case FLASH_5720_EEPROM_HD: | |
12228 | case FLASH_5720_EEPROM_LD: | |
12229 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f | 12230 | tg3_flag_set(tp, NVRAM_BUFFERED); |
9b91b5f1 MC |
12231 | |
12232 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
12233 | tw32(NVRAM_CFG1, nvcfg1); | |
12234 | if (nvmpinstrp == FLASH_5720_EEPROM_HD) | |
12235 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
12236 | else | |
12237 | tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE; | |
12238 | return; | |
12239 | case FLASH_5720VENDOR_M_ATMEL_DB011D: | |
12240 | case FLASH_5720VENDOR_A_ATMEL_DB011B: | |
12241 | case FLASH_5720VENDOR_A_ATMEL_DB011D: | |
12242 | case FLASH_5720VENDOR_M_ATMEL_DB021D: | |
12243 | case FLASH_5720VENDOR_A_ATMEL_DB021B: | |
12244 | case FLASH_5720VENDOR_A_ATMEL_DB021D: | |
12245 | case FLASH_5720VENDOR_M_ATMEL_DB041D: | |
12246 | case FLASH_5720VENDOR_A_ATMEL_DB041B: | |
12247 | case FLASH_5720VENDOR_A_ATMEL_DB041D: | |
12248 | case FLASH_5720VENDOR_M_ATMEL_DB081D: | |
12249 | case FLASH_5720VENDOR_A_ATMEL_DB081D: | |
12250 | case FLASH_5720VENDOR_ATMEL_45USPT: | |
12251 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
12252 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12253 | tg3_flag_set(tp, FLASH); | |
9b91b5f1 MC |
12254 | |
12255 | switch (nvmpinstrp) { | |
12256 | case FLASH_5720VENDOR_M_ATMEL_DB021D: | |
12257 | case FLASH_5720VENDOR_A_ATMEL_DB021B: | |
12258 | case FLASH_5720VENDOR_A_ATMEL_DB021D: | |
12259 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12260 | break; | |
12261 | case FLASH_5720VENDOR_M_ATMEL_DB041D: | |
12262 | case FLASH_5720VENDOR_A_ATMEL_DB041B: | |
12263 | case FLASH_5720VENDOR_A_ATMEL_DB041D: | |
12264 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
12265 | break; | |
12266 | case FLASH_5720VENDOR_M_ATMEL_DB081D: | |
12267 | case FLASH_5720VENDOR_A_ATMEL_DB081D: | |
12268 | tp->nvram_size = TG3_NVRAM_SIZE_1MB; | |
12269 | break; | |
12270 | default: | |
12271 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
12272 | break; | |
12273 | } | |
12274 | break; | |
12275 | case FLASH_5720VENDOR_M_ST_M25PE10: | |
12276 | case FLASH_5720VENDOR_M_ST_M45PE10: | |
12277 | case FLASH_5720VENDOR_A_ST_M25PE10: | |
12278 | case FLASH_5720VENDOR_A_ST_M45PE10: | |
12279 | case FLASH_5720VENDOR_M_ST_M25PE20: | |
12280 | case FLASH_5720VENDOR_M_ST_M45PE20: | |
12281 | case FLASH_5720VENDOR_A_ST_M25PE20: | |
12282 | case FLASH_5720VENDOR_A_ST_M45PE20: | |
12283 | case FLASH_5720VENDOR_M_ST_M25PE40: | |
12284 | case FLASH_5720VENDOR_M_ST_M45PE40: | |
12285 | case FLASH_5720VENDOR_A_ST_M25PE40: | |
12286 | case FLASH_5720VENDOR_A_ST_M45PE40: | |
12287 | case FLASH_5720VENDOR_M_ST_M25PE80: | |
12288 | case FLASH_5720VENDOR_M_ST_M45PE80: | |
12289 | case FLASH_5720VENDOR_A_ST_M25PE80: | |
12290 | case FLASH_5720VENDOR_A_ST_M45PE80: | |
12291 | case FLASH_5720VENDOR_ST_25USPT: | |
12292 | case FLASH_5720VENDOR_ST_45USPT: | |
12293 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
12294 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12295 | tg3_flag_set(tp, FLASH); | |
9b91b5f1 MC |
12296 | |
12297 | switch (nvmpinstrp) { | |
12298 | case FLASH_5720VENDOR_M_ST_M25PE20: | |
12299 | case FLASH_5720VENDOR_M_ST_M45PE20: | |
12300 | case FLASH_5720VENDOR_A_ST_M25PE20: | |
12301 | case FLASH_5720VENDOR_A_ST_M45PE20: | |
12302 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12303 | break; | |
12304 | case FLASH_5720VENDOR_M_ST_M25PE40: | |
12305 | case FLASH_5720VENDOR_M_ST_M45PE40: | |
12306 | case FLASH_5720VENDOR_A_ST_M25PE40: | |
12307 | case FLASH_5720VENDOR_A_ST_M45PE40: | |
12308 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
12309 | break; | |
12310 | case FLASH_5720VENDOR_M_ST_M25PE80: | |
12311 | case FLASH_5720VENDOR_M_ST_M45PE80: | |
12312 | case FLASH_5720VENDOR_A_ST_M25PE80: | |
12313 | case FLASH_5720VENDOR_A_ST_M45PE80: | |
12314 | tp->nvram_size = TG3_NVRAM_SIZE_1MB; | |
12315 | break; | |
12316 | default: | |
12317 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
12318 | break; | |
12319 | } | |
12320 | break; | |
12321 | default: | |
63c3a66f | 12322 | tg3_flag_set(tp, NO_NVRAM); |
9b91b5f1 MC |
12323 | return; |
12324 | } | |
12325 | ||
12326 | tg3_nvram_get_pagesize(tp, nvcfg1); | |
12327 | if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) | |
63c3a66f | 12328 | tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); |
9b91b5f1 MC |
12329 | } |
12330 | ||
1da177e4 LT |
12331 | /* Chips other than 5700/5701 use the NVRAM for fetching info. */ |
12332 | static void __devinit tg3_nvram_init(struct tg3 *tp) | |
12333 | { | |
1da177e4 LT |
12334 | tw32_f(GRC_EEPROM_ADDR, |
12335 | (EEPROM_ADDR_FSM_RESET | | |
12336 | (EEPROM_DEFAULT_CLOCK_PERIOD << | |
12337 | EEPROM_ADDR_CLKPERD_SHIFT))); | |
12338 | ||
9d57f01c | 12339 | msleep(1); |
1da177e4 LT |
12340 | |
12341 | /* Enable seeprom accesses. */ | |
12342 | tw32_f(GRC_LOCAL_CTRL, | |
12343 | tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM); | |
12344 | udelay(100); | |
12345 | ||
12346 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
12347 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) { | |
63c3a66f | 12348 | tg3_flag_set(tp, NVRAM); |
1da177e4 | 12349 | |
ec41c7df | 12350 | if (tg3_nvram_lock(tp)) { |
5129c3a3 MC |
12351 | netdev_warn(tp->dev, |
12352 | "Cannot get nvram lock, %s failed\n", | |
05dbe005 | 12353 | __func__); |
ec41c7df MC |
12354 | return; |
12355 | } | |
e6af301b | 12356 | tg3_enable_nvram_access(tp); |
1da177e4 | 12357 | |
989a9d23 MC |
12358 | tp->nvram_size = 0; |
12359 | ||
361b4ac2 MC |
12360 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) |
12361 | tg3_get_5752_nvram_info(tp); | |
d3c7b886 MC |
12362 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) |
12363 | tg3_get_5755_nvram_info(tp); | |
d30cdd28 | 12364 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || |
57e6983c MC |
12365 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
12366 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
1b27777a | 12367 | tg3_get_5787_nvram_info(tp); |
6b91fa02 MC |
12368 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) |
12369 | tg3_get_5761_nvram_info(tp); | |
b5d3772c MC |
12370 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
12371 | tg3_get_5906_nvram_info(tp); | |
b703df6f MC |
12372 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
12373 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
321d32a0 | 12374 | tg3_get_57780_nvram_info(tp); |
9b91b5f1 MC |
12375 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
12376 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | |
a1b950d5 | 12377 | tg3_get_5717_nvram_info(tp); |
9b91b5f1 MC |
12378 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) |
12379 | tg3_get_5720_nvram_info(tp); | |
361b4ac2 MC |
12380 | else |
12381 | tg3_get_nvram_info(tp); | |
12382 | ||
989a9d23 MC |
12383 | if (tp->nvram_size == 0) |
12384 | tg3_get_nvram_size(tp); | |
1da177e4 | 12385 | |
e6af301b | 12386 | tg3_disable_nvram_access(tp); |
381291b7 | 12387 | tg3_nvram_unlock(tp); |
1da177e4 LT |
12388 | |
12389 | } else { | |
63c3a66f JP |
12390 | tg3_flag_clear(tp, NVRAM); |
12391 | tg3_flag_clear(tp, NVRAM_BUFFERED); | |
1da177e4 LT |
12392 | |
12393 | tg3_get_eeprom_size(tp); | |
12394 | } | |
12395 | } | |
12396 | ||
1da177e4 LT |
12397 | static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp, |
12398 | u32 offset, u32 len, u8 *buf) | |
12399 | { | |
12400 | int i, j, rc = 0; | |
12401 | u32 val; | |
12402 | ||
12403 | for (i = 0; i < len; i += 4) { | |
b9fc7dc5 | 12404 | u32 addr; |
a9dc529d | 12405 | __be32 data; |
1da177e4 LT |
12406 | |
12407 | addr = offset + i; | |
12408 | ||
12409 | memcpy(&data, buf + i, 4); | |
12410 | ||
62cedd11 MC |
12411 | /* |
12412 | * The SEEPROM interface expects the data to always be opposite | |
12413 | * the native endian format. We accomplish this by reversing | |
12414 | * all the operations that would have been performed on the | |
12415 | * data from a call to tg3_nvram_read_be32(). | |
12416 | */ | |
12417 | tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data))); | |
1da177e4 LT |
12418 | |
12419 | val = tr32(GRC_EEPROM_ADDR); | |
12420 | tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE); | |
12421 | ||
12422 | val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK | | |
12423 | EEPROM_ADDR_READ); | |
12424 | tw32(GRC_EEPROM_ADDR, val | | |
12425 | (0 << EEPROM_ADDR_DEVID_SHIFT) | | |
12426 | (addr & EEPROM_ADDR_ADDR_MASK) | | |
12427 | EEPROM_ADDR_START | | |
12428 | EEPROM_ADDR_WRITE); | |
6aa20a22 | 12429 | |
9d57f01c | 12430 | for (j = 0; j < 1000; j++) { |
1da177e4 LT |
12431 | val = tr32(GRC_EEPROM_ADDR); |
12432 | ||
12433 | if (val & EEPROM_ADDR_COMPLETE) | |
12434 | break; | |
9d57f01c | 12435 | msleep(1); |
1da177e4 LT |
12436 | } |
12437 | if (!(val & EEPROM_ADDR_COMPLETE)) { | |
12438 | rc = -EBUSY; | |
12439 | break; | |
12440 | } | |
12441 | } | |
12442 | ||
12443 | return rc; | |
12444 | } | |
12445 | ||
12446 | /* offset and length are dword aligned */ | |
12447 | static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len, | |
12448 | u8 *buf) | |
12449 | { | |
12450 | int ret = 0; | |
12451 | u32 pagesize = tp->nvram_pagesize; | |
12452 | u32 pagemask = pagesize - 1; | |
12453 | u32 nvram_cmd; | |
12454 | u8 *tmp; | |
12455 | ||
12456 | tmp = kmalloc(pagesize, GFP_KERNEL); | |
12457 | if (tmp == NULL) | |
12458 | return -ENOMEM; | |
12459 | ||
12460 | while (len) { | |
12461 | int j; | |
e6af301b | 12462 | u32 phy_addr, page_off, size; |
1da177e4 LT |
12463 | |
12464 | phy_addr = offset & ~pagemask; | |
6aa20a22 | 12465 | |
1da177e4 | 12466 | for (j = 0; j < pagesize; j += 4) { |
a9dc529d MC |
12467 | ret = tg3_nvram_read_be32(tp, phy_addr + j, |
12468 | (__be32 *) (tmp + j)); | |
12469 | if (ret) | |
1da177e4 LT |
12470 | break; |
12471 | } | |
12472 | if (ret) | |
12473 | break; | |
12474 | ||
c6cdf436 | 12475 | page_off = offset & pagemask; |
1da177e4 LT |
12476 | size = pagesize; |
12477 | if (len < size) | |
12478 | size = len; | |
12479 | ||
12480 | len -= size; | |
12481 | ||
12482 | memcpy(tmp + page_off, buf, size); | |
12483 | ||
12484 | offset = offset + (pagesize - page_off); | |
12485 | ||
e6af301b | 12486 | tg3_enable_nvram_access(tp); |
1da177e4 LT |
12487 | |
12488 | /* | |
12489 | * Before we can erase the flash page, we need | |
12490 | * to issue a special "write enable" command. | |
12491 | */ | |
12492 | nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
12493 | ||
12494 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) | |
12495 | break; | |
12496 | ||
12497 | /* Erase the target page */ | |
12498 | tw32(NVRAM_ADDR, phy_addr); | |
12499 | ||
12500 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR | | |
12501 | NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE; | |
12502 | ||
c6cdf436 | 12503 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) |
1da177e4 LT |
12504 | break; |
12505 | ||
12506 | /* Issue another write enable to start the write. */ | |
12507 | nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
12508 | ||
12509 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) | |
12510 | break; | |
12511 | ||
12512 | for (j = 0; j < pagesize; j += 4) { | |
b9fc7dc5 | 12513 | __be32 data; |
1da177e4 | 12514 | |
b9fc7dc5 | 12515 | data = *((__be32 *) (tmp + j)); |
a9dc529d | 12516 | |
b9fc7dc5 | 12517 | tw32(NVRAM_WRDATA, be32_to_cpu(data)); |
1da177e4 LT |
12518 | |
12519 | tw32(NVRAM_ADDR, phy_addr + j); | |
12520 | ||
12521 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | | |
12522 | NVRAM_CMD_WR; | |
12523 | ||
12524 | if (j == 0) | |
12525 | nvram_cmd |= NVRAM_CMD_FIRST; | |
12526 | else if (j == (pagesize - 4)) | |
12527 | nvram_cmd |= NVRAM_CMD_LAST; | |
12528 | ||
12529 | if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd))) | |
12530 | break; | |
12531 | } | |
12532 | if (ret) | |
12533 | break; | |
12534 | } | |
12535 | ||
12536 | nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
12537 | tg3_nvram_exec_cmd(tp, nvram_cmd); | |
12538 | ||
12539 | kfree(tmp); | |
12540 | ||
12541 | return ret; | |
12542 | } | |
12543 | ||
12544 | /* offset and length are dword aligned */ | |
12545 | static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len, | |
12546 | u8 *buf) | |
12547 | { | |
12548 | int i, ret = 0; | |
12549 | ||
12550 | for (i = 0; i < len; i += 4, offset += 4) { | |
b9fc7dc5 AV |
12551 | u32 page_off, phy_addr, nvram_cmd; |
12552 | __be32 data; | |
1da177e4 LT |
12553 | |
12554 | memcpy(&data, buf + i, 4); | |
b9fc7dc5 | 12555 | tw32(NVRAM_WRDATA, be32_to_cpu(data)); |
1da177e4 | 12556 | |
c6cdf436 | 12557 | page_off = offset % tp->nvram_pagesize; |
1da177e4 | 12558 | |
1820180b | 12559 | phy_addr = tg3_nvram_phys_addr(tp, offset); |
1da177e4 LT |
12560 | |
12561 | tw32(NVRAM_ADDR, phy_addr); | |
12562 | ||
12563 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR; | |
12564 | ||
c6cdf436 | 12565 | if (page_off == 0 || i == 0) |
1da177e4 | 12566 | nvram_cmd |= NVRAM_CMD_FIRST; |
f6d9a256 | 12567 | if (page_off == (tp->nvram_pagesize - 4)) |
1da177e4 LT |
12568 | nvram_cmd |= NVRAM_CMD_LAST; |
12569 | ||
12570 | if (i == (len - 4)) | |
12571 | nvram_cmd |= NVRAM_CMD_LAST; | |
12572 | ||
321d32a0 | 12573 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 && |
63c3a66f | 12574 | !tg3_flag(tp, 5755_PLUS) && |
4c987487 MC |
12575 | (tp->nvram_jedecnum == JEDEC_ST) && |
12576 | (nvram_cmd & NVRAM_CMD_FIRST)) { | |
1da177e4 LT |
12577 | |
12578 | if ((ret = tg3_nvram_exec_cmd(tp, | |
12579 | NVRAM_CMD_WREN | NVRAM_CMD_GO | | |
12580 | NVRAM_CMD_DONE))) | |
12581 | ||
12582 | break; | |
12583 | } | |
63c3a66f | 12584 | if (!tg3_flag(tp, FLASH)) { |
1da177e4 LT |
12585 | /* We always do complete word writes to eeprom. */ |
12586 | nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST); | |
12587 | } | |
12588 | ||
12589 | if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd))) | |
12590 | break; | |
12591 | } | |
12592 | return ret; | |
12593 | } | |
12594 | ||
12595 | /* offset and length are dword aligned */ | |
12596 | static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf) | |
12597 | { | |
12598 | int ret; | |
12599 | ||
63c3a66f | 12600 | if (tg3_flag(tp, EEPROM_WRITE_PROT)) { |
314fba34 MC |
12601 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl & |
12602 | ~GRC_LCLCTRL_GPIO_OUTPUT1); | |
1da177e4 LT |
12603 | udelay(40); |
12604 | } | |
12605 | ||
63c3a66f | 12606 | if (!tg3_flag(tp, NVRAM)) { |
1da177e4 | 12607 | ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf); |
859a5887 | 12608 | } else { |
1da177e4 LT |
12609 | u32 grc_mode; |
12610 | ||
ec41c7df MC |
12611 | ret = tg3_nvram_lock(tp); |
12612 | if (ret) | |
12613 | return ret; | |
1da177e4 | 12614 | |
e6af301b | 12615 | tg3_enable_nvram_access(tp); |
63c3a66f | 12616 | if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) |
1da177e4 | 12617 | tw32(NVRAM_WRITE1, 0x406); |
1da177e4 LT |
12618 | |
12619 | grc_mode = tr32(GRC_MODE); | |
12620 | tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE); | |
12621 | ||
63c3a66f | 12622 | if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) { |
1da177e4 LT |
12623 | ret = tg3_nvram_write_block_buffered(tp, offset, len, |
12624 | buf); | |
859a5887 | 12625 | } else { |
1da177e4 LT |
12626 | ret = tg3_nvram_write_block_unbuffered(tp, offset, len, |
12627 | buf); | |
12628 | } | |
12629 | ||
12630 | grc_mode = tr32(GRC_MODE); | |
12631 | tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE); | |
12632 | ||
e6af301b | 12633 | tg3_disable_nvram_access(tp); |
1da177e4 LT |
12634 | tg3_nvram_unlock(tp); |
12635 | } | |
12636 | ||
63c3a66f | 12637 | if (tg3_flag(tp, EEPROM_WRITE_PROT)) { |
314fba34 | 12638 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); |
1da177e4 LT |
12639 | udelay(40); |
12640 | } | |
12641 | ||
12642 | return ret; | |
12643 | } | |
12644 | ||
12645 | struct subsys_tbl_ent { | |
12646 | u16 subsys_vendor, subsys_devid; | |
12647 | u32 phy_id; | |
12648 | }; | |
12649 | ||
24daf2b0 | 12650 | static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = { |
1da177e4 | 12651 | /* Broadcom boards. */ |
24daf2b0 | 12652 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12653 | TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 }, |
24daf2b0 | 12654 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12655 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12656 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12657 | TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 }, |
24daf2b0 MC |
12658 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
12659 | TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 }, | |
12660 | { TG3PCI_SUBVENDOR_ID_BROADCOM, | |
79eb6904 | 12661 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12662 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12663 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 }, |
24daf2b0 MC |
12664 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
12665 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 }, | |
12666 | { TG3PCI_SUBVENDOR_ID_BROADCOM, | |
79eb6904 | 12667 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12668 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12669 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12670 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12671 | TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 }, |
24daf2b0 | 12672 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12673 | TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 }, |
1da177e4 LT |
12674 | |
12675 | /* 3com boards. */ | |
24daf2b0 | 12676 | { TG3PCI_SUBVENDOR_ID_3COM, |
79eb6904 | 12677 | TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 }, |
24daf2b0 | 12678 | { TG3PCI_SUBVENDOR_ID_3COM, |
79eb6904 | 12679 | TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 }, |
24daf2b0 MC |
12680 | { TG3PCI_SUBVENDOR_ID_3COM, |
12681 | TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 }, | |
12682 | { TG3PCI_SUBVENDOR_ID_3COM, | |
79eb6904 | 12683 | TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12684 | { TG3PCI_SUBVENDOR_ID_3COM, |
79eb6904 | 12685 | TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 }, |
1da177e4 LT |
12686 | |
12687 | /* DELL boards. */ | |
24daf2b0 | 12688 | { TG3PCI_SUBVENDOR_ID_DELL, |
79eb6904 | 12689 | TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 }, |
24daf2b0 | 12690 | { TG3PCI_SUBVENDOR_ID_DELL, |
79eb6904 | 12691 | TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 }, |
24daf2b0 | 12692 | { TG3PCI_SUBVENDOR_ID_DELL, |
79eb6904 | 12693 | TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 }, |
24daf2b0 | 12694 | { TG3PCI_SUBVENDOR_ID_DELL, |
79eb6904 | 12695 | TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 }, |
1da177e4 LT |
12696 | |
12697 | /* Compaq boards. */ | |
24daf2b0 | 12698 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
79eb6904 | 12699 | TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12700 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
79eb6904 | 12701 | TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 }, |
24daf2b0 MC |
12702 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
12703 | TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 }, | |
12704 | { TG3PCI_SUBVENDOR_ID_COMPAQ, | |
79eb6904 | 12705 | TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12706 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
79eb6904 | 12707 | TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 }, |
1da177e4 LT |
12708 | |
12709 | /* IBM boards. */ | |
24daf2b0 MC |
12710 | { TG3PCI_SUBVENDOR_ID_IBM, |
12711 | TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 } | |
1da177e4 LT |
12712 | }; |
12713 | ||
24daf2b0 | 12714 | static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp) |
1da177e4 LT |
12715 | { |
12716 | int i; | |
12717 | ||
12718 | for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) { | |
12719 | if ((subsys_id_to_phy_id[i].subsys_vendor == | |
12720 | tp->pdev->subsystem_vendor) && | |
12721 | (subsys_id_to_phy_id[i].subsys_devid == | |
12722 | tp->pdev->subsystem_device)) | |
12723 | return &subsys_id_to_phy_id[i]; | |
12724 | } | |
12725 | return NULL; | |
12726 | } | |
12727 | ||
7d0c41ef | 12728 | static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp) |
1da177e4 | 12729 | { |
1da177e4 | 12730 | u32 val; |
f49639e6 | 12731 | |
79eb6904 | 12732 | tp->phy_id = TG3_PHY_ID_INVALID; |
7d0c41ef MC |
12733 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; |
12734 | ||
a85feb8c | 12735 | /* Assume an onboard device and WOL capable by default. */ |
63c3a66f JP |
12736 | tg3_flag_set(tp, EEPROM_WRITE_PROT); |
12737 | tg3_flag_set(tp, WOL_CAP); | |
72b845e0 | 12738 | |
b5d3772c | 12739 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
9d26e213 | 12740 | if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) { |
63c3a66f JP |
12741 | tg3_flag_clear(tp, EEPROM_WRITE_PROT); |
12742 | tg3_flag_set(tp, IS_NIC); | |
9d26e213 | 12743 | } |
0527ba35 MC |
12744 | val = tr32(VCPU_CFGSHDW); |
12745 | if (val & VCPU_CFGSHDW_ASPM_DBNC) | |
63c3a66f | 12746 | tg3_flag_set(tp, ASPM_WORKAROUND); |
0527ba35 | 12747 | if ((val & VCPU_CFGSHDW_WOL_ENABLE) && |
6fdbab9d | 12748 | (val & VCPU_CFGSHDW_WOL_MAGPKT)) { |
63c3a66f | 12749 | tg3_flag_set(tp, WOL_ENABLE); |
6fdbab9d RW |
12750 | device_set_wakeup_enable(&tp->pdev->dev, true); |
12751 | } | |
05ac4cb7 | 12752 | goto done; |
b5d3772c MC |
12753 | } |
12754 | ||
1da177e4 LT |
12755 | tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); |
12756 | if (val == NIC_SRAM_DATA_SIG_MAGIC) { | |
12757 | u32 nic_cfg, led_cfg; | |
a9daf367 | 12758 | u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id; |
7d0c41ef | 12759 | int eeprom_phy_serdes = 0; |
1da177e4 LT |
12760 | |
12761 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); | |
12762 | tp->nic_sram_data_cfg = nic_cfg; | |
12763 | ||
12764 | tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver); | |
12765 | ver >>= NIC_SRAM_DATA_VER_SHIFT; | |
6ff6f81d MC |
12766 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && |
12767 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 && | |
12768 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703 && | |
1da177e4 LT |
12769 | (ver > 0) && (ver < 0x100)) |
12770 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2); | |
12771 | ||
a9daf367 MC |
12772 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) |
12773 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4); | |
12774 | ||
1da177e4 LT |
12775 | if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) == |
12776 | NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER) | |
12777 | eeprom_phy_serdes = 1; | |
12778 | ||
12779 | tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id); | |
12780 | if (nic_phy_id != 0) { | |
12781 | u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK; | |
12782 | u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK; | |
12783 | ||
12784 | eeprom_phy_id = (id1 >> 16) << 10; | |
12785 | eeprom_phy_id |= (id2 & 0xfc00) << 16; | |
12786 | eeprom_phy_id |= (id2 & 0x03ff) << 0; | |
12787 | } else | |
12788 | eeprom_phy_id = 0; | |
12789 | ||
7d0c41ef | 12790 | tp->phy_id = eeprom_phy_id; |
747e8f8b | 12791 | if (eeprom_phy_serdes) { |
63c3a66f | 12792 | if (!tg3_flag(tp, 5705_PLUS)) |
f07e9af3 | 12793 | tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; |
a50d0796 | 12794 | else |
f07e9af3 | 12795 | tp->phy_flags |= TG3_PHYFLG_MII_SERDES; |
747e8f8b | 12796 | } |
7d0c41ef | 12797 | |
63c3a66f | 12798 | if (tg3_flag(tp, 5750_PLUS)) |
1da177e4 LT |
12799 | led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK | |
12800 | SHASTA_EXT_LED_MODE_MASK); | |
cbf46853 | 12801 | else |
1da177e4 LT |
12802 | led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK; |
12803 | ||
12804 | switch (led_cfg) { | |
12805 | default: | |
12806 | case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1: | |
12807 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
12808 | break; | |
12809 | ||
12810 | case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2: | |
12811 | tp->led_ctrl = LED_CTRL_MODE_PHY_2; | |
12812 | break; | |
12813 | ||
12814 | case NIC_SRAM_DATA_CFG_LED_MODE_MAC: | |
12815 | tp->led_ctrl = LED_CTRL_MODE_MAC; | |
9ba27794 MC |
12816 | |
12817 | /* Default to PHY_1_MODE if 0 (MAC_MODE) is | |
12818 | * read on some older 5700/5701 bootcode. | |
12819 | */ | |
12820 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | |
12821 | ASIC_REV_5700 || | |
12822 | GET_ASIC_REV(tp->pci_chip_rev_id) == | |
12823 | ASIC_REV_5701) | |
12824 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
12825 | ||
1da177e4 LT |
12826 | break; |
12827 | ||
12828 | case SHASTA_EXT_LED_SHARED: | |
12829 | tp->led_ctrl = LED_CTRL_MODE_SHARED; | |
12830 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 && | |
12831 | tp->pci_chip_rev_id != CHIPREV_ID_5750_A1) | |
12832 | tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | | |
12833 | LED_CTRL_MODE_PHY_2); | |
12834 | break; | |
12835 | ||
12836 | case SHASTA_EXT_LED_MAC: | |
12837 | tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC; | |
12838 | break; | |
12839 | ||
12840 | case SHASTA_EXT_LED_COMBO: | |
12841 | tp->led_ctrl = LED_CTRL_MODE_COMBO; | |
12842 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) | |
12843 | tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | | |
12844 | LED_CTRL_MODE_PHY_2); | |
12845 | break; | |
12846 | ||
855e1111 | 12847 | } |
1da177e4 LT |
12848 | |
12849 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
12850 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) && | |
12851 | tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL) | |
12852 | tp->led_ctrl = LED_CTRL_MODE_PHY_2; | |
12853 | ||
b2a5c19c MC |
12854 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) |
12855 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
5f60891b | 12856 | |
9d26e213 | 12857 | if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) { |
63c3a66f | 12858 | tg3_flag_set(tp, EEPROM_WRITE_PROT); |
9d26e213 MC |
12859 | if ((tp->pdev->subsystem_vendor == |
12860 | PCI_VENDOR_ID_ARIMA) && | |
12861 | (tp->pdev->subsystem_device == 0x205a || | |
12862 | tp->pdev->subsystem_device == 0x2063)) | |
63c3a66f | 12863 | tg3_flag_clear(tp, EEPROM_WRITE_PROT); |
9d26e213 | 12864 | } else { |
63c3a66f JP |
12865 | tg3_flag_clear(tp, EEPROM_WRITE_PROT); |
12866 | tg3_flag_set(tp, IS_NIC); | |
9d26e213 | 12867 | } |
1da177e4 LT |
12868 | |
12869 | if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) { | |
63c3a66f JP |
12870 | tg3_flag_set(tp, ENABLE_ASF); |
12871 | if (tg3_flag(tp, 5750_PLUS)) | |
12872 | tg3_flag_set(tp, ASF_NEW_HANDSHAKE); | |
1da177e4 | 12873 | } |
b2b98d4a MC |
12874 | |
12875 | if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) && | |
63c3a66f JP |
12876 | tg3_flag(tp, 5750_PLUS)) |
12877 | tg3_flag_set(tp, ENABLE_APE); | |
b2b98d4a | 12878 | |
f07e9af3 | 12879 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES && |
a85feb8c | 12880 | !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)) |
63c3a66f | 12881 | tg3_flag_clear(tp, WOL_CAP); |
1da177e4 | 12882 | |
63c3a66f | 12883 | if (tg3_flag(tp, WOL_CAP) && |
6fdbab9d | 12884 | (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) { |
63c3a66f | 12885 | tg3_flag_set(tp, WOL_ENABLE); |
6fdbab9d RW |
12886 | device_set_wakeup_enable(&tp->pdev->dev, true); |
12887 | } | |
0527ba35 | 12888 | |
1da177e4 | 12889 | if (cfg2 & (1 << 17)) |
f07e9af3 | 12890 | tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING; |
1da177e4 LT |
12891 | |
12892 | /* serdes signal pre-emphasis in register 0x590 set by */ | |
12893 | /* bootcode if bit 18 is set */ | |
12894 | if (cfg2 & (1 << 18)) | |
f07e9af3 | 12895 | tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS; |
8ed5d97e | 12896 | |
63c3a66f JP |
12897 | if ((tg3_flag(tp, 57765_PLUS) || |
12898 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && | |
12899 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) && | |
6833c043 | 12900 | (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN)) |
f07e9af3 | 12901 | tp->phy_flags |= TG3_PHYFLG_ENABLE_APD; |
6833c043 | 12902 | |
63c3a66f | 12903 | if (tg3_flag(tp, PCI_EXPRESS) && |
8c69b1e7 | 12904 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && |
63c3a66f | 12905 | !tg3_flag(tp, 57765_PLUS)) { |
8ed5d97e MC |
12906 | u32 cfg3; |
12907 | ||
12908 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3); | |
12909 | if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE) | |
63c3a66f | 12910 | tg3_flag_set(tp, ASPM_WORKAROUND); |
8ed5d97e | 12911 | } |
a9daf367 | 12912 | |
14417063 | 12913 | if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE) |
63c3a66f | 12914 | tg3_flag_set(tp, RGMII_INBAND_DISABLE); |
a9daf367 | 12915 | if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN) |
63c3a66f | 12916 | tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN); |
a9daf367 | 12917 | if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN) |
63c3a66f | 12918 | tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN); |
1da177e4 | 12919 | } |
05ac4cb7 | 12920 | done: |
63c3a66f | 12921 | if (tg3_flag(tp, WOL_CAP)) |
43067ed8 | 12922 | device_set_wakeup_enable(&tp->pdev->dev, |
63c3a66f | 12923 | tg3_flag(tp, WOL_ENABLE)); |
43067ed8 RW |
12924 | else |
12925 | device_set_wakeup_capable(&tp->pdev->dev, false); | |
7d0c41ef MC |
12926 | } |
12927 | ||
b2a5c19c MC |
12928 | static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd) |
12929 | { | |
12930 | int i; | |
12931 | u32 val; | |
12932 | ||
12933 | tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START); | |
12934 | tw32(OTP_CTRL, cmd); | |
12935 | ||
12936 | /* Wait for up to 1 ms for command to execute. */ | |
12937 | for (i = 0; i < 100; i++) { | |
12938 | val = tr32(OTP_STATUS); | |
12939 | if (val & OTP_STATUS_CMD_DONE) | |
12940 | break; | |
12941 | udelay(10); | |
12942 | } | |
12943 | ||
12944 | return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY; | |
12945 | } | |
12946 | ||
12947 | /* Read the gphy configuration from the OTP region of the chip. The gphy | |
12948 | * configuration is a 32-bit value that straddles the alignment boundary. | |
12949 | * We do two 32-bit reads and then shift and merge the results. | |
12950 | */ | |
12951 | static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp) | |
12952 | { | |
12953 | u32 bhalf_otp, thalf_otp; | |
12954 | ||
12955 | tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC); | |
12956 | ||
12957 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT)) | |
12958 | return 0; | |
12959 | ||
12960 | tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1); | |
12961 | ||
12962 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) | |
12963 | return 0; | |
12964 | ||
12965 | thalf_otp = tr32(OTP_READ_DATA); | |
12966 | ||
12967 | tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2); | |
12968 | ||
12969 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) | |
12970 | return 0; | |
12971 | ||
12972 | bhalf_otp = tr32(OTP_READ_DATA); | |
12973 | ||
12974 | return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16); | |
12975 | } | |
12976 | ||
e256f8a3 MC |
12977 | static void __devinit tg3_phy_init_link_config(struct tg3 *tp) |
12978 | { | |
12979 | u32 adv = ADVERTISED_Autoneg | | |
12980 | ADVERTISED_Pause; | |
12981 | ||
12982 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) | |
12983 | adv |= ADVERTISED_1000baseT_Half | | |
12984 | ADVERTISED_1000baseT_Full; | |
12985 | ||
12986 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) | |
12987 | adv |= ADVERTISED_100baseT_Half | | |
12988 | ADVERTISED_100baseT_Full | | |
12989 | ADVERTISED_10baseT_Half | | |
12990 | ADVERTISED_10baseT_Full | | |
12991 | ADVERTISED_TP; | |
12992 | else | |
12993 | adv |= ADVERTISED_FIBRE; | |
12994 | ||
12995 | tp->link_config.advertising = adv; | |
12996 | tp->link_config.speed = SPEED_INVALID; | |
12997 | tp->link_config.duplex = DUPLEX_INVALID; | |
12998 | tp->link_config.autoneg = AUTONEG_ENABLE; | |
12999 | tp->link_config.active_speed = SPEED_INVALID; | |
13000 | tp->link_config.active_duplex = DUPLEX_INVALID; | |
13001 | tp->link_config.orig_speed = SPEED_INVALID; | |
13002 | tp->link_config.orig_duplex = DUPLEX_INVALID; | |
13003 | tp->link_config.orig_autoneg = AUTONEG_INVALID; | |
13004 | } | |
13005 | ||
7d0c41ef MC |
13006 | static int __devinit tg3_phy_probe(struct tg3 *tp) |
13007 | { | |
13008 | u32 hw_phy_id_1, hw_phy_id_2; | |
13009 | u32 hw_phy_id, hw_phy_id_masked; | |
13010 | int err; | |
1da177e4 | 13011 | |
e256f8a3 | 13012 | /* flow control autonegotiation is default behavior */ |
63c3a66f | 13013 | tg3_flag_set(tp, PAUSE_AUTONEG); |
e256f8a3 MC |
13014 | tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; |
13015 | ||
63c3a66f | 13016 | if (tg3_flag(tp, USE_PHYLIB)) |
b02fd9e3 MC |
13017 | return tg3_phy_init(tp); |
13018 | ||
1da177e4 | 13019 | /* Reading the PHY ID register can conflict with ASF |
877d0310 | 13020 | * firmware access to the PHY hardware. |
1da177e4 LT |
13021 | */ |
13022 | err = 0; | |
63c3a66f | 13023 | if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) { |
79eb6904 | 13024 | hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID; |
1da177e4 LT |
13025 | } else { |
13026 | /* Now read the physical PHY_ID from the chip and verify | |
13027 | * that it is sane. If it doesn't look good, we fall back | |
13028 | * to either the hard-coded table based PHY_ID and failing | |
13029 | * that the value found in the eeprom area. | |
13030 | */ | |
13031 | err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1); | |
13032 | err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2); | |
13033 | ||
13034 | hw_phy_id = (hw_phy_id_1 & 0xffff) << 10; | |
13035 | hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16; | |
13036 | hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0; | |
13037 | ||
79eb6904 | 13038 | hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK; |
1da177e4 LT |
13039 | } |
13040 | ||
79eb6904 | 13041 | if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) { |
1da177e4 | 13042 | tp->phy_id = hw_phy_id; |
79eb6904 | 13043 | if (hw_phy_id_masked == TG3_PHY_ID_BCM8002) |
f07e9af3 | 13044 | tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; |
da6b2d01 | 13045 | else |
f07e9af3 | 13046 | tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES; |
1da177e4 | 13047 | } else { |
79eb6904 | 13048 | if (tp->phy_id != TG3_PHY_ID_INVALID) { |
7d0c41ef MC |
13049 | /* Do nothing, phy ID already set up in |
13050 | * tg3_get_eeprom_hw_cfg(). | |
13051 | */ | |
1da177e4 LT |
13052 | } else { |
13053 | struct subsys_tbl_ent *p; | |
13054 | ||
13055 | /* No eeprom signature? Try the hardcoded | |
13056 | * subsys device table. | |
13057 | */ | |
24daf2b0 | 13058 | p = tg3_lookup_by_subsys(tp); |
1da177e4 LT |
13059 | if (!p) |
13060 | return -ENODEV; | |
13061 | ||
13062 | tp->phy_id = p->phy_id; | |
13063 | if (!tp->phy_id || | |
79eb6904 | 13064 | tp->phy_id == TG3_PHY_ID_BCM8002) |
f07e9af3 | 13065 | tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; |
1da177e4 LT |
13066 | } |
13067 | } | |
13068 | ||
a6b68dab MC |
13069 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && |
13070 | ((tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 && | |
13071 | tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) || | |
13072 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 && | |
13073 | tp->pci_chip_rev_id != CHIPREV_ID_57765_A0))) | |
52b02d04 MC |
13074 | tp->phy_flags |= TG3_PHYFLG_EEE_CAP; |
13075 | ||
e256f8a3 MC |
13076 | tg3_phy_init_link_config(tp); |
13077 | ||
f07e9af3 | 13078 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && |
63c3a66f JP |
13079 | !tg3_flag(tp, ENABLE_APE) && |
13080 | !tg3_flag(tp, ENABLE_ASF)) { | |
42b64a45 | 13081 | u32 bmsr, mask; |
1da177e4 LT |
13082 | |
13083 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
13084 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
13085 | (bmsr & BMSR_LSTATUS)) | |
13086 | goto skip_phy_reset; | |
6aa20a22 | 13087 | |
1da177e4 LT |
13088 | err = tg3_phy_reset(tp); |
13089 | if (err) | |
13090 | return err; | |
13091 | ||
42b64a45 | 13092 | tg3_phy_set_wirespeed(tp); |
1da177e4 | 13093 | |
3600d918 MC |
13094 | mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | |
13095 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | | |
13096 | ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full); | |
13097 | if (!tg3_copper_is_advertising_all(tp, mask)) { | |
42b64a45 MC |
13098 | tg3_phy_autoneg_cfg(tp, tp->link_config.advertising, |
13099 | tp->link_config.flowctrl); | |
1da177e4 LT |
13100 | |
13101 | tg3_writephy(tp, MII_BMCR, | |
13102 | BMCR_ANENABLE | BMCR_ANRESTART); | |
13103 | } | |
1da177e4 LT |
13104 | } |
13105 | ||
13106 | skip_phy_reset: | |
79eb6904 | 13107 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { |
1da177e4 LT |
13108 | err = tg3_init_5401phy_dsp(tp); |
13109 | if (err) | |
13110 | return err; | |
1da177e4 | 13111 | |
1da177e4 LT |
13112 | err = tg3_init_5401phy_dsp(tp); |
13113 | } | |
13114 | ||
1da177e4 LT |
13115 | return err; |
13116 | } | |
13117 | ||
184b8904 | 13118 | static void __devinit tg3_read_vpd(struct tg3 *tp) |
1da177e4 | 13119 | { |
a4a8bb15 | 13120 | u8 *vpd_data; |
4181b2c8 | 13121 | unsigned int block_end, rosize, len; |
184b8904 | 13122 | int j, i = 0; |
a4a8bb15 | 13123 | |
c3e94500 | 13124 | vpd_data = (u8 *)tg3_vpd_readblock(tp); |
a4a8bb15 MC |
13125 | if (!vpd_data) |
13126 | goto out_no_vpd; | |
1da177e4 | 13127 | |
4181b2c8 MC |
13128 | i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN, |
13129 | PCI_VPD_LRDT_RO_DATA); | |
13130 | if (i < 0) | |
13131 | goto out_not_found; | |
1da177e4 | 13132 | |
4181b2c8 MC |
13133 | rosize = pci_vpd_lrdt_size(&vpd_data[i]); |
13134 | block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize; | |
13135 | i += PCI_VPD_LRDT_TAG_SIZE; | |
1da177e4 | 13136 | |
4181b2c8 MC |
13137 | if (block_end > TG3_NVM_VPD_LEN) |
13138 | goto out_not_found; | |
af2c6a4a | 13139 | |
184b8904 MC |
13140 | j = pci_vpd_find_info_keyword(vpd_data, i, rosize, |
13141 | PCI_VPD_RO_KEYWORD_MFR_ID); | |
13142 | if (j > 0) { | |
13143 | len = pci_vpd_info_field_size(&vpd_data[j]); | |
13144 | ||
13145 | j += PCI_VPD_INFO_FLD_HDR_SIZE; | |
13146 | if (j + len > block_end || len != 4 || | |
13147 | memcmp(&vpd_data[j], "1028", 4)) | |
13148 | goto partno; | |
13149 | ||
13150 | j = pci_vpd_find_info_keyword(vpd_data, i, rosize, | |
13151 | PCI_VPD_RO_KEYWORD_VENDOR0); | |
13152 | if (j < 0) | |
13153 | goto partno; | |
13154 | ||
13155 | len = pci_vpd_info_field_size(&vpd_data[j]); | |
13156 | ||
13157 | j += PCI_VPD_INFO_FLD_HDR_SIZE; | |
13158 | if (j + len > block_end) | |
13159 | goto partno; | |
13160 | ||
13161 | memcpy(tp->fw_ver, &vpd_data[j], len); | |
13162 | strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1); | |
13163 | } | |
13164 | ||
13165 | partno: | |
4181b2c8 MC |
13166 | i = pci_vpd_find_info_keyword(vpd_data, i, rosize, |
13167 | PCI_VPD_RO_KEYWORD_PARTNO); | |
13168 | if (i < 0) | |
13169 | goto out_not_found; | |
af2c6a4a | 13170 | |
4181b2c8 | 13171 | len = pci_vpd_info_field_size(&vpd_data[i]); |
1da177e4 | 13172 | |
4181b2c8 MC |
13173 | i += PCI_VPD_INFO_FLD_HDR_SIZE; |
13174 | if (len > TG3_BPN_SIZE || | |
13175 | (len + i) > TG3_NVM_VPD_LEN) | |
13176 | goto out_not_found; | |
1da177e4 | 13177 | |
4181b2c8 | 13178 | memcpy(tp->board_part_number, &vpd_data[i], len); |
1da177e4 | 13179 | |
1da177e4 | 13180 | out_not_found: |
a4a8bb15 | 13181 | kfree(vpd_data); |
37a949c5 | 13182 | if (tp->board_part_number[0]) |
a4a8bb15 MC |
13183 | return; |
13184 | ||
13185 | out_no_vpd: | |
37a949c5 MC |
13186 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) { |
13187 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717) | |
13188 | strcpy(tp->board_part_number, "BCM5717"); | |
13189 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718) | |
13190 | strcpy(tp->board_part_number, "BCM5718"); | |
13191 | else | |
13192 | goto nomatch; | |
13193 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { | |
13194 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780) | |
13195 | strcpy(tp->board_part_number, "BCM57780"); | |
13196 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760) | |
13197 | strcpy(tp->board_part_number, "BCM57760"); | |
13198 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790) | |
13199 | strcpy(tp->board_part_number, "BCM57790"); | |
13200 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788) | |
13201 | strcpy(tp->board_part_number, "BCM57788"); | |
13202 | else | |
13203 | goto nomatch; | |
13204 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) { | |
13205 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761) | |
13206 | strcpy(tp->board_part_number, "BCM57761"); | |
13207 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765) | |
13208 | strcpy(tp->board_part_number, "BCM57765"); | |
13209 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781) | |
13210 | strcpy(tp->board_part_number, "BCM57781"); | |
13211 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785) | |
13212 | strcpy(tp->board_part_number, "BCM57785"); | |
13213 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791) | |
13214 | strcpy(tp->board_part_number, "BCM57791"); | |
13215 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795) | |
13216 | strcpy(tp->board_part_number, "BCM57795"); | |
13217 | else | |
13218 | goto nomatch; | |
13219 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
b5d3772c | 13220 | strcpy(tp->board_part_number, "BCM95906"); |
37a949c5 MC |
13221 | } else { |
13222 | nomatch: | |
b5d3772c | 13223 | strcpy(tp->board_part_number, "none"); |
37a949c5 | 13224 | } |
1da177e4 LT |
13225 | } |
13226 | ||
9c8a620e MC |
13227 | static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset) |
13228 | { | |
13229 | u32 val; | |
13230 | ||
e4f34110 | 13231 | if (tg3_nvram_read(tp, offset, &val) || |
9c8a620e | 13232 | (val & 0xfc000000) != 0x0c000000 || |
e4f34110 | 13233 | tg3_nvram_read(tp, offset + 4, &val) || |
9c8a620e MC |
13234 | val != 0) |
13235 | return 0; | |
13236 | ||
13237 | return 1; | |
13238 | } | |
13239 | ||
acd9c119 MC |
13240 | static void __devinit tg3_read_bc_ver(struct tg3 *tp) |
13241 | { | |
ff3a7cb2 | 13242 | u32 val, offset, start, ver_offset; |
75f9936e | 13243 | int i, dst_off; |
ff3a7cb2 | 13244 | bool newver = false; |
acd9c119 MC |
13245 | |
13246 | if (tg3_nvram_read(tp, 0xc, &offset) || | |
13247 | tg3_nvram_read(tp, 0x4, &start)) | |
13248 | return; | |
13249 | ||
13250 | offset = tg3_nvram_logical_addr(tp, offset); | |
13251 | ||
ff3a7cb2 | 13252 | if (tg3_nvram_read(tp, offset, &val)) |
acd9c119 MC |
13253 | return; |
13254 | ||
ff3a7cb2 MC |
13255 | if ((val & 0xfc000000) == 0x0c000000) { |
13256 | if (tg3_nvram_read(tp, offset + 4, &val)) | |
acd9c119 MC |
13257 | return; |
13258 | ||
ff3a7cb2 MC |
13259 | if (val == 0) |
13260 | newver = true; | |
13261 | } | |
13262 | ||
75f9936e MC |
13263 | dst_off = strlen(tp->fw_ver); |
13264 | ||
ff3a7cb2 | 13265 | if (newver) { |
75f9936e MC |
13266 | if (TG3_VER_SIZE - dst_off < 16 || |
13267 | tg3_nvram_read(tp, offset + 8, &ver_offset)) | |
ff3a7cb2 MC |
13268 | return; |
13269 | ||
13270 | offset = offset + ver_offset - start; | |
13271 | for (i = 0; i < 16; i += 4) { | |
13272 | __be32 v; | |
13273 | if (tg3_nvram_read_be32(tp, offset + i, &v)) | |
13274 | return; | |
13275 | ||
75f9936e | 13276 | memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v)); |
ff3a7cb2 MC |
13277 | } |
13278 | } else { | |
13279 | u32 major, minor; | |
13280 | ||
13281 | if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset)) | |
13282 | return; | |
13283 | ||
13284 | major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >> | |
13285 | TG3_NVM_BCVER_MAJSFT; | |
13286 | minor = ver_offset & TG3_NVM_BCVER_MINMSK; | |
75f9936e MC |
13287 | snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off, |
13288 | "v%d.%02d", major, minor); | |
acd9c119 MC |
13289 | } |
13290 | } | |
13291 | ||
a6f6cb1c MC |
13292 | static void __devinit tg3_read_hwsb_ver(struct tg3 *tp) |
13293 | { | |
13294 | u32 val, major, minor; | |
13295 | ||
13296 | /* Use native endian representation */ | |
13297 | if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val)) | |
13298 | return; | |
13299 | ||
13300 | major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >> | |
13301 | TG3_NVM_HWSB_CFG1_MAJSFT; | |
13302 | minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >> | |
13303 | TG3_NVM_HWSB_CFG1_MINSFT; | |
13304 | ||
13305 | snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor); | |
13306 | } | |
13307 | ||
dfe00d7d MC |
13308 | static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val) |
13309 | { | |
13310 | u32 offset, major, minor, build; | |
13311 | ||
75f9936e | 13312 | strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1); |
dfe00d7d MC |
13313 | |
13314 | if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1) | |
13315 | return; | |
13316 | ||
13317 | switch (val & TG3_EEPROM_SB_REVISION_MASK) { | |
13318 | case TG3_EEPROM_SB_REVISION_0: | |
13319 | offset = TG3_EEPROM_SB_F1R0_EDH_OFF; | |
13320 | break; | |
13321 | case TG3_EEPROM_SB_REVISION_2: | |
13322 | offset = TG3_EEPROM_SB_F1R2_EDH_OFF; | |
13323 | break; | |
13324 | case TG3_EEPROM_SB_REVISION_3: | |
13325 | offset = TG3_EEPROM_SB_F1R3_EDH_OFF; | |
13326 | break; | |
a4153d40 MC |
13327 | case TG3_EEPROM_SB_REVISION_4: |
13328 | offset = TG3_EEPROM_SB_F1R4_EDH_OFF; | |
13329 | break; | |
13330 | case TG3_EEPROM_SB_REVISION_5: | |
13331 | offset = TG3_EEPROM_SB_F1R5_EDH_OFF; | |
13332 | break; | |
bba226ac MC |
13333 | case TG3_EEPROM_SB_REVISION_6: |
13334 | offset = TG3_EEPROM_SB_F1R6_EDH_OFF; | |
13335 | break; | |
dfe00d7d MC |
13336 | default: |
13337 | return; | |
13338 | } | |
13339 | ||
e4f34110 | 13340 | if (tg3_nvram_read(tp, offset, &val)) |
dfe00d7d MC |
13341 | return; |
13342 | ||
13343 | build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >> | |
13344 | TG3_EEPROM_SB_EDH_BLD_SHFT; | |
13345 | major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >> | |
13346 | TG3_EEPROM_SB_EDH_MAJ_SHFT; | |
13347 | minor = val & TG3_EEPROM_SB_EDH_MIN_MASK; | |
13348 | ||
13349 | if (minor > 99 || build > 26) | |
13350 | return; | |
13351 | ||
75f9936e MC |
13352 | offset = strlen(tp->fw_ver); |
13353 | snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset, | |
13354 | " v%d.%02d", major, minor); | |
dfe00d7d MC |
13355 | |
13356 | if (build > 0) { | |
75f9936e MC |
13357 | offset = strlen(tp->fw_ver); |
13358 | if (offset < TG3_VER_SIZE - 1) | |
13359 | tp->fw_ver[offset] = 'a' + build - 1; | |
dfe00d7d MC |
13360 | } |
13361 | } | |
13362 | ||
acd9c119 | 13363 | static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp) |
c4e6575c MC |
13364 | { |
13365 | u32 val, offset, start; | |
acd9c119 | 13366 | int i, vlen; |
9c8a620e MC |
13367 | |
13368 | for (offset = TG3_NVM_DIR_START; | |
13369 | offset < TG3_NVM_DIR_END; | |
13370 | offset += TG3_NVM_DIRENT_SIZE) { | |
e4f34110 | 13371 | if (tg3_nvram_read(tp, offset, &val)) |
c4e6575c MC |
13372 | return; |
13373 | ||
9c8a620e MC |
13374 | if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI) |
13375 | break; | |
13376 | } | |
13377 | ||
13378 | if (offset == TG3_NVM_DIR_END) | |
13379 | return; | |
13380 | ||
63c3a66f | 13381 | if (!tg3_flag(tp, 5705_PLUS)) |
9c8a620e | 13382 | start = 0x08000000; |
e4f34110 | 13383 | else if (tg3_nvram_read(tp, offset - 4, &start)) |
9c8a620e MC |
13384 | return; |
13385 | ||
e4f34110 | 13386 | if (tg3_nvram_read(tp, offset + 4, &offset) || |
9c8a620e | 13387 | !tg3_fw_img_is_valid(tp, offset) || |
e4f34110 | 13388 | tg3_nvram_read(tp, offset + 8, &val)) |
9c8a620e MC |
13389 | return; |
13390 | ||
13391 | offset += val - start; | |
13392 | ||
acd9c119 | 13393 | vlen = strlen(tp->fw_ver); |
9c8a620e | 13394 | |
acd9c119 MC |
13395 | tp->fw_ver[vlen++] = ','; |
13396 | tp->fw_ver[vlen++] = ' '; | |
9c8a620e MC |
13397 | |
13398 | for (i = 0; i < 4; i++) { | |
a9dc529d MC |
13399 | __be32 v; |
13400 | if (tg3_nvram_read_be32(tp, offset, &v)) | |
c4e6575c MC |
13401 | return; |
13402 | ||
b9fc7dc5 | 13403 | offset += sizeof(v); |
c4e6575c | 13404 | |
acd9c119 MC |
13405 | if (vlen > TG3_VER_SIZE - sizeof(v)) { |
13406 | memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen); | |
9c8a620e | 13407 | break; |
c4e6575c | 13408 | } |
9c8a620e | 13409 | |
acd9c119 MC |
13410 | memcpy(&tp->fw_ver[vlen], &v, sizeof(v)); |
13411 | vlen += sizeof(v); | |
c4e6575c | 13412 | } |
acd9c119 MC |
13413 | } |
13414 | ||
7fd76445 MC |
13415 | static void __devinit tg3_read_dash_ver(struct tg3 *tp) |
13416 | { | |
13417 | int vlen; | |
13418 | u32 apedata; | |
ecc79648 | 13419 | char *fwtype; |
7fd76445 | 13420 | |
63c3a66f | 13421 | if (!tg3_flag(tp, ENABLE_APE) || !tg3_flag(tp, ENABLE_ASF)) |
7fd76445 MC |
13422 | return; |
13423 | ||
13424 | apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); | |
13425 | if (apedata != APE_SEG_SIG_MAGIC) | |
13426 | return; | |
13427 | ||
13428 | apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); | |
13429 | if (!(apedata & APE_FW_STATUS_READY)) | |
13430 | return; | |
13431 | ||
13432 | apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION); | |
13433 | ||
dc6d0744 | 13434 | if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) { |
63c3a66f | 13435 | tg3_flag_set(tp, APE_HAS_NCSI); |
ecc79648 | 13436 | fwtype = "NCSI"; |
dc6d0744 | 13437 | } else { |
ecc79648 | 13438 | fwtype = "DASH"; |
dc6d0744 | 13439 | } |
ecc79648 | 13440 | |
7fd76445 MC |
13441 | vlen = strlen(tp->fw_ver); |
13442 | ||
ecc79648 MC |
13443 | snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d", |
13444 | fwtype, | |
7fd76445 MC |
13445 | (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT, |
13446 | (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT, | |
13447 | (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT, | |
13448 | (apedata & APE_FW_VERSION_BLDMSK)); | |
13449 | } | |
13450 | ||
acd9c119 MC |
13451 | static void __devinit tg3_read_fw_ver(struct tg3 *tp) |
13452 | { | |
13453 | u32 val; | |
75f9936e | 13454 | bool vpd_vers = false; |
acd9c119 | 13455 | |
75f9936e MC |
13456 | if (tp->fw_ver[0] != 0) |
13457 | vpd_vers = true; | |
df259d8c | 13458 | |
63c3a66f | 13459 | if (tg3_flag(tp, NO_NVRAM)) { |
75f9936e | 13460 | strcat(tp->fw_ver, "sb"); |
df259d8c MC |
13461 | return; |
13462 | } | |
13463 | ||
acd9c119 MC |
13464 | if (tg3_nvram_read(tp, 0, &val)) |
13465 | return; | |
13466 | ||
13467 | if (val == TG3_EEPROM_MAGIC) | |
13468 | tg3_read_bc_ver(tp); | |
13469 | else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) | |
13470 | tg3_read_sb_ver(tp, val); | |
a6f6cb1c MC |
13471 | else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW) |
13472 | tg3_read_hwsb_ver(tp); | |
acd9c119 MC |
13473 | else |
13474 | return; | |
13475 | ||
c9cab24e | 13476 | if (vpd_vers) |
75f9936e | 13477 | goto done; |
acd9c119 | 13478 | |
c9cab24e MC |
13479 | if (tg3_flag(tp, ENABLE_APE)) { |
13480 | if (tg3_flag(tp, ENABLE_ASF)) | |
13481 | tg3_read_dash_ver(tp); | |
13482 | } else if (tg3_flag(tp, ENABLE_ASF)) { | |
13483 | tg3_read_mgmtfw_ver(tp); | |
13484 | } | |
9c8a620e | 13485 | |
75f9936e | 13486 | done: |
9c8a620e | 13487 | tp->fw_ver[TG3_VER_SIZE - 1] = 0; |
c4e6575c MC |
13488 | } |
13489 | ||
7544b097 MC |
13490 | static struct pci_dev * __devinit tg3_find_peer(struct tg3 *); |
13491 | ||
7cb32cf2 MC |
13492 | static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp) |
13493 | { | |
63c3a66f | 13494 | if (tg3_flag(tp, LRG_PROD_RING_CAP)) |
de9f5230 | 13495 | return TG3_RX_RET_MAX_SIZE_5717; |
63c3a66f | 13496 | else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) |
de9f5230 | 13497 | return TG3_RX_RET_MAX_SIZE_5700; |
7cb32cf2 | 13498 | else |
de9f5230 | 13499 | return TG3_RX_RET_MAX_SIZE_5705; |
7cb32cf2 MC |
13500 | } |
13501 | ||
4143470c | 13502 | static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = { |
895950c2 JP |
13503 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) }, |
13504 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) }, | |
13505 | { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) }, | |
13506 | { }, | |
13507 | }; | |
13508 | ||
1da177e4 LT |
13509 | static int __devinit tg3_get_invariants(struct tg3 *tp) |
13510 | { | |
1da177e4 | 13511 | u32 misc_ctrl_reg; |
1da177e4 LT |
13512 | u32 pci_state_reg, grc_misc_cfg; |
13513 | u32 val; | |
13514 | u16 pci_cmd; | |
5e7dfd0f | 13515 | int err; |
1da177e4 | 13516 | |
1da177e4 LT |
13517 | /* Force memory write invalidate off. If we leave it on, |
13518 | * then on 5700_BX chips we have to enable a workaround. | |
13519 | * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary | |
13520 | * to match the cacheline size. The Broadcom driver have this | |
13521 | * workaround but turns MWI off all the times so never uses | |
13522 | * it. This seems to suggest that the workaround is insufficient. | |
13523 | */ | |
13524 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
13525 | pci_cmd &= ~PCI_COMMAND_INVALIDATE; | |
13526 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
13527 | ||
16821285 MC |
13528 | /* Important! -- Make sure register accesses are byteswapped |
13529 | * correctly. Also, for those chips that require it, make | |
13530 | * sure that indirect register accesses are enabled before | |
13531 | * the first operation. | |
1da177e4 LT |
13532 | */ |
13533 | pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
13534 | &misc_ctrl_reg); | |
16821285 MC |
13535 | tp->misc_host_ctrl |= (misc_ctrl_reg & |
13536 | MISC_HOST_CTRL_CHIPREV); | |
13537 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
13538 | tp->misc_host_ctrl); | |
1da177e4 LT |
13539 | |
13540 | tp->pci_chip_rev_id = (misc_ctrl_reg >> | |
13541 | MISC_HOST_CTRL_CHIPREV_SHIFT); | |
795d01c5 MC |
13542 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) { |
13543 | u32 prod_id_asic_rev; | |
13544 | ||
5001e2f6 MC |
13545 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || |
13546 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 || | |
d78b59f5 MC |
13547 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 || |
13548 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720) | |
f6eb9b1f MC |
13549 | pci_read_config_dword(tp->pdev, |
13550 | TG3PCI_GEN2_PRODID_ASICREV, | |
13551 | &prod_id_asic_rev); | |
b703df6f MC |
13552 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 || |
13553 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 || | |
13554 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 || | |
13555 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 || | |
13556 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 || | |
13557 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795) | |
13558 | pci_read_config_dword(tp->pdev, | |
13559 | TG3PCI_GEN15_PRODID_ASICREV, | |
13560 | &prod_id_asic_rev); | |
f6eb9b1f MC |
13561 | else |
13562 | pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV, | |
13563 | &prod_id_asic_rev); | |
13564 | ||
321d32a0 | 13565 | tp->pci_chip_rev_id = prod_id_asic_rev; |
795d01c5 | 13566 | } |
1da177e4 | 13567 | |
ff645bec MC |
13568 | /* Wrong chip ID in 5752 A0. This code can be removed later |
13569 | * as A0 is not in production. | |
13570 | */ | |
13571 | if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW) | |
13572 | tp->pci_chip_rev_id = CHIPREV_ID_5752_A0; | |
13573 | ||
6892914f MC |
13574 | /* If we have 5702/03 A1 or A2 on certain ICH chipsets, |
13575 | * we need to disable memory and use config. cycles | |
13576 | * only to access all registers. The 5702/03 chips | |
13577 | * can mistakenly decode the special cycles from the | |
13578 | * ICH chipsets as memory write cycles, causing corruption | |
13579 | * of register and memory space. Only certain ICH bridges | |
13580 | * will drive special cycles with non-zero data during the | |
13581 | * address phase which can fall within the 5703's address | |
13582 | * range. This is not an ICH bug as the PCI spec allows | |
13583 | * non-zero address during special cycles. However, only | |
13584 | * these ICH bridges are known to drive non-zero addresses | |
13585 | * during special cycles. | |
13586 | * | |
13587 | * Since special cycles do not cross PCI bridges, we only | |
13588 | * enable this workaround if the 5703 is on the secondary | |
13589 | * bus of these ICH bridges. | |
13590 | */ | |
13591 | if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) || | |
13592 | (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) { | |
13593 | static struct tg3_dev_id { | |
13594 | u32 vendor; | |
13595 | u32 device; | |
13596 | u32 rev; | |
13597 | } ich_chipsets[] = { | |
13598 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8, | |
13599 | PCI_ANY_ID }, | |
13600 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8, | |
13601 | PCI_ANY_ID }, | |
13602 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11, | |
13603 | 0xa }, | |
13604 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6, | |
13605 | PCI_ANY_ID }, | |
13606 | { }, | |
13607 | }; | |
13608 | struct tg3_dev_id *pci_id = &ich_chipsets[0]; | |
13609 | struct pci_dev *bridge = NULL; | |
13610 | ||
13611 | while (pci_id->vendor != 0) { | |
13612 | bridge = pci_get_device(pci_id->vendor, pci_id->device, | |
13613 | bridge); | |
13614 | if (!bridge) { | |
13615 | pci_id++; | |
13616 | continue; | |
13617 | } | |
13618 | if (pci_id->rev != PCI_ANY_ID) { | |
44c10138 | 13619 | if (bridge->revision > pci_id->rev) |
6892914f MC |
13620 | continue; |
13621 | } | |
13622 | if (bridge->subordinate && | |
13623 | (bridge->subordinate->number == | |
13624 | tp->pdev->bus->number)) { | |
63c3a66f | 13625 | tg3_flag_set(tp, ICH_WORKAROUND); |
6892914f MC |
13626 | pci_dev_put(bridge); |
13627 | break; | |
13628 | } | |
13629 | } | |
13630 | } | |
13631 | ||
6ff6f81d | 13632 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { |
41588ba1 MC |
13633 | static struct tg3_dev_id { |
13634 | u32 vendor; | |
13635 | u32 device; | |
13636 | } bridge_chipsets[] = { | |
13637 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 }, | |
13638 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 }, | |
13639 | { }, | |
13640 | }; | |
13641 | struct tg3_dev_id *pci_id = &bridge_chipsets[0]; | |
13642 | struct pci_dev *bridge = NULL; | |
13643 | ||
13644 | while (pci_id->vendor != 0) { | |
13645 | bridge = pci_get_device(pci_id->vendor, | |
13646 | pci_id->device, | |
13647 | bridge); | |
13648 | if (!bridge) { | |
13649 | pci_id++; | |
13650 | continue; | |
13651 | } | |
13652 | if (bridge->subordinate && | |
13653 | (bridge->subordinate->number <= | |
13654 | tp->pdev->bus->number) && | |
13655 | (bridge->subordinate->subordinate >= | |
13656 | tp->pdev->bus->number)) { | |
63c3a66f | 13657 | tg3_flag_set(tp, 5701_DMA_BUG); |
41588ba1 MC |
13658 | pci_dev_put(bridge); |
13659 | break; | |
13660 | } | |
13661 | } | |
13662 | } | |
13663 | ||
4a29cc2e MC |
13664 | /* The EPB bridge inside 5714, 5715, and 5780 cannot support |
13665 | * DMA addresses > 40-bit. This bridge may have other additional | |
13666 | * 57xx devices behind it in some 4-port NIC designs for example. | |
13667 | * Any tg3 device found behind the bridge will also need the 40-bit | |
13668 | * DMA workaround. | |
13669 | */ | |
a4e2b347 MC |
13670 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 || |
13671 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { | |
63c3a66f JP |
13672 | tg3_flag_set(tp, 5780_CLASS); |
13673 | tg3_flag_set(tp, 40BIT_DMA_BUG); | |
4cf78e4f | 13674 | tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI); |
859a5887 | 13675 | } else { |
4a29cc2e MC |
13676 | struct pci_dev *bridge = NULL; |
13677 | ||
13678 | do { | |
13679 | bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, | |
13680 | PCI_DEVICE_ID_SERVERWORKS_EPB, | |
13681 | bridge); | |
13682 | if (bridge && bridge->subordinate && | |
13683 | (bridge->subordinate->number <= | |
13684 | tp->pdev->bus->number) && | |
13685 | (bridge->subordinate->subordinate >= | |
13686 | tp->pdev->bus->number)) { | |
63c3a66f | 13687 | tg3_flag_set(tp, 40BIT_DMA_BUG); |
4a29cc2e MC |
13688 | pci_dev_put(bridge); |
13689 | break; | |
13690 | } | |
13691 | } while (bridge); | |
13692 | } | |
4cf78e4f | 13693 | |
f6eb9b1f MC |
13694 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || |
13695 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 || | |
d78b59f5 MC |
13696 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
13697 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
7544b097 MC |
13698 | tp->pdev_peer = tg3_find_peer(tp); |
13699 | ||
c885e824 | 13700 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
d78b59f5 MC |
13701 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
13702 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
63c3a66f | 13703 | tg3_flag_set(tp, 5717_PLUS); |
0a58d668 MC |
13704 | |
13705 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 || | |
63c3a66f JP |
13706 | tg3_flag(tp, 5717_PLUS)) |
13707 | tg3_flag_set(tp, 57765_PLUS); | |
c885e824 | 13708 | |
321d32a0 MC |
13709 | /* Intentionally exclude ASIC_REV_5906 */ |
13710 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || | |
d9ab5ad1 | 13711 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || |
d30cdd28 | 13712 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
9936bcf6 | 13713 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
57e6983c | 13714 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
f6eb9b1f | 13715 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
63c3a66f JP |
13716 | tg3_flag(tp, 57765_PLUS)) |
13717 | tg3_flag_set(tp, 5755_PLUS); | |
321d32a0 MC |
13718 | |
13719 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || | |
13720 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || | |
b5d3772c | 13721 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 || |
63c3a66f JP |
13722 | tg3_flag(tp, 5755_PLUS) || |
13723 | tg3_flag(tp, 5780_CLASS)) | |
13724 | tg3_flag_set(tp, 5750_PLUS); | |
6708e5cc | 13725 | |
6ff6f81d | 13726 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 || |
63c3a66f JP |
13727 | tg3_flag(tp, 5750_PLUS)) |
13728 | tg3_flag_set(tp, 5705_PLUS); | |
1b440c56 | 13729 | |
507399f1 | 13730 | /* Determine TSO capabilities */ |
2866d956 | 13731 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) |
4d163b75 | 13732 | ; /* Do nothing. HW bug. */ |
63c3a66f JP |
13733 | else if (tg3_flag(tp, 57765_PLUS)) |
13734 | tg3_flag_set(tp, HW_TSO_3); | |
13735 | else if (tg3_flag(tp, 5755_PLUS) || | |
e849cdc3 | 13736 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
63c3a66f JP |
13737 | tg3_flag_set(tp, HW_TSO_2); |
13738 | else if (tg3_flag(tp, 5750_PLUS)) { | |
13739 | tg3_flag_set(tp, HW_TSO_1); | |
13740 | tg3_flag_set(tp, TSO_BUG); | |
507399f1 MC |
13741 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 && |
13742 | tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2) | |
63c3a66f | 13743 | tg3_flag_clear(tp, TSO_BUG); |
507399f1 MC |
13744 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && |
13745 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 && | |
13746 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { | |
63c3a66f | 13747 | tg3_flag_set(tp, TSO_BUG); |
507399f1 MC |
13748 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) |
13749 | tp->fw_needed = FIRMWARE_TG3TSO5; | |
13750 | else | |
13751 | tp->fw_needed = FIRMWARE_TG3TSO; | |
13752 | } | |
13753 | ||
dabc5c67 | 13754 | /* Selectively allow TSO based on operating conditions */ |
6ff6f81d MC |
13755 | if (tg3_flag(tp, HW_TSO_1) || |
13756 | tg3_flag(tp, HW_TSO_2) || | |
13757 | tg3_flag(tp, HW_TSO_3) || | |
dabc5c67 MC |
13758 | (tp->fw_needed && !tg3_flag(tp, ENABLE_ASF))) |
13759 | tg3_flag_set(tp, TSO_CAPABLE); | |
13760 | else { | |
13761 | tg3_flag_clear(tp, TSO_CAPABLE); | |
13762 | tg3_flag_clear(tp, TSO_BUG); | |
13763 | tp->fw_needed = NULL; | |
13764 | } | |
13765 | ||
13766 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) | |
13767 | tp->fw_needed = FIRMWARE_TG3; | |
13768 | ||
507399f1 MC |
13769 | tp->irq_max = 1; |
13770 | ||
63c3a66f JP |
13771 | if (tg3_flag(tp, 5750_PLUS)) { |
13772 | tg3_flag_set(tp, SUPPORT_MSI); | |
7544b097 MC |
13773 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX || |
13774 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX || | |
13775 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 && | |
13776 | tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 && | |
13777 | tp->pdev_peer == tp->pdev)) | |
63c3a66f | 13778 | tg3_flag_clear(tp, SUPPORT_MSI); |
7544b097 | 13779 | |
63c3a66f | 13780 | if (tg3_flag(tp, 5755_PLUS) || |
b5d3772c | 13781 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
63c3a66f | 13782 | tg3_flag_set(tp, 1SHOT_MSI); |
52c0fd83 | 13783 | } |
4f125f42 | 13784 | |
63c3a66f JP |
13785 | if (tg3_flag(tp, 57765_PLUS)) { |
13786 | tg3_flag_set(tp, SUPPORT_MSIX); | |
507399f1 MC |
13787 | tp->irq_max = TG3_IRQ_MAX_VECS; |
13788 | } | |
f6eb9b1f | 13789 | } |
0e1406dd | 13790 | |
2ffcc981 | 13791 | if (tg3_flag(tp, 5755_PLUS)) |
63c3a66f | 13792 | tg3_flag_set(tp, SHORT_DMA_BUG); |
f6eb9b1f | 13793 | |
63c3a66f JP |
13794 | if (tg3_flag(tp, 5717_PLUS)) |
13795 | tg3_flag_set(tp, LRG_PROD_RING_CAP); | |
de9f5230 | 13796 | |
63c3a66f | 13797 | if (tg3_flag(tp, 57765_PLUS) && |
2866d956 | 13798 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719) |
63c3a66f | 13799 | tg3_flag_set(tp, USE_JUMBO_BDFLAG); |
b703df6f | 13800 | |
63c3a66f JP |
13801 | if (!tg3_flag(tp, 5705_PLUS) || |
13802 | tg3_flag(tp, 5780_CLASS) || | |
13803 | tg3_flag(tp, USE_JUMBO_BDFLAG)) | |
13804 | tg3_flag_set(tp, JUMBO_CAPABLE); | |
0f893dc6 | 13805 | |
52f4490c MC |
13806 | pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, |
13807 | &pci_state_reg); | |
13808 | ||
708ebb3a | 13809 | if (pci_is_pcie(tp->pdev)) { |
5e7dfd0f MC |
13810 | u16 lnkctl; |
13811 | ||
63c3a66f | 13812 | tg3_flag_set(tp, PCI_EXPRESS); |
5f5c51e3 | 13813 | |
cf79003d | 13814 | tp->pcie_readrq = 4096; |
d78b59f5 MC |
13815 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
13816 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
b4495ed8 | 13817 | tp->pcie_readrq = 2048; |
cf79003d MC |
13818 | |
13819 | pcie_set_readrq(tp->pdev, tp->pcie_readrq); | |
5f5c51e3 | 13820 | |
5e7dfd0f | 13821 | pci_read_config_word(tp->pdev, |
708ebb3a | 13822 | pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL, |
5e7dfd0f MC |
13823 | &lnkctl); |
13824 | if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) { | |
7196cd6c MC |
13825 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == |
13826 | ASIC_REV_5906) { | |
63c3a66f | 13827 | tg3_flag_clear(tp, HW_TSO_2); |
dabc5c67 | 13828 | tg3_flag_clear(tp, TSO_CAPABLE); |
7196cd6c | 13829 | } |
5e7dfd0f | 13830 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
321d32a0 | 13831 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
9cf74ebb MC |
13832 | tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 || |
13833 | tp->pci_chip_rev_id == CHIPREV_ID_57780_A1) | |
63c3a66f | 13834 | tg3_flag_set(tp, CLKREQ_BUG); |
614b0590 | 13835 | } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) { |
63c3a66f | 13836 | tg3_flag_set(tp, L1PLLPD_EN); |
c7835a77 | 13837 | } |
52f4490c | 13838 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { |
708ebb3a JM |
13839 | /* BCM5785 devices are effectively PCIe devices, and should |
13840 | * follow PCIe codepaths, but do not have a PCIe capabilities | |
13841 | * section. | |
13842 | */ | |
63c3a66f JP |
13843 | tg3_flag_set(tp, PCI_EXPRESS); |
13844 | } else if (!tg3_flag(tp, 5705_PLUS) || | |
13845 | tg3_flag(tp, 5780_CLASS)) { | |
52f4490c MC |
13846 | tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX); |
13847 | if (!tp->pcix_cap) { | |
2445e461 MC |
13848 | dev_err(&tp->pdev->dev, |
13849 | "Cannot find PCI-X capability, aborting\n"); | |
52f4490c MC |
13850 | return -EIO; |
13851 | } | |
13852 | ||
13853 | if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE)) | |
63c3a66f | 13854 | tg3_flag_set(tp, PCIX_MODE); |
52f4490c | 13855 | } |
1da177e4 | 13856 | |
399de50b MC |
13857 | /* If we have an AMD 762 or VIA K8T800 chipset, write |
13858 | * reordering to the mailbox registers done by the host | |
13859 | * controller can cause major troubles. We read back from | |
13860 | * every mailbox register write to force the writes to be | |
13861 | * posted to the chip in order. | |
13862 | */ | |
4143470c | 13863 | if (pci_dev_present(tg3_write_reorder_chipsets) && |
63c3a66f JP |
13864 | !tg3_flag(tp, PCI_EXPRESS)) |
13865 | tg3_flag_set(tp, MBOX_WRITE_REORDER); | |
399de50b | 13866 | |
69fc4053 MC |
13867 | pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, |
13868 | &tp->pci_cacheline_sz); | |
13869 | pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER, | |
13870 | &tp->pci_lat_timer); | |
1da177e4 LT |
13871 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && |
13872 | tp->pci_lat_timer < 64) { | |
13873 | tp->pci_lat_timer = 64; | |
69fc4053 MC |
13874 | pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, |
13875 | tp->pci_lat_timer); | |
1da177e4 LT |
13876 | } |
13877 | ||
16821285 MC |
13878 | /* Important! -- It is critical that the PCI-X hw workaround |
13879 | * situation is decided before the first MMIO register access. | |
13880 | */ | |
52f4490c MC |
13881 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) { |
13882 | /* 5700 BX chips need to have their TX producer index | |
13883 | * mailboxes written twice to workaround a bug. | |
13884 | */ | |
63c3a66f | 13885 | tg3_flag_set(tp, TXD_MBOX_HWBUG); |
1da177e4 | 13886 | |
52f4490c | 13887 | /* If we are in PCI-X mode, enable register write workaround. |
1da177e4 LT |
13888 | * |
13889 | * The workaround is to use indirect register accesses | |
13890 | * for all chip writes not to mailbox registers. | |
13891 | */ | |
63c3a66f | 13892 | if (tg3_flag(tp, PCIX_MODE)) { |
1da177e4 | 13893 | u32 pm_reg; |
1da177e4 | 13894 | |
63c3a66f | 13895 | tg3_flag_set(tp, PCIX_TARGET_HWBUG); |
1da177e4 LT |
13896 | |
13897 | /* The chip can have it's power management PCI config | |
13898 | * space registers clobbered due to this bug. | |
13899 | * So explicitly force the chip into D0 here. | |
13900 | */ | |
9974a356 MC |
13901 | pci_read_config_dword(tp->pdev, |
13902 | tp->pm_cap + PCI_PM_CTRL, | |
1da177e4 LT |
13903 | &pm_reg); |
13904 | pm_reg &= ~PCI_PM_CTRL_STATE_MASK; | |
13905 | pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */; | |
9974a356 MC |
13906 | pci_write_config_dword(tp->pdev, |
13907 | tp->pm_cap + PCI_PM_CTRL, | |
1da177e4 LT |
13908 | pm_reg); |
13909 | ||
13910 | /* Also, force SERR#/PERR# in PCI command. */ | |
13911 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
13912 | pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR; | |
13913 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
13914 | } | |
13915 | } | |
13916 | ||
1da177e4 | 13917 | if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0) |
63c3a66f | 13918 | tg3_flag_set(tp, PCI_HIGH_SPEED); |
1da177e4 | 13919 | if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0) |
63c3a66f | 13920 | tg3_flag_set(tp, PCI_32BIT); |
1da177e4 LT |
13921 | |
13922 | /* Chip-specific fixup from Broadcom driver */ | |
13923 | if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) && | |
13924 | (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) { | |
13925 | pci_state_reg |= PCISTATE_RETRY_SAME_DMA; | |
13926 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg); | |
13927 | } | |
13928 | ||
1ee582d8 | 13929 | /* Default fast path register access methods */ |
20094930 | 13930 | tp->read32 = tg3_read32; |
1ee582d8 | 13931 | tp->write32 = tg3_write32; |
09ee929c | 13932 | tp->read32_mbox = tg3_read32; |
20094930 | 13933 | tp->write32_mbox = tg3_write32; |
1ee582d8 MC |
13934 | tp->write32_tx_mbox = tg3_write32; |
13935 | tp->write32_rx_mbox = tg3_write32; | |
13936 | ||
13937 | /* Various workaround register access methods */ | |
63c3a66f | 13938 | if (tg3_flag(tp, PCIX_TARGET_HWBUG)) |
1ee582d8 | 13939 | tp->write32 = tg3_write_indirect_reg32; |
98efd8a6 | 13940 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 || |
63c3a66f | 13941 | (tg3_flag(tp, PCI_EXPRESS) && |
98efd8a6 MC |
13942 | tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) { |
13943 | /* | |
13944 | * Back to back register writes can cause problems on these | |
13945 | * chips, the workaround is to read back all reg writes | |
13946 | * except those to mailbox regs. | |
13947 | * | |
13948 | * See tg3_write_indirect_reg32(). | |
13949 | */ | |
1ee582d8 | 13950 | tp->write32 = tg3_write_flush_reg32; |
98efd8a6 MC |
13951 | } |
13952 | ||
63c3a66f | 13953 | if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) { |
1ee582d8 | 13954 | tp->write32_tx_mbox = tg3_write32_tx_mbox; |
63c3a66f | 13955 | if (tg3_flag(tp, MBOX_WRITE_REORDER)) |
1ee582d8 MC |
13956 | tp->write32_rx_mbox = tg3_write_flush_reg32; |
13957 | } | |
20094930 | 13958 | |
63c3a66f | 13959 | if (tg3_flag(tp, ICH_WORKAROUND)) { |
6892914f MC |
13960 | tp->read32 = tg3_read_indirect_reg32; |
13961 | tp->write32 = tg3_write_indirect_reg32; | |
13962 | tp->read32_mbox = tg3_read_indirect_mbox; | |
13963 | tp->write32_mbox = tg3_write_indirect_mbox; | |
13964 | tp->write32_tx_mbox = tg3_write_indirect_mbox; | |
13965 | tp->write32_rx_mbox = tg3_write_indirect_mbox; | |
13966 | ||
13967 | iounmap(tp->regs); | |
22abe310 | 13968 | tp->regs = NULL; |
6892914f MC |
13969 | |
13970 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
13971 | pci_cmd &= ~PCI_COMMAND_MEMORY; | |
13972 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
13973 | } | |
b5d3772c MC |
13974 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
13975 | tp->read32_mbox = tg3_read32_mbox_5906; | |
13976 | tp->write32_mbox = tg3_write32_mbox_5906; | |
13977 | tp->write32_tx_mbox = tg3_write32_mbox_5906; | |
13978 | tp->write32_rx_mbox = tg3_write32_mbox_5906; | |
13979 | } | |
6892914f | 13980 | |
bbadf503 | 13981 | if (tp->write32 == tg3_write_indirect_reg32 || |
63c3a66f | 13982 | (tg3_flag(tp, PCIX_MODE) && |
bbadf503 | 13983 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
f49639e6 | 13984 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701))) |
63c3a66f | 13985 | tg3_flag_set(tp, SRAM_USE_CONFIG); |
bbadf503 | 13986 | |
16821285 MC |
13987 | /* The memory arbiter has to be enabled in order for SRAM accesses |
13988 | * to succeed. Normally on powerup the tg3 chip firmware will make | |
13989 | * sure it is enabled, but other entities such as system netboot | |
13990 | * code might disable it. | |
13991 | */ | |
13992 | val = tr32(MEMARB_MODE); | |
13993 | tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE); | |
13994 | ||
69f11c99 MC |
13995 | if (tg3_flag(tp, PCIX_MODE)) { |
13996 | pci_read_config_dword(tp->pdev, | |
13997 | tp->pcix_cap + PCI_X_STATUS, &val); | |
13998 | tp->pci_fn = val & 0x7; | |
13999 | } else { | |
14000 | tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3; | |
14001 | } | |
14002 | ||
7d0c41ef | 14003 | /* Get eeprom hw config before calling tg3_set_power_state(). |
63c3a66f | 14004 | * In particular, the TG3_FLAG_IS_NIC flag must be |
7d0c41ef MC |
14005 | * determined before calling tg3_set_power_state() so that |
14006 | * we know whether or not to switch out of Vaux power. | |
14007 | * When the flag is set, it means that GPIO1 is used for eeprom | |
14008 | * write protect and also implies that it is a LOM where GPIOs | |
14009 | * are not used to switch power. | |
6aa20a22 | 14010 | */ |
7d0c41ef MC |
14011 | tg3_get_eeprom_hw_cfg(tp); |
14012 | ||
63c3a66f | 14013 | if (tg3_flag(tp, ENABLE_APE)) { |
0d3031d9 MC |
14014 | /* Allow reads and writes to the |
14015 | * APE register and memory space. | |
14016 | */ | |
14017 | pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR | | |
f92d9dc1 MC |
14018 | PCISTATE_ALLOW_APE_SHMEM_WR | |
14019 | PCISTATE_ALLOW_APE_PSPACE_WR; | |
0d3031d9 MC |
14020 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, |
14021 | pci_state_reg); | |
c9cab24e MC |
14022 | |
14023 | tg3_ape_lock_init(tp); | |
0d3031d9 MC |
14024 | } |
14025 | ||
9936bcf6 | 14026 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
57e6983c | 14027 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
321d32a0 | 14028 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
f6eb9b1f | 14029 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
63c3a66f JP |
14030 | tg3_flag(tp, 57765_PLUS)) |
14031 | tg3_flag_set(tp, CPMU_PRESENT); | |
d30cdd28 | 14032 | |
16821285 MC |
14033 | /* Set up tp->grc_local_ctrl before calling |
14034 | * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high | |
14035 | * will bring 5700's external PHY out of reset. | |
314fba34 MC |
14036 | * It is also used as eeprom write protect on LOMs. |
14037 | */ | |
14038 | tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM; | |
6ff6f81d | 14039 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
63c3a66f | 14040 | tg3_flag(tp, EEPROM_WRITE_PROT)) |
314fba34 MC |
14041 | tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | |
14042 | GRC_LCLCTRL_GPIO_OUTPUT1); | |
3e7d83bc MC |
14043 | /* Unused GPIO3 must be driven as output on 5752 because there |
14044 | * are no pull-up resistors on unused GPIO pins. | |
14045 | */ | |
14046 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) | |
14047 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; | |
314fba34 | 14048 | |
321d32a0 | 14049 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || |
cb4ed1fd MC |
14050 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
14051 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
af36e6b6 MC |
14052 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; |
14053 | ||
8d519ab2 MC |
14054 | if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || |
14055 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { | |
5f0c4a3c MC |
14056 | /* Turn off the debug UART. */ |
14057 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; | |
63c3a66f | 14058 | if (tg3_flag(tp, IS_NIC)) |
5f0c4a3c MC |
14059 | /* Keep VMain power. */ |
14060 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 | | |
14061 | GRC_LCLCTRL_GPIO_OUTPUT0; | |
14062 | } | |
14063 | ||
16821285 MC |
14064 | /* Switch out of Vaux if it is a NIC */ |
14065 | tg3_pwrsrc_switch_to_vmain(tp); | |
1da177e4 | 14066 | |
1da177e4 LT |
14067 | /* Derive initial jumbo mode from MTU assigned in |
14068 | * ether_setup() via the alloc_etherdev() call | |
14069 | */ | |
63c3a66f JP |
14070 | if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS)) |
14071 | tg3_flag_set(tp, JUMBO_RING_ENABLE); | |
1da177e4 LT |
14072 | |
14073 | /* Determine WakeOnLan speed to use. */ | |
14074 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
14075 | tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
14076 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 || | |
14077 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) { | |
63c3a66f | 14078 | tg3_flag_clear(tp, WOL_SPEED_100MB); |
1da177e4 | 14079 | } else { |
63c3a66f | 14080 | tg3_flag_set(tp, WOL_SPEED_100MB); |
1da177e4 LT |
14081 | } |
14082 | ||
7f97a4bd | 14083 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
f07e9af3 | 14084 | tp->phy_flags |= TG3_PHYFLG_IS_FET; |
7f97a4bd | 14085 | |
1da177e4 | 14086 | /* A few boards don't want Ethernet@WireSpeed phy feature */ |
6ff6f81d MC |
14087 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
14088 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && | |
1da177e4 | 14089 | (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) && |
747e8f8b | 14090 | (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) || |
f07e9af3 MC |
14091 | (tp->phy_flags & TG3_PHYFLG_IS_FET) || |
14092 | (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) | |
14093 | tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED; | |
1da177e4 LT |
14094 | |
14095 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX || | |
14096 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX) | |
f07e9af3 | 14097 | tp->phy_flags |= TG3_PHYFLG_ADC_BUG; |
1da177e4 | 14098 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) |
f07e9af3 | 14099 | tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG; |
1da177e4 | 14100 | |
63c3a66f | 14101 | if (tg3_flag(tp, 5705_PLUS) && |
f07e9af3 | 14102 | !(tp->phy_flags & TG3_PHYFLG_IS_FET) && |
321d32a0 | 14103 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && |
f6eb9b1f | 14104 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 && |
63c3a66f | 14105 | !tg3_flag(tp, 57765_PLUS)) { |
c424cb24 | 14106 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || |
d30cdd28 | 14107 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || |
9936bcf6 MC |
14108 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
14109 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) { | |
d4011ada MC |
14110 | if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 && |
14111 | tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722) | |
f07e9af3 | 14112 | tp->phy_flags |= TG3_PHYFLG_JITTER_BUG; |
c1d2a196 | 14113 | if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M) |
f07e9af3 | 14114 | tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM; |
321d32a0 | 14115 | } else |
f07e9af3 | 14116 | tp->phy_flags |= TG3_PHYFLG_BER_BUG; |
c424cb24 | 14117 | } |
1da177e4 | 14118 | |
b2a5c19c MC |
14119 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && |
14120 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) { | |
14121 | tp->phy_otp = tg3_read_otp_phycfg(tp); | |
14122 | if (tp->phy_otp == 0) | |
14123 | tp->phy_otp = TG3_OTP_DEFAULT; | |
14124 | } | |
14125 | ||
63c3a66f | 14126 | if (tg3_flag(tp, CPMU_PRESENT)) |
8ef21428 MC |
14127 | tp->mi_mode = MAC_MI_MODE_500KHZ_CONST; |
14128 | else | |
14129 | tp->mi_mode = MAC_MI_MODE_BASE; | |
14130 | ||
1da177e4 | 14131 | tp->coalesce_mode = 0; |
1da177e4 LT |
14132 | if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX && |
14133 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX) | |
14134 | tp->coalesce_mode |= HOSTCC_MODE_32BYTE; | |
14135 | ||
4d958473 MC |
14136 | /* Set these bits to enable statistics workaround. */ |
14137 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
14138 | tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 || | |
14139 | tp->pci_chip_rev_id == CHIPREV_ID_5720_A0) { | |
14140 | tp->coalesce_mode |= HOSTCC_MODE_ATTN; | |
14141 | tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN; | |
14142 | } | |
14143 | ||
321d32a0 MC |
14144 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
14145 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
63c3a66f | 14146 | tg3_flag_set(tp, USE_PHYLIB); |
57e6983c | 14147 | |
158d7abd MC |
14148 | err = tg3_mdio_init(tp); |
14149 | if (err) | |
14150 | return err; | |
1da177e4 LT |
14151 | |
14152 | /* Initialize data/descriptor byte/word swapping. */ | |
14153 | val = tr32(GRC_MODE); | |
f2096f94 MC |
14154 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) |
14155 | val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA | | |
14156 | GRC_MODE_WORD_SWAP_B2HRX_DATA | | |
14157 | GRC_MODE_B2HRX_ENABLE | | |
14158 | GRC_MODE_HTX2B_ENABLE | | |
14159 | GRC_MODE_HOST_STACKUP); | |
14160 | else | |
14161 | val &= GRC_MODE_HOST_STACKUP; | |
14162 | ||
1da177e4 LT |
14163 | tw32(GRC_MODE, val | tp->grc_mode); |
14164 | ||
14165 | tg3_switch_clocks(tp); | |
14166 | ||
14167 | /* Clear this out for sanity. */ | |
14168 | tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
14169 | ||
14170 | pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, | |
14171 | &pci_state_reg); | |
14172 | if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 && | |
63c3a66f | 14173 | !tg3_flag(tp, PCIX_TARGET_HWBUG)) { |
1da177e4 LT |
14174 | u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl); |
14175 | ||
14176 | if (chiprevid == CHIPREV_ID_5701_A0 || | |
14177 | chiprevid == CHIPREV_ID_5701_B0 || | |
14178 | chiprevid == CHIPREV_ID_5701_B2 || | |
14179 | chiprevid == CHIPREV_ID_5701_B5) { | |
14180 | void __iomem *sram_base; | |
14181 | ||
14182 | /* Write some dummy words into the SRAM status block | |
14183 | * area, see if it reads back correctly. If the return | |
14184 | * value is bad, force enable the PCIX workaround. | |
14185 | */ | |
14186 | sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK; | |
14187 | ||
14188 | writel(0x00000000, sram_base); | |
14189 | writel(0x00000000, sram_base + 4); | |
14190 | writel(0xffffffff, sram_base + 4); | |
14191 | if (readl(sram_base) != 0x00000000) | |
63c3a66f | 14192 | tg3_flag_set(tp, PCIX_TARGET_HWBUG); |
1da177e4 LT |
14193 | } |
14194 | } | |
14195 | ||
14196 | udelay(50); | |
14197 | tg3_nvram_init(tp); | |
14198 | ||
14199 | grc_misc_cfg = tr32(GRC_MISC_CFG); | |
14200 | grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK; | |
14201 | ||
1da177e4 LT |
14202 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && |
14203 | (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 || | |
14204 | grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M)) | |
63c3a66f | 14205 | tg3_flag_set(tp, IS_5788); |
1da177e4 | 14206 | |
63c3a66f | 14207 | if (!tg3_flag(tp, IS_5788) && |
6ff6f81d | 14208 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) |
63c3a66f JP |
14209 | tg3_flag_set(tp, TAGGED_STATUS); |
14210 | if (tg3_flag(tp, TAGGED_STATUS)) { | |
fac9b83e DM |
14211 | tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD | |
14212 | HOSTCC_MODE_CLRTICK_TXBD); | |
14213 | ||
14214 | tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS; | |
14215 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
14216 | tp->misc_host_ctrl); | |
14217 | } | |
14218 | ||
3bda1258 | 14219 | /* Preserve the APE MAC_MODE bits */ |
63c3a66f | 14220 | if (tg3_flag(tp, ENABLE_APE)) |
d2394e6b | 14221 | tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; |
3bda1258 MC |
14222 | else |
14223 | tp->mac_mode = TG3_DEF_MAC_MODE; | |
14224 | ||
1da177e4 LT |
14225 | /* these are limited to 10/100 only */ |
14226 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && | |
14227 | (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) || | |
14228 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && | |
14229 | tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM && | |
14230 | (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 || | |
14231 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 || | |
14232 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) || | |
14233 | (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM && | |
14234 | (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F || | |
676917d4 MC |
14235 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F || |
14236 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) || | |
321d32a0 | 14237 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 || |
d1101142 MC |
14238 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 || |
14239 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 || | |
f07e9af3 MC |
14240 | (tp->phy_flags & TG3_PHYFLG_IS_FET)) |
14241 | tp->phy_flags |= TG3_PHYFLG_10_100_ONLY; | |
1da177e4 LT |
14242 | |
14243 | err = tg3_phy_probe(tp); | |
14244 | if (err) { | |
2445e461 | 14245 | dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err); |
1da177e4 | 14246 | /* ... but do not return immediately ... */ |
b02fd9e3 | 14247 | tg3_mdio_fini(tp); |
1da177e4 LT |
14248 | } |
14249 | ||
184b8904 | 14250 | tg3_read_vpd(tp); |
c4e6575c | 14251 | tg3_read_fw_ver(tp); |
1da177e4 | 14252 | |
f07e9af3 MC |
14253 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
14254 | tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; | |
1da177e4 LT |
14255 | } else { |
14256 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) | |
f07e9af3 | 14257 | tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; |
1da177e4 | 14258 | else |
f07e9af3 | 14259 | tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; |
1da177e4 LT |
14260 | } |
14261 | ||
14262 | /* 5700 {AX,BX} chips have a broken status block link | |
14263 | * change bit implementation, so we must use the | |
14264 | * status register in those cases. | |
14265 | */ | |
14266 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) | |
63c3a66f | 14267 | tg3_flag_set(tp, USE_LINKCHG_REG); |
1da177e4 | 14268 | else |
63c3a66f | 14269 | tg3_flag_clear(tp, USE_LINKCHG_REG); |
1da177e4 LT |
14270 | |
14271 | /* The led_ctrl is set during tg3_phy_probe, here we might | |
14272 | * have to force the link status polling mechanism based | |
14273 | * upon subsystem IDs. | |
14274 | */ | |
14275 | if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL && | |
007a880d | 14276 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 && |
f07e9af3 MC |
14277 | !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { |
14278 | tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; | |
63c3a66f | 14279 | tg3_flag_set(tp, USE_LINKCHG_REG); |
1da177e4 LT |
14280 | } |
14281 | ||
14282 | /* For all SERDES we poll the MAC status register. */ | |
f07e9af3 | 14283 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
63c3a66f | 14284 | tg3_flag_set(tp, POLL_SERDES); |
1da177e4 | 14285 | else |
63c3a66f | 14286 | tg3_flag_clear(tp, POLL_SERDES); |
1da177e4 | 14287 | |
bf933c80 | 14288 | tp->rx_offset = NET_IP_ALIGN; |
d2757fc4 | 14289 | tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD; |
1da177e4 | 14290 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 && |
63c3a66f | 14291 | tg3_flag(tp, PCIX_MODE)) { |
bf933c80 | 14292 | tp->rx_offset = 0; |
d2757fc4 | 14293 | #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS |
9dc7a113 | 14294 | tp->rx_copy_thresh = ~(u16)0; |
d2757fc4 MC |
14295 | #endif |
14296 | } | |
1da177e4 | 14297 | |
2c49a44d MC |
14298 | tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1; |
14299 | tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1; | |
7cb32cf2 MC |
14300 | tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1; |
14301 | ||
2c49a44d | 14302 | tp->rx_std_max_post = tp->rx_std_ring_mask + 1; |
f92905de MC |
14303 | |
14304 | /* Increment the rx prod index on the rx std ring by at most | |
14305 | * 8 for these chips to workaround hw errata. | |
14306 | */ | |
14307 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || | |
14308 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || | |
14309 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) | |
14310 | tp->rx_std_max_post = 8; | |
14311 | ||
63c3a66f | 14312 | if (tg3_flag(tp, ASPM_WORKAROUND)) |
8ed5d97e MC |
14313 | tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) & |
14314 | PCIE_PWR_MGMT_L1_THRESH_MSK; | |
14315 | ||
1da177e4 LT |
14316 | return err; |
14317 | } | |
14318 | ||
49b6e95f | 14319 | #ifdef CONFIG_SPARC |
1da177e4 LT |
14320 | static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp) |
14321 | { | |
14322 | struct net_device *dev = tp->dev; | |
14323 | struct pci_dev *pdev = tp->pdev; | |
49b6e95f | 14324 | struct device_node *dp = pci_device_to_OF_node(pdev); |
374d4cac | 14325 | const unsigned char *addr; |
49b6e95f DM |
14326 | int len; |
14327 | ||
14328 | addr = of_get_property(dp, "local-mac-address", &len); | |
14329 | if (addr && len == 6) { | |
14330 | memcpy(dev->dev_addr, addr, 6); | |
14331 | memcpy(dev->perm_addr, dev->dev_addr, 6); | |
14332 | return 0; | |
1da177e4 LT |
14333 | } |
14334 | return -ENODEV; | |
14335 | } | |
14336 | ||
14337 | static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp) | |
14338 | { | |
14339 | struct net_device *dev = tp->dev; | |
14340 | ||
14341 | memcpy(dev->dev_addr, idprom->id_ethaddr, 6); | |
2ff43697 | 14342 | memcpy(dev->perm_addr, idprom->id_ethaddr, 6); |
1da177e4 LT |
14343 | return 0; |
14344 | } | |
14345 | #endif | |
14346 | ||
14347 | static int __devinit tg3_get_device_address(struct tg3 *tp) | |
14348 | { | |
14349 | struct net_device *dev = tp->dev; | |
14350 | u32 hi, lo, mac_offset; | |
008652b3 | 14351 | int addr_ok = 0; |
1da177e4 | 14352 | |
49b6e95f | 14353 | #ifdef CONFIG_SPARC |
1da177e4 LT |
14354 | if (!tg3_get_macaddr_sparc(tp)) |
14355 | return 0; | |
14356 | #endif | |
14357 | ||
14358 | mac_offset = 0x7c; | |
6ff6f81d | 14359 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || |
63c3a66f | 14360 | tg3_flag(tp, 5780_CLASS)) { |
1da177e4 LT |
14361 | if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) |
14362 | mac_offset = 0xcc; | |
14363 | if (tg3_nvram_lock(tp)) | |
14364 | tw32_f(NVRAM_CMD, NVRAM_CMD_RESET); | |
14365 | else | |
14366 | tg3_nvram_unlock(tp); | |
63c3a66f | 14367 | } else if (tg3_flag(tp, 5717_PLUS)) { |
69f11c99 | 14368 | if (tp->pci_fn & 1) |
a1b950d5 | 14369 | mac_offset = 0xcc; |
69f11c99 | 14370 | if (tp->pci_fn > 1) |
a50d0796 | 14371 | mac_offset += 0x18c; |
a1b950d5 | 14372 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
b5d3772c | 14373 | mac_offset = 0x10; |
1da177e4 LT |
14374 | |
14375 | /* First try to get it from MAC address mailbox. */ | |
14376 | tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi); | |
14377 | if ((hi >> 16) == 0x484b) { | |
14378 | dev->dev_addr[0] = (hi >> 8) & 0xff; | |
14379 | dev->dev_addr[1] = (hi >> 0) & 0xff; | |
14380 | ||
14381 | tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo); | |
14382 | dev->dev_addr[2] = (lo >> 24) & 0xff; | |
14383 | dev->dev_addr[3] = (lo >> 16) & 0xff; | |
14384 | dev->dev_addr[4] = (lo >> 8) & 0xff; | |
14385 | dev->dev_addr[5] = (lo >> 0) & 0xff; | |
1da177e4 | 14386 | |
008652b3 MC |
14387 | /* Some old bootcode may report a 0 MAC address in SRAM */ |
14388 | addr_ok = is_valid_ether_addr(&dev->dev_addr[0]); | |
14389 | } | |
14390 | if (!addr_ok) { | |
14391 | /* Next, try NVRAM. */ | |
63c3a66f | 14392 | if (!tg3_flag(tp, NO_NVRAM) && |
df259d8c | 14393 | !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) && |
6d348f2c | 14394 | !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) { |
62cedd11 MC |
14395 | memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2); |
14396 | memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo)); | |
008652b3 MC |
14397 | } |
14398 | /* Finally just fetch it out of the MAC control regs. */ | |
14399 | else { | |
14400 | hi = tr32(MAC_ADDR_0_HIGH); | |
14401 | lo = tr32(MAC_ADDR_0_LOW); | |
14402 | ||
14403 | dev->dev_addr[5] = lo & 0xff; | |
14404 | dev->dev_addr[4] = (lo >> 8) & 0xff; | |
14405 | dev->dev_addr[3] = (lo >> 16) & 0xff; | |
14406 | dev->dev_addr[2] = (lo >> 24) & 0xff; | |
14407 | dev->dev_addr[1] = hi & 0xff; | |
14408 | dev->dev_addr[0] = (hi >> 8) & 0xff; | |
14409 | } | |
1da177e4 LT |
14410 | } |
14411 | ||
14412 | if (!is_valid_ether_addr(&dev->dev_addr[0])) { | |
7582a335 | 14413 | #ifdef CONFIG_SPARC |
1da177e4 LT |
14414 | if (!tg3_get_default_macaddr_sparc(tp)) |
14415 | return 0; | |
14416 | #endif | |
14417 | return -EINVAL; | |
14418 | } | |
2ff43697 | 14419 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
1da177e4 LT |
14420 | return 0; |
14421 | } | |
14422 | ||
59e6b434 DM |
14423 | #define BOUNDARY_SINGLE_CACHELINE 1 |
14424 | #define BOUNDARY_MULTI_CACHELINE 2 | |
14425 | ||
14426 | static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val) | |
14427 | { | |
14428 | int cacheline_size; | |
14429 | u8 byte; | |
14430 | int goal; | |
14431 | ||
14432 | pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte); | |
14433 | if (byte == 0) | |
14434 | cacheline_size = 1024; | |
14435 | else | |
14436 | cacheline_size = (int) byte * 4; | |
14437 | ||
14438 | /* On 5703 and later chips, the boundary bits have no | |
14439 | * effect. | |
14440 | */ | |
14441 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
14442 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 && | |
63c3a66f | 14443 | !tg3_flag(tp, PCI_EXPRESS)) |
59e6b434 DM |
14444 | goto out; |
14445 | ||
14446 | #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC) | |
14447 | goal = BOUNDARY_MULTI_CACHELINE; | |
14448 | #else | |
14449 | #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA) | |
14450 | goal = BOUNDARY_SINGLE_CACHELINE; | |
14451 | #else | |
14452 | goal = 0; | |
14453 | #endif | |
14454 | #endif | |
14455 | ||
63c3a66f | 14456 | if (tg3_flag(tp, 57765_PLUS)) { |
cbf9ca6c MC |
14457 | val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT; |
14458 | goto out; | |
14459 | } | |
14460 | ||
59e6b434 DM |
14461 | if (!goal) |
14462 | goto out; | |
14463 | ||
14464 | /* PCI controllers on most RISC systems tend to disconnect | |
14465 | * when a device tries to burst across a cache-line boundary. | |
14466 | * Therefore, letting tg3 do so just wastes PCI bandwidth. | |
14467 | * | |
14468 | * Unfortunately, for PCI-E there are only limited | |
14469 | * write-side controls for this, and thus for reads | |
14470 | * we will still get the disconnects. We'll also waste | |
14471 | * these PCI cycles for both read and write for chips | |
14472 | * other than 5700 and 5701 which do not implement the | |
14473 | * boundary bits. | |
14474 | */ | |
63c3a66f | 14475 | if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) { |
59e6b434 DM |
14476 | switch (cacheline_size) { |
14477 | case 16: | |
14478 | case 32: | |
14479 | case 64: | |
14480 | case 128: | |
14481 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14482 | val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX | | |
14483 | DMA_RWCTRL_WRITE_BNDRY_128_PCIX); | |
14484 | } else { | |
14485 | val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX | | |
14486 | DMA_RWCTRL_WRITE_BNDRY_384_PCIX); | |
14487 | } | |
14488 | break; | |
14489 | ||
14490 | case 256: | |
14491 | val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX | | |
14492 | DMA_RWCTRL_WRITE_BNDRY_256_PCIX); | |
14493 | break; | |
14494 | ||
14495 | default: | |
14496 | val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX | | |
14497 | DMA_RWCTRL_WRITE_BNDRY_384_PCIX); | |
14498 | break; | |
855e1111 | 14499 | } |
63c3a66f | 14500 | } else if (tg3_flag(tp, PCI_EXPRESS)) { |
59e6b434 DM |
14501 | switch (cacheline_size) { |
14502 | case 16: | |
14503 | case 32: | |
14504 | case 64: | |
14505 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14506 | val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE; | |
14507 | val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE; | |
14508 | break; | |
14509 | } | |
14510 | /* fallthrough */ | |
14511 | case 128: | |
14512 | default: | |
14513 | val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE; | |
14514 | val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE; | |
14515 | break; | |
855e1111 | 14516 | } |
59e6b434 DM |
14517 | } else { |
14518 | switch (cacheline_size) { | |
14519 | case 16: | |
14520 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14521 | val |= (DMA_RWCTRL_READ_BNDRY_16 | | |
14522 | DMA_RWCTRL_WRITE_BNDRY_16); | |
14523 | break; | |
14524 | } | |
14525 | /* fallthrough */ | |
14526 | case 32: | |
14527 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14528 | val |= (DMA_RWCTRL_READ_BNDRY_32 | | |
14529 | DMA_RWCTRL_WRITE_BNDRY_32); | |
14530 | break; | |
14531 | } | |
14532 | /* fallthrough */ | |
14533 | case 64: | |
14534 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14535 | val |= (DMA_RWCTRL_READ_BNDRY_64 | | |
14536 | DMA_RWCTRL_WRITE_BNDRY_64); | |
14537 | break; | |
14538 | } | |
14539 | /* fallthrough */ | |
14540 | case 128: | |
14541 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14542 | val |= (DMA_RWCTRL_READ_BNDRY_128 | | |
14543 | DMA_RWCTRL_WRITE_BNDRY_128); | |
14544 | break; | |
14545 | } | |
14546 | /* fallthrough */ | |
14547 | case 256: | |
14548 | val |= (DMA_RWCTRL_READ_BNDRY_256 | | |
14549 | DMA_RWCTRL_WRITE_BNDRY_256); | |
14550 | break; | |
14551 | case 512: | |
14552 | val |= (DMA_RWCTRL_READ_BNDRY_512 | | |
14553 | DMA_RWCTRL_WRITE_BNDRY_512); | |
14554 | break; | |
14555 | case 1024: | |
14556 | default: | |
14557 | val |= (DMA_RWCTRL_READ_BNDRY_1024 | | |
14558 | DMA_RWCTRL_WRITE_BNDRY_1024); | |
14559 | break; | |
855e1111 | 14560 | } |
59e6b434 DM |
14561 | } |
14562 | ||
14563 | out: | |
14564 | return val; | |
14565 | } | |
14566 | ||
1da177e4 LT |
14567 | static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device) |
14568 | { | |
14569 | struct tg3_internal_buffer_desc test_desc; | |
14570 | u32 sram_dma_descs; | |
14571 | int i, ret; | |
14572 | ||
14573 | sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE; | |
14574 | ||
14575 | tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0); | |
14576 | tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0); | |
14577 | tw32(RDMAC_STATUS, 0); | |
14578 | tw32(WDMAC_STATUS, 0); | |
14579 | ||
14580 | tw32(BUFMGR_MODE, 0); | |
14581 | tw32(FTQ_RESET, 0); | |
14582 | ||
14583 | test_desc.addr_hi = ((u64) buf_dma) >> 32; | |
14584 | test_desc.addr_lo = buf_dma & 0xffffffff; | |
14585 | test_desc.nic_mbuf = 0x00002100; | |
14586 | test_desc.len = size; | |
14587 | ||
14588 | /* | |
14589 | * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz | |
14590 | * the *second* time the tg3 driver was getting loaded after an | |
14591 | * initial scan. | |
14592 | * | |
14593 | * Broadcom tells me: | |
14594 | * ...the DMA engine is connected to the GRC block and a DMA | |
14595 | * reset may affect the GRC block in some unpredictable way... | |
14596 | * The behavior of resets to individual blocks has not been tested. | |
14597 | * | |
14598 | * Broadcom noted the GRC reset will also reset all sub-components. | |
14599 | */ | |
14600 | if (to_device) { | |
14601 | test_desc.cqid_sqid = (13 << 8) | 2; | |
14602 | ||
14603 | tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE); | |
14604 | udelay(40); | |
14605 | } else { | |
14606 | test_desc.cqid_sqid = (16 << 8) | 7; | |
14607 | ||
14608 | tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE); | |
14609 | udelay(40); | |
14610 | } | |
14611 | test_desc.flags = 0x00000005; | |
14612 | ||
14613 | for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) { | |
14614 | u32 val; | |
14615 | ||
14616 | val = *(((u32 *)&test_desc) + i); | |
14617 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, | |
14618 | sram_dma_descs + (i * sizeof(u32))); | |
14619 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
14620 | } | |
14621 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
14622 | ||
859a5887 | 14623 | if (to_device) |
1da177e4 | 14624 | tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs); |
859a5887 | 14625 | else |
1da177e4 | 14626 | tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs); |
1da177e4 LT |
14627 | |
14628 | ret = -ENODEV; | |
14629 | for (i = 0; i < 40; i++) { | |
14630 | u32 val; | |
14631 | ||
14632 | if (to_device) | |
14633 | val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ); | |
14634 | else | |
14635 | val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ); | |
14636 | if ((val & 0xffff) == sram_dma_descs) { | |
14637 | ret = 0; | |
14638 | break; | |
14639 | } | |
14640 | ||
14641 | udelay(100); | |
14642 | } | |
14643 | ||
14644 | return ret; | |
14645 | } | |
14646 | ||
ded7340d | 14647 | #define TEST_BUFFER_SIZE 0x2000 |
1da177e4 | 14648 | |
4143470c | 14649 | static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = { |
895950c2 JP |
14650 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) }, |
14651 | { }, | |
14652 | }; | |
14653 | ||
1da177e4 LT |
14654 | static int __devinit tg3_test_dma(struct tg3 *tp) |
14655 | { | |
14656 | dma_addr_t buf_dma; | |
59e6b434 | 14657 | u32 *buf, saved_dma_rwctrl; |
cbf9ca6c | 14658 | int ret = 0; |
1da177e4 | 14659 | |
4bae65c8 MC |
14660 | buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, |
14661 | &buf_dma, GFP_KERNEL); | |
1da177e4 LT |
14662 | if (!buf) { |
14663 | ret = -ENOMEM; | |
14664 | goto out_nofree; | |
14665 | } | |
14666 | ||
14667 | tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) | | |
14668 | (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT)); | |
14669 | ||
59e6b434 | 14670 | tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl); |
1da177e4 | 14671 | |
63c3a66f | 14672 | if (tg3_flag(tp, 57765_PLUS)) |
cbf9ca6c MC |
14673 | goto out; |
14674 | ||
63c3a66f | 14675 | if (tg3_flag(tp, PCI_EXPRESS)) { |
1da177e4 LT |
14676 | /* DMA read watermark not used on PCIE */ |
14677 | tp->dma_rwctrl |= 0x00180000; | |
63c3a66f | 14678 | } else if (!tg3_flag(tp, PCIX_MODE)) { |
85e94ced MC |
14679 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 || |
14680 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) | |
1da177e4 LT |
14681 | tp->dma_rwctrl |= 0x003f0000; |
14682 | else | |
14683 | tp->dma_rwctrl |= 0x003f000f; | |
14684 | } else { | |
14685 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
14686 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
14687 | u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f); | |
49afdeb6 | 14688 | u32 read_water = 0x7; |
1da177e4 | 14689 | |
4a29cc2e MC |
14690 | /* If the 5704 is behind the EPB bridge, we can |
14691 | * do the less restrictive ONE_DMA workaround for | |
14692 | * better performance. | |
14693 | */ | |
63c3a66f | 14694 | if (tg3_flag(tp, 40BIT_DMA_BUG) && |
4a29cc2e MC |
14695 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) |
14696 | tp->dma_rwctrl |= 0x8000; | |
14697 | else if (ccval == 0x6 || ccval == 0x7) | |
1da177e4 LT |
14698 | tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; |
14699 | ||
49afdeb6 MC |
14700 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) |
14701 | read_water = 4; | |
59e6b434 | 14702 | /* Set bit 23 to enable PCIX hw bug fix */ |
49afdeb6 MC |
14703 | tp->dma_rwctrl |= |
14704 | (read_water << DMA_RWCTRL_READ_WATER_SHIFT) | | |
14705 | (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) | | |
14706 | (1 << 23); | |
4cf78e4f MC |
14707 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) { |
14708 | /* 5780 always in PCIX mode */ | |
14709 | tp->dma_rwctrl |= 0x00144000; | |
a4e2b347 MC |
14710 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { |
14711 | /* 5714 always in PCIX mode */ | |
14712 | tp->dma_rwctrl |= 0x00148000; | |
1da177e4 LT |
14713 | } else { |
14714 | tp->dma_rwctrl |= 0x001b000f; | |
14715 | } | |
14716 | } | |
14717 | ||
14718 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
14719 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) | |
14720 | tp->dma_rwctrl &= 0xfffffff0; | |
14721 | ||
14722 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
14723 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
14724 | /* Remove this if it causes problems for some boards. */ | |
14725 | tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT; | |
14726 | ||
14727 | /* On 5700/5701 chips, we need to set this bit. | |
14728 | * Otherwise the chip will issue cacheline transactions | |
14729 | * to streamable DMA memory with not all the byte | |
14730 | * enables turned on. This is an error on several | |
14731 | * RISC PCI controllers, in particular sparc64. | |
14732 | * | |
14733 | * On 5703/5704 chips, this bit has been reassigned | |
14734 | * a different meaning. In particular, it is used | |
14735 | * on those chips to enable a PCI-X workaround. | |
14736 | */ | |
14737 | tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE; | |
14738 | } | |
14739 | ||
14740 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
14741 | ||
14742 | #if 0 | |
14743 | /* Unneeded, already done by tg3_get_invariants. */ | |
14744 | tg3_switch_clocks(tp); | |
14745 | #endif | |
14746 | ||
1da177e4 LT |
14747 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && |
14748 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) | |
14749 | goto out; | |
14750 | ||
59e6b434 DM |
14751 | /* It is best to perform DMA test with maximum write burst size |
14752 | * to expose the 5700/5701 write DMA bug. | |
14753 | */ | |
14754 | saved_dma_rwctrl = tp->dma_rwctrl; | |
14755 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; | |
14756 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
14757 | ||
1da177e4 LT |
14758 | while (1) { |
14759 | u32 *p = buf, i; | |
14760 | ||
14761 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) | |
14762 | p[i] = i; | |
14763 | ||
14764 | /* Send the buffer to the chip. */ | |
14765 | ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1); | |
14766 | if (ret) { | |
2445e461 MC |
14767 | dev_err(&tp->pdev->dev, |
14768 | "%s: Buffer write failed. err = %d\n", | |
14769 | __func__, ret); | |
1da177e4 LT |
14770 | break; |
14771 | } | |
14772 | ||
14773 | #if 0 | |
14774 | /* validate data reached card RAM correctly. */ | |
14775 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) { | |
14776 | u32 val; | |
14777 | tg3_read_mem(tp, 0x2100 + (i*4), &val); | |
14778 | if (le32_to_cpu(val) != p[i]) { | |
2445e461 MC |
14779 | dev_err(&tp->pdev->dev, |
14780 | "%s: Buffer corrupted on device! " | |
14781 | "(%d != %d)\n", __func__, val, i); | |
1da177e4 LT |
14782 | /* ret = -ENODEV here? */ |
14783 | } | |
14784 | p[i] = 0; | |
14785 | } | |
14786 | #endif | |
14787 | /* Now read it back. */ | |
14788 | ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0); | |
14789 | if (ret) { | |
5129c3a3 MC |
14790 | dev_err(&tp->pdev->dev, "%s: Buffer read failed. " |
14791 | "err = %d\n", __func__, ret); | |
1da177e4 LT |
14792 | break; |
14793 | } | |
14794 | ||
14795 | /* Verify it. */ | |
14796 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) { | |
14797 | if (p[i] == i) | |
14798 | continue; | |
14799 | ||
59e6b434 DM |
14800 | if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != |
14801 | DMA_RWCTRL_WRITE_BNDRY_16) { | |
14802 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; | |
1da177e4 LT |
14803 | tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; |
14804 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
14805 | break; | |
14806 | } else { | |
2445e461 MC |
14807 | dev_err(&tp->pdev->dev, |
14808 | "%s: Buffer corrupted on read back! " | |
14809 | "(%d != %d)\n", __func__, p[i], i); | |
1da177e4 LT |
14810 | ret = -ENODEV; |
14811 | goto out; | |
14812 | } | |
14813 | } | |
14814 | ||
14815 | if (i == (TEST_BUFFER_SIZE / sizeof(u32))) { | |
14816 | /* Success. */ | |
14817 | ret = 0; | |
14818 | break; | |
14819 | } | |
14820 | } | |
59e6b434 DM |
14821 | if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != |
14822 | DMA_RWCTRL_WRITE_BNDRY_16) { | |
14823 | /* DMA test passed without adjusting DMA boundary, | |
6d1cfbab MC |
14824 | * now look for chipsets that are known to expose the |
14825 | * DMA bug without failing the test. | |
59e6b434 | 14826 | */ |
4143470c | 14827 | if (pci_dev_present(tg3_dma_wait_state_chipsets)) { |
6d1cfbab MC |
14828 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; |
14829 | tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; | |
859a5887 | 14830 | } else { |
6d1cfbab MC |
14831 | /* Safe to use the calculated DMA boundary. */ |
14832 | tp->dma_rwctrl = saved_dma_rwctrl; | |
859a5887 | 14833 | } |
6d1cfbab | 14834 | |
59e6b434 DM |
14835 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); |
14836 | } | |
1da177e4 LT |
14837 | |
14838 | out: | |
4bae65c8 | 14839 | dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma); |
1da177e4 LT |
14840 | out_nofree: |
14841 | return ret; | |
14842 | } | |
14843 | ||
1da177e4 LT |
14844 | static void __devinit tg3_init_bufmgr_config(struct tg3 *tp) |
14845 | { | |
63c3a66f | 14846 | if (tg3_flag(tp, 57765_PLUS)) { |
666bc831 MC |
14847 | tp->bufmgr_config.mbuf_read_dma_low_water = |
14848 | DEFAULT_MB_RDMA_LOW_WATER_5705; | |
14849 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
14850 | DEFAULT_MB_MACRX_LOW_WATER_57765; | |
14851 | tp->bufmgr_config.mbuf_high_water = | |
14852 | DEFAULT_MB_HIGH_WATER_57765; | |
14853 | ||
14854 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = | |
14855 | DEFAULT_MB_RDMA_LOW_WATER_5705; | |
14856 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = | |
14857 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765; | |
14858 | tp->bufmgr_config.mbuf_high_water_jumbo = | |
14859 | DEFAULT_MB_HIGH_WATER_JUMBO_57765; | |
63c3a66f | 14860 | } else if (tg3_flag(tp, 5705_PLUS)) { |
fdfec172 MC |
14861 | tp->bufmgr_config.mbuf_read_dma_low_water = |
14862 | DEFAULT_MB_RDMA_LOW_WATER_5705; | |
14863 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
14864 | DEFAULT_MB_MACRX_LOW_WATER_5705; | |
14865 | tp->bufmgr_config.mbuf_high_water = | |
14866 | DEFAULT_MB_HIGH_WATER_5705; | |
b5d3772c MC |
14867 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
14868 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
14869 | DEFAULT_MB_MACRX_LOW_WATER_5906; | |
14870 | tp->bufmgr_config.mbuf_high_water = | |
14871 | DEFAULT_MB_HIGH_WATER_5906; | |
14872 | } | |
fdfec172 MC |
14873 | |
14874 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = | |
14875 | DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780; | |
14876 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = | |
14877 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780; | |
14878 | tp->bufmgr_config.mbuf_high_water_jumbo = | |
14879 | DEFAULT_MB_HIGH_WATER_JUMBO_5780; | |
14880 | } else { | |
14881 | tp->bufmgr_config.mbuf_read_dma_low_water = | |
14882 | DEFAULT_MB_RDMA_LOW_WATER; | |
14883 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
14884 | DEFAULT_MB_MACRX_LOW_WATER; | |
14885 | tp->bufmgr_config.mbuf_high_water = | |
14886 | DEFAULT_MB_HIGH_WATER; | |
14887 | ||
14888 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = | |
14889 | DEFAULT_MB_RDMA_LOW_WATER_JUMBO; | |
14890 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = | |
14891 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO; | |
14892 | tp->bufmgr_config.mbuf_high_water_jumbo = | |
14893 | DEFAULT_MB_HIGH_WATER_JUMBO; | |
14894 | } | |
1da177e4 LT |
14895 | |
14896 | tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER; | |
14897 | tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER; | |
14898 | } | |
14899 | ||
14900 | static char * __devinit tg3_phy_string(struct tg3 *tp) | |
14901 | { | |
79eb6904 MC |
14902 | switch (tp->phy_id & TG3_PHY_ID_MASK) { |
14903 | case TG3_PHY_ID_BCM5400: return "5400"; | |
14904 | case TG3_PHY_ID_BCM5401: return "5401"; | |
14905 | case TG3_PHY_ID_BCM5411: return "5411"; | |
14906 | case TG3_PHY_ID_BCM5701: return "5701"; | |
14907 | case TG3_PHY_ID_BCM5703: return "5703"; | |
14908 | case TG3_PHY_ID_BCM5704: return "5704"; | |
14909 | case TG3_PHY_ID_BCM5705: return "5705"; | |
14910 | case TG3_PHY_ID_BCM5750: return "5750"; | |
14911 | case TG3_PHY_ID_BCM5752: return "5752"; | |
14912 | case TG3_PHY_ID_BCM5714: return "5714"; | |
14913 | case TG3_PHY_ID_BCM5780: return "5780"; | |
14914 | case TG3_PHY_ID_BCM5755: return "5755"; | |
14915 | case TG3_PHY_ID_BCM5787: return "5787"; | |
14916 | case TG3_PHY_ID_BCM5784: return "5784"; | |
14917 | case TG3_PHY_ID_BCM5756: return "5722/5756"; | |
14918 | case TG3_PHY_ID_BCM5906: return "5906"; | |
14919 | case TG3_PHY_ID_BCM5761: return "5761"; | |
14920 | case TG3_PHY_ID_BCM5718C: return "5718C"; | |
14921 | case TG3_PHY_ID_BCM5718S: return "5718S"; | |
14922 | case TG3_PHY_ID_BCM57765: return "57765"; | |
302b500b | 14923 | case TG3_PHY_ID_BCM5719C: return "5719C"; |
6418f2c1 | 14924 | case TG3_PHY_ID_BCM5720C: return "5720C"; |
79eb6904 | 14925 | case TG3_PHY_ID_BCM8002: return "8002/serdes"; |
1da177e4 LT |
14926 | case 0: return "serdes"; |
14927 | default: return "unknown"; | |
855e1111 | 14928 | } |
1da177e4 LT |
14929 | } |
14930 | ||
f9804ddb MC |
14931 | static char * __devinit tg3_bus_string(struct tg3 *tp, char *str) |
14932 | { | |
63c3a66f | 14933 | if (tg3_flag(tp, PCI_EXPRESS)) { |
f9804ddb MC |
14934 | strcpy(str, "PCI Express"); |
14935 | return str; | |
63c3a66f | 14936 | } else if (tg3_flag(tp, PCIX_MODE)) { |
f9804ddb MC |
14937 | u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f; |
14938 | ||
14939 | strcpy(str, "PCIX:"); | |
14940 | ||
14941 | if ((clock_ctrl == 7) || | |
14942 | ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) == | |
14943 | GRC_MISC_CFG_BOARD_ID_5704CIOBE)) | |
14944 | strcat(str, "133MHz"); | |
14945 | else if (clock_ctrl == 0) | |
14946 | strcat(str, "33MHz"); | |
14947 | else if (clock_ctrl == 2) | |
14948 | strcat(str, "50MHz"); | |
14949 | else if (clock_ctrl == 4) | |
14950 | strcat(str, "66MHz"); | |
14951 | else if (clock_ctrl == 6) | |
14952 | strcat(str, "100MHz"); | |
f9804ddb MC |
14953 | } else { |
14954 | strcpy(str, "PCI:"); | |
63c3a66f | 14955 | if (tg3_flag(tp, PCI_HIGH_SPEED)) |
f9804ddb MC |
14956 | strcat(str, "66MHz"); |
14957 | else | |
14958 | strcat(str, "33MHz"); | |
14959 | } | |
63c3a66f | 14960 | if (tg3_flag(tp, PCI_32BIT)) |
f9804ddb MC |
14961 | strcat(str, ":32-bit"); |
14962 | else | |
14963 | strcat(str, ":64-bit"); | |
14964 | return str; | |
14965 | } | |
14966 | ||
8c2dc7e1 | 14967 | static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp) |
1da177e4 LT |
14968 | { |
14969 | struct pci_dev *peer; | |
14970 | unsigned int func, devnr = tp->pdev->devfn & ~7; | |
14971 | ||
14972 | for (func = 0; func < 8; func++) { | |
14973 | peer = pci_get_slot(tp->pdev->bus, devnr | func); | |
14974 | if (peer && peer != tp->pdev) | |
14975 | break; | |
14976 | pci_dev_put(peer); | |
14977 | } | |
16fe9d74 MC |
14978 | /* 5704 can be configured in single-port mode, set peer to |
14979 | * tp->pdev in that case. | |
14980 | */ | |
14981 | if (!peer) { | |
14982 | peer = tp->pdev; | |
14983 | return peer; | |
14984 | } | |
1da177e4 LT |
14985 | |
14986 | /* | |
14987 | * We don't need to keep the refcount elevated; there's no way | |
14988 | * to remove one half of this device without removing the other | |
14989 | */ | |
14990 | pci_dev_put(peer); | |
14991 | ||
14992 | return peer; | |
14993 | } | |
14994 | ||
15f9850d DM |
14995 | static void __devinit tg3_init_coal(struct tg3 *tp) |
14996 | { | |
14997 | struct ethtool_coalesce *ec = &tp->coal; | |
14998 | ||
14999 | memset(ec, 0, sizeof(*ec)); | |
15000 | ec->cmd = ETHTOOL_GCOALESCE; | |
15001 | ec->rx_coalesce_usecs = LOW_RXCOL_TICKS; | |
15002 | ec->tx_coalesce_usecs = LOW_TXCOL_TICKS; | |
15003 | ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES; | |
15004 | ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES; | |
15005 | ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT; | |
15006 | ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT; | |
15007 | ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT; | |
15008 | ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT; | |
15009 | ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS; | |
15010 | ||
15011 | if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD | | |
15012 | HOSTCC_MODE_CLRTICK_TXBD)) { | |
15013 | ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS; | |
15014 | ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS; | |
15015 | ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS; | |
15016 | ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS; | |
15017 | } | |
d244c892 | 15018 | |
63c3a66f | 15019 | if (tg3_flag(tp, 5705_PLUS)) { |
d244c892 MC |
15020 | ec->rx_coalesce_usecs_irq = 0; |
15021 | ec->tx_coalesce_usecs_irq = 0; | |
15022 | ec->stats_block_coalesce_usecs = 0; | |
15023 | } | |
15f9850d DM |
15024 | } |
15025 | ||
7c7d64b8 SH |
15026 | static const struct net_device_ops tg3_netdev_ops = { |
15027 | .ndo_open = tg3_open, | |
15028 | .ndo_stop = tg3_close, | |
00829823 | 15029 | .ndo_start_xmit = tg3_start_xmit, |
511d2224 | 15030 | .ndo_get_stats64 = tg3_get_stats64, |
00829823 SH |
15031 | .ndo_validate_addr = eth_validate_addr, |
15032 | .ndo_set_multicast_list = tg3_set_rx_mode, | |
15033 | .ndo_set_mac_address = tg3_set_mac_addr, | |
15034 | .ndo_do_ioctl = tg3_ioctl, | |
15035 | .ndo_tx_timeout = tg3_tx_timeout, | |
15036 | .ndo_change_mtu = tg3_change_mtu, | |
dc668910 | 15037 | .ndo_fix_features = tg3_fix_features, |
06c03c02 | 15038 | .ndo_set_features = tg3_set_features, |
00829823 SH |
15039 | #ifdef CONFIG_NET_POLL_CONTROLLER |
15040 | .ndo_poll_controller = tg3_poll_controller, | |
15041 | #endif | |
15042 | }; | |
15043 | ||
1da177e4 LT |
15044 | static int __devinit tg3_init_one(struct pci_dev *pdev, |
15045 | const struct pci_device_id *ent) | |
15046 | { | |
1da177e4 LT |
15047 | struct net_device *dev; |
15048 | struct tg3 *tp; | |
646c9edd MC |
15049 | int i, err, pm_cap; |
15050 | u32 sndmbx, rcvmbx, intmbx; | |
f9804ddb | 15051 | char str[40]; |
72f2afb8 | 15052 | u64 dma_mask, persist_dma_mask; |
0da0606f | 15053 | u32 features = 0; |
1da177e4 | 15054 | |
05dbe005 | 15055 | printk_once(KERN_INFO "%s\n", version); |
1da177e4 LT |
15056 | |
15057 | err = pci_enable_device(pdev); | |
15058 | if (err) { | |
2445e461 | 15059 | dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); |
1da177e4 LT |
15060 | return err; |
15061 | } | |
15062 | ||
1da177e4 LT |
15063 | err = pci_request_regions(pdev, DRV_MODULE_NAME); |
15064 | if (err) { | |
2445e461 | 15065 | dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); |
1da177e4 LT |
15066 | goto err_out_disable_pdev; |
15067 | } | |
15068 | ||
15069 | pci_set_master(pdev); | |
15070 | ||
15071 | /* Find power-management capability. */ | |
15072 | pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); | |
15073 | if (pm_cap == 0) { | |
2445e461 MC |
15074 | dev_err(&pdev->dev, |
15075 | "Cannot find Power Management capability, aborting\n"); | |
1da177e4 LT |
15076 | err = -EIO; |
15077 | goto err_out_free_res; | |
15078 | } | |
15079 | ||
16821285 MC |
15080 | err = pci_set_power_state(pdev, PCI_D0); |
15081 | if (err) { | |
15082 | dev_err(&pdev->dev, "Transition to D0 failed, aborting\n"); | |
15083 | goto err_out_free_res; | |
15084 | } | |
15085 | ||
fe5f5787 | 15086 | dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS); |
1da177e4 | 15087 | if (!dev) { |
2445e461 | 15088 | dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n"); |
1da177e4 | 15089 | err = -ENOMEM; |
16821285 | 15090 | goto err_out_power_down; |
1da177e4 LT |
15091 | } |
15092 | ||
1da177e4 LT |
15093 | SET_NETDEV_DEV(dev, &pdev->dev); |
15094 | ||
1da177e4 LT |
15095 | tp = netdev_priv(dev); |
15096 | tp->pdev = pdev; | |
15097 | tp->dev = dev; | |
15098 | tp->pm_cap = pm_cap; | |
1da177e4 LT |
15099 | tp->rx_mode = TG3_DEF_RX_MODE; |
15100 | tp->tx_mode = TG3_DEF_TX_MODE; | |
8ef21428 | 15101 | |
1da177e4 LT |
15102 | if (tg3_debug > 0) |
15103 | tp->msg_enable = tg3_debug; | |
15104 | else | |
15105 | tp->msg_enable = TG3_DEF_MSG_ENABLE; | |
15106 | ||
15107 | /* The word/byte swap controls here control register access byte | |
15108 | * swapping. DMA data byte swapping is controlled in the GRC_MODE | |
15109 | * setting below. | |
15110 | */ | |
15111 | tp->misc_host_ctrl = | |
15112 | MISC_HOST_CTRL_MASK_PCI_INT | | |
15113 | MISC_HOST_CTRL_WORD_SWAP | | |
15114 | MISC_HOST_CTRL_INDIR_ACCESS | | |
15115 | MISC_HOST_CTRL_PCISTATE_RW; | |
15116 | ||
15117 | /* The NONFRM (non-frame) byte/word swap controls take effect | |
15118 | * on descriptor entries, anything which isn't packet data. | |
15119 | * | |
15120 | * The StrongARM chips on the board (one for tx, one for rx) | |
15121 | * are running in big-endian mode. | |
15122 | */ | |
15123 | tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA | | |
15124 | GRC_MODE_WSWAP_NONFRM_DATA); | |
15125 | #ifdef __BIG_ENDIAN | |
15126 | tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA; | |
15127 | #endif | |
15128 | spin_lock_init(&tp->lock); | |
1da177e4 | 15129 | spin_lock_init(&tp->indirect_lock); |
c4028958 | 15130 | INIT_WORK(&tp->reset_task, tg3_reset_task); |
1da177e4 | 15131 | |
d5fe488a | 15132 | tp->regs = pci_ioremap_bar(pdev, BAR_0); |
ab0049b4 | 15133 | if (!tp->regs) { |
ab96b241 | 15134 | dev_err(&pdev->dev, "Cannot map device registers, aborting\n"); |
1da177e4 LT |
15135 | err = -ENOMEM; |
15136 | goto err_out_free_dev; | |
15137 | } | |
15138 | ||
c9cab24e MC |
15139 | if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || |
15140 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E || | |
15141 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S || | |
15142 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE || | |
15143 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || | |
15144 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 || | |
15145 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 || | |
15146 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720) { | |
15147 | tg3_flag_set(tp, ENABLE_APE); | |
15148 | tp->aperegs = pci_ioremap_bar(pdev, BAR_2); | |
15149 | if (!tp->aperegs) { | |
15150 | dev_err(&pdev->dev, | |
15151 | "Cannot map APE registers, aborting\n"); | |
15152 | err = -ENOMEM; | |
15153 | goto err_out_iounmap; | |
15154 | } | |
15155 | } | |
15156 | ||
1da177e4 LT |
15157 | tp->rx_pending = TG3_DEF_RX_RING_PENDING; |
15158 | tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING; | |
1da177e4 | 15159 | |
1da177e4 | 15160 | dev->ethtool_ops = &tg3_ethtool_ops; |
1da177e4 | 15161 | dev->watchdog_timeo = TG3_TX_TIMEOUT; |
2ffcc981 | 15162 | dev->netdev_ops = &tg3_netdev_ops; |
1da177e4 | 15163 | dev->irq = pdev->irq; |
1da177e4 LT |
15164 | |
15165 | err = tg3_get_invariants(tp); | |
15166 | if (err) { | |
ab96b241 MC |
15167 | dev_err(&pdev->dev, |
15168 | "Problem fetching invariants of chip, aborting\n"); | |
c9cab24e | 15169 | goto err_out_apeunmap; |
1da177e4 LT |
15170 | } |
15171 | ||
4a29cc2e MC |
15172 | /* The EPB bridge inside 5714, 5715, and 5780 and any |
15173 | * device behind the EPB cannot support DMA addresses > 40-bit. | |
72f2afb8 MC |
15174 | * On 64-bit systems with IOMMU, use 40-bit dma_mask. |
15175 | * On 64-bit systems without IOMMU, use 64-bit dma_mask and | |
15176 | * do DMA address check in tg3_start_xmit(). | |
15177 | */ | |
63c3a66f | 15178 | if (tg3_flag(tp, IS_5788)) |
284901a9 | 15179 | persist_dma_mask = dma_mask = DMA_BIT_MASK(32); |
63c3a66f | 15180 | else if (tg3_flag(tp, 40BIT_DMA_BUG)) { |
50cf156a | 15181 | persist_dma_mask = dma_mask = DMA_BIT_MASK(40); |
72f2afb8 | 15182 | #ifdef CONFIG_HIGHMEM |
6a35528a | 15183 | dma_mask = DMA_BIT_MASK(64); |
72f2afb8 | 15184 | #endif |
4a29cc2e | 15185 | } else |
6a35528a | 15186 | persist_dma_mask = dma_mask = DMA_BIT_MASK(64); |
72f2afb8 MC |
15187 | |
15188 | /* Configure DMA attributes. */ | |
284901a9 | 15189 | if (dma_mask > DMA_BIT_MASK(32)) { |
72f2afb8 MC |
15190 | err = pci_set_dma_mask(pdev, dma_mask); |
15191 | if (!err) { | |
0da0606f | 15192 | features |= NETIF_F_HIGHDMA; |
72f2afb8 MC |
15193 | err = pci_set_consistent_dma_mask(pdev, |
15194 | persist_dma_mask); | |
15195 | if (err < 0) { | |
ab96b241 MC |
15196 | dev_err(&pdev->dev, "Unable to obtain 64 bit " |
15197 | "DMA for consistent allocations\n"); | |
c9cab24e | 15198 | goto err_out_apeunmap; |
72f2afb8 MC |
15199 | } |
15200 | } | |
15201 | } | |
284901a9 YH |
15202 | if (err || dma_mask == DMA_BIT_MASK(32)) { |
15203 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
72f2afb8 | 15204 | if (err) { |
ab96b241 MC |
15205 | dev_err(&pdev->dev, |
15206 | "No usable DMA configuration, aborting\n"); | |
c9cab24e | 15207 | goto err_out_apeunmap; |
72f2afb8 MC |
15208 | } |
15209 | } | |
15210 | ||
fdfec172 | 15211 | tg3_init_bufmgr_config(tp); |
1da177e4 | 15212 | |
0da0606f MC |
15213 | features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; |
15214 | ||
15215 | /* 5700 B0 chips do not support checksumming correctly due | |
15216 | * to hardware bugs. | |
15217 | */ | |
15218 | if (tp->pci_chip_rev_id != CHIPREV_ID_5700_B0) { | |
15219 | features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM; | |
15220 | ||
15221 | if (tg3_flag(tp, 5755_PLUS)) | |
15222 | features |= NETIF_F_IPV6_CSUM; | |
15223 | } | |
15224 | ||
4e3a7aaa MC |
15225 | /* TSO is on by default on chips that support hardware TSO. |
15226 | * Firmware TSO on older chips gives lower performance, so it | |
15227 | * is off by default, but can be enabled using ethtool. | |
15228 | */ | |
63c3a66f JP |
15229 | if ((tg3_flag(tp, HW_TSO_1) || |
15230 | tg3_flag(tp, HW_TSO_2) || | |
15231 | tg3_flag(tp, HW_TSO_3)) && | |
0da0606f MC |
15232 | (features & NETIF_F_IP_CSUM)) |
15233 | features |= NETIF_F_TSO; | |
63c3a66f | 15234 | if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) { |
0da0606f MC |
15235 | if (features & NETIF_F_IPV6_CSUM) |
15236 | features |= NETIF_F_TSO6; | |
63c3a66f | 15237 | if (tg3_flag(tp, HW_TSO_3) || |
e849cdc3 | 15238 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
57e6983c MC |
15239 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && |
15240 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) || | |
63c3a66f | 15241 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
dc668910 | 15242 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) |
0da0606f | 15243 | features |= NETIF_F_TSO_ECN; |
b0026624 | 15244 | } |
1da177e4 | 15245 | |
d542fe27 MC |
15246 | dev->features |= features; |
15247 | dev->vlan_features |= features; | |
15248 | ||
06c03c02 MB |
15249 | /* |
15250 | * Add loopback capability only for a subset of devices that support | |
15251 | * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY | |
15252 | * loopback for the remaining devices. | |
15253 | */ | |
15254 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780 && | |
15255 | !tg3_flag(tp, CPMU_PRESENT)) | |
15256 | /* Add the loopback capability */ | |
0da0606f MC |
15257 | features |= NETIF_F_LOOPBACK; |
15258 | ||
0da0606f | 15259 | dev->hw_features |= features; |
06c03c02 | 15260 | |
1da177e4 | 15261 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 && |
63c3a66f | 15262 | !tg3_flag(tp, TSO_CAPABLE) && |
1da177e4 | 15263 | !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) { |
63c3a66f | 15264 | tg3_flag_set(tp, MAX_RXPEND_64); |
1da177e4 LT |
15265 | tp->rx_pending = 63; |
15266 | } | |
15267 | ||
1da177e4 LT |
15268 | err = tg3_get_device_address(tp); |
15269 | if (err) { | |
ab96b241 MC |
15270 | dev_err(&pdev->dev, |
15271 | "Could not obtain valid ethernet address, aborting\n"); | |
c9cab24e | 15272 | goto err_out_apeunmap; |
c88864df MC |
15273 | } |
15274 | ||
1da177e4 LT |
15275 | /* |
15276 | * Reset chip in case UNDI or EFI driver did not shutdown | |
15277 | * DMA self test will enable WDMAC and we'll see (spurious) | |
15278 | * pending DMA on the PCI bus at that point. | |
15279 | */ | |
15280 | if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) || | |
15281 | (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { | |
1da177e4 | 15282 | tw32(MEMARB_MODE, MEMARB_MODE_ENABLE); |
944d980e | 15283 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 LT |
15284 | } |
15285 | ||
15286 | err = tg3_test_dma(tp); | |
15287 | if (err) { | |
ab96b241 | 15288 | dev_err(&pdev->dev, "DMA engine test failed, aborting\n"); |
c88864df | 15289 | goto err_out_apeunmap; |
1da177e4 LT |
15290 | } |
15291 | ||
78f90dcf MC |
15292 | intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW; |
15293 | rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW; | |
15294 | sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW; | |
6fd45cb8 | 15295 | for (i = 0; i < tp->irq_max; i++) { |
78f90dcf MC |
15296 | struct tg3_napi *tnapi = &tp->napi[i]; |
15297 | ||
15298 | tnapi->tp = tp; | |
15299 | tnapi->tx_pending = TG3_DEF_TX_RING_PENDING; | |
15300 | ||
15301 | tnapi->int_mbox = intmbx; | |
15302 | if (i < 4) | |
15303 | intmbx += 0x8; | |
15304 | else | |
15305 | intmbx += 0x4; | |
15306 | ||
15307 | tnapi->consmbox = rcvmbx; | |
15308 | tnapi->prodmbox = sndmbx; | |
15309 | ||
66cfd1bd | 15310 | if (i) |
78f90dcf | 15311 | tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1); |
66cfd1bd | 15312 | else |
78f90dcf | 15313 | tnapi->coal_now = HOSTCC_MODE_NOW; |
78f90dcf | 15314 | |
63c3a66f | 15315 | if (!tg3_flag(tp, SUPPORT_MSIX)) |
78f90dcf MC |
15316 | break; |
15317 | ||
15318 | /* | |
15319 | * If we support MSIX, we'll be using RSS. If we're using | |
15320 | * RSS, the first vector only handles link interrupts and the | |
15321 | * remaining vectors handle rx and tx interrupts. Reuse the | |
15322 | * mailbox values for the next iteration. The values we setup | |
15323 | * above are still useful for the single vectored mode. | |
15324 | */ | |
15325 | if (!i) | |
15326 | continue; | |
15327 | ||
15328 | rcvmbx += 0x8; | |
15329 | ||
15330 | if (sndmbx & 0x4) | |
15331 | sndmbx -= 0x4; | |
15332 | else | |
15333 | sndmbx += 0xc; | |
15334 | } | |
15335 | ||
15f9850d DM |
15336 | tg3_init_coal(tp); |
15337 | ||
c49a1561 MC |
15338 | pci_set_drvdata(pdev, dev); |
15339 | ||
1da177e4 LT |
15340 | err = register_netdev(dev); |
15341 | if (err) { | |
ab96b241 | 15342 | dev_err(&pdev->dev, "Cannot register net device, aborting\n"); |
0d3031d9 | 15343 | goto err_out_apeunmap; |
1da177e4 LT |
15344 | } |
15345 | ||
05dbe005 JP |
15346 | netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n", |
15347 | tp->board_part_number, | |
15348 | tp->pci_chip_rev_id, | |
15349 | tg3_bus_string(tp, str), | |
15350 | dev->dev_addr); | |
1da177e4 | 15351 | |
f07e9af3 | 15352 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { |
3f0e3ad7 MC |
15353 | struct phy_device *phydev; |
15354 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; | |
5129c3a3 MC |
15355 | netdev_info(dev, |
15356 | "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n", | |
05dbe005 | 15357 | phydev->drv->name, dev_name(&phydev->dev)); |
f07e9af3 MC |
15358 | } else { |
15359 | char *ethtype; | |
15360 | ||
15361 | if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) | |
15362 | ethtype = "10/100Base-TX"; | |
15363 | else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) | |
15364 | ethtype = "1000Base-SX"; | |
15365 | else | |
15366 | ethtype = "10/100/1000Base-T"; | |
15367 | ||
5129c3a3 | 15368 | netdev_info(dev, "attached PHY is %s (%s Ethernet) " |
47007831 MC |
15369 | "(WireSpeed[%d], EEE[%d])\n", |
15370 | tg3_phy_string(tp), ethtype, | |
15371 | (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0, | |
15372 | (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0); | |
f07e9af3 | 15373 | } |
05dbe005 JP |
15374 | |
15375 | netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n", | |
dc668910 | 15376 | (dev->features & NETIF_F_RXCSUM) != 0, |
63c3a66f | 15377 | tg3_flag(tp, USE_LINKCHG_REG) != 0, |
f07e9af3 | 15378 | (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0, |
63c3a66f JP |
15379 | tg3_flag(tp, ENABLE_ASF) != 0, |
15380 | tg3_flag(tp, TSO_CAPABLE) != 0); | |
05dbe005 JP |
15381 | netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n", |
15382 | tp->dma_rwctrl, | |
15383 | pdev->dma_mask == DMA_BIT_MASK(32) ? 32 : | |
15384 | ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64); | |
1da177e4 | 15385 | |
b45aa2f6 MC |
15386 | pci_save_state(pdev); |
15387 | ||
1da177e4 LT |
15388 | return 0; |
15389 | ||
0d3031d9 MC |
15390 | err_out_apeunmap: |
15391 | if (tp->aperegs) { | |
15392 | iounmap(tp->aperegs); | |
15393 | tp->aperegs = NULL; | |
15394 | } | |
15395 | ||
1da177e4 | 15396 | err_out_iounmap: |
6892914f MC |
15397 | if (tp->regs) { |
15398 | iounmap(tp->regs); | |
22abe310 | 15399 | tp->regs = NULL; |
6892914f | 15400 | } |
1da177e4 LT |
15401 | |
15402 | err_out_free_dev: | |
15403 | free_netdev(dev); | |
15404 | ||
16821285 MC |
15405 | err_out_power_down: |
15406 | pci_set_power_state(pdev, PCI_D3hot); | |
15407 | ||
1da177e4 LT |
15408 | err_out_free_res: |
15409 | pci_release_regions(pdev); | |
15410 | ||
15411 | err_out_disable_pdev: | |
15412 | pci_disable_device(pdev); | |
15413 | pci_set_drvdata(pdev, NULL); | |
15414 | return err; | |
15415 | } | |
15416 | ||
15417 | static void __devexit tg3_remove_one(struct pci_dev *pdev) | |
15418 | { | |
15419 | struct net_device *dev = pci_get_drvdata(pdev); | |
15420 | ||
15421 | if (dev) { | |
15422 | struct tg3 *tp = netdev_priv(dev); | |
15423 | ||
077f849d JSR |
15424 | if (tp->fw) |
15425 | release_firmware(tp->fw); | |
15426 | ||
23f333a2 | 15427 | cancel_work_sync(&tp->reset_task); |
158d7abd | 15428 | |
63c3a66f | 15429 | if (!tg3_flag(tp, USE_PHYLIB)) { |
b02fd9e3 | 15430 | tg3_phy_fini(tp); |
158d7abd | 15431 | tg3_mdio_fini(tp); |
b02fd9e3 | 15432 | } |
158d7abd | 15433 | |
1da177e4 | 15434 | unregister_netdev(dev); |
0d3031d9 MC |
15435 | if (tp->aperegs) { |
15436 | iounmap(tp->aperegs); | |
15437 | tp->aperegs = NULL; | |
15438 | } | |
6892914f MC |
15439 | if (tp->regs) { |
15440 | iounmap(tp->regs); | |
22abe310 | 15441 | tp->regs = NULL; |
6892914f | 15442 | } |
1da177e4 LT |
15443 | free_netdev(dev); |
15444 | pci_release_regions(pdev); | |
15445 | pci_disable_device(pdev); | |
15446 | pci_set_drvdata(pdev, NULL); | |
15447 | } | |
15448 | } | |
15449 | ||
aa6027ca | 15450 | #ifdef CONFIG_PM_SLEEP |
c866b7ea | 15451 | static int tg3_suspend(struct device *device) |
1da177e4 | 15452 | { |
c866b7ea | 15453 | struct pci_dev *pdev = to_pci_dev(device); |
1da177e4 LT |
15454 | struct net_device *dev = pci_get_drvdata(pdev); |
15455 | struct tg3 *tp = netdev_priv(dev); | |
15456 | int err; | |
15457 | ||
15458 | if (!netif_running(dev)) | |
15459 | return 0; | |
15460 | ||
23f333a2 | 15461 | flush_work_sync(&tp->reset_task); |
b02fd9e3 | 15462 | tg3_phy_stop(tp); |
1da177e4 LT |
15463 | tg3_netif_stop(tp); |
15464 | ||
15465 | del_timer_sync(&tp->timer); | |
15466 | ||
f47c11ee | 15467 | tg3_full_lock(tp, 1); |
1da177e4 | 15468 | tg3_disable_ints(tp); |
f47c11ee | 15469 | tg3_full_unlock(tp); |
1da177e4 LT |
15470 | |
15471 | netif_device_detach(dev); | |
15472 | ||
f47c11ee | 15473 | tg3_full_lock(tp, 0); |
944d980e | 15474 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
63c3a66f | 15475 | tg3_flag_clear(tp, INIT_COMPLETE); |
f47c11ee | 15476 | tg3_full_unlock(tp); |
1da177e4 | 15477 | |
c866b7ea | 15478 | err = tg3_power_down_prepare(tp); |
1da177e4 | 15479 | if (err) { |
b02fd9e3 MC |
15480 | int err2; |
15481 | ||
f47c11ee | 15482 | tg3_full_lock(tp, 0); |
1da177e4 | 15483 | |
63c3a66f | 15484 | tg3_flag_set(tp, INIT_COMPLETE); |
b02fd9e3 MC |
15485 | err2 = tg3_restart_hw(tp, 1); |
15486 | if (err2) | |
b9ec6c1b | 15487 | goto out; |
1da177e4 LT |
15488 | |
15489 | tp->timer.expires = jiffies + tp->timer_offset; | |
15490 | add_timer(&tp->timer); | |
15491 | ||
15492 | netif_device_attach(dev); | |
15493 | tg3_netif_start(tp); | |
15494 | ||
b9ec6c1b | 15495 | out: |
f47c11ee | 15496 | tg3_full_unlock(tp); |
b02fd9e3 MC |
15497 | |
15498 | if (!err2) | |
15499 | tg3_phy_start(tp); | |
1da177e4 LT |
15500 | } |
15501 | ||
15502 | return err; | |
15503 | } | |
15504 | ||
c866b7ea | 15505 | static int tg3_resume(struct device *device) |
1da177e4 | 15506 | { |
c866b7ea | 15507 | struct pci_dev *pdev = to_pci_dev(device); |
1da177e4 LT |
15508 | struct net_device *dev = pci_get_drvdata(pdev); |
15509 | struct tg3 *tp = netdev_priv(dev); | |
15510 | int err; | |
15511 | ||
15512 | if (!netif_running(dev)) | |
15513 | return 0; | |
15514 | ||
1da177e4 LT |
15515 | netif_device_attach(dev); |
15516 | ||
f47c11ee | 15517 | tg3_full_lock(tp, 0); |
1da177e4 | 15518 | |
63c3a66f | 15519 | tg3_flag_set(tp, INIT_COMPLETE); |
b9ec6c1b MC |
15520 | err = tg3_restart_hw(tp, 1); |
15521 | if (err) | |
15522 | goto out; | |
1da177e4 LT |
15523 | |
15524 | tp->timer.expires = jiffies + tp->timer_offset; | |
15525 | add_timer(&tp->timer); | |
15526 | ||
1da177e4 LT |
15527 | tg3_netif_start(tp); |
15528 | ||
b9ec6c1b | 15529 | out: |
f47c11ee | 15530 | tg3_full_unlock(tp); |
1da177e4 | 15531 | |
b02fd9e3 MC |
15532 | if (!err) |
15533 | tg3_phy_start(tp); | |
15534 | ||
b9ec6c1b | 15535 | return err; |
1da177e4 LT |
15536 | } |
15537 | ||
c866b7ea | 15538 | static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume); |
aa6027ca ED |
15539 | #define TG3_PM_OPS (&tg3_pm_ops) |
15540 | ||
15541 | #else | |
15542 | ||
15543 | #define TG3_PM_OPS NULL | |
15544 | ||
15545 | #endif /* CONFIG_PM_SLEEP */ | |
c866b7ea | 15546 | |
b45aa2f6 MC |
15547 | /** |
15548 | * tg3_io_error_detected - called when PCI error is detected | |
15549 | * @pdev: Pointer to PCI device | |
15550 | * @state: The current pci connection state | |
15551 | * | |
15552 | * This function is called after a PCI bus error affecting | |
15553 | * this device has been detected. | |
15554 | */ | |
15555 | static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev, | |
15556 | pci_channel_state_t state) | |
15557 | { | |
15558 | struct net_device *netdev = pci_get_drvdata(pdev); | |
15559 | struct tg3 *tp = netdev_priv(netdev); | |
15560 | pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET; | |
15561 | ||
15562 | netdev_info(netdev, "PCI I/O error detected\n"); | |
15563 | ||
15564 | rtnl_lock(); | |
15565 | ||
15566 | if (!netif_running(netdev)) | |
15567 | goto done; | |
15568 | ||
15569 | tg3_phy_stop(tp); | |
15570 | ||
15571 | tg3_netif_stop(tp); | |
15572 | ||
15573 | del_timer_sync(&tp->timer); | |
63c3a66f | 15574 | tg3_flag_clear(tp, RESTART_TIMER); |
b45aa2f6 MC |
15575 | |
15576 | /* Want to make sure that the reset task doesn't run */ | |
15577 | cancel_work_sync(&tp->reset_task); | |
63c3a66f JP |
15578 | tg3_flag_clear(tp, TX_RECOVERY_PENDING); |
15579 | tg3_flag_clear(tp, RESTART_TIMER); | |
b45aa2f6 MC |
15580 | |
15581 | netif_device_detach(netdev); | |
15582 | ||
15583 | /* Clean up software state, even if MMIO is blocked */ | |
15584 | tg3_full_lock(tp, 0); | |
15585 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); | |
15586 | tg3_full_unlock(tp); | |
15587 | ||
15588 | done: | |
15589 | if (state == pci_channel_io_perm_failure) | |
15590 | err = PCI_ERS_RESULT_DISCONNECT; | |
15591 | else | |
15592 | pci_disable_device(pdev); | |
15593 | ||
15594 | rtnl_unlock(); | |
15595 | ||
15596 | return err; | |
15597 | } | |
15598 | ||
15599 | /** | |
15600 | * tg3_io_slot_reset - called after the pci bus has been reset. | |
15601 | * @pdev: Pointer to PCI device | |
15602 | * | |
15603 | * Restart the card from scratch, as if from a cold-boot. | |
15604 | * At this point, the card has exprienced a hard reset, | |
15605 | * followed by fixups by BIOS, and has its config space | |
15606 | * set up identically to what it was at cold boot. | |
15607 | */ | |
15608 | static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev) | |
15609 | { | |
15610 | struct net_device *netdev = pci_get_drvdata(pdev); | |
15611 | struct tg3 *tp = netdev_priv(netdev); | |
15612 | pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT; | |
15613 | int err; | |
15614 | ||
15615 | rtnl_lock(); | |
15616 | ||
15617 | if (pci_enable_device(pdev)) { | |
15618 | netdev_err(netdev, "Cannot re-enable PCI device after reset.\n"); | |
15619 | goto done; | |
15620 | } | |
15621 | ||
15622 | pci_set_master(pdev); | |
15623 | pci_restore_state(pdev); | |
15624 | pci_save_state(pdev); | |
15625 | ||
15626 | if (!netif_running(netdev)) { | |
15627 | rc = PCI_ERS_RESULT_RECOVERED; | |
15628 | goto done; | |
15629 | } | |
15630 | ||
15631 | err = tg3_power_up(tp); | |
bed9829f | 15632 | if (err) |
b45aa2f6 | 15633 | goto done; |
b45aa2f6 MC |
15634 | |
15635 | rc = PCI_ERS_RESULT_RECOVERED; | |
15636 | ||
15637 | done: | |
15638 | rtnl_unlock(); | |
15639 | ||
15640 | return rc; | |
15641 | } | |
15642 | ||
15643 | /** | |
15644 | * tg3_io_resume - called when traffic can start flowing again. | |
15645 | * @pdev: Pointer to PCI device | |
15646 | * | |
15647 | * This callback is called when the error recovery driver tells | |
15648 | * us that its OK to resume normal operation. | |
15649 | */ | |
15650 | static void tg3_io_resume(struct pci_dev *pdev) | |
15651 | { | |
15652 | struct net_device *netdev = pci_get_drvdata(pdev); | |
15653 | struct tg3 *tp = netdev_priv(netdev); | |
15654 | int err; | |
15655 | ||
15656 | rtnl_lock(); | |
15657 | ||
15658 | if (!netif_running(netdev)) | |
15659 | goto done; | |
15660 | ||
15661 | tg3_full_lock(tp, 0); | |
63c3a66f | 15662 | tg3_flag_set(tp, INIT_COMPLETE); |
b45aa2f6 MC |
15663 | err = tg3_restart_hw(tp, 1); |
15664 | tg3_full_unlock(tp); | |
15665 | if (err) { | |
15666 | netdev_err(netdev, "Cannot restart hardware after reset.\n"); | |
15667 | goto done; | |
15668 | } | |
15669 | ||
15670 | netif_device_attach(netdev); | |
15671 | ||
15672 | tp->timer.expires = jiffies + tp->timer_offset; | |
15673 | add_timer(&tp->timer); | |
15674 | ||
15675 | tg3_netif_start(tp); | |
15676 | ||
15677 | tg3_phy_start(tp); | |
15678 | ||
15679 | done: | |
15680 | rtnl_unlock(); | |
15681 | } | |
15682 | ||
15683 | static struct pci_error_handlers tg3_err_handler = { | |
15684 | .error_detected = tg3_io_error_detected, | |
15685 | .slot_reset = tg3_io_slot_reset, | |
15686 | .resume = tg3_io_resume | |
15687 | }; | |
15688 | ||
1da177e4 LT |
15689 | static struct pci_driver tg3_driver = { |
15690 | .name = DRV_MODULE_NAME, | |
15691 | .id_table = tg3_pci_tbl, | |
15692 | .probe = tg3_init_one, | |
15693 | .remove = __devexit_p(tg3_remove_one), | |
b45aa2f6 | 15694 | .err_handler = &tg3_err_handler, |
aa6027ca | 15695 | .driver.pm = TG3_PM_OPS, |
1da177e4 LT |
15696 | }; |
15697 | ||
15698 | static int __init tg3_init(void) | |
15699 | { | |
29917620 | 15700 | return pci_register_driver(&tg3_driver); |
1da177e4 LT |
15701 | } |
15702 | ||
15703 | static void __exit tg3_cleanup(void) | |
15704 | { | |
15705 | pci_unregister_driver(&tg3_driver); | |
15706 | } | |
15707 | ||
15708 | module_init(tg3_init); | |
15709 | module_exit(tg3_cleanup); |