[linux-block.git] / drivers / net / tehuti.h

/*
 * Tehuti Networks(R) Network Driver
 * Copyright (C) 2007 Tehuti Networks Ltd. All rights reserved
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#ifndef _TEHUTI_H
#define _TEHUTI_H

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/ethtool.h>
#include <linux/mii.h>
#include <linux/crc32.h>
#include <linux/uaccess.h>
#include <linux/in.h>
#include <linux/ip.h>
#include <linux/tcp.h>
#include <linux/sched.h>
#include <linux/tty.h>
#include <linux/if_vlan.h>
#include <linux/interrupt.h>
#include <linux/vmalloc.h>
#include <linux/firmware.h>
#include <asm/byteorder.h>
#include <linux/dma-mapping.h>

/* Compile Time Switches */
/* start */
#define BDX_TSO
#define BDX_LLTX
#define BDX_DELAY_WPTR
/* #define BDX_MSI */
/* end */

#if !defined CONFIG_PCI_MSI
#   undef BDX_MSI
#endif

#define BDX_DEF_MSG_ENABLE	(NETIF_MSG_DRV          | \
				NETIF_MSG_PROBE        | \
				NETIF_MSG_LINK)

/* ioctl ops */
#define BDX_OP_READ  1
#define BDX_OP_WRITE 2

/* RX copy break size */
#define BDX_COPYBREAK    257

#define DRIVER_AUTHOR     "Tehuti Networks(R)"
#define BDX_DRV_DESC      "Tehuti Networks(R) Network Driver"
#define BDX_DRV_NAME      "tehuti"
#define BDX_NIC_NAME      "Tehuti 10 Giga TOE SmartNIC"
#define BDX_NIC2PORT_NAME "Tehuti 2-Port 10 Giga TOE SmartNIC"
#define BDX_DRV_VERSION   "7.29.3"

#ifdef BDX_MSI
#    define BDX_MSI_STRING "msi "
#else
#    define BDX_MSI_STRING ""
#endif

/* netdev tx queue len for Luxor. default value is, btw, 1000
 * ifcontig eth1 txqueuelen 3000 - to change it at runtime */
#define BDX_NDEV_TXQ_LEN 3000

#define FIFO_SIZE  4096
#define FIFO_EXTRA_SPACE            1024

#define MIN(x, y)  ((x) < (y) ? (x) : (y))

#if BITS_PER_LONG == 64
#    define H32_64(x)  (u32) ((u64)(x) >> 32)
#    define L32_64(x)  (u32) ((u64)(x) & 0xffffffff)
#elif BITS_PER_LONG == 32
#    define H32_64(x)  0
#    define L32_64(x)  ((u32) (x))
#else				/* BITS_PER_LONG == ?? */
#    error BITS_PER_LONG is undefined. Must be 64 or 32
#endif				/* BITS_PER_LONG */

#ifdef __BIG_ENDIAN
#   define CPU_CHIP_SWAP32(x) swab32(x)
#   define CPU_CHIP_SWAP16(x) swab16(x)
#else
#   define CPU_CHIP_SWAP32(x) (x)
#   define CPU_CHIP_SWAP16(x) (x)
#endif

#define READ_REG(pp, reg)         readl(pp->pBdxRegs + reg)
#define WRITE_REG(pp, reg, val)   writel(val, pp->pBdxRegs + reg)

#ifndef NET_IP_ALIGN
#   define NET_IP_ALIGN 2
#endif

#ifndef NETDEV_TX_OK
#   define NETDEV_TX_OK 0
#endif

#define LUXOR_MAX_PORT     2
#define BDX_MAX_RX_DONE    150
#define BDX_TXF_DESC_SZ    16
#define BDX_MAX_TX_LEVEL   (priv->txd_fifo0.m.memsz - 16)
#define BDX_MIN_TX_LEVEL   256
#define BDX_NO_UPD_PACKETS 40

struct pci_nic {
	int port_num;
	void __iomem *regs;
	int irq_type;
	struct bdx_priv *priv[LUXOR_MAX_PORT];
};

enum { IRQ_INTX, IRQ_MSI, IRQ_MSIX };

#define PCK_TH_MULT   128
#define INT_COAL_MULT 2

#define BITS_MASK(nbits)			((1<<nbits)-1)
#define GET_BITS_SHIFT(x, nbits, nshift)	(((x)>>nshift)&BITS_MASK(nbits))
#define BITS_SHIFT_MASK(nbits, nshift)		(BITS_MASK(nbits)<<nshift)
#define BITS_SHIFT_VAL(x, nbits, nshift)	(((x)&BITS_MASK(nbits))<<nshift)
#define BITS_SHIFT_CLEAR(x, nbits, nshift)	\
	((x)&(~BITS_SHIFT_MASK(nbits, nshift)))

#define GET_INT_COAL(x)				GET_BITS_SHIFT(x, 15, 0)
#define GET_INT_COAL_RC(x)			GET_BITS_SHIFT(x, 1, 15)
#define GET_RXF_TH(x)				GET_BITS_SHIFT(x, 4, 16)
#define GET_PCK_TH(x)				GET_BITS_SHIFT(x, 4, 20)

#define INT_REG_VAL(coal, coal_rc, rxf_th, pck_th)	\
	((coal)|((coal_rc)<<15)|((rxf_th)<<16)|((pck_th)<<20))

struct fifo {
	dma_addr_t da;		/* physical address of fifo (used by HW) */
	char *va;		/* virtual address of fifo (used by SW) */
	u32 rptr, wptr;		/* cached values of RPTR and WPTR registers,
				   they're 32 bits on both 32 and 64 archs */
	u16 reg_CFG0, reg_CFG1;
	u16 reg_RPTR, reg_WPTR;
	u16 memsz;		/* memory size allocated for fifo */
	u16 size_mask;
	u16 pktsz;		/* skb packet size to allocate */
	u16 rcvno;		/* number of buffers that come from this RXF */
};

struct txf_fifo {
	struct fifo m;		/* minimal set of variables used by all fifos */
};

struct txd_fifo {
	struct fifo m;		/* minimal set of variables used by all fifos */
};

struct rxf_fifo {
	struct fifo m;		/* minimal set of variables used by all fifos */
};

struct rxd_fifo {
	struct fifo m;		/* minimal set of variables used by all fifos */
};

struct rx_map {
	u64 dma;
	struct sk_buff *skb;
};

struct rxdb {
	int *stack;
	struct rx_map *elems;
	int nelem;
	int top;
};

union bdx_dma_addr {
	dma_addr_t dma;
	struct sk_buff *skb;
};

/* Entry in the db.
 * if len == 0 addr is dma
 * if len != 0 addr is skb */
struct tx_map {
	union bdx_dma_addr addr;
	int len;
};

/* tx database - implemented as circular fifo buffer*/
struct txdb {
	struct tx_map *start;	/* points to the first element */
	struct tx_map *end;	/* points just AFTER the last element */
	struct tx_map *rptr;	/* points to the next element to read */
	struct tx_map *wptr;	/* points to the next element to write */
	int size;		/* number of elements in the db */
};

/*Internal stats structure*/
struct bdx_stats {
	u64 InUCast;			/* 0x7200 */
	u64 InMCast;			/* 0x7210 */
	u64 InBCast;			/* 0x7220 */
	u64 InPkts;			/* 0x7230 */
	u64 InErrors;			/* 0x7240 */
	u64 InDropped;			/* 0x7250 */
	u64 FrameTooLong;		/* 0x7260 */
	u64 FrameSequenceErrors;	/* 0x7270 */
	u64 InVLAN;			/* 0x7280 */
	u64 InDroppedDFE;		/* 0x7290 */
	u64 InDroppedIntFull;		/* 0x72A0 */
	u64 InFrameAlignErrors;		/* 0x72B0 */

	/* 0x72C0-0x72E0 RSRV */

	u64 OutUCast;			/* 0x72F0 */
	u64 OutMCast;			/* 0x7300 */
	u64 OutBCast;			/* 0x7310 */
	u64 OutPkts;			/* 0x7320 */

	/* 0x7330-0x7360 RSRV */

	u64 OutVLAN;			/* 0x7370 */
	u64 InUCastOctects;		/* 0x7380 */
	u64 OutUCastOctects;		/* 0x7390 */

	/* 0x73A0-0x73B0 RSRV */

	u64 InBCastOctects;		/* 0x73C0 */
	u64 OutBCastOctects;		/* 0x73D0 */
	u64 InOctects;			/* 0x73E0 */
	u64 OutOctects;			/* 0x73F0 */
};

struct bdx_priv {
	void __iomem *pBdxRegs;
	struct net_device *ndev;

	struct napi_struct napi;

	/* RX FIFOs: 1 for data (full) descs, and 2 for free descs */
	struct rxd_fifo rxd_fifo0;
	struct rxf_fifo rxf_fifo0;
	struct rxdb *rxdb;	/* rx dbs to store skb pointers */
	int napi_stop;
	struct vlan_group *vlgrp;

	/* Tx FIFOs: 1 for data desc, 1 for empty (acks) desc */
	struct txd_fifo txd_fifo0;
	struct txf_fifo txf_fifo0;

	struct txdb txdb;
	int tx_level;
#ifdef BDX_DELAY_WPTR
	int tx_update_mark;
	int tx_noupd;
#endif
	spinlock_t tx_lock;	/* NETIF_F_LLTX mode */

	/* rarely used */
	u8 port;
	u32 msg_enable;
	int stats_flag;
	struct bdx_stats hw_stats;
	struct net_device_stats net_stats;
	struct pci_dev *pdev;

	struct pci_nic *nic;

	u8 txd_size;
	u8 txf_size;
	u8 rxd_size;
	u8 rxf_size;
	u32 rdintcm;
	u32 tdintcm;
};

/* RX FREE descriptor - 64bit*/
struct rxf_desc {
	u32 info;		/* Buffer Count + Info - described below */
	u32 va_lo;		/* VAdr[31:0] */
	u32 va_hi;		/* VAdr[63:32] */
	u32 pa_lo;		/* PAdr[31:0] */
	u32 pa_hi;		/* PAdr[63:32] */
	u32 len;		/* Buffer Length */
};

#define GET_RXD_BC(x)			GET_BITS_SHIFT((x), 5, 0)
#define GET_RXD_RXFQ(x)			GET_BITS_SHIFT((x), 2, 8)
#define GET_RXD_TO(x)			GET_BITS_SHIFT((x), 1, 15)
#define GET_RXD_TYPE(x)			GET_BITS_SHIFT((x), 4, 16)
#define GET_RXD_ERR(x)			GET_BITS_SHIFT((x), 6, 21)
#define GET_RXD_RXP(x)			GET_BITS_SHIFT((x), 1, 27)
#define GET_RXD_PKT_ID(x)		GET_BITS_SHIFT((x), 3, 28)
#define GET_RXD_VTAG(x)			GET_BITS_SHIFT((x), 1, 31)
#define GET_RXD_VLAN_ID(x)		GET_BITS_SHIFT((x), 12, 0)
#define GET_RXD_VLAN_TCI(x)		GET_BITS_SHIFT((x), 16, 0)
#define GET_RXD_CFI(x)			GET_BITS_SHIFT((x), 1, 12)
#define GET_RXD_PRIO(x)			GET_BITS_SHIFT((x), 3, 13)

struct rxd_desc {
	u32 rxd_val1;
	u16 len;
	u16 rxd_vlan;
	u32 va_lo;
	u32 va_hi;
};

/* PBL describes each virtual buffer to be */
/* transmitted from the host.*/
struct pbl {
	u32 pa_lo;
	u32 pa_hi;
	u32 len;
};

/* First word for TXD descriptor. It means: type = 3 for regular Tx packet,
 * hw_csum = 7 for ip+udp+tcp hw checksums */
#define TXD_W1_VAL(bc, checksum, vtag, lgsnd, vlan_id)	\
	((bc) | ((checksum)<<5) | ((vtag)<<8) | \
	((lgsnd)<<9) | (0x30000) | ((vlan_id)<<20))

struct txd_desc {
	u32 txd_val1;
	u16 mss;
	u16 length;
	u32 va_lo;
	u32 va_hi;
	struct pbl pbl[0];	/* Fragments */
} __attribute__ ((packed));

/* Register region size */
#define BDX_REGS_SIZE	  0x1000

/* Registers from 0x0000-0x00fc were remapped to 0x4000-0x40fc */
#define regTXD_CFG1_0   0x4000
#define regRXF_CFG1_0   0x4010
#define regRXD_CFG1_0   0x4020
#define regTXF_CFG1_0   0x4030
#define regTXD_CFG0_0   0x4040
#define regRXF_CFG0_0   0x4050
#define regRXD_CFG0_0   0x4060
#define regTXF_CFG0_0   0x4070
#define regTXD_WPTR_0   0x4080
#define regRXF_WPTR_0   0x4090
#define regRXD_WPTR_0   0x40A0
#define regTXF_WPTR_0   0x40B0
#define regTXD_RPTR_0   0x40C0
#define regRXF_RPTR_0   0x40D0
#define regRXD_RPTR_0   0x40E0
#define regTXF_RPTR_0   0x40F0
#define regTXF_RPTR_3   0x40FC

/* hardware versioning */
#define  FW_VER         0x5010
#define  SROM_VER       0x5020
#define  FPGA_VER       0x5030
#define  FPGA_SEED      0x5040

/* Registers from 0x0100-0x0150 were remapped to 0x5100-0x5150 */
#define regISR regISR0
#define regISR0          0x5100

#define regIMR regIMR0
#define regIMR0          0x5110

#define regRDINTCM0      0x5120
#define regRDINTCM2      0x5128

#define regTDINTCM0      0x5130

#define regISR_MSK0      0x5140

#define regINIT_SEMAPHORE 0x5170
#define regINIT_STATUS    0x5180

#define regMAC_LNK_STAT  0x0200
#define MAC_LINK_STAT    0x4	/* Link state */

#define regGMAC_RXF_A   0x1240

#define regUNC_MAC0_A   0x1250
#define regUNC_MAC1_A   0x1260
#define regUNC_MAC2_A   0x1270

#define regVLAN_0       0x1800

#define regMAX_FRAME_A  0x12C0

#define regRX_MAC_MCST0    0x1A80
#define regRX_MAC_MCST1    0x1A84
#define MAC_MCST_NUM       15
#define regRX_MCST_HASH0   0x1A00
#define MAC_MCST_HASH_NUM  8

#define regVPC                  0x2300
#define regVIC                  0x2320
#define regVGLB                 0x2340

#define regCLKPLL               0x5000

/*for 10G only*/
#define regREVISION        0x6000
#define regSCRATCH         0x6004
#define regCTRLST          0x6008
#define regMAC_ADDR_0      0x600C
#define regMAC_ADDR_1      0x6010
#define regFRM_LENGTH      0x6014
#define regPAUSE_QUANT     0x6018
#define regRX_FIFO_SECTION 0x601C
#define regTX_FIFO_SECTION 0x6020
#define regRX_FULLNESS     0x6024
#define regTX_FULLNESS     0x6028
#define regHASHTABLE       0x602C
#define regMDIO_ST         0x6030
#define regMDIO_CTL        0x6034
#define regMDIO_DATA       0x6038
#define regMDIO_ADDR       0x603C

#define regRST_PORT        0x7000
#define regDIS_PORT        0x7010
#define regRST_QU          0x7020
#define regDIS_QU          0x7030

#define regCTRLST_TX_ENA   0x0001
#define regCTRLST_RX_ENA   0x0002
#define regCTRLST_PRM_ENA  0x0010
#define regCTRLST_PAD_ENA  0x0020

#define regCTRLST_BASE     (regCTRLST_PAD_ENA|regCTRLST_PRM_ENA)

#define regRX_FLT   0x1400

/* TXD TXF RXF RXD  CONFIG 0x0000 --- 0x007c*/
#define  TX_RX_CFG1_BASE          0xffffffff	/*0-31 */
#define  TX_RX_CFG0_BASE          0xfffff000	/*31:12 */
#define  TX_RX_CFG0_RSVD          0x0ffc	/*11:2 */
#define  TX_RX_CFG0_SIZE          0x0003	/*1:0 */

/*  TXD TXF RXF RXD  WRITE 0x0080 --- 0x00BC */
#define  TXF_WPTR_WR_PTR        0x7ff8	/*14:3 */

/*  TXD TXF RXF RXD  READ  0x00CO --- 0x00FC */
#define  TXF_RPTR_RD_PTR        0x7ff8	/*14:3 */

#define TXF_WPTR_MASK 0x7ff0	/* last 4 bits are dropped
				 * size is rounded to 16 */

/*  regISR 0x0100 */
/*  regIMR 0x0110 */
#define  IMR_INPROG   0x80000000	/*31 */
#define  IR_LNKCHG1   0x10000000	/*28 */
#define  IR_LNKCHG0   0x08000000	/*27 */
#define  IR_GPIO      0x04000000	/*26 */
#define  IR_RFRSH     0x02000000	/*25 */
#define  IR_RSVD      0x01000000	/*24 */
#define  IR_SWI       0x00800000	/*23 */
#define  IR_RX_FREE_3 0x00400000	/*22 */
#define  IR_RX_FREE_2 0x00200000	/*21 */
#define  IR_RX_FREE_1 0x00100000	/*20 */
#define  IR_RX_FREE_0 0x00080000	/*19 */
#define  IR_TX_FREE_3 0x00040000	/*18 */
#define  IR_TX_FREE_2 0x00020000	/*17 */
#define  IR_TX_FREE_1 0x00010000	/*16 */
#define  IR_TX_FREE_0 0x00008000	/*15 */
#define  IR_RX_DESC_3 0x00004000	/*14 */
#define  IR_RX_DESC_2 0x00002000	/*13 */
#define  IR_RX_DESC_1 0x00001000	/*12 */
#define  IR_RX_DESC_0 0x00000800	/*11 */
#define  IR_PSE       0x00000400	/*10 */
#define  IR_TMR3      0x00000200	/*9 */
#define  IR_TMR2      0x00000100	/*8 */
#define  IR_TMR1      0x00000080	/*7 */
#define  IR_TMR0      0x00000040	/*6 */
#define  IR_VNT       0x00000020	/*5 */
#define  IR_RxFL      0x00000010	/*4 */
#define  IR_SDPERR    0x00000008	/*3 */
#define  IR_TR        0x00000004	/*2 */
#define  IR_PCIE_LINK 0x00000002	/*1 */
#define  IR_PCIE_TOUT 0x00000001	/*0 */

#define  IR_EXTRA (IR_RX_FREE_0 | IR_LNKCHG0 | IR_PSE | \
    IR_TMR0 | IR_PCIE_LINK | IR_PCIE_TOUT)
#define  IR_RUN (IR_EXTRA | IR_RX_DESC_0 | IR_TX_FREE_0)
#define  IR_ALL 0xfdfffff7

#define  IR_LNKCHG0_ofst        27

#define  GMAC_RX_FILTER_OSEN  0x1000	/* shared OS enable */
#define  GMAC_RX_FILTER_TXFC  0x0400	/* Tx flow control */
#define  GMAC_RX_FILTER_RSV0  0x0200	/* reserved */
#define  GMAC_RX_FILTER_FDA   0x0100	/* filter out direct address */
#define  GMAC_RX_FILTER_AOF   0x0080	/* accept over run */
#define  GMAC_RX_FILTER_ACF   0x0040	/* accept control frames */
#define  GMAC_RX_FILTER_ARUNT 0x0020	/* accept under run */
#define  GMAC_RX_FILTER_ACRC  0x0010	/* accept crc error */
#define  GMAC_RX_FILTER_AM    0x0008	/* accept multicast */
#define  GMAC_RX_FILTER_AB    0x0004	/* accept broadcast */
#define  GMAC_RX_FILTER_PRM   0x0001	/* [0:1] promiscous mode */

#define  MAX_FRAME_AB_VAL       0x3fff	/* 13:0 */

#define  CLKPLL_PLLLKD          0x0200	/*9 */
#define  CLKPLL_RSTEND          0x0100	/*8 */
#define  CLKPLL_SFTRST          0x0001	/*0 */

#define  CLKPLL_LKD             (CLKPLL_PLLLKD|CLKPLL_RSTEND)

/*
 * PCI-E Device Control Register (Offset 0x88)
 * Source: Luxor Data Sheet, 7.1.3.3.3
 */
#define PCI_DEV_CTRL_REG 0x88
#define GET_DEV_CTRL_MAXPL(x)           GET_BITS_SHIFT(x, 3, 5)
#define GET_DEV_CTRL_MRRS(x)            GET_BITS_SHIFT(x, 3, 12)

/*
 * PCI-E Link Status Register (Offset 0x92)
 * Source: Luxor Data Sheet, 7.1.3.3.7
 */
#define PCI_LINK_STATUS_REG 0x92
#define GET_LINK_STATUS_LANES(x)		GET_BITS_SHIFT(x, 6, 4)

/* Debugging Macros */

#define ERR(fmt, args...) printk(KERN_ERR fmt, ## args)
#define DBG2(fmt, args...)	\
	printk(KERN_ERR  "%s:%-5d: " fmt, __func__, __LINE__, ## args)

#define BDX_ASSERT(x) BUG_ON(x)

#ifdef DEBUG

#define ENTER          do { \
	printk(KERN_ERR  "%s:%-5d: ENTER\n", __func__, __LINE__); \
} while (0)

#define RET(args...)   do { \
	printk(KERN_ERR  "%s:%-5d: RETURN\n", __func__, __LINE__); \
return args; } while (0)

#define DBG(fmt, args...)	\
	printk(KERN_ERR  "%s:%-5d: " fmt, __func__, __LINE__, ## args)
#else
#define ENTER         do {  } while (0)
#define RET(args...)   return args
#define DBG(fmt, args...)   do {  } while (0)
#endif

#endif /* _BDX__H */
Commit	Line	Data
1a348ccc AG	1	/*
	2	* Tehuti Networks(R) Network Driver
	3	* Copyright (C) 2007 Tehuti Networks Ltd. All rights reserved
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; either version 2 of the License, or
	8	* (at your option) any later version.
	9	*/
	10
	11	#ifndef _TEHUTI_H
	12	#define _TEHUTI_H
	13
	14	#include <linux/module.h>
	15	#include <linux/kernel.h>
	16	#include <linux/netdevice.h>
	17	#include <linux/etherdevice.h>
	18	#include <linux/pci.h>
	19	#include <linux/delay.h>
	20	#include <linux/ethtool.h>
	21	#include <linux/mii.h>
	22	#include <linux/crc32.h>
	23	#include <linux/uaccess.h>
	24	#include <linux/in.h>
	25	#include <linux/ip.h>
	26	#include <linux/tcp.h>
	27	#include <linux/sched.h>
	28	#include <linux/tty.h>
	29	#include <linux/if_vlan.h>
1a348ccc AG	30	#include <linux/interrupt.h>
1a348ccc AG	31	#include <linux/vmalloc.h>
06e1f9ff	32	#include <linux/firmware.h>
1a348ccc	33	#include <asm/byteorder.h>
6a35528a	34	#include <linux/dma-mapping.h>
1a348ccc AG	35
	36	/* Compile Time Switches */
	37	/* start */
	38	#define BDX_TSO
	39	#define BDX_LLTX
	40	#define BDX_DELAY_WPTR
	41	/* #define BDX_MSI */
	42	/* end */
	43
	44	#if !defined CONFIG_PCI_MSI
	45	# undef BDX_MSI
	46	#endif
	47
	48	#define BDX_DEF_MSG_ENABLE (NETIF_MSG_DRV \| \
	49	NETIF_MSG_PROBE \| \
	50	NETIF_MSG_LINK)
	51
	52	/* ioctl ops */
	53	#define BDX_OP_READ 1
	54	#define BDX_OP_WRITE 2
	55
	56	/* RX copy break size */
	57	#define BDX_COPYBREAK 257
	58
	59	#define DRIVER_AUTHOR "Tehuti Networks(R)"
	60	#define BDX_DRV_DESC "Tehuti Networks(R) Network Driver"
	61	#define BDX_DRV_NAME "tehuti"
	62	#define BDX_NIC_NAME "Tehuti 10 Giga TOE SmartNIC"
	63	#define BDX_NIC2PORT_NAME "Tehuti 2-Port 10 Giga TOE SmartNIC"
	64	#define BDX_DRV_VERSION "7.29.3"
	65
	66	#ifdef BDX_MSI
	67	# define BDX_MSI_STRING "msi "
	68	#else
	69	# define BDX_MSI_STRING ""
	70	#endif
	71
	72	/* netdev tx queue len for Luxor. default value is, btw, 1000
	73	* ifcontig eth1 txqueuelen 3000 - to change it at runtime */
	74	#define BDX_NDEV_TXQ_LEN 3000
	75
	76	#define FIFO_SIZE 4096
	77	#define FIFO_EXTRA_SPACE 1024
	78
	79	#define MIN(x, y) ((x) < (y) ? (x) : (y))
	80
	81	#if BITS_PER_LONG == 64
	82	# define H32_64(x) (u32) ((u64)(x) >> 32)
	83	# define L32_64(x) (u32) ((u64)(x) & 0xffffffff)
	84	#elif BITS_PER_LONG == 32
	85	# define H32_64(x) 0
	86	# define L32_64(x) ((u32) (x))
	87	#else /* BITS_PER_LONG == ?? */
	88	# error BITS_PER_LONG is undefined. Must be 64 or 32
	89	#endif /* BITS_PER_LONG */
	90
	91	#ifdef __BIG_ENDIAN
	92	# define CPU_CHIP_SWAP32(x) swab32(x)
	93	# define CPU_CHIP_SWAP16(x) swab16(x)
	94	#else
	95	# define CPU_CHIP_SWAP32(x) (x)
	96	# define CPU_CHIP_SWAP16(x) (x)
	97	#endif
	98
99	#define READ_REG(pp, reg) readl(pp->pBdxRegs + reg)
100	#define WRITE_REG(pp, reg, val) writel(val, pp->pBdxRegs + reg)
101
1a348ccc AG	102	#ifndef NET_IP_ALIGN
	103	# define NET_IP_ALIGN 2
	104	#endif
	105
	106	#ifndef NETDEV_TX_OK
	107	# define NETDEV_TX_OK 0
	108	#endif
	109
	110	#define LUXOR_MAX_PORT 2
	111	#define BDX_MAX_RX_DONE 150
	112	#define BDX_TXF_DESC_SZ 16
	113	#define BDX_MAX_TX_LEVEL (priv->txd_fifo0.m.memsz - 16)
	114	#define BDX_MIN_TX_LEVEL 256
	115	#define BDX_NO_UPD_PACKETS 40
	116
	117	struct pci_nic {
	118	int port_num;
	119	void __iomem *regs;
	120	int irq_type;
	121	struct bdx_priv *priv[LUXOR_MAX_PORT];
	122	};
	123
	124	enum { IRQ_INTX, IRQ_MSI, IRQ_MSIX };
	125
	126	#define PCK_TH_MULT 128
	127	#define INT_COAL_MULT 2
	128
	129	#define BITS_MASK(nbits) ((1<<nbits)-1)
	130	#define GET_BITS_SHIFT(x, nbits, nshift) (((x)>>nshift)&BITS_MASK(nbits))
	131	#define BITS_SHIFT_MASK(nbits, nshift) (BITS_MASK(nbits)<<nshift)
	132	#define BITS_SHIFT_VAL(x, nbits, nshift) (((x)&BITS_MASK(nbits))<<nshift)
	133	#define BITS_SHIFT_CLEAR(x, nbits, nshift) \
	134	((x)&(~BITS_SHIFT_MASK(nbits, nshift)))
	135
	136	#define GET_INT_COAL(x) GET_BITS_SHIFT(x, 15, 0)
	137	#define GET_INT_COAL_RC(x) GET_BITS_SHIFT(x, 1, 15)
	138	#define GET_RXF_TH(x) GET_BITS_SHIFT(x, 4, 16)
	139	#define GET_PCK_TH(x) GET_BITS_SHIFT(x, 4, 20)
	140
	141	#define INT_REG_VAL(coal, coal_rc, rxf_th, pck_th) \
	142	((coal)\|((coal_rc)<<15)\|((rxf_th)<<16)\|((pck_th)<<20))
	143
	144	struct fifo {
	145	dma_addr_t da; /* physical address of fifo (used by HW) */
	146	char va; / virtual address of fifo (used by SW) */
	147	u32 rptr, wptr; /* cached values of RPTR and WPTR registers,
	148	they're 32 bits on both 32 and 64 archs */
	149	u16 reg_CFG0, reg_CFG1;
	150	u16 reg_RPTR, reg_WPTR;
	151	u16 memsz; /* memory size allocated for fifo */
	152	u16 size_mask;
	153	u16 pktsz; /* skb packet size to allocate */
	154	u16 rcvno; /* number of buffers that come from this RXF */
	155	};
	156
	157	struct txf_fifo {
	158	struct fifo m; /* minimal set of variables used by all fifos */
	159	};
	160
	161	struct txd_fifo {
	162	struct fifo m; /* minimal set of variables used by all fifos */
	163	};
	164
	165	struct rxf_fifo {
166	struct fifo m; /* minimal set of variables used by all fifos */
167	};
168
169	struct rxd_fifo {
170	struct fifo m; /* minimal set of variables used by all fifos */
171	};
172
173	struct rx_map {
174	u64 dma;
175	struct sk_buff *skb;
176	};
177
178	struct rxdb {
179	int *stack;
180	struct rx_map *elems;
181	int nelem;
182	int top;
183	};
184
185	union bdx_dma_addr {
186	dma_addr_t dma;
187	struct sk_buff *skb;
188	};
189
190	/* Entry in the db.
191	* if len == 0 addr is dma
192	* if len != 0 addr is skb */
193	struct tx_map {
194	union bdx_dma_addr addr;
195	int len;
196	};
197
198	/* tx database - implemented as circular fifo buffer*/
199	struct txdb {
200	struct tx_map start; / points to the first element */
201	struct tx_map end; / points just AFTER the last element */
202	struct tx_map rptr; / points to the next element to read */
203	struct tx_map wptr; / points to the next element to write */
204	int size; /* number of elements in the db */
205	};
206
207	/Internal stats structure/
208	struct bdx_stats {
209	u64 InUCast; /* 0x7200 */
210	u64 InMCast; /* 0x7210 */
211	u64 InBCast; /* 0x7220 */
212	u64 InPkts; /* 0x7230 */
213	u64 InErrors; /* 0x7240 */
214	u64 InDropped; /* 0x7250 */
215	u64 FrameTooLong; /* 0x7260 */
216	u64 FrameSequenceErrors; /* 0x7270 */
217	u64 InVLAN; /* 0x7280 */
218	u64 InDroppedDFE; /* 0x7290 */
219	u64 InDroppedIntFull; /* 0x72A0 */
220	u64 InFrameAlignErrors; /* 0x72B0 */
221
222	/* 0x72C0-0x72E0 RSRV */
223
224	u64 OutUCast; /* 0x72F0 */
225	u64 OutMCast; /* 0x7300 */
226	u64 OutBCast; /* 0x7310 */
227	u64 OutPkts; /* 0x7320 */
228
229	/* 0x7330-0x7360 RSRV */
230
231	u64 OutVLAN; /* 0x7370 */
232	u64 InUCastOctects; /* 0x7380 */
233	u64 OutUCastOctects; /* 0x7390 */
234
235	/* 0x73A0-0x73B0 RSRV */
236
237	u64 InBCastOctects; /* 0x73C0 */
238	u64 OutBCastOctects; /* 0x73D0 */
239	u64 InOctects; /* 0x73E0 */
240	u64 OutOctects; /* 0x73F0 */
241	};
242
243	struct bdx_priv {
244	void __iomem *pBdxRegs;
245	struct net_device *ndev;
246
247	struct napi_struct napi;
248
249	/* RX FIFOs: 1 for data (full) descs, and 2 for free descs */
250	struct rxd_fifo rxd_fifo0;
251	struct rxf_fifo rxf_fifo0;
252	struct rxdb rxdb; / rx dbs to store skb pointers */
253	int napi_stop;
254	struct vlan_group *vlgrp;
255
256	/* Tx FIFOs: 1 for data desc, 1 for empty (acks) desc */
257	struct txd_fifo txd_fifo0;
258	struct txf_fifo txf_fifo0;
259
260	struct txdb txdb;
261	int tx_level;
262	#ifdef BDX_DELAY_WPTR
263	int tx_update_mark;
264	int tx_noupd;
265	#endif
266	spinlock_t tx_lock; /* NETIF_F_LLTX mode */
267
268	/* rarely used */
269	u8 port;
270	u32 msg_enable;
271	int stats_flag;
272	struct bdx_stats hw_stats;
273	struct net_device_stats net_stats;
274	struct pci_dev *pdev;
275
276	struct pci_nic *nic;
277
278	u8 txd_size;
279	u8 txf_size;
280	u8 rxd_size;
281	u8 rxf_size;
282	u32 rdintcm;
283	u32 tdintcm;
284	};
285
286	/* RX FREE descriptor - 64bit*/
287	struct rxf_desc {
288	u32 info; /* Buffer Count + Info - described below */
289	u32 va_lo; /* VAdr[31:0] */
290	u32 va_hi; /* VAdr[63:32] */
291	u32 pa_lo; /* PAdr[31:0] */
292	u32 pa_hi; /* PAdr[63:32] */
293	u32 len; /* Buffer Length */
294	};
295
296	#define GET_RXD_BC(x) GET_BITS_SHIFT((x), 5, 0)
297	#define GET_RXD_RXFQ(x) GET_BITS_SHIFT((x), 2, 8)
298	#define GET_RXD_TO(x) GET_BITS_SHIFT((x), 1, 15)
299	#define GET_RXD_TYPE(x) GET_BITS_SHIFT((x), 4, 16)
300	#define GET_RXD_ERR(x) GET_BITS_SHIFT((x), 6, 21)
301	#define GET_RXD_RXP(x) GET_BITS_SHIFT((x), 1, 27)
302	#define GET_RXD_PKT_ID(x) GET_BITS_SHIFT((x), 3, 28)
303	#define GET_RXD_VTAG(x) GET_BITS_SHIFT((x), 1, 31)
304	#define GET_RXD_VLAN_ID(x) GET_BITS_SHIFT((x), 12, 0)
38b22195	305	#define GET_RXD_VLAN_TCI(x) GET_BITS_SHIFT((x), 16, 0)
1a348ccc AG	306	#define GET_RXD_CFI(x) GET_BITS_SHIFT((x), 1, 12)
	307	#define GET_RXD_PRIO(x) GET_BITS_SHIFT((x), 3, 13)
	308
	309	struct rxd_desc {
	310	u32 rxd_val1;
	311	u16 len;
	312	u16 rxd_vlan;
	313	u32 va_lo;
	314	u32 va_hi;
	315	};
	316
	317	/* PBL describes each virtual buffer to be */
	318	/* transmitted from the host.*/
	319	struct pbl {
	320	u32 pa_lo;
	321	u32 pa_hi;
	322	u32 len;
	323	};
	324
	325	/* First word for TXD descriptor. It means: type = 3 for regular Tx packet,
	326	* hw_csum = 7 for ip+udp+tcp hw checksums */
	327	#define TXD_W1_VAL(bc, checksum, vtag, lgsnd, vlan_id) \
	328	((bc) \| ((checksum)<<5) \| ((vtag)<<8) \| \
	329	((lgsnd)<<9) \| (0x30000) \| ((vlan_id)<<20))
	330
	331	struct txd_desc {
	332	u32 txd_val1;
	333	u16 mss;
	334	u16 length;
	335	u32 va_lo;
	336	u32 va_hi;
	337	struct pbl pbl[0]; /* Fragments */
	338	} __attribute__ ((packed));
	339
	340	/* Register region size */
	341	#define BDX_REGS_SIZE 0x1000
	342
	343	/* Registers from 0x0000-0x00fc were remapped to 0x4000-0x40fc */
	344	#define regTXD_CFG1_0 0x4000
	345	#define regRXF_CFG1_0 0x4010
	346	#define regRXD_CFG1_0 0x4020
	347	#define regTXF_CFG1_0 0x4030
	348	#define regTXD_CFG0_0 0x4040
	349	#define regRXF_CFG0_0 0x4050
	350	#define regRXD_CFG0_0 0x4060
	351	#define regTXF_CFG0_0 0x4070
	352	#define regTXD_WPTR_0 0x4080
	353	#define regRXF_WPTR_0 0x4090
	354	#define regRXD_WPTR_0 0x40A0
	355	#define regTXF_WPTR_0 0x40B0
	356	#define regTXD_RPTR_0 0x40C0
	357	#define regRXF_RPTR_0 0x40D0
	358	#define regRXD_RPTR_0 0x40E0
	359	#define regTXF_RPTR_0 0x40F0
	360	#define regTXF_RPTR_3 0x40FC
	361
	362	/* hardware versioning */
	363	#define FW_VER 0x5010
	364	#define SROM_VER 0x5020
	365	#define FPGA_VER 0x5030
	366	#define FPGA_SEED 0x5040
	367
	368	/* Registers from 0x0100-0x0150 were remapped to 0x5100-0x5150 */
	369	#define regISR regISR0
370	#define regISR0 0x5100
371
372	#define regIMR regIMR0
373	#define regIMR0 0x5110
374
375	#define regRDINTCM0 0x5120
376	#define regRDINTCM2 0x5128
377
378	#define regTDINTCM0 0x5130
379
380	#define regISR_MSK0 0x5140
381
382	#define regINIT_SEMAPHORE 0x5170
383	#define regINIT_STATUS 0x5180
384
385	#define regMAC_LNK_STAT 0x0200
386	#define MAC_LINK_STAT 0x4 /* Link state */
387
388	#define regGMAC_RXF_A 0x1240
389
390	#define regUNC_MAC0_A 0x1250
391	#define regUNC_MAC1_A 0x1260
392	#define regUNC_MAC2_A 0x1270
393
394	#define regVLAN_0 0x1800
395
396	#define regMAX_FRAME_A 0x12C0
397
398	#define regRX_MAC_MCST0 0x1A80
399	#define regRX_MAC_MCST1 0x1A84
400	#define MAC_MCST_NUM 15
401	#define regRX_MCST_HASH0 0x1A00
402	#define MAC_MCST_HASH_NUM 8
403
404	#define regVPC 0x2300
405	#define regVIC 0x2320
406	#define regVGLB 0x2340
407
408	#define regCLKPLL 0x5000
409
410	/for 10G only/
411	#define regREVISION 0x6000
412	#define regSCRATCH 0x6004
413	#define regCTRLST 0x6008
414	#define regMAC_ADDR_0 0x600C
415	#define regMAC_ADDR_1 0x6010
416	#define regFRM_LENGTH 0x6014
417	#define regPAUSE_QUANT 0x6018
418	#define regRX_FIFO_SECTION 0x601C
419	#define regTX_FIFO_SECTION 0x6020
420	#define regRX_FULLNESS 0x6024
421	#define regTX_FULLNESS 0x6028
422	#define regHASHTABLE 0x602C
423	#define regMDIO_ST 0x6030
424	#define regMDIO_CTL 0x6034
425	#define regMDIO_DATA 0x6038
426	#define regMDIO_ADDR 0x603C
427
428	#define regRST_PORT 0x7000
429	#define regDIS_PORT 0x7010
430	#define regRST_QU 0x7020
431	#define regDIS_QU 0x7030
432
433	#define regCTRLST_TX_ENA 0x0001
434	#define regCTRLST_RX_ENA 0x0002
435	#define regCTRLST_PRM_ENA 0x0010
436	#define regCTRLST_PAD_ENA 0x0020
437
438	#define regCTRLST_BASE (regCTRLST_PAD_ENA\|regCTRLST_PRM_ENA)
439
440	#define regRX_FLT 0x1400
441
442	/* TXD TXF RXF RXD CONFIG 0x0000 --- 0x007c*/
443	#define TX_RX_CFG1_BASE 0xffffffff /0-31 /
444	#define TX_RX_CFG0_BASE 0xfffff000 /31:12 /
445	#define TX_RX_CFG0_RSVD 0x0ffc /11:2 /
446	#define TX_RX_CFG0_SIZE 0x0003 /1:0 /
447
448	/* TXD TXF RXF RXD WRITE 0x0080 --- 0x00BC */
449	#define TXF_WPTR_WR_PTR 0x7ff8 /14:3 /
450
451	/* TXD TXF RXF RXD READ 0x00CO --- 0x00FC */
452	#define TXF_RPTR_RD_PTR 0x7ff8 /14:3 /
453
454	#define TXF_WPTR_MASK 0x7ff0 /* last 4 bits are dropped
455	* size is rounded to 16 */
456
457	/* regISR 0x0100 */
458	/* regIMR 0x0110 */
459	#define IMR_INPROG 0x80000000 /31 /
460	#define IR_LNKCHG1 0x10000000 /28 /
461	#define IR_LNKCHG0 0x08000000 /27 /
462	#define IR_GPIO 0x04000000 /26 /
463	#define IR_RFRSH 0x02000000 /25 /
464	#define IR_RSVD 0x01000000 /24 /
465	#define IR_SWI 0x00800000 /23 /
466	#define IR_RX_FREE_3 0x00400000 /22 /
467	#define IR_RX_FREE_2 0x00200000 /21 /
468	#define IR_RX_FREE_1 0x00100000 /20 /
469	#define IR_RX_FREE_0 0x00080000 /19 /
470	#define IR_TX_FREE_3 0x00040000 /18 /
471	#define IR_TX_FREE_2 0x00020000 /17 /
472	#define IR_TX_FREE_1 0x00010000 /16 /
473	#define IR_TX_FREE_0 0x00008000 /15 /
474	#define IR_RX_DESC_3 0x00004000 /14 /
475	#define IR_RX_DESC_2 0x00002000 /13 /
476	#define IR_RX_DESC_1 0x00001000 /12 /
477	#define IR_RX_DESC_0 0x00000800 /11 /
478	#define IR_PSE 0x00000400 /10 /
479	#define IR_TMR3 0x00000200 /9 /
480	#define IR_TMR2 0x00000100 /8 /
481	#define IR_TMR1 0x00000080 /7 /
482	#define IR_TMR0 0x00000040 /6 /
483	#define IR_VNT 0x00000020 /5 /
484	#define IR_RxFL 0x00000010 /4 /
485	#define IR_SDPERR 0x00000008 /3 /
486	#define IR_TR 0x00000004 /2 /
487	#define IR_PCIE_LINK 0x00000002 /1 /
488	#define IR_PCIE_TOUT 0x00000001 /0 /
489
490	#define IR_EXTRA (IR_RX_FREE_0 \| IR_LNKCHG0 \| IR_PSE \| \
491	IR_TMR0 \| IR_PCIE_LINK \| IR_PCIE_TOUT)
492	#define IR_RUN (IR_EXTRA \| IR_RX_DESC_0 \| IR_TX_FREE_0)
493	#define IR_ALL 0xfdfffff7
494
495	#define IR_LNKCHG0_ofst 27
496
497	#define GMAC_RX_FILTER_OSEN 0x1000 /* shared OS enable */
498	#define GMAC_RX_FILTER_TXFC 0x0400 /* Tx flow control */
499	#define GMAC_RX_FILTER_RSV0 0x0200 /* reserved */
500	#define GMAC_RX_FILTER_FDA 0x0100 /* filter out direct address */
501	#define GMAC_RX_FILTER_AOF 0x0080 /* accept over run */
502	#define GMAC_RX_FILTER_ACF 0x0040 /* accept control frames */
503	#define GMAC_RX_FILTER_ARUNT 0x0020 /* accept under run */
504	#define GMAC_RX_FILTER_ACRC 0x0010 /* accept crc error */
505	#define GMAC_RX_FILTER_AM 0x0008 /* accept multicast */
506	#define GMAC_RX_FILTER_AB 0x0004 /* accept broadcast */
507	#define GMAC_RX_FILTER_PRM 0x0001 /* [0:1] promiscous mode */
508
509	#define MAX_FRAME_AB_VAL 0x3fff /* 13:0 */
510
511	#define CLKPLL_PLLLKD 0x0200 /9 /
512	#define CLKPLL_RSTEND 0x0100 /8 /
513	#define CLKPLL_SFTRST 0x0001 /0 /
514
515	#define CLKPLL_LKD (CLKPLL_PLLLKD\|CLKPLL_RSTEND)
516
517	/*
518	* PCI-E Device Control Register (Offset 0x88)
519	* Source: Luxor Data Sheet, 7.1.3.3.3
520	*/
521	#define PCI_DEV_CTRL_REG 0x88
522	#define GET_DEV_CTRL_MAXPL(x) GET_BITS_SHIFT(x, 3, 5)
523	#define GET_DEV_CTRL_MRRS(x) GET_BITS_SHIFT(x, 3, 12)
524
525	/*
526	* PCI-E Link Status Register (Offset 0x92)
527	* Source: Luxor Data Sheet, 7.1.3.3.7
528	*/
529	#define PCI_LINK_STATUS_REG 0x92
530	#define GET_LINK_STATUS_LANES(x) GET_BITS_SHIFT(x, 6, 4)
531
532	/* Debugging Macros */
533
534	#define ERR(fmt, args...) printk(KERN_ERR fmt, ## args)
535	#define DBG2(fmt, args...) \
b39d66a8	536	printk(KERN_ERR "%s:%-5d: " fmt, __func__, __LINE__, ## args)
1a348ccc AG	537
	538	#define BDX_ASSERT(x) BUG_ON(x)
	539
	540	#ifdef DEBUG
	541
	542	#define ENTER do { \
b39d66a8	543	printk(KERN_ERR "%s:%-5d: ENTER\n", __func__, __LINE__); \
1a348ccc AG	544	} while (0)
	545
	546	#define RET(args...) do { \
b39d66a8	547	printk(KERN_ERR "%s:%-5d: RETURN\n", __func__, __LINE__); \
1a348ccc AG	548	return args; } while (0)
	549
	550	#define DBG(fmt, args...) \
b39d66a8	551	printk(KERN_ERR "%s:%-5d: " fmt, __func__, __LINE__, ## args)
1a348ccc AG	552	#else
	553	#define ENTER do { } while (0)
	554	#define RET(args...) return args
	555	#define DBG(fmt, args...) do { } while (0)
	556	#endif
	557
	558	#endif /* _BDX__H */