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[linux-block.git] / drivers / net / sun3lance.c
CommitLineData
1da177e4
LT		 1/* sun3lance.c: Ethernet driver for SUN3 Lance chip */
2/*
3
6aa20a22 4 Sun3 Lance ethernet driver, by Sam Creasey (sammy@users.qual.net).
1da177e4
LT		 5 This driver is a part of the linux kernel, and is thus distributed
6 under the GNU General Public License.
6aa20a22 7
1da177e4
LT		 8 The values used in LANCE_OBIO and LANCE_IRQ seem to be empirically
9 true for the correct IRQ and address of the lance registers. They
10 have not been widely tested, however. What we probably need is a
11 "proper" way to search for a device in the sun3's prom, but, alas,
6aa20a22 12 linux has no such thing.
1da177e4
LT		 13
14 This driver is largely based on atarilance.c, by Roman Hodek. Other
15 sources of inspiration were the NetBSD sun3 am7990 driver, and the
6aa20a22 16 linux sparc lance driver (sunlance.c).
1da177e4
LT		 17
18 There are more assumptions made throughout this driver, it almost
19 certainly still needs work, but it does work at least for RARP/BOOTP and
20 mounting the root NFS filesystem.
6aa20a22 21
1da177e4
LT		 22*/
23
24static char *version = "sun3lance.c: v1.2 1/12/2001 Sam Creasey (sammy@sammy.net)\n";
25
26#include <linux/module.h>
27#include <linux/stddef.h>
28#include <linux/kernel.h>
29#include <linux/string.h>
30#include <linux/errno.h>
31#include <linux/slab.h>
32#include <linux/interrupt.h>
33#include <linux/init.h>
34#include <linux/ioport.h>
35#include <linux/delay.h>
36#include <linux/netdevice.h>
37#include <linux/etherdevice.h>
38#include <linux/skbuff.h>
39#include <linux/bitops.h>
40
a1f8e7f7 41#include <asm/cacheflush.h>
1da177e4
LT		 42#include <asm/setup.h>
43#include <asm/irq.h>
44#include <asm/io.h>
45#include <asm/pgtable.h>
46#include <asm/dvma.h>
47#include <asm/idprom.h>
48#include <asm/machines.h>
49
50#ifdef CONFIG_SUN3
51#include <asm/sun3mmu.h>
52#else
53#include <asm/sun3xprom.h>
54#endif
55
56/* sun3/60 addr/irq for the lance chip. If your sun is different,
57 change this. */
58#define LANCE_OBIO 0x120000
4facfde9 59#define LANCE_IRQ IRQ_AUTO_3
1da177e4
LT		 60
61/* Debug level:
62 * 0 = silent, print only serious errors
63 * 1 = normal, print error messages
64 * 2 = debug, print debug infos
65 * 3 = debug, print even more debug infos (packet data)
66 */
67
68#define LANCE_DEBUG 0
69
70#ifdef LANCE_DEBUG
71static int lance_debug = LANCE_DEBUG;
72#else
73static int lance_debug = 1;
74#endif
8d3b33f6 75module_param(lance_debug, int, 0);
1da177e4
LT		 76MODULE_PARM_DESC(lance_debug, "SUN3 Lance debug level (0-3)");
77MODULE_LICENSE("GPL");
78
79#define DPRINTK(n,a) \
80 do { \
81 if (lance_debug >= n) \
82 printk a; \
83 } while( 0 )
84
85
86/* we're only using 32k of memory, so we use 4 TX
87 buffers and 16 RX buffers. These values are expressed as log2. */
88
89#define TX_LOG_RING_SIZE 3
90#define RX_LOG_RING_SIZE 5
91
92/* These are the derived values */
93
94#define TX_RING_SIZE (1 << TX_LOG_RING_SIZE)
95#define TX_RING_LEN_BITS (TX_LOG_RING_SIZE << 5)
96#define TX_RING_MOD_MASK (TX_RING_SIZE - 1)
97
98#define RX_RING_SIZE (1 << RX_LOG_RING_SIZE)
99#define RX_RING_LEN_BITS (RX_LOG_RING_SIZE << 5)
100#define RX_RING_MOD_MASK (RX_RING_SIZE - 1)
101
102/* Definitions for packet buffer access: */
103#define PKT_BUF_SZ 1544
104
105/* Get the address of a packet buffer corresponding to a given buffer head */
106#define PKTBUF_ADDR(head) (void *)((unsigned long)(MEM) | (head)->base)
107
108
109/* The LANCE Rx and Tx ring descriptors. */
110struct lance_rx_head {
111 unsigned short base; /* Low word of base addr */
112 volatile unsigned char flag;
113 unsigned char base_hi; /* High word of base addr (unused) */
114 short buf_length; /* This length is 2s complement! */
115 volatile short msg_length; /* This length is "normal". */
116};
117
118struct lance_tx_head {
119 unsigned short base; /* Low word of base addr */
120 volatile unsigned char flag;
121 unsigned char base_hi; /* High word of base addr (unused) */
122 short length; /* Length is 2s complement! */
123 volatile short misc;
124};
125
126/* The LANCE initialization block, described in databook. */
127struct lance_init_block {
128 unsigned short mode; /* Pre-set mode */
129 unsigned char hwaddr[6]; /* Physical ethernet address */
130 unsigned int filter[2]; /* Multicast filter (unused). */
131 /* Receive and transmit ring base, along with length bits. */
132 unsigned short rdra;
133 unsigned short rlen;
134 unsigned short tdra;
135 unsigned short tlen;
136 unsigned short pad[4]; /* is thie needed? */
137};
138
139/* The whole layout of the Lance shared memory */
140struct lance_memory {
141 struct lance_init_block init;
142 struct lance_tx_head tx_head[TX_RING_SIZE];
143 struct lance_rx_head rx_head[RX_RING_SIZE];
144 char rx_data[RX_RING_SIZE][PKT_BUF_SZ];
145 char tx_data[TX_RING_SIZE][PKT_BUF_SZ];
146};
147
148/* The driver's private device structure */
149
150struct lance_private {
151 volatile unsigned short *iobase;
152 struct lance_memory *mem;
153 int new_rx, new_tx; /* The next free ring entry */
154 int old_tx, old_rx; /* ring entry to be processed */
1da177e4
LT		 155/* These two must be longs for set_bit() */
156 long tx_full;
157 long lock;
158};
159
160/* I/O register access macros */
161
162#define MEM lp->mem
163#define DREG lp->iobase[0]
164#define AREG lp->iobase[1]
e345d5ef 165#define REGA(a) (*( AREG = (a), &DREG ))
1da177e4
LT		 166
167/* Definitions for the Lance */
168
169/* tx_head flags */
170#define TMD1_ENP 0x01 /* end of packet */
171#define TMD1_STP 0x02 /* start of packet */
172#define TMD1_DEF 0x04 /* deferred */
173#define TMD1_ONE 0x08 /* one retry needed */
174#define TMD1_MORE 0x10 /* more than one retry needed */
175#define TMD1_ERR 0x40 /* error summary */
176#define TMD1_OWN 0x80 /* ownership (set: chip owns) */
177
178#define TMD1_OWN_CHIP TMD1_OWN
179#define TMD1_OWN_HOST 0
180
181/* tx_head misc field */
182#define TMD3_TDR 0x03FF /* Time Domain Reflectometry counter */
183#define TMD3_RTRY 0x0400 /* failed after 16 retries */
184#define TMD3_LCAR 0x0800 /* carrier lost */
185#define TMD3_LCOL 0x1000 /* late collision */
186#define TMD3_UFLO 0x4000 /* underflow (late memory) */
187#define TMD3_BUFF 0x8000 /* buffering error (no ENP) */
188
189/* rx_head flags */
190#define RMD1_ENP 0x01 /* end of packet */
191#define RMD1_STP 0x02 /* start of packet */
192#define RMD1_BUFF 0x04 /* buffer error */
193#define RMD1_CRC 0x08 /* CRC error */
194#define RMD1_OFLO 0x10 /* overflow */
195#define RMD1_FRAM 0x20 /* framing error */
196#define RMD1_ERR 0x40 /* error summary */
197#define RMD1_OWN 0x80 /* ownership (set: ship owns) */
198
199#define RMD1_OWN_CHIP RMD1_OWN
200#define RMD1_OWN_HOST 0
201
202/* register names */
203#define CSR0 0 /* mode/status */
204#define CSR1 1 /* init block addr (low) */
205#define CSR2 2 /* init block addr (high) */
206#define CSR3 3 /* misc */
207#define CSR8 8 /* address filter */
208#define CSR15 15 /* promiscuous mode */
209
210/* CSR0 */
211/* (R=readable, W=writeable, S=set on write, C=clear on write) */
212#define CSR0_INIT 0x0001 /* initialize (RS) */
213#define CSR0_STRT 0x0002 /* start (RS) */
214#define CSR0_STOP 0x0004 /* stop (RS) */
215#define CSR0_TDMD 0x0008 /* transmit demand (RS) */
216#define CSR0_TXON 0x0010 /* transmitter on (R) */
217#define CSR0_RXON 0x0020 /* receiver on (R) */
218#define CSR0_INEA 0x0040 /* interrupt enable (RW) */
219#define CSR0_INTR 0x0080 /* interrupt active (R) */
220#define CSR0_IDON 0x0100 /* initialization done (RC) */
221#define CSR0_TINT 0x0200 /* transmitter interrupt (RC) */
222#define CSR0_RINT 0x0400 /* receiver interrupt (RC) */
223#define CSR0_MERR 0x0800 /* memory error (RC) */
224#define CSR0_MISS 0x1000 /* missed frame (RC) */
225#define CSR0_CERR 0x2000 /* carrier error (no heartbeat :-) (RC) */
226#define CSR0_BABL 0x4000 /* babble: tx-ed too many bits (RC) */
227#define CSR0_ERR 0x8000 /* error (RC) */
228
229/* CSR3 */
230#define CSR3_BCON 0x0001 /* byte control */
231#define CSR3_ACON 0x0002 /* ALE control */
232#define CSR3_BSWP 0x0004 /* byte swap (1=big endian) */
233
234/***************************** Prototypes *****************************/
235
236static int lance_probe( struct net_device *dev);
237static int lance_open( struct net_device *dev );
238static void lance_init_ring( struct net_device *dev );
239static int lance_start_xmit( struct sk_buff *skb, struct net_device *dev );
7d12e780 240static irqreturn_t lance_interrupt( int irq, void *dev_id);
1da177e4
LT		 241static int lance_rx( struct net_device *dev );
242static int lance_close( struct net_device *dev );
1da177e4
LT		 243static void set_multicast_list( struct net_device *dev );
244
245/************************* End of Prototypes **************************/
246
247struct net_device * __init sun3lance_probe(int unit)
248{
249 struct net_device *dev;
250 static int found;
251 int err = -ENODEV;
252
0f734484
GU		 253 if (!MACH_IS_SUN3 && !MACH_IS_SUN3X)
254 return ERR_PTR(-ENODEV);
255
1da177e4
LT		 256 /* check that this machine has an onboard lance */
257 switch(idprom->id_machtype) {
258 case SM_SUN3|SM_3_50:
259 case SM_SUN3|SM_3_60:
260 case SM_SUN3X|SM_3_80:
261 /* these machines have lance */
262 break;
263
264 default:
265 return ERR_PTR(-ENODEV);
266 }
267
268 if (found)
269 return ERR_PTR(-ENODEV);
270
271 dev = alloc_etherdev(sizeof(struct lance_private));
272 if (!dev)
273 return ERR_PTR(-ENOMEM);
274 if (unit >= 0) {
275 sprintf(dev->name, "eth%d", unit);
276 netdev_boot_setup_check(dev);
277 }
1da177e4
LT		 278
279 if (!lance_probe(dev))
280 goto out;
281
282 err = register_netdev(dev);
283 if (err)
284 goto out1;
285 found = 1;
286 return dev;
287
288out1:
289#ifdef CONFIG_SUN3
437111ca 290 iounmap((void __iomem *)dev->base_addr);
1da177e4
LT		 291#endif
292out:
293 free_netdev(dev);
294 return ERR_PTR(err);
295}
296
297static int __init lance_probe( struct net_device *dev)
6aa20a22 298{
1da177e4 299 unsigned long ioaddr;
6aa20a22 300
1da177e4
LT		 301 struct lance_private *lp;
302 int i;
303 static int did_version;
304 volatile unsigned short *ioaddr_probe;
305 unsigned short tmp1, tmp2;
306
307#ifdef CONFIG_SUN3
308 ioaddr = (unsigned long)ioremap(LANCE_OBIO, PAGE_SIZE);
309 if (!ioaddr)
310 return 0;
311#else
312 ioaddr = SUN3X_LANCE;
313#endif
314
315 /* test to see if there's really a lance here */
316 /* (CSRO_INIT shouldn't be readable) */
6aa20a22 317
1da177e4
LT		 318 ioaddr_probe = (volatile unsigned short *)ioaddr;
319 tmp1 = ioaddr_probe[0];
320 tmp2 = ioaddr_probe[1];
321
322 ioaddr_probe[1] = CSR0;
323 ioaddr_probe[0] = CSR0_INIT | CSR0_STOP;
324
325 if(ioaddr_probe[0] != CSR0_STOP) {
326 ioaddr_probe[0] = tmp1;
327 ioaddr_probe[1] = tmp2;
328
329#ifdef CONFIG_SUN3
437111ca 330 iounmap((void __iomem *)ioaddr);
1da177e4
LT		 331#endif
332 return 0;
333 }
334
335 lp = netdev_priv(dev);
336
337 /* XXX - leak? */
338 MEM = dvma_malloc_align(sizeof(struct lance_memory), 0x10000);
c14bac62
CG		 339 if (MEM == NULL) {
340#ifdef CONFIG_SUN3
341 iounmap((void __iomem *)ioaddr);
342#endif
343 printk(KERN_WARNING "SUN3 Lance couldn't allocate DVMA memory\n");
344 return 0;
345 }
1da177e4
LT		 346
347 lp->iobase = (volatile unsigned short *)ioaddr;
348 dev->base_addr = (unsigned long)ioaddr; /* informational only */
349
6aa20a22 350 REGA(CSR0) = CSR0_STOP;
1da177e4 351
c14bac62
CG		 352 if (request_irq(LANCE_IRQ, lance_interrupt, IRQF_DISABLED, "SUN3 Lance", dev) < 0) {
353#ifdef CONFIG_SUN3
354 iounmap((void __iomem *)ioaddr);
355#endif
356 dvma_free((void *)MEM);
357 printk(KERN_WARNING "SUN3 Lance unable to allocate IRQ\n");
358 return 0;
359 }
1da177e4
LT		 360 dev->irq = (unsigned short)LANCE_IRQ;
361
362
363 printk("%s: SUN3 Lance at io %#lx, mem %#lx, irq %d, hwaddr ",
364 dev->name,
365 (unsigned long)ioaddr,
366 (unsigned long)MEM,
367 dev->irq);
368
369 /* copy in the ethernet address from the prom */
370 for(i = 0; i < 6 ; i++)
371 dev->dev_addr[i] = idprom->id_ethaddr[i];
372
373 /* tell the card it's ether address, bytes swapped */
374 MEM->init.hwaddr[0] = dev->dev_addr[1];
375 MEM->init.hwaddr[1] = dev->dev_addr[0];
376 MEM->init.hwaddr[2] = dev->dev_addr[3];
377 MEM->init.hwaddr[3] = dev->dev_addr[2];
378 MEM->init.hwaddr[4] = dev->dev_addr[5];
379 MEM->init.hwaddr[5] = dev->dev_addr[4];
380
e174961c 381 printk("%pM\n", dev->dev_addr);
1da177e4
LT		 382
383 MEM->init.mode = 0x0000;
384 MEM->init.filter[0] = 0x00000000;
385 MEM->init.filter[1] = 0x00000000;
386 MEM->init.rdra = dvma_vtob(MEM->rx_head);
387 MEM->init.rlen = (RX_LOG_RING_SIZE << 13) |
388 (dvma_vtob(MEM->rx_head) >> 16);
389 MEM->init.tdra = dvma_vtob(MEM->tx_head);
390 MEM->init.tlen = (TX_LOG_RING_SIZE << 13) |
391 (dvma_vtob(MEM->tx_head) >> 16);
392
393 DPRINTK(2, ("initaddr: %08lx rx_ring: %08lx tx_ring: %08lx\n",
394 dvma_vtob(&(MEM->init)), dvma_vtob(MEM->rx_head),
6aa20a22 395 (dvma_vtob(MEM->tx_head))));
1da177e4
LT		 396
397 if (did_version++ == 0)
398 printk( version );
399
400 /* The LANCE-specific entries in the device structure. */
401 dev->open = &lance_open;
402 dev->hard_start_xmit = &lance_start_xmit;
403 dev->stop = &lance_close;
1da177e4 404 dev->set_multicast_list = &set_multicast_list;
a5d361fc 405 dev->set_mac_address = NULL;
1da177e4
LT		 406// KLUDGE -- REMOVE ME
407 set_bit(__LINK_STATE_PRESENT, &dev->state);
408
409
1da177e4
LT		 410 return 1;
411}
412
413static int lance_open( struct net_device *dev )
414{
415 struct lance_private *lp = netdev_priv(dev);
416 int i;
417
418 DPRINTK( 2, ( "%s: lance_open()\n", dev->name ));
419
420 REGA(CSR0) = CSR0_STOP;
421
422 lance_init_ring(dev);
423
424 /* From now on, AREG is kept to point to CSR0 */
425 REGA(CSR0) = CSR0_INIT;
426
427 i = 1000000;
428 while (--i > 0)
429 if (DREG & CSR0_IDON)
430 break;
cff71e89 431 if (i <= 0 || (DREG & CSR0_ERR)) {
1da177e4
LT		 432 DPRINTK( 2, ( "lance_open(): opening %s failed, i=%d, csr0=%04x\n",
433 dev->name, i, DREG ));
434 DREG = CSR0_STOP;
435 return( -EIO );
436 }
437
438 DREG = CSR0_IDON | CSR0_STRT | CSR0_INEA;
439
440 netif_start_queue(dev);
6aa20a22 441
1da177e4
LT		 442 DPRINTK( 2, ( "%s: LANCE is open, csr0 %04x\n", dev->name, DREG ));
443
444 return( 0 );
445}
446
447
448/* Initialize the LANCE Rx and Tx rings. */
449
450static void lance_init_ring( struct net_device *dev )
451{
452 struct lance_private *lp = netdev_priv(dev);
453 int i;
454
455 lp->lock = 0;
456 lp->tx_full = 0;
457 lp->new_rx = lp->new_tx = 0;
458 lp->old_rx = lp->old_tx = 0;
459
460 for( i = 0; i < TX_RING_SIZE; i++ ) {
461 MEM->tx_head[i].base = dvma_vtob(MEM->tx_data[i]);
462 MEM->tx_head[i].flag = 0;
6aa20a22 463 MEM->tx_head[i].base_hi =
1da177e4
LT		 464 (dvma_vtob(MEM->tx_data[i])) >>16;
465 MEM->tx_head[i].length = 0;
466 MEM->tx_head[i].misc = 0;
467 }
468
469 for( i = 0; i < RX_RING_SIZE; i++ ) {
470 MEM->rx_head[i].base = dvma_vtob(MEM->rx_data[i]);
471 MEM->rx_head[i].flag = RMD1_OWN_CHIP;
6aa20a22 472 MEM->rx_head[i].base_hi =
1da177e4
LT		 473 (dvma_vtob(MEM->rx_data[i])) >> 16;
474 MEM->rx_head[i].buf_length = -PKT_BUF_SZ | 0xf000;
475 MEM->rx_head[i].msg_length = 0;
476 }
477
478 /* tell the card it's ether address, bytes swapped */
479 MEM->init.hwaddr[0] = dev->dev_addr[1];
480 MEM->init.hwaddr[1] = dev->dev_addr[0];
481 MEM->init.hwaddr[2] = dev->dev_addr[3];
482 MEM->init.hwaddr[3] = dev->dev_addr[2];
483 MEM->init.hwaddr[4] = dev->dev_addr[5];
484 MEM->init.hwaddr[5] = dev->dev_addr[4];
485
486 MEM->init.mode = 0x0000;
487 MEM->init.filter[0] = 0x00000000;
488 MEM->init.filter[1] = 0x00000000;
489 MEM->init.rdra = dvma_vtob(MEM->rx_head);
490 MEM->init.rlen = (RX_LOG_RING_SIZE << 13) |
491 (dvma_vtob(MEM->rx_head) >> 16);
492 MEM->init.tdra = dvma_vtob(MEM->tx_head);
493 MEM->init.tlen = (TX_LOG_RING_SIZE << 13) |
494 (dvma_vtob(MEM->tx_head) >> 16);
495
496
497 /* tell the lance the address of its init block */
498 REGA(CSR1) = dvma_vtob(&(MEM->init));
499 REGA(CSR2) = dvma_vtob(&(MEM->init)) >> 16;
500
501#ifdef CONFIG_SUN3X
502 REGA(CSR3) = CSR3_BSWP | CSR3_ACON | CSR3_BCON;
503#else
504 REGA(CSR3) = CSR3_BSWP;
505#endif
506
507}
508
509
510static int lance_start_xmit( struct sk_buff *skb, struct net_device *dev )
511{
512 struct lance_private *lp = netdev_priv(dev);
513 int entry, len;
514 struct lance_tx_head *head;
515 unsigned long flags;
516
517 DPRINTK( 1, ( "%s: transmit start.\n",
518 dev->name));
519
520 /* Transmitter timeout, serious problems. */
521 if (netif_queue_stopped(dev)) {
522 int tickssofar = jiffies - dev->trans_start;
523 if (tickssofar < 20)
524 return( 1 );
525
526 DPRINTK( 1, ( "%s: transmit timed out, status %04x, resetting.\n",
527 dev->name, DREG ));
528 DREG = CSR0_STOP;
529 /*
530 * Always set BSWP after a STOP as STOP puts it back into
531 * little endian mode.
532 */
533 REGA(CSR3) = CSR3_BSWP;
09f75cd7 534 dev->stats.tx_errors++;
1da177e4
LT		 535
536 if(lance_debug >= 2) {
537 int i;
538 printk("Ring data: old_tx %d new_tx %d%s new_rx %d\n",
539 lp->old_tx, lp->new_tx,
540 lp->tx_full ? " (full)" : "",
541 lp->new_rx );
542 for( i = 0 ; i < RX_RING_SIZE; i++ )
543 printk( "rx #%d: base=%04x blen=%04x mlen=%04x\n",
544 i, MEM->rx_head[i].base,
545 -MEM->rx_head[i].buf_length,
546 MEM->rx_head[i].msg_length);
547 for( i = 0 ; i < TX_RING_SIZE; i++ )
548 printk("tx #%d: base=%04x len=%04x misc=%04x\n",
549 i, MEM->tx_head[i].base,
550 -MEM->tx_head[i].length,
551 MEM->tx_head[i].misc );
552 }
553
554 lance_init_ring(dev);
555 REGA( CSR0 ) = CSR0_INEA | CSR0_INIT | CSR0_STRT;
6aa20a22 556
1da177e4
LT		 557 netif_start_queue(dev);
558 dev->trans_start = jiffies;
6aa20a22 559
1da177e4
LT		 560 return 0;
561 }
562
6aa20a22 563
1da177e4
LT		 564 /* Block a timer-based transmit from overlapping. This could better be
565 done with atomic_swap(1, dev->tbusy), but set_bit() works as well. */
566
567 /* Block a timer-based transmit from overlapping with us by
568 stopping the queue for a bit... */
6aa20a22 569
1da177e4 570 netif_stop_queue(dev);
6aa20a22 571
1da177e4
LT		 572 if (test_and_set_bit( 0, (void*)&lp->lock ) != 0) {
573 printk( "%s: tx queue lock!.\n", dev->name);
574 /* don't clear dev->tbusy flag. */
575 return 1;
576 }
577
578 AREG = CSR0;
579 DPRINTK( 2, ( "%s: lance_start_xmit() called, csr0 %4.4x.\n",
580 dev->name, DREG ));
581
582#ifdef CONFIG_SUN3X
583 /* this weirdness doesn't appear on sun3... */
584 if(!(DREG & CSR0_INIT)) {
585 DPRINTK( 1, ("INIT not set, reinitializing...\n"));
586 REGA( CSR0 ) = CSR0_STOP;
587 lance_init_ring(dev);
588 REGA( CSR0 ) = CSR0_INIT | CSR0_STRT;
589 }
590#endif
591
592 /* Fill in a Tx ring entry */
593#if 0
594 if (lance_debug >= 2) {
0795af57
JP		 595 printk( "%s: TX pkt %d type 0x%04x"
596 " from %s to %s"
597 " data at 0x%08x len %d\n",
598 dev->name, lp->new_tx, ((u_short *)skb->data)[6],
599 DEV_ADDR(&skb->data[6]), DEV_ADDR(skb->data),
600 (int)skb->data, (int)skb->len );
1da177e4 601 }
6aa20a22 602#endif
1da177e4
LT		 603 /* We're not prepared for the int until the last flags are set/reset.
604 * And the int may happen already after setting the OWN_CHIP... */
605 local_irq_save(flags);
606
607 /* Mask to ring buffer boundary. */
608 entry = lp->new_tx;
609 head = &(MEM->tx_head[entry]);
610
611 /* Caution: the write order is important here, set the "ownership" bits
612 * last.
613 */
614
615 /* the sun3's lance needs it's buffer padded to the minimum
616 size */
617 len = (ETH_ZLEN < skb->len) ? skb->len : ETH_ZLEN;
618
619// head->length = -len;
620 head->length = (-len) | 0xf000;
621 head->misc = 0;
622
d626f62b 623 skb_copy_from_linear_data(skb, PKTBUF_ADDR(head), skb->len);
1da177e4
LT		 624 if (len != skb->len)
625 memset(PKTBUF_ADDR(head) + skb->len, 0, len-skb->len);
626
627 head->flag = TMD1_OWN_CHIP | TMD1_ENP | TMD1_STP;
628 lp->new_tx = (lp->new_tx + 1) & TX_RING_MOD_MASK;
09f75cd7 629 dev->stats.tx_bytes += skb->len;
1da177e4
LT		 630
631 /* Trigger an immediate send poll. */
632 REGA(CSR0) = CSR0_INEA | CSR0_TDMD | CSR0_STRT;
633 AREG = CSR0;
634 DPRINTK( 2, ( "%s: lance_start_xmit() exiting, csr0 %4.4x.\n",
635 dev->name, DREG ));
636 dev->trans_start = jiffies;
637 dev_kfree_skb( skb );
638
639 lp->lock = 0;
640 if ((MEM->tx_head[(entry+1) & TX_RING_MOD_MASK].flag & TMD1_OWN) ==
6aa20a22 641 TMD1_OWN_HOST)
1da177e4
LT		 642 netif_start_queue(dev);
643
644 local_irq_restore(flags);
645
646 return 0;
647}
648
649/* The LANCE interrupt handler. */
650
7d12e780 651static irqreturn_t lance_interrupt( int irq, void *dev_id)
1da177e4
LT		 652{
653 struct net_device *dev = dev_id;
654 struct lance_private *lp = netdev_priv(dev);
655 int csr0;
656 static int in_interrupt;
657
658 if (dev == NULL) {
659 DPRINTK( 1, ( "lance_interrupt(): invalid dev_id\n" ));
660 return IRQ_NONE;
661 }
662
663 if (in_interrupt)
664 DPRINTK( 2, ( "%s: Re-entering the interrupt handler.\n", dev->name ));
665 in_interrupt = 1;
6aa20a22 666
1da177e4
LT		 667 still_more:
668 flush_cache_all();
6aa20a22 669
1da177e4
LT		 670 AREG = CSR0;
671 csr0 = DREG;
672
673 /* ack interrupts */
674 DREG = csr0 & (CSR0_TINT | CSR0_RINT | CSR0_IDON);
675
676 /* clear errors */
677 if(csr0 & CSR0_ERR)
678 DREG = CSR0_BABL | CSR0_MERR | CSR0_CERR | CSR0_MISS;
679
680
681 DPRINTK( 2, ( "%s: interrupt csr0=%04x new csr=%04x.\n",
682 dev->name, csr0, DREG ));
683
684 if (csr0 & CSR0_TINT) { /* Tx-done interrupt */
685 int old_tx = lp->old_tx;
686
687// if(lance_debug >= 3) {
688// int i;
6aa20a22 689//
1da177e4 690// printk("%s: tx int\n", dev->name);
6aa20a22 691//
1da177e4
LT		 692// for(i = 0; i < TX_RING_SIZE; i++)
693// printk("ring %d flag=%04x\n", i,
694// MEM->tx_head[i].flag);
695// }
6aa20a22 696
1da177e4 697 while( old_tx != lp->new_tx) {
6aa20a22
JG		 698 struct lance_tx_head *head = &(MEM->tx_head[old_tx]);
699
1da177e4
LT		 700 DPRINTK(3, ("on tx_ring %d\n", old_tx));
701
702 if (head->flag & TMD1_OWN_CHIP)
703 break; /* It still hasn't been Txed */
6aa20a22 704
1da177e4
LT		 705 if (head->flag & TMD1_ERR) {
706 int status = head->misc;
09f75cd7
JG		 707 dev->stats.tx_errors++;
708 if (status & TMD3_RTRY) dev->stats.tx_aborted_errors++;
709 if (status & TMD3_LCAR) dev->stats.tx_carrier_errors++;
710 if (status & TMD3_LCOL) dev->stats.tx_window_errors++;
1da177e4 711 if (status & (TMD3_UFLO | TMD3_BUFF)) {
09f75cd7 712 dev->stats.tx_fifo_errors++;
1da177e4 713 printk("%s: Tx FIFO error\n",
6aa20a22 714 dev->name);
1da177e4
LT		 715 REGA(CSR0) = CSR0_STOP;
716 REGA(CSR3) = CSR3_BSWP;
717 lance_init_ring(dev);
718 REGA(CSR0) = CSR0_STRT | CSR0_INEA;
719 return IRQ_HANDLED;
720 }
721 } else if(head->flag & (TMD1_ENP | TMD1_STP)) {
6aa20a22 722
1da177e4
LT		 723 head->flag &= ~(TMD1_ENP | TMD1_STP);
724 if(head->flag & (TMD1_ONE | TMD1_MORE))
09f75cd7 725 dev->stats.collisions++;
6aa20a22 726
09f75cd7 727 dev->stats.tx_packets++;
1da177e4
LT		 728 DPRINTK(3, ("cleared tx ring %d\n", old_tx));
729 }
730 old_tx = (old_tx +1) & TX_RING_MOD_MASK;
731 }
732
733 lp->old_tx = old_tx;
734 }
735
736
737 if (netif_queue_stopped(dev)) {
738 /* The ring is no longer full, clear tbusy. */
739 netif_start_queue(dev);
740 netif_wake_queue(dev);
741 }
742
743 if (csr0 & CSR0_RINT) /* Rx interrupt */
744 lance_rx( dev );
6aa20a22 745
1da177e4 746 /* Log misc errors. */
09f75cd7
JG		 747 if (csr0 & CSR0_BABL) dev->stats.tx_errors++; /* Tx babble. */
748 if (csr0 & CSR0_MISS) dev->stats.rx_errors++; /* Missed a Rx frame. */
1da177e4
LT		 749 if (csr0 & CSR0_MERR) {
750 DPRINTK( 1, ( "%s: Bus master arbitration failure (?!?), "
751 "status %04x.\n", dev->name, csr0 ));
752 /* Restart the chip. */
753 REGA(CSR0) = CSR0_STOP;
754 REGA(CSR3) = CSR3_BSWP;
755 lance_init_ring(dev);
756 REGA(CSR0) = CSR0_STRT | CSR0_INEA;
757 }
758
759
760 /* Clear any other interrupt, and set interrupt enable. */
761// DREG = CSR0_BABL | CSR0_CERR | CSR0_MISS | CSR0_MERR |
762// CSR0_IDON | CSR0_INEA;
763
764 REGA(CSR0) = CSR0_INEA;
765
766 if(DREG & (CSR0_RINT | CSR0_TINT)) {
767 DPRINTK(2, ("restarting interrupt, csr0=%#04x\n", DREG));
768 goto still_more;
769 }
770
771 DPRINTK( 2, ( "%s: exiting interrupt, csr0=%#04x.\n",
772 dev->name, DREG ));
773 in_interrupt = 0;
774 return IRQ_HANDLED;
775}
776
777/* get packet, toss into skbuff */
778static int lance_rx( struct net_device *dev )
779{
780 struct lance_private *lp = netdev_priv(dev);
781 int entry = lp->new_rx;
782
783 /* If we own the next entry, it's a new packet. Send it up. */
784 while( (MEM->rx_head[entry].flag & RMD1_OWN) == RMD1_OWN_HOST ) {
785 struct lance_rx_head *head = &(MEM->rx_head[entry]);
786 int status = head->flag;
6aa20a22 787
1da177e4
LT		 788 if (status != (RMD1_ENP|RMD1_STP)) { /* There was an error. */
789 /* There is a tricky error noted by John Murphy,
6aa20a22 790 <murf@perftech.com> to Russ Nelson: Even with
1da177e4
LT		 791 full-sized buffers it's possible for a jabber packet to use two
792 buffers, with only the last correctly noting the error. */
793 if (status & RMD1_ENP) /* Only count a general error at the */
09f75cd7
JG		 794 dev->stats.rx_errors++; /* end of a packet.*/
795 if (status & RMD1_FRAM) dev->stats.rx_frame_errors++;
796 if (status & RMD1_OFLO) dev->stats.rx_over_errors++;
797 if (status & RMD1_CRC) dev->stats.rx_crc_errors++;
798 if (status & RMD1_BUFF) dev->stats.rx_fifo_errors++;
1da177e4
LT		 799 head->flag &= (RMD1_ENP|RMD1_STP);
800 } else {
801 /* Malloc up new buffer, compatible with net-3. */
802// short pkt_len = head->msg_length;// & 0xfff;
803 short pkt_len = (head->msg_length & 0xfff) - 4;
804 struct sk_buff *skb;
805
806 if (pkt_len < 60) {
807 printk( "%s: Runt packet!\n", dev->name );
09f75cd7 808 dev->stats.rx_errors++;
1da177e4
LT		 809 }
810 else {
811 skb = dev_alloc_skb( pkt_len+2 );
812 if (skb == NULL) {
813 DPRINTK( 1, ( "%s: Memory squeeze, deferring packet.\n",
814 dev->name ));
6aa20a22 815
09f75cd7 816 dev->stats.rx_dropped++;
1da177e4
LT		 817 head->msg_length = 0;
818 head->flag |= RMD1_OWN_CHIP;
819 lp->new_rx = (lp->new_rx+1) &
820 RX_RING_MOD_MASK;
821 }
822
823#if 0
824 if (lance_debug >= 3) {
0795af57 825 u_char *data = PKTBUF_ADDR(head);
0795af57 826 printk("%s: RX pkt %d type 0x%04x"
e174961c 827 " from %pM to %pM",
0795af57 828 dev->name, lp->new_tx, ((u_short *)data)[6],
e174961c 829 &data[6], data);
0795af57 830
1da177e4
LT		 831 printk(" data %02x %02x %02x %02x %02x %02x %02x %02x "
832 "len %d at %08x\n",
833 data[15], data[16], data[17], data[18],
834 data[19], data[20], data[21], data[22],
835 pkt_len, data);
836 }
837#endif
838 if (lance_debug >= 3) {
839 u_char *data = PKTBUF_ADDR(head);
840 printk( "%s: RX pkt %d type 0x%04x len %d\n ", dev->name, entry, ((u_short *)data)[6], pkt_len);
6aa20a22 841 }
1da177e4
LT		 842
843
1da177e4
LT		 844 skb_reserve( skb, 2 ); /* 16 byte align */
845 skb_put( skb, pkt_len ); /* Make room */
8c7b7faa 846 skb_copy_to_linear_data(skb,
1da177e4 847 PKTBUF_ADDR(head),
8c7b7faa 848 pkt_len);
1da177e4
LT		 849
850 skb->protocol = eth_type_trans( skb, dev );
851 netif_rx( skb );
09f75cd7
JG		 852 dev->stats.rx_packets++;
853 dev->stats.rx_bytes += pkt_len;
1da177e4
LT		 854 }
855 }
856
857// head->buf_length = -PKT_BUF_SZ | 0xf000;
858 head->msg_length = 0;
859 head->flag = RMD1_OWN_CHIP;
860
861 entry = lp->new_rx = (lp->new_rx +1) & RX_RING_MOD_MASK;
862 }
863
864 /* From lance.c (Donald Becker): */
865 /* We should check that at least two ring entries are free.
866 If not, we should free one and mark stats->rx_dropped++. */
867
868 return 0;
869}
870
871
872static int lance_close( struct net_device *dev )
873{
874 struct lance_private *lp = netdev_priv(dev);
875
876 netif_stop_queue(dev);
877
878 AREG = CSR0;
879
880 DPRINTK( 2, ( "%s: Shutting down ethercard, status was %2.2x.\n",
881 dev->name, DREG ));
882
883 /* We stop the LANCE here -- it occasionally polls
884 memory if we don't. */
885 DREG = CSR0_STOP;
886 return 0;
887}
888
889
1da177e4
LT		 890/* Set or clear the multicast filter for this adaptor.
891 num_addrs == -1 Promiscuous mode, receive all packets
892 num_addrs == 0 Normal mode, clear multicast list
893 num_addrs > 0 Multicast mode, receive normal and MC packets, and do
894 best-effort filtering.
895 */
896
897/* completely untested on a sun3 */
898static void set_multicast_list( struct net_device *dev )
899{
900 struct lance_private *lp = netdev_priv(dev);
901
902 if(netif_queue_stopped(dev))
903 /* Only possible if board is already started */
904 return;
905
906 /* We take the simple way out and always enable promiscuous mode. */
907 DREG = CSR0_STOP; /* Temporarily stop the lance. */
908
909 if (dev->flags & IFF_PROMISC) {
910 /* Log any net taps. */
d5b20697 911 DPRINTK( 3, ( "%s: Promiscuous mode enabled.\n", dev->name ));
1da177e4
LT		 912 REGA( CSR15 ) = 0x8000; /* Set promiscuous mode */
913 } else {
914 short multicast_table[4];
915 int num_addrs = dev->mc_count;
916 int i;
917 /* We don't use the multicast table, but rely on upper-layer
918 * filtering. */
919 memset( multicast_table, (num_addrs == 0) ? 0 : -1,
920 sizeof(multicast_table) );
921 for( i = 0; i < 4; i++ )
922 REGA( CSR8+i ) = multicast_table[i];
923 REGA( CSR15 ) = 0; /* Unset promiscuous mode */
924 }
925
926 /*
927 * Always set BSWP after a STOP as STOP puts it back into
928 * little endian mode.
929 */
930 REGA( CSR3 ) = CSR3_BSWP;
931
932 /* Resume normal operation and reset AREG to CSR0 */
933 REGA( CSR0 ) = CSR0_IDON | CSR0_INEA | CSR0_STRT;
934}
935
936
937#ifdef MODULE
938
939static struct net_device *sun3lance_dev;
940
afc8eb46 941int __init init_module(void)
1da177e4
LT		 942{
943 sun3lance_dev = sun3lance_probe(-1);
944 if (IS_ERR(sun3lance_dev))
945 return PTR_ERR(sun3lance_dev);
946 return 0;
947}
948
afc8eb46 949void __exit cleanup_module(void)
1da177e4
LT		 950{
951 unregister_netdev(sun3lance_dev);
952#ifdef CONFIG_SUN3
437111ca 953 iounmap((void __iomem *)sun3lance_dev->base_addr);
1da177e4
LT		 954#endif
955 free_netdev(sun3lance_dev);
956}
957
958#endif /* MODULE */
959
Linux 6.x block layer and io_uring tree(s)