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New driver "sfc" for Solarstorm SFC4000 controller.
[linux-2.6-block.git] / drivers / net / sfc / efx.c
CommitLineData
8ceee660
BH		 1/****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2005-2008 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#include <linux/module.h>
12#include <linux/pci.h>
13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/delay.h>
16#include <linux/notifier.h>
17#include <linux/ip.h>
18#include <linux/tcp.h>
19#include <linux/in.h>
20#include <linux/crc32.h>
21#include <linux/ethtool.h>
22#include "net_driver.h"
23#include "gmii.h"
24#include "ethtool.h"
25#include "tx.h"
26#include "rx.h"
27#include "efx.h"
28#include "mdio_10g.h"
29#include "falcon.h"
30#include "workarounds.h"
31#include "mac.h"
32
33#define EFX_MAX_MTU (9 * 1024)
34
35/* RX slow fill workqueue. If memory allocation fails in the fast path,
36 * a work item is pushed onto this work queue to retry the allocation later,
37 * to avoid the NIC being starved of RX buffers. Since this is a per cpu
38 * workqueue, there is nothing to be gained in making it per NIC
39 */
40static struct workqueue_struct *refill_workqueue;
41
42/**************************************************************************
43 *
44 * Configurable values
45 *
46 *************************************************************************/
47
48/*
49 * Enable large receive offload (LRO) aka soft segment reassembly (SSR)
50 *
51 * This sets the default for new devices. It can be controlled later
52 * using ethtool.
53 */
54static int lro = 1;
55module_param(lro, int, 0644);
56MODULE_PARM_DESC(lro, "Large receive offload acceleration");
57
58/*
59 * Use separate channels for TX and RX events
60 *
61 * Set this to 1 to use separate channels for TX and RX. It allows us to
62 * apply a higher level of interrupt moderation to TX events.
63 *
64 * This is forced to 0 for MSI interrupt mode as the interrupt vector
65 * is not written
66 */
67static unsigned int separate_tx_and_rx_channels = 1;
68
69/* This is the weight assigned to each of the (per-channel) virtual
70 * NAPI devices.
71 */
72static int napi_weight = 64;
73
74/* This is the time (in jiffies) between invocations of the hardware
75 * monitor, which checks for known hardware bugs and resets the
76 * hardware and driver as necessary.
77 */
78unsigned int efx_monitor_interval = 1 * HZ;
79
80/* This controls whether or not the hardware monitor will trigger a
81 * reset when it detects an error condition.
82 */
83static unsigned int monitor_reset = 1;
84
85/* This controls whether or not the driver will initialise devices
86 * with invalid MAC addresses stored in the EEPROM or flash. If true,
87 * such devices will be initialised with a random locally-generated
88 * MAC address. This allows for loading the sfc_mtd driver to
89 * reprogram the flash, even if the flash contents (including the MAC
90 * address) have previously been erased.
91 */
92static unsigned int allow_bad_hwaddr;
93
94/* Initial interrupt moderation settings. They can be modified after
95 * module load with ethtool.
96 *
97 * The default for RX should strike a balance between increasing the
98 * round-trip latency and reducing overhead.
99 */
100static unsigned int rx_irq_mod_usec = 60;
101
102/* Initial interrupt moderation settings. They can be modified after
103 * module load with ethtool.
104 *
105 * This default is chosen to ensure that a 10G link does not go idle
106 * while a TX queue is stopped after it has become full. A queue is
107 * restarted when it drops below half full. The time this takes (assuming
108 * worst case 3 descriptors per packet and 1024 descriptors) is
109 * 512 / 3 * 1.2 = 205 usec.
110 */
111static unsigned int tx_irq_mod_usec = 150;
112
113/* This is the first interrupt mode to try out of:
114 * 0 => MSI-X
115 * 1 => MSI
116 * 2 => legacy
117 */
118static unsigned int interrupt_mode;
119
120/* This is the requested number of CPUs to use for Receive-Side Scaling (RSS),
121 * i.e. the number of CPUs among which we may distribute simultaneous
122 * interrupt handling.
123 *
124 * Cards without MSI-X will only target one CPU via legacy or MSI interrupt.
125 * The default (0) means to assign an interrupt to each package (level II cache)
126 */
127static unsigned int rss_cpus;
128module_param(rss_cpus, uint, 0444);
129MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling");
130
131/**************************************************************************
132 *
133 * Utility functions and prototypes
134 *
135 *************************************************************************/
136static void efx_remove_channel(struct efx_channel *channel);
137static void efx_remove_port(struct efx_nic *efx);
138static void efx_fini_napi(struct efx_nic *efx);
139static void efx_fini_channels(struct efx_nic *efx);
140
141#define EFX_ASSERT_RESET_SERIALISED(efx) \
142 do { \
143 if ((efx->state == STATE_RUNNING) || \
144 (efx->state == STATE_RESETTING)) \
145 ASSERT_RTNL(); \
146 } while (0)
147
148/**************************************************************************
149 *
150 * Event queue processing
151 *
152 *************************************************************************/
153
154/* Process channel's event queue
155 *
156 * This function is responsible for processing the event queue of a
157 * single channel. The caller must guarantee that this function will
158 * never be concurrently called more than once on the same channel,
159 * though different channels may be being processed concurrently.
160 */
161static inline int efx_process_channel(struct efx_channel *channel, int rx_quota)
162{
163 int rxdmaqs;
164 struct efx_rx_queue *rx_queue;
165
166 if (unlikely(channel->efx->reset_pending != RESET_TYPE_NONE ||
167 !channel->enabled))
168 return rx_quota;
169
170 rxdmaqs = falcon_process_eventq(channel, &rx_quota);
171
172 /* Deliver last RX packet. */
173 if (channel->rx_pkt) {
174 __efx_rx_packet(channel, channel->rx_pkt,
175 channel->rx_pkt_csummed);
176 channel->rx_pkt = NULL;
177 }
178
179 efx_flush_lro(channel);
180 efx_rx_strategy(channel);
181
182 /* Refill descriptor rings as necessary */
183 rx_queue = &channel->efx->rx_queue[0];
184 while (rxdmaqs) {
185 if (rxdmaqs & 0x01)
186 efx_fast_push_rx_descriptors(rx_queue);
187 rx_queue++;
188 rxdmaqs >>= 1;
189 }
190
191 return rx_quota;
192}
193
194/* Mark channel as finished processing
195 *
196 * Note that since we will not receive further interrupts for this
197 * channel before we finish processing and call the eventq_read_ack()
198 * method, there is no need to use the interrupt hold-off timers.
199 */
200static inline void efx_channel_processed(struct efx_channel *channel)
201{
202 /* Write to EVQ_RPTR_REG. If a new event arrived in a race
203 * with finishing processing, a new interrupt will be raised.
204 */
205 channel->work_pending = 0;
206 smp_wmb(); /* Ensure channel updated before any new interrupt. */
207 falcon_eventq_read_ack(channel);
208}
209
210/* NAPI poll handler
211 *
212 * NAPI guarantees serialisation of polls of the same device, which
213 * provides the guarantee required by efx_process_channel().
214 */
215static int efx_poll(struct napi_struct *napi, int budget)
216{
217 struct efx_channel *channel =
218 container_of(napi, struct efx_channel, napi_str);
219 struct net_device *napi_dev = channel->napi_dev;
220 int unused;
221 int rx_packets;
222
223 EFX_TRACE(channel->efx, "channel %d NAPI poll executing on CPU %d\n",
224 channel->channel, raw_smp_processor_id());
225
226 unused = efx_process_channel(channel, budget);
227 rx_packets = (budget - unused);
228
229 if (rx_packets < budget) {
230 /* There is no race here; although napi_disable() will
231 * only wait for netif_rx_complete(), this isn't a problem
232 * since efx_channel_processed() will have no effect if
233 * interrupts have already been disabled.
234 */
235 netif_rx_complete(napi_dev, napi);
236 efx_channel_processed(channel);
237 }
238
239 return rx_packets;
240}
241
242/* Process the eventq of the specified channel immediately on this CPU
243 *
244 * Disable hardware generated interrupts, wait for any existing
245 * processing to finish, then directly poll (and ack ) the eventq.
246 * Finally reenable NAPI and interrupts.
247 *
248 * Since we are touching interrupts the caller should hold the suspend lock
249 */
250void efx_process_channel_now(struct efx_channel *channel)
251{
252 struct efx_nic *efx = channel->efx;
253
254 BUG_ON(!channel->used_flags);
255 BUG_ON(!channel->enabled);
256
257 /* Disable interrupts and wait for ISRs to complete */
258 falcon_disable_interrupts(efx);
259 if (efx->legacy_irq)
260 synchronize_irq(efx->legacy_irq);
261 if (channel->has_interrupt && channel->irq)
262 synchronize_irq(channel->irq);
263
264 /* Wait for any NAPI processing to complete */
265 napi_disable(&channel->napi_str);
266
267 /* Poll the channel */
268 (void) efx_process_channel(channel, efx->type->evq_size);
269
270 /* Ack the eventq. This may cause an interrupt to be generated
271 * when they are reenabled */
272 efx_channel_processed(channel);
273
274 napi_enable(&channel->napi_str);
275 falcon_enable_interrupts(efx);
276}
277
278/* Create event queue
279 * Event queue memory allocations are done only once. If the channel
280 * is reset, the memory buffer will be reused; this guards against
281 * errors during channel reset and also simplifies interrupt handling.
282 */
283static int efx_probe_eventq(struct efx_channel *channel)
284{
285 EFX_LOG(channel->efx, "chan %d create event queue\n", channel->channel);
286
287 return falcon_probe_eventq(channel);
288}
289
290/* Prepare channel's event queue */
291static int efx_init_eventq(struct efx_channel *channel)
292{
293 EFX_LOG(channel->efx, "chan %d init event queue\n", channel->channel);
294
295 channel->eventq_read_ptr = 0;
296
297 return falcon_init_eventq(channel);
298}
299
300static void efx_fini_eventq(struct efx_channel *channel)
301{
302 EFX_LOG(channel->efx, "chan %d fini event queue\n", channel->channel);
303
304 falcon_fini_eventq(channel);
305}
306
307static void efx_remove_eventq(struct efx_channel *channel)
308{
309 EFX_LOG(channel->efx, "chan %d remove event queue\n", channel->channel);
310
311 falcon_remove_eventq(channel);
312}
313
314/**************************************************************************
315 *
316 * Channel handling
317 *
318 *************************************************************************/
319
320/* Setup per-NIC RX buffer parameters.
321 * Calculate the rx buffer allocation parameters required to support
322 * the current MTU, including padding for header alignment and overruns.
323 */
324static void efx_calc_rx_buffer_params(struct efx_nic *efx)
325{
326 unsigned int order, len;
327
328 len = (max(EFX_PAGE_IP_ALIGN, NET_IP_ALIGN) +
329 EFX_MAX_FRAME_LEN(efx->net_dev->mtu) +
330 efx->type->rx_buffer_padding);
331
332 /* Calculate page-order */
333 for (order = 0; ((1u << order) * PAGE_SIZE) < len; ++order)
334 ;
335
336 efx->rx_buffer_len = len;
337 efx->rx_buffer_order = order;
338}
339
340static int efx_probe_channel(struct efx_channel *channel)
341{
342 struct efx_tx_queue *tx_queue;
343 struct efx_rx_queue *rx_queue;
344 int rc;
345
346 EFX_LOG(channel->efx, "creating channel %d\n", channel->channel);
347
348 rc = efx_probe_eventq(channel);
349 if (rc)
350 goto fail1;
351
352 efx_for_each_channel_tx_queue(tx_queue, channel) {
353 rc = efx_probe_tx_queue(tx_queue);
354 if (rc)
355 goto fail2;
356 }
357
358 efx_for_each_channel_rx_queue(rx_queue, channel) {
359 rc = efx_probe_rx_queue(rx_queue);
360 if (rc)
361 goto fail3;
362 }
363
364 channel->n_rx_frm_trunc = 0;
365
366 return 0;
367
368 fail3:
369 efx_for_each_channel_rx_queue(rx_queue, channel)
370 efx_remove_rx_queue(rx_queue);
371 fail2:
372 efx_for_each_channel_tx_queue(tx_queue, channel)
373 efx_remove_tx_queue(tx_queue);
374 fail1:
375 return rc;
376}
377
378
379/* Channels are shutdown and reinitialised whilst the NIC is running
380 * to propagate configuration changes (mtu, checksum offload), or
381 * to clear hardware error conditions
382 */
383static int efx_init_channels(struct efx_nic *efx)
384{
385 struct efx_tx_queue *tx_queue;
386 struct efx_rx_queue *rx_queue;
387 struct efx_channel *channel;
388 int rc = 0;
389
390 efx_calc_rx_buffer_params(efx);
391
392 /* Initialise the channels */
393 efx_for_each_channel(channel, efx) {
394 EFX_LOG(channel->efx, "init chan %d\n", channel->channel);
395
396 rc = efx_init_eventq(channel);
397 if (rc)
398 goto err;
399
400 efx_for_each_channel_tx_queue(tx_queue, channel) {
401 rc = efx_init_tx_queue(tx_queue);
402 if (rc)
403 goto err;
404 }
405
406 /* The rx buffer allocation strategy is MTU dependent */
407 efx_rx_strategy(channel);
408
409 efx_for_each_channel_rx_queue(rx_queue, channel) {
410 rc = efx_init_rx_queue(rx_queue);
411 if (rc)
412 goto err;
413 }
414
415 WARN_ON(channel->rx_pkt != NULL);
416 efx_rx_strategy(channel);
417 }
418
419 return 0;
420
421 err:
422 EFX_ERR(efx, "failed to initialise channel %d\n",
423 channel ? channel->channel : -1);
424 efx_fini_channels(efx);
425 return rc;
426}
427
428/* This enables event queue processing and packet transmission.
429 *
430 * Note that this function is not allowed to fail, since that would
431 * introduce too much complexity into the suspend/resume path.
432 */
433static void efx_start_channel(struct efx_channel *channel)
434{
435 struct efx_rx_queue *rx_queue;
436
437 EFX_LOG(channel->efx, "starting chan %d\n", channel->channel);
438
439 if (!(channel->efx->net_dev->flags & IFF_UP))
440 netif_napi_add(channel->napi_dev, &channel->napi_str,
441 efx_poll, napi_weight);
442
443 channel->work_pending = 0;
444 channel->enabled = 1;
445 smp_wmb(); /* ensure channel updated before first interrupt */
446
447 napi_enable(&channel->napi_str);
448
449 /* Load up RX descriptors */
450 efx_for_each_channel_rx_queue(rx_queue, channel)
451 efx_fast_push_rx_descriptors(rx_queue);
452}
453
454/* This disables event queue processing and packet transmission.
455 * This function does not guarantee that all queue processing
456 * (e.g. RX refill) is complete.
457 */
458static void efx_stop_channel(struct efx_channel *channel)
459{
460 struct efx_rx_queue *rx_queue;
461
462 if (!channel->enabled)
463 return;
464
465 EFX_LOG(channel->efx, "stop chan %d\n", channel->channel);
466
467 channel->enabled = 0;
468 napi_disable(&channel->napi_str);
469
470 /* Ensure that any worker threads have exited or will be no-ops */
471 efx_for_each_channel_rx_queue(rx_queue, channel) {
472 spin_lock_bh(&rx_queue->add_lock);
473 spin_unlock_bh(&rx_queue->add_lock);
474 }
475}
476
477static void efx_fini_channels(struct efx_nic *efx)
478{
479 struct efx_channel *channel;
480 struct efx_tx_queue *tx_queue;
481 struct efx_rx_queue *rx_queue;
482
483 EFX_ASSERT_RESET_SERIALISED(efx);
484 BUG_ON(efx->port_enabled);
485
486 efx_for_each_channel(channel, efx) {
487 EFX_LOG(channel->efx, "shut down chan %d\n", channel->channel);
488
489 efx_for_each_channel_rx_queue(rx_queue, channel)
490 efx_fini_rx_queue(rx_queue);
491 efx_for_each_channel_tx_queue(tx_queue, channel)
492 efx_fini_tx_queue(tx_queue);
493 }
494
495 /* Do the event queues last so that we can handle flush events
496 * for all DMA queues. */
497 efx_for_each_channel(channel, efx) {
498 EFX_LOG(channel->efx, "shut down evq %d\n", channel->channel);
499
500 efx_fini_eventq(channel);
501 }
502}
503
504static void efx_remove_channel(struct efx_channel *channel)
505{
506 struct efx_tx_queue *tx_queue;
507 struct efx_rx_queue *rx_queue;
508
509 EFX_LOG(channel->efx, "destroy chan %d\n", channel->channel);
510
511 efx_for_each_channel_rx_queue(rx_queue, channel)
512 efx_remove_rx_queue(rx_queue);
513 efx_for_each_channel_tx_queue(tx_queue, channel)
514 efx_remove_tx_queue(tx_queue);
515 efx_remove_eventq(channel);
516
517 channel->used_flags = 0;
518}
519
520void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue, int delay)
521{
522 queue_delayed_work(refill_workqueue, &rx_queue->work, delay);
523}
524
525/**************************************************************************
526 *
527 * Port handling
528 *
529 **************************************************************************/
530
531/* This ensures that the kernel is kept informed (via
532 * netif_carrier_on/off) of the link status, and also maintains the
533 * link status's stop on the port's TX queue.
534 */
535static void efx_link_status_changed(struct efx_nic *efx)
536{
537 int carrier_ok;
538
539 /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure
540 * that no events are triggered between unregister_netdev() and the
541 * driver unloading. A more general condition is that NETDEV_CHANGE
542 * can only be generated between NETDEV_UP and NETDEV_DOWN */
543 if (!netif_running(efx->net_dev))
544 return;
545
546 carrier_ok = netif_carrier_ok(efx->net_dev) ? 1 : 0;
547 if (efx->link_up != carrier_ok) {
548 efx->n_link_state_changes++;
549
550 if (efx->link_up)
551 netif_carrier_on(efx->net_dev);
552 else
553 netif_carrier_off(efx->net_dev);
554 }
555
556 /* Status message for kernel log */
557 if (efx->link_up) {
558 struct mii_if_info *gmii = &efx->mii;
559 unsigned adv, lpa;
560 /* NONE here means direct XAUI from the controller, with no
561 * MDIO-attached device we can query. */
562 if (efx->phy_type != PHY_TYPE_NONE) {
563 adv = gmii_advertised(gmii);
564 lpa = gmii_lpa(gmii);
565 } else {
566 lpa = GM_LPA_10000 | LPA_DUPLEX;
567 adv = lpa;
568 }
569 EFX_INFO(efx, "link up at %dMbps %s-duplex "
570 "(adv %04x lpa %04x) (MTU %d)%s\n",
571 (efx->link_options & GM_LPA_10000 ? 10000 :
572 (efx->link_options & GM_LPA_1000 ? 1000 :
573 (efx->link_options & GM_LPA_100 ? 100 :
574 10))),
575 (efx->link_options & GM_LPA_DUPLEX ?
576 "full" : "half"),
577 adv, lpa,
578 efx->net_dev->mtu,
579 (efx->promiscuous ? " [PROMISC]" : ""));
580 } else {
581 EFX_INFO(efx, "link down\n");
582 }
583
584}
585
586/* This call reinitialises the MAC to pick up new PHY settings. The
587 * caller must hold the mac_lock */
588static void __efx_reconfigure_port(struct efx_nic *efx)
589{
590 WARN_ON(!mutex_is_locked(&efx->mac_lock));
591
592 EFX_LOG(efx, "reconfiguring MAC from PHY settings on CPU %d\n",
593 raw_smp_processor_id());
594
595 falcon_reconfigure_xmac(efx);
596
597 /* Inform kernel of loss/gain of carrier */
598 efx_link_status_changed(efx);
599}
600
601/* Reinitialise the MAC to pick up new PHY settings, even if the port is
602 * disabled. */
603void efx_reconfigure_port(struct efx_nic *efx)
604{
605 EFX_ASSERT_RESET_SERIALISED(efx);
606
607 mutex_lock(&efx->mac_lock);
608 __efx_reconfigure_port(efx);
609 mutex_unlock(&efx->mac_lock);
610}
611
612/* Asynchronous efx_reconfigure_port work item. To speed up efx_flush_all()
613 * we don't efx_reconfigure_port() if the port is disabled. Care is taken
614 * in efx_stop_all() and efx_start_port() to prevent PHY events being lost */
615static void efx_reconfigure_work(struct work_struct *data)
616{
617 struct efx_nic *efx = container_of(data, struct efx_nic,
618 reconfigure_work);
619
620 mutex_lock(&efx->mac_lock);
621 if (efx->port_enabled)
622 __efx_reconfigure_port(efx);
623 mutex_unlock(&efx->mac_lock);
624}
625
626static int efx_probe_port(struct efx_nic *efx)
627{
628 int rc;
629
630 EFX_LOG(efx, "create port\n");
631
632 /* Connect up MAC/PHY operations table and read MAC address */
633 rc = falcon_probe_port(efx);
634 if (rc)
635 goto err;
636
637 /* Sanity check MAC address */
638 if (is_valid_ether_addr(efx->mac_address)) {
639 memcpy(efx->net_dev->dev_addr, efx->mac_address, ETH_ALEN);
640 } else {
641 DECLARE_MAC_BUF(mac);
642
643 EFX_ERR(efx, "invalid MAC address %s\n",
644 print_mac(mac, efx->mac_address));
645 if (!allow_bad_hwaddr) {
646 rc = -EINVAL;
647 goto err;
648 }
649 random_ether_addr(efx->net_dev->dev_addr);
650 EFX_INFO(efx, "using locally-generated MAC %s\n",
651 print_mac(mac, efx->net_dev->dev_addr));
652 }
653
654 return 0;
655
656 err:
657 efx_remove_port(efx);
658 return rc;
659}
660
661static int efx_init_port(struct efx_nic *efx)
662{
663 int rc;
664
665 EFX_LOG(efx, "init port\n");
666
667 /* Initialise the MAC and PHY */
668 rc = falcon_init_xmac(efx);
669 if (rc)
670 return rc;
671
672 efx->port_initialized = 1;
673
674 /* Reconfigure port to program MAC registers */
675 falcon_reconfigure_xmac(efx);
676
677 return 0;
678}
679
680/* Allow efx_reconfigure_port() to be scheduled, and close the window
681 * between efx_stop_port and efx_flush_all whereby a previously scheduled
682 * efx_reconfigure_port() may have been cancelled */
683static void efx_start_port(struct efx_nic *efx)
684{
685 EFX_LOG(efx, "start port\n");
686 BUG_ON(efx->port_enabled);
687
688 mutex_lock(&efx->mac_lock);
689 efx->port_enabled = 1;
690 __efx_reconfigure_port(efx);
691 mutex_unlock(&efx->mac_lock);
692}
693
694/* Prevent efx_reconfigure_work and efx_monitor() from executing, and
695 * efx_set_multicast_list() from scheduling efx_reconfigure_work.
696 * efx_reconfigure_work can still be scheduled via NAPI processing
697 * until efx_flush_all() is called */
698static void efx_stop_port(struct efx_nic *efx)
699{
700 EFX_LOG(efx, "stop port\n");
701
702 mutex_lock(&efx->mac_lock);
703 efx->port_enabled = 0;
704 mutex_unlock(&efx->mac_lock);
705
706 /* Serialise against efx_set_multicast_list() */
707 if (NET_DEV_REGISTERED(efx)) {
708 netif_tx_lock_bh(efx->net_dev);
709 netif_tx_unlock_bh(efx->net_dev);
710 }
711}
712
713static void efx_fini_port(struct efx_nic *efx)
714{
715 EFX_LOG(efx, "shut down port\n");
716
717 if (!efx->port_initialized)
718 return;
719
720 falcon_fini_xmac(efx);
721 efx->port_initialized = 0;
722
723 efx->link_up = 0;
724 efx_link_status_changed(efx);
725}
726
727static void efx_remove_port(struct efx_nic *efx)
728{
729 EFX_LOG(efx, "destroying port\n");
730
731 falcon_remove_port(efx);
732}
733
734/**************************************************************************
735 *
736 * NIC handling
737 *
738 **************************************************************************/
739
740/* This configures the PCI device to enable I/O and DMA. */
741static int efx_init_io(struct efx_nic *efx)
742{
743 struct pci_dev *pci_dev = efx->pci_dev;
744 dma_addr_t dma_mask = efx->type->max_dma_mask;
745 int rc;
746
747 EFX_LOG(efx, "initialising I/O\n");
748
749 rc = pci_enable_device(pci_dev);
750 if (rc) {
751 EFX_ERR(efx, "failed to enable PCI device\n");
752 goto fail1;
753 }
754
755 pci_set_master(pci_dev);
756
757 /* Set the PCI DMA mask. Try all possibilities from our
758 * genuine mask down to 32 bits, because some architectures
759 * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit
760 * masks event though they reject 46 bit masks.
761 */
762 while (dma_mask > 0x7fffffffUL) {
763 if (pci_dma_supported(pci_dev, dma_mask) &&
764 ((rc = pci_set_dma_mask(pci_dev, dma_mask)) == 0))
765 break;
766 dma_mask >>= 1;
767 }
768 if (rc) {
769 EFX_ERR(efx, "could not find a suitable DMA mask\n");
770 goto fail2;
771 }
772 EFX_LOG(efx, "using DMA mask %llx\n", (unsigned long long) dma_mask);
773 rc = pci_set_consistent_dma_mask(pci_dev, dma_mask);
774 if (rc) {
775 /* pci_set_consistent_dma_mask() is not *allowed* to
776 * fail with a mask that pci_set_dma_mask() accepted,
777 * but just in case...
778 */
779 EFX_ERR(efx, "failed to set consistent DMA mask\n");
780 goto fail2;
781 }
782
783 efx->membase_phys = pci_resource_start(efx->pci_dev,
784 efx->type->mem_bar);
785 rc = pci_request_region(pci_dev, efx->type->mem_bar, "sfc");
786 if (rc) {
787 EFX_ERR(efx, "request for memory BAR failed\n");
788 rc = -EIO;
789 goto fail3;
790 }
791 efx->membase = ioremap_nocache(efx->membase_phys,
792 efx->type->mem_map_size);
793 if (!efx->membase) {
794 EFX_ERR(efx, "could not map memory BAR %d at %lx+%x\n",
795 efx->type->mem_bar, efx->membase_phys,
796 efx->type->mem_map_size);
797 rc = -ENOMEM;
798 goto fail4;
799 }
800 EFX_LOG(efx, "memory BAR %u at %lx+%x (virtual %p)\n",
801 efx->type->mem_bar, efx->membase_phys, efx->type->mem_map_size,
802 efx->membase);
803
804 return 0;
805
806 fail4:
807 release_mem_region(efx->membase_phys, efx->type->mem_map_size);
808 fail3:
809 efx->membase_phys = 0UL;
810 fail2:
811 pci_disable_device(efx->pci_dev);
812 fail1:
813 return rc;
814}
815
816static void efx_fini_io(struct efx_nic *efx)
817{
818 EFX_LOG(efx, "shutting down I/O\n");
819
820 if (efx->membase) {
821 iounmap(efx->membase);
822 efx->membase = NULL;
823 }
824
825 if (efx->membase_phys) {
826 pci_release_region(efx->pci_dev, efx->type->mem_bar);
827 efx->membase_phys = 0UL;
828 }
829
830 pci_disable_device(efx->pci_dev);
831}
832
833/* Probe the number and type of interrupts we are able to obtain. */
834static void efx_probe_interrupts(struct efx_nic *efx)
835{
836 int max_channel = efx->type->phys_addr_channels - 1;
837 struct msix_entry xentries[EFX_MAX_CHANNELS];
838 int rc, i;
839
840 if (efx->interrupt_mode == EFX_INT_MODE_MSIX) {
841 BUG_ON(!pci_find_capability(efx->pci_dev, PCI_CAP_ID_MSIX));
842
843 efx->rss_queues = rss_cpus ? rss_cpus : num_online_cpus();
844 efx->rss_queues = min(efx->rss_queues, max_channel + 1);
845 efx->rss_queues = min(efx->rss_queues, EFX_MAX_CHANNELS);
846
847 /* Request maximum number of MSI interrupts, and fill out
848 * the channel interrupt information the allowed allocation */
849 for (i = 0; i < efx->rss_queues; i++)
850 xentries[i].entry = i;
851 rc = pci_enable_msix(efx->pci_dev, xentries, efx->rss_queues);
852 if (rc > 0) {
853 EFX_BUG_ON_PARANOID(rc >= efx->rss_queues);
854 efx->rss_queues = rc;
855 rc = pci_enable_msix(efx->pci_dev, xentries,
856 efx->rss_queues);
857 }
858
859 if (rc == 0) {
860 for (i = 0; i < efx->rss_queues; i++) {
861 efx->channel[i].has_interrupt = 1;
862 efx->channel[i].irq = xentries[i].vector;
863 }
864 } else {
865 /* Fall back to single channel MSI */
866 efx->interrupt_mode = EFX_INT_MODE_MSI;
867 EFX_ERR(efx, "could not enable MSI-X\n");
868 }
869 }
870
871 /* Try single interrupt MSI */
872 if (efx->interrupt_mode == EFX_INT_MODE_MSI) {
873 efx->rss_queues = 1;
874 rc = pci_enable_msi(efx->pci_dev);
875 if (rc == 0) {
876 efx->channel[0].irq = efx->pci_dev->irq;
877 efx->channel[0].has_interrupt = 1;
878 } else {
879 EFX_ERR(efx, "could not enable MSI\n");
880 efx->interrupt_mode = EFX_INT_MODE_LEGACY;
881 }
882 }
883
884 /* Assume legacy interrupts */
885 if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) {
886 efx->rss_queues = 1;
887 /* Every channel is interruptible */
888 for (i = 0; i < EFX_MAX_CHANNELS; i++)
889 efx->channel[i].has_interrupt = 1;
890 efx->legacy_irq = efx->pci_dev->irq;
891 }
892}
893
894static void efx_remove_interrupts(struct efx_nic *efx)
895{
896 struct efx_channel *channel;
897
898 /* Remove MSI/MSI-X interrupts */
899 efx_for_each_channel_with_interrupt(channel, efx)
900 channel->irq = 0;
901 pci_disable_msi(efx->pci_dev);
902 pci_disable_msix(efx->pci_dev);
903
904 /* Remove legacy interrupt */
905 efx->legacy_irq = 0;
906}
907
908/* Select number of used resources
909 * Should be called after probe_interrupts()
910 */
911static void efx_select_used(struct efx_nic *efx)
912{
913 struct efx_tx_queue *tx_queue;
914 struct efx_rx_queue *rx_queue;
915 int i;
916
917 /* TX queues. One per port per channel with TX capability
918 * (more than one per port won't work on Linux, due to out
919 * of order issues... but will be fine on Solaris)
920 */
921 tx_queue = &efx->tx_queue[0];
922
923 /* Perform this for each channel with TX capabilities.
924 * At the moment, we only support a single TX queue
925 */
926 tx_queue->used = 1;
927 if ((!EFX_INT_MODE_USE_MSI(efx)) && separate_tx_and_rx_channels)
928 tx_queue->channel = &efx->channel[1];
929 else
930 tx_queue->channel = &efx->channel[0];
931 tx_queue->channel->used_flags |= EFX_USED_BY_TX;
932 tx_queue++;
933
934 /* RX queues. Each has a dedicated channel. */
935 for (i = 0; i < EFX_MAX_RX_QUEUES; i++) {
936 rx_queue = &efx->rx_queue[i];
937
938 if (i < efx->rss_queues) {
939 rx_queue->used = 1;
940 /* If we allow multiple RX queues per channel
941 * we need to decide that here
942 */
943 rx_queue->channel = &efx->channel[rx_queue->queue];
944 rx_queue->channel->used_flags |= EFX_USED_BY_RX;
945 rx_queue++;
946 }
947 }
948}
949
950static int efx_probe_nic(struct efx_nic *efx)
951{
952 int rc;
953
954 EFX_LOG(efx, "creating NIC\n");
955
956 /* Carry out hardware-type specific initialisation */
957 rc = falcon_probe_nic(efx);
958 if (rc)
959 return rc;
960
961 /* Determine the number of channels and RX queues by trying to hook
962 * in MSI-X interrupts. */
963 efx_probe_interrupts(efx);
964
965 /* Determine number of RX queues and TX queues */
966 efx_select_used(efx);
967
968 /* Initialise the interrupt moderation settings */
969 efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec);
970
971 return 0;
972}
973
974static void efx_remove_nic(struct efx_nic *efx)
975{
976 EFX_LOG(efx, "destroying NIC\n");
977
978 efx_remove_interrupts(efx);
979 falcon_remove_nic(efx);
980}
981
982/**************************************************************************
983 *
984 * NIC startup/shutdown
985 *
986 *************************************************************************/
987
988static int efx_probe_all(struct efx_nic *efx)
989{
990 struct efx_channel *channel;
991 int rc;
992
993 /* Create NIC */
994 rc = efx_probe_nic(efx);
995 if (rc) {
996 EFX_ERR(efx, "failed to create NIC\n");
997 goto fail1;
998 }
999
1000 /* Create port */
1001 rc = efx_probe_port(efx);
1002 if (rc) {
1003 EFX_ERR(efx, "failed to create port\n");
1004 goto fail2;
1005 }
1006
1007 /* Create channels */
1008 efx_for_each_channel(channel, efx) {
1009 rc = efx_probe_channel(channel);
1010 if (rc) {
1011 EFX_ERR(efx, "failed to create channel %d\n",
1012 channel->channel);
1013 goto fail3;
1014 }
1015 }
1016
1017 return 0;
1018
1019 fail3:
1020 efx_for_each_channel(channel, efx)
1021 efx_remove_channel(channel);
1022 efx_remove_port(efx);
1023 fail2:
1024 efx_remove_nic(efx);
1025 fail1:
1026 return rc;
1027}
1028
1029/* Called after previous invocation(s) of efx_stop_all, restarts the
1030 * port, kernel transmit queue, NAPI processing and hardware interrupts,
1031 * and ensures that the port is scheduled to be reconfigured.
1032 * This function is safe to call multiple times when the NIC is in any
1033 * state. */
1034static void efx_start_all(struct efx_nic *efx)
1035{
1036 struct efx_channel *channel;
1037
1038 EFX_ASSERT_RESET_SERIALISED(efx);
1039
1040 /* Check that it is appropriate to restart the interface. All
1041 * of these flags are safe to read under just the rtnl lock */
1042 if (efx->port_enabled)
1043 return;
1044 if ((efx->state != STATE_RUNNING) && (efx->state != STATE_INIT))
1045 return;
1046 if (NET_DEV_REGISTERED(efx) && !netif_running(efx->net_dev))
1047 return;
1048
1049 /* Mark the port as enabled so port reconfigurations can start, then
1050 * restart the transmit interface early so the watchdog timer stops */
1051 efx_start_port(efx);
1052 efx_wake_queue(efx);
1053
1054 efx_for_each_channel(channel, efx)
1055 efx_start_channel(channel);
1056
1057 falcon_enable_interrupts(efx);
1058
1059 /* Start hardware monitor if we're in RUNNING */
1060 if (efx->state == STATE_RUNNING)
1061 queue_delayed_work(efx->workqueue, &efx->monitor_work,
1062 efx_monitor_interval);
1063}
1064
1065/* Flush all delayed work. Should only be called when no more delayed work
1066 * will be scheduled. This doesn't flush pending online resets (efx_reset),
1067 * since we're holding the rtnl_lock at this point. */
1068static void efx_flush_all(struct efx_nic *efx)
1069{
1070 struct efx_rx_queue *rx_queue;
1071
1072 /* Make sure the hardware monitor is stopped */
1073 cancel_delayed_work_sync(&efx->monitor_work);
1074
1075 /* Ensure that all RX slow refills are complete. */
1076 efx_for_each_rx_queue(rx_queue, efx) {
1077 cancel_delayed_work_sync(&rx_queue->work);
1078 }
1079
1080 /* Stop scheduled port reconfigurations */
1081 cancel_work_sync(&efx->reconfigure_work);
1082
1083}
1084
1085/* Quiesce hardware and software without bringing the link down.
1086 * Safe to call multiple times, when the nic and interface is in any
1087 * state. The caller is guaranteed to subsequently be in a position
1088 * to modify any hardware and software state they see fit without
1089 * taking locks. */
1090static void efx_stop_all(struct efx_nic *efx)
1091{
1092 struct efx_channel *channel;
1093
1094 EFX_ASSERT_RESET_SERIALISED(efx);
1095
1096 /* port_enabled can be read safely under the rtnl lock */
1097 if (!efx->port_enabled)
1098 return;
1099
1100 /* Disable interrupts and wait for ISR to complete */
1101 falcon_disable_interrupts(efx);
1102 if (efx->legacy_irq)
1103 synchronize_irq(efx->legacy_irq);
1104 efx_for_each_channel_with_interrupt(channel, efx)
1105 if (channel->irq)
1106 synchronize_irq(channel->irq);
1107
1108 /* Stop all NAPI processing and synchronous rx refills */
1109 efx_for_each_channel(channel, efx)
1110 efx_stop_channel(channel);
1111
1112 /* Stop all asynchronous port reconfigurations. Since all
1113 * event processing has already been stopped, there is no
1114 * window to loose phy events */
1115 efx_stop_port(efx);
1116
1117 /* Flush reconfigure_work, refill_workqueue, monitor_work */
1118 efx_flush_all(efx);
1119
1120 /* Isolate the MAC from the TX and RX engines, so that queue
1121 * flushes will complete in a timely fashion. */
1122 falcon_deconfigure_mac_wrapper(efx);
1123 falcon_drain_tx_fifo(efx);
1124
1125 /* Stop the kernel transmit interface late, so the watchdog
1126 * timer isn't ticking over the flush */
1127 efx_stop_queue(efx);
1128 if (NET_DEV_REGISTERED(efx)) {
1129 netif_tx_lock_bh(efx->net_dev);
1130 netif_tx_unlock_bh(efx->net_dev);
1131 }
1132}
1133
1134static void efx_remove_all(struct efx_nic *efx)
1135{
1136 struct efx_channel *channel;
1137
1138 efx_for_each_channel(channel, efx)
1139 efx_remove_channel(channel);
1140 efx_remove_port(efx);
1141 efx_remove_nic(efx);
1142}
1143
1144/* A convinience function to safely flush all the queues */
1145int efx_flush_queues(struct efx_nic *efx)
1146{
1147 int rc;
1148
1149 EFX_ASSERT_RESET_SERIALISED(efx);
1150
1151 efx_stop_all(efx);
1152
1153 efx_fini_channels(efx);
1154 rc = efx_init_channels(efx);
1155 if (rc) {
1156 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1157 return rc;
1158 }
1159
1160 efx_start_all(efx);
1161
1162 return 0;
1163}
1164
1165/**************************************************************************
1166 *
1167 * Interrupt moderation
1168 *
1169 **************************************************************************/
1170
1171/* Set interrupt moderation parameters */
1172void efx_init_irq_moderation(struct efx_nic *efx, int tx_usecs, int rx_usecs)
1173{
1174 struct efx_tx_queue *tx_queue;
1175 struct efx_rx_queue *rx_queue;
1176
1177 EFX_ASSERT_RESET_SERIALISED(efx);
1178
1179 efx_for_each_tx_queue(tx_queue, efx)
1180 tx_queue->channel->irq_moderation = tx_usecs;
1181
1182 efx_for_each_rx_queue(rx_queue, efx)
1183 rx_queue->channel->irq_moderation = rx_usecs;
1184}
1185
1186/**************************************************************************
1187 *
1188 * Hardware monitor
1189 *
1190 **************************************************************************/
1191
1192/* Run periodically off the general workqueue. Serialised against
1193 * efx_reconfigure_port via the mac_lock */
1194static void efx_monitor(struct work_struct *data)
1195{
1196 struct efx_nic *efx = container_of(data, struct efx_nic,
1197 monitor_work.work);
1198 int rc = 0;
1199
1200 EFX_TRACE(efx, "hardware monitor executing on CPU %d\n",
1201 raw_smp_processor_id());
1202
1203
1204 /* If the mac_lock is already held then it is likely a port
1205 * reconfiguration is already in place, which will likely do
1206 * most of the work of check_hw() anyway. */
1207 if (!mutex_trylock(&efx->mac_lock)) {
1208 queue_delayed_work(efx->workqueue, &efx->monitor_work,
1209 efx_monitor_interval);
1210 return;
1211 }
1212
1213 if (efx->port_enabled)
1214 rc = falcon_check_xmac(efx);
1215 mutex_unlock(&efx->mac_lock);
1216
1217 if (rc) {
1218 if (monitor_reset) {
1219 EFX_ERR(efx, "hardware monitor detected a fault: "
1220 "triggering reset\n");
1221 efx_schedule_reset(efx, RESET_TYPE_MONITOR);
1222 } else {
1223 EFX_ERR(efx, "hardware monitor detected a fault, "
1224 "skipping reset\n");
1225 }
1226 }
1227
1228 queue_delayed_work(efx->workqueue, &efx->monitor_work,
1229 efx_monitor_interval);
1230}
1231
1232/**************************************************************************
1233 *
1234 * ioctls
1235 *
1236 *************************************************************************/
1237
1238/* Net device ioctl
1239 * Context: process, rtnl_lock() held.
1240 */
1241static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
1242{
1243 struct efx_nic *efx = net_dev->priv;
1244
1245 EFX_ASSERT_RESET_SERIALISED(efx);
1246
1247 return generic_mii_ioctl(&efx->mii, if_mii(ifr), cmd, NULL);
1248}
1249
1250/**************************************************************************
1251 *
1252 * NAPI interface
1253 *
1254 **************************************************************************/
1255
1256static int efx_init_napi(struct efx_nic *efx)
1257{
1258 struct efx_channel *channel;
1259 int rc;
1260
1261 efx_for_each_channel(channel, efx) {
1262 channel->napi_dev = efx->net_dev;
1263 rc = efx_lro_init(&channel->lro_mgr, efx);
1264 if (rc)
1265 goto err;
1266 }
1267 return 0;
1268 err:
1269 efx_fini_napi(efx);
1270 return rc;
1271}
1272
1273static void efx_fini_napi(struct efx_nic *efx)
1274{
1275 struct efx_channel *channel;
1276
1277 efx_for_each_channel(channel, efx) {
1278 efx_lro_fini(&channel->lro_mgr);
1279 channel->napi_dev = NULL;
1280 }
1281}
1282
1283/**************************************************************************
1284 *
1285 * Kernel netpoll interface
1286 *
1287 *************************************************************************/
1288
1289#ifdef CONFIG_NET_POLL_CONTROLLER
1290
1291/* Although in the common case interrupts will be disabled, this is not
1292 * guaranteed. However, all our work happens inside the NAPI callback,
1293 * so no locking is required.
1294 */
1295static void efx_netpoll(struct net_device *net_dev)
1296{
1297 struct efx_nic *efx = net_dev->priv;
1298 struct efx_channel *channel;
1299
1300 efx_for_each_channel_with_interrupt(channel, efx)
1301 efx_schedule_channel(channel);
1302}
1303
1304#endif
1305
1306/**************************************************************************
1307 *
1308 * Kernel net device interface
1309 *
1310 *************************************************************************/
1311
1312/* Context: process, rtnl_lock() held. */
1313static int efx_net_open(struct net_device *net_dev)
1314{
1315 struct efx_nic *efx = net_dev->priv;
1316 EFX_ASSERT_RESET_SERIALISED(efx);
1317
1318 EFX_LOG(efx, "opening device %s on CPU %d\n", net_dev->name,
1319 raw_smp_processor_id());
1320
1321 efx_start_all(efx);
1322 return 0;
1323}
1324
1325/* Context: process, rtnl_lock() held.
1326 * Note that the kernel will ignore our return code; this method
1327 * should really be a void.
1328 */
1329static int efx_net_stop(struct net_device *net_dev)
1330{
1331 struct efx_nic *efx = net_dev->priv;
1332 int rc;
1333
1334 EFX_LOG(efx, "closing %s on CPU %d\n", net_dev->name,
1335 raw_smp_processor_id());
1336
1337 /* Stop the device and flush all the channels */
1338 efx_stop_all(efx);
1339 efx_fini_channels(efx);
1340 rc = efx_init_channels(efx);
1341 if (rc)
1342 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1343
1344 return 0;
1345}
1346
1347/* Context: process, dev_base_lock held, non-blocking. */
1348static struct net_device_stats *efx_net_stats(struct net_device *net_dev)
1349{
1350 struct efx_nic *efx = net_dev->priv;
1351 struct efx_mac_stats *mac_stats = &efx->mac_stats;
1352 struct net_device_stats *stats = &net_dev->stats;
1353
1354 if (!spin_trylock(&efx->stats_lock))
1355 return stats;
1356 if (efx->state == STATE_RUNNING) {
1357 falcon_update_stats_xmac(efx);
1358 falcon_update_nic_stats(efx);
1359 }
1360 spin_unlock(&efx->stats_lock);
1361
1362 stats->rx_packets = mac_stats->rx_packets;
1363 stats->tx_packets = mac_stats->tx_packets;
1364 stats->rx_bytes = mac_stats->rx_bytes;
1365 stats->tx_bytes = mac_stats->tx_bytes;
1366 stats->multicast = mac_stats->rx_multicast;
1367 stats->collisions = mac_stats->tx_collision;
1368 stats->rx_length_errors = (mac_stats->rx_gtjumbo +
1369 mac_stats->rx_length_error);
1370 stats->rx_over_errors = efx->n_rx_nodesc_drop_cnt;
1371 stats->rx_crc_errors = mac_stats->rx_bad;
1372 stats->rx_frame_errors = mac_stats->rx_align_error;
1373 stats->rx_fifo_errors = mac_stats->rx_overflow;
1374 stats->rx_missed_errors = mac_stats->rx_missed;
1375 stats->tx_window_errors = mac_stats->tx_late_collision;
1376
1377 stats->rx_errors = (stats->rx_length_errors +
1378 stats->rx_over_errors +
1379 stats->rx_crc_errors +
1380 stats->rx_frame_errors +
1381 stats->rx_fifo_errors +
1382 stats->rx_missed_errors +
1383 mac_stats->rx_symbol_error);
1384 stats->tx_errors = (stats->tx_window_errors +
1385 mac_stats->tx_bad);
1386
1387 return stats;
1388}
1389
1390/* Context: netif_tx_lock held, BHs disabled. */
1391static void efx_watchdog(struct net_device *net_dev)
1392{
1393 struct efx_nic *efx = net_dev->priv;
1394
1395 EFX_ERR(efx, "TX stuck with stop_count=%d port_enabled=%d: %s\n",
1396 atomic_read(&efx->netif_stop_count), efx->port_enabled,
1397 monitor_reset ? "resetting channels" : "skipping reset");
1398
1399 if (monitor_reset)
1400 efx_schedule_reset(efx, RESET_TYPE_MONITOR);
1401}
1402
1403
1404/* Context: process, rtnl_lock() held. */
1405static int efx_change_mtu(struct net_device *net_dev, int new_mtu)
1406{
1407 struct efx_nic *efx = net_dev->priv;
1408 int rc = 0;
1409
1410 EFX_ASSERT_RESET_SERIALISED(efx);
1411
1412 if (new_mtu > EFX_MAX_MTU)
1413 return -EINVAL;
1414
1415 efx_stop_all(efx);
1416
1417 EFX_LOG(efx, "changing MTU to %d\n", new_mtu);
1418
1419 efx_fini_channels(efx);
1420 net_dev->mtu = new_mtu;
1421 rc = efx_init_channels(efx);
1422 if (rc)
1423 goto fail;
1424
1425 efx_start_all(efx);
1426 return rc;
1427
1428 fail:
1429 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1430 return rc;
1431}
1432
1433static int efx_set_mac_address(struct net_device *net_dev, void *data)
1434{
1435 struct efx_nic *efx = net_dev->priv;
1436 struct sockaddr *addr = data;
1437 char *new_addr = addr->sa_data;
1438
1439 EFX_ASSERT_RESET_SERIALISED(efx);
1440
1441 if (!is_valid_ether_addr(new_addr)) {
1442 DECLARE_MAC_BUF(mac);
1443 EFX_ERR(efx, "invalid ethernet MAC address requested: %s\n",
1444 print_mac(mac, new_addr));
1445 return -EINVAL;
1446 }
1447
1448 memcpy(net_dev->dev_addr, new_addr, net_dev->addr_len);
1449
1450 /* Reconfigure the MAC */
1451 efx_reconfigure_port(efx);
1452
1453 return 0;
1454}
1455
1456/* Context: netif_tx_lock held, BHs disabled. */
1457static void efx_set_multicast_list(struct net_device *net_dev)
1458{
1459 struct efx_nic *efx = net_dev->priv;
1460 struct dev_mc_list *mc_list = net_dev->mc_list;
1461 union efx_multicast_hash *mc_hash = &efx->multicast_hash;
1462 int promiscuous;
1463 u32 crc;
1464 int bit;
1465 int i;
1466
1467 /* Set per-MAC promiscuity flag and reconfigure MAC if necessary */
1468 promiscuous = (net_dev->flags & IFF_PROMISC) ? 1 : 0;
1469 if (efx->promiscuous != promiscuous) {
1470 efx->promiscuous = promiscuous;
1471 /* Close the window between efx_stop_port() and efx_flush_all()
1472 * by only queuing work when the port is enabled. */
1473 if (efx->port_enabled)
1474 queue_work(efx->workqueue, &efx->reconfigure_work);
1475 }
1476
1477 /* Build multicast hash table */
1478 if (promiscuous || (net_dev->flags & IFF_ALLMULTI)) {
1479 memset(mc_hash, 0xff, sizeof(*mc_hash));
1480 } else {
1481 memset(mc_hash, 0x00, sizeof(*mc_hash));
1482 for (i = 0; i < net_dev->mc_count; i++) {
1483 crc = ether_crc_le(ETH_ALEN, mc_list->dmi_addr);
1484 bit = crc & (EFX_MCAST_HASH_ENTRIES - 1);
1485 set_bit_le(bit, mc_hash->byte);
1486 mc_list = mc_list->next;
1487 }
1488 }
1489
1490 /* Create and activate new global multicast hash table */
1491 falcon_set_multicast_hash(efx);
1492}
1493
1494static int efx_netdev_event(struct notifier_block *this,
1495 unsigned long event, void *ptr)
1496{
1497 struct net_device *net_dev = (struct net_device *)ptr;
1498
1499 if (net_dev->open == efx_net_open && event == NETDEV_CHANGENAME) {
1500 struct efx_nic *efx = net_dev->priv;
1501
1502 strcpy(efx->name, net_dev->name);
1503 }
1504
1505 return NOTIFY_DONE;
1506}
1507
1508static struct notifier_block efx_netdev_notifier = {
1509 .notifier_call = efx_netdev_event,
1510};
1511
1512static int efx_register_netdev(struct efx_nic *efx)
1513{
1514 struct net_device *net_dev = efx->net_dev;
1515 int rc;
1516
1517 net_dev->watchdog_timeo = 5 * HZ;
1518 net_dev->irq = efx->pci_dev->irq;
1519 net_dev->open = efx_net_open;
1520 net_dev->stop = efx_net_stop;
1521 net_dev->get_stats = efx_net_stats;
1522 net_dev->tx_timeout = &efx_watchdog;
1523 net_dev->hard_start_xmit = efx_hard_start_xmit;
1524 net_dev->do_ioctl = efx_ioctl;
1525 net_dev->change_mtu = efx_change_mtu;
1526 net_dev->set_mac_address = efx_set_mac_address;
1527 net_dev->set_multicast_list = efx_set_multicast_list;
1528#ifdef CONFIG_NET_POLL_CONTROLLER
1529 net_dev->poll_controller = efx_netpoll;
1530#endif
1531 SET_NETDEV_DEV(net_dev, &efx->pci_dev->dev);
1532 SET_ETHTOOL_OPS(net_dev, &efx_ethtool_ops);
1533
1534 /* Always start with carrier off; PHY events will detect the link */
1535 netif_carrier_off(efx->net_dev);
1536
1537 /* Clear MAC statistics */
1538 falcon_update_stats_xmac(efx);
1539 memset(&efx->mac_stats, 0, sizeof(efx->mac_stats));
1540
1541 rc = register_netdev(net_dev);
1542 if (rc) {
1543 EFX_ERR(efx, "could not register net dev\n");
1544 return rc;
1545 }
1546 strcpy(efx->name, net_dev->name);
1547
1548 return 0;
1549}
1550
1551static void efx_unregister_netdev(struct efx_nic *efx)
1552{
1553 struct efx_tx_queue *tx_queue;
1554
1555 if (!efx->net_dev)
1556 return;
1557
1558 BUG_ON(efx->net_dev->priv != efx);
1559
1560 /* Free up any skbs still remaining. This has to happen before
1561 * we try to unregister the netdev as running their destructors
1562 * may be needed to get the device ref. count to 0. */
1563 efx_for_each_tx_queue(tx_queue, efx)
1564 efx_release_tx_buffers(tx_queue);
1565
1566 if (NET_DEV_REGISTERED(efx)) {
1567 strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name));
1568 unregister_netdev(efx->net_dev);
1569 }
1570}
1571
1572/**************************************************************************
1573 *
1574 * Device reset and suspend
1575 *
1576 **************************************************************************/
1577
1578/* The final hardware and software finalisation before reset. */
1579static int efx_reset_down(struct efx_nic *efx, struct ethtool_cmd *ecmd)
1580{
1581 int rc;
1582
1583 EFX_ASSERT_RESET_SERIALISED(efx);
1584
1585 rc = falcon_xmac_get_settings(efx, ecmd);
1586 if (rc) {
1587 EFX_ERR(efx, "could not back up PHY settings\n");
1588 goto fail;
1589 }
1590
1591 efx_fini_channels(efx);
1592 return 0;
1593
1594 fail:
1595 return rc;
1596}
1597
1598/* The first part of software initialisation after a hardware reset
1599 * This function does not handle serialisation with the kernel, it
1600 * assumes the caller has done this */
1601static int efx_reset_up(struct efx_nic *efx, struct ethtool_cmd *ecmd)
1602{
1603 int rc;
1604
1605 rc = efx_init_channels(efx);
1606 if (rc)
1607 goto fail1;
1608
1609 /* Restore MAC and PHY settings. */
1610 rc = falcon_xmac_set_settings(efx, ecmd);
1611 if (rc) {
1612 EFX_ERR(efx, "could not restore PHY settings\n");
1613 goto fail2;
1614 }
1615
1616 return 0;
1617
1618 fail2:
1619 efx_fini_channels(efx);
1620 fail1:
1621 return rc;
1622}
1623
1624/* Reset the NIC as transparently as possible. Do not reset the PHY
1625 * Note that the reset may fail, in which case the card will be left
1626 * in a most-probably-unusable state.
1627 *
1628 * This function will sleep. You cannot reset from within an atomic
1629 * state; use efx_schedule_reset() instead.
1630 *
1631 * Grabs the rtnl_lock.
1632 */
1633static int efx_reset(struct efx_nic *efx)
1634{
1635 struct ethtool_cmd ecmd;
1636 enum reset_type method = efx->reset_pending;
1637 int rc;
1638
1639 /* Serialise with kernel interfaces */
1640 rtnl_lock();
1641
1642 /* If we're not RUNNING then don't reset. Leave the reset_pending
1643 * flag set so that efx_pci_probe_main will be retried */
1644 if (efx->state != STATE_RUNNING) {
1645 EFX_INFO(efx, "scheduled reset quenched. NIC not RUNNING\n");
1646 goto unlock_rtnl;
1647 }
1648
1649 efx->state = STATE_RESETTING;
1650 EFX_INFO(efx, "resetting (%d)\n", method);
1651
1652 /* The net_dev->get_stats handler is quite slow, and will fail
1653 * if a fetch is pending over reset. Serialise against it. */
1654 spin_lock(&efx->stats_lock);
1655 spin_unlock(&efx->stats_lock);
1656
1657 efx_stop_all(efx);
1658 mutex_lock(&efx->mac_lock);
1659
1660 rc = efx_reset_down(efx, &ecmd);
1661 if (rc)
1662 goto fail1;
1663
1664 rc = falcon_reset_hw(efx, method);
1665 if (rc) {
1666 EFX_ERR(efx, "failed to reset hardware\n");
1667 goto fail2;
1668 }
1669
1670 /* Allow resets to be rescheduled. */
1671 efx->reset_pending = RESET_TYPE_NONE;
1672
1673 /* Reinitialise bus-mastering, which may have been turned off before
1674 * the reset was scheduled. This is still appropriate, even in the
1675 * RESET_TYPE_DISABLE since this driver generally assumes the hardware
1676 * can respond to requests. */
1677 pci_set_master(efx->pci_dev);
1678
1679 /* Reinitialise device. This is appropriate in the RESET_TYPE_DISABLE
1680 * case so the driver can talk to external SRAM */
1681 rc = falcon_init_nic(efx);
1682 if (rc) {
1683 EFX_ERR(efx, "failed to initialise NIC\n");
1684 goto fail3;
1685 }
1686
1687 /* Leave device stopped if necessary */
1688 if (method == RESET_TYPE_DISABLE) {
1689 /* Reinitialise the device anyway so the driver unload sequence
1690 * can talk to the external SRAM */
1691 (void) falcon_init_nic(efx);
1692 rc = -EIO;
1693 goto fail4;
1694 }
1695
1696 rc = efx_reset_up(efx, &ecmd);
1697 if (rc)
1698 goto fail5;
1699
1700 mutex_unlock(&efx->mac_lock);
1701 EFX_LOG(efx, "reset complete\n");
1702
1703 efx->state = STATE_RUNNING;
1704 efx_start_all(efx);
1705
1706 unlock_rtnl:
1707 rtnl_unlock();
1708 return 0;
1709
1710 fail5:
1711 fail4:
1712 fail3:
1713 fail2:
1714 fail1:
1715 EFX_ERR(efx, "has been disabled\n");
1716 efx->state = STATE_DISABLED;
1717
1718 mutex_unlock(&efx->mac_lock);
1719 rtnl_unlock();
1720 efx_unregister_netdev(efx);
1721 efx_fini_port(efx);
1722 return rc;
1723}
1724
1725/* The worker thread exists so that code that cannot sleep can
1726 * schedule a reset for later.
1727 */
1728static void efx_reset_work(struct work_struct *data)
1729{
1730 struct efx_nic *nic = container_of(data, struct efx_nic, reset_work);
1731
1732 efx_reset(nic);
1733}
1734
1735void efx_schedule_reset(struct efx_nic *efx, enum reset_type type)
1736{
1737 enum reset_type method;
1738
1739 if (efx->reset_pending != RESET_TYPE_NONE) {
1740 EFX_INFO(efx, "quenching already scheduled reset\n");
1741 return;
1742 }
1743
1744 switch (type) {
1745 case RESET_TYPE_INVISIBLE:
1746 case RESET_TYPE_ALL:
1747 case RESET_TYPE_WORLD:
1748 case RESET_TYPE_DISABLE:
1749 method = type;
1750 break;
1751 case RESET_TYPE_RX_RECOVERY:
1752 case RESET_TYPE_RX_DESC_FETCH:
1753 case RESET_TYPE_TX_DESC_FETCH:
1754 case RESET_TYPE_TX_SKIP:
1755 method = RESET_TYPE_INVISIBLE;
1756 break;
1757 default:
1758 method = RESET_TYPE_ALL;
1759 break;
1760 }
1761
1762 if (method != type)
1763 EFX_LOG(efx, "scheduling reset (%d:%d)\n", type, method);
1764 else
1765 EFX_LOG(efx, "scheduling reset (%d)\n", method);
1766
1767 efx->reset_pending = method;
1768
1769 queue_work(efx->workqueue, &efx->reset_work);
1770}
1771
1772/**************************************************************************
1773 *
1774 * List of NICs we support
1775 *
1776 **************************************************************************/
1777
1778/* PCI device ID table */
1779static struct pci_device_id efx_pci_table[] __devinitdata = {
1780 {PCI_DEVICE(EFX_VENDID_SFC, FALCON_A_P_DEVID),
1781 .driver_data = (unsigned long) &falcon_a_nic_type},
1782 {PCI_DEVICE(EFX_VENDID_SFC, FALCON_B_P_DEVID),
1783 .driver_data = (unsigned long) &falcon_b_nic_type},
1784 {0} /* end of list */
1785};
1786
1787/**************************************************************************
1788 *
1789 * Dummy PHY/MAC/Board operations
1790 *
1791 * Can be used where the MAC does not implement this operation
1792 * Needed so all function pointers are valid and do not have to be tested
1793 * before use
1794 *
1795 **************************************************************************/
1796int efx_port_dummy_op_int(struct efx_nic *efx)
1797{
1798 return 0;
1799}
1800void efx_port_dummy_op_void(struct efx_nic *efx) {}
1801void efx_port_dummy_op_blink(struct efx_nic *efx, int blink) {}
1802
1803static struct efx_phy_operations efx_dummy_phy_operations = {
1804 .init = efx_port_dummy_op_int,
1805 .reconfigure = efx_port_dummy_op_void,
1806 .check_hw = efx_port_dummy_op_int,
1807 .fini = efx_port_dummy_op_void,
1808 .clear_interrupt = efx_port_dummy_op_void,
1809 .reset_xaui = efx_port_dummy_op_void,
1810};
1811
1812/* Dummy board operations */
1813static int efx_nic_dummy_op_int(struct efx_nic *nic)
1814{
1815 return 0;
1816}
1817
1818static struct efx_board efx_dummy_board_info = {
1819 .init = efx_nic_dummy_op_int,
1820 .init_leds = efx_port_dummy_op_int,
1821 .set_fault_led = efx_port_dummy_op_blink,
1822};
1823
1824/**************************************************************************
1825 *
1826 * Data housekeeping
1827 *
1828 **************************************************************************/
1829
1830/* This zeroes out and then fills in the invariants in a struct
1831 * efx_nic (including all sub-structures).
1832 */
1833static int efx_init_struct(struct efx_nic *efx, struct efx_nic_type *type,
1834 struct pci_dev *pci_dev, struct net_device *net_dev)
1835{
1836 struct efx_channel *channel;
1837 struct efx_tx_queue *tx_queue;
1838 struct efx_rx_queue *rx_queue;
1839 int i, rc;
1840
1841 /* Initialise common structures */
1842 memset(efx, 0, sizeof(*efx));
1843 spin_lock_init(&efx->biu_lock);
1844 spin_lock_init(&efx->phy_lock);
1845 INIT_WORK(&efx->reset_work, efx_reset_work);
1846 INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor);
1847 efx->pci_dev = pci_dev;
1848 efx->state = STATE_INIT;
1849 efx->reset_pending = RESET_TYPE_NONE;
1850 strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name));
1851 efx->board_info = efx_dummy_board_info;
1852
1853 efx->net_dev = net_dev;
1854 efx->rx_checksum_enabled = 1;
1855 spin_lock_init(&efx->netif_stop_lock);
1856 spin_lock_init(&efx->stats_lock);
1857 mutex_init(&efx->mac_lock);
1858 efx->phy_op = &efx_dummy_phy_operations;
1859 efx->mii.dev = net_dev;
1860 INIT_WORK(&efx->reconfigure_work, efx_reconfigure_work);
1861 atomic_set(&efx->netif_stop_count, 1);
1862
1863 for (i = 0; i < EFX_MAX_CHANNELS; i++) {
1864 channel = &efx->channel[i];
1865 channel->efx = efx;
1866 channel->channel = i;
1867 channel->evqnum = i;
1868 channel->work_pending = 0;
1869 }
1870 for (i = 0; i < EFX_MAX_TX_QUEUES; i++) {
1871 tx_queue = &efx->tx_queue[i];
1872 tx_queue->efx = efx;
1873 tx_queue->queue = i;
1874 tx_queue->buffer = NULL;
1875 tx_queue->channel = &efx->channel[0]; /* for safety */
1876 }
1877 for (i = 0; i < EFX_MAX_RX_QUEUES; i++) {
1878 rx_queue = &efx->rx_queue[i];
1879 rx_queue->efx = efx;
1880 rx_queue->queue = i;
1881 rx_queue->channel = &efx->channel[0]; /* for safety */
1882 rx_queue->buffer = NULL;
1883 spin_lock_init(&rx_queue->add_lock);
1884 INIT_DELAYED_WORK(&rx_queue->work, efx_rx_work);
1885 }
1886
1887 efx->type = type;
1888
1889 /* Sanity-check NIC type */
1890 EFX_BUG_ON_PARANOID(efx->type->txd_ring_mask &
1891 (efx->type->txd_ring_mask + 1));
1892 EFX_BUG_ON_PARANOID(efx->type->rxd_ring_mask &
1893 (efx->type->rxd_ring_mask + 1));
1894 EFX_BUG_ON_PARANOID(efx->type->evq_size &
1895 (efx->type->evq_size - 1));
1896 /* As close as we can get to guaranteeing that we don't overflow */
1897 EFX_BUG_ON_PARANOID(efx->type->evq_size <
1898 (efx->type->txd_ring_mask + 1 +
1899 efx->type->rxd_ring_mask + 1));
1900 EFX_BUG_ON_PARANOID(efx->type->phys_addr_channels > EFX_MAX_CHANNELS);
1901
1902 /* Higher numbered interrupt modes are less capable! */
1903 efx->interrupt_mode = max(efx->type->max_interrupt_mode,
1904 interrupt_mode);
1905
1906 efx->workqueue = create_singlethread_workqueue("sfc_work");
1907 if (!efx->workqueue) {
1908 rc = -ENOMEM;
1909 goto fail1;
1910 }
1911
1912 return 0;
1913
1914 fail1:
1915 return rc;
1916}
1917
1918static void efx_fini_struct(struct efx_nic *efx)
1919{
1920 if (efx->workqueue) {
1921 destroy_workqueue(efx->workqueue);
1922 efx->workqueue = NULL;
1923 }
1924}
1925
1926/**************************************************************************
1927 *
1928 * PCI interface
1929 *
1930 **************************************************************************/
1931
1932/* Main body of final NIC shutdown code
1933 * This is called only at module unload (or hotplug removal).
1934 */
1935static void efx_pci_remove_main(struct efx_nic *efx)
1936{
1937 EFX_ASSERT_RESET_SERIALISED(efx);
1938
1939 /* Skip everything if we never obtained a valid membase */
1940 if (!efx->membase)
1941 return;
1942
1943 efx_fini_channels(efx);
1944 efx_fini_port(efx);
1945
1946 /* Shutdown the board, then the NIC and board state */
1947 falcon_fini_interrupt(efx);
1948
1949 efx_fini_napi(efx);
1950 efx_remove_all(efx);
1951}
1952
1953/* Final NIC shutdown
1954 * This is called only at module unload (or hotplug removal).
1955 */
1956static void efx_pci_remove(struct pci_dev *pci_dev)
1957{
1958 struct efx_nic *efx;
1959
1960 efx = pci_get_drvdata(pci_dev);
1961 if (!efx)
1962 return;
1963
1964 /* Mark the NIC as fini, then stop the interface */
1965 rtnl_lock();
1966 efx->state = STATE_FINI;
1967 dev_close(efx->net_dev);
1968
1969 /* Allow any queued efx_resets() to complete */
1970 rtnl_unlock();
1971
1972 if (efx->membase == NULL)
1973 goto out;
1974
1975 efx_unregister_netdev(efx);
1976
1977 /* Wait for any scheduled resets to complete. No more will be
1978 * scheduled from this point because efx_stop_all() has been
1979 * called, we are no longer registered with driverlink, and
1980 * the net_device's have been removed. */
1981 flush_workqueue(efx->workqueue);
1982
1983 efx_pci_remove_main(efx);
1984
1985out:
1986 efx_fini_io(efx);
1987 EFX_LOG(efx, "shutdown successful\n");
1988
1989 pci_set_drvdata(pci_dev, NULL);
1990 efx_fini_struct(efx);
1991 free_netdev(efx->net_dev);
1992};
1993
1994/* Main body of NIC initialisation
1995 * This is called at module load (or hotplug insertion, theoretically).
1996 */
1997static int efx_pci_probe_main(struct efx_nic *efx)
1998{
1999 int rc;
2000
2001 /* Do start-of-day initialisation */
2002 rc = efx_probe_all(efx);
2003 if (rc)
2004 goto fail1;
2005
2006 rc = efx_init_napi(efx);
2007 if (rc)
2008 goto fail2;
2009
2010 /* Initialise the board */
2011 rc = efx->board_info.init(efx);
2012 if (rc) {
2013 EFX_ERR(efx, "failed to initialise board\n");
2014 goto fail3;
2015 }
2016
2017 rc = falcon_init_nic(efx);
2018 if (rc) {
2019 EFX_ERR(efx, "failed to initialise NIC\n");
2020 goto fail4;
2021 }
2022
2023 rc = efx_init_port(efx);
2024 if (rc) {
2025 EFX_ERR(efx, "failed to initialise port\n");
2026 goto fail5;
2027 }
2028
2029 rc = efx_init_channels(efx);
2030 if (rc)
2031 goto fail6;
2032
2033 rc = falcon_init_interrupt(efx);
2034 if (rc)
2035 goto fail7;
2036
2037 return 0;
2038
2039 fail7:
2040 efx_fini_channels(efx);
2041 fail6:
2042 efx_fini_port(efx);
2043 fail5:
2044 fail4:
2045 fail3:
2046 efx_fini_napi(efx);
2047 fail2:
2048 efx_remove_all(efx);
2049 fail1:
2050 return rc;
2051}
2052
2053/* NIC initialisation
2054 *
2055 * This is called at module load (or hotplug insertion,
2056 * theoretically). It sets up PCI mappings, tests and resets the NIC,
2057 * sets up and registers the network devices with the kernel and hooks
2058 * the interrupt service routine. It does not prepare the device for
2059 * transmission; this is left to the first time one of the network
2060 * interfaces is brought up (i.e. efx_net_open).
2061 */
2062static int __devinit efx_pci_probe(struct pci_dev *pci_dev,
2063 const struct pci_device_id *entry)
2064{
2065 struct efx_nic_type *type = (struct efx_nic_type *) entry->driver_data;
2066 struct net_device *net_dev;
2067 struct efx_nic *efx;
2068 int i, rc;
2069
2070 /* Allocate and initialise a struct net_device and struct efx_nic */
2071 net_dev = alloc_etherdev(sizeof(*efx));
2072 if (!net_dev)
2073 return -ENOMEM;
2074 net_dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA;
2075 if (lro)
2076 net_dev->features |= NETIF_F_LRO;
2077 efx = net_dev->priv;
2078 pci_set_drvdata(pci_dev, efx);
2079 rc = efx_init_struct(efx, type, pci_dev, net_dev);
2080 if (rc)
2081 goto fail1;
2082
2083 EFX_INFO(efx, "Solarflare Communications NIC detected\n");
2084
2085 /* Set up basic I/O (BAR mappings etc) */
2086 rc = efx_init_io(efx);
2087 if (rc)
2088 goto fail2;
2089
2090 /* No serialisation is required with the reset path because
2091 * we're in STATE_INIT. */
2092 for (i = 0; i < 5; i++) {
2093 rc = efx_pci_probe_main(efx);
2094 if (rc == 0)
2095 break;
2096
2097 /* Serialise against efx_reset(). No more resets will be
2098 * scheduled since efx_stop_all() has been called, and we
2099 * have not and never have been registered with either
2100 * the rtnetlink or driverlink layers. */
2101 cancel_work_sync(&efx->reset_work);
2102
2103 /* Retry if a recoverably reset event has been scheduled */
2104 if ((efx->reset_pending != RESET_TYPE_INVISIBLE) &&
2105 (efx->reset_pending != RESET_TYPE_ALL))
2106 goto fail3;
2107
2108 efx->reset_pending = RESET_TYPE_NONE;
2109 }
2110
2111 if (rc) {
2112 EFX_ERR(efx, "Could not reset NIC\n");
2113 goto fail4;
2114 }
2115
2116 /* Switch to the running state before we expose the device to
2117 * the OS. This is to ensure that the initial gathering of
2118 * MAC stats succeeds. */
2119 rtnl_lock();
2120 efx->state = STATE_RUNNING;
2121 rtnl_unlock();
2122
2123 rc = efx_register_netdev(efx);
2124 if (rc)
2125 goto fail5;
2126
2127 EFX_LOG(efx, "initialisation successful\n");
2128
2129 return 0;
2130
2131 fail5:
2132 efx_pci_remove_main(efx);
2133 fail4:
2134 fail3:
2135 efx_fini_io(efx);
2136 fail2:
2137 efx_fini_struct(efx);
2138 fail1:
2139 EFX_LOG(efx, "initialisation failed. rc=%d\n", rc);
2140 free_netdev(net_dev);
2141 return rc;
2142}
2143
2144static struct pci_driver efx_pci_driver = {
2145 .name = EFX_DRIVER_NAME,
2146 .id_table = efx_pci_table,
2147 .probe = efx_pci_probe,
2148 .remove = efx_pci_remove,
2149};
2150
2151/**************************************************************************
2152 *
2153 * Kernel module interface
2154 *
2155 *************************************************************************/
2156
2157module_param(interrupt_mode, uint, 0444);
2158MODULE_PARM_DESC(interrupt_mode,
2159 "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)");
2160
2161static int __init efx_init_module(void)
2162{
2163 int rc;
2164
2165 printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n");
2166
2167 rc = register_netdevice_notifier(&efx_netdev_notifier);
2168 if (rc)
2169 goto err_notifier;
2170
2171 refill_workqueue = create_workqueue("sfc_refill");
2172 if (!refill_workqueue) {
2173 rc = -ENOMEM;
2174 goto err_refill;
2175 }
2176
2177 rc = pci_register_driver(&efx_pci_driver);
2178 if (rc < 0)
2179 goto err_pci;
2180
2181 return 0;
2182
2183 err_pci:
2184 destroy_workqueue(refill_workqueue);
2185 err_refill:
2186 unregister_netdevice_notifier(&efx_netdev_notifier);
2187 err_notifier:
2188 return rc;
2189}
2190
2191static void __exit efx_exit_module(void)
2192{
2193 printk(KERN_INFO "Solarflare NET driver unloading\n");
2194
2195 pci_unregister_driver(&efx_pci_driver);
2196 destroy_workqueue(refill_workqueue);
2197 unregister_netdevice_notifier(&efx_netdev_notifier);
2198
2199}
2200
2201module_init(efx_init_module);
2202module_exit(efx_exit_module);
2203
2204MODULE_AUTHOR("Michael Brown <mbrown@fensystems.co.uk> and "
2205 "Solarflare Communications");
2206MODULE_DESCRIPTION("Solarflare Communications network driver");
2207MODULE_LICENSE("GPL");
2208MODULE_DEVICE_TABLE(pci, efx_pci_table);
Linux 6.x block layer and io_uring tree(s)