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[linux-2.6-block.git] / drivers / net / r8169.c
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1da177e4
LT		 1/*
2=========================================================================
3 r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver for Linux kernel 2.4.x.
4 --------------------------------------------------------------------
5
6 History:
7 Feb 4 2002 - created initially by ShuChen <shuchen@realtek.com.tw>.
8 May 20 2002 - Add link status force-mode and TBI mode support.
5b0384f4 9 2004 - Massive updates. See kernel SCM system for details.
1da177e4
LT		 10=========================================================================
11 1. [DEPRECATED: use ethtool instead] The media can be forced in 5 modes.
12 Command: 'insmod r8169 media = SET_MEDIA'
13 Ex: 'insmod r8169 media = 0x04' will force PHY to operate in 100Mpbs Half-duplex.
5b0384f4 14
1da177e4
LT		 15 SET_MEDIA can be:
16 _10_Half = 0x01
17 _10_Full = 0x02
18 _100_Half = 0x04
19 _100_Full = 0x08
20 _1000_Full = 0x10
5b0384f4 21
1da177e4
LT		 22 2. Support TBI mode.
23=========================================================================
24VERSION 1.1 <2002/10/4>
25
26 The bit4:0 of MII register 4 is called "selector field", and have to be
27 00001b to indicate support of IEEE std 802.3 during NWay process of
5b0384f4 28 exchanging Link Code Word (FLP).
1da177e4
LT		 29
30VERSION 1.2 <2002/11/30>
31
32 - Large style cleanup
33 - Use ether_crc in stock kernel (linux/crc32.h)
34 - Copy mc_filter setup code from 8139cp
35 (includes an optimization, and avoids set_bit use)
36
37VERSION 1.6LK <2004/04/14>
38
39 - Merge of Realtek's version 1.6
40 - Conversion to DMA API
41 - Suspend/resume
42 - Endianness
43 - Misc Rx/Tx bugs
44
45VERSION 2.2LK <2005/01/25>
46
47 - RX csum, TX csum/SG, TSO
48 - VLAN
49 - baby (< 7200) Jumbo frames support
50 - Merge of Realtek's version 2.2 (new phy)
51 */
52
53#include <linux/module.h>
54#include <linux/moduleparam.h>
55#include <linux/pci.h>
56#include <linux/netdevice.h>
57#include <linux/etherdevice.h>
58#include <linux/delay.h>
59#include <linux/ethtool.h>
60#include <linux/mii.h>
61#include <linux/if_vlan.h>
62#include <linux/crc32.h>
63#include <linux/in.h>
64#include <linux/ip.h>
65#include <linux/tcp.h>
66#include <linux/init.h>
67#include <linux/dma-mapping.h>
68
69#include <asm/io.h>
70#include <asm/irq.h>
71
f7ccf420
SH		 72#ifdef CONFIG_R8169_NAPI
73#define NAPI_SUFFIX "-NAPI"
74#else
75#define NAPI_SUFFIX ""
76#endif
77
78#define RTL8169_VERSION "2.2LK" NAPI_SUFFIX
1da177e4
LT		 79#define MODULENAME "r8169"
80#define PFX MODULENAME ": "
81
82#ifdef RTL8169_DEBUG
83#define assert(expr) \
5b0384f4
FR		 84 if (!(expr)) { \
85 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
86 #expr,__FILE__,__FUNCTION__,__LINE__); \
87 }
1da177e4
LT		 88#define dprintk(fmt, args...) do { printk(PFX fmt, ## args); } while (0)
89#else
90#define assert(expr) do {} while (0)
91#define dprintk(fmt, args...) do {} while (0)
92#endif /* RTL8169_DEBUG */
93
b57b7e5a 94#define R8169_MSG_DEFAULT \
f0e837d9 95 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 96
1da177e4
LT		 97#define TX_BUFFS_AVAIL(tp) \
98 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
99
100#ifdef CONFIG_R8169_NAPI
101#define rtl8169_rx_skb netif_receive_skb
0b50f81d 102#define rtl8169_rx_hwaccel_skb vlan_hwaccel_receive_skb
1da177e4
LT		 103#define rtl8169_rx_quota(count, quota) min(count, quota)
104#else
105#define rtl8169_rx_skb netif_rx
0b50f81d 106#define rtl8169_rx_hwaccel_skb vlan_hwaccel_rx
1da177e4
LT		 107#define rtl8169_rx_quota(count, quota) count
108#endif
109
110/* media options */
111#define MAX_UNITS 8
112static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
113static int num_media = 0;
114
115/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
f71e1309 116static const int max_interrupt_work = 20;
1da177e4
LT		 117
118/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
119 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 120static const int multicast_filter_limit = 32;
1da177e4
LT		 121
122/* MAC address length */
123#define MAC_ADDR_LEN 6
124
125#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
126#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
127#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
128#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
129#define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
130#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
131#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
132
133#define R8169_REGS_SIZE 256
134#define R8169_NAPI_WEIGHT 64
135#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
136#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
137#define RX_BUF_SIZE 1536 /* Rx Buffer size */
138#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
139#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
140
141#define RTL8169_TX_TIMEOUT (6*HZ)
142#define RTL8169_PHY_TIMEOUT (10*HZ)
143
144/* write/read MMIO register */
145#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
146#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
147#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
148#define RTL_R8(reg) readb (ioaddr + (reg))
149#define RTL_R16(reg) readw (ioaddr + (reg))
150#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
151
152enum mac_version {
bcf0bf90
FR		 153 RTL_GIGA_MAC_VER_01 = 0x00,
154 RTL_GIGA_MAC_VER_02 = 0x01,
155 RTL_GIGA_MAC_VER_03 = 0x02,
156 RTL_GIGA_MAC_VER_04 = 0x03,
157 RTL_GIGA_MAC_VER_05 = 0x04,
158 RTL_GIGA_MAC_VER_11 = 0x0b,
159 RTL_GIGA_MAC_VER_12 = 0x0c,
160 RTL_GIGA_MAC_VER_13 = 0x0d,
161 RTL_GIGA_MAC_VER_14 = 0x0e,
162 RTL_GIGA_MAC_VER_15 = 0x0f
1da177e4
LT		 163};
164
165enum phy_version {
166 RTL_GIGA_PHY_VER_C = 0x03, /* PHY Reg 0x03 bit0-3 == 0x0000 */
167 RTL_GIGA_PHY_VER_D = 0x04, /* PHY Reg 0x03 bit0-3 == 0x0000 */
168 RTL_GIGA_PHY_VER_E = 0x05, /* PHY Reg 0x03 bit0-3 == 0x0000 */
169 RTL_GIGA_PHY_VER_F = 0x06, /* PHY Reg 0x03 bit0-3 == 0x0001 */
170 RTL_GIGA_PHY_VER_G = 0x07, /* PHY Reg 0x03 bit0-3 == 0x0002 */
171 RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */
172};
173
1da177e4
LT		 174#define _R(NAME,MAC,MASK) \
175 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
176
3c6bee1d 177static const struct {
1da177e4
LT		 178 const char *name;
179 u8 mac_version;
180 u32 RxConfigMask; /* Clears the bits supported by this chip */
181} rtl_chip_info[] = {
bcf0bf90
FR		 182 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880),
183 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_02, 0xff7e1880),
184 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880),
185 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880),
186 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880),
187 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
188 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
189 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
190 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
191 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880) // PCI-E 8139
1da177e4
LT		 192};
193#undef _R
194
bcf0bf90
FR		 195enum cfg_version {
196 RTL_CFG_0 = 0x00,
197 RTL_CFG_1,
198 RTL_CFG_2
199};
200
201static const struct {
202 unsigned int region;
203 unsigned int align;
204} rtl_cfg_info[] = {
205 [RTL_CFG_0] = { 1, NET_IP_ALIGN },
206 [RTL_CFG_1] = { 2, NET_IP_ALIGN },
207 [RTL_CFG_2] = { 2, 8 }
208};
209
1da177e4 210static struct pci_device_id rtl8169_pci_tbl[] = {
bcf0bf90 211 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 212 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 213 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 214 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_2 },
215 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
216 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
73f5e28b 217 { PCI_DEVICE(0x1259, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 218 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
219 { PCI_VENDOR_ID_LINKSYS, 0x1032,
220 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
1da177e4
LT		 221 {0,},
222};
223
224MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
225
226static int rx_copybreak = 200;
227static int use_dac;
b57b7e5a
SH		 228static struct {
229 u32 msg_enable;
230} debug = { -1 };
1da177e4
LT		 231
232enum RTL8169_registers {
233 MAC0 = 0, /* Ethernet hardware address. */
234 MAR0 = 8, /* Multicast filter. */
d4a3a0fc
SH		 235 CounterAddrLow = 0x10,
236 CounterAddrHigh = 0x14,
1da177e4
LT		 237 TxDescStartAddrLow = 0x20,
238 TxDescStartAddrHigh = 0x24,
239 TxHDescStartAddrLow = 0x28,
240 TxHDescStartAddrHigh = 0x2c,
241 FLASH = 0x30,
242 ERSR = 0x36,
243 ChipCmd = 0x37,
244 TxPoll = 0x38,
245 IntrMask = 0x3C,
246 IntrStatus = 0x3E,
247 TxConfig = 0x40,
248 RxConfig = 0x44,
249 RxMissed = 0x4C,
250 Cfg9346 = 0x50,
251 Config0 = 0x51,
252 Config1 = 0x52,
253 Config2 = 0x53,
254 Config3 = 0x54,
255 Config4 = 0x55,
256 Config5 = 0x56,
257 MultiIntr = 0x5C,
258 PHYAR = 0x60,
259 TBICSR = 0x64,
260 TBI_ANAR = 0x68,
261 TBI_LPAR = 0x6A,
262 PHYstatus = 0x6C,
263 RxMaxSize = 0xDA,
264 CPlusCmd = 0xE0,
265 IntrMitigate = 0xE2,
266 RxDescAddrLow = 0xE4,
267 RxDescAddrHigh = 0xE8,
268 EarlyTxThres = 0xEC,
269 FuncEvent = 0xF0,
270 FuncEventMask = 0xF4,
271 FuncPresetState = 0xF8,
272 FuncForceEvent = 0xFC,
273};
274
275enum RTL8169_register_content {
276 /* InterruptStatusBits */
277 SYSErr = 0x8000,
278 PCSTimeout = 0x4000,
279 SWInt = 0x0100,
280 TxDescUnavail = 0x80,
281 RxFIFOOver = 0x40,
282 LinkChg = 0x20,
283 RxOverflow = 0x10,
284 TxErr = 0x08,
285 TxOK = 0x04,
286 RxErr = 0x02,
287 RxOK = 0x01,
288
289 /* RxStatusDesc */
9dccf611
FR		 290 RxFOVF = (1 << 23),
291 RxRWT = (1 << 22),
292 RxRES = (1 << 21),
293 RxRUNT = (1 << 20),
294 RxCRC = (1 << 19),
1da177e4
LT		 295
296 /* ChipCmdBits */
297 CmdReset = 0x10,
298 CmdRxEnb = 0x08,
299 CmdTxEnb = 0x04,
300 RxBufEmpty = 0x01,
301
302 /* Cfg9346Bits */
303 Cfg9346_Lock = 0x00,
304 Cfg9346_Unlock = 0xC0,
305
306 /* rx_mode_bits */
307 AcceptErr = 0x20,
308 AcceptRunt = 0x10,
309 AcceptBroadcast = 0x08,
310 AcceptMulticast = 0x04,
311 AcceptMyPhys = 0x02,
312 AcceptAllPhys = 0x01,
313
314 /* RxConfigBits */
315 RxCfgFIFOShift = 13,
316 RxCfgDMAShift = 8,
317
318 /* TxConfigBits */
319 TxInterFrameGapShift = 24,
320 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
321
5d06a99f
FR		 322 /* Config1 register p.24 */
323 PMEnable = (1 << 0), /* Power Management Enable */
324
61a4dcc2
FR		 325 /* Config3 register p.25 */
326 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
327 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
328
5d06a99f 329 /* Config5 register p.27 */
61a4dcc2
FR		 330 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
331 MWF = (1 << 5), /* Accept Multicast wakeup frame */
332 UWF = (1 << 4), /* Accept Unicast wakeup frame */
333 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 334 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
335
1da177e4
LT		 336 /* TBICSR p.28 */
337 TBIReset = 0x80000000,
338 TBILoopback = 0x40000000,
339 TBINwEnable = 0x20000000,
340 TBINwRestart = 0x10000000,
341 TBILinkOk = 0x02000000,
342 TBINwComplete = 0x01000000,
343
344 /* CPlusCmd p.31 */
345 RxVlan = (1 << 6),
346 RxChkSum = (1 << 5),
347 PCIDAC = (1 << 4),
348 PCIMulRW = (1 << 3),
349
350 /* rtl8169_PHYstatus */
351 TBI_Enable = 0x80,
352 TxFlowCtrl = 0x40,
353 RxFlowCtrl = 0x20,
354 _1000bpsF = 0x10,
355 _100bps = 0x08,
356 _10bps = 0x04,
357 LinkStatus = 0x02,
358 FullDup = 0x01,
359
1da177e4
LT		 360 /* _MediaType */
361 _10_Half = 0x01,
362 _10_Full = 0x02,
363 _100_Half = 0x04,
364 _100_Full = 0x08,
365 _1000_Full = 0x10,
366
367 /* _TBICSRBit */
368 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 369
370 /* DumpCounterCommand */
371 CounterDump = 0x8,
1da177e4
LT		 372};
373
374enum _DescStatusBit {
375 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
376 RingEnd = (1 << 30), /* End of descriptor ring */
377 FirstFrag = (1 << 29), /* First segment of a packet */
378 LastFrag = (1 << 28), /* Final segment of a packet */
379
380 /* Tx private */
381 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
382 MSSShift = 16, /* MSS value position */
383 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
384 IPCS = (1 << 18), /* Calculate IP checksum */
385 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
386 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
387 TxVlanTag = (1 << 17), /* Add VLAN tag */
388
389 /* Rx private */
390 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
391 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
392
393#define RxProtoUDP (PID1)
394#define RxProtoTCP (PID0)
395#define RxProtoIP (PID1 | PID0)
396#define RxProtoMask RxProtoIP
397
398 IPFail = (1 << 16), /* IP checksum failed */
399 UDPFail = (1 << 15), /* UDP/IP checksum failed */
400 TCPFail = (1 << 14), /* TCP/IP checksum failed */
401 RxVlanTag = (1 << 16), /* VLAN tag available */
402};
403
404#define RsvdMask 0x3fffc000
405
406struct TxDesc {
407 u32 opts1;
408 u32 opts2;
409 u64 addr;
410};
411
412struct RxDesc {
413 u32 opts1;
414 u32 opts2;
415 u64 addr;
416};
417
418struct ring_info {
419 struct sk_buff *skb;
420 u32 len;
421 u8 __pad[sizeof(void *) - sizeof(u32)];
422};
423
424struct rtl8169_private {
425 void __iomem *mmio_addr; /* memory map physical address */
426 struct pci_dev *pci_dev; /* Index of PCI device */
427 struct net_device_stats stats; /* statistics of net device */
428 spinlock_t lock; /* spin lock flag */
b57b7e5a 429 u32 msg_enable;
1da177e4
LT		 430 int chipset;
431 int mac_version;
432 int phy_version;
433 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
434 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
435 u32 dirty_rx;
436 u32 dirty_tx;
437 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
438 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
439 dma_addr_t TxPhyAddr;
440 dma_addr_t RxPhyAddr;
441 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
442 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
bcf0bf90 443 unsigned align;
1da177e4
LT		 444 unsigned rx_buf_sz;
445 struct timer_list timer;
446 u16 cp_cmd;
447 u16 intr_mask;
448 int phy_auto_nego_reg;
449 int phy_1000_ctrl_reg;
450#ifdef CONFIG_R8169_VLAN
451 struct vlan_group *vlgrp;
452#endif
453 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
454 void (*get_settings)(struct net_device *, struct ethtool_cmd *);
455 void (*phy_reset_enable)(void __iomem *);
456 unsigned int (*phy_reset_pending)(void __iomem *);
457 unsigned int (*link_ok)(void __iomem *);
458 struct work_struct task;
61a4dcc2 459 unsigned wol_enabled : 1;
1da177e4
LT		 460};
461
979b6c13 462MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4
LT		 463MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
464module_param_array(media, int, &num_media, 0);
df0a1bf6 465MODULE_PARM_DESC(media, "force phy operation. Deprecated by ethtool (8).");
1da177e4 466module_param(rx_copybreak, int, 0);
1b7efd58 467MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
1da177e4
LT		 468module_param(use_dac, int, 0);
469MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 470module_param_named(debug, debug.msg_enable, int, 0);
471MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 472MODULE_LICENSE("GPL");
473MODULE_VERSION(RTL8169_VERSION);
474
475static int rtl8169_open(struct net_device *dev);
476static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
7d12e780 477static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4
LT		 478static int rtl8169_init_ring(struct net_device *dev);
479static void rtl8169_hw_start(struct net_device *dev);
480static int rtl8169_close(struct net_device *dev);
481static void rtl8169_set_rx_mode(struct net_device *dev);
482static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 483static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4
LT		 484static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
485 void __iomem *);
4dcb7d33 486static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4
LT		 487static void rtl8169_down(struct net_device *dev);
488
489#ifdef CONFIG_R8169_NAPI
490static int rtl8169_poll(struct net_device *dev, int *budget);
491#endif
492
493static const u16 rtl8169_intr_mask =
494 SYSErr | LinkChg | RxOverflow | RxFIFOOver | TxErr | TxOK | RxErr | RxOK;
495static const u16 rtl8169_napi_event =
496 RxOK | RxOverflow | RxFIFOOver | TxOK | TxErr;
497static const unsigned int rtl8169_rx_config =
5b0384f4 498 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4
LT		 499
500static void mdio_write(void __iomem *ioaddr, int RegAddr, int value)
501{
502 int i;
503
504 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
1da177e4 505
2371408c 506 for (i = 20; i > 0; i--) {
1da177e4 507 /* Check if the RTL8169 has completed writing to the specified MII register */
5b0384f4 508 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 509 break;
2371408c 510 udelay(25);
1da177e4
LT		 511 }
512}
513
514static int mdio_read(void __iomem *ioaddr, int RegAddr)
515{
516 int i, value = -1;
517
518 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
1da177e4 519
2371408c 520 for (i = 20; i > 0; i--) {
1da177e4
LT		 521 /* Check if the RTL8169 has completed retrieving data from the specified MII register */
522 if (RTL_R32(PHYAR) & 0x80000000) {
523 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
524 break;
525 }
2371408c 526 udelay(25);
1da177e4
LT		 527 }
528 return value;
529}
530
531static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
532{
533 RTL_W16(IntrMask, 0x0000);
534
535 RTL_W16(IntrStatus, 0xffff);
536}
537
538static void rtl8169_asic_down(void __iomem *ioaddr)
539{
540 RTL_W8(ChipCmd, 0x00);
541 rtl8169_irq_mask_and_ack(ioaddr);
542 RTL_R16(CPlusCmd);
543}
544
545static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
546{
547 return RTL_R32(TBICSR) & TBIReset;
548}
549
550static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
551{
64e4bfb4 552 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 553}
554
555static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
556{
557 return RTL_R32(TBICSR) & TBILinkOk;
558}
559
560static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
561{
562 return RTL_R8(PHYstatus) & LinkStatus;
563}
564
565static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
566{
567 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
568}
569
570static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
571{
572 unsigned int val;
573
64e4bfb4
FR		 574 val = (mdio_read(ioaddr, MII_BMCR) | BMCR_RESET) & 0xffff;
575 mdio_write(ioaddr, MII_BMCR, val);
1da177e4
LT		 576}
577
578static void rtl8169_check_link_status(struct net_device *dev,
579 struct rtl8169_private *tp, void __iomem *ioaddr)
580{
581 unsigned long flags;
582
583 spin_lock_irqsave(&tp->lock, flags);
584 if (tp->link_ok(ioaddr)) {
585 netif_carrier_on(dev);
b57b7e5a
SH		 586 if (netif_msg_ifup(tp))
587 printk(KERN_INFO PFX "%s: link up\n", dev->name);
588 } else {
589 if (netif_msg_ifdown(tp))
590 printk(KERN_INFO PFX "%s: link down\n", dev->name);
1da177e4 591 netif_carrier_off(dev);
b57b7e5a 592 }
1da177e4
LT		 593 spin_unlock_irqrestore(&tp->lock, flags);
594}
595
596static void rtl8169_link_option(int idx, u8 *autoneg, u16 *speed, u8 *duplex)
597{
598 struct {
599 u16 speed;
600 u8 duplex;
601 u8 autoneg;
602 u8 media;
603 } link_settings[] = {
604 { SPEED_10, DUPLEX_HALF, AUTONEG_DISABLE, _10_Half },
605 { SPEED_10, DUPLEX_FULL, AUTONEG_DISABLE, _10_Full },
606 { SPEED_100, DUPLEX_HALF, AUTONEG_DISABLE, _100_Half },
607 { SPEED_100, DUPLEX_FULL, AUTONEG_DISABLE, _100_Full },
608 { SPEED_1000, DUPLEX_FULL, AUTONEG_DISABLE, _1000_Full },
609 /* Make TBI happy */
610 { SPEED_1000, DUPLEX_FULL, AUTONEG_ENABLE, 0xff }
611 }, *p;
612 unsigned char option;
5b0384f4 613
1da177e4
LT		 614 option = ((idx < MAX_UNITS) && (idx >= 0)) ? media[idx] : 0xff;
615
b57b7e5a 616 if ((option != 0xff) && !idx && netif_msg_drv(&debug))
1da177e4
LT		 617 printk(KERN_WARNING PFX "media option is deprecated.\n");
618
619 for (p = link_settings; p->media != 0xff; p++) {
620 if (p->media == option)
621 break;
622 }
623 *autoneg = p->autoneg;
624 *speed = p->speed;
625 *duplex = p->duplex;
626}
627
61a4dcc2
FR		 628static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
629{
630 struct rtl8169_private *tp = netdev_priv(dev);
631 void __iomem *ioaddr = tp->mmio_addr;
632 u8 options;
633
634 wol->wolopts = 0;
635
636#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
637 wol->supported = WAKE_ANY;
638
639 spin_lock_irq(&tp->lock);
640
641 options = RTL_R8(Config1);
642 if (!(options & PMEnable))
643 goto out_unlock;
644
645 options = RTL_R8(Config3);
646 if (options & LinkUp)
647 wol->wolopts |= WAKE_PHY;
648 if (options & MagicPacket)
649 wol->wolopts |= WAKE_MAGIC;
650
651 options = RTL_R8(Config5);
652 if (options & UWF)
653 wol->wolopts |= WAKE_UCAST;
654 if (options & BWF)
5b0384f4 655 wol->wolopts |= WAKE_BCAST;
61a4dcc2 656 if (options & MWF)
5b0384f4 657 wol->wolopts |= WAKE_MCAST;
61a4dcc2
FR		 658
659out_unlock:
660 spin_unlock_irq(&tp->lock);
661}
662
663static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
664{
665 struct rtl8169_private *tp = netdev_priv(dev);
666 void __iomem *ioaddr = tp->mmio_addr;
667 int i;
668 static struct {
669 u32 opt;
670 u16 reg;
671 u8 mask;
672 } cfg[] = {
673 { WAKE_ANY, Config1, PMEnable },
674 { WAKE_PHY, Config3, LinkUp },
675 { WAKE_MAGIC, Config3, MagicPacket },
676 { WAKE_UCAST, Config5, UWF },
677 { WAKE_BCAST, Config5, BWF },
678 { WAKE_MCAST, Config5, MWF },
679 { WAKE_ANY, Config5, LanWake }
680 };
681
682 spin_lock_irq(&tp->lock);
683
684 RTL_W8(Cfg9346, Cfg9346_Unlock);
685
686 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
687 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
688 if (wol->wolopts & cfg[i].opt)
689 options |= cfg[i].mask;
690 RTL_W8(cfg[i].reg, options);
691 }
692
693 RTL_W8(Cfg9346, Cfg9346_Lock);
694
695 tp->wol_enabled = (wol->wolopts) ? 1 : 0;
696
697 spin_unlock_irq(&tp->lock);
698
699 return 0;
700}
701
1da177e4
LT		 702static void rtl8169_get_drvinfo(struct net_device *dev,
703 struct ethtool_drvinfo *info)
704{
705 struct rtl8169_private *tp = netdev_priv(dev);
706
707 strcpy(info->driver, MODULENAME);
708 strcpy(info->version, RTL8169_VERSION);
709 strcpy(info->bus_info, pci_name(tp->pci_dev));
710}
711
712static int rtl8169_get_regs_len(struct net_device *dev)
713{
714 return R8169_REGS_SIZE;
715}
716
717static int rtl8169_set_speed_tbi(struct net_device *dev,
718 u8 autoneg, u16 speed, u8 duplex)
719{
720 struct rtl8169_private *tp = netdev_priv(dev);
721 void __iomem *ioaddr = tp->mmio_addr;
722 int ret = 0;
723 u32 reg;
724
725 reg = RTL_R32(TBICSR);
726 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
727 (duplex == DUPLEX_FULL)) {
728 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
729 } else if (autoneg == AUTONEG_ENABLE)
730 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
731 else {
b57b7e5a
SH		 732 if (netif_msg_link(tp)) {
733 printk(KERN_WARNING "%s: "
734 "incorrect speed setting refused in TBI mode\n",
735 dev->name);
736 }
1da177e4
LT		 737 ret = -EOPNOTSUPP;
738 }
739
740 return ret;
741}
742
743static int rtl8169_set_speed_xmii(struct net_device *dev,
744 u8 autoneg, u16 speed, u8 duplex)
745{
746 struct rtl8169_private *tp = netdev_priv(dev);
747 void __iomem *ioaddr = tp->mmio_addr;
748 int auto_nego, giga_ctrl;
749
64e4bfb4
FR		 750 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
751 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
752 ADVERTISE_100HALF | ADVERTISE_100FULL);
753 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
754 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 755
756 if (autoneg == AUTONEG_ENABLE) {
64e4bfb4
FR		 757 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
758 ADVERTISE_100HALF | ADVERTISE_100FULL);
759 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 760 } else {
761 if (speed == SPEED_10)
64e4bfb4 762 auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1da177e4 763 else if (speed == SPEED_100)
64e4bfb4 764 auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
1da177e4 765 else if (speed == SPEED_1000)
64e4bfb4 766 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 767
768 if (duplex == DUPLEX_HALF)
64e4bfb4 769 auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
726ecdcf
AG		 770
771 if (duplex == DUPLEX_FULL)
64e4bfb4 772 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
bcf0bf90
FR		 773
774 /* This tweak comes straight from Realtek's driver. */
775 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
776 (tp->mac_version == RTL_GIGA_MAC_VER_13)) {
64e4bfb4 777 auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
bcf0bf90
FR		 778 }
779 }
780
781 /* The 8100e/8101e do Fast Ethernet only. */
782 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
783 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
784 (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
64e4bfb4 785 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
bcf0bf90
FR		 786 netif_msg_link(tp)) {
787 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
788 dev->name);
789 }
64e4bfb4 790 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 791 }
792
623a1593
FR		 793 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
794
1da177e4
LT		 795 tp->phy_auto_nego_reg = auto_nego;
796 tp->phy_1000_ctrl_reg = giga_ctrl;
797
64e4bfb4
FR		 798 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
799 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
800 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
1da177e4
LT		 801 return 0;
802}
803
804static int rtl8169_set_speed(struct net_device *dev,
805 u8 autoneg, u16 speed, u8 duplex)
806{
807 struct rtl8169_private *tp = netdev_priv(dev);
808 int ret;
809
810 ret = tp->set_speed(dev, autoneg, speed, duplex);
811
64e4bfb4 812 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 813 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
814
815 return ret;
816}
817
818static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
819{
820 struct rtl8169_private *tp = netdev_priv(dev);
821 unsigned long flags;
822 int ret;
823
824 spin_lock_irqsave(&tp->lock, flags);
825 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
826 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 827
1da177e4
LT		 828 return ret;
829}
830
831static u32 rtl8169_get_rx_csum(struct net_device *dev)
832{
833 struct rtl8169_private *tp = netdev_priv(dev);
834
835 return tp->cp_cmd & RxChkSum;
836}
837
838static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
839{
840 struct rtl8169_private *tp = netdev_priv(dev);
841 void __iomem *ioaddr = tp->mmio_addr;
842 unsigned long flags;
843
844 spin_lock_irqsave(&tp->lock, flags);
845
846 if (data)
847 tp->cp_cmd |= RxChkSum;
848 else
849 tp->cp_cmd &= ~RxChkSum;
850
851 RTL_W16(CPlusCmd, tp->cp_cmd);
852 RTL_R16(CPlusCmd);
853
854 spin_unlock_irqrestore(&tp->lock, flags);
855
856 return 0;
857}
858
859#ifdef CONFIG_R8169_VLAN
860
861static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
862 struct sk_buff *skb)
863{
864 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
865 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
866}
867
868static void rtl8169_vlan_rx_register(struct net_device *dev,
869 struct vlan_group *grp)
870{
871 struct rtl8169_private *tp = netdev_priv(dev);
872 void __iomem *ioaddr = tp->mmio_addr;
873 unsigned long flags;
874
875 spin_lock_irqsave(&tp->lock, flags);
876 tp->vlgrp = grp;
877 if (tp->vlgrp)
878 tp->cp_cmd |= RxVlan;
879 else
880 tp->cp_cmd &= ~RxVlan;
881 RTL_W16(CPlusCmd, tp->cp_cmd);
882 RTL_R16(CPlusCmd);
883 spin_unlock_irqrestore(&tp->lock, flags);
884}
885
886static void rtl8169_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
887{
888 struct rtl8169_private *tp = netdev_priv(dev);
889 unsigned long flags;
890
891 spin_lock_irqsave(&tp->lock, flags);
892 if (tp->vlgrp)
893 tp->vlgrp->vlan_devices[vid] = NULL;
894 spin_unlock_irqrestore(&tp->lock, flags);
895}
896
897static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
898 struct sk_buff *skb)
899{
900 u32 opts2 = le32_to_cpu(desc->opts2);
901 int ret;
902
903 if (tp->vlgrp && (opts2 & RxVlanTag)) {
904 rtl8169_rx_hwaccel_skb(skb, tp->vlgrp,
905 swab16(opts2 & 0xffff));
906 ret = 0;
907 } else
908 ret = -1;
909 desc->opts2 = 0;
910 return ret;
911}
912
913#else /* !CONFIG_R8169_VLAN */
914
915static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
916 struct sk_buff *skb)
917{
918 return 0;
919}
920
921static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
922 struct sk_buff *skb)
923{
924 return -1;
925}
926
927#endif
928
929static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
930{
931 struct rtl8169_private *tp = netdev_priv(dev);
932 void __iomem *ioaddr = tp->mmio_addr;
933 u32 status;
934
935 cmd->supported =
936 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
937 cmd->port = PORT_FIBRE;
938 cmd->transceiver = XCVR_INTERNAL;
939
940 status = RTL_R32(TBICSR);
941 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
942 cmd->autoneg = !!(status & TBINwEnable);
943
944 cmd->speed = SPEED_1000;
945 cmd->duplex = DUPLEX_FULL; /* Always set */
946}
947
948static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
949{
950 struct rtl8169_private *tp = netdev_priv(dev);
951 void __iomem *ioaddr = tp->mmio_addr;
952 u8 status;
953
954 cmd->supported = SUPPORTED_10baseT_Half |
955 SUPPORTED_10baseT_Full |
956 SUPPORTED_100baseT_Half |
957 SUPPORTED_100baseT_Full |
958 SUPPORTED_1000baseT_Full |
959 SUPPORTED_Autoneg |
5b0384f4 960 SUPPORTED_TP;
1da177e4
LT		 961
962 cmd->autoneg = 1;
963 cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
964
64e4bfb4 965 if (tp->phy_auto_nego_reg & ADVERTISE_10HALF)
1da177e4 966 cmd->advertising |= ADVERTISED_10baseT_Half;
64e4bfb4 967 if (tp->phy_auto_nego_reg & ADVERTISE_10FULL)
1da177e4 968 cmd->advertising |= ADVERTISED_10baseT_Full;
64e4bfb4 969 if (tp->phy_auto_nego_reg & ADVERTISE_100HALF)
1da177e4 970 cmd->advertising |= ADVERTISED_100baseT_Half;
64e4bfb4 971 if (tp->phy_auto_nego_reg & ADVERTISE_100FULL)
1da177e4 972 cmd->advertising |= ADVERTISED_100baseT_Full;
64e4bfb4 973 if (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)
1da177e4
LT		 974 cmd->advertising |= ADVERTISED_1000baseT_Full;
975
976 status = RTL_R8(PHYstatus);
977
978 if (status & _1000bpsF)
979 cmd->speed = SPEED_1000;
980 else if (status & _100bps)
981 cmd->speed = SPEED_100;
982 else if (status & _10bps)
983 cmd->speed = SPEED_10;
984
623a1593
FR		 985 if (status & TxFlowCtrl)
986 cmd->advertising |= ADVERTISED_Asym_Pause;
987 if (status & RxFlowCtrl)
988 cmd->advertising |= ADVERTISED_Pause;
989
1da177e4
LT		 990 cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ?
991 DUPLEX_FULL : DUPLEX_HALF;
992}
993
994static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
995{
996 struct rtl8169_private *tp = netdev_priv(dev);
997 unsigned long flags;
998
999 spin_lock_irqsave(&tp->lock, flags);
1000
1001 tp->get_settings(dev, cmd);
1002
1003 spin_unlock_irqrestore(&tp->lock, flags);
1004 return 0;
1005}
1006
1007static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1008 void *p)
1009{
5b0384f4
FR		 1010 struct rtl8169_private *tp = netdev_priv(dev);
1011 unsigned long flags;
1da177e4 1012
5b0384f4
FR		 1013 if (regs->len > R8169_REGS_SIZE)
1014 regs->len = R8169_REGS_SIZE;
1da177e4 1015
5b0384f4
FR		 1016 spin_lock_irqsave(&tp->lock, flags);
1017 memcpy_fromio(p, tp->mmio_addr, regs->len);
1018 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 1019}
1020
b57b7e5a
SH		 1021static u32 rtl8169_get_msglevel(struct net_device *dev)
1022{
1023 struct rtl8169_private *tp = netdev_priv(dev);
1024
1025 return tp->msg_enable;
1026}
1027
1028static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1029{
1030 struct rtl8169_private *tp = netdev_priv(dev);
1031
1032 tp->msg_enable = value;
1033}
1034
d4a3a0fc
SH		 1035static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1036 "tx_packets",
1037 "rx_packets",
1038 "tx_errors",
1039 "rx_errors",
1040 "rx_missed",
1041 "align_errors",
1042 "tx_single_collisions",
1043 "tx_multi_collisions",
1044 "unicast",
1045 "broadcast",
1046 "multicast",
1047 "tx_aborted",
1048 "tx_underrun",
1049};
1050
1051struct rtl8169_counters {
1052 u64 tx_packets;
1053 u64 rx_packets;
1054 u64 tx_errors;
1055 u32 rx_errors;
1056 u16 rx_missed;
1057 u16 align_errors;
1058 u32 tx_one_collision;
1059 u32 tx_multi_collision;
1060 u64 rx_unicast;
1061 u64 rx_broadcast;
1062 u32 rx_multicast;
1063 u16 tx_aborted;
1064 u16 tx_underun;
1065};
1066
1067static int rtl8169_get_stats_count(struct net_device *dev)
1068{
1069 return ARRAY_SIZE(rtl8169_gstrings);
1070}
1071
1072static void rtl8169_get_ethtool_stats(struct net_device *dev,
1073 struct ethtool_stats *stats, u64 *data)
1074{
1075 struct rtl8169_private *tp = netdev_priv(dev);
1076 void __iomem *ioaddr = tp->mmio_addr;
1077 struct rtl8169_counters *counters;
1078 dma_addr_t paddr;
1079 u32 cmd;
1080
1081 ASSERT_RTNL();
1082
1083 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1084 if (!counters)
1085 return;
1086
1087 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1088 cmd = (u64)paddr & DMA_32BIT_MASK;
1089 RTL_W32(CounterAddrLow, cmd);
1090 RTL_W32(CounterAddrLow, cmd | CounterDump);
1091
1092 while (RTL_R32(CounterAddrLow) & CounterDump) {
1093 if (msleep_interruptible(1))
1094 break;
1095 }
1096
1097 RTL_W32(CounterAddrLow, 0);
1098 RTL_W32(CounterAddrHigh, 0);
1099
5b0384f4 1100 data[0] = le64_to_cpu(counters->tx_packets);
d4a3a0fc
SH		 1101 data[1] = le64_to_cpu(counters->rx_packets);
1102 data[2] = le64_to_cpu(counters->tx_errors);
1103 data[3] = le32_to_cpu(counters->rx_errors);
1104 data[4] = le16_to_cpu(counters->rx_missed);
1105 data[5] = le16_to_cpu(counters->align_errors);
1106 data[6] = le32_to_cpu(counters->tx_one_collision);
1107 data[7] = le32_to_cpu(counters->tx_multi_collision);
1108 data[8] = le64_to_cpu(counters->rx_unicast);
1109 data[9] = le64_to_cpu(counters->rx_broadcast);
1110 data[10] = le32_to_cpu(counters->rx_multicast);
1111 data[11] = le16_to_cpu(counters->tx_aborted);
1112 data[12] = le16_to_cpu(counters->tx_underun);
1113
1114 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1115}
1116
1117static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1118{
1119 switch(stringset) {
1120 case ETH_SS_STATS:
1121 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1122 break;
1123 }
1124}
1125
1126
7282d491 1127static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1128 .get_drvinfo = rtl8169_get_drvinfo,
1129 .get_regs_len = rtl8169_get_regs_len,
1130 .get_link = ethtool_op_get_link,
1131 .get_settings = rtl8169_get_settings,
1132 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1133 .get_msglevel = rtl8169_get_msglevel,
1134 .set_msglevel = rtl8169_set_msglevel,
1da177e4
LT		 1135 .get_rx_csum = rtl8169_get_rx_csum,
1136 .set_rx_csum = rtl8169_set_rx_csum,
1137 .get_tx_csum = ethtool_op_get_tx_csum,
1138 .set_tx_csum = ethtool_op_set_tx_csum,
1139 .get_sg = ethtool_op_get_sg,
1140 .set_sg = ethtool_op_set_sg,
1141 .get_tso = ethtool_op_get_tso,
1142 .set_tso = ethtool_op_set_tso,
1143 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1144 .get_wol = rtl8169_get_wol,
1145 .set_wol = rtl8169_set_wol,
d4a3a0fc
SH		 1146 .get_strings = rtl8169_get_strings,
1147 .get_stats_count = rtl8169_get_stats_count,
1148 .get_ethtool_stats = rtl8169_get_ethtool_stats,
6d6525b7 1149 .get_perm_addr = ethtool_op_get_perm_addr,
1da177e4
LT		 1150};
1151
1152static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg, int bitnum,
1153 int bitval)
1154{
1155 int val;
1156
1157 val = mdio_read(ioaddr, reg);
1158 val = (bitval == 1) ?
1159 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
5b0384f4 1160 mdio_write(ioaddr, reg, val & 0xffff);
1da177e4
LT		 1161}
1162
1163static void rtl8169_get_mac_version(struct rtl8169_private *tp, void __iomem *ioaddr)
1164{
1165 const struct {
1166 u32 mask;
1167 int mac_version;
1168 } mac_info[] = {
bcf0bf90
FR		 1169 { 0x38800000, RTL_GIGA_MAC_VER_15 },
1170 { 0x38000000, RTL_GIGA_MAC_VER_12 },
1171 { 0x34000000, RTL_GIGA_MAC_VER_13 },
1172 { 0x30800000, RTL_GIGA_MAC_VER_14 },
5b0384f4 1173 { 0x30000000, RTL_GIGA_MAC_VER_11 },
bcf0bf90
FR		 1174 { 0x18000000, RTL_GIGA_MAC_VER_05 },
1175 { 0x10000000, RTL_GIGA_MAC_VER_04 },
1176 { 0x04000000, RTL_GIGA_MAC_VER_03 },
1177 { 0x00800000, RTL_GIGA_MAC_VER_02 },
1178 { 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
1da177e4
LT		 1179 }, *p = mac_info;
1180 u32 reg;
1181
1182 reg = RTL_R32(TxConfig) & 0x7c800000;
1183 while ((reg & p->mask) != p->mask)
1184 p++;
1185 tp->mac_version = p->mac_version;
1186}
1187
1188static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1189{
bcf0bf90 1190 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1191}
1192
1193static void rtl8169_get_phy_version(struct rtl8169_private *tp, void __iomem *ioaddr)
1194{
1195 const struct {
1196 u16 mask;
1197 u16 set;
1198 int phy_version;
1199 } phy_info[] = {
1200 { 0x000f, 0x0002, RTL_GIGA_PHY_VER_G },
1201 { 0x000f, 0x0001, RTL_GIGA_PHY_VER_F },
1202 { 0x000f, 0x0000, RTL_GIGA_PHY_VER_E },
1203 { 0x0000, 0x0000, RTL_GIGA_PHY_VER_D } /* Catch-all */
1204 }, *p = phy_info;
1205 u16 reg;
1206
64e4bfb4 1207 reg = mdio_read(ioaddr, MII_PHYSID2) & 0xffff;
1da177e4
LT		 1208 while ((reg & p->mask) != p->set)
1209 p++;
1210 tp->phy_version = p->phy_version;
1211}
1212
1213static void rtl8169_print_phy_version(struct rtl8169_private *tp)
1214{
1215 struct {
1216 int version;
1217 char *msg;
1218 u32 reg;
1219 } phy_print[] = {
1220 { RTL_GIGA_PHY_VER_G, "RTL_GIGA_PHY_VER_G", 0x0002 },
1221 { RTL_GIGA_PHY_VER_F, "RTL_GIGA_PHY_VER_F", 0x0001 },
1222 { RTL_GIGA_PHY_VER_E, "RTL_GIGA_PHY_VER_E", 0x0000 },
1223 { RTL_GIGA_PHY_VER_D, "RTL_GIGA_PHY_VER_D", 0x0000 },
1224 { 0, NULL, 0x0000 }
1225 }, *p;
1226
1227 for (p = phy_print; p->msg; p++) {
1228 if (tp->phy_version == p->version) {
1229 dprintk("phy_version == %s (%04x)\n", p->msg, p->reg);
1230 return;
1231 }
1232 }
1233 dprintk("phy_version == Unknown\n");
1234}
1235
1236static void rtl8169_hw_phy_config(struct net_device *dev)
1237{
1238 struct rtl8169_private *tp = netdev_priv(dev);
1239 void __iomem *ioaddr = tp->mmio_addr;
1240 struct {
1241 u16 regs[5]; /* Beware of bit-sign propagation */
1242 } phy_magic[5] = { {
1243 { 0x0000, //w 4 15 12 0
1244 0x00a1, //w 3 15 0 00a1
1245 0x0008, //w 2 15 0 0008
1246 0x1020, //w 1 15 0 1020
1247 0x1000 } },{ //w 0 15 0 1000
1248 { 0x7000, //w 4 15 12 7
1249 0xff41, //w 3 15 0 ff41
1250 0xde60, //w 2 15 0 de60
1251 0x0140, //w 1 15 0 0140
1252 0x0077 } },{ //w 0 15 0 0077
1253 { 0xa000, //w 4 15 12 a
1254 0xdf01, //w 3 15 0 df01
1255 0xdf20, //w 2 15 0 df20
1256 0xff95, //w 1 15 0 ff95
1257 0xfa00 } },{ //w 0 15 0 fa00
1258 { 0xb000, //w 4 15 12 b
1259 0xff41, //w 3 15 0 ff41
1260 0xde20, //w 2 15 0 de20
1261 0x0140, //w 1 15 0 0140
1262 0x00bb } },{ //w 0 15 0 00bb
1263 { 0xf000, //w 4 15 12 f
1264 0xdf01, //w 3 15 0 df01
1265 0xdf20, //w 2 15 0 df20
1266 0xff95, //w 1 15 0 ff95
1267 0xbf00 } //w 0 15 0 bf00
1268 }
1269 }, *p = phy_magic;
1270 int i;
1271
1272 rtl8169_print_mac_version(tp);
1273 rtl8169_print_phy_version(tp);
1274
bcf0bf90 1275 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 1276 return;
1277 if (tp->phy_version >= RTL_GIGA_PHY_VER_H)
1278 return;
1279
1280 dprintk("MAC version != 0 && PHY version == 0 or 1\n");
1281 dprintk("Do final_reg2.cfg\n");
1282
1283 /* Shazam ! */
1284
bcf0bf90 1285 if (tp->mac_version == RTL_GIGA_MAC_VER_04) {
1da177e4
LT		 1286 mdio_write(ioaddr, 31, 0x0001);
1287 mdio_write(ioaddr, 9, 0x273a);
1288 mdio_write(ioaddr, 14, 0x7bfb);
1289 mdio_write(ioaddr, 27, 0x841e);
1290
1291 mdio_write(ioaddr, 31, 0x0002);
1292 mdio_write(ioaddr, 1, 0x90d0);
1293 mdio_write(ioaddr, 31, 0x0000);
1294 return;
1295 }
1296
1297 /* phy config for RTL8169s mac_version C chip */
1298 mdio_write(ioaddr, 31, 0x0001); //w 31 2 0 1
1299 mdio_write(ioaddr, 21, 0x1000); //w 21 15 0 1000
1300 mdio_write(ioaddr, 24, 0x65c7); //w 24 15 0 65c7
1301 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1302
1303 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1304 int val, pos = 4;
1305
1306 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1307 mdio_write(ioaddr, pos, val);
1308 while (--pos >= 0)
1309 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1310 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1311 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1312 }
1313 mdio_write(ioaddr, 31, 0x0000); //w 31 2 0 0
1314}
1315
1316static void rtl8169_phy_timer(unsigned long __opaque)
1317{
1318 struct net_device *dev = (struct net_device *)__opaque;
1319 struct rtl8169_private *tp = netdev_priv(dev);
1320 struct timer_list *timer = &tp->timer;
1321 void __iomem *ioaddr = tp->mmio_addr;
1322 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1323
bcf0bf90 1324 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4
LT		 1325 assert(tp->phy_version < RTL_GIGA_PHY_VER_H);
1326
64e4bfb4 1327 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 1328 return;
1329
1330 spin_lock_irq(&tp->lock);
1331
1332 if (tp->phy_reset_pending(ioaddr)) {
5b0384f4 1333 /*
1da177e4
LT		 1334 * A busy loop could burn quite a few cycles on nowadays CPU.
1335 * Let's delay the execution of the timer for a few ticks.
1336 */
1337 timeout = HZ/10;
1338 goto out_mod_timer;
1339 }
1340
1341 if (tp->link_ok(ioaddr))
1342 goto out_unlock;
1343
b57b7e5a
SH		 1344 if (netif_msg_link(tp))
1345 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1da177e4
LT		 1346
1347 tp->phy_reset_enable(ioaddr);
1348
1349out_mod_timer:
1350 mod_timer(timer, jiffies + timeout);
1351out_unlock:
1352 spin_unlock_irq(&tp->lock);
1353}
1354
1355static inline void rtl8169_delete_timer(struct net_device *dev)
1356{
1357 struct rtl8169_private *tp = netdev_priv(dev);
1358 struct timer_list *timer = &tp->timer;
1359
bcf0bf90 1360 if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1da177e4
LT		 1361 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1362 return;
1363
1364 del_timer_sync(timer);
1365}
1366
1367static inline void rtl8169_request_timer(struct net_device *dev)
1368{
1369 struct rtl8169_private *tp = netdev_priv(dev);
1370 struct timer_list *timer = &tp->timer;
1371
bcf0bf90 1372 if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1da177e4
LT		 1373 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1374 return;
1375
1376 init_timer(timer);
1377 timer->expires = jiffies + RTL8169_PHY_TIMEOUT;
1378 timer->data = (unsigned long)(dev);
1379 timer->function = rtl8169_phy_timer;
1380 add_timer(timer);
1381}
1382
1383#ifdef CONFIG_NET_POLL_CONTROLLER
1384/*
1385 * Polling 'interrupt' - used by things like netconsole to send skbs
1386 * without having to re-enable interrupts. It's not called while
1387 * the interrupt routine is executing.
1388 */
1389static void rtl8169_netpoll(struct net_device *dev)
1390{
1391 struct rtl8169_private *tp = netdev_priv(dev);
1392 struct pci_dev *pdev = tp->pci_dev;
1393
1394 disable_irq(pdev->irq);
7d12e780 1395 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 1396 enable_irq(pdev->irq);
1397}
1398#endif
1399
1400static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1401 void __iomem *ioaddr)
1402{
1403 iounmap(ioaddr);
1404 pci_release_regions(pdev);
1405 pci_disable_device(pdev);
1406 free_netdev(dev);
1407}
1408
4ff96fa6
FR		 1409static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1410{
1411 void __iomem *ioaddr = tp->mmio_addr;
1412 static int board_idx = -1;
1413 u8 autoneg, duplex;
1414 u16 speed;
1415
1416 board_idx++;
1417
1418 rtl8169_hw_phy_config(dev);
1419
1420 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1421 RTL_W8(0x82, 0x01);
1422
bcf0bf90 1423 if (tp->mac_version < RTL_GIGA_MAC_VER_03) {
4ff96fa6
FR		 1424 dprintk("Set PCI Latency=0x40\n");
1425 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1426 }
1427
bcf0bf90 1428 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 1429 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1430 RTL_W8(0x82, 0x01);
1431 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1432 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1433 }
1434
1435 rtl8169_link_option(board_idx, &autoneg, &speed, &duplex);
1436
1437 rtl8169_set_speed(dev, autoneg, speed, duplex);
1438
1439 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1440 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1441}
1442
5f787a1a
FR		 1443static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1444{
1445 struct rtl8169_private *tp = netdev_priv(dev);
1446 struct mii_ioctl_data *data = if_mii(ifr);
1447
1448 if (!netif_running(dev))
1449 return -ENODEV;
1450
1451 switch (cmd) {
1452 case SIOCGMIIPHY:
1453 data->phy_id = 32; /* Internal PHY */
1454 return 0;
1455
1456 case SIOCGMIIREG:
1457 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1458 return 0;
1459
1460 case SIOCSMIIREG:
1461 if (!capable(CAP_NET_ADMIN))
1462 return -EPERM;
1463 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1464 return 0;
1465 }
1466 return -EOPNOTSUPP;
1467}
1468
1da177e4 1469static int __devinit
4ff96fa6 1470rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1471{
bcf0bf90 1472 const unsigned int region = rtl_cfg_info[ent->driver_data].region;
1da177e4 1473 struct rtl8169_private *tp;
4ff96fa6
FR		 1474 struct net_device *dev;
1475 void __iomem *ioaddr;
315917d2
FR		 1476 unsigned int pm_cap;
1477 int i, rc;
1da177e4 1478
4ff96fa6
FR		 1479 if (netif_msg_drv(&debug)) {
1480 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1481 MODULENAME, RTL8169_VERSION);
1482 }
1da177e4 1483
1da177e4 1484 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 1485 if (!dev) {
b57b7e5a 1486 if (netif_msg_drv(&debug))
9b91cf9d 1487 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 1488 rc = -ENOMEM;
1489 goto out;
1da177e4
LT		 1490 }
1491
1492 SET_MODULE_OWNER(dev);
1493 SET_NETDEV_DEV(dev, &pdev->dev);
1494 tp = netdev_priv(dev);
b57b7e5a 1495 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4
LT		 1496
1497 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1498 rc = pci_enable_device(pdev);
b57b7e5a 1499 if (rc < 0) {
2e8a538d 1500 if (netif_msg_probe(tp))
9b91cf9d 1501 dev_err(&pdev->dev, "enable failure\n");
4ff96fa6 1502 goto err_out_free_dev_1;
1da177e4
LT		 1503 }
1504
1505 rc = pci_set_mwi(pdev);
1506 if (rc < 0)
4ff96fa6 1507 goto err_out_disable_2;
1da177e4
LT		 1508
1509 /* save power state before pci_enable_device overwrites it */
1510 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
1511 if (pm_cap) {
4ff96fa6 1512 u16 pwr_command, acpi_idle_state;
1da177e4
LT		 1513
1514 pci_read_config_word(pdev, pm_cap + PCI_PM_CTRL, &pwr_command);
1515 acpi_idle_state = pwr_command & PCI_PM_CTRL_STATE_MASK;
1516 } else {
4ff96fa6 1517 if (netif_msg_probe(tp)) {
9b91cf9d 1518 dev_err(&pdev->dev,
4ff96fa6
FR		 1519 "PowerManagement capability not found.\n");
1520 }
1da177e4
LT		 1521 }
1522
1523 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 1524 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
4ff96fa6 1525 if (netif_msg_probe(tp)) {
9b91cf9d 1526 dev_err(&pdev->dev,
bcf0bf90
FR		 1527 "region #%d not an MMIO resource, aborting\n",
1528 region);
4ff96fa6 1529 }
1da177e4 1530 rc = -ENODEV;
4ff96fa6 1531 goto err_out_mwi_3;
1da177e4 1532 }
4ff96fa6 1533
1da177e4 1534 /* check for weird/broken PCI region reporting */
bcf0bf90 1535 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
4ff96fa6 1536 if (netif_msg_probe(tp)) {
9b91cf9d 1537 dev_err(&pdev->dev,
4ff96fa6
FR		 1538 "Invalid PCI region size(s), aborting\n");
1539 }
1da177e4 1540 rc = -ENODEV;
4ff96fa6 1541 goto err_out_mwi_3;
1da177e4
LT		 1542 }
1543
1544 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 1545 if (rc < 0) {
2e8a538d 1546 if (netif_msg_probe(tp))
9b91cf9d 1547 dev_err(&pdev->dev, "could not request regions.\n");
4ff96fa6 1548 goto err_out_mwi_3;
1da177e4
LT		 1549 }
1550
1551 tp->cp_cmd = PCIMulRW | RxChkSum;
1552
1553 if ((sizeof(dma_addr_t) > 4) &&
1554 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1555 tp->cp_cmd |= PCIDAC;
1556 dev->features |= NETIF_F_HIGHDMA;
1557 } else {
1558 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1559 if (rc < 0) {
4ff96fa6 1560 if (netif_msg_probe(tp)) {
9b91cf9d 1561 dev_err(&pdev->dev,
4ff96fa6
FR		 1562 "DMA configuration failed.\n");
1563 }
1564 goto err_out_free_res_4;
1da177e4
LT		 1565 }
1566 }
1567
1568 pci_set_master(pdev);
1569
1570 /* ioremap MMIO region */
bcf0bf90 1571 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 1572 if (!ioaddr) {
b57b7e5a 1573 if (netif_msg_probe(tp))
9b91cf9d 1574 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1da177e4 1575 rc = -EIO;
4ff96fa6 1576 goto err_out_free_res_4;
1da177e4
LT		 1577 }
1578
1579 /* Unneeded ? Don't mess with Mrs. Murphy. */
1580 rtl8169_irq_mask_and_ack(ioaddr);
1581
1582 /* Soft reset the chip. */
1583 RTL_W8(ChipCmd, CmdReset);
1584
1585 /* Check that the chip has finished the reset. */
b518fa8e 1586 for (i = 100; i > 0; i--) {
1da177e4
LT		 1587 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1588 break;
b518fa8e 1589 msleep_interruptible(1);
1da177e4
LT		 1590 }
1591
1592 /* Identify chip attached to board */
1593 rtl8169_get_mac_version(tp, ioaddr);
1594 rtl8169_get_phy_version(tp, ioaddr);
1595
1596 rtl8169_print_mac_version(tp);
1597 rtl8169_print_phy_version(tp);
1598
1599 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) {
1600 if (tp->mac_version == rtl_chip_info[i].mac_version)
1601 break;
1602 }
1603 if (i < 0) {
1604 /* Unknown chip: assume array element #0, original RTL-8169 */
b57b7e5a 1605 if (netif_msg_probe(tp)) {
2e8a538d 1606 dev_printk(KERN_DEBUG, &pdev->dev,
4ff96fa6
FR		 1607 "unknown chip version, assuming %s\n",
1608 rtl_chip_info[0].name);
b57b7e5a 1609 }
1da177e4
LT		 1610 i++;
1611 }
1612 tp->chipset = i;
1613
5d06a99f
FR		 1614 RTL_W8(Cfg9346, Cfg9346_Unlock);
1615 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1616 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
1617 RTL_W8(Cfg9346, Cfg9346_Lock);
1618
1da177e4
LT		 1619 if (RTL_R8(PHYstatus) & TBI_Enable) {
1620 tp->set_speed = rtl8169_set_speed_tbi;
1621 tp->get_settings = rtl8169_gset_tbi;
1622 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1623 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1624 tp->link_ok = rtl8169_tbi_link_ok;
1625
64e4bfb4 1626 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1da177e4
LT		 1627 } else {
1628 tp->set_speed = rtl8169_set_speed_xmii;
1629 tp->get_settings = rtl8169_gset_xmii;
1630 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1631 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1632 tp->link_ok = rtl8169_xmii_link_ok;
5f787a1a
FR		 1633
1634 dev->do_ioctl = rtl8169_ioctl;
1da177e4
LT		 1635 }
1636
1637 /* Get MAC address. FIXME: read EEPROM */
1638 for (i = 0; i < MAC_ADDR_LEN; i++)
1639 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 1640 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 1641
1642 dev->open = rtl8169_open;
1643 dev->hard_start_xmit = rtl8169_start_xmit;
1644 dev->get_stats = rtl8169_get_stats;
1645 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1646 dev->stop = rtl8169_close;
1647 dev->tx_timeout = rtl8169_tx_timeout;
1648 dev->set_multicast_list = rtl8169_set_rx_mode;
1649 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1650 dev->irq = pdev->irq;
1651 dev->base_addr = (unsigned long) ioaddr;
1652 dev->change_mtu = rtl8169_change_mtu;
1653
1654#ifdef CONFIG_R8169_NAPI
1655 dev->poll = rtl8169_poll;
1656 dev->weight = R8169_NAPI_WEIGHT;
1da177e4
LT		 1657#endif
1658
1659#ifdef CONFIG_R8169_VLAN
1660 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1661 dev->vlan_rx_register = rtl8169_vlan_rx_register;
1662 dev->vlan_rx_kill_vid = rtl8169_vlan_rx_kill_vid;
1663#endif
1664
1665#ifdef CONFIG_NET_POLL_CONTROLLER
1666 dev->poll_controller = rtl8169_netpoll;
1667#endif
1668
1669 tp->intr_mask = 0xffff;
1670 tp->pci_dev = pdev;
1671 tp->mmio_addr = ioaddr;
bcf0bf90 1672 tp->align = rtl_cfg_info[ent->driver_data].align;
1da177e4
LT		 1673
1674 spin_lock_init(&tp->lock);
1675
1676 rc = register_netdev(dev);
4ff96fa6
FR		 1677 if (rc < 0)
1678 goto err_out_unmap_5;
1da177e4
LT		 1679
1680 pci_set_drvdata(pdev, dev);
1681
b57b7e5a
SH		 1682 if (netif_msg_probe(tp)) {
1683 printk(KERN_INFO "%s: %s at 0x%lx, "
1684 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1685 "IRQ %d\n",
1686 dev->name,
bcf0bf90 1687 rtl_chip_info[tp->chipset].name,
b57b7e5a
SH		 1688 dev->base_addr,
1689 dev->dev_addr[0], dev->dev_addr[1],
1690 dev->dev_addr[2], dev->dev_addr[3],
1691 dev->dev_addr[4], dev->dev_addr[5], dev->irq);
1692 }
1da177e4 1693
4ff96fa6 1694 rtl8169_init_phy(dev, tp);
1da177e4 1695
4ff96fa6
FR		 1696out:
1697 return rc;
1da177e4 1698
4ff96fa6
FR		 1699err_out_unmap_5:
1700 iounmap(ioaddr);
1701err_out_free_res_4:
1702 pci_release_regions(pdev);
1703err_out_mwi_3:
1704 pci_clear_mwi(pdev);
1705err_out_disable_2:
1706 pci_disable_device(pdev);
1707err_out_free_dev_1:
1708 free_netdev(dev);
1709 goto out;
1da177e4
LT		 1710}
1711
1712static void __devexit
1713rtl8169_remove_one(struct pci_dev *pdev)
1714{
1715 struct net_device *dev = pci_get_drvdata(pdev);
1716 struct rtl8169_private *tp = netdev_priv(dev);
1717
1718 assert(dev != NULL);
1719 assert(tp != NULL);
1720
1721 unregister_netdev(dev);
1722 rtl8169_release_board(pdev, dev, tp->mmio_addr);
1723 pci_set_drvdata(pdev, NULL);
1724}
1725
1da177e4
LT		 1726static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
1727 struct net_device *dev)
1728{
1729 unsigned int mtu = dev->mtu;
1730
1731 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1732}
1733
1734static int rtl8169_open(struct net_device *dev)
1735{
1736 struct rtl8169_private *tp = netdev_priv(dev);
1737 struct pci_dev *pdev = tp->pci_dev;
1738 int retval;
1739
1740 rtl8169_set_rxbufsize(tp, dev);
1741
1742 retval =
1fb9df5d 1743 request_irq(dev->irq, rtl8169_interrupt, IRQF_SHARED, dev->name, dev);
1da177e4
LT		 1744 if (retval < 0)
1745 goto out;
1746
1747 retval = -ENOMEM;
1748
1749 /*
1750 * Rx and Tx desscriptors needs 256 bytes alignment.
1751 * pci_alloc_consistent provides more.
1752 */
1753 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1754 &tp->TxPhyAddr);
1755 if (!tp->TxDescArray)
1756 goto err_free_irq;
1757
1758 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1759 &tp->RxPhyAddr);
1760 if (!tp->RxDescArray)
1761 goto err_free_tx;
1762
1763 retval = rtl8169_init_ring(dev);
1764 if (retval < 0)
1765 goto err_free_rx;
1766
1767 INIT_WORK(&tp->task, NULL, dev);
1768
1769 rtl8169_hw_start(dev);
1770
1771 rtl8169_request_timer(dev);
1772
1773 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1774out:
1775 return retval;
1776
1777err_free_rx:
1778 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1779 tp->RxPhyAddr);
1780err_free_tx:
1781 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1782 tp->TxPhyAddr);
1783err_free_irq:
1784 free_irq(dev->irq, dev);
1785 goto out;
1786}
1787
1788static void rtl8169_hw_reset(void __iomem *ioaddr)
1789{
1790 /* Disable interrupts */
1791 rtl8169_irq_mask_and_ack(ioaddr);
1792
1793 /* Reset the chipset */
1794 RTL_W8(ChipCmd, CmdReset);
1795
1796 /* PCI commit */
1797 RTL_R8(ChipCmd);
1798}
1799
1800static void
1801rtl8169_hw_start(struct net_device *dev)
1802{
1803 struct rtl8169_private *tp = netdev_priv(dev);
1804 void __iomem *ioaddr = tp->mmio_addr;
bcf0bf90 1805 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 1806 u32 i;
1807
1808 /* Soft reset the chip. */
1809 RTL_W8(ChipCmd, CmdReset);
1810
1811 /* Check that the chip has finished the reset. */
b518fa8e 1812 for (i = 100; i > 0; i--) {
1da177e4
LT		 1813 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1814 break;
b518fa8e 1815 msleep_interruptible(1);
1da177e4
LT		 1816 }
1817
bcf0bf90
FR		 1818 if (tp->mac_version == RTL_GIGA_MAC_VER_13) {
1819 pci_write_config_word(pdev, 0x68, 0x00);
1820 pci_write_config_word(pdev, 0x69, 0x08);
1821 }
1822
1823 /* Undocumented stuff. */
1824 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
1825 u16 cmd;
1826
1827 /* Realtek's r1000_n.c driver uses '&& 0x01' here. Well... */
1828 if ((RTL_R8(Config2) & 0x07) & 0x01)
1829 RTL_W32(0x7c, 0x0007ffff);
1830
1831 RTL_W32(0x7c, 0x0007ff00);
1832
1833 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
1834 cmd = cmd & 0xef;
1835 pci_write_config_word(pdev, PCI_COMMAND, cmd);
1da177e4
LT		 1836 }
1837
bcf0bf90 1838
1da177e4 1839 RTL_W8(Cfg9346, Cfg9346_Unlock);
1da177e4
LT		 1840 RTL_W8(EarlyTxThres, EarlyTxThld);
1841
126fa4b9
FR		 1842 /* Low hurts. Let's disable the filtering. */
1843 RTL_W16(RxMaxSize, 16383);
1da177e4
LT		 1844
1845 /* Set Rx Config register */
1846 i = rtl8169_rx_config |
1847 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1848 RTL_W32(RxConfig, i);
1849
1850 /* Set DMA burst size and Interframe Gap Time */
5b0384f4
FR		 1851 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
1852 (InterFrameGap << TxInterFrameGapShift));
1da177e4 1853
bcf0bf90 1854 tp->cp_cmd |= RTL_R16(CPlusCmd) | PCIMulRW;
1da177e4 1855
bcf0bf90
FR		 1856 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1857 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1da177e4
LT		 1858 dprintk(KERN_INFO PFX "Set MAC Reg C+CR Offset 0xE0. "
1859 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 1860 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 1861 }
1862
bcf0bf90
FR		 1863 RTL_W16(CPlusCmd, tp->cp_cmd);
1864
1da177e4
LT		 1865 /*
1866 * Undocumented corner. Supposedly:
1867 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
1868 */
1869 RTL_W16(IntrMitigate, 0x0000);
1870
b39fe41f
FR		 1871 /*
1872 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
1873 * register to be written before TxDescAddrLow to work.
1874 * Switching from MMIO to I/O access fixes the issue as well.
1875 */
1da177e4 1876 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr >> 32));
b39fe41f 1877 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr & DMA_32BIT_MASK));
1da177e4 1878 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr >> 32));
b39fe41f 1879 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr & DMA_32BIT_MASK));
bcf0bf90 1880 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1da177e4 1881 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 1882
1883 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
1884 RTL_R8(IntrMask);
1da177e4
LT		 1885
1886 RTL_W32(RxMissed, 0);
1887
1888 rtl8169_set_rx_mode(dev);
1889
1890 /* no early-rx interrupts */
1891 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
1892
1893 /* Enable all known interrupts by setting the interrupt mask. */
1894 RTL_W16(IntrMask, rtl8169_intr_mask);
1895
1896 netif_start_queue(dev);
1897}
1898
1899static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
1900{
1901 struct rtl8169_private *tp = netdev_priv(dev);
1902 int ret = 0;
1903
1904 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
1905 return -EINVAL;
1906
1907 dev->mtu = new_mtu;
1908
1909 if (!netif_running(dev))
1910 goto out;
1911
1912 rtl8169_down(dev);
1913
1914 rtl8169_set_rxbufsize(tp, dev);
1915
1916 ret = rtl8169_init_ring(dev);
1917 if (ret < 0)
1918 goto out;
1919
1920 netif_poll_enable(dev);
1921
1922 rtl8169_hw_start(dev);
1923
1924 rtl8169_request_timer(dev);
1925
1926out:
1927 return ret;
1928}
1929
1930static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
1931{
1932 desc->addr = 0x0badbadbadbadbadull;
1933 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
1934}
1935
1936static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
1937 struct sk_buff **sk_buff, struct RxDesc *desc)
1938{
1939 struct pci_dev *pdev = tp->pci_dev;
1940
1941 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
1942 PCI_DMA_FROMDEVICE);
1943 dev_kfree_skb(*sk_buff);
1944 *sk_buff = NULL;
1945 rtl8169_make_unusable_by_asic(desc);
1946}
1947
1948static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
1949{
1950 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
1951
1952 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
1953}
1954
1955static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
1956 u32 rx_buf_sz)
1957{
1958 desc->addr = cpu_to_le64(mapping);
1959 wmb();
1960 rtl8169_mark_to_asic(desc, rx_buf_sz);
1961}
1962
1963static int rtl8169_alloc_rx_skb(struct pci_dev *pdev, struct sk_buff **sk_buff,
bcf0bf90
FR		 1964 struct RxDesc *desc, int rx_buf_sz,
1965 unsigned int align)
1da177e4
LT		 1966{
1967 struct sk_buff *skb;
1968 dma_addr_t mapping;
1969 int ret = 0;
1970
bcf0bf90 1971 skb = dev_alloc_skb(rx_buf_sz + align);
1da177e4
LT		 1972 if (!skb)
1973 goto err_out;
1974
bcf0bf90 1975 skb_reserve(skb, align);
1da177e4
LT		 1976 *sk_buff = skb;
1977
689be439 1978 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
1da177e4
LT		 1979 PCI_DMA_FROMDEVICE);
1980
1981 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
1982
1983out:
1984 return ret;
1985
1986err_out:
1987 ret = -ENOMEM;
1988 rtl8169_make_unusable_by_asic(desc);
1989 goto out;
1990}
1991
1992static void rtl8169_rx_clear(struct rtl8169_private *tp)
1993{
1994 int i;
1995
1996 for (i = 0; i < NUM_RX_DESC; i++) {
1997 if (tp->Rx_skbuff[i]) {
1998 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
1999 tp->RxDescArray + i);
2000 }
2001 }
2002}
2003
2004static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2005 u32 start, u32 end)
2006{
2007 u32 cur;
5b0384f4 2008
1da177e4
LT		 2009 for (cur = start; end - cur > 0; cur++) {
2010 int ret, i = cur % NUM_RX_DESC;
2011
2012 if (tp->Rx_skbuff[i])
2013 continue;
bcf0bf90 2014
1da177e4 2015 ret = rtl8169_alloc_rx_skb(tp->pci_dev, tp->Rx_skbuff + i,
bcf0bf90 2016 tp->RxDescArray + i, tp->rx_buf_sz, tp->align);
1da177e4
LT		 2017 if (ret < 0)
2018 break;
2019 }
2020 return cur - start;
2021}
2022
2023static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2024{
2025 desc->opts1 |= cpu_to_le32(RingEnd);
2026}
2027
2028static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2029{
2030 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2031}
2032
2033static int rtl8169_init_ring(struct net_device *dev)
2034{
2035 struct rtl8169_private *tp = netdev_priv(dev);
2036
2037 rtl8169_init_ring_indexes(tp);
2038
2039 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2040 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2041
2042 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2043 goto err_out;
2044
2045 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2046
2047 return 0;
2048
2049err_out:
2050 rtl8169_rx_clear(tp);
2051 return -ENOMEM;
2052}
2053
2054static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2055 struct TxDesc *desc)
2056{
2057 unsigned int len = tx_skb->len;
2058
2059 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2060 desc->opts1 = 0x00;
2061 desc->opts2 = 0x00;
2062 desc->addr = 0x00;
2063 tx_skb->len = 0;
2064}
2065
2066static void rtl8169_tx_clear(struct rtl8169_private *tp)
2067{
2068 unsigned int i;
2069
2070 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2071 unsigned int entry = i % NUM_TX_DESC;
2072 struct ring_info *tx_skb = tp->tx_skb + entry;
2073 unsigned int len = tx_skb->len;
2074
2075 if (len) {
2076 struct sk_buff *skb = tx_skb->skb;
2077
2078 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2079 tp->TxDescArray + entry);
2080 if (skb) {
2081 dev_kfree_skb(skb);
2082 tx_skb->skb = NULL;
2083 }
2084 tp->stats.tx_dropped++;
2085 }
2086 }
2087 tp->cur_tx = tp->dirty_tx = 0;
2088}
2089
2090static void rtl8169_schedule_work(struct net_device *dev, void (*task)(void *))
2091{
2092 struct rtl8169_private *tp = netdev_priv(dev);
2093
2094 PREPARE_WORK(&tp->task, task, dev);
2095 schedule_delayed_work(&tp->task, 4);
2096}
2097
2098static void rtl8169_wait_for_quiescence(struct net_device *dev)
2099{
2100 struct rtl8169_private *tp = netdev_priv(dev);
2101 void __iomem *ioaddr = tp->mmio_addr;
2102
2103 synchronize_irq(dev->irq);
2104
2105 /* Wait for any pending NAPI task to complete */
2106 netif_poll_disable(dev);
2107
2108 rtl8169_irq_mask_and_ack(ioaddr);
2109
2110 netif_poll_enable(dev);
2111}
2112
2113static void rtl8169_reinit_task(void *_data)
2114{
2115 struct net_device *dev = _data;
2116 int ret;
2117
2118 if (netif_running(dev)) {
2119 rtl8169_wait_for_quiescence(dev);
2120 rtl8169_close(dev);
2121 }
2122
2123 ret = rtl8169_open(dev);
2124 if (unlikely(ret < 0)) {
2125 if (net_ratelimit()) {
b57b7e5a
SH		 2126 struct rtl8169_private *tp = netdev_priv(dev);
2127
2128 if (netif_msg_drv(tp)) {
2129 printk(PFX KERN_ERR
2130 "%s: reinit failure (status = %d)."
2131 " Rescheduling.\n", dev->name, ret);
2132 }
1da177e4
LT		 2133 }
2134 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2135 }
2136}
2137
2138static void rtl8169_reset_task(void *_data)
2139{
2140 struct net_device *dev = _data;
2141 struct rtl8169_private *tp = netdev_priv(dev);
2142
2143 if (!netif_running(dev))
2144 return;
2145
2146 rtl8169_wait_for_quiescence(dev);
2147
2148 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr);
2149 rtl8169_tx_clear(tp);
2150
2151 if (tp->dirty_rx == tp->cur_rx) {
2152 rtl8169_init_ring_indexes(tp);
2153 rtl8169_hw_start(dev);
2154 netif_wake_queue(dev);
2155 } else {
2156 if (net_ratelimit()) {
b57b7e5a
SH		 2157 struct rtl8169_private *tp = netdev_priv(dev);
2158
2159 if (netif_msg_intr(tp)) {
2160 printk(PFX KERN_EMERG
2161 "%s: Rx buffers shortage\n", dev->name);
2162 }
1da177e4
LT		 2163 }
2164 rtl8169_schedule_work(dev, rtl8169_reset_task);
2165 }
2166}
2167
2168static void rtl8169_tx_timeout(struct net_device *dev)
2169{
2170 struct rtl8169_private *tp = netdev_priv(dev);
2171
2172 rtl8169_hw_reset(tp->mmio_addr);
2173
2174 /* Let's wait a bit while any (async) irq lands on */
2175 rtl8169_schedule_work(dev, rtl8169_reset_task);
2176}
2177
2178static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2179 u32 opts1)
2180{
2181 struct skb_shared_info *info = skb_shinfo(skb);
2182 unsigned int cur_frag, entry;
2183 struct TxDesc *txd;
2184
2185 entry = tp->cur_tx;
2186 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2187 skb_frag_t *frag = info->frags + cur_frag;
2188 dma_addr_t mapping;
2189 u32 status, len;
2190 void *addr;
2191
2192 entry = (entry + 1) % NUM_TX_DESC;
2193
2194 txd = tp->TxDescArray + entry;
2195 len = frag->size;
2196 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2197 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2198
2199 /* anti gcc 2.95.3 bugware (sic) */
2200 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2201
2202 txd->opts1 = cpu_to_le32(status);
2203 txd->addr = cpu_to_le64(mapping);
2204
2205 tp->tx_skb[entry].len = len;
2206 }
2207
2208 if (cur_frag) {
2209 tp->tx_skb[entry].skb = skb;
2210 txd->opts1 |= cpu_to_le32(LastFrag);
2211 }
2212
2213 return cur_frag;
2214}
2215
2216static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2217{
2218 if (dev->features & NETIF_F_TSO) {
7967168c 2219 u32 mss = skb_shinfo(skb)->gso_size;
1da177e4
LT		 2220
2221 if (mss)
2222 return LargeSend | ((mss & MSSMask) << MSSShift);
2223 }
84fa7933 2224 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1da177e4
LT		 2225 const struct iphdr *ip = skb->nh.iph;
2226
2227 if (ip->protocol == IPPROTO_TCP)
2228 return IPCS | TCPCS;
2229 else if (ip->protocol == IPPROTO_UDP)
2230 return IPCS | UDPCS;
2231 WARN_ON(1); /* we need a WARN() */
2232 }
2233 return 0;
2234}
2235
2236static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2237{
2238 struct rtl8169_private *tp = netdev_priv(dev);
2239 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2240 struct TxDesc *txd = tp->TxDescArray + entry;
2241 void __iomem *ioaddr = tp->mmio_addr;
2242 dma_addr_t mapping;
2243 u32 status, len;
2244 u32 opts1;
188f4af0 2245 int ret = NETDEV_TX_OK;
5b0384f4 2246
1da177e4 2247 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
b57b7e5a
SH		 2248 if (netif_msg_drv(tp)) {
2249 printk(KERN_ERR
2250 "%s: BUG! Tx Ring full when queue awake!\n",
2251 dev->name);
2252 }
1da177e4
LT		 2253 goto err_stop;
2254 }
2255
2256 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2257 goto err_stop;
2258
2259 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2260
2261 frags = rtl8169_xmit_frags(tp, skb, opts1);
2262 if (frags) {
2263 len = skb_headlen(skb);
2264 opts1 |= FirstFrag;
2265 } else {
2266 len = skb->len;
2267
2268 if (unlikely(len < ETH_ZLEN)) {
5b057c6b 2269 if (skb_padto(skb, ETH_ZLEN))
1da177e4
LT		 2270 goto err_update_stats;
2271 len = ETH_ZLEN;
2272 }
2273
2274 opts1 |= FirstFrag | LastFrag;
2275 tp->tx_skb[entry].skb = skb;
2276 }
2277
2278 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2279
2280 tp->tx_skb[entry].len = len;
2281 txd->addr = cpu_to_le64(mapping);
2282 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2283
2284 wmb();
2285
2286 /* anti gcc 2.95.3 bugware (sic) */
2287 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2288 txd->opts1 = cpu_to_le32(status);
2289
2290 dev->trans_start = jiffies;
2291
2292 tp->cur_tx += frags + 1;
2293
2294 smp_wmb();
2295
2296 RTL_W8(TxPoll, 0x40); /* set polling bit */
2297
2298 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2299 netif_stop_queue(dev);
2300 smp_rmb();
2301 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2302 netif_wake_queue(dev);
2303 }
2304
2305out:
2306 return ret;
2307
2308err_stop:
2309 netif_stop_queue(dev);
188f4af0 2310 ret = NETDEV_TX_BUSY;
1da177e4
LT		 2311err_update_stats:
2312 tp->stats.tx_dropped++;
2313 goto out;
2314}
2315
2316static void rtl8169_pcierr_interrupt(struct net_device *dev)
2317{
2318 struct rtl8169_private *tp = netdev_priv(dev);
2319 struct pci_dev *pdev = tp->pci_dev;
2320 void __iomem *ioaddr = tp->mmio_addr;
2321 u16 pci_status, pci_cmd;
2322
2323 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2324 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2325
b57b7e5a
SH		 2326 if (netif_msg_intr(tp)) {
2327 printk(KERN_ERR
2328 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2329 dev->name, pci_cmd, pci_status);
2330 }
1da177e4
LT		 2331
2332 /*
2333 * The recovery sequence below admits a very elaborated explanation:
2334 * - it seems to work;
2335 * - I did not see what else could be done.
2336 *
2337 * Feel free to adjust to your needs.
2338 */
2339 pci_write_config_word(pdev, PCI_COMMAND,
2340 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
2341
2342 pci_write_config_word(pdev, PCI_STATUS,
2343 pci_status & (PCI_STATUS_DETECTED_PARITY |
2344 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2345 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2346
2347 /* The infamous DAC f*ckup only happens at boot time */
2348 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
b57b7e5a
SH		 2349 if (netif_msg_intr(tp))
2350 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
1da177e4
LT		 2351 tp->cp_cmd &= ~PCIDAC;
2352 RTL_W16(CPlusCmd, tp->cp_cmd);
2353 dev->features &= ~NETIF_F_HIGHDMA;
2354 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2355 }
2356
2357 rtl8169_hw_reset(ioaddr);
2358}
2359
2360static void
2361rtl8169_tx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
2362 void __iomem *ioaddr)
2363{
2364 unsigned int dirty_tx, tx_left;
2365
2366 assert(dev != NULL);
2367 assert(tp != NULL);
2368 assert(ioaddr != NULL);
2369
2370 dirty_tx = tp->dirty_tx;
2371 smp_rmb();
2372 tx_left = tp->cur_tx - dirty_tx;
2373
2374 while (tx_left > 0) {
2375 unsigned int entry = dirty_tx % NUM_TX_DESC;
2376 struct ring_info *tx_skb = tp->tx_skb + entry;
2377 u32 len = tx_skb->len;
2378 u32 status;
2379
2380 rmb();
2381 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2382 if (status & DescOwn)
2383 break;
2384
2385 tp->stats.tx_bytes += len;
2386 tp->stats.tx_packets++;
2387
2388 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2389
2390 if (status & LastFrag) {
2391 dev_kfree_skb_irq(tx_skb->skb);
2392 tx_skb->skb = NULL;
2393 }
2394 dirty_tx++;
2395 tx_left--;
2396 }
2397
2398 if (tp->dirty_tx != dirty_tx) {
2399 tp->dirty_tx = dirty_tx;
2400 smp_wmb();
2401 if (netif_queue_stopped(dev) &&
2402 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2403 netif_wake_queue(dev);
2404 }
2405 }
2406}
2407
126fa4b9
FR		 2408static inline int rtl8169_fragmented_frame(u32 status)
2409{
2410 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2411}
2412
1da177e4
LT		 2413static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2414{
2415 u32 opts1 = le32_to_cpu(desc->opts1);
2416 u32 status = opts1 & RxProtoMask;
2417
2418 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2419 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2420 ((status == RxProtoIP) && !(opts1 & IPFail)))
2421 skb->ip_summed = CHECKSUM_UNNECESSARY;
2422 else
2423 skb->ip_summed = CHECKSUM_NONE;
2424}
2425
2426static inline int rtl8169_try_rx_copy(struct sk_buff **sk_buff, int pkt_size,
bcf0bf90
FR		 2427 struct RxDesc *desc, int rx_buf_sz,
2428 unsigned int align)
1da177e4
LT		 2429{
2430 int ret = -1;
2431
2432 if (pkt_size < rx_copybreak) {
2433 struct sk_buff *skb;
2434
bcf0bf90 2435 skb = dev_alloc_skb(pkt_size + align);
1da177e4 2436 if (skb) {
bcf0bf90 2437 skb_reserve(skb, align);
689be439 2438 eth_copy_and_sum(skb, sk_buff[0]->data, pkt_size, 0);
1da177e4
LT		 2439 *sk_buff = skb;
2440 rtl8169_mark_to_asic(desc, rx_buf_sz);
2441 ret = 0;
2442 }
2443 }
2444 return ret;
2445}
2446
2447static int
2448rtl8169_rx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
2449 void __iomem *ioaddr)
2450{
2451 unsigned int cur_rx, rx_left;
2452 unsigned int delta, count;
2453
2454 assert(dev != NULL);
2455 assert(tp != NULL);
2456 assert(ioaddr != NULL);
2457
2458 cur_rx = tp->cur_rx;
2459 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
2460 rx_left = rtl8169_rx_quota(rx_left, (u32) dev->quota);
2461
4dcb7d33 2462 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 2463 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 2464 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 2465 u32 status;
2466
2467 rmb();
126fa4b9 2468 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 2469
2470 if (status & DescOwn)
2471 break;
4dcb7d33 2472 if (unlikely(status & RxRES)) {
b57b7e5a
SH		 2473 if (netif_msg_rx_err(tp)) {
2474 printk(KERN_INFO
2475 "%s: Rx ERROR. status = %08x\n",
2476 dev->name, status);
2477 }
1da177e4
LT		 2478 tp->stats.rx_errors++;
2479 if (status & (RxRWT | RxRUNT))
2480 tp->stats.rx_length_errors++;
2481 if (status & RxCRC)
2482 tp->stats.rx_crc_errors++;
9dccf611
FR		 2483 if (status & RxFOVF) {
2484 rtl8169_schedule_work(dev, rtl8169_reset_task);
2485 tp->stats.rx_fifo_errors++;
2486 }
126fa4b9 2487 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
1da177e4 2488 } else {
1da177e4
LT		 2489 struct sk_buff *skb = tp->Rx_skbuff[entry];
2490 int pkt_size = (status & 0x00001FFF) - 4;
2491 void (*pci_action)(struct pci_dev *, dma_addr_t,
2492 size_t, int) = pci_dma_sync_single_for_device;
2493
126fa4b9
FR		 2494 /*
2495 * The driver does not support incoming fragmented
2496 * frames. They are seen as a symptom of over-mtu
2497 * sized frames.
2498 */
2499 if (unlikely(rtl8169_fragmented_frame(status))) {
2500 tp->stats.rx_dropped++;
2501 tp->stats.rx_length_errors++;
2502 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4dcb7d33 2503 continue;
126fa4b9
FR		 2504 }
2505
1da177e4 2506 rtl8169_rx_csum(skb, desc);
bcf0bf90 2507
1da177e4
LT		 2508 pci_dma_sync_single_for_cpu(tp->pci_dev,
2509 le64_to_cpu(desc->addr), tp->rx_buf_sz,
2510 PCI_DMA_FROMDEVICE);
2511
2512 if (rtl8169_try_rx_copy(&skb, pkt_size, desc,
bcf0bf90 2513 tp->rx_buf_sz, tp->align)) {
1da177e4
LT		 2514 pci_action = pci_unmap_single;
2515 tp->Rx_skbuff[entry] = NULL;
2516 }
2517
2518 pci_action(tp->pci_dev, le64_to_cpu(desc->addr),
2519 tp->rx_buf_sz, PCI_DMA_FROMDEVICE);
2520
2521 skb->dev = dev;
2522 skb_put(skb, pkt_size);
2523 skb->protocol = eth_type_trans(skb, dev);
2524
2525 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
2526 rtl8169_rx_skb(skb);
2527
2528 dev->last_rx = jiffies;
2529 tp->stats.rx_bytes += pkt_size;
2530 tp->stats.rx_packets++;
2531 }
1da177e4
LT		 2532 }
2533
2534 count = cur_rx - tp->cur_rx;
2535 tp->cur_rx = cur_rx;
2536
2537 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
b57b7e5a 2538 if (!delta && count && netif_msg_intr(tp))
1da177e4
LT		 2539 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
2540 tp->dirty_rx += delta;
2541
2542 /*
2543 * FIXME: until there is periodic timer to try and refill the ring,
2544 * a temporary shortage may definitely kill the Rx process.
2545 * - disable the asic to try and avoid an overflow and kick it again
2546 * after refill ?
2547 * - how do others driver handle this condition (Uh oh...).
2548 */
b57b7e5a 2549 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
1da177e4
LT		 2550 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
2551
2552 return count;
2553}
2554
2555/* The interrupt handler does all of the Rx thread work and cleans up after the Tx thread. */
2556static irqreturn_t
7d12e780 2557rtl8169_interrupt(int irq, void *dev_instance)
1da177e4
LT		 2558{
2559 struct net_device *dev = (struct net_device *) dev_instance;
2560 struct rtl8169_private *tp = netdev_priv(dev);
2561 int boguscnt = max_interrupt_work;
2562 void __iomem *ioaddr = tp->mmio_addr;
2563 int status;
2564 int handled = 0;
2565
2566 do {
2567 status = RTL_R16(IntrStatus);
2568
2569 /* hotplug/major error/no more work/shared irq */
2570 if ((status == 0xFFFF) || !status)
2571 break;
2572
2573 handled = 1;
2574
2575 if (unlikely(!netif_running(dev))) {
2576 rtl8169_asic_down(ioaddr);
2577 goto out;
2578 }
2579
2580 status &= tp->intr_mask;
2581 RTL_W16(IntrStatus,
2582 (status & RxFIFOOver) ? (status | RxOverflow) : status);
2583
2584 if (!(status & rtl8169_intr_mask))
2585 break;
2586
2587 if (unlikely(status & SYSErr)) {
2588 rtl8169_pcierr_interrupt(dev);
2589 break;
2590 }
2591
2592 if (status & LinkChg)
2593 rtl8169_check_link_status(dev, tp, ioaddr);
2594
2595#ifdef CONFIG_R8169_NAPI
2596 RTL_W16(IntrMask, rtl8169_intr_mask & ~rtl8169_napi_event);
2597 tp->intr_mask = ~rtl8169_napi_event;
2598
2599 if (likely(netif_rx_schedule_prep(dev)))
2600 __netif_rx_schedule(dev);
b57b7e5a 2601 else if (netif_msg_intr(tp)) {
1da177e4 2602 printk(KERN_INFO "%s: interrupt %04x taken in poll\n",
5b0384f4 2603 dev->name, status);
1da177e4
LT		 2604 }
2605 break;
2606#else
2607 /* Rx interrupt */
2608 if (status & (RxOK | RxOverflow | RxFIFOOver)) {
2609 rtl8169_rx_interrupt(dev, tp, ioaddr);
2610 }
2611 /* Tx interrupt */
2612 if (status & (TxOK | TxErr))
2613 rtl8169_tx_interrupt(dev, tp, ioaddr);
2614#endif
2615
2616 boguscnt--;
2617 } while (boguscnt > 0);
2618
2619 if (boguscnt <= 0) {
7c8b2eb4 2620 if (netif_msg_intr(tp) && net_ratelimit() ) {
b57b7e5a
SH		 2621 printk(KERN_WARNING
2622 "%s: Too much work at interrupt!\n", dev->name);
2623 }
1da177e4
LT		 2624 /* Clear all interrupt sources. */
2625 RTL_W16(IntrStatus, 0xffff);
2626 }
2627out:
2628 return IRQ_RETVAL(handled);
2629}
2630
2631#ifdef CONFIG_R8169_NAPI
2632static int rtl8169_poll(struct net_device *dev, int *budget)
2633{
2634 unsigned int work_done, work_to_do = min(*budget, dev->quota);
2635 struct rtl8169_private *tp = netdev_priv(dev);
2636 void __iomem *ioaddr = tp->mmio_addr;
2637
2638 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr);
2639 rtl8169_tx_interrupt(dev, tp, ioaddr);
2640
2641 *budget -= work_done;
2642 dev->quota -= work_done;
2643
2644 if (work_done < work_to_do) {
2645 netif_rx_complete(dev);
2646 tp->intr_mask = 0xffff;
2647 /*
2648 * 20040426: the barrier is not strictly required but the
2649 * behavior of the irq handler could be less predictable
2650 * without it. Btw, the lack of flush for the posted pci
2651 * write is safe - FR
2652 */
2653 smp_wmb();
2654 RTL_W16(IntrMask, rtl8169_intr_mask);
2655 }
2656
2657 return (work_done >= work_to_do);
2658}
2659#endif
2660
2661static void rtl8169_down(struct net_device *dev)
2662{
2663 struct rtl8169_private *tp = netdev_priv(dev);
2664 void __iomem *ioaddr = tp->mmio_addr;
2665 unsigned int poll_locked = 0;
733b736c 2666 unsigned int intrmask;
1da177e4
LT		 2667
2668 rtl8169_delete_timer(dev);
2669
2670 netif_stop_queue(dev);
2671
2672 flush_scheduled_work();
2673
2674core_down:
2675 spin_lock_irq(&tp->lock);
2676
2677 rtl8169_asic_down(ioaddr);
2678
2679 /* Update the error counts. */
2680 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2681 RTL_W32(RxMissed, 0);
2682
2683 spin_unlock_irq(&tp->lock);
2684
2685 synchronize_irq(dev->irq);
2686
2687 if (!poll_locked) {
2688 netif_poll_disable(dev);
2689 poll_locked++;
2690 }
2691
2692 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 2693 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4
LT		 2694
2695 /*
2696 * And now for the 50k$ question: are IRQ disabled or not ?
2697 *
2698 * Two paths lead here:
2699 * 1) dev->close
2700 * -> netif_running() is available to sync the current code and the
2701 * IRQ handler. See rtl8169_interrupt for details.
2702 * 2) dev->change_mtu
2703 * -> rtl8169_poll can not be issued again and re-enable the
2704 * interruptions. Let's simply issue the IRQ down sequence again.
733b736c
AP		 2705 *
2706 * No loop if hotpluged or major error (0xffff).
1da177e4 2707 */
733b736c
AP		 2708 intrmask = RTL_R16(IntrMask);
2709 if (intrmask && (intrmask != 0xffff))
1da177e4
LT		 2710 goto core_down;
2711
2712 rtl8169_tx_clear(tp);
2713
2714 rtl8169_rx_clear(tp);
2715}
2716
2717static int rtl8169_close(struct net_device *dev)
2718{
2719 struct rtl8169_private *tp = netdev_priv(dev);
2720 struct pci_dev *pdev = tp->pci_dev;
2721
2722 rtl8169_down(dev);
2723
2724 free_irq(dev->irq, dev);
2725
2726 netif_poll_enable(dev);
2727
2728 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2729 tp->RxPhyAddr);
2730 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2731 tp->TxPhyAddr);
2732 tp->TxDescArray = NULL;
2733 tp->RxDescArray = NULL;
2734
2735 return 0;
2736}
2737
2738static void
2739rtl8169_set_rx_mode(struct net_device *dev)
2740{
2741 struct rtl8169_private *tp = netdev_priv(dev);
2742 void __iomem *ioaddr = tp->mmio_addr;
2743 unsigned long flags;
2744 u32 mc_filter[2]; /* Multicast hash filter */
2745 int i, rx_mode;
2746 u32 tmp = 0;
2747
2748 if (dev->flags & IFF_PROMISC) {
2749 /* Unconditionally log net taps. */
b57b7e5a
SH		 2750 if (netif_msg_link(tp)) {
2751 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2752 dev->name);
2753 }
1da177e4
LT		 2754 rx_mode =
2755 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2756 AcceptAllPhys;
2757 mc_filter[1] = mc_filter[0] = 0xffffffff;
2758 } else if ((dev->mc_count > multicast_filter_limit)
2759 || (dev->flags & IFF_ALLMULTI)) {
2760 /* Too many to filter perfectly -- accept all multicasts. */
2761 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2762 mc_filter[1] = mc_filter[0] = 0xffffffff;
2763 } else {
2764 struct dev_mc_list *mclist;
2765 rx_mode = AcceptBroadcast | AcceptMyPhys;
2766 mc_filter[1] = mc_filter[0] = 0;
2767 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2768 i++, mclist = mclist->next) {
2769 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2770 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2771 rx_mode |= AcceptMulticast;
2772 }
2773 }
2774
2775 spin_lock_irqsave(&tp->lock, flags);
2776
2777 tmp = rtl8169_rx_config | rx_mode |
2778 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2779
bcf0bf90
FR		 2780 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
2781 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
2782 (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2783 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
2784 (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
2785 mc_filter[0] = 0xffffffff;
2786 mc_filter[1] = 0xffffffff;
2787 }
2788
1da177e4
LT		 2789 RTL_W32(RxConfig, tmp);
2790 RTL_W32(MAR0 + 0, mc_filter[0]);
2791 RTL_W32(MAR0 + 4, mc_filter[1]);
2792
2793 spin_unlock_irqrestore(&tp->lock, flags);
2794}
2795
2796/**
2797 * rtl8169_get_stats - Get rtl8169 read/write statistics
2798 * @dev: The Ethernet Device to get statistics for
2799 *
2800 * Get TX/RX statistics for rtl8169
2801 */
2802static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
2803{
2804 struct rtl8169_private *tp = netdev_priv(dev);
2805 void __iomem *ioaddr = tp->mmio_addr;
2806 unsigned long flags;
2807
2808 if (netif_running(dev)) {
2809 spin_lock_irqsave(&tp->lock, flags);
2810 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2811 RTL_W32(RxMissed, 0);
2812 spin_unlock_irqrestore(&tp->lock, flags);
2813 }
5b0384f4 2814
1da177e4
LT		 2815 return &tp->stats;
2816}
2817
5d06a99f
FR		 2818#ifdef CONFIG_PM
2819
2820static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
2821{
2822 struct net_device *dev = pci_get_drvdata(pdev);
2823 struct rtl8169_private *tp = netdev_priv(dev);
2824 void __iomem *ioaddr = tp->mmio_addr;
2825
2826 if (!netif_running(dev))
2827 goto out;
2828
2829 netif_device_detach(dev);
2830 netif_stop_queue(dev);
2831
2832 spin_lock_irq(&tp->lock);
2833
2834 rtl8169_asic_down(ioaddr);
2835
2836 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2837 RTL_W32(RxMissed, 0);
2838
2839 spin_unlock_irq(&tp->lock);
2840
2841 pci_save_state(pdev);
61a4dcc2 2842 pci_enable_wake(pdev, pci_choose_state(pdev, state), tp->wol_enabled);
5d06a99f
FR		 2843 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2844out:
2845 return 0;
2846}
2847
2848static int rtl8169_resume(struct pci_dev *pdev)
2849{
2850 struct net_device *dev = pci_get_drvdata(pdev);
2851
2852 if (!netif_running(dev))
2853 goto out;
2854
2855 netif_device_attach(dev);
2856
2857 pci_set_power_state(pdev, PCI_D0);
2858 pci_restore_state(pdev);
61a4dcc2 2859 pci_enable_wake(pdev, PCI_D0, 0);
5d06a99f
FR		 2860
2861 rtl8169_schedule_work(dev, rtl8169_reset_task);
2862out:
2863 return 0;
2864}
2865
2866#endif /* CONFIG_PM */
2867
1da177e4
LT		 2868static struct pci_driver rtl8169_pci_driver = {
2869 .name = MODULENAME,
2870 .id_table = rtl8169_pci_tbl,
2871 .probe = rtl8169_init_one,
2872 .remove = __devexit_p(rtl8169_remove_one),
2873#ifdef CONFIG_PM
2874 .suspend = rtl8169_suspend,
2875 .resume = rtl8169_resume,
2876#endif
2877};
2878
2879static int __init
2880rtl8169_init_module(void)
2881{
29917620 2882 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 2883}
2884
2885static void __exit
2886rtl8169_cleanup_module(void)
2887{
2888 pci_unregister_driver(&rtl8169_pci_driver);
2889}
2890
2891module_init(rtl8169_init_module);
2892module_exit(rtl8169_cleanup_module);
Linux 6.x block layer and io_uring tree(s)