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r8169: magic.
[linux-2.6-block.git] / drivers / net / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
25#include <linux/dma-mapping.h>
e1759441 26#include <linux/pm_runtime.h>
bca03d5f 27#include <linux/firmware.h>
1da177e4 28
99f252b0 29#include <asm/system.h>
1da177e4
LT		 30#include <asm/io.h>
31#include <asm/irq.h>
32
865c652d 33#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 34#define MODULENAME "r8169"
35#define PFX MODULENAME ": "
36
bca03d5f 37#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
38#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
39
1da177e4
LT		 40#ifdef RTL8169_DEBUG
41#define assert(expr) \
5b0384f4
FR		 42 if (!(expr)) { \
43 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 44 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 45 }
06fa7358
JP		 46#define dprintk(fmt, args...) \
47 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 48#else
49#define assert(expr) do {} while (0)
50#define dprintk(fmt, args...) do {} while (0)
51#endif /* RTL8169_DEBUG */
52
b57b7e5a 53#define R8169_MSG_DEFAULT \
f0e837d9 54 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 55
1da177e4
LT		 56#define TX_BUFFS_AVAIL(tp) \
57 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
58
1da177e4
LT		 59/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
60 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 61static const int multicast_filter_limit = 32;
1da177e4
LT		 62
63/* MAC address length */
64#define MAC_ADDR_LEN 6
65
9c14ceaf 66#define MAX_READ_REQUEST_SHIFT 12
1da177e4
LT		 67#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
68#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
69#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
1da177e4
LT		 70#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
71#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
72
73#define R8169_REGS_SIZE 256
74#define R8169_NAPI_WEIGHT 64
75#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
76#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
77#define RX_BUF_SIZE 1536 /* Rx Buffer size */
78#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
79#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
80
81#define RTL8169_TX_TIMEOUT (6*HZ)
82#define RTL8169_PHY_TIMEOUT (10*HZ)
83
ea8dbdd1 84#define RTL_EEPROM_SIG cpu_to_le32(0x8129)
85#define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
e1564ec9
FR		 86#define RTL_EEPROM_SIG_ADDR 0x0000
87
1da177e4
LT		 88/* write/read MMIO register */
89#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
90#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
91#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
92#define RTL_R8(reg) readb (ioaddr + (reg))
93#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 94#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 95
96enum mac_version {
f21b75e9 97 RTL_GIGA_MAC_NONE = 0x00,
ba6eb6ee
FR		 98 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
99 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
100 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
101 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
102 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
6dccd16b 103 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
2857ffb7
FR		 104 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
105 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
106 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
107 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
2dd99530 108 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
e3cf0cc0
FR		 109 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
110 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
111 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
112 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
113 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
114 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
115 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
116 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
197ff761 117 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
6fb07058 118 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
ef3386f0 119 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
7f3e3d3a 120 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
5b538df9 121 RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
daf9df6d 122 RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
123 RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
124 RTL_GIGA_MAC_VER_27 = 0x1b // 8168DP
1da177e4
LT		 125};
126
1da177e4
LT		 127#define _R(NAME,MAC,MASK) \
128 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
129
3c6bee1d 130static const struct {
1da177e4
LT		 131 const char *name;
132 u8 mac_version;
133 u32 RxConfigMask; /* Clears the bits supported by this chip */
134} rtl_chip_info[] = {
ba6eb6ee
FR		 135 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
136 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
137 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
138 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
139 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
6dccd16b 140 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
2857ffb7
FR		 141 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
142 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
143 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
144 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
bcf0bf90
FR		 145 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
146 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
147 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
148 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
e3cf0cc0
FR		 149 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
150 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
151 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
152 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
153 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
197ff761 154 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
6fb07058 155 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
ef3386f0 156 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
7f3e3d3a 157 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
5b538df9 158 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
daf9df6d 159 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E
160 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E
161 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27, 0xff7e1880) // PCI-E
1da177e4
LT		 162};
163#undef _R
164
bcf0bf90
FR		 165enum cfg_version {
166 RTL_CFG_0 = 0x00,
167 RTL_CFG_1,
168 RTL_CFG_2
169};
170
07ce4064
FR		 171static void rtl_hw_start_8169(struct net_device *);
172static void rtl_hw_start_8168(struct net_device *);
173static void rtl_hw_start_8101(struct net_device *);
174
a3aa1884 175static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
bcf0bf90 176 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 177 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 178 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 179 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 180 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
181 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
bc1660b5 182 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 183 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
184 { PCI_VENDOR_ID_LINKSYS, 0x1032,
185 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 186 { 0x0001, 0x8168,
187 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 188 {0,},
189};
190
191MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
192
6f0333b8 193static int rx_buf_sz = 16383;
4300e8c7 194static int use_dac;
b57b7e5a
SH		 195static struct {
196 u32 msg_enable;
197} debug = { -1 };
1da177e4 198
07d3f51f
FR		 199enum rtl_registers {
200 MAC0 = 0, /* Ethernet hardware address. */
773d2021 201 MAC4 = 4,
07d3f51f
FR		 202 MAR0 = 8, /* Multicast filter. */
203 CounterAddrLow = 0x10,
204 CounterAddrHigh = 0x14,
205 TxDescStartAddrLow = 0x20,
206 TxDescStartAddrHigh = 0x24,
207 TxHDescStartAddrLow = 0x28,
208 TxHDescStartAddrHigh = 0x2c,
209 FLASH = 0x30,
210 ERSR = 0x36,
211 ChipCmd = 0x37,
212 TxPoll = 0x38,
213 IntrMask = 0x3c,
214 IntrStatus = 0x3e,
215 TxConfig = 0x40,
216 RxConfig = 0x44,
217 RxMissed = 0x4c,
218 Cfg9346 = 0x50,
219 Config0 = 0x51,
220 Config1 = 0x52,
221 Config2 = 0x53,
222 Config3 = 0x54,
223 Config4 = 0x55,
224 Config5 = 0x56,
225 MultiIntr = 0x5c,
226 PHYAR = 0x60,
07d3f51f
FR		 227 PHYstatus = 0x6c,
228 RxMaxSize = 0xda,
229 CPlusCmd = 0xe0,
230 IntrMitigate = 0xe2,
231 RxDescAddrLow = 0xe4,
232 RxDescAddrHigh = 0xe8,
f0298f81 233 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
234
235#define NoEarlyTx 0x3f /* Max value : no early transmit. */
236
237 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
238
239#define TxPacketMax (8064 >> 7)
240
07d3f51f
FR		 241 FuncEvent = 0xf0,
242 FuncEventMask = 0xf4,
243 FuncPresetState = 0xf8,
244 FuncForceEvent = 0xfc,
1da177e4
LT		 245};
246
f162a5d1
FR		 247enum rtl8110_registers {
248 TBICSR = 0x64,
249 TBI_ANAR = 0x68,
250 TBI_LPAR = 0x6a,
251};
252
253enum rtl8168_8101_registers {
254 CSIDR = 0x64,
255 CSIAR = 0x68,
256#define CSIAR_FLAG 0x80000000
257#define CSIAR_WRITE_CMD 0x80000000
258#define CSIAR_BYTE_ENABLE 0x0f
259#define CSIAR_BYTE_ENABLE_SHIFT 12
260#define CSIAR_ADDR_MASK 0x0fff
065c27c1 261 PMCH = 0x6f,
f162a5d1
FR		 262 EPHYAR = 0x80,
263#define EPHYAR_FLAG 0x80000000
264#define EPHYAR_WRITE_CMD 0x80000000
265#define EPHYAR_REG_MASK 0x1f
266#define EPHYAR_REG_SHIFT 16
267#define EPHYAR_DATA_MASK 0xffff
268 DBG_REG = 0xd1,
269#define FIX_NAK_1 (1 << 4)
270#define FIX_NAK_2 (1 << 3)
daf9df6d 271 EFUSEAR = 0xdc,
272#define EFUSEAR_FLAG 0x80000000
273#define EFUSEAR_WRITE_CMD 0x80000000
274#define EFUSEAR_READ_CMD 0x00000000
275#define EFUSEAR_REG_MASK 0x03ff
276#define EFUSEAR_REG_SHIFT 8
277#define EFUSEAR_DATA_MASK 0xff
f162a5d1
FR		 278};
279
c0e45c1c 280enum rtl8168_registers {
b646d900 281 ERIDR = 0x70,
282 ERIAR = 0x74,
283#define ERIAR_FLAG 0x80000000
284#define ERIAR_WRITE_CMD 0x80000000
285#define ERIAR_READ_CMD 0x00000000
286#define ERIAR_ADDR_BYTE_ALIGN 4
287#define ERIAR_EXGMAC 0
288#define ERIAR_MSIX 1
289#define ERIAR_ASF 2
290#define ERIAR_TYPE_SHIFT 16
291#define ERIAR_BYTEEN 0x0f
292#define ERIAR_BYTEEN_SHIFT 12
c0e45c1c 293 EPHY_RXER_NUM = 0x7c,
294 OCPDR = 0xb0, /* OCP GPHY access */
295#define OCPDR_WRITE_CMD 0x80000000
296#define OCPDR_READ_CMD 0x00000000
297#define OCPDR_REG_MASK 0x7f
298#define OCPDR_GPHY_REG_SHIFT 16
299#define OCPDR_DATA_MASK 0xffff
300 OCPAR = 0xb4,
301#define OCPAR_FLAG 0x80000000
302#define OCPAR_GPHY_WRITE_CMD 0x8000f060
303#define OCPAR_GPHY_READ_CMD 0x0000f060
304};
305
07d3f51f 306enum rtl_register_content {
1da177e4 307 /* InterruptStatusBits */
07d3f51f
FR		 308 SYSErr = 0x8000,
309 PCSTimeout = 0x4000,
310 SWInt = 0x0100,
311 TxDescUnavail = 0x0080,
312 RxFIFOOver = 0x0040,
313 LinkChg = 0x0020,
314 RxOverflow = 0x0010,
315 TxErr = 0x0008,
316 TxOK = 0x0004,
317 RxErr = 0x0002,
318 RxOK = 0x0001,
1da177e4
LT		 319
320 /* RxStatusDesc */
9dccf611
FR		 321 RxFOVF = (1 << 23),
322 RxRWT = (1 << 22),
323 RxRES = (1 << 21),
324 RxRUNT = (1 << 20),
325 RxCRC = (1 << 19),
1da177e4
LT		 326
327 /* ChipCmdBits */
07d3f51f
FR		 328 CmdReset = 0x10,
329 CmdRxEnb = 0x08,
330 CmdTxEnb = 0x04,
331 RxBufEmpty = 0x01,
1da177e4 332
275391a4
FR		 333 /* TXPoll register p.5 */
334 HPQ = 0x80, /* Poll cmd on the high prio queue */
335 NPQ = 0x40, /* Poll cmd on the low prio queue */
336 FSWInt = 0x01, /* Forced software interrupt */
337
1da177e4 338 /* Cfg9346Bits */
07d3f51f
FR		 339 Cfg9346_Lock = 0x00,
340 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 341
342 /* rx_mode_bits */
07d3f51f
FR		 343 AcceptErr = 0x20,
344 AcceptRunt = 0x10,
345 AcceptBroadcast = 0x08,
346 AcceptMulticast = 0x04,
347 AcceptMyPhys = 0x02,
348 AcceptAllPhys = 0x01,
1da177e4
LT		 349
350 /* RxConfigBits */
07d3f51f
FR		 351 RxCfgFIFOShift = 13,
352 RxCfgDMAShift = 8,
1da177e4
LT		 353
354 /* TxConfigBits */
355 TxInterFrameGapShift = 24,
356 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
357
5d06a99f 358 /* Config1 register p.24 */
f162a5d1
FR		 359 LEDS1 = (1 << 7),
360 LEDS0 = (1 << 6),
fbac58fc 361 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
f162a5d1
FR		 362 Speed_down = (1 << 4),
363 MEMMAP = (1 << 3),
364 IOMAP = (1 << 2),
365 VPD = (1 << 1),
5d06a99f
FR		 366 PMEnable = (1 << 0), /* Power Management Enable */
367
6dccd16b
FR		 368 /* Config2 register p. 25 */
369 PCI_Clock_66MHz = 0x01,
370 PCI_Clock_33MHz = 0x00,
371
61a4dcc2
FR		 372 /* Config3 register p.25 */
373 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
374 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
f162a5d1 375 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 376
5d06a99f 377 /* Config5 register p.27 */
61a4dcc2
FR		 378 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
379 MWF = (1 << 5), /* Accept Multicast wakeup frame */
380 UWF = (1 << 4), /* Accept Unicast wakeup frame */
381 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 382 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
383
1da177e4
LT		 384 /* TBICSR p.28 */
385 TBIReset = 0x80000000,
386 TBILoopback = 0x40000000,
387 TBINwEnable = 0x20000000,
388 TBINwRestart = 0x10000000,
389 TBILinkOk = 0x02000000,
390 TBINwComplete = 0x01000000,
391
392 /* CPlusCmd p.31 */
f162a5d1
FR		 393 EnableBist = (1 << 15), // 8168 8101
394 Mac_dbgo_oe = (1 << 14), // 8168 8101
395 Normal_mode = (1 << 13), // unused
396 Force_half_dup = (1 << 12), // 8168 8101
397 Force_rxflow_en = (1 << 11), // 8168 8101
398 Force_txflow_en = (1 << 10), // 8168 8101
399 Cxpl_dbg_sel = (1 << 9), // 8168 8101
400 ASF = (1 << 8), // 8168 8101
401 PktCntrDisable = (1 << 7), // 8168 8101
402 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 403 RxVlan = (1 << 6),
404 RxChkSum = (1 << 5),
405 PCIDAC = (1 << 4),
406 PCIMulRW = (1 << 3),
0e485150
FR		 407 INTT_0 = 0x0000, // 8168
408 INTT_1 = 0x0001, // 8168
409 INTT_2 = 0x0002, // 8168
410 INTT_3 = 0x0003, // 8168
1da177e4
LT		 411
412 /* rtl8169_PHYstatus */
07d3f51f
FR		 413 TBI_Enable = 0x80,
414 TxFlowCtrl = 0x40,
415 RxFlowCtrl = 0x20,
416 _1000bpsF = 0x10,
417 _100bps = 0x08,
418 _10bps = 0x04,
419 LinkStatus = 0x02,
420 FullDup = 0x01,
1da177e4 421
1da177e4 422 /* _TBICSRBit */
07d3f51f 423 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 424
425 /* DumpCounterCommand */
07d3f51f 426 CounterDump = 0x8,
1da177e4
LT		 427};
428
07d3f51f 429enum desc_status_bit {
1da177e4
LT		 430 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
431 RingEnd = (1 << 30), /* End of descriptor ring */
432 FirstFrag = (1 << 29), /* First segment of a packet */
433 LastFrag = (1 << 28), /* Final segment of a packet */
434
435 /* Tx private */
436 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
437 MSSShift = 16, /* MSS value position */
438 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
439 IPCS = (1 << 18), /* Calculate IP checksum */
440 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
441 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
442 TxVlanTag = (1 << 17), /* Add VLAN tag */
443
444 /* Rx private */
445 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
446 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
447
448#define RxProtoUDP (PID1)
449#define RxProtoTCP (PID0)
450#define RxProtoIP (PID1 | PID0)
451#define RxProtoMask RxProtoIP
452
453 IPFail = (1 << 16), /* IP checksum failed */
454 UDPFail = (1 << 15), /* UDP/IP checksum failed */
455 TCPFail = (1 << 14), /* TCP/IP checksum failed */
456 RxVlanTag = (1 << 16), /* VLAN tag available */
457};
458
459#define RsvdMask 0x3fffc000
460
461struct TxDesc {
6cccd6e7
REB		 462 __le32 opts1;
463 __le32 opts2;
464 __le64 addr;
1da177e4
LT		 465};
466
467struct RxDesc {
6cccd6e7
REB		 468 __le32 opts1;
469 __le32 opts2;
470 __le64 addr;
1da177e4
LT		 471};
472
473struct ring_info {
474 struct sk_buff *skb;
475 u32 len;
476 u8 __pad[sizeof(void *) - sizeof(u32)];
477};
478
f23e7fda 479enum features {
ccdffb9a
FR		 480 RTL_FEATURE_WOL = (1 << 0),
481 RTL_FEATURE_MSI = (1 << 1),
482 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 483};
484
355423d0
IV		 485struct rtl8169_counters {
486 __le64 tx_packets;
487 __le64 rx_packets;
488 __le64 tx_errors;
489 __le32 rx_errors;
490 __le16 rx_missed;
491 __le16 align_errors;
492 __le32 tx_one_collision;
493 __le32 tx_multi_collision;
494 __le64 rx_unicast;
495 __le64 rx_broadcast;
496 __le32 rx_multicast;
497 __le16 tx_aborted;
498 __le16 tx_underun;
499};
500
1da177e4
LT		 501struct rtl8169_private {
502 void __iomem *mmio_addr; /* memory map physical address */
503 struct pci_dev *pci_dev; /* Index of PCI device */
c4028958 504 struct net_device *dev;
bea3348e 505 struct napi_struct napi;
1da177e4 506 spinlock_t lock; /* spin lock flag */
b57b7e5a 507 u32 msg_enable;
1da177e4
LT		 508 int chipset;
509 int mac_version;
1da177e4
LT		 510 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
511 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
512 u32 dirty_rx;
513 u32 dirty_tx;
514 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
515 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
516 dma_addr_t TxPhyAddr;
517 dma_addr_t RxPhyAddr;
6f0333b8 518 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 519 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 520 struct timer_list timer;
521 u16 cp_cmd;
0e485150
FR		 522 u16 intr_event;
523 u16 napi_event;
1da177e4 524 u16 intr_mask;
1da177e4
LT		 525 int phy_1000_ctrl_reg;
526#ifdef CONFIG_R8169_VLAN
527 struct vlan_group *vlgrp;
528#endif
c0e45c1c 529
530 struct mdio_ops {
531 void (*write)(void __iomem *, int, int);
532 int (*read)(void __iomem *, int);
533 } mdio_ops;
534
065c27c1 535 struct pll_power_ops {
536 void (*down)(struct rtl8169_private *);
537 void (*up)(struct rtl8169_private *);
538 } pll_power_ops;
539
1da177e4 540 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
ccdffb9a 541 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
4da19633 542 void (*phy_reset_enable)(struct rtl8169_private *tp);
07ce4064 543 void (*hw_start)(struct net_device *);
4da19633 544 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1da177e4 545 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 546 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
9c14ceaf 547 int pcie_cap;
c4028958 548 struct delayed_work task;
f23e7fda 549 unsigned features;
ccdffb9a
FR		 550
551 struct mii_if_info mii;
355423d0 552 struct rtl8169_counters counters;
e1759441 553 u32 saved_wolopts;
1da177e4
LT		 554};
555
979b6c13 556MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 557MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 558module_param(use_dac, int, 0);
4300e8c7 559MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 560module_param_named(debug, debug.msg_enable, int, 0);
561MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 562MODULE_LICENSE("GPL");
563MODULE_VERSION(RTL8169_VERSION);
bca03d5f 564MODULE_FIRMWARE(FIRMWARE_8168D_1);
565MODULE_FIRMWARE(FIRMWARE_8168D_2);
1da177e4
LT		 566
567static int rtl8169_open(struct net_device *dev);
61357325
SH		 568static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
569 struct net_device *dev);
7d12e780 570static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 571static int rtl8169_init_ring(struct net_device *dev);
07ce4064 572static void rtl_hw_start(struct net_device *dev);
1da177e4 573static int rtl8169_close(struct net_device *dev);
07ce4064 574static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 575static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 576static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4 577static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
bea3348e 578 void __iomem *, u32 budget);
4dcb7d33 579static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 580static void rtl8169_down(struct net_device *dev);
99f252b0 581static void rtl8169_rx_clear(struct rtl8169_private *tp);
bea3348e 582static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4 583
1da177e4 584static const unsigned int rtl8169_rx_config =
5b0384f4 585 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4 586
b646d900 587static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
588{
589 void __iomem *ioaddr = tp->mmio_addr;
590 int i;
591
592 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
593 for (i = 0; i < 20; i++) {
594 udelay(100);
595 if (RTL_R32(OCPAR) & OCPAR_FLAG)
596 break;
597 }
598 return RTL_R32(OCPDR);
599}
600
601static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
602{
603 void __iomem *ioaddr = tp->mmio_addr;
604 int i;
605
606 RTL_W32(OCPDR, data);
607 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
608 for (i = 0; i < 20; i++) {
609 udelay(100);
610 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
611 break;
612 }
613}
614
615static void rtl8168_oob_notify(void __iomem *ioaddr, u8 cmd)
616{
617 int i;
618
619 RTL_W8(ERIDR, cmd);
620 RTL_W32(ERIAR, 0x800010e8);
621 msleep(2);
622 for (i = 0; i < 5; i++) {
623 udelay(100);
624 if (!(RTL_R32(ERIDR) & ERIAR_FLAG))
625 break;
626 }
627
628 ocp_write(ioaddr, 0x1, 0x30, 0x00000001);
629}
630
631#define OOB_CMD_RESET 0x00
632#define OOB_CMD_DRIVER_START 0x05
633#define OOB_CMD_DRIVER_STOP 0x06
634
635static void rtl8168_driver_start(struct rtl8169_private *tp)
636{
637 int i;
638
639 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
640
641 for (i = 0; i < 10; i++) {
642 msleep(10);
643 if (ocp_read(tp, 0x0f, 0x0010) & 0x00000800)
644 break;
645 }
646}
647
648static void rtl8168_driver_stop(struct rtl8169_private *tp)
649{
650 int i;
651
652 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
653
654 for (i = 0; i < 10; i++) {
655 msleep(10);
656 if ((ocp_read(tp, 0x0f, 0x0010) & 0x00000800) == 0)
657 break;
658 }
659}
660
661
4da19633 662static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 663{
664 int i;
665
a6baf3af 666 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
1da177e4 667
2371408c 668 for (i = 20; i > 0; i--) {
07d3f51f
FR		 669 /*
670 * Check if the RTL8169 has completed writing to the specified
671 * MII register.
672 */
5b0384f4 673 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 674 break;
2371408c 675 udelay(25);
1da177e4 676 }
024a07ba 677 /*
81a95f04
TT		 678 * According to hardware specs a 20us delay is required after write
679 * complete indication, but before sending next command.
024a07ba 680 */
81a95f04 681 udelay(20);
1da177e4
LT		 682}
683
4da19633 684static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 685{
686 int i, value = -1;
687
a6baf3af 688 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
1da177e4 689
2371408c 690 for (i = 20; i > 0; i--) {
07d3f51f
FR		 691 /*
692 * Check if the RTL8169 has completed retrieving data from
693 * the specified MII register.
694 */
1da177e4 695 if (RTL_R32(PHYAR) & 0x80000000) {
a6baf3af 696 value = RTL_R32(PHYAR) & 0xffff;
1da177e4
LT		 697 break;
698 }
2371408c 699 udelay(25);
1da177e4 700 }
81a95f04
TT		 701 /*
702 * According to hardware specs a 20us delay is required after read
703 * complete indication, but before sending next command.
704 */
705 udelay(20);
706
1da177e4
LT		 707 return value;
708}
709
c0e45c1c 710static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
711{
712 int i;
713
714 RTL_W32(OCPDR, data |
715 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
716 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
717 RTL_W32(EPHY_RXER_NUM, 0);
718
719 for (i = 0; i < 100; i++) {
720 mdelay(1);
721 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
722 break;
723 }
724}
725
726static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
727{
728 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
729 (value & OCPDR_DATA_MASK));
730}
731
732static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
733{
734 int i;
735
736 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
737
738 mdelay(1);
739 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
740 RTL_W32(EPHY_RXER_NUM, 0);
741
742 for (i = 0; i < 100; i++) {
743 mdelay(1);
744 if (RTL_R32(OCPAR) & OCPAR_FLAG)
745 break;
746 }
747
748 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
749}
750
4da19633 751static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 752{
c0e45c1c 753 tp->mdio_ops.write(tp->mmio_addr, location, val);
dacf8154
FR		 754}
755
4da19633 756static int rtl_readphy(struct rtl8169_private *tp, int location)
757{
c0e45c1c 758 return tp->mdio_ops.read(tp->mmio_addr, location);
4da19633 759}
760
761static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
762{
763 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
764}
765
766static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 767{
768 int val;
769
4da19633 770 val = rtl_readphy(tp, reg_addr);
771 rtl_writephy(tp, reg_addr, (val | p) & ~m);
daf9df6d 772}
773
ccdffb9a
FR		 774static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
775 int val)
776{
777 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 778
4da19633 779 rtl_writephy(tp, location, val);
ccdffb9a
FR		 780}
781
782static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
783{
784 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 785
4da19633 786 return rtl_readphy(tp, location);
ccdffb9a
FR		 787}
788
dacf8154
FR		 789static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
790{
791 unsigned int i;
792
793 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
794 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
795
796 for (i = 0; i < 100; i++) {
797 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
798 break;
799 udelay(10);
800 }
801}
802
803static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
804{
805 u16 value = 0xffff;
806 unsigned int i;
807
808 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
809
810 for (i = 0; i < 100; i++) {
811 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
812 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
813 break;
814 }
815 udelay(10);
816 }
817
818 return value;
819}
820
821static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
822{
823 unsigned int i;
824
825 RTL_W32(CSIDR, value);
826 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
827 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
828
829 for (i = 0; i < 100; i++) {
830 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
831 break;
832 udelay(10);
833 }
834}
835
836static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
837{
838 u32 value = ~0x00;
839 unsigned int i;
840
841 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
842 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
843
844 for (i = 0; i < 100; i++) {
845 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
846 value = RTL_R32(CSIDR);
847 break;
848 }
849 udelay(10);
850 }
851
852 return value;
853}
854
daf9df6d 855static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
856{
857 u8 value = 0xff;
858 unsigned int i;
859
860 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
861
862 for (i = 0; i < 300; i++) {
863 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
864 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
865 break;
866 }
867 udelay(100);
868 }
869
870 return value;
871}
872
1da177e4
LT		 873static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
874{
875 RTL_W16(IntrMask, 0x0000);
876
877 RTL_W16(IntrStatus, 0xffff);
878}
879
880static void rtl8169_asic_down(void __iomem *ioaddr)
881{
882 RTL_W8(ChipCmd, 0x00);
883 rtl8169_irq_mask_and_ack(ioaddr);
884 RTL_R16(CPlusCmd);
885}
886
4da19633 887static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 888{
4da19633 889 void __iomem *ioaddr = tp->mmio_addr;
890
1da177e4
LT		 891 return RTL_R32(TBICSR) & TBIReset;
892}
893
4da19633 894static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 895{
4da19633 896 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 897}
898
899static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
900{
901 return RTL_R32(TBICSR) & TBILinkOk;
902}
903
904static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
905{
906 return RTL_R8(PHYstatus) & LinkStatus;
907}
908
4da19633 909static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 910{
4da19633 911 void __iomem *ioaddr = tp->mmio_addr;
912
1da177e4
LT		 913 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
914}
915
4da19633 916static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 917{
918 unsigned int val;
919
4da19633 920 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
921 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 922}
923
e4fbce74 924static void __rtl8169_check_link_status(struct net_device *dev,
07d3f51f 925 struct rtl8169_private *tp,
e4fbce74
RW		 926 void __iomem *ioaddr,
927 bool pm)
1da177e4
LT		 928{
929 unsigned long flags;
930
931 spin_lock_irqsave(&tp->lock, flags);
932 if (tp->link_ok(ioaddr)) {
e1759441 933 /* This is to cancel a scheduled suspend if there's one. */
e4fbce74
RW		 934 if (pm)
935 pm_request_resume(&tp->pci_dev->dev);
1da177e4 936 netif_carrier_on(dev);
bf82c189 937 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 938 } else {
1da177e4 939 netif_carrier_off(dev);
bf82c189 940 netif_info(tp, ifdown, dev, "link down\n");
e4fbce74
RW		 941 if (pm)
942 pm_schedule_suspend(&tp->pci_dev->dev, 100);
b57b7e5a 943 }
1da177e4
LT		 944 spin_unlock_irqrestore(&tp->lock, flags);
945}
946
e4fbce74
RW		 947static void rtl8169_check_link_status(struct net_device *dev,
948 struct rtl8169_private *tp,
949 void __iomem *ioaddr)
950{
951 __rtl8169_check_link_status(dev, tp, ioaddr, false);
952}
953
e1759441
RW		 954#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
955
956static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 957{
61a4dcc2
FR		 958 void __iomem *ioaddr = tp->mmio_addr;
959 u8 options;
e1759441 960 u32 wolopts = 0;
61a4dcc2
FR		 961
962 options = RTL_R8(Config1);
963 if (!(options & PMEnable))
e1759441 964 return 0;
61a4dcc2
FR		 965
966 options = RTL_R8(Config3);
967 if (options & LinkUp)
e1759441 968 wolopts |= WAKE_PHY;
61a4dcc2 969 if (options & MagicPacket)
e1759441 970 wolopts |= WAKE_MAGIC;
61a4dcc2
FR		 971
972 options = RTL_R8(Config5);
973 if (options & UWF)
e1759441 974 wolopts |= WAKE_UCAST;
61a4dcc2 975 if (options & BWF)
e1759441 976 wolopts |= WAKE_BCAST;
61a4dcc2 977 if (options & MWF)
e1759441 978 wolopts |= WAKE_MCAST;
61a4dcc2 979
e1759441 980 return wolopts;
61a4dcc2
FR		 981}
982
e1759441 983static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 984{
985 struct rtl8169_private *tp = netdev_priv(dev);
e1759441
RW		 986
987 spin_lock_irq(&tp->lock);
988
989 wol->supported = WAKE_ANY;
990 wol->wolopts = __rtl8169_get_wol(tp);
991
992 spin_unlock_irq(&tp->lock);
993}
994
995static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
996{
61a4dcc2 997 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 998 unsigned int i;
350f7596 999 static const struct {
61a4dcc2
FR		 1000 u32 opt;
1001 u16 reg;
1002 u8 mask;
1003 } cfg[] = {
1004 { WAKE_ANY, Config1, PMEnable },
1005 { WAKE_PHY, Config3, LinkUp },
1006 { WAKE_MAGIC, Config3, MagicPacket },
1007 { WAKE_UCAST, Config5, UWF },
1008 { WAKE_BCAST, Config5, BWF },
1009 { WAKE_MCAST, Config5, MWF },
1010 { WAKE_ANY, Config5, LanWake }
1011 };
1012
61a4dcc2
FR		 1013 RTL_W8(Cfg9346, Cfg9346_Unlock);
1014
1015 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1016 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 1017 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 1018 options |= cfg[i].mask;
1019 RTL_W8(cfg[i].reg, options);
1020 }
1021
1022 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 1023}
1024
1025static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1026{
1027 struct rtl8169_private *tp = netdev_priv(dev);
1028
1029 spin_lock_irq(&tp->lock);
61a4dcc2 1030
f23e7fda
FR		 1031 if (wol->wolopts)
1032 tp->features |= RTL_FEATURE_WOL;
1033 else
1034 tp->features &= ~RTL_FEATURE_WOL;
e1759441 1035 __rtl8169_set_wol(tp, wol->wolopts);
61a4dcc2
FR		 1036 spin_unlock_irq(&tp->lock);
1037
ea80907f 1038 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1039
61a4dcc2
FR		 1040 return 0;
1041}
1042
1da177e4
LT		 1043static void rtl8169_get_drvinfo(struct net_device *dev,
1044 struct ethtool_drvinfo *info)
1045{
1046 struct rtl8169_private *tp = netdev_priv(dev);
1047
1048 strcpy(info->driver, MODULENAME);
1049 strcpy(info->version, RTL8169_VERSION);
1050 strcpy(info->bus_info, pci_name(tp->pci_dev));
1051}
1052
1053static int rtl8169_get_regs_len(struct net_device *dev)
1054{
1055 return R8169_REGS_SIZE;
1056}
1057
1058static int rtl8169_set_speed_tbi(struct net_device *dev,
1059 u8 autoneg, u16 speed, u8 duplex)
1060{
1061 struct rtl8169_private *tp = netdev_priv(dev);
1062 void __iomem *ioaddr = tp->mmio_addr;
1063 int ret = 0;
1064 u32 reg;
1065
1066 reg = RTL_R32(TBICSR);
1067 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1068 (duplex == DUPLEX_FULL)) {
1069 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1070 } else if (autoneg == AUTONEG_ENABLE)
1071 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1072 else {
bf82c189
JP		 1073 netif_warn(tp, link, dev,
1074 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 1075 ret = -EOPNOTSUPP;
1076 }
1077
1078 return ret;
1079}
1080
1081static int rtl8169_set_speed_xmii(struct net_device *dev,
1082 u8 autoneg, u16 speed, u8 duplex)
1083{
1084 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1085 int giga_ctrl, bmcr;
1da177e4
LT		 1086
1087 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1088 int auto_nego;
1089
4da19633 1090 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
64e4bfb4
FR		 1091 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
1092 ADVERTISE_100HALF | ADVERTISE_100FULL);
3577aa1b 1093 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1094
4da19633 1095 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1096 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1097
3577aa1b 1098 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1099 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
1100 (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
1101 (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
1102 (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
1103 (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
1104 (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
1105 (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
1106 (tp->mac_version != RTL_GIGA_MAC_VER_16)) {
1107 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
bf82c189
JP		 1108 } else {
1109 netif_info(tp, link, dev,
1110 "PHY does not support 1000Mbps\n");
bcf0bf90 1111 }
1da177e4 1112
3577aa1b 1113 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1114
1115 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
1116 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
1117 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
1118 /*
1119 * Wake up the PHY.
1120 * Vendor specific (0x1f) and reserved (0x0e) MII
1121 * registers.
1122 */
4da19633 1123 rtl_writephy(tp, 0x1f, 0x0000);
1124 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1125 }
1126
4da19633 1127 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1128 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1129 } else {
1130 giga_ctrl = 0;
1131
1132 if (speed == SPEED_10)
1133 bmcr = 0;
1134 else if (speed == SPEED_100)
1135 bmcr = BMCR_SPEED100;
1136 else
1137 return -EINVAL;
1138
1139 if (duplex == DUPLEX_FULL)
1140 bmcr |= BMCR_FULLDPLX;
623a1593 1141
4da19633 1142 rtl_writephy(tp, 0x1f, 0x0000);
2584fbc3
RS		 1143 }
1144
1da177e4
LT		 1145 tp->phy_1000_ctrl_reg = giga_ctrl;
1146
4da19633 1147 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1148
1149 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1150 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1151 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1152 rtl_writephy(tp, 0x17, 0x2138);
1153 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1154 } else {
4da19633 1155 rtl_writephy(tp, 0x17, 0x2108);
1156 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1157 }
1158 }
1159
1da177e4
LT		 1160 return 0;
1161}
1162
1163static int rtl8169_set_speed(struct net_device *dev,
1164 u8 autoneg, u16 speed, u8 duplex)
1165{
1166 struct rtl8169_private *tp = netdev_priv(dev);
1167 int ret;
1168
1169 ret = tp->set_speed(dev, autoneg, speed, duplex);
1170
64e4bfb4 1171 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 1172 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1173
1174 return ret;
1175}
1176
1177static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1178{
1179 struct rtl8169_private *tp = netdev_priv(dev);
1180 unsigned long flags;
1181 int ret;
1182
1183 spin_lock_irqsave(&tp->lock, flags);
1184 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
1185 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 1186
1da177e4
LT		 1187 return ret;
1188}
1189
1190static u32 rtl8169_get_rx_csum(struct net_device *dev)
1191{
1192 struct rtl8169_private *tp = netdev_priv(dev);
1193
1194 return tp->cp_cmd & RxChkSum;
1195}
1196
1197static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
1198{
1199 struct rtl8169_private *tp = netdev_priv(dev);
1200 void __iomem *ioaddr = tp->mmio_addr;
1201 unsigned long flags;
1202
1203 spin_lock_irqsave(&tp->lock, flags);
1204
1205 if (data)
1206 tp->cp_cmd |= RxChkSum;
1207 else
1208 tp->cp_cmd &= ~RxChkSum;
1209
1210 RTL_W16(CPlusCmd, tp->cp_cmd);
1211 RTL_R16(CPlusCmd);
1212
1213 spin_unlock_irqrestore(&tp->lock, flags);
1214
1215 return 0;
1216}
1217
1218#ifdef CONFIG_R8169_VLAN
1219
1220static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1221 struct sk_buff *skb)
1222{
eab6d18d 1223 return (vlan_tx_tag_present(skb)) ?
1da177e4
LT		 1224 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1225}
1226
1227static void rtl8169_vlan_rx_register(struct net_device *dev,
1228 struct vlan_group *grp)
1229{
1230 struct rtl8169_private *tp = netdev_priv(dev);
1231 void __iomem *ioaddr = tp->mmio_addr;
1232 unsigned long flags;
1233
1234 spin_lock_irqsave(&tp->lock, flags);
1235 tp->vlgrp = grp;
05af2142
SW		 1236 /*
1237 * Do not disable RxVlan on 8110SCd.
1238 */
1239 if (tp->vlgrp || (tp->mac_version == RTL_GIGA_MAC_VER_05))
1da177e4
LT		 1240 tp->cp_cmd |= RxVlan;
1241 else
1242 tp->cp_cmd &= ~RxVlan;
1243 RTL_W16(CPlusCmd, tp->cp_cmd);
1244 RTL_R16(CPlusCmd);
1245 spin_unlock_irqrestore(&tp->lock, flags);
1246}
1247
1da177e4 1248static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
630b943c 1249 struct sk_buff *skb, int polling)
1da177e4
LT		 1250{
1251 u32 opts2 = le32_to_cpu(desc->opts2);
865c652d 1252 struct vlan_group *vlgrp = tp->vlgrp;
1da177e4
LT		 1253 int ret;
1254
865c652d 1255 if (vlgrp && (opts2 & RxVlanTag)) {
2edae08e
ED		 1256 u16 vtag = swab16(opts2 & 0xffff);
1257
1258 if (likely(polling))
1259 vlan_gro_receive(&tp->napi, vlgrp, vtag, skb);
1260 else
1261 __vlan_hwaccel_rx(skb, vlgrp, vtag, polling);
1da177e4
LT		 1262 ret = 0;
1263 } else
1264 ret = -1;
1265 desc->opts2 = 0;
1266 return ret;
1267}
1268
1269#else /* !CONFIG_R8169_VLAN */
1270
1271static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1272 struct sk_buff *skb)
1273{
1274 return 0;
1275}
1276
1277static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
630b943c 1278 struct sk_buff *skb, int polling)
1da177e4
LT		 1279{
1280 return -1;
1281}
1282
1283#endif
1284
ccdffb9a 1285static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1286{
1287 struct rtl8169_private *tp = netdev_priv(dev);
1288 void __iomem *ioaddr = tp->mmio_addr;
1289 u32 status;
1290
1291 cmd->supported =
1292 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1293 cmd->port = PORT_FIBRE;
1294 cmd->transceiver = XCVR_INTERNAL;
1295
1296 status = RTL_R32(TBICSR);
1297 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1298 cmd->autoneg = !!(status & TBINwEnable);
1299
1300 cmd->speed = SPEED_1000;
1301 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1302
1303 return 0;
1da177e4
LT		 1304}
1305
ccdffb9a 1306static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1307{
1308 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1309
1310 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1311}
1312
1313static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1314{
1315 struct rtl8169_private *tp = netdev_priv(dev);
1316 unsigned long flags;
ccdffb9a 1317 int rc;
1da177e4
LT		 1318
1319 spin_lock_irqsave(&tp->lock, flags);
1320
ccdffb9a 1321 rc = tp->get_settings(dev, cmd);
1da177e4
LT		 1322
1323 spin_unlock_irqrestore(&tp->lock, flags);
ccdffb9a 1324 return rc;
1da177e4
LT		 1325}
1326
1327static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1328 void *p)
1329{
5b0384f4
FR		 1330 struct rtl8169_private *tp = netdev_priv(dev);
1331 unsigned long flags;
1da177e4 1332
5b0384f4
FR		 1333 if (regs->len > R8169_REGS_SIZE)
1334 regs->len = R8169_REGS_SIZE;
1da177e4 1335
5b0384f4
FR		 1336 spin_lock_irqsave(&tp->lock, flags);
1337 memcpy_fromio(p, tp->mmio_addr, regs->len);
1338 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 1339}
1340
b57b7e5a
SH		 1341static u32 rtl8169_get_msglevel(struct net_device *dev)
1342{
1343 struct rtl8169_private *tp = netdev_priv(dev);
1344
1345 return tp->msg_enable;
1346}
1347
1348static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1349{
1350 struct rtl8169_private *tp = netdev_priv(dev);
1351
1352 tp->msg_enable = value;
1353}
1354
d4a3a0fc
SH		 1355static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1356 "tx_packets",
1357 "rx_packets",
1358 "tx_errors",
1359 "rx_errors",
1360 "rx_missed",
1361 "align_errors",
1362 "tx_single_collisions",
1363 "tx_multi_collisions",
1364 "unicast",
1365 "broadcast",
1366 "multicast",
1367 "tx_aborted",
1368 "tx_underrun",
1369};
1370
b9f2c044 1371static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1372{
b9f2c044
JG		 1373 switch (sset) {
1374 case ETH_SS_STATS:
1375 return ARRAY_SIZE(rtl8169_gstrings);
1376 default:
1377 return -EOPNOTSUPP;
1378 }
d4a3a0fc
SH		 1379}
1380
355423d0 1381static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1382{
1383 struct rtl8169_private *tp = netdev_priv(dev);
1384 void __iomem *ioaddr = tp->mmio_addr;
1385 struct rtl8169_counters *counters;
1386 dma_addr_t paddr;
1387 u32 cmd;
355423d0 1388 int wait = 1000;
48addcc9 1389 struct device *d = &tp->pci_dev->dev;
d4a3a0fc 1390
355423d0
IV		 1391 /*
1392 * Some chips are unable to dump tally counters when the receiver
1393 * is disabled.
1394 */
1395 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1396 return;
d4a3a0fc 1397
48addcc9 1398 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
d4a3a0fc
SH		 1399 if (!counters)
1400 return;
1401
1402 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1403 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1404 RTL_W32(CounterAddrLow, cmd);
1405 RTL_W32(CounterAddrLow, cmd | CounterDump);
1406
355423d0
IV		 1407 while (wait--) {
1408 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1409 /* copy updated counters */
1410 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc 1411 break;
355423d0
IV		 1412 }
1413 udelay(10);
d4a3a0fc
SH		 1414 }
1415
1416 RTL_W32(CounterAddrLow, 0);
1417 RTL_W32(CounterAddrHigh, 0);
1418
48addcc9 1419 dma_free_coherent(d, sizeof(*counters), counters, paddr);
d4a3a0fc
SH		 1420}
1421
355423d0
IV		 1422static void rtl8169_get_ethtool_stats(struct net_device *dev,
1423 struct ethtool_stats *stats, u64 *data)
1424{
1425 struct rtl8169_private *tp = netdev_priv(dev);
1426
1427 ASSERT_RTNL();
1428
1429 rtl8169_update_counters(dev);
1430
1431 data[0] = le64_to_cpu(tp->counters.tx_packets);
1432 data[1] = le64_to_cpu(tp->counters.rx_packets);
1433 data[2] = le64_to_cpu(tp->counters.tx_errors);
1434 data[3] = le32_to_cpu(tp->counters.rx_errors);
1435 data[4] = le16_to_cpu(tp->counters.rx_missed);
1436 data[5] = le16_to_cpu(tp->counters.align_errors);
1437 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1438 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1439 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1440 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1441 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1442 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1443 data[12] = le16_to_cpu(tp->counters.tx_underun);
1444}
1445
d4a3a0fc
SH		 1446static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1447{
1448 switch(stringset) {
1449 case ETH_SS_STATS:
1450 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1451 break;
1452 }
1453}
1454
7282d491 1455static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1456 .get_drvinfo = rtl8169_get_drvinfo,
1457 .get_regs_len = rtl8169_get_regs_len,
1458 .get_link = ethtool_op_get_link,
1459 .get_settings = rtl8169_get_settings,
1460 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1461 .get_msglevel = rtl8169_get_msglevel,
1462 .set_msglevel = rtl8169_set_msglevel,
1da177e4
LT		 1463 .get_rx_csum = rtl8169_get_rx_csum,
1464 .set_rx_csum = rtl8169_set_rx_csum,
1da177e4 1465 .set_tx_csum = ethtool_op_set_tx_csum,
1da177e4 1466 .set_sg = ethtool_op_set_sg,
1da177e4
LT		 1467 .set_tso = ethtool_op_set_tso,
1468 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1469 .get_wol = rtl8169_get_wol,
1470 .set_wol = rtl8169_set_wol,
d4a3a0fc 1471 .get_strings = rtl8169_get_strings,
b9f2c044 1472 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1473 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1474};
1475
07d3f51f
FR		 1476static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1477 void __iomem *ioaddr)
1da177e4 1478{
0e485150
FR		 1479 /*
1480 * The driver currently handles the 8168Bf and the 8168Be identically
1481 * but they can be identified more specifically through the test below
1482 * if needed:
1483 *
1484 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1485 *
1486 * Same thing for the 8101Eb and the 8101Ec:
1487 *
1488 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1489 */
350f7596 1490 static const struct {
1da177e4 1491 u32 mask;
e3cf0cc0 1492 u32 val;
1da177e4
LT		 1493 int mac_version;
1494 } mac_info[] = {
5b538df9 1495 /* 8168D family. */
daf9df6d 1496 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1497 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
1498 { 0x7c800000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1499 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 1500
ef808d50 1501 /* 8168C family. */
17c99297 1502 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 1503 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 1504 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 1505 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 1506 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1507 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 1508 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 1509 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 1510 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 1511
1512 /* 8168B family. */
1513 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1514 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1515 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1516 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1517
1518 /* 8101 family. */
2857ffb7
FR		 1519 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1520 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1521 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1522 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1523 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1524 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 1525 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 1526 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 1527 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 1528 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1529 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 1530 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1531 /* FIXME: where did these entries come from ? -- FR */
1532 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1533 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1534
1535 /* 8110 family. */
1536 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1537 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1538 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1539 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1540 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1541 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1542
f21b75e9
JD		 1543 /* Catch-all */
1544 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1da177e4
LT		 1545 }, *p = mac_info;
1546 u32 reg;
1547
e3cf0cc0
FR		 1548 reg = RTL_R32(TxConfig);
1549 while ((reg & p->mask) != p->val)
1da177e4
LT		 1550 p++;
1551 tp->mac_version = p->mac_version;
1552}
1553
1554static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1555{
bcf0bf90 1556 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1557}
1558
867763c1
FR		 1559struct phy_reg {
1560 u16 reg;
1561 u16 val;
1562};
1563
4da19633 1564static void rtl_writephy_batch(struct rtl8169_private *tp,
1565 const struct phy_reg *regs, int len)
867763c1
FR		 1566{
1567 while (len-- > 0) {
4da19633 1568 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 1569 regs++;
1570 }
1571}
1572
bca03d5f 1573#define PHY_READ 0x00000000
1574#define PHY_DATA_OR 0x10000000
1575#define PHY_DATA_AND 0x20000000
1576#define PHY_BJMPN 0x30000000
1577#define PHY_READ_EFUSE 0x40000000
1578#define PHY_READ_MAC_BYTE 0x50000000
1579#define PHY_WRITE_MAC_BYTE 0x60000000
1580#define PHY_CLEAR_READCOUNT 0x70000000
1581#define PHY_WRITE 0x80000000
1582#define PHY_READCOUNT_EQ_SKIP 0x90000000
1583#define PHY_COMP_EQ_SKIPN 0xa0000000
1584#define PHY_COMP_NEQ_SKIPN 0xb0000000
1585#define PHY_WRITE_PREVIOUS 0xc0000000
1586#define PHY_SKIPN 0xd0000000
1587#define PHY_DELAY_MS 0xe0000000
1588#define PHY_WRITE_ERI_WORD 0xf0000000
1589
1590static void
1591rtl_phy_write_fw(struct rtl8169_private *tp, const struct firmware *fw)
1592{
bca03d5f 1593 __le32 *phytable = (__le32 *)fw->data;
1594 struct net_device *dev = tp->dev;
1595 size_t i;
1596
1597 if (fw->size % sizeof(*phytable)) {
1598 netif_err(tp, probe, dev, "odd sized firmware %zd\n", fw->size);
1599 return;
1600 }
1601
1602 for (i = 0; i < fw->size / sizeof(*phytable); i++) {
1603 u32 action = le32_to_cpu(phytable[i]);
1604
1605 if (!action)
1606 break;
1607
1608 if ((action & 0xf0000000) != PHY_WRITE) {
1609 netif_err(tp, probe, dev,
1610 "unknown action 0x%08x\n", action);
1611 return;
1612 }
1613 }
1614
1615 while (i-- != 0) {
1616 u32 action = le32_to_cpu(*phytable);
1617 u32 data = action & 0x0000ffff;
1618 u32 reg = (action & 0x0fff0000) >> 16;
1619
1620 switch(action & 0xf0000000) {
1621 case PHY_WRITE:
4da19633 1622 rtl_writephy(tp, reg, data);
bca03d5f 1623 phytable++;
1624 break;
1625 default:
1626 BUG();
1627 }
1628 }
1629}
1630
4da19633 1631static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 1632{
350f7596 1633 static const struct phy_reg phy_reg_init[] = {
0b9b571d 1634 { 0x1f, 0x0001 },
1635 { 0x06, 0x006e },
1636 { 0x08, 0x0708 },
1637 { 0x15, 0x4000 },
1638 { 0x18, 0x65c7 },
1da177e4 1639
0b9b571d 1640 { 0x1f, 0x0001 },
1641 { 0x03, 0x00a1 },
1642 { 0x02, 0x0008 },
1643 { 0x01, 0x0120 },
1644 { 0x00, 0x1000 },
1645 { 0x04, 0x0800 },
1646 { 0x04, 0x0000 },
1da177e4 1647
0b9b571d 1648 { 0x03, 0xff41 },
1649 { 0x02, 0xdf60 },
1650 { 0x01, 0x0140 },
1651 { 0x00, 0x0077 },
1652 { 0x04, 0x7800 },
1653 { 0x04, 0x7000 },
1654
1655 { 0x03, 0x802f },
1656 { 0x02, 0x4f02 },
1657 { 0x01, 0x0409 },
1658 { 0x00, 0xf0f9 },
1659 { 0x04, 0x9800 },
1660 { 0x04, 0x9000 },
1661
1662 { 0x03, 0xdf01 },
1663 { 0x02, 0xdf20 },
1664 { 0x01, 0xff95 },
1665 { 0x00, 0xba00 },
1666 { 0x04, 0xa800 },
1667 { 0x04, 0xa000 },
1668
1669 { 0x03, 0xff41 },
1670 { 0x02, 0xdf20 },
1671 { 0x01, 0x0140 },
1672 { 0x00, 0x00bb },
1673 { 0x04, 0xb800 },
1674 { 0x04, 0xb000 },
1675
1676 { 0x03, 0xdf41 },
1677 { 0x02, 0xdc60 },
1678 { 0x01, 0x6340 },
1679 { 0x00, 0x007d },
1680 { 0x04, 0xd800 },
1681 { 0x04, 0xd000 },
1682
1683 { 0x03, 0xdf01 },
1684 { 0x02, 0xdf20 },
1685 { 0x01, 0x100a },
1686 { 0x00, 0xa0ff },
1687 { 0x04, 0xf800 },
1688 { 0x04, 0xf000 },
1689
1690 { 0x1f, 0x0000 },
1691 { 0x0b, 0x0000 },
1692 { 0x00, 0x9200 }
1693 };
1da177e4 1694
4da19633 1695 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 1696}
1697
4da19633 1698static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 1699{
350f7596 1700 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 1701 { 0x1f, 0x0002 },
1702 { 0x01, 0x90d0 },
1703 { 0x1f, 0x0000 }
1704 };
1705
4da19633 1706 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 1707}
1708
4da19633 1709static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 1710{
1711 struct pci_dev *pdev = tp->pci_dev;
1712 u16 vendor_id, device_id;
1713
1714 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1715 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1716
1717 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1718 return;
1719
4da19633 1720 rtl_writephy(tp, 0x1f, 0x0001);
1721 rtl_writephy(tp, 0x10, 0xf01b);
1722 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 1723}
1724
4da19633 1725static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 1726{
350f7596 1727 static const struct phy_reg phy_reg_init[] = {
2e955856 1728 { 0x1f, 0x0001 },
1729 { 0x04, 0x0000 },
1730 { 0x03, 0x00a1 },
1731 { 0x02, 0x0008 },
1732 { 0x01, 0x0120 },
1733 { 0x00, 0x1000 },
1734 { 0x04, 0x0800 },
1735 { 0x04, 0x9000 },
1736 { 0x03, 0x802f },
1737 { 0x02, 0x4f02 },
1738 { 0x01, 0x0409 },
1739 { 0x00, 0xf099 },
1740 { 0x04, 0x9800 },
1741 { 0x04, 0xa000 },
1742 { 0x03, 0xdf01 },
1743 { 0x02, 0xdf20 },
1744 { 0x01, 0xff95 },
1745 { 0x00, 0xba00 },
1746 { 0x04, 0xa800 },
1747 { 0x04, 0xf000 },
1748 { 0x03, 0xdf01 },
1749 { 0x02, 0xdf20 },
1750 { 0x01, 0x101a },
1751 { 0x00, 0xa0ff },
1752 { 0x04, 0xf800 },
1753 { 0x04, 0x0000 },
1754 { 0x1f, 0x0000 },
1755
1756 { 0x1f, 0x0001 },
1757 { 0x10, 0xf41b },
1758 { 0x14, 0xfb54 },
1759 { 0x18, 0xf5c7 },
1760 { 0x1f, 0x0000 },
1761
1762 { 0x1f, 0x0001 },
1763 { 0x17, 0x0cc0 },
1764 { 0x1f, 0x0000 }
1765 };
1766
4da19633 1767 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 1768
4da19633 1769 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 1770}
1771
4da19633 1772static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 1773{
350f7596 1774 static const struct phy_reg phy_reg_init[] = {
8c7006aa 1775 { 0x1f, 0x0001 },
1776 { 0x04, 0x0000 },
1777 { 0x03, 0x00a1 },
1778 { 0x02, 0x0008 },
1779 { 0x01, 0x0120 },
1780 { 0x00, 0x1000 },
1781 { 0x04, 0x0800 },
1782 { 0x04, 0x9000 },
1783 { 0x03, 0x802f },
1784 { 0x02, 0x4f02 },
1785 { 0x01, 0x0409 },
1786 { 0x00, 0xf099 },
1787 { 0x04, 0x9800 },
1788 { 0x04, 0xa000 },
1789 { 0x03, 0xdf01 },
1790 { 0x02, 0xdf20 },
1791 { 0x01, 0xff95 },
1792 { 0x00, 0xba00 },
1793 { 0x04, 0xa800 },
1794 { 0x04, 0xf000 },
1795 { 0x03, 0xdf01 },
1796 { 0x02, 0xdf20 },
1797 { 0x01, 0x101a },
1798 { 0x00, 0xa0ff },
1799 { 0x04, 0xf800 },
1800 { 0x04, 0x0000 },
1801 { 0x1f, 0x0000 },
1802
1803 { 0x1f, 0x0001 },
1804 { 0x0b, 0x8480 },
1805 { 0x1f, 0x0000 },
1806
1807 { 0x1f, 0x0001 },
1808 { 0x18, 0x67c7 },
1809 { 0x04, 0x2000 },
1810 { 0x03, 0x002f },
1811 { 0x02, 0x4360 },
1812 { 0x01, 0x0109 },
1813 { 0x00, 0x3022 },
1814 { 0x04, 0x2800 },
1815 { 0x1f, 0x0000 },
1816
1817 { 0x1f, 0x0001 },
1818 { 0x17, 0x0cc0 },
1819 { 0x1f, 0x0000 }
1820 };
1821
4da19633 1822 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 1823}
1824
4da19633 1825static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 1826{
350f7596 1827 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 1828 { 0x10, 0xf41b },
1829 { 0x1f, 0x0000 }
1830 };
1831
4da19633 1832 rtl_writephy(tp, 0x1f, 0x0001);
1833 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 1834
4da19633 1835 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 1836}
1837
4da19633 1838static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 1839{
350f7596 1840 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 1841 { 0x1f, 0x0001 },
1842 { 0x10, 0xf41b },
1843 { 0x1f, 0x0000 }
1844 };
1845
4da19633 1846 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 1847}
1848
4da19633 1849static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 1850{
350f7596 1851 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 1852 { 0x1f, 0x0000 },
1853 { 0x1d, 0x0f00 },
1854 { 0x1f, 0x0002 },
1855 { 0x0c, 0x1ec8 },
1856 { 0x1f, 0x0000 }
1857 };
1858
4da19633 1859 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 1860}
1861
4da19633 1862static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 1863{
350f7596 1864 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 1865 { 0x1f, 0x0001 },
1866 { 0x1d, 0x3d98 },
1867 { 0x1f, 0x0000 }
1868 };
1869
4da19633 1870 rtl_writephy(tp, 0x1f, 0x0000);
1871 rtl_patchphy(tp, 0x14, 1 << 5);
1872 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 1873
4da19633 1874 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 1875}
1876
4da19633 1877static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 1878{
350f7596 1879 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 1880 { 0x1f, 0x0001 },
1881 { 0x12, 0x2300 },
867763c1
FR		 1882 { 0x1f, 0x0002 },
1883 { 0x00, 0x88d4 },
1884 { 0x01, 0x82b1 },
1885 { 0x03, 0x7002 },
1886 { 0x08, 0x9e30 },
1887 { 0x09, 0x01f0 },
1888 { 0x0a, 0x5500 },
1889 { 0x0c, 0x00c8 },
1890 { 0x1f, 0x0003 },
1891 { 0x12, 0xc096 },
1892 { 0x16, 0x000a },
f50d4275
FR		 1893 { 0x1f, 0x0000 },
1894 { 0x1f, 0x0000 },
1895 { 0x09, 0x2000 },
1896 { 0x09, 0x0000 }
867763c1
FR		 1897 };
1898
4da19633 1899 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 1900
4da19633 1901 rtl_patchphy(tp, 0x14, 1 << 5);
1902 rtl_patchphy(tp, 0x0d, 1 << 5);
1903 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 1904}
1905
4da19633 1906static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 1907{
350f7596 1908 static const struct phy_reg phy_reg_init[] = {
f50d4275 1909 { 0x1f, 0x0001 },
7da97ec9 1910 { 0x12, 0x2300 },
f50d4275
FR		 1911 { 0x03, 0x802f },
1912 { 0x02, 0x4f02 },
1913 { 0x01, 0x0409 },
1914 { 0x00, 0xf099 },
1915 { 0x04, 0x9800 },
1916 { 0x04, 0x9000 },
1917 { 0x1d, 0x3d98 },
7da97ec9
FR		 1918 { 0x1f, 0x0002 },
1919 { 0x0c, 0x7eb8 },
f50d4275
FR		 1920 { 0x06, 0x0761 },
1921 { 0x1f, 0x0003 },
1922 { 0x16, 0x0f0a },
7da97ec9
FR		 1923 { 0x1f, 0x0000 }
1924 };
1925
4da19633 1926 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 1927
4da19633 1928 rtl_patchphy(tp, 0x16, 1 << 0);
1929 rtl_patchphy(tp, 0x14, 1 << 5);
1930 rtl_patchphy(tp, 0x0d, 1 << 5);
1931 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 1932}
1933
4da19633 1934static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 1935{
350f7596 1936 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 1937 { 0x1f, 0x0001 },
1938 { 0x12, 0x2300 },
1939 { 0x1d, 0x3d98 },
1940 { 0x1f, 0x0002 },
1941 { 0x0c, 0x7eb8 },
1942 { 0x06, 0x5461 },
1943 { 0x1f, 0x0003 },
1944 { 0x16, 0x0f0a },
1945 { 0x1f, 0x0000 }
1946 };
1947
4da19633 1948 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 1949
4da19633 1950 rtl_patchphy(tp, 0x16, 1 << 0);
1951 rtl_patchphy(tp, 0x14, 1 << 5);
1952 rtl_patchphy(tp, 0x0d, 1 << 5);
1953 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 1954}
1955
4da19633 1956static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 1957{
4da19633 1958 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 1959}
1960
bca03d5f 1961static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 1962{
350f7596 1963 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 1964 /* Channel Estimation */
5b538df9 1965 { 0x1f, 0x0001 },
daf9df6d 1966 { 0x06, 0x4064 },
1967 { 0x07, 0x2863 },
1968 { 0x08, 0x059c },
1969 { 0x09, 0x26b4 },
1970 { 0x0a, 0x6a19 },
1971 { 0x0b, 0xdcc8 },
1972 { 0x10, 0xf06d },
1973 { 0x14, 0x7f68 },
1974 { 0x18, 0x7fd9 },
1975 { 0x1c, 0xf0ff },
1976 { 0x1d, 0x3d9c },
5b538df9 1977 { 0x1f, 0x0003 },
daf9df6d 1978 { 0x12, 0xf49f },
1979 { 0x13, 0x070b },
1980 { 0x1a, 0x05ad },
bca03d5f 1981 { 0x14, 0x94c0 },
1982
1983 /*
1984 * Tx Error Issue
1985 * enhance line driver power
1986 */
5b538df9 1987 { 0x1f, 0x0002 },
daf9df6d 1988 { 0x06, 0x5561 },
1989 { 0x1f, 0x0005 },
1990 { 0x05, 0x8332 },
bca03d5f 1991 { 0x06, 0x5561 },
1992
1993 /*
1994 * Can not link to 1Gbps with bad cable
1995 * Decrease SNR threshold form 21.07dB to 19.04dB
1996 */
1997 { 0x1f, 0x0001 },
1998 { 0x17, 0x0cc0 },
daf9df6d 1999
5b538df9 2000 { 0x1f, 0x0000 },
bca03d5f 2001 { 0x0d, 0xf880 }
daf9df6d 2002 };
bca03d5f 2003 void __iomem *ioaddr = tp->mmio_addr;
2004 const struct firmware *fw;
daf9df6d 2005
4da19633 2006 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 2007
bca03d5f 2008 /*
2009 * Rx Error Issue
2010 * Fine Tune Switching regulator parameter
2011 */
4da19633 2012 rtl_writephy(tp, 0x1f, 0x0002);
2013 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2014 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 2015
daf9df6d 2016 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2017 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2018 { 0x1f, 0x0002 },
2019 { 0x05, 0x669a },
2020 { 0x1f, 0x0005 },
2021 { 0x05, 0x8330 },
2022 { 0x06, 0x669a },
2023 { 0x1f, 0x0002 }
2024 };
2025 int val;
2026
4da19633 2027 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2028
4da19633 2029 val = rtl_readphy(tp, 0x0d);
daf9df6d 2030
2031 if ((val & 0x00ff) != 0x006c) {
350f7596 2032 static const u32 set[] = {
daf9df6d 2033 0x0065, 0x0066, 0x0067, 0x0068,
2034 0x0069, 0x006a, 0x006b, 0x006c
2035 };
2036 int i;
2037
4da19633 2038 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2039
2040 val &= 0xff00;
2041 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2042 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2043 }
2044 } else {
350f7596 2045 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2046 { 0x1f, 0x0002 },
2047 { 0x05, 0x6662 },
2048 { 0x1f, 0x0005 },
2049 { 0x05, 0x8330 },
2050 { 0x06, 0x6662 }
2051 };
2052
4da19633 2053 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2054 }
2055
bca03d5f 2056 /* RSET couple improve */
4da19633 2057 rtl_writephy(tp, 0x1f, 0x0002);
2058 rtl_patchphy(tp, 0x0d, 0x0300);
2059 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 2060
bca03d5f 2061 /* Fine tune PLL performance */
4da19633 2062 rtl_writephy(tp, 0x1f, 0x0002);
2063 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2064 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2065
4da19633 2066 rtl_writephy(tp, 0x1f, 0x0005);
2067 rtl_writephy(tp, 0x05, 0x001b);
2068 if (rtl_readphy(tp, 0x06) == 0xbf00 &&
bca03d5f 2069 request_firmware(&fw, FIRMWARE_8168D_1, &tp->pci_dev->dev) == 0) {
2070 rtl_phy_write_fw(tp, fw);
2071 release_firmware(fw);
2072 } else {
2073 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2074 }
2075
4da19633 2076 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2077}
2078
bca03d5f 2079static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2080{
350f7596 2081 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2082 /* Channel Estimation */
daf9df6d 2083 { 0x1f, 0x0001 },
2084 { 0x06, 0x4064 },
2085 { 0x07, 0x2863 },
2086 { 0x08, 0x059c },
2087 { 0x09, 0x26b4 },
2088 { 0x0a, 0x6a19 },
2089 { 0x0b, 0xdcc8 },
2090 { 0x10, 0xf06d },
2091 { 0x14, 0x7f68 },
2092 { 0x18, 0x7fd9 },
2093 { 0x1c, 0xf0ff },
2094 { 0x1d, 0x3d9c },
2095 { 0x1f, 0x0003 },
2096 { 0x12, 0xf49f },
2097 { 0x13, 0x070b },
2098 { 0x1a, 0x05ad },
2099 { 0x14, 0x94c0 },
2100
bca03d5f 2101 /*
2102 * Tx Error Issue
2103 * enhance line driver power
2104 */
daf9df6d 2105 { 0x1f, 0x0002 },
2106 { 0x06, 0x5561 },
2107 { 0x1f, 0x0005 },
2108 { 0x05, 0x8332 },
bca03d5f 2109 { 0x06, 0x5561 },
2110
2111 /*
2112 * Can not link to 1Gbps with bad cable
2113 * Decrease SNR threshold form 21.07dB to 19.04dB
2114 */
2115 { 0x1f, 0x0001 },
2116 { 0x17, 0x0cc0 },
daf9df6d 2117
2118 { 0x1f, 0x0000 },
bca03d5f 2119 { 0x0d, 0xf880 }
5b538df9 2120 };
bca03d5f 2121 void __iomem *ioaddr = tp->mmio_addr;
2122 const struct firmware *fw;
5b538df9 2123
4da19633 2124 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 2125
daf9df6d 2126 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2127 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2128 { 0x1f, 0x0002 },
2129 { 0x05, 0x669a },
5b538df9 2130 { 0x1f, 0x0005 },
daf9df6d 2131 { 0x05, 0x8330 },
2132 { 0x06, 0x669a },
2133
2134 { 0x1f, 0x0002 }
2135 };
2136 int val;
2137
4da19633 2138 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2139
4da19633 2140 val = rtl_readphy(tp, 0x0d);
daf9df6d 2141 if ((val & 0x00ff) != 0x006c) {
b6bc7650 2142 static const u32 set[] = {
daf9df6d 2143 0x0065, 0x0066, 0x0067, 0x0068,
2144 0x0069, 0x006a, 0x006b, 0x006c
2145 };
2146 int i;
2147
4da19633 2148 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2149
2150 val &= 0xff00;
2151 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2152 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2153 }
2154 } else {
350f7596 2155 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2156 { 0x1f, 0x0002 },
2157 { 0x05, 0x2642 },
5b538df9 2158 { 0x1f, 0x0005 },
daf9df6d 2159 { 0x05, 0x8330 },
2160 { 0x06, 0x2642 }
5b538df9
FR		 2161 };
2162
4da19633 2163 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2164 }
2165
bca03d5f 2166 /* Fine tune PLL performance */
4da19633 2167 rtl_writephy(tp, 0x1f, 0x0002);
2168 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2169 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2170
bca03d5f 2171 /* Switching regulator Slew rate */
4da19633 2172 rtl_writephy(tp, 0x1f, 0x0002);
2173 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 2174
4da19633 2175 rtl_writephy(tp, 0x1f, 0x0005);
2176 rtl_writephy(tp, 0x05, 0x001b);
2177 if (rtl_readphy(tp, 0x06) == 0xb300 &&
bca03d5f 2178 request_firmware(&fw, FIRMWARE_8168D_2, &tp->pci_dev->dev) == 0) {
2179 rtl_phy_write_fw(tp, fw);
2180 release_firmware(fw);
2181 } else {
2182 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2183 }
2184
4da19633 2185 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2186}
2187
4da19633 2188static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2189{
350f7596 2190 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2191 { 0x1f, 0x0002 },
2192 { 0x10, 0x0008 },
2193 { 0x0d, 0x006c },
2194
2195 { 0x1f, 0x0000 },
2196 { 0x0d, 0xf880 },
2197
2198 { 0x1f, 0x0001 },
2199 { 0x17, 0x0cc0 },
2200
2201 { 0x1f, 0x0001 },
2202 { 0x0b, 0xa4d8 },
2203 { 0x09, 0x281c },
2204 { 0x07, 0x2883 },
2205 { 0x0a, 0x6b35 },
2206 { 0x1d, 0x3da4 },
2207 { 0x1c, 0xeffd },
2208 { 0x14, 0x7f52 },
2209 { 0x18, 0x7fc6 },
2210 { 0x08, 0x0601 },
2211 { 0x06, 0x4063 },
2212 { 0x10, 0xf074 },
2213 { 0x1f, 0x0003 },
2214 { 0x13, 0x0789 },
2215 { 0x12, 0xf4bd },
2216 { 0x1a, 0x04fd },
2217 { 0x14, 0x84b0 },
2218 { 0x1f, 0x0000 },
2219 { 0x00, 0x9200 },
2220
2221 { 0x1f, 0x0005 },
2222 { 0x01, 0x0340 },
2223 { 0x1f, 0x0001 },
2224 { 0x04, 0x4000 },
2225 { 0x03, 0x1d21 },
2226 { 0x02, 0x0c32 },
2227 { 0x01, 0x0200 },
2228 { 0x00, 0x5554 },
2229 { 0x04, 0x4800 },
2230 { 0x04, 0x4000 },
2231 { 0x04, 0xf000 },
2232 { 0x03, 0xdf01 },
2233 { 0x02, 0xdf20 },
2234 { 0x01, 0x101a },
2235 { 0x00, 0xa0ff },
2236 { 0x04, 0xf800 },
2237 { 0x04, 0xf000 },
2238 { 0x1f, 0x0000 },
2239
2240 { 0x1f, 0x0007 },
2241 { 0x1e, 0x0023 },
2242 { 0x16, 0x0000 },
2243 { 0x1f, 0x0000 }
2244 };
2245
4da19633 2246 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2247}
2248
4da19633 2249static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 2250{
350f7596 2251 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 2252 { 0x1f, 0x0003 },
2253 { 0x08, 0x441d },
2254 { 0x01, 0x9100 },
2255 { 0x1f, 0x0000 }
2256 };
2257
4da19633 2258 rtl_writephy(tp, 0x1f, 0x0000);
2259 rtl_patchphy(tp, 0x11, 1 << 12);
2260 rtl_patchphy(tp, 0x19, 1 << 13);
2261 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 2262
4da19633 2263 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 2264}
2265
5615d9f1
FR		 2266static void rtl_hw_phy_config(struct net_device *dev)
2267{
2268 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 2269
2270 rtl8169_print_mac_version(tp);
2271
2272 switch (tp->mac_version) {
2273 case RTL_GIGA_MAC_VER_01:
2274 break;
2275 case RTL_GIGA_MAC_VER_02:
2276 case RTL_GIGA_MAC_VER_03:
4da19633 2277 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 2278 break;
2279 case RTL_GIGA_MAC_VER_04:
4da19633 2280 rtl8169sb_hw_phy_config(tp);
5615d9f1 2281 break;
2e955856 2282 case RTL_GIGA_MAC_VER_05:
4da19633 2283 rtl8169scd_hw_phy_config(tp);
2e955856 2284 break;
8c7006aa 2285 case RTL_GIGA_MAC_VER_06:
4da19633 2286 rtl8169sce_hw_phy_config(tp);
8c7006aa 2287 break;
2857ffb7
FR		 2288 case RTL_GIGA_MAC_VER_07:
2289 case RTL_GIGA_MAC_VER_08:
2290 case RTL_GIGA_MAC_VER_09:
4da19633 2291 rtl8102e_hw_phy_config(tp);
2857ffb7 2292 break;
236b8082 2293 case RTL_GIGA_MAC_VER_11:
4da19633 2294 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 2295 break;
2296 case RTL_GIGA_MAC_VER_12:
4da19633 2297 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 2298 break;
2299 case RTL_GIGA_MAC_VER_17:
4da19633 2300 rtl8168bef_hw_phy_config(tp);
236b8082 2301 break;
867763c1 2302 case RTL_GIGA_MAC_VER_18:
4da19633 2303 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 2304 break;
2305 case RTL_GIGA_MAC_VER_19:
4da19633 2306 rtl8168c_1_hw_phy_config(tp);
867763c1 2307 break;
7da97ec9 2308 case RTL_GIGA_MAC_VER_20:
4da19633 2309 rtl8168c_2_hw_phy_config(tp);
7da97ec9 2310 break;
197ff761 2311 case RTL_GIGA_MAC_VER_21:
4da19633 2312 rtl8168c_3_hw_phy_config(tp);
197ff761 2313 break;
6fb07058 2314 case RTL_GIGA_MAC_VER_22:
4da19633 2315 rtl8168c_4_hw_phy_config(tp);
6fb07058 2316 break;
ef3386f0 2317 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 2318 case RTL_GIGA_MAC_VER_24:
4da19633 2319 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 2320 break;
5b538df9 2321 case RTL_GIGA_MAC_VER_25:
bca03d5f 2322 rtl8168d_1_hw_phy_config(tp);
daf9df6d 2323 break;
2324 case RTL_GIGA_MAC_VER_26:
bca03d5f 2325 rtl8168d_2_hw_phy_config(tp);
daf9df6d 2326 break;
2327 case RTL_GIGA_MAC_VER_27:
4da19633 2328 rtl8168d_3_hw_phy_config(tp);
5b538df9 2329 break;
ef3386f0 2330
5615d9f1
FR		 2331 default:
2332 break;
2333 }
2334}
2335
1da177e4
LT		 2336static void rtl8169_phy_timer(unsigned long __opaque)
2337{
2338 struct net_device *dev = (struct net_device *)__opaque;
2339 struct rtl8169_private *tp = netdev_priv(dev);
2340 struct timer_list *timer = &tp->timer;
2341 void __iomem *ioaddr = tp->mmio_addr;
2342 unsigned long timeout = RTL8169_PHY_TIMEOUT;
2343
bcf0bf90 2344 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 2345
64e4bfb4 2346 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 2347 return;
2348
2349 spin_lock_irq(&tp->lock);
2350
4da19633 2351 if (tp->phy_reset_pending(tp)) {
5b0384f4 2352 /*
1da177e4
LT		 2353 * A busy loop could burn quite a few cycles on nowadays CPU.
2354 * Let's delay the execution of the timer for a few ticks.
2355 */
2356 timeout = HZ/10;
2357 goto out_mod_timer;
2358 }
2359
2360 if (tp->link_ok(ioaddr))
2361 goto out_unlock;
2362
bf82c189 2363 netif_warn(tp, link, dev, "PHY reset until link up\n");
1da177e4 2364
4da19633 2365 tp->phy_reset_enable(tp);
1da177e4
LT		 2366
2367out_mod_timer:
2368 mod_timer(timer, jiffies + timeout);
2369out_unlock:
2370 spin_unlock_irq(&tp->lock);
2371}
2372
2373static inline void rtl8169_delete_timer(struct net_device *dev)
2374{
2375 struct rtl8169_private *tp = netdev_priv(dev);
2376 struct timer_list *timer = &tp->timer;
2377
e179bb7b 2378 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 2379 return;
2380
2381 del_timer_sync(timer);
2382}
2383
2384static inline void rtl8169_request_timer(struct net_device *dev)
2385{
2386 struct rtl8169_private *tp = netdev_priv(dev);
2387 struct timer_list *timer = &tp->timer;
2388
e179bb7b 2389 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 2390 return;
2391
2efa53f3 2392 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1da177e4
LT		 2393}
2394
2395#ifdef CONFIG_NET_POLL_CONTROLLER
2396/*
2397 * Polling 'interrupt' - used by things like netconsole to send skbs
2398 * without having to re-enable interrupts. It's not called while
2399 * the interrupt routine is executing.
2400 */
2401static void rtl8169_netpoll(struct net_device *dev)
2402{
2403 struct rtl8169_private *tp = netdev_priv(dev);
2404 struct pci_dev *pdev = tp->pci_dev;
2405
2406 disable_irq(pdev->irq);
7d12e780 2407 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 2408 enable_irq(pdev->irq);
2409}
2410#endif
2411
2412static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2413 void __iomem *ioaddr)
2414{
2415 iounmap(ioaddr);
2416 pci_release_regions(pdev);
87aeec76 2417 pci_clear_mwi(pdev);
1da177e4
LT		 2418 pci_disable_device(pdev);
2419 free_netdev(dev);
2420}
2421
bf793295
FR		 2422static void rtl8169_phy_reset(struct net_device *dev,
2423 struct rtl8169_private *tp)
2424{
07d3f51f 2425 unsigned int i;
bf793295 2426
4da19633 2427 tp->phy_reset_enable(tp);
bf793295 2428 for (i = 0; i < 100; i++) {
4da19633 2429 if (!tp->phy_reset_pending(tp))
bf793295
FR		 2430 return;
2431 msleep(1);
2432 }
bf82c189 2433 netif_err(tp, link, dev, "PHY reset failed\n");
bf793295
FR		 2434}
2435
4ff96fa6
FR		 2436static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2437{
2438 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 2439
5615d9f1 2440 rtl_hw_phy_config(dev);
4ff96fa6 2441
77332894
MS		 2442 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2443 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2444 RTL_W8(0x82, 0x01);
2445 }
4ff96fa6 2446
6dccd16b
FR		 2447 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2448
2449 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2450 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 2451
bcf0bf90 2452 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 2453 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2454 RTL_W8(0x82, 0x01);
2455 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4da19633 2456 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 2457 }
2458
bf793295
FR		 2459 rtl8169_phy_reset(dev, tp);
2460
901dda2b
FR		 2461 /*
2462 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
2463 * only 8101. Don't panic.
2464 */
2465 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
4ff96fa6 2466
bf82c189
JP		 2467 if (RTL_R8(PHYstatus) & TBI_Enable)
2468 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 2469}
2470
773d2021
FR		 2471static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2472{
2473 void __iomem *ioaddr = tp->mmio_addr;
2474 u32 high;
2475 u32 low;
2476
2477 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2478 high = addr[4] | (addr[5] << 8);
2479
2480 spin_lock_irq(&tp->lock);
2481
2482 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 2483
773d2021 2484 RTL_W32(MAC4, high);
908ba2bf 2485 RTL_R32(MAC4);
2486
78f1cd02 2487 RTL_W32(MAC0, low);
908ba2bf 2488 RTL_R32(MAC0);
2489
773d2021
FR		 2490 RTL_W8(Cfg9346, Cfg9346_Lock);
2491
2492 spin_unlock_irq(&tp->lock);
2493}
2494
2495static int rtl_set_mac_address(struct net_device *dev, void *p)
2496{
2497 struct rtl8169_private *tp = netdev_priv(dev);
2498 struct sockaddr *addr = p;
2499
2500 if (!is_valid_ether_addr(addr->sa_data))
2501 return -EADDRNOTAVAIL;
2502
2503 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2504
2505 rtl_rar_set(tp, dev->dev_addr);
2506
2507 return 0;
2508}
2509
5f787a1a
FR		 2510static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2511{
2512 struct rtl8169_private *tp = netdev_priv(dev);
2513 struct mii_ioctl_data *data = if_mii(ifr);
2514
8b4ab28d
FR		 2515 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2516}
5f787a1a 2517
8b4ab28d
FR		 2518static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2519{
5f787a1a
FR		 2520 switch (cmd) {
2521 case SIOCGMIIPHY:
2522 data->phy_id = 32; /* Internal PHY */
2523 return 0;
2524
2525 case SIOCGMIIREG:
4da19633 2526 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 2527 return 0;
2528
2529 case SIOCSMIIREG:
4da19633 2530 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 2531 return 0;
2532 }
2533 return -EOPNOTSUPP;
2534}
2535
8b4ab28d
FR		 2536static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2537{
2538 return -EOPNOTSUPP;
2539}
2540
0e485150
FR		 2541static const struct rtl_cfg_info {
2542 void (*hw_start)(struct net_device *);
2543 unsigned int region;
2544 unsigned int align;
2545 u16 intr_event;
2546 u16 napi_event;
ccdffb9a 2547 unsigned features;
f21b75e9 2548 u8 default_ver;
0e485150
FR		 2549} rtl_cfg_infos [] = {
2550 [RTL_CFG_0] = {
2551 .hw_start = rtl_hw_start_8169,
2552 .region = 1,
e9f63f30 2553 .align = 0,
0e485150
FR		 2554 .intr_event = SYSErr | LinkChg | RxOverflow |
2555 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 2556 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2557 .features = RTL_FEATURE_GMII,
2558 .default_ver = RTL_GIGA_MAC_VER_01,
0e485150
FR		 2559 },
2560 [RTL_CFG_1] = {
2561 .hw_start = rtl_hw_start_8168,
2562 .region = 2,
2563 .align = 8,
53f57357 2564 .intr_event = SYSErr | LinkChg | RxOverflow |
0e485150 2565 TxErr | TxOK | RxOK | RxErr,
fbac58fc 2566 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2567 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2568 .default_ver = RTL_GIGA_MAC_VER_11,
0e485150
FR		 2569 },
2570 [RTL_CFG_2] = {
2571 .hw_start = rtl_hw_start_8101,
2572 .region = 2,
2573 .align = 8,
2574 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2575 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 2576 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2577 .features = RTL_FEATURE_MSI,
2578 .default_ver = RTL_GIGA_MAC_VER_13,
0e485150
FR		 2579 }
2580};
2581
fbac58fc
FR		 2582/* Cfg9346_Unlock assumed. */
2583static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2584 const struct rtl_cfg_info *cfg)
2585{
2586 unsigned msi = 0;
2587 u8 cfg2;
2588
2589 cfg2 = RTL_R8(Config2) & ~MSIEnable;
ccdffb9a 2590 if (cfg->features & RTL_FEATURE_MSI) {
fbac58fc
FR		 2591 if (pci_enable_msi(pdev)) {
2592 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2593 } else {
2594 cfg2 |= MSIEnable;
2595 msi = RTL_FEATURE_MSI;
2596 }
2597 }
2598 RTL_W8(Config2, cfg2);
2599 return msi;
2600}
2601
2602static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2603{
2604 if (tp->features & RTL_FEATURE_MSI) {
2605 pci_disable_msi(pdev);
2606 tp->features &= ~RTL_FEATURE_MSI;
2607 }
2608}
2609
8b4ab28d
FR		 2610static const struct net_device_ops rtl8169_netdev_ops = {
2611 .ndo_open = rtl8169_open,
2612 .ndo_stop = rtl8169_close,
2613 .ndo_get_stats = rtl8169_get_stats,
00829823 2614 .ndo_start_xmit = rtl8169_start_xmit,
8b4ab28d
FR		 2615 .ndo_tx_timeout = rtl8169_tx_timeout,
2616 .ndo_validate_addr = eth_validate_addr,
2617 .ndo_change_mtu = rtl8169_change_mtu,
2618 .ndo_set_mac_address = rtl_set_mac_address,
2619 .ndo_do_ioctl = rtl8169_ioctl,
2620 .ndo_set_multicast_list = rtl_set_rx_mode,
2621#ifdef CONFIG_R8169_VLAN
2622 .ndo_vlan_rx_register = rtl8169_vlan_rx_register,
2623#endif
2624#ifdef CONFIG_NET_POLL_CONTROLLER
2625 .ndo_poll_controller = rtl8169_netpoll,
2626#endif
2627
2628};
2629
c0e45c1c 2630static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
2631{
2632 struct mdio_ops *ops = &tp->mdio_ops;
2633
2634 switch (tp->mac_version) {
2635 case RTL_GIGA_MAC_VER_27:
2636 ops->write = r8168dp_1_mdio_write;
2637 ops->read = r8168dp_1_mdio_read;
2638 break;
2639 default:
2640 ops->write = r8169_mdio_write;
2641 ops->read = r8169_mdio_read;
2642 break;
2643 }
2644}
2645
065c27c1 2646static void r810x_phy_power_down(struct rtl8169_private *tp)
2647{
2648 rtl_writephy(tp, 0x1f, 0x0000);
2649 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
2650}
2651
2652static void r810x_phy_power_up(struct rtl8169_private *tp)
2653{
2654 rtl_writephy(tp, 0x1f, 0x0000);
2655 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
2656}
2657
2658static void r810x_pll_power_down(struct rtl8169_private *tp)
2659{
2660 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
2661 rtl_writephy(tp, 0x1f, 0x0000);
2662 rtl_writephy(tp, MII_BMCR, 0x0000);
2663 return;
2664 }
2665
2666 r810x_phy_power_down(tp);
2667}
2668
2669static void r810x_pll_power_up(struct rtl8169_private *tp)
2670{
2671 r810x_phy_power_up(tp);
2672}
2673
2674static void r8168_phy_power_up(struct rtl8169_private *tp)
2675{
2676 rtl_writephy(tp, 0x1f, 0x0000);
2677 rtl_writephy(tp, 0x0e, 0x0000);
2678 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
2679}
2680
2681static void r8168_phy_power_down(struct rtl8169_private *tp)
2682{
2683 rtl_writephy(tp, 0x1f, 0x0000);
2684 rtl_writephy(tp, 0x0e, 0x0200);
2685 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
2686}
2687
2688static void r8168_pll_power_down(struct rtl8169_private *tp)
2689{
2690 void __iomem *ioaddr = tp->mmio_addr;
2691
2692 if (tp->mac_version == RTL_GIGA_MAC_VER_27)
2693 return;
2694
2695 if (((tp->mac_version == RTL_GIGA_MAC_VER_23) ||
2696 (tp->mac_version == RTL_GIGA_MAC_VER_24)) &&
2697 (RTL_R16(CPlusCmd) & ASF)) {
2698 return;
2699 }
2700
2701 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
2702 rtl_writephy(tp, 0x1f, 0x0000);
2703 rtl_writephy(tp, MII_BMCR, 0x0000);
2704
2705 RTL_W32(RxConfig, RTL_R32(RxConfig) |
2706 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
2707 return;
2708 }
2709
2710 r8168_phy_power_down(tp);
2711
2712 switch (tp->mac_version) {
2713 case RTL_GIGA_MAC_VER_25:
2714 case RTL_GIGA_MAC_VER_26:
2715 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
2716 break;
2717 }
2718}
2719
2720static void r8168_pll_power_up(struct rtl8169_private *tp)
2721{
2722 void __iomem *ioaddr = tp->mmio_addr;
2723
2724 if (tp->mac_version == RTL_GIGA_MAC_VER_27)
2725 return;
2726
2727 switch (tp->mac_version) {
2728 case RTL_GIGA_MAC_VER_25:
2729 case RTL_GIGA_MAC_VER_26:
2730 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
2731 break;
2732 }
2733
2734 r8168_phy_power_up(tp);
2735}
2736
2737static void rtl_pll_power_op(struct rtl8169_private *tp,
2738 void (*op)(struct rtl8169_private *))
2739{
2740 if (op)
2741 op(tp);
2742}
2743
2744static void rtl_pll_power_down(struct rtl8169_private *tp)
2745{
2746 rtl_pll_power_op(tp, tp->pll_power_ops.down);
2747}
2748
2749static void rtl_pll_power_up(struct rtl8169_private *tp)
2750{
2751 rtl_pll_power_op(tp, tp->pll_power_ops.up);
2752}
2753
2754static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
2755{
2756 struct pll_power_ops *ops = &tp->pll_power_ops;
2757
2758 switch (tp->mac_version) {
2759 case RTL_GIGA_MAC_VER_07:
2760 case RTL_GIGA_MAC_VER_08:
2761 case RTL_GIGA_MAC_VER_09:
2762 case RTL_GIGA_MAC_VER_10:
2763 case RTL_GIGA_MAC_VER_16:
2764 ops->down = r810x_pll_power_down;
2765 ops->up = r810x_pll_power_up;
2766 break;
2767
2768 case RTL_GIGA_MAC_VER_11:
2769 case RTL_GIGA_MAC_VER_12:
2770 case RTL_GIGA_MAC_VER_17:
2771 case RTL_GIGA_MAC_VER_18:
2772 case RTL_GIGA_MAC_VER_19:
2773 case RTL_GIGA_MAC_VER_20:
2774 case RTL_GIGA_MAC_VER_21:
2775 case RTL_GIGA_MAC_VER_22:
2776 case RTL_GIGA_MAC_VER_23:
2777 case RTL_GIGA_MAC_VER_24:
2778 case RTL_GIGA_MAC_VER_25:
2779 case RTL_GIGA_MAC_VER_26:
2780 case RTL_GIGA_MAC_VER_27:
2781 ops->down = r8168_pll_power_down;
2782 ops->up = r8168_pll_power_up;
2783 break;
2784
2785 default:
2786 ops->down = NULL;
2787 ops->up = NULL;
2788 break;
2789 }
2790}
2791
1da177e4 2792static int __devinit
4ff96fa6 2793rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 2794{
0e485150
FR		 2795 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
2796 const unsigned int region = cfg->region;
1da177e4 2797 struct rtl8169_private *tp;
ccdffb9a 2798 struct mii_if_info *mii;
4ff96fa6
FR		 2799 struct net_device *dev;
2800 void __iomem *ioaddr;
07d3f51f
FR		 2801 unsigned int i;
2802 int rc;
1da177e4 2803
4ff96fa6
FR		 2804 if (netif_msg_drv(&debug)) {
2805 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
2806 MODULENAME, RTL8169_VERSION);
2807 }
1da177e4 2808
1da177e4 2809 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 2810 if (!dev) {
b57b7e5a 2811 if (netif_msg_drv(&debug))
9b91cf9d 2812 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 2813 rc = -ENOMEM;
2814 goto out;
1da177e4
LT		 2815 }
2816
1da177e4 2817 SET_NETDEV_DEV(dev, &pdev->dev);
8b4ab28d 2818 dev->netdev_ops = &rtl8169_netdev_ops;
1da177e4 2819 tp = netdev_priv(dev);
c4028958 2820 tp->dev = dev;
21e197f2 2821 tp->pci_dev = pdev;
b57b7e5a 2822 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4 2823
ccdffb9a
FR		 2824 mii = &tp->mii;
2825 mii->dev = dev;
2826 mii->mdio_read = rtl_mdio_read;
2827 mii->mdio_write = rtl_mdio_write;
2828 mii->phy_id_mask = 0x1f;
2829 mii->reg_num_mask = 0x1f;
2830 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
2831
1da177e4
LT		 2832 /* enable device (incl. PCI PM wakeup and hotplug setup) */
2833 rc = pci_enable_device(pdev);
b57b7e5a 2834 if (rc < 0) {
bf82c189 2835 netif_err(tp, probe, dev, "enable failure\n");
4ff96fa6 2836 goto err_out_free_dev_1;
1da177e4
LT		 2837 }
2838
87aeec76 2839 if (pci_set_mwi(pdev) < 0)
2840 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
1da177e4 2841
1da177e4 2842 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 2843 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
bf82c189
JP		 2844 netif_err(tp, probe, dev,
2845 "region #%d not an MMIO resource, aborting\n",
2846 region);
1da177e4 2847 rc = -ENODEV;
87aeec76 2848 goto err_out_mwi_2;
1da177e4 2849 }
4ff96fa6 2850
1da177e4 2851 /* check for weird/broken PCI region reporting */
bcf0bf90 2852 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
bf82c189
JP		 2853 netif_err(tp, probe, dev,
2854 "Invalid PCI region size(s), aborting\n");
1da177e4 2855 rc = -ENODEV;
87aeec76 2856 goto err_out_mwi_2;
1da177e4
LT		 2857 }
2858
2859 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 2860 if (rc < 0) {
bf82c189 2861 netif_err(tp, probe, dev, "could not request regions\n");
87aeec76 2862 goto err_out_mwi_2;
1da177e4
LT		 2863 }
2864
2865 tp->cp_cmd = PCIMulRW | RxChkSum;
2866
2867 if ((sizeof(dma_addr_t) > 4) &&
4300e8c7 2868 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
1da177e4
LT		 2869 tp->cp_cmd |= PCIDAC;
2870 dev->features |= NETIF_F_HIGHDMA;
2871 } else {
284901a9 2872 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 2873 if (rc < 0) {
bf82c189 2874 netif_err(tp, probe, dev, "DMA configuration failed\n");
87aeec76 2875 goto err_out_free_res_3;
1da177e4
LT		 2876 }
2877 }
2878
1da177e4 2879 /* ioremap MMIO region */
bcf0bf90 2880 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 2881 if (!ioaddr) {
bf82c189 2882 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
1da177e4 2883 rc = -EIO;
87aeec76 2884 goto err_out_free_res_3;
1da177e4
LT		 2885 }
2886
4300e8c7
DM		 2887 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2888 if (!tp->pcie_cap)
2889 netif_info(tp, probe, dev, "no PCI Express capability\n");
2890
d78ad8cb 2891 RTL_W16(IntrMask, 0x0000);
1da177e4
LT		 2892
2893 /* Soft reset the chip. */
2894 RTL_W8(ChipCmd, CmdReset);
2895
2896 /* Check that the chip has finished the reset. */
07d3f51f 2897 for (i = 0; i < 100; i++) {
1da177e4
LT		 2898 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2899 break;
b518fa8e 2900 msleep_interruptible(1);
1da177e4
LT		 2901 }
2902
d78ad8cb
KW		 2903 RTL_W16(IntrStatus, 0xffff);
2904
ca52efd5 2905 pci_set_master(pdev);
2906
1da177e4
LT		 2907 /* Identify chip attached to board */
2908 rtl8169_get_mac_version(tp, ioaddr);
1da177e4 2909
c0e45c1c 2910 rtl_init_mdio_ops(tp);
065c27c1 2911 rtl_init_pll_power_ops(tp);
c0e45c1c 2912
f21b75e9
JD		 2913 /* Use appropriate default if unknown */
2914 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
bf82c189
JP		 2915 netif_notice(tp, probe, dev,
2916 "unknown MAC, using family default\n");
f21b75e9
JD		 2917 tp->mac_version = cfg->default_ver;
2918 }
2919
1da177e4 2920 rtl8169_print_mac_version(tp);
1da177e4 2921
cee60c37 2922 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
1da177e4
LT		 2923 if (tp->mac_version == rtl_chip_info[i].mac_version)
2924 break;
2925 }
cee60c37 2926 if (i == ARRAY_SIZE(rtl_chip_info)) {
f21b75e9
JD		 2927 dev_err(&pdev->dev,
2928 "driver bug, MAC version not found in rtl_chip_info\n");
87aeec76 2929 goto err_out_msi_4;
1da177e4
LT		 2930 }
2931 tp->chipset = i;
2932
5d06a99f
FR		 2933 RTL_W8(Cfg9346, Cfg9346_Unlock);
2934 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
2935 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
20037fa4
BP		 2936 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
2937 tp->features |= RTL_FEATURE_WOL;
2938 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
2939 tp->features |= RTL_FEATURE_WOL;
fbac58fc 2940 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
5d06a99f
FR		 2941 RTL_W8(Cfg9346, Cfg9346_Lock);
2942
66ec5d4f
FR		 2943 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
2944 (RTL_R8(PHYstatus) & TBI_Enable)) {
1da177e4
LT		 2945 tp->set_speed = rtl8169_set_speed_tbi;
2946 tp->get_settings = rtl8169_gset_tbi;
2947 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
2948 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
2949 tp->link_ok = rtl8169_tbi_link_ok;
8b4ab28d 2950 tp->do_ioctl = rtl_tbi_ioctl;
1da177e4 2951
64e4bfb4 2952 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1da177e4
LT		 2953 } else {
2954 tp->set_speed = rtl8169_set_speed_xmii;
2955 tp->get_settings = rtl8169_gset_xmii;
2956 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
2957 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
2958 tp->link_ok = rtl8169_xmii_link_ok;
8b4ab28d 2959 tp->do_ioctl = rtl_xmii_ioctl;
1da177e4
LT		 2960 }
2961
df58ef51
FR		 2962 spin_lock_init(&tp->lock);
2963
738e1e69
PV		 2964 tp->mmio_addr = ioaddr;
2965
7bf6bf48 2966 /* Get MAC address */
1da177e4
LT		 2967 for (i = 0; i < MAC_ADDR_LEN; i++)
2968 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 2969 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4 2970
1da177e4 2971 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1da177e4
LT		 2972 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
2973 dev->irq = pdev->irq;
2974 dev->base_addr = (unsigned long) ioaddr;
1da177e4 2975
bea3348e 2976 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4
LT		 2977
2978#ifdef CONFIG_R8169_VLAN
2979 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4 2980#endif
2edae08e 2981 dev->features |= NETIF_F_GRO;
1da177e4
LT		 2982
2983 tp->intr_mask = 0xffff;
0e485150
FR		 2984 tp->hw_start = cfg->hw_start;
2985 tp->intr_event = cfg->intr_event;
2986 tp->napi_event = cfg->napi_event;
1da177e4 2987
2efa53f3
FR		 2988 init_timer(&tp->timer);
2989 tp->timer.data = (unsigned long) dev;
2990 tp->timer.function = rtl8169_phy_timer;
2991
1da177e4 2992 rc = register_netdev(dev);
4ff96fa6 2993 if (rc < 0)
87aeec76 2994 goto err_out_msi_4;
1da177e4
LT		 2995
2996 pci_set_drvdata(pdev, dev);
2997
bf82c189
JP		 2998 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
2999 rtl_chip_info[tp->chipset].name,
3000 dev->base_addr, dev->dev_addr,
3001 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
1da177e4 3002
b646d900 3003 if (tp->mac_version == RTL_GIGA_MAC_VER_27)
3004 rtl8168_driver_start(tp);
3005
4ff96fa6 3006 rtl8169_init_phy(dev, tp);
05af2142
SW		 3007
3008 /*
3009 * Pretend we are using VLANs; This bypasses a nasty bug where
3010 * Interrupts stop flowing on high load on 8110SCd controllers.
3011 */
3012 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3013 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | RxVlan);
3014
8b76ab39 3015 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
1da177e4 3016
f3ec4f87
AS		 3017 if (pci_dev_run_wake(pdev))
3018 pm_runtime_put_noidle(&pdev->dev);
e1759441 3019
4ff96fa6
FR		 3020out:
3021 return rc;
1da177e4 3022
87aeec76 3023err_out_msi_4:
fbac58fc 3024 rtl_disable_msi(pdev, tp);
4ff96fa6 3025 iounmap(ioaddr);
87aeec76 3026err_out_free_res_3:
4ff96fa6 3027 pci_release_regions(pdev);
87aeec76 3028err_out_mwi_2:
4ff96fa6 3029 pci_clear_mwi(pdev);
4ff96fa6
FR		 3030 pci_disable_device(pdev);
3031err_out_free_dev_1:
3032 free_netdev(dev);
3033 goto out;
1da177e4
LT		 3034}
3035
07d3f51f 3036static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 3037{
3038 struct net_device *dev = pci_get_drvdata(pdev);
3039 struct rtl8169_private *tp = netdev_priv(dev);
3040
b646d900 3041 if (tp->mac_version == RTL_GIGA_MAC_VER_27)
3042 rtl8168_driver_stop(tp);
3043
23f333a2 3044 cancel_delayed_work_sync(&tp->task);
eb2a021c 3045
1da177e4 3046 unregister_netdev(dev);
cc098dc7 3047
f3ec4f87
AS		 3048 if (pci_dev_run_wake(pdev))
3049 pm_runtime_get_noresume(&pdev->dev);
e1759441 3050
cc098dc7
IV		 3051 /* restore original MAC address */
3052 rtl_rar_set(tp, dev->perm_addr);
3053
fbac58fc 3054 rtl_disable_msi(pdev, tp);
1da177e4
LT		 3055 rtl8169_release_board(pdev, dev, tp->mmio_addr);
3056 pci_set_drvdata(pdev, NULL);
3057}
3058
1da177e4
LT		 3059static int rtl8169_open(struct net_device *dev)
3060{
3061 struct rtl8169_private *tp = netdev_priv(dev);
3062 struct pci_dev *pdev = tp->pci_dev;
99f252b0 3063 int retval = -ENOMEM;
1da177e4 3064
e1759441 3065 pm_runtime_get_sync(&pdev->dev);
1da177e4 3066
1da177e4
LT		 3067 /*
3068 * Rx and Tx desscriptors needs 256 bytes alignment.
82553bb6 3069 * dma_alloc_coherent provides more.
1da177e4 3070 */
82553bb6
SG		 3071 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3072 &tp->TxPhyAddr, GFP_KERNEL);
1da177e4 3073 if (!tp->TxDescArray)
e1759441 3074 goto err_pm_runtime_put;
1da177e4 3075
82553bb6
SG		 3076 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3077 &tp->RxPhyAddr, GFP_KERNEL);
1da177e4 3078 if (!tp->RxDescArray)
99f252b0 3079 goto err_free_tx_0;
1da177e4
LT		 3080
3081 retval = rtl8169_init_ring(dev);
3082 if (retval < 0)
99f252b0 3083 goto err_free_rx_1;
1da177e4 3084
c4028958 3085 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 3086
99f252b0
FR		 3087 smp_mb();
3088
fbac58fc
FR		 3089 retval = request_irq(dev->irq, rtl8169_interrupt,
3090 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 3091 dev->name, dev);
3092 if (retval < 0)
3093 goto err_release_ring_2;
3094
bea3348e 3095 napi_enable(&tp->napi);
bea3348e 3096
065c27c1 3097 rtl_pll_power_up(tp);
3098
07ce4064 3099 rtl_hw_start(dev);
1da177e4
LT		 3100
3101 rtl8169_request_timer(dev);
3102
e1759441
RW		 3103 tp->saved_wolopts = 0;
3104 pm_runtime_put_noidle(&pdev->dev);
3105
1da177e4
LT		 3106 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
3107out:
3108 return retval;
3109
99f252b0
FR		 3110err_release_ring_2:
3111 rtl8169_rx_clear(tp);
3112err_free_rx_1:
82553bb6
SG		 3113 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3114 tp->RxPhyAddr);
e1759441 3115 tp->RxDescArray = NULL;
99f252b0 3116err_free_tx_0:
82553bb6
SG		 3117 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3118 tp->TxPhyAddr);
e1759441
RW		 3119 tp->TxDescArray = NULL;
3120err_pm_runtime_put:
3121 pm_runtime_put_noidle(&pdev->dev);
1da177e4
LT		 3122 goto out;
3123}
3124
3125static void rtl8169_hw_reset(void __iomem *ioaddr)
3126{
3127 /* Disable interrupts */
3128 rtl8169_irq_mask_and_ack(ioaddr);
3129
3130 /* Reset the chipset */
3131 RTL_W8(ChipCmd, CmdReset);
3132
3133 /* PCI commit */
3134 RTL_R8(ChipCmd);
3135}
3136
7f796d83 3137static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 3138{
3139 void __iomem *ioaddr = tp->mmio_addr;
3140 u32 cfg = rtl8169_rx_config;
3141
3142 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3143 RTL_W32(RxConfig, cfg);
3144
3145 /* Set DMA burst size and Interframe Gap Time */
3146 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3147 (InterFrameGap << TxInterFrameGapShift));
3148}
3149
07ce4064 3150static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 3151{
3152 struct rtl8169_private *tp = netdev_priv(dev);
3153 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 3154 unsigned int i;
1da177e4
LT		 3155
3156 /* Soft reset the chip. */
3157 RTL_W8(ChipCmd, CmdReset);
3158
3159 /* Check that the chip has finished the reset. */
07d3f51f 3160 for (i = 0; i < 100; i++) {
1da177e4
LT		 3161 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3162 break;
b518fa8e 3163 msleep_interruptible(1);
1da177e4
LT		 3164 }
3165
07ce4064
FR		 3166 tp->hw_start(dev);
3167
07ce4064
FR		 3168 netif_start_queue(dev);
3169}
3170
3171
7f796d83
FR		 3172static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3173 void __iomem *ioaddr)
3174{
3175 /*
3176 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3177 * register to be written before TxDescAddrLow to work.
3178 * Switching from MMIO to I/O access fixes the issue as well.
3179 */
3180 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 3181 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 3182 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 3183 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 3184}
3185
3186static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3187{
3188 u16 cmd;
3189
3190 cmd = RTL_R16(CPlusCmd);
3191 RTL_W16(CPlusCmd, cmd);
3192 return cmd;
3193}
3194
fdd7b4c3 3195static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 3196{
3197 /* Low hurts. Let's disable the filtering. */
207d6e87 3198 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 3199}
3200
6dccd16b
FR		 3201static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3202{
350f7596 3203 static const struct {
6dccd16b
FR		 3204 u32 mac_version;
3205 u32 clk;
3206 u32 val;
3207 } cfg2_info [] = {
3208 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3209 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3210 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3211 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3212 }, *p = cfg2_info;
3213 unsigned int i;
3214 u32 clk;
3215
3216 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 3217 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 3218 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3219 RTL_W32(0x7c, p->val);
3220 break;
3221 }
3222 }
3223}
3224
07ce4064
FR		 3225static void rtl_hw_start_8169(struct net_device *dev)
3226{
3227 struct rtl8169_private *tp = netdev_priv(dev);
3228 void __iomem *ioaddr = tp->mmio_addr;
3229 struct pci_dev *pdev = tp->pci_dev;
07ce4064 3230
9cb427b6
FR		 3231 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3232 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3233 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3234 }
3235
1da177e4 3236 RTL_W8(Cfg9346, Cfg9346_Unlock);
9cb427b6
FR		 3237 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3238 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3239 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3240 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3241 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3242
f0298f81 3243 RTL_W8(EarlyTxThres, NoEarlyTx);
1da177e4 3244
6f0333b8 3245 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
1da177e4 3246
c946b304
FR		 3247 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3248 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3249 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3250 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3251 rtl_set_rx_tx_config_registers(tp);
1da177e4 3252
7f796d83 3253 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 3254
bcf0bf90
FR		 3255 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3256 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
06fa7358 3257 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 3258 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 3259 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 3260 }
3261
bcf0bf90
FR		 3262 RTL_W16(CPlusCmd, tp->cp_cmd);
3263
6dccd16b
FR		 3264 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3265
1da177e4
LT		 3266 /*
3267 * Undocumented corner. Supposedly:
3268 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3269 */
3270 RTL_W16(IntrMitigate, 0x0000);
3271
7f796d83 3272 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 3273
c946b304
FR		 3274 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
3275 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
3276 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
3277 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
3278 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3279 rtl_set_rx_tx_config_registers(tp);
3280 }
3281
1da177e4 3282 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 3283
3284 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3285 RTL_R8(IntrMask);
1da177e4
LT		 3286
3287 RTL_W32(RxMissed, 0);
3288
07ce4064 3289 rtl_set_rx_mode(dev);
1da177e4
LT		 3290
3291 /* no early-rx interrupts */
3292 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 3293
3294 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 3295 RTL_W16(IntrMask, tp->intr_event);
07ce4064 3296}
1da177e4 3297
9c14ceaf 3298static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
458a9f61 3299{
9c14ceaf
FR		 3300 struct net_device *dev = pci_get_drvdata(pdev);
3301 struct rtl8169_private *tp = netdev_priv(dev);
3302 int cap = tp->pcie_cap;
3303
3304 if (cap) {
3305 u16 ctl;
458a9f61 3306
9c14ceaf
FR		 3307 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3308 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3309 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3310 }
458a9f61
FR		 3311}
3312
dacf8154
FR		 3313static void rtl_csi_access_enable(void __iomem *ioaddr)
3314{
3315 u32 csi;
3316
3317 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
3318 rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
3319}
3320
3321struct ephy_info {
3322 unsigned int offset;
3323 u16 mask;
3324 u16 bits;
3325};
3326
350f7596 3327static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
dacf8154
FR		 3328{
3329 u16 w;
3330
3331 while (len-- > 0) {
3332 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3333 rtl_ephy_write(ioaddr, e->offset, w);
3334 e++;
3335 }
3336}
3337
b726e493
FR		 3338static void rtl_disable_clock_request(struct pci_dev *pdev)
3339{
3340 struct net_device *dev = pci_get_drvdata(pdev);
3341 struct rtl8169_private *tp = netdev_priv(dev);
3342 int cap = tp->pcie_cap;
3343
3344 if (cap) {
3345 u16 ctl;
3346
3347 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3348 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3349 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3350 }
3351}
3352
3353#define R8168_CPCMD_QUIRK_MASK (\
3354 EnableBist | \
3355 Mac_dbgo_oe | \
3356 Force_half_dup | \
3357 Force_rxflow_en | \
3358 Force_txflow_en | \
3359 Cxpl_dbg_sel | \
3360 ASF | \
3361 PktCntrDisable | \
3362 Mac_dbgo_sel)
3363
219a1e9d
FR		 3364static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3365{
b726e493
FR		 3366 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3367
3368 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3369
2e68ae44
FR		 3370 rtl_tx_performance_tweak(pdev,
3371 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
219a1e9d
FR		 3372}
3373
3374static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3375{
3376 rtl_hw_start_8168bb(ioaddr, pdev);
b726e493 3377
f0298f81 3378 RTL_W8(MaxTxPacketSize, TxPacketMax);
b726e493
FR		 3379
3380 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 3381}
3382
3383static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3384{
b726e493
FR		 3385 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3386
3387 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3388
219a1e9d 3389 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 3390
3391 rtl_disable_clock_request(pdev);
3392
3393 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 3394}
3395
ef3386f0 3396static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
219a1e9d 3397{
350f7596 3398 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 3399 { 0x01, 0, 0x0001 },
3400 { 0x02, 0x0800, 0x1000 },
3401 { 0x03, 0, 0x0042 },
3402 { 0x06, 0x0080, 0x0000 },
3403 { 0x07, 0, 0x2000 }
3404 };
3405
3406 rtl_csi_access_enable(ioaddr);
3407
3408 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3409
219a1e9d
FR		 3410 __rtl_hw_start_8168cp(ioaddr, pdev);
3411}
3412
ef3386f0
FR		 3413static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3414{
3415 rtl_csi_access_enable(ioaddr);
3416
3417 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3418
3419 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3420
3421 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3422}
3423
7f3e3d3a
FR		 3424static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3425{
3426 rtl_csi_access_enable(ioaddr);
3427
3428 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3429
3430 /* Magic. */
3431 RTL_W8(DBG_REG, 0x20);
3432
f0298f81 3433 RTL_W8(MaxTxPacketSize, TxPacketMax);
7f3e3d3a
FR		 3434
3435 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3436
3437 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3438}
3439
219a1e9d
FR		 3440static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3441{
350f7596 3442 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 3443 { 0x02, 0x0800, 0x1000 },
3444 { 0x03, 0, 0x0002 },
3445 { 0x06, 0x0080, 0x0000 }
3446 };
3447
3448 rtl_csi_access_enable(ioaddr);
3449
3450 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3451
3452 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3453
219a1e9d
FR		 3454 __rtl_hw_start_8168cp(ioaddr, pdev);
3455}
3456
3457static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3458{
350f7596 3459 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 3460 { 0x01, 0, 0x0001 },
3461 { 0x03, 0x0400, 0x0220 }
3462 };
3463
3464 rtl_csi_access_enable(ioaddr);
3465
3466 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3467
219a1e9d
FR		 3468 __rtl_hw_start_8168cp(ioaddr, pdev);
3469}
3470
197ff761
FR		 3471static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3472{
3473 rtl_hw_start_8168c_2(ioaddr, pdev);
3474}
3475
6fb07058
FR		 3476static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3477{
3478 rtl_csi_access_enable(ioaddr);
3479
3480 __rtl_hw_start_8168cp(ioaddr, pdev);
3481}
3482
5b538df9
FR		 3483static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3484{
3485 rtl_csi_access_enable(ioaddr);
3486
3487 rtl_disable_clock_request(pdev);
3488
f0298f81 3489 RTL_W8(MaxTxPacketSize, TxPacketMax);
5b538df9
FR		 3490
3491 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3492
3493 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3494}
3495
07ce4064
FR		 3496static void rtl_hw_start_8168(struct net_device *dev)
3497{
2dd99530
FR		 3498 struct rtl8169_private *tp = netdev_priv(dev);
3499 void __iomem *ioaddr = tp->mmio_addr;
0e485150 3500 struct pci_dev *pdev = tp->pci_dev;
2dd99530
FR		 3501
3502 RTL_W8(Cfg9346, Cfg9346_Unlock);
3503
f0298f81 3504 RTL_W8(MaxTxPacketSize, TxPacketMax);
2dd99530 3505
6f0333b8 3506 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2dd99530 3507
0e485150 3508 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 3509
3510 RTL_W16(CPlusCmd, tp->cp_cmd);
3511
0e485150 3512 RTL_W16(IntrMitigate, 0x5151);
2dd99530 3513
0e485150
FR		 3514 /* Work around for RxFIFO overflow. */
3515 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
3516 tp->intr_event |= RxFIFOOver | PCSTimeout;
3517 tp->intr_event &= ~RxOverflow;
3518 }
3519
3520 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 3521
b8363901
FR		 3522 rtl_set_rx_mode(dev);
3523
3524 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3525 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 3526
3527 RTL_R8(IntrMask);
3528
219a1e9d
FR		 3529 switch (tp->mac_version) {
3530 case RTL_GIGA_MAC_VER_11:
3531 rtl_hw_start_8168bb(ioaddr, pdev);
3532 break;
3533
3534 case RTL_GIGA_MAC_VER_12:
3535 case RTL_GIGA_MAC_VER_17:
3536 rtl_hw_start_8168bef(ioaddr, pdev);
3537 break;
3538
3539 case RTL_GIGA_MAC_VER_18:
ef3386f0 3540 rtl_hw_start_8168cp_1(ioaddr, pdev);
219a1e9d
FR		 3541 break;
3542
3543 case RTL_GIGA_MAC_VER_19:
3544 rtl_hw_start_8168c_1(ioaddr, pdev);
3545 break;
3546
3547 case RTL_GIGA_MAC_VER_20:
3548 rtl_hw_start_8168c_2(ioaddr, pdev);
3549 break;
3550
197ff761
FR		 3551 case RTL_GIGA_MAC_VER_21:
3552 rtl_hw_start_8168c_3(ioaddr, pdev);
3553 break;
3554
6fb07058
FR		 3555 case RTL_GIGA_MAC_VER_22:
3556 rtl_hw_start_8168c_4(ioaddr, pdev);
3557 break;
3558
ef3386f0
FR		 3559 case RTL_GIGA_MAC_VER_23:
3560 rtl_hw_start_8168cp_2(ioaddr, pdev);
3561 break;
3562
7f3e3d3a
FR		 3563 case RTL_GIGA_MAC_VER_24:
3564 rtl_hw_start_8168cp_3(ioaddr, pdev);
3565 break;
3566
5b538df9 3567 case RTL_GIGA_MAC_VER_25:
daf9df6d 3568 case RTL_GIGA_MAC_VER_26:
3569 case RTL_GIGA_MAC_VER_27:
5b538df9
FR		 3570 rtl_hw_start_8168d(ioaddr, pdev);
3571 break;
3572
219a1e9d
FR		 3573 default:
3574 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
3575 dev->name, tp->mac_version);
3576 break;
3577 }
2dd99530 3578
0e485150
FR		 3579 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3580
b8363901
FR		 3581 RTL_W8(Cfg9346, Cfg9346_Lock);
3582
2dd99530 3583 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 3584
0e485150 3585 RTL_W16(IntrMask, tp->intr_event);
07ce4064 3586}
1da177e4 3587
2857ffb7
FR		 3588#define R810X_CPCMD_QUIRK_MASK (\
3589 EnableBist | \
3590 Mac_dbgo_oe | \
3591 Force_half_dup | \
5edcc537 3592 Force_rxflow_en | \
2857ffb7
FR		 3593 Force_txflow_en | \
3594 Cxpl_dbg_sel | \
3595 ASF | \
3596 PktCntrDisable | \
3597 PCIDAC | \
3598 PCIMulRW)
3599
3600static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3601{
350f7596 3602 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 3603 { 0x01, 0, 0x6e65 },
3604 { 0x02, 0, 0x091f },
3605 { 0x03, 0, 0xc2f9 },
3606 { 0x06, 0, 0xafb5 },
3607 { 0x07, 0, 0x0e00 },
3608 { 0x19, 0, 0xec80 },
3609 { 0x01, 0, 0x2e65 },
3610 { 0x01, 0, 0x6e65 }
3611 };
3612 u8 cfg1;
3613
3614 rtl_csi_access_enable(ioaddr);
3615
3616 RTL_W8(DBG_REG, FIX_NAK_1);
3617
3618 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3619
3620 RTL_W8(Config1,
3621 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3622 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3623
3624 cfg1 = RTL_R8(Config1);
3625 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3626 RTL_W8(Config1, cfg1 & ~LEDS0);
3627
3628 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3629
3630 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
3631}
3632
3633static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
3634{
3635 rtl_csi_access_enable(ioaddr);
3636
3637 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3638
3639 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
3640 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3641
3642 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3643}
3644
3645static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
3646{
3647 rtl_hw_start_8102e_2(ioaddr, pdev);
3648
3649 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
3650}
3651
07ce4064
FR		 3652static void rtl_hw_start_8101(struct net_device *dev)
3653{
cdf1a608
FR		 3654 struct rtl8169_private *tp = netdev_priv(dev);
3655 void __iomem *ioaddr = tp->mmio_addr;
3656 struct pci_dev *pdev = tp->pci_dev;
3657
e3cf0cc0
FR		 3658 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
3659 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
9c14ceaf
FR		 3660 int cap = tp->pcie_cap;
3661
3662 if (cap) {
3663 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
3664 PCI_EXP_DEVCTL_NOSNOOP_EN);
3665 }
cdf1a608
FR		 3666 }
3667
2857ffb7
FR		 3668 switch (tp->mac_version) {
3669 case RTL_GIGA_MAC_VER_07:
3670 rtl_hw_start_8102e_1(ioaddr, pdev);
3671 break;
3672
3673 case RTL_GIGA_MAC_VER_08:
3674 rtl_hw_start_8102e_3(ioaddr, pdev);
3675 break;
3676
3677 case RTL_GIGA_MAC_VER_09:
3678 rtl_hw_start_8102e_2(ioaddr, pdev);
3679 break;
cdf1a608
FR		 3680 }
3681
3682 RTL_W8(Cfg9346, Cfg9346_Unlock);
3683
f0298f81 3684 RTL_W8(MaxTxPacketSize, TxPacketMax);
cdf1a608 3685
6f0333b8 3686 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
cdf1a608
FR		 3687
3688 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3689
3690 RTL_W16(CPlusCmd, tp->cp_cmd);
3691
3692 RTL_W16(IntrMitigate, 0x0000);
3693
3694 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3695
3696 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3697 rtl_set_rx_tx_config_registers(tp);
3698
3699 RTL_W8(Cfg9346, Cfg9346_Lock);
3700
3701 RTL_R8(IntrMask);
3702
cdf1a608
FR		 3703 rtl_set_rx_mode(dev);
3704
0e485150
FR		 3705 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3706
cdf1a608 3707 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 3708
0e485150 3709 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 3710}
3711
3712static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3713{
1da177e4
LT		 3714 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
3715 return -EINVAL;
3716
3717 dev->mtu = new_mtu;
323bb685 3718 return 0;
1da177e4
LT		 3719}
3720
3721static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
3722{
95e0918d 3723 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 3724 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
3725}
3726
6f0333b8
ED		 3727static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
3728 void **data_buff, struct RxDesc *desc)
1da177e4 3729{
48addcc9 3730 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
231aee63 3731 DMA_FROM_DEVICE);
48addcc9 3732
6f0333b8
ED		 3733 kfree(*data_buff);
3734 *data_buff = NULL;
1da177e4
LT		 3735 rtl8169_make_unusable_by_asic(desc);
3736}
3737
3738static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
3739{
3740 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3741
3742 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
3743}
3744
3745static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
3746 u32 rx_buf_sz)
3747{
3748 desc->addr = cpu_to_le64(mapping);
3749 wmb();
3750 rtl8169_mark_to_asic(desc, rx_buf_sz);
3751}
3752
6f0333b8
ED		 3753static inline void *rtl8169_align(void *data)
3754{
3755 return (void *)ALIGN((long)data, 16);
3756}
3757
0ecbe1ca
SG		 3758static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
3759 struct RxDesc *desc)
1da177e4 3760{
6f0333b8 3761 void *data;
1da177e4 3762 dma_addr_t mapping;
48addcc9 3763 struct device *d = &tp->pci_dev->dev;
0ecbe1ca 3764 struct net_device *dev = tp->dev;
6f0333b8 3765 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
1da177e4 3766
6f0333b8
ED		 3767 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
3768 if (!data)
3769 return NULL;
e9f63f30 3770
6f0333b8
ED		 3771 if (rtl8169_align(data) != data) {
3772 kfree(data);
3773 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
3774 if (!data)
3775 return NULL;
3776 }
3eafe507 3777
48addcc9 3778 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
231aee63 3779 DMA_FROM_DEVICE);
d827d86b
SG		 3780 if (unlikely(dma_mapping_error(d, mapping))) {
3781 if (net_ratelimit())
3782 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 3783 goto err_out;
d827d86b 3784 }
1da177e4
LT		 3785
3786 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6f0333b8 3787 return data;
3eafe507
SG		 3788
3789err_out:
3790 kfree(data);
3791 return NULL;
1da177e4
LT		 3792}
3793
3794static void rtl8169_rx_clear(struct rtl8169_private *tp)
3795{
07d3f51f 3796 unsigned int i;
1da177e4
LT		 3797
3798 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 3799 if (tp->Rx_databuff[i]) {
3800 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 3801 tp->RxDescArray + i);
3802 }
3803 }
3804}
3805
0ecbe1ca 3806static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 3807{
0ecbe1ca
SG		 3808 desc->opts1 |= cpu_to_le32(RingEnd);
3809}
5b0384f4 3810
0ecbe1ca
SG		 3811static int rtl8169_rx_fill(struct rtl8169_private *tp)
3812{
3813 unsigned int i;
1da177e4 3814
0ecbe1ca
SG		 3815 for (i = 0; i < NUM_RX_DESC; i++) {
3816 void *data;
4ae47c2d 3817
6f0333b8 3818 if (tp->Rx_databuff[i])
1da177e4 3819 continue;
bcf0bf90 3820
0ecbe1ca 3821 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 3822 if (!data) {
3823 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 3824 goto err_out;
6f0333b8
ED		 3825 }
3826 tp->Rx_databuff[i] = data;
1da177e4 3827 }
1da177e4 3828
0ecbe1ca
SG		 3829 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
3830 return 0;
3831
3832err_out:
3833 rtl8169_rx_clear(tp);
3834 return -ENOMEM;
1da177e4
LT		 3835}
3836
3837static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3838{
3839 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3840}
3841
3842static int rtl8169_init_ring(struct net_device *dev)
3843{
3844 struct rtl8169_private *tp = netdev_priv(dev);
3845
3846 rtl8169_init_ring_indexes(tp);
3847
3848 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6f0333b8 3849 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
1da177e4 3850
0ecbe1ca 3851 return rtl8169_rx_fill(tp);
1da177e4
LT		 3852}
3853
48addcc9 3854static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 3855 struct TxDesc *desc)
3856{
3857 unsigned int len = tx_skb->len;
3858
48addcc9
SG		 3859 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
3860
1da177e4
LT		 3861 desc->opts1 = 0x00;
3862 desc->opts2 = 0x00;
3863 desc->addr = 0x00;
3864 tx_skb->len = 0;
3865}
3866
3eafe507
SG		 3867static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
3868 unsigned int n)
1da177e4
LT		 3869{
3870 unsigned int i;
3871
3eafe507
SG		 3872 for (i = 0; i < n; i++) {
3873 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 3874 struct ring_info *tx_skb = tp->tx_skb + entry;
3875 unsigned int len = tx_skb->len;
3876
3877 if (len) {
3878 struct sk_buff *skb = tx_skb->skb;
3879
48addcc9 3880 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
1da177e4
LT		 3881 tp->TxDescArray + entry);
3882 if (skb) {
cac4b22f 3883 tp->dev->stats.tx_dropped++;
1da177e4
LT		 3884 dev_kfree_skb(skb);
3885 tx_skb->skb = NULL;
3886 }
1da177e4
LT		 3887 }
3888 }
3eafe507
SG		 3889}
3890
3891static void rtl8169_tx_clear(struct rtl8169_private *tp)
3892{
3893 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 3894 tp->cur_tx = tp->dirty_tx = 0;
3895}
3896
c4028958 3897static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 3898{
3899 struct rtl8169_private *tp = netdev_priv(dev);
3900
c4028958 3901 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 3902 schedule_delayed_work(&tp->task, 4);
3903}
3904
3905static void rtl8169_wait_for_quiescence(struct net_device *dev)
3906{
3907 struct rtl8169_private *tp = netdev_priv(dev);
3908 void __iomem *ioaddr = tp->mmio_addr;
3909
3910 synchronize_irq(dev->irq);
3911
3912 /* Wait for any pending NAPI task to complete */
bea3348e 3913 napi_disable(&tp->napi);
1da177e4
LT		 3914
3915 rtl8169_irq_mask_and_ack(ioaddr);
3916
d1d08d12
DM		 3917 tp->intr_mask = 0xffff;
3918 RTL_W16(IntrMask, tp->intr_event);
bea3348e 3919 napi_enable(&tp->napi);
1da177e4
LT		 3920}
3921
c4028958 3922static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 3923{
c4028958
DH		 3924 struct rtl8169_private *tp =
3925 container_of(work, struct rtl8169_private, task.work);
3926 struct net_device *dev = tp->dev;
1da177e4
LT		 3927 int ret;
3928
eb2a021c
FR		 3929 rtnl_lock();
3930
3931 if (!netif_running(dev))
3932 goto out_unlock;
3933
3934 rtl8169_wait_for_quiescence(dev);
3935 rtl8169_close(dev);
1da177e4
LT		 3936
3937 ret = rtl8169_open(dev);
3938 if (unlikely(ret < 0)) {
bf82c189
JP		 3939 if (net_ratelimit())
3940 netif_err(tp, drv, dev,
3941 "reinit failure (status = %d). Rescheduling\n",
3942 ret);
1da177e4
LT		 3943 rtl8169_schedule_work(dev, rtl8169_reinit_task);
3944 }
eb2a021c
FR		 3945
3946out_unlock:
3947 rtnl_unlock();
1da177e4
LT		 3948}
3949
c4028958 3950static void rtl8169_reset_task(struct work_struct *work)
1da177e4 3951{
c4028958
DH		 3952 struct rtl8169_private *tp =
3953 container_of(work, struct rtl8169_private, task.work);
3954 struct net_device *dev = tp->dev;
1da177e4 3955
eb2a021c
FR		 3956 rtnl_lock();
3957
1da177e4 3958 if (!netif_running(dev))
eb2a021c 3959 goto out_unlock;
1da177e4
LT		 3960
3961 rtl8169_wait_for_quiescence(dev);
3962
bea3348e 3963 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
1da177e4
LT		 3964 rtl8169_tx_clear(tp);
3965
3966 if (tp->dirty_rx == tp->cur_rx) {
3967 rtl8169_init_ring_indexes(tp);
07ce4064 3968 rtl_hw_start(dev);
1da177e4 3969 netif_wake_queue(dev);
cebf8cc7 3970 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4 3971 } else {
bf82c189
JP		 3972 if (net_ratelimit())
3973 netif_emerg(tp, intr, dev, "Rx buffers shortage\n");
1da177e4
LT		 3974 rtl8169_schedule_work(dev, rtl8169_reset_task);
3975 }
eb2a021c
FR		 3976
3977out_unlock:
3978 rtnl_unlock();
1da177e4
LT		 3979}
3980
3981static void rtl8169_tx_timeout(struct net_device *dev)
3982{
3983 struct rtl8169_private *tp = netdev_priv(dev);
3984
3985 rtl8169_hw_reset(tp->mmio_addr);
3986
3987 /* Let's wait a bit while any (async) irq lands on */
3988 rtl8169_schedule_work(dev, rtl8169_reset_task);
3989}
3990
3991static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
3992 u32 opts1)
3993{
3994 struct skb_shared_info *info = skb_shinfo(skb);
3995 unsigned int cur_frag, entry;
a6343afb 3996 struct TxDesc * uninitialized_var(txd);
48addcc9 3997 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 3998
3999 entry = tp->cur_tx;
4000 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4001 skb_frag_t *frag = info->frags + cur_frag;
4002 dma_addr_t mapping;
4003 u32 status, len;
4004 void *addr;
4005
4006 entry = (entry + 1) % NUM_TX_DESC;
4007
4008 txd = tp->TxDescArray + entry;
4009 len = frag->size;
4010 addr = ((void *) page_address(frag->page)) + frag->page_offset;
48addcc9 4011 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 4012 if (unlikely(dma_mapping_error(d, mapping))) {
4013 if (net_ratelimit())
4014 netif_err(tp, drv, tp->dev,
4015 "Failed to map TX fragments DMA!\n");
3eafe507 4016 goto err_out;
d827d86b 4017 }
1da177e4
LT		 4018
4019 /* anti gcc 2.95.3 bugware (sic) */
4020 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4021
4022 txd->opts1 = cpu_to_le32(status);
4023 txd->addr = cpu_to_le64(mapping);
4024
4025 tp->tx_skb[entry].len = len;
4026 }
4027
4028 if (cur_frag) {
4029 tp->tx_skb[entry].skb = skb;
4030 txd->opts1 |= cpu_to_le32(LastFrag);
4031 }
4032
4033 return cur_frag;
3eafe507
SG		 4034
4035err_out:
4036 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4037 return -EIO;
1da177e4
LT		 4038}
4039
4040static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
4041{
4042 if (dev->features & NETIF_F_TSO) {
7967168c 4043 u32 mss = skb_shinfo(skb)->gso_size;
1da177e4
LT		 4044
4045 if (mss)
4046 return LargeSend | ((mss & MSSMask) << MSSShift);
4047 }
84fa7933 4048 if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 4049 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 4050
4051 if (ip->protocol == IPPROTO_TCP)
4052 return IPCS | TCPCS;
4053 else if (ip->protocol == IPPROTO_UDP)
4054 return IPCS | UDPCS;
4055 WARN_ON(1); /* we need a WARN() */
4056 }
4057 return 0;
4058}
4059
61357325
SH		 4060static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4061 struct net_device *dev)
1da177e4
LT		 4062{
4063 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 4064 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4
LT		 4065 struct TxDesc *txd = tp->TxDescArray + entry;
4066 void __iomem *ioaddr = tp->mmio_addr;
48addcc9 4067 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 4068 dma_addr_t mapping;
4069 u32 status, len;
4070 u32 opts1;
3eafe507 4071 int frags;
5b0384f4 4072
1da177e4 4073 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
bf82c189 4074 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 4075 goto err_stop_0;
1da177e4
LT		 4076 }
4077
4078 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 4079 goto err_stop_0;
4080
4081 len = skb_headlen(skb);
48addcc9 4082 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 4083 if (unlikely(dma_mapping_error(d, mapping))) {
4084 if (net_ratelimit())
4085 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 4086 goto err_dma_0;
d827d86b 4087 }
3eafe507
SG		 4088
4089 tp->tx_skb[entry].len = len;
4090 txd->addr = cpu_to_le64(mapping);
4091 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
1da177e4
LT		 4092
4093 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
4094
4095 frags = rtl8169_xmit_frags(tp, skb, opts1);
3eafe507
SG		 4096 if (frags < 0)
4097 goto err_dma_1;
4098 else if (frags)
1da177e4 4099 opts1 |= FirstFrag;
3eafe507 4100 else {
1da177e4
LT		 4101 opts1 |= FirstFrag | LastFrag;
4102 tp->tx_skb[entry].skb = skb;
4103 }
4104
1da177e4
LT		 4105 wmb();
4106
4107 /* anti gcc 2.95.3 bugware (sic) */
4108 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4109 txd->opts1 = cpu_to_le32(status);
4110
1da177e4
LT		 4111 tp->cur_tx += frags + 1;
4112
4c020a96 4113 wmb();
1da177e4 4114
275391a4 4115 RTL_W8(TxPoll, NPQ); /* set polling bit */
1da177e4
LT		 4116
4117 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4118 netif_stop_queue(dev);
4119 smp_rmb();
4120 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4121 netif_wake_queue(dev);
4122 }
4123
61357325 4124 return NETDEV_TX_OK;
1da177e4 4125
3eafe507 4126err_dma_1:
48addcc9 4127 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507
SG		 4128err_dma_0:
4129 dev_kfree_skb(skb);
4130 dev->stats.tx_dropped++;
4131 return NETDEV_TX_OK;
4132
4133err_stop_0:
1da177e4 4134 netif_stop_queue(dev);
cebf8cc7 4135 dev->stats.tx_dropped++;
61357325 4136 return NETDEV_TX_BUSY;
1da177e4
LT		 4137}
4138
4139static void rtl8169_pcierr_interrupt(struct net_device *dev)
4140{
4141 struct rtl8169_private *tp = netdev_priv(dev);
4142 struct pci_dev *pdev = tp->pci_dev;
4143 void __iomem *ioaddr = tp->mmio_addr;
4144 u16 pci_status, pci_cmd;
4145
4146 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4147 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4148
bf82c189
JP		 4149 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4150 pci_cmd, pci_status);
1da177e4
LT		 4151
4152 /*
4153 * The recovery sequence below admits a very elaborated explanation:
4154 * - it seems to work;
d03902b8
FR		 4155 * - I did not see what else could be done;
4156 * - it makes iop3xx happy.
1da177e4
LT		 4157 *
4158 * Feel free to adjust to your needs.
4159 */
a27993f3 4160 if (pdev->broken_parity_status)
d03902b8
FR		 4161 pci_cmd &= ~PCI_COMMAND_PARITY;
4162 else
4163 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4164
4165 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 4166
4167 pci_write_config_word(pdev, PCI_STATUS,
4168 pci_status & (PCI_STATUS_DETECTED_PARITY |
4169 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4170 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4171
4172 /* The infamous DAC f*ckup only happens at boot time */
4173 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
bf82c189 4174 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 4175 tp->cp_cmd &= ~PCIDAC;
4176 RTL_W16(CPlusCmd, tp->cp_cmd);
4177 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 4178 }
4179
4180 rtl8169_hw_reset(ioaddr);
d03902b8
FR		 4181
4182 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 4183}
4184
07d3f51f
FR		 4185static void rtl8169_tx_interrupt(struct net_device *dev,
4186 struct rtl8169_private *tp,
4187 void __iomem *ioaddr)
1da177e4
LT		 4188{
4189 unsigned int dirty_tx, tx_left;
4190
1da177e4
LT		 4191 dirty_tx = tp->dirty_tx;
4192 smp_rmb();
4193 tx_left = tp->cur_tx - dirty_tx;
4194
4195 while (tx_left > 0) {
4196 unsigned int entry = dirty_tx % NUM_TX_DESC;
4197 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 4198 u32 status;
4199
4200 rmb();
4201 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4202 if (status & DescOwn)
4203 break;
4204
48addcc9
SG		 4205 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4206 tp->TxDescArray + entry);
1da177e4 4207 if (status & LastFrag) {
cac4b22f
SG		 4208 dev->stats.tx_packets++;
4209 dev->stats.tx_bytes += tx_skb->skb->len;
87433bfc 4210 dev_kfree_skb(tx_skb->skb);
1da177e4
LT		 4211 tx_skb->skb = NULL;
4212 }
4213 dirty_tx++;
4214 tx_left--;
4215 }
4216
4217 if (tp->dirty_tx != dirty_tx) {
4218 tp->dirty_tx = dirty_tx;
4219 smp_wmb();
4220 if (netif_queue_stopped(dev) &&
4221 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4222 netif_wake_queue(dev);
4223 }
d78ae2dc
FR		 4224 /*
4225 * 8168 hack: TxPoll requests are lost when the Tx packets are
4226 * too close. Let's kick an extra TxPoll request when a burst
4227 * of start_xmit activity is detected (if it is not detected,
4228 * it is slow enough). -- FR
4229 */
4230 smp_rmb();
4231 if (tp->cur_tx != dirty_tx)
4232 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 4233 }
4234}
4235
126fa4b9
FR		 4236static inline int rtl8169_fragmented_frame(u32 status)
4237{
4238 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4239}
4240
adea1ac7 4241static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 4242{
1da177e4
LT		 4243 u32 status = opts1 & RxProtoMask;
4244
4245 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 4246 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 4247 skb->ip_summed = CHECKSUM_UNNECESSARY;
4248 else
bc8acf2c 4249 skb_checksum_none_assert(skb);
1da177e4
LT		 4250}
4251
6f0333b8
ED		 4252static struct sk_buff *rtl8169_try_rx_copy(void *data,
4253 struct rtl8169_private *tp,
4254 int pkt_size,
4255 dma_addr_t addr)
1da177e4 4256{
b449655f 4257 struct sk_buff *skb;
48addcc9 4258 struct device *d = &tp->pci_dev->dev;
b449655f 4259
6f0333b8 4260 data = rtl8169_align(data);
48addcc9 4261 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8
ED		 4262 prefetch(data);
4263 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
4264 if (skb)
4265 memcpy(skb->data, data, pkt_size);
48addcc9
SG		 4266 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4267
6f0333b8 4268 return skb;
1da177e4
LT		 4269}
4270
630b943c
ED		 4271/*
4272 * Warning : rtl8169_rx_interrupt() might be called :
4273 * 1) from NAPI (softirq) context
4274 * (polling = 1 : we should call netif_receive_skb())
4275 * 2) from process context (rtl8169_reset_task())
4276 * (polling = 0 : we must call netif_rx() instead)
4277 */
07d3f51f
FR		 4278static int rtl8169_rx_interrupt(struct net_device *dev,
4279 struct rtl8169_private *tp,
bea3348e 4280 void __iomem *ioaddr, u32 budget)
1da177e4
LT		 4281{
4282 unsigned int cur_rx, rx_left;
6f0333b8 4283 unsigned int count;
630b943c 4284 int polling = (budget != ~(u32)0) ? 1 : 0;
1da177e4 4285
1da177e4
LT		 4286 cur_rx = tp->cur_rx;
4287 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 4288 rx_left = min(rx_left, budget);
1da177e4 4289
4dcb7d33 4290 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 4291 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 4292 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 4293 u32 status;
4294
4295 rmb();
126fa4b9 4296 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 4297
4298 if (status & DescOwn)
4299 break;
4dcb7d33 4300 if (unlikely(status & RxRES)) {
bf82c189
JP		 4301 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4302 status);
cebf8cc7 4303 dev->stats.rx_errors++;
1da177e4 4304 if (status & (RxRWT | RxRUNT))
cebf8cc7 4305 dev->stats.rx_length_errors++;
1da177e4 4306 if (status & RxCRC)
cebf8cc7 4307 dev->stats.rx_crc_errors++;
9dccf611
FR		 4308 if (status & RxFOVF) {
4309 rtl8169_schedule_work(dev, rtl8169_reset_task);
cebf8cc7 4310 dev->stats.rx_fifo_errors++;
9dccf611 4311 }
6f0333b8 4312 rtl8169_mark_to_asic(desc, rx_buf_sz);
1da177e4 4313 } else {
6f0333b8 4314 struct sk_buff *skb;
b449655f 4315 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 4316 int pkt_size = (status & 0x00001FFF) - 4;
1da177e4 4317
126fa4b9
FR		 4318 /*
4319 * The driver does not support incoming fragmented
4320 * frames. They are seen as a symptom of over-mtu
4321 * sized frames.
4322 */
4323 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 4324 dev->stats.rx_dropped++;
4325 dev->stats.rx_length_errors++;
6f0333b8 4326 rtl8169_mark_to_asic(desc, rx_buf_sz);
4dcb7d33 4327 continue;
126fa4b9
FR		 4328 }
4329
6f0333b8
ED		 4330 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
4331 tp, pkt_size, addr);
4332 rtl8169_mark_to_asic(desc, rx_buf_sz);
4333 if (!skb) {
4334 dev->stats.rx_dropped++;
4335 continue;
1da177e4
LT		 4336 }
4337
adea1ac7 4338 rtl8169_rx_csum(skb, status);
1da177e4
LT		 4339 skb_put(skb, pkt_size);
4340 skb->protocol = eth_type_trans(skb, dev);
4341
630b943c
ED		 4342 if (rtl8169_rx_vlan_skb(tp, desc, skb, polling) < 0) {
4343 if (likely(polling))
2edae08e 4344 napi_gro_receive(&tp->napi, skb);
630b943c
ED		 4345 else
4346 netif_rx(skb);
4347 }
1da177e4 4348
cebf8cc7
FR		 4349 dev->stats.rx_bytes += pkt_size;
4350 dev->stats.rx_packets++;
1da177e4 4351 }
6dccd16b
FR		 4352
4353 /* Work around for AMD plateform. */
95e0918d 4354 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 4355 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4356 desc->opts2 = 0;
4357 cur_rx++;
4358 }
1da177e4
LT		 4359 }
4360
4361 count = cur_rx - tp->cur_rx;
4362 tp->cur_rx = cur_rx;
4363
6f0333b8 4364 tp->dirty_rx += count;
1da177e4
LT		 4365
4366 return count;
4367}
4368
07d3f51f 4369static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 4370{
07d3f51f 4371 struct net_device *dev = dev_instance;
1da177e4 4372 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 4373 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 4374 int handled = 0;
865c652d 4375 int status;
1da177e4 4376
f11a377b
DD		 4377 /* loop handling interrupts until we have no new ones or
4378 * we hit a invalid/hotplug case.
4379 */
865c652d 4380 status = RTL_R16(IntrStatus);
f11a377b
DD		 4381 while (status && status != 0xffff) {
4382 handled = 1;
1da177e4 4383
f11a377b
DD		 4384 /* Handle all of the error cases first. These will reset
4385 * the chip, so just exit the loop.
4386 */
4387 if (unlikely(!netif_running(dev))) {
4388 rtl8169_asic_down(ioaddr);
4389 break;
4390 }
1da177e4 4391
f11a377b 4392 /* Work around for rx fifo overflow */
53f57357 4393 if (unlikely(status & RxFIFOOver) &&
4394 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
f11a377b
DD		 4395 netif_stop_queue(dev);
4396 rtl8169_tx_timeout(dev);
4397 break;
4398 }
1da177e4 4399
f11a377b
DD		 4400 if (unlikely(status & SYSErr)) {
4401 rtl8169_pcierr_interrupt(dev);
4402 break;
4403 }
1da177e4 4404
f11a377b 4405 if (status & LinkChg)
e4fbce74 4406 __rtl8169_check_link_status(dev, tp, ioaddr, true);
0e485150 4407
f11a377b
DD		 4408 /* We need to see the lastest version of tp->intr_mask to
4409 * avoid ignoring an MSI interrupt and having to wait for
4410 * another event which may never come.
4411 */
4412 smp_rmb();
4413 if (status & tp->intr_mask & tp->napi_event) {
4414 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
4415 tp->intr_mask = ~tp->napi_event;
4416
4417 if (likely(napi_schedule_prep(&tp->napi)))
4418 __napi_schedule(&tp->napi);
bf82c189
JP		 4419 else
4420 netif_info(tp, intr, dev,
4421 "interrupt %04x in poll\n", status);
f11a377b 4422 }
1da177e4 4423
f11a377b
DD		 4424 /* We only get a new MSI interrupt when all active irq
4425 * sources on the chip have been acknowledged. So, ack
4426 * everything we've seen and check if new sources have become
4427 * active to avoid blocking all interrupts from the chip.
4428 */
4429 RTL_W16(IntrStatus,
4430 (status & RxFIFOOver) ? (status | RxOverflow) : status);
4431 status = RTL_R16(IntrStatus);
865c652d 4432 }
1da177e4 4433
1da177e4
LT		 4434 return IRQ_RETVAL(handled);
4435}
4436
bea3348e 4437static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 4438{
bea3348e
SH		 4439 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4440 struct net_device *dev = tp->dev;
1da177e4 4441 void __iomem *ioaddr = tp->mmio_addr;
bea3348e 4442 int work_done;
1da177e4 4443
bea3348e 4444 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
1da177e4
LT		 4445 rtl8169_tx_interrupt(dev, tp, ioaddr);
4446
bea3348e 4447 if (work_done < budget) {
288379f0 4448 napi_complete(napi);
f11a377b
DD		 4449
4450 /* We need for force the visibility of tp->intr_mask
4451 * for other CPUs, as we can loose an MSI interrupt
4452 * and potentially wait for a retransmit timeout if we don't.
4453 * The posted write to IntrMask is safe, as it will
4454 * eventually make it to the chip and we won't loose anything
4455 * until it does.
1da177e4 4456 */
f11a377b 4457 tp->intr_mask = 0xffff;
4c020a96 4458 wmb();
0e485150 4459 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 4460 }
4461
bea3348e 4462 return work_done;
1da177e4 4463}
1da177e4 4464
523a6094
FR		 4465static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
4466{
4467 struct rtl8169_private *tp = netdev_priv(dev);
4468
4469 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
4470 return;
4471
4472 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
4473 RTL_W32(RxMissed, 0);
4474}
4475
1da177e4
LT		 4476static void rtl8169_down(struct net_device *dev)
4477{
4478 struct rtl8169_private *tp = netdev_priv(dev);
4479 void __iomem *ioaddr = tp->mmio_addr;
1da177e4
LT		 4480
4481 rtl8169_delete_timer(dev);
4482
4483 netif_stop_queue(dev);
4484
93dd79e8 4485 napi_disable(&tp->napi);
93dd79e8 4486
1da177e4
LT		 4487 spin_lock_irq(&tp->lock);
4488
4489 rtl8169_asic_down(ioaddr);
323bb685
SG		 4490 /*
4491 * At this point device interrupts can not be enabled in any function,
4492 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
4493 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
4494 */
523a6094 4495 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 4496
4497 spin_unlock_irq(&tp->lock);
4498
4499 synchronize_irq(dev->irq);
4500
1da177e4 4501 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 4502 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4 4503
1da177e4
LT		 4504 rtl8169_tx_clear(tp);
4505
4506 rtl8169_rx_clear(tp);
065c27c1 4507
4508 rtl_pll_power_down(tp);
1da177e4
LT		 4509}
4510
4511static int rtl8169_close(struct net_device *dev)
4512{
4513 struct rtl8169_private *tp = netdev_priv(dev);
4514 struct pci_dev *pdev = tp->pci_dev;
4515
e1759441
RW		 4516 pm_runtime_get_sync(&pdev->dev);
4517
355423d0
IV		 4518 /* update counters before going down */
4519 rtl8169_update_counters(dev);
4520
1da177e4
LT		 4521 rtl8169_down(dev);
4522
4523 free_irq(dev->irq, dev);
4524
82553bb6
SG		 4525 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4526 tp->RxPhyAddr);
4527 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4528 tp->TxPhyAddr);
1da177e4
LT		 4529 tp->TxDescArray = NULL;
4530 tp->RxDescArray = NULL;
4531
e1759441
RW		 4532 pm_runtime_put_sync(&pdev->dev);
4533
1da177e4
LT		 4534 return 0;
4535}
4536
07ce4064 4537static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 4538{
4539 struct rtl8169_private *tp = netdev_priv(dev);
4540 void __iomem *ioaddr = tp->mmio_addr;
4541 unsigned long flags;
4542 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 4543 int rx_mode;
1da177e4
LT		 4544 u32 tmp = 0;
4545
4546 if (dev->flags & IFF_PROMISC) {
4547 /* Unconditionally log net taps. */
bf82c189 4548 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
1da177e4
LT		 4549 rx_mode =
4550 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4551 AcceptAllPhys;
4552 mc_filter[1] = mc_filter[0] = 0xffffffff;
4cd24eaf 4553 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
8e95a202 4554 (dev->flags & IFF_ALLMULTI)) {
1da177e4
LT		 4555 /* Too many to filter perfectly -- accept all multicasts. */
4556 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4557 mc_filter[1] = mc_filter[0] = 0xffffffff;
4558 } else {
22bedad3 4559 struct netdev_hw_addr *ha;
07d3f51f 4560
1da177e4
LT		 4561 rx_mode = AcceptBroadcast | AcceptMyPhys;
4562 mc_filter[1] = mc_filter[0] = 0;
22bedad3
JP		 4563 netdev_for_each_mc_addr(ha, dev) {
4564 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1da177e4
LT		 4565 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4566 rx_mode |= AcceptMulticast;
4567 }
4568 }
4569
4570 spin_lock_irqsave(&tp->lock, flags);
4571
4572 tmp = rtl8169_rx_config | rx_mode |
4573 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
4574
f887cce8 4575 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
1087f4f4
FR		 4576 u32 data = mc_filter[0];
4577
4578 mc_filter[0] = swab32(mc_filter[1]);
4579 mc_filter[1] = swab32(data);
bcf0bf90
FR		 4580 }
4581
1da177e4 4582 RTL_W32(MAR0 + 4, mc_filter[1]);
78f1cd02 4583 RTL_W32(MAR0 + 0, mc_filter[0]);
1da177e4 4584
57a9f236
FR		 4585 RTL_W32(RxConfig, tmp);
4586
1da177e4
LT		 4587 spin_unlock_irqrestore(&tp->lock, flags);
4588}
4589
4590/**
4591 * rtl8169_get_stats - Get rtl8169 read/write statistics
4592 * @dev: The Ethernet Device to get statistics for
4593 *
4594 * Get TX/RX statistics for rtl8169
4595 */
4596static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
4597{
4598 struct rtl8169_private *tp = netdev_priv(dev);
4599 void __iomem *ioaddr = tp->mmio_addr;
4600 unsigned long flags;
4601
4602 if (netif_running(dev)) {
4603 spin_lock_irqsave(&tp->lock, flags);
523a6094 4604 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 4605 spin_unlock_irqrestore(&tp->lock, flags);
4606 }
5b0384f4 4607
cebf8cc7 4608 return &dev->stats;
1da177e4
LT		 4609}
4610
861ab440 4611static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 4612{
065c27c1 4613 struct rtl8169_private *tp = netdev_priv(dev);
4614
5d06a99f 4615 if (!netif_running(dev))
861ab440 4616 return;
5d06a99f 4617
065c27c1 4618 rtl_pll_power_down(tp);
4619
5d06a99f
FR		 4620 netif_device_detach(dev);
4621 netif_stop_queue(dev);
861ab440
RW		 4622}
4623
4624#ifdef CONFIG_PM
4625
4626static int rtl8169_suspend(struct device *device)
4627{
4628 struct pci_dev *pdev = to_pci_dev(device);
4629 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 4630
861ab440 4631 rtl8169_net_suspend(dev);
1371fa6d 4632
5d06a99f
FR		 4633 return 0;
4634}
4635
e1759441
RW		 4636static void __rtl8169_resume(struct net_device *dev)
4637{
065c27c1 4638 struct rtl8169_private *tp = netdev_priv(dev);
4639
e1759441 4640 netif_device_attach(dev);
065c27c1 4641
4642 rtl_pll_power_up(tp);
4643
e1759441
RW		 4644 rtl8169_schedule_work(dev, rtl8169_reset_task);
4645}
4646
861ab440 4647static int rtl8169_resume(struct device *device)
5d06a99f 4648{
861ab440 4649 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 4650 struct net_device *dev = pci_get_drvdata(pdev);
fccec10b
SG		 4651 struct rtl8169_private *tp = netdev_priv(dev);
4652
4653 rtl8169_init_phy(dev, tp);
5d06a99f 4654
e1759441
RW		 4655 if (netif_running(dev))
4656 __rtl8169_resume(dev);
5d06a99f 4657
e1759441
RW		 4658 return 0;
4659}
4660
4661static int rtl8169_runtime_suspend(struct device *device)
4662{
4663 struct pci_dev *pdev = to_pci_dev(device);
4664 struct net_device *dev = pci_get_drvdata(pdev);
4665 struct rtl8169_private *tp = netdev_priv(dev);
4666
4667 if (!tp->TxDescArray)
4668 return 0;
4669
4670 spin_lock_irq(&tp->lock);
4671 tp->saved_wolopts = __rtl8169_get_wol(tp);
4672 __rtl8169_set_wol(tp, WAKE_ANY);
4673 spin_unlock_irq(&tp->lock);
4674
4675 rtl8169_net_suspend(dev);
4676
4677 return 0;
4678}
4679
4680static int rtl8169_runtime_resume(struct device *device)
4681{
4682 struct pci_dev *pdev = to_pci_dev(device);
4683 struct net_device *dev = pci_get_drvdata(pdev);
4684 struct rtl8169_private *tp = netdev_priv(dev);
4685
4686 if (!tp->TxDescArray)
4687 return 0;
4688
4689 spin_lock_irq(&tp->lock);
4690 __rtl8169_set_wol(tp, tp->saved_wolopts);
4691 tp->saved_wolopts = 0;
4692 spin_unlock_irq(&tp->lock);
4693
fccec10b
SG		 4694 rtl8169_init_phy(dev, tp);
4695
e1759441 4696 __rtl8169_resume(dev);
5d06a99f 4697
5d06a99f
FR		 4698 return 0;
4699}
4700
e1759441
RW		 4701static int rtl8169_runtime_idle(struct device *device)
4702{
4703 struct pci_dev *pdev = to_pci_dev(device);
4704 struct net_device *dev = pci_get_drvdata(pdev);
4705 struct rtl8169_private *tp = netdev_priv(dev);
4706
e4fbce74 4707 return tp->TxDescArray ? -EBUSY : 0;
e1759441
RW		 4708}
4709
47145210 4710static const struct dev_pm_ops rtl8169_pm_ops = {
861ab440
RW		 4711 .suspend = rtl8169_suspend,
4712 .resume = rtl8169_resume,
4713 .freeze = rtl8169_suspend,
4714 .thaw = rtl8169_resume,
4715 .poweroff = rtl8169_suspend,
4716 .restore = rtl8169_resume,
e1759441
RW		 4717 .runtime_suspend = rtl8169_runtime_suspend,
4718 .runtime_resume = rtl8169_runtime_resume,
4719 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 4720};
4721
4722#define RTL8169_PM_OPS (&rtl8169_pm_ops)
4723
4724#else /* !CONFIG_PM */
4725
4726#define RTL8169_PM_OPS NULL
4727
4728#endif /* !CONFIG_PM */
4729
1765f95d
FR		 4730static void rtl_shutdown(struct pci_dev *pdev)
4731{
861ab440 4732 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 4733 struct rtl8169_private *tp = netdev_priv(dev);
4734 void __iomem *ioaddr = tp->mmio_addr;
861ab440
RW		 4735
4736 rtl8169_net_suspend(dev);
1765f95d 4737
cc098dc7
IV		 4738 /* restore original MAC address */
4739 rtl_rar_set(tp, dev->perm_addr);
4740
4bb3f522 4741 spin_lock_irq(&tp->lock);
4742
4743 rtl8169_asic_down(ioaddr);
4744
4745 spin_unlock_irq(&tp->lock);
4746
861ab440 4747 if (system_state == SYSTEM_POWER_OFF) {
ca52efd5 4748 /* WoL fails with some 8168 when the receiver is disabled. */
4749 if (tp->features & RTL_FEATURE_WOL) {
4750 pci_clear_master(pdev);
4751
4752 RTL_W8(ChipCmd, CmdRxEnb);
4753 /* PCI commit */
4754 RTL_R8(ChipCmd);
4755 }
4756
861ab440
RW		 4757 pci_wake_from_d3(pdev, true);
4758 pci_set_power_state(pdev, PCI_D3hot);
4759 }
4760}
5d06a99f 4761
1da177e4
LT		 4762static struct pci_driver rtl8169_pci_driver = {
4763 .name = MODULENAME,
4764 .id_table = rtl8169_pci_tbl,
4765 .probe = rtl8169_init_one,
4766 .remove = __devexit_p(rtl8169_remove_one),
1765f95d 4767 .shutdown = rtl_shutdown,
861ab440 4768 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 4769};
4770
07d3f51f 4771static int __init rtl8169_init_module(void)
1da177e4 4772{
29917620 4773 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 4774}
4775
07d3f51f 4776static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 4777{
4778 pci_unregister_driver(&rtl8169_pci_driver);
4779}
4780
4781module_init(rtl8169_init_module);
4782module_exit(rtl8169_cleanup_module);
Linux 6.x block layer and io_uring tree(s)