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r8169: RX fifo overflow recovery
[linux-2.6-block.git] / drivers / net / r8169.c
CommitLineData
1da177e4
LT		 1/*
2=========================================================================
3 r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver for Linux kernel 2.4.x.
4 --------------------------------------------------------------------
5
6 History:
7 Feb 4 2002 - created initially by ShuChen <shuchen@realtek.com.tw>.
8 May 20 2002 - Add link status force-mode and TBI mode support.
9 2004 - Massive updates. See kernel SCM system for details.
10=========================================================================
11 1. [DEPRECATED: use ethtool instead] The media can be forced in 5 modes.
12 Command: 'insmod r8169 media = SET_MEDIA'
13 Ex: 'insmod r8169 media = 0x04' will force PHY to operate in 100Mpbs Half-duplex.
14
15 SET_MEDIA can be:
16 _10_Half = 0x01
17 _10_Full = 0x02
18 _100_Half = 0x04
19 _100_Full = 0x08
20 _1000_Full = 0x10
21
22 2. Support TBI mode.
23=========================================================================
24VERSION 1.1 <2002/10/4>
25
26 The bit4:0 of MII register 4 is called "selector field", and have to be
27 00001b to indicate support of IEEE std 802.3 during NWay process of
28 exchanging Link Code Word (FLP).
29
30VERSION 1.2 <2002/11/30>
31
32 - Large style cleanup
33 - Use ether_crc in stock kernel (linux/crc32.h)
34 - Copy mc_filter setup code from 8139cp
35 (includes an optimization, and avoids set_bit use)
36
37VERSION 1.6LK <2004/04/14>
38
39 - Merge of Realtek's version 1.6
40 - Conversion to DMA API
41 - Suspend/resume
42 - Endianness
43 - Misc Rx/Tx bugs
44
45VERSION 2.2LK <2005/01/25>
46
47 - RX csum, TX csum/SG, TSO
48 - VLAN
49 - baby (< 7200) Jumbo frames support
50 - Merge of Realtek's version 2.2 (new phy)
51 */
52
53#include <linux/module.h>
54#include <linux/moduleparam.h>
55#include <linux/pci.h>
56#include <linux/netdevice.h>
57#include <linux/etherdevice.h>
58#include <linux/delay.h>
59#include <linux/ethtool.h>
60#include <linux/mii.h>
61#include <linux/if_vlan.h>
62#include <linux/crc32.h>
63#include <linux/in.h>
64#include <linux/ip.h>
65#include <linux/tcp.h>
66#include <linux/init.h>
67#include <linux/dma-mapping.h>
68
69#include <asm/io.h>
70#include <asm/irq.h>
71
f7ccf420
SH		 72#ifdef CONFIG_R8169_NAPI
73#define NAPI_SUFFIX "-NAPI"
74#else
75#define NAPI_SUFFIX ""
76#endif
77
78#define RTL8169_VERSION "2.2LK" NAPI_SUFFIX
1da177e4
LT		 79#define MODULENAME "r8169"
80#define PFX MODULENAME ": "
81
82#ifdef RTL8169_DEBUG
83#define assert(expr) \
84 if(!(expr)) { \
85 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
86 #expr,__FILE__,__FUNCTION__,__LINE__); \
87 }
88#define dprintk(fmt, args...) do { printk(PFX fmt, ## args); } while (0)
89#else
90#define assert(expr) do {} while (0)
91#define dprintk(fmt, args...) do {} while (0)
92#endif /* RTL8169_DEBUG */
93
b57b7e5a 94#define R8169_MSG_DEFAULT \
f0e837d9 95 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 96
1da177e4
LT		 97#define TX_BUFFS_AVAIL(tp) \
98 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
99
100#ifdef CONFIG_R8169_NAPI
101#define rtl8169_rx_skb netif_receive_skb
0b50f81d 102#define rtl8169_rx_hwaccel_skb vlan_hwaccel_receive_skb
1da177e4
LT		 103#define rtl8169_rx_quota(count, quota) min(count, quota)
104#else
105#define rtl8169_rx_skb netif_rx
0b50f81d 106#define rtl8169_rx_hwaccel_skb vlan_hwaccel_rx
1da177e4
LT		 107#define rtl8169_rx_quota(count, quota) count
108#endif
109
110/* media options */
111#define MAX_UNITS 8
112static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
113static int num_media = 0;
114
115/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
f71e1309 116static const int max_interrupt_work = 20;
1da177e4
LT		 117
118/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
119 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 120static const int multicast_filter_limit = 32;
1da177e4
LT		 121
122/* MAC address length */
123#define MAC_ADDR_LEN 6
124
125#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
126#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
127#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
128#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
129#define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
130#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
131#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
132
133#define R8169_REGS_SIZE 256
134#define R8169_NAPI_WEIGHT 64
135#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
136#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
137#define RX_BUF_SIZE 1536 /* Rx Buffer size */
138#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
139#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
140
141#define RTL8169_TX_TIMEOUT (6*HZ)
142#define RTL8169_PHY_TIMEOUT (10*HZ)
143
144/* write/read MMIO register */
145#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
146#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
147#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
148#define RTL_R8(reg) readb (ioaddr + (reg))
149#define RTL_R16(reg) readw (ioaddr + (reg))
150#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
151
152enum mac_version {
153 RTL_GIGA_MAC_VER_B = 0x00,
154 /* RTL_GIGA_MAC_VER_C = 0x03, */
155 RTL_GIGA_MAC_VER_D = 0x01,
156 RTL_GIGA_MAC_VER_E = 0x02,
157 RTL_GIGA_MAC_VER_X = 0x04 /* Greater than RTL_GIGA_MAC_VER_E */
158};
159
160enum phy_version {
161 RTL_GIGA_PHY_VER_C = 0x03, /* PHY Reg 0x03 bit0-3 == 0x0000 */
162 RTL_GIGA_PHY_VER_D = 0x04, /* PHY Reg 0x03 bit0-3 == 0x0000 */
163 RTL_GIGA_PHY_VER_E = 0x05, /* PHY Reg 0x03 bit0-3 == 0x0000 */
164 RTL_GIGA_PHY_VER_F = 0x06, /* PHY Reg 0x03 bit0-3 == 0x0001 */
165 RTL_GIGA_PHY_VER_G = 0x07, /* PHY Reg 0x03 bit0-3 == 0x0002 */
166 RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */
167};
168
169
170#define _R(NAME,MAC,MASK) \
171 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
172
3c6bee1d 173static const struct {
1da177e4
LT		 174 const char *name;
175 u8 mac_version;
176 u32 RxConfigMask; /* Clears the bits supported by this chip */
177} rtl_chip_info[] = {
178 _R("RTL8169", RTL_GIGA_MAC_VER_B, 0xff7e1880),
179 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_D, 0xff7e1880),
180 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_E, 0xff7e1880),
181 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_X, 0xff7e1880),
182};
183#undef _R
184
185static struct pci_device_id rtl8169_pci_tbl[] = {
53456f60 186 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), },
de1e938e 187 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), },
53456f60
FR		 188 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), },
189 { PCI_DEVICE(0x16ec, 0x0116), },
86f0cd50 190 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024, },
1da177e4
LT		 191 {0,},
192};
193
194MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
195
196static int rx_copybreak = 200;
197static int use_dac;
b57b7e5a
SH		 198static struct {
199 u32 msg_enable;
200} debug = { -1 };
1da177e4
LT		 201
202enum RTL8169_registers {
203 MAC0 = 0, /* Ethernet hardware address. */
204 MAR0 = 8, /* Multicast filter. */
d4a3a0fc
SH		 205 CounterAddrLow = 0x10,
206 CounterAddrHigh = 0x14,
1da177e4
LT		 207 TxDescStartAddrLow = 0x20,
208 TxDescStartAddrHigh = 0x24,
209 TxHDescStartAddrLow = 0x28,
210 TxHDescStartAddrHigh = 0x2c,
211 FLASH = 0x30,
212 ERSR = 0x36,
213 ChipCmd = 0x37,
214 TxPoll = 0x38,
215 IntrMask = 0x3C,
216 IntrStatus = 0x3E,
217 TxConfig = 0x40,
218 RxConfig = 0x44,
219 RxMissed = 0x4C,
220 Cfg9346 = 0x50,
221 Config0 = 0x51,
222 Config1 = 0x52,
223 Config2 = 0x53,
224 Config3 = 0x54,
225 Config4 = 0x55,
226 Config5 = 0x56,
227 MultiIntr = 0x5C,
228 PHYAR = 0x60,
229 TBICSR = 0x64,
230 TBI_ANAR = 0x68,
231 TBI_LPAR = 0x6A,
232 PHYstatus = 0x6C,
233 RxMaxSize = 0xDA,
234 CPlusCmd = 0xE0,
235 IntrMitigate = 0xE2,
236 RxDescAddrLow = 0xE4,
237 RxDescAddrHigh = 0xE8,
238 EarlyTxThres = 0xEC,
239 FuncEvent = 0xF0,
240 FuncEventMask = 0xF4,
241 FuncPresetState = 0xF8,
242 FuncForceEvent = 0xFC,
243};
244
245enum RTL8169_register_content {
246 /* InterruptStatusBits */
247 SYSErr = 0x8000,
248 PCSTimeout = 0x4000,
249 SWInt = 0x0100,
250 TxDescUnavail = 0x80,
251 RxFIFOOver = 0x40,
252 LinkChg = 0x20,
253 RxOverflow = 0x10,
254 TxErr = 0x08,
255 TxOK = 0x04,
256 RxErr = 0x02,
257 RxOK = 0x01,
258
259 /* RxStatusDesc */
9dccf611
FR		 260 RxFOVF = (1 << 23),
261 RxRWT = (1 << 22),
262 RxRES = (1 << 21),
263 RxRUNT = (1 << 20),
264 RxCRC = (1 << 19),
1da177e4
LT		 265
266 /* ChipCmdBits */
267 CmdReset = 0x10,
268 CmdRxEnb = 0x08,
269 CmdTxEnb = 0x04,
270 RxBufEmpty = 0x01,
271
272 /* Cfg9346Bits */
273 Cfg9346_Lock = 0x00,
274 Cfg9346_Unlock = 0xC0,
275
276 /* rx_mode_bits */
277 AcceptErr = 0x20,
278 AcceptRunt = 0x10,
279 AcceptBroadcast = 0x08,
280 AcceptMulticast = 0x04,
281 AcceptMyPhys = 0x02,
282 AcceptAllPhys = 0x01,
283
284 /* RxConfigBits */
285 RxCfgFIFOShift = 13,
286 RxCfgDMAShift = 8,
287
288 /* TxConfigBits */
289 TxInterFrameGapShift = 24,
290 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
291
5d06a99f
FR		 292 /* Config1 register p.24 */
293 PMEnable = (1 << 0), /* Power Management Enable */
294
61a4dcc2
FR		 295 /* Config3 register p.25 */
296 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
297 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
298
5d06a99f 299 /* Config5 register p.27 */
61a4dcc2
FR		 300 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
301 MWF = (1 << 5), /* Accept Multicast wakeup frame */
302 UWF = (1 << 4), /* Accept Unicast wakeup frame */
303 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 304 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
305
1da177e4
LT		 306 /* TBICSR p.28 */
307 TBIReset = 0x80000000,
308 TBILoopback = 0x40000000,
309 TBINwEnable = 0x20000000,
310 TBINwRestart = 0x10000000,
311 TBILinkOk = 0x02000000,
312 TBINwComplete = 0x01000000,
313
314 /* CPlusCmd p.31 */
315 RxVlan = (1 << 6),
316 RxChkSum = (1 << 5),
317 PCIDAC = (1 << 4),
318 PCIMulRW = (1 << 3),
319
320 /* rtl8169_PHYstatus */
321 TBI_Enable = 0x80,
322 TxFlowCtrl = 0x40,
323 RxFlowCtrl = 0x20,
324 _1000bpsF = 0x10,
325 _100bps = 0x08,
326 _10bps = 0x04,
327 LinkStatus = 0x02,
328 FullDup = 0x01,
329
330 /* GIGABIT_PHY_registers */
331 PHY_CTRL_REG = 0,
332 PHY_STAT_REG = 1,
333 PHY_AUTO_NEGO_REG = 4,
334 PHY_1000_CTRL_REG = 9,
335
336 /* GIGABIT_PHY_REG_BIT */
337 PHY_Restart_Auto_Nego = 0x0200,
338 PHY_Enable_Auto_Nego = 0x1000,
339
340 /* PHY_STAT_REG = 1 */
341 PHY_Auto_Neco_Comp = 0x0020,
342
343 /* PHY_AUTO_NEGO_REG = 4 */
344 PHY_Cap_10_Half = 0x0020,
345 PHY_Cap_10_Full = 0x0040,
346 PHY_Cap_100_Half = 0x0080,
347 PHY_Cap_100_Full = 0x0100,
348
349 /* PHY_1000_CTRL_REG = 9 */
350 PHY_Cap_1000_Full = 0x0200,
351
352 PHY_Cap_Null = 0x0,
353
354 /* _MediaType */
355 _10_Half = 0x01,
356 _10_Full = 0x02,
357 _100_Half = 0x04,
358 _100_Full = 0x08,
359 _1000_Full = 0x10,
360
361 /* _TBICSRBit */
362 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 363
364 /* DumpCounterCommand */
365 CounterDump = 0x8,
1da177e4
LT		 366};
367
368enum _DescStatusBit {
369 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
370 RingEnd = (1 << 30), /* End of descriptor ring */
371 FirstFrag = (1 << 29), /* First segment of a packet */
372 LastFrag = (1 << 28), /* Final segment of a packet */
373
374 /* Tx private */
375 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
376 MSSShift = 16, /* MSS value position */
377 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
378 IPCS = (1 << 18), /* Calculate IP checksum */
379 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
380 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
381 TxVlanTag = (1 << 17), /* Add VLAN tag */
382
383 /* Rx private */
384 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
385 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
386
387#define RxProtoUDP (PID1)
388#define RxProtoTCP (PID0)
389#define RxProtoIP (PID1 | PID0)
390#define RxProtoMask RxProtoIP
391
392 IPFail = (1 << 16), /* IP checksum failed */
393 UDPFail = (1 << 15), /* UDP/IP checksum failed */
394 TCPFail = (1 << 14), /* TCP/IP checksum failed */
395 RxVlanTag = (1 << 16), /* VLAN tag available */
396};
397
398#define RsvdMask 0x3fffc000
399
400struct TxDesc {
401 u32 opts1;
402 u32 opts2;
403 u64 addr;
404};
405
406struct RxDesc {
407 u32 opts1;
408 u32 opts2;
409 u64 addr;
410};
411
412struct ring_info {
413 struct sk_buff *skb;
414 u32 len;
415 u8 __pad[sizeof(void *) - sizeof(u32)];
416};
417
418struct rtl8169_private {
419 void __iomem *mmio_addr; /* memory map physical address */
420 struct pci_dev *pci_dev; /* Index of PCI device */
421 struct net_device_stats stats; /* statistics of net device */
422 spinlock_t lock; /* spin lock flag */
b57b7e5a 423 u32 msg_enable;
1da177e4
LT		 424 int chipset;
425 int mac_version;
426 int phy_version;
427 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
428 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
429 u32 dirty_rx;
430 u32 dirty_tx;
431 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
432 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
433 dma_addr_t TxPhyAddr;
434 dma_addr_t RxPhyAddr;
435 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
436 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
437 unsigned rx_buf_sz;
438 struct timer_list timer;
439 u16 cp_cmd;
440 u16 intr_mask;
441 int phy_auto_nego_reg;
442 int phy_1000_ctrl_reg;
443#ifdef CONFIG_R8169_VLAN
444 struct vlan_group *vlgrp;
445#endif
446 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
447 void (*get_settings)(struct net_device *, struct ethtool_cmd *);
448 void (*phy_reset_enable)(void __iomem *);
449 unsigned int (*phy_reset_pending)(void __iomem *);
450 unsigned int (*link_ok)(void __iomem *);
451 struct work_struct task;
61a4dcc2 452 unsigned wol_enabled : 1;
1da177e4
LT		 453};
454
979b6c13 455MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4
LT		 456MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
457module_param_array(media, int, &num_media, 0);
df0a1bf6 458MODULE_PARM_DESC(media, "force phy operation. Deprecated by ethtool (8).");
1da177e4 459module_param(rx_copybreak, int, 0);
1b7efd58 460MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
1da177e4
LT		 461module_param(use_dac, int, 0);
462MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 463module_param_named(debug, debug.msg_enable, int, 0);
464MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 465MODULE_LICENSE("GPL");
466MODULE_VERSION(RTL8169_VERSION);
467
468static int rtl8169_open(struct net_device *dev);
469static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
470static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance,
471 struct pt_regs *regs);
472static int rtl8169_init_ring(struct net_device *dev);
473static void rtl8169_hw_start(struct net_device *dev);
474static int rtl8169_close(struct net_device *dev);
475static void rtl8169_set_rx_mode(struct net_device *dev);
476static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 477static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4
LT		 478static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
479 void __iomem *);
4dcb7d33 480static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4
LT		 481static void rtl8169_down(struct net_device *dev);
482
483#ifdef CONFIG_R8169_NAPI
484static int rtl8169_poll(struct net_device *dev, int *budget);
485#endif
486
487static const u16 rtl8169_intr_mask =
488 SYSErr | LinkChg | RxOverflow | RxFIFOOver | TxErr | TxOK | RxErr | RxOK;
489static const u16 rtl8169_napi_event =
490 RxOK | RxOverflow | RxFIFOOver | TxOK | TxErr;
491static const unsigned int rtl8169_rx_config =
492 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
493
494#define PHY_Cap_10_Half_Or_Less PHY_Cap_10_Half
495#define PHY_Cap_10_Full_Or_Less PHY_Cap_10_Full | PHY_Cap_10_Half_Or_Less
496#define PHY_Cap_100_Half_Or_Less PHY_Cap_100_Half | PHY_Cap_10_Full_Or_Less
497#define PHY_Cap_100_Full_Or_Less PHY_Cap_100_Full | PHY_Cap_100_Half_Or_Less
498
499static void mdio_write(void __iomem *ioaddr, int RegAddr, int value)
500{
501 int i;
502
503 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
1da177e4 504
2371408c 505 for (i = 20; i > 0; i--) {
1da177e4
LT		 506 /* Check if the RTL8169 has completed writing to the specified MII register */
507 if (!(RTL_R32(PHYAR) & 0x80000000))
508 break;
2371408c 509 udelay(25);
1da177e4
LT		 510 }
511}
512
513static int mdio_read(void __iomem *ioaddr, int RegAddr)
514{
515 int i, value = -1;
516
517 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
1da177e4 518
2371408c 519 for (i = 20; i > 0; i--) {
1da177e4
LT		 520 /* Check if the RTL8169 has completed retrieving data from the specified MII register */
521 if (RTL_R32(PHYAR) & 0x80000000) {
522 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
523 break;
524 }
2371408c 525 udelay(25);
1da177e4
LT		 526 }
527 return value;
528}
529
530static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
531{
532 RTL_W16(IntrMask, 0x0000);
533
534 RTL_W16(IntrStatus, 0xffff);
535}
536
537static void rtl8169_asic_down(void __iomem *ioaddr)
538{
539 RTL_W8(ChipCmd, 0x00);
540 rtl8169_irq_mask_and_ack(ioaddr);
541 RTL_R16(CPlusCmd);
542}
543
544static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
545{
546 return RTL_R32(TBICSR) & TBIReset;
547}
548
549static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
550{
551 return mdio_read(ioaddr, 0) & 0x8000;
552}
553
554static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
555{
556 return RTL_R32(TBICSR) & TBILinkOk;
557}
558
559static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
560{
561 return RTL_R8(PHYstatus) & LinkStatus;
562}
563
564static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
565{
566 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
567}
568
569static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
570{
571 unsigned int val;
572
573 val = (mdio_read(ioaddr, PHY_CTRL_REG) | 0x8000) & 0xffff;
574 mdio_write(ioaddr, PHY_CTRL_REG, val);
575}
576
577static void rtl8169_check_link_status(struct net_device *dev,
578 struct rtl8169_private *tp, void __iomem *ioaddr)
579{
580 unsigned long flags;
581
582 spin_lock_irqsave(&tp->lock, flags);
583 if (tp->link_ok(ioaddr)) {
584 netif_carrier_on(dev);
b57b7e5a
SH		 585 if (netif_msg_ifup(tp))
586 printk(KERN_INFO PFX "%s: link up\n", dev->name);
587 } else {
588 if (netif_msg_ifdown(tp))
589 printk(KERN_INFO PFX "%s: link down\n", dev->name);
1da177e4 590 netif_carrier_off(dev);
b57b7e5a 591 }
1da177e4
LT		 592 spin_unlock_irqrestore(&tp->lock, flags);
593}
594
595static void rtl8169_link_option(int idx, u8 *autoneg, u16 *speed, u8 *duplex)
596{
597 struct {
598 u16 speed;
599 u8 duplex;
600 u8 autoneg;
601 u8 media;
602 } link_settings[] = {
603 { SPEED_10, DUPLEX_HALF, AUTONEG_DISABLE, _10_Half },
604 { SPEED_10, DUPLEX_FULL, AUTONEG_DISABLE, _10_Full },
605 { SPEED_100, DUPLEX_HALF, AUTONEG_DISABLE, _100_Half },
606 { SPEED_100, DUPLEX_FULL, AUTONEG_DISABLE, _100_Full },
607 { SPEED_1000, DUPLEX_FULL, AUTONEG_DISABLE, _1000_Full },
608 /* Make TBI happy */
609 { SPEED_1000, DUPLEX_FULL, AUTONEG_ENABLE, 0xff }
610 }, *p;
611 unsigned char option;
612
613 option = ((idx < MAX_UNITS) && (idx >= 0)) ? media[idx] : 0xff;
614
b57b7e5a 615 if ((option != 0xff) && !idx && netif_msg_drv(&debug))
1da177e4
LT		 616 printk(KERN_WARNING PFX "media option is deprecated.\n");
617
618 for (p = link_settings; p->media != 0xff; p++) {
619 if (p->media == option)
620 break;
621 }
622 *autoneg = p->autoneg;
623 *speed = p->speed;
624 *duplex = p->duplex;
625}
626
61a4dcc2
FR		 627static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
628{
629 struct rtl8169_private *tp = netdev_priv(dev);
630 void __iomem *ioaddr = tp->mmio_addr;
631 u8 options;
632
633 wol->wolopts = 0;
634
635#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
636 wol->supported = WAKE_ANY;
637
638 spin_lock_irq(&tp->lock);
639
640 options = RTL_R8(Config1);
641 if (!(options & PMEnable))
642 goto out_unlock;
643
644 options = RTL_R8(Config3);
645 if (options & LinkUp)
646 wol->wolopts |= WAKE_PHY;
647 if (options & MagicPacket)
648 wol->wolopts |= WAKE_MAGIC;
649
650 options = RTL_R8(Config5);
651 if (options & UWF)
652 wol->wolopts |= WAKE_UCAST;
653 if (options & BWF)
654 wol->wolopts |= WAKE_BCAST;
655 if (options & MWF)
656 wol->wolopts |= WAKE_MCAST;
657
658out_unlock:
659 spin_unlock_irq(&tp->lock);
660}
661
662static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
663{
664 struct rtl8169_private *tp = netdev_priv(dev);
665 void __iomem *ioaddr = tp->mmio_addr;
666 int i;
667 static struct {
668 u32 opt;
669 u16 reg;
670 u8 mask;
671 } cfg[] = {
672 { WAKE_ANY, Config1, PMEnable },
673 { WAKE_PHY, Config3, LinkUp },
674 { WAKE_MAGIC, Config3, MagicPacket },
675 { WAKE_UCAST, Config5, UWF },
676 { WAKE_BCAST, Config5, BWF },
677 { WAKE_MCAST, Config5, MWF },
678 { WAKE_ANY, Config5, LanWake }
679 };
680
681 spin_lock_irq(&tp->lock);
682
683 RTL_W8(Cfg9346, Cfg9346_Unlock);
684
685 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
686 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
687 if (wol->wolopts & cfg[i].opt)
688 options |= cfg[i].mask;
689 RTL_W8(cfg[i].reg, options);
690 }
691
692 RTL_W8(Cfg9346, Cfg9346_Lock);
693
694 tp->wol_enabled = (wol->wolopts) ? 1 : 0;
695
696 spin_unlock_irq(&tp->lock);
697
698 return 0;
699}
700
1da177e4
LT		 701static void rtl8169_get_drvinfo(struct net_device *dev,
702 struct ethtool_drvinfo *info)
703{
704 struct rtl8169_private *tp = netdev_priv(dev);
705
706 strcpy(info->driver, MODULENAME);
707 strcpy(info->version, RTL8169_VERSION);
708 strcpy(info->bus_info, pci_name(tp->pci_dev));
709}
710
711static int rtl8169_get_regs_len(struct net_device *dev)
712{
713 return R8169_REGS_SIZE;
714}
715
716static int rtl8169_set_speed_tbi(struct net_device *dev,
717 u8 autoneg, u16 speed, u8 duplex)
718{
719 struct rtl8169_private *tp = netdev_priv(dev);
720 void __iomem *ioaddr = tp->mmio_addr;
721 int ret = 0;
722 u32 reg;
723
724 reg = RTL_R32(TBICSR);
725 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
726 (duplex == DUPLEX_FULL)) {
727 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
728 } else if (autoneg == AUTONEG_ENABLE)
729 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
730 else {
b57b7e5a
SH		 731 if (netif_msg_link(tp)) {
732 printk(KERN_WARNING "%s: "
733 "incorrect speed setting refused in TBI mode\n",
734 dev->name);
735 }
1da177e4
LT		 736 ret = -EOPNOTSUPP;
737 }
738
739 return ret;
740}
741
742static int rtl8169_set_speed_xmii(struct net_device *dev,
743 u8 autoneg, u16 speed, u8 duplex)
744{
745 struct rtl8169_private *tp = netdev_priv(dev);
746 void __iomem *ioaddr = tp->mmio_addr;
747 int auto_nego, giga_ctrl;
748
749 auto_nego = mdio_read(ioaddr, PHY_AUTO_NEGO_REG);
750 auto_nego &= ~(PHY_Cap_10_Half | PHY_Cap_10_Full |
751 PHY_Cap_100_Half | PHY_Cap_100_Full);
752 giga_ctrl = mdio_read(ioaddr, PHY_1000_CTRL_REG);
753 giga_ctrl &= ~(PHY_Cap_1000_Full | PHY_Cap_Null);
754
755 if (autoneg == AUTONEG_ENABLE) {
756 auto_nego |= (PHY_Cap_10_Half | PHY_Cap_10_Full |
757 PHY_Cap_100_Half | PHY_Cap_100_Full);
758 giga_ctrl |= PHY_Cap_1000_Full;
759 } else {
760 if (speed == SPEED_10)
761 auto_nego |= PHY_Cap_10_Half | PHY_Cap_10_Full;
762 else if (speed == SPEED_100)
763 auto_nego |= PHY_Cap_100_Half | PHY_Cap_100_Full;
764 else if (speed == SPEED_1000)
765 giga_ctrl |= PHY_Cap_1000_Full;
766
767 if (duplex == DUPLEX_HALF)
768 auto_nego &= ~(PHY_Cap_10_Full | PHY_Cap_100_Full);
726ecdcf
AG		 769
770 if (duplex == DUPLEX_FULL)
771 auto_nego &= ~(PHY_Cap_10_Half | PHY_Cap_100_Half);
1da177e4
LT		 772 }
773
774 tp->phy_auto_nego_reg = auto_nego;
775 tp->phy_1000_ctrl_reg = giga_ctrl;
776
777 mdio_write(ioaddr, PHY_AUTO_NEGO_REG, auto_nego);
778 mdio_write(ioaddr, PHY_1000_CTRL_REG, giga_ctrl);
779 mdio_write(ioaddr, PHY_CTRL_REG, PHY_Enable_Auto_Nego |
780 PHY_Restart_Auto_Nego);
781 return 0;
782}
783
784static int rtl8169_set_speed(struct net_device *dev,
785 u8 autoneg, u16 speed, u8 duplex)
786{
787 struct rtl8169_private *tp = netdev_priv(dev);
788 int ret;
789
790 ret = tp->set_speed(dev, autoneg, speed, duplex);
791
792 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & PHY_Cap_1000_Full))
793 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
794
795 return ret;
796}
797
798static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
799{
800 struct rtl8169_private *tp = netdev_priv(dev);
801 unsigned long flags;
802 int ret;
803
804 spin_lock_irqsave(&tp->lock, flags);
805 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
806 spin_unlock_irqrestore(&tp->lock, flags);
807
808 return ret;
809}
810
811static u32 rtl8169_get_rx_csum(struct net_device *dev)
812{
813 struct rtl8169_private *tp = netdev_priv(dev);
814
815 return tp->cp_cmd & RxChkSum;
816}
817
818static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
819{
820 struct rtl8169_private *tp = netdev_priv(dev);
821 void __iomem *ioaddr = tp->mmio_addr;
822 unsigned long flags;
823
824 spin_lock_irqsave(&tp->lock, flags);
825
826 if (data)
827 tp->cp_cmd |= RxChkSum;
828 else
829 tp->cp_cmd &= ~RxChkSum;
830
831 RTL_W16(CPlusCmd, tp->cp_cmd);
832 RTL_R16(CPlusCmd);
833
834 spin_unlock_irqrestore(&tp->lock, flags);
835
836 return 0;
837}
838
839#ifdef CONFIG_R8169_VLAN
840
841static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
842 struct sk_buff *skb)
843{
844 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
845 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
846}
847
848static void rtl8169_vlan_rx_register(struct net_device *dev,
849 struct vlan_group *grp)
850{
851 struct rtl8169_private *tp = netdev_priv(dev);
852 void __iomem *ioaddr = tp->mmio_addr;
853 unsigned long flags;
854
855 spin_lock_irqsave(&tp->lock, flags);
856 tp->vlgrp = grp;
857 if (tp->vlgrp)
858 tp->cp_cmd |= RxVlan;
859 else
860 tp->cp_cmd &= ~RxVlan;
861 RTL_W16(CPlusCmd, tp->cp_cmd);
862 RTL_R16(CPlusCmd);
863 spin_unlock_irqrestore(&tp->lock, flags);
864}
865
866static void rtl8169_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
867{
868 struct rtl8169_private *tp = netdev_priv(dev);
869 unsigned long flags;
870
871 spin_lock_irqsave(&tp->lock, flags);
872 if (tp->vlgrp)
873 tp->vlgrp->vlan_devices[vid] = NULL;
874 spin_unlock_irqrestore(&tp->lock, flags);
875}
876
877static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
878 struct sk_buff *skb)
879{
880 u32 opts2 = le32_to_cpu(desc->opts2);
881 int ret;
882
883 if (tp->vlgrp && (opts2 & RxVlanTag)) {
884 rtl8169_rx_hwaccel_skb(skb, tp->vlgrp,
885 swab16(opts2 & 0xffff));
886 ret = 0;
887 } else
888 ret = -1;
889 desc->opts2 = 0;
890 return ret;
891}
892
893#else /* !CONFIG_R8169_VLAN */
894
895static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
896 struct sk_buff *skb)
897{
898 return 0;
899}
900
901static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
902 struct sk_buff *skb)
903{
904 return -1;
905}
906
907#endif
908
909static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
910{
911 struct rtl8169_private *tp = netdev_priv(dev);
912 void __iomem *ioaddr = tp->mmio_addr;
913 u32 status;
914
915 cmd->supported =
916 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
917 cmd->port = PORT_FIBRE;
918 cmd->transceiver = XCVR_INTERNAL;
919
920 status = RTL_R32(TBICSR);
921 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
922 cmd->autoneg = !!(status & TBINwEnable);
923
924 cmd->speed = SPEED_1000;
925 cmd->duplex = DUPLEX_FULL; /* Always set */
926}
927
928static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
929{
930 struct rtl8169_private *tp = netdev_priv(dev);
931 void __iomem *ioaddr = tp->mmio_addr;
932 u8 status;
933
934 cmd->supported = SUPPORTED_10baseT_Half |
935 SUPPORTED_10baseT_Full |
936 SUPPORTED_100baseT_Half |
937 SUPPORTED_100baseT_Full |
938 SUPPORTED_1000baseT_Full |
939 SUPPORTED_Autoneg |
940 SUPPORTED_TP;
941
942 cmd->autoneg = 1;
943 cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
944
945 if (tp->phy_auto_nego_reg & PHY_Cap_10_Half)
946 cmd->advertising |= ADVERTISED_10baseT_Half;
947 if (tp->phy_auto_nego_reg & PHY_Cap_10_Full)
948 cmd->advertising |= ADVERTISED_10baseT_Full;
949 if (tp->phy_auto_nego_reg & PHY_Cap_100_Half)
950 cmd->advertising |= ADVERTISED_100baseT_Half;
951 if (tp->phy_auto_nego_reg & PHY_Cap_100_Full)
952 cmd->advertising |= ADVERTISED_100baseT_Full;
953 if (tp->phy_1000_ctrl_reg & PHY_Cap_1000_Full)
954 cmd->advertising |= ADVERTISED_1000baseT_Full;
955
956 status = RTL_R8(PHYstatus);
957
958 if (status & _1000bpsF)
959 cmd->speed = SPEED_1000;
960 else if (status & _100bps)
961 cmd->speed = SPEED_100;
962 else if (status & _10bps)
963 cmd->speed = SPEED_10;
964
965 cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ?
966 DUPLEX_FULL : DUPLEX_HALF;
967}
968
969static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
970{
971 struct rtl8169_private *tp = netdev_priv(dev);
972 unsigned long flags;
973
974 spin_lock_irqsave(&tp->lock, flags);
975
976 tp->get_settings(dev, cmd);
977
978 spin_unlock_irqrestore(&tp->lock, flags);
979 return 0;
980}
981
982static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
983 void *p)
984{
985 struct rtl8169_private *tp = netdev_priv(dev);
986 unsigned long flags;
987
988 if (regs->len > R8169_REGS_SIZE)
989 regs->len = R8169_REGS_SIZE;
990
991 spin_lock_irqsave(&tp->lock, flags);
992 memcpy_fromio(p, tp->mmio_addr, regs->len);
993 spin_unlock_irqrestore(&tp->lock, flags);
994}
995
b57b7e5a
SH		 996static u32 rtl8169_get_msglevel(struct net_device *dev)
997{
998 struct rtl8169_private *tp = netdev_priv(dev);
999
1000 return tp->msg_enable;
1001}
1002
1003static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1004{
1005 struct rtl8169_private *tp = netdev_priv(dev);
1006
1007 tp->msg_enable = value;
1008}
1009
d4a3a0fc
SH		 1010static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1011 "tx_packets",
1012 "rx_packets",
1013 "tx_errors",
1014 "rx_errors",
1015 "rx_missed",
1016 "align_errors",
1017 "tx_single_collisions",
1018 "tx_multi_collisions",
1019 "unicast",
1020 "broadcast",
1021 "multicast",
1022 "tx_aborted",
1023 "tx_underrun",
1024};
1025
1026struct rtl8169_counters {
1027 u64 tx_packets;
1028 u64 rx_packets;
1029 u64 tx_errors;
1030 u32 rx_errors;
1031 u16 rx_missed;
1032 u16 align_errors;
1033 u32 tx_one_collision;
1034 u32 tx_multi_collision;
1035 u64 rx_unicast;
1036 u64 rx_broadcast;
1037 u32 rx_multicast;
1038 u16 tx_aborted;
1039 u16 tx_underun;
1040};
1041
1042static int rtl8169_get_stats_count(struct net_device *dev)
1043{
1044 return ARRAY_SIZE(rtl8169_gstrings);
1045}
1046
1047static void rtl8169_get_ethtool_stats(struct net_device *dev,
1048 struct ethtool_stats *stats, u64 *data)
1049{
1050 struct rtl8169_private *tp = netdev_priv(dev);
1051 void __iomem *ioaddr = tp->mmio_addr;
1052 struct rtl8169_counters *counters;
1053 dma_addr_t paddr;
1054 u32 cmd;
1055
1056 ASSERT_RTNL();
1057
1058 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1059 if (!counters)
1060 return;
1061
1062 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1063 cmd = (u64)paddr & DMA_32BIT_MASK;
1064 RTL_W32(CounterAddrLow, cmd);
1065 RTL_W32(CounterAddrLow, cmd | CounterDump);
1066
1067 while (RTL_R32(CounterAddrLow) & CounterDump) {
1068 if (msleep_interruptible(1))
1069 break;
1070 }
1071
1072 RTL_W32(CounterAddrLow, 0);
1073 RTL_W32(CounterAddrHigh, 0);
1074
1075 data[0] = le64_to_cpu(counters->tx_packets);
1076 data[1] = le64_to_cpu(counters->rx_packets);
1077 data[2] = le64_to_cpu(counters->tx_errors);
1078 data[3] = le32_to_cpu(counters->rx_errors);
1079 data[4] = le16_to_cpu(counters->rx_missed);
1080 data[5] = le16_to_cpu(counters->align_errors);
1081 data[6] = le32_to_cpu(counters->tx_one_collision);
1082 data[7] = le32_to_cpu(counters->tx_multi_collision);
1083 data[8] = le64_to_cpu(counters->rx_unicast);
1084 data[9] = le64_to_cpu(counters->rx_broadcast);
1085 data[10] = le32_to_cpu(counters->rx_multicast);
1086 data[11] = le16_to_cpu(counters->tx_aborted);
1087 data[12] = le16_to_cpu(counters->tx_underun);
1088
1089 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1090}
1091
1092static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1093{
1094 switch(stringset) {
1095 case ETH_SS_STATS:
1096 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1097 break;
1098 }
1099}
1100
1101
1da177e4
LT		 1102static struct ethtool_ops rtl8169_ethtool_ops = {
1103 .get_drvinfo = rtl8169_get_drvinfo,
1104 .get_regs_len = rtl8169_get_regs_len,
1105 .get_link = ethtool_op_get_link,
1106 .get_settings = rtl8169_get_settings,
1107 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1108 .get_msglevel = rtl8169_get_msglevel,
1109 .set_msglevel = rtl8169_set_msglevel,
1da177e4
LT		 1110 .get_rx_csum = rtl8169_get_rx_csum,
1111 .set_rx_csum = rtl8169_set_rx_csum,
1112 .get_tx_csum = ethtool_op_get_tx_csum,
1113 .set_tx_csum = ethtool_op_set_tx_csum,
1114 .get_sg = ethtool_op_get_sg,
1115 .set_sg = ethtool_op_set_sg,
1116 .get_tso = ethtool_op_get_tso,
1117 .set_tso = ethtool_op_set_tso,
1118 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1119 .get_wol = rtl8169_get_wol,
1120 .set_wol = rtl8169_set_wol,
d4a3a0fc
SH		 1121 .get_strings = rtl8169_get_strings,
1122 .get_stats_count = rtl8169_get_stats_count,
1123 .get_ethtool_stats = rtl8169_get_ethtool_stats,
6d6525b7 1124 .get_perm_addr = ethtool_op_get_perm_addr,
1da177e4
LT		 1125};
1126
1127static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg, int bitnum,
1128 int bitval)
1129{
1130 int val;
1131
1132 val = mdio_read(ioaddr, reg);
1133 val = (bitval == 1) ?
1134 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
1135 mdio_write(ioaddr, reg, val & 0xffff);
1136}
1137
1138static void rtl8169_get_mac_version(struct rtl8169_private *tp, void __iomem *ioaddr)
1139{
1140 const struct {
1141 u32 mask;
1142 int mac_version;
1143 } mac_info[] = {
1144 { 0x1 << 28, RTL_GIGA_MAC_VER_X },
1145 { 0x1 << 26, RTL_GIGA_MAC_VER_E },
1146 { 0x1 << 23, RTL_GIGA_MAC_VER_D },
1147 { 0x00000000, RTL_GIGA_MAC_VER_B } /* Catch-all */
1148 }, *p = mac_info;
1149 u32 reg;
1150
1151 reg = RTL_R32(TxConfig) & 0x7c800000;
1152 while ((reg & p->mask) != p->mask)
1153 p++;
1154 tp->mac_version = p->mac_version;
1155}
1156
1157static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1158{
1159 struct {
1160 int version;
1161 char *msg;
1162 } mac_print[] = {
1163 { RTL_GIGA_MAC_VER_E, "RTL_GIGA_MAC_VER_E" },
1164 { RTL_GIGA_MAC_VER_D, "RTL_GIGA_MAC_VER_D" },
1165 { RTL_GIGA_MAC_VER_B, "RTL_GIGA_MAC_VER_B" },
1166 { 0, NULL }
1167 }, *p;
1168
1169 for (p = mac_print; p->msg; p++) {
1170 if (tp->mac_version == p->version) {
1171 dprintk("mac_version == %s (%04d)\n", p->msg,
1172 p->version);
1173 return;
1174 }
1175 }
1176 dprintk("mac_version == Unknown\n");
1177}
1178
1179static void rtl8169_get_phy_version(struct rtl8169_private *tp, void __iomem *ioaddr)
1180{
1181 const struct {
1182 u16 mask;
1183 u16 set;
1184 int phy_version;
1185 } phy_info[] = {
1186 { 0x000f, 0x0002, RTL_GIGA_PHY_VER_G },
1187 { 0x000f, 0x0001, RTL_GIGA_PHY_VER_F },
1188 { 0x000f, 0x0000, RTL_GIGA_PHY_VER_E },
1189 { 0x0000, 0x0000, RTL_GIGA_PHY_VER_D } /* Catch-all */
1190 }, *p = phy_info;
1191 u16 reg;
1192
1193 reg = mdio_read(ioaddr, 3) & 0xffff;
1194 while ((reg & p->mask) != p->set)
1195 p++;
1196 tp->phy_version = p->phy_version;
1197}
1198
1199static void rtl8169_print_phy_version(struct rtl8169_private *tp)
1200{
1201 struct {
1202 int version;
1203 char *msg;
1204 u32 reg;
1205 } phy_print[] = {
1206 { RTL_GIGA_PHY_VER_G, "RTL_GIGA_PHY_VER_G", 0x0002 },
1207 { RTL_GIGA_PHY_VER_F, "RTL_GIGA_PHY_VER_F", 0x0001 },
1208 { RTL_GIGA_PHY_VER_E, "RTL_GIGA_PHY_VER_E", 0x0000 },
1209 { RTL_GIGA_PHY_VER_D, "RTL_GIGA_PHY_VER_D", 0x0000 },
1210 { 0, NULL, 0x0000 }
1211 }, *p;
1212
1213 for (p = phy_print; p->msg; p++) {
1214 if (tp->phy_version == p->version) {
1215 dprintk("phy_version == %s (%04x)\n", p->msg, p->reg);
1216 return;
1217 }
1218 }
1219 dprintk("phy_version == Unknown\n");
1220}
1221
1222static void rtl8169_hw_phy_config(struct net_device *dev)
1223{
1224 struct rtl8169_private *tp = netdev_priv(dev);
1225 void __iomem *ioaddr = tp->mmio_addr;
1226 struct {
1227 u16 regs[5]; /* Beware of bit-sign propagation */
1228 } phy_magic[5] = { {
1229 { 0x0000, //w 4 15 12 0
1230 0x00a1, //w 3 15 0 00a1
1231 0x0008, //w 2 15 0 0008
1232 0x1020, //w 1 15 0 1020
1233 0x1000 } },{ //w 0 15 0 1000
1234 { 0x7000, //w 4 15 12 7
1235 0xff41, //w 3 15 0 ff41
1236 0xde60, //w 2 15 0 de60
1237 0x0140, //w 1 15 0 0140
1238 0x0077 } },{ //w 0 15 0 0077
1239 { 0xa000, //w 4 15 12 a
1240 0xdf01, //w 3 15 0 df01
1241 0xdf20, //w 2 15 0 df20
1242 0xff95, //w 1 15 0 ff95
1243 0xfa00 } },{ //w 0 15 0 fa00
1244 { 0xb000, //w 4 15 12 b
1245 0xff41, //w 3 15 0 ff41
1246 0xde20, //w 2 15 0 de20
1247 0x0140, //w 1 15 0 0140
1248 0x00bb } },{ //w 0 15 0 00bb
1249 { 0xf000, //w 4 15 12 f
1250 0xdf01, //w 3 15 0 df01
1251 0xdf20, //w 2 15 0 df20
1252 0xff95, //w 1 15 0 ff95
1253 0xbf00 } //w 0 15 0 bf00
1254 }
1255 }, *p = phy_magic;
1256 int i;
1257
1258 rtl8169_print_mac_version(tp);
1259 rtl8169_print_phy_version(tp);
1260
1261 if (tp->mac_version <= RTL_GIGA_MAC_VER_B)
1262 return;
1263 if (tp->phy_version >= RTL_GIGA_PHY_VER_H)
1264 return;
1265
1266 dprintk("MAC version != 0 && PHY version == 0 or 1\n");
1267 dprintk("Do final_reg2.cfg\n");
1268
1269 /* Shazam ! */
1270
1271 if (tp->mac_version == RTL_GIGA_MAC_VER_X) {
1272 mdio_write(ioaddr, 31, 0x0001);
1273 mdio_write(ioaddr, 9, 0x273a);
1274 mdio_write(ioaddr, 14, 0x7bfb);
1275 mdio_write(ioaddr, 27, 0x841e);
1276
1277 mdio_write(ioaddr, 31, 0x0002);
1278 mdio_write(ioaddr, 1, 0x90d0);
1279 mdio_write(ioaddr, 31, 0x0000);
1280 return;
1281 }
1282
1283 /* phy config for RTL8169s mac_version C chip */
1284 mdio_write(ioaddr, 31, 0x0001); //w 31 2 0 1
1285 mdio_write(ioaddr, 21, 0x1000); //w 21 15 0 1000
1286 mdio_write(ioaddr, 24, 0x65c7); //w 24 15 0 65c7
1287 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1288
1289 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1290 int val, pos = 4;
1291
1292 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1293 mdio_write(ioaddr, pos, val);
1294 while (--pos >= 0)
1295 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1296 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1297 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1298 }
1299 mdio_write(ioaddr, 31, 0x0000); //w 31 2 0 0
1300}
1301
1302static void rtl8169_phy_timer(unsigned long __opaque)
1303{
1304 struct net_device *dev = (struct net_device *)__opaque;
1305 struct rtl8169_private *tp = netdev_priv(dev);
1306 struct timer_list *timer = &tp->timer;
1307 void __iomem *ioaddr = tp->mmio_addr;
1308 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1309
1310 assert(tp->mac_version > RTL_GIGA_MAC_VER_B);
1311 assert(tp->phy_version < RTL_GIGA_PHY_VER_H);
1312
1313 if (!(tp->phy_1000_ctrl_reg & PHY_Cap_1000_Full))
1314 return;
1315
1316 spin_lock_irq(&tp->lock);
1317
1318 if (tp->phy_reset_pending(ioaddr)) {
1319 /*
1320 * A busy loop could burn quite a few cycles on nowadays CPU.
1321 * Let's delay the execution of the timer for a few ticks.
1322 */
1323 timeout = HZ/10;
1324 goto out_mod_timer;
1325 }
1326
1327 if (tp->link_ok(ioaddr))
1328 goto out_unlock;
1329
b57b7e5a
SH		 1330 if (netif_msg_link(tp))
1331 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1da177e4
LT		 1332
1333 tp->phy_reset_enable(ioaddr);
1334
1335out_mod_timer:
1336 mod_timer(timer, jiffies + timeout);
1337out_unlock:
1338 spin_unlock_irq(&tp->lock);
1339}
1340
1341static inline void rtl8169_delete_timer(struct net_device *dev)
1342{
1343 struct rtl8169_private *tp = netdev_priv(dev);
1344 struct timer_list *timer = &tp->timer;
1345
1346 if ((tp->mac_version <= RTL_GIGA_MAC_VER_B) ||
1347 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1348 return;
1349
1350 del_timer_sync(timer);
1351}
1352
1353static inline void rtl8169_request_timer(struct net_device *dev)
1354{
1355 struct rtl8169_private *tp = netdev_priv(dev);
1356 struct timer_list *timer = &tp->timer;
1357
1358 if ((tp->mac_version <= RTL_GIGA_MAC_VER_B) ||
1359 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1360 return;
1361
1362 init_timer(timer);
1363 timer->expires = jiffies + RTL8169_PHY_TIMEOUT;
1364 timer->data = (unsigned long)(dev);
1365 timer->function = rtl8169_phy_timer;
1366 add_timer(timer);
1367}
1368
1369#ifdef CONFIG_NET_POLL_CONTROLLER
1370/*
1371 * Polling 'interrupt' - used by things like netconsole to send skbs
1372 * without having to re-enable interrupts. It's not called while
1373 * the interrupt routine is executing.
1374 */
1375static void rtl8169_netpoll(struct net_device *dev)
1376{
1377 struct rtl8169_private *tp = netdev_priv(dev);
1378 struct pci_dev *pdev = tp->pci_dev;
1379
1380 disable_irq(pdev->irq);
1381 rtl8169_interrupt(pdev->irq, dev, NULL);
1382 enable_irq(pdev->irq);
1383}
1384#endif
1385
a2b98a69
FR		 1386static void __rtl8169_set_mac_addr(struct net_device *dev, void __iomem *ioaddr)
1387{
1388 unsigned int i, j;
1389
1390 RTL_W8(Cfg9346, Cfg9346_Unlock);
1391 for (i = 0; i < 2; i++) {
1392 __le32 l = 0;
1393
1394 for (j = 0; j < 4; j++) {
1395 l <<= 8;
1396 l |= dev->dev_addr[4*i + j];
1397 }
1398 RTL_W32(MAC0 + 4*i, cpu_to_be32(l));
1399 }
1400 RTL_W8(Cfg9346, Cfg9346_Lock);
1401}
1402
1403static int rtl8169_set_mac_addr(struct net_device *dev, void *p)
1404{
1405 struct rtl8169_private *tp = netdev_priv(dev);
1406 struct sockaddr *addr = p;
1407
1408 if (!is_valid_ether_addr(addr->sa_data))
1409 return -EINVAL;
1410
1411 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1412
1413 if (netif_running(dev)) {
1414 spin_lock_irq(&tp->lock);
1415 __rtl8169_set_mac_addr(dev, tp->mmio_addr);
1416 spin_unlock_irq(&tp->lock);
1417 }
1418 return 0;
1419}
1420
1da177e4
LT		 1421static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1422 void __iomem *ioaddr)
1423{
1424 iounmap(ioaddr);
1425 pci_release_regions(pdev);
1426 pci_disable_device(pdev);
1427 free_netdev(dev);
1428}
1429
1430static int __devinit
1431rtl8169_init_board(struct pci_dev *pdev, struct net_device **dev_out,
1432 void __iomem **ioaddr_out)
1433{
1434 void __iomem *ioaddr;
1435 struct net_device *dev;
1436 struct rtl8169_private *tp;
1437 int rc = -ENOMEM, i, acpi_idle_state = 0, pm_cap;
1438
1439 assert(ioaddr_out != NULL);
1440
1441 /* dev zeroed in alloc_etherdev */
1442 dev = alloc_etherdev(sizeof (*tp));
1443 if (dev == NULL) {
b57b7e5a 1444 if (netif_msg_drv(&debug))
9b91cf9d 1445 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
1da177e4
LT		 1446 goto err_out;
1447 }
1448
1449 SET_MODULE_OWNER(dev);
1450 SET_NETDEV_DEV(dev, &pdev->dev);
1451 tp = netdev_priv(dev);
b57b7e5a 1452 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4
LT		 1453
1454 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1455 rc = pci_enable_device(pdev);
b57b7e5a 1456 if (rc < 0) {
2e8a538d 1457 if (netif_msg_probe(tp))
9b91cf9d 1458 dev_err(&pdev->dev, "enable failure\n");
1da177e4
LT		 1459 goto err_out_free_dev;
1460 }
1461
1462 rc = pci_set_mwi(pdev);
1463 if (rc < 0)
1464 goto err_out_disable;
1465
1466 /* save power state before pci_enable_device overwrites it */
1467 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
1468 if (pm_cap) {
1469 u16 pwr_command;
1470
1471 pci_read_config_word(pdev, pm_cap + PCI_PM_CTRL, &pwr_command);
1472 acpi_idle_state = pwr_command & PCI_PM_CTRL_STATE_MASK;
1473 } else {
2e8a538d 1474 if (netif_msg_probe(tp))
9b91cf9d 1475 dev_err(&pdev->dev,
e53091fa 1476 "PowerManagement capability not found.\n");
1da177e4
LT		 1477 }
1478
1479 /* make sure PCI base addr 1 is MMIO */
1480 if (!(pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
2e8a538d 1481 if (netif_msg_probe(tp))
9b91cf9d 1482 dev_err(&pdev->dev,
b57b7e5a 1483 "region #1 not an MMIO resource, aborting\n");
1da177e4
LT		 1484 rc = -ENODEV;
1485 goto err_out_mwi;
1486 }
1487 /* check for weird/broken PCI region reporting */
1488 if (pci_resource_len(pdev, 1) < R8169_REGS_SIZE) {
2e8a538d 1489 if (netif_msg_probe(tp))
9b91cf9d 1490 dev_err(&pdev->dev,
b57b7e5a 1491 "Invalid PCI region size(s), aborting\n");
1da177e4
LT		 1492 rc = -ENODEV;
1493 goto err_out_mwi;
1494 }
1495
1496 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 1497 if (rc < 0) {
2e8a538d 1498 if (netif_msg_probe(tp))
9b91cf9d 1499 dev_err(&pdev->dev, "could not request regions.\n");
1da177e4
LT		 1500 goto err_out_mwi;
1501 }
1502
1503 tp->cp_cmd = PCIMulRW | RxChkSum;
1504
1505 if ((sizeof(dma_addr_t) > 4) &&
1506 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1507 tp->cp_cmd |= PCIDAC;
1508 dev->features |= NETIF_F_HIGHDMA;
1509 } else {
1510 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1511 if (rc < 0) {
2e8a538d 1512 if (netif_msg_probe(tp))
9b91cf9d 1513 dev_err(&pdev->dev,
b57b7e5a 1514 "DMA configuration failed.\n");
1da177e4
LT		 1515 goto err_out_free_res;
1516 }
1517 }
1518
1519 pci_set_master(pdev);
1520
1521 /* ioremap MMIO region */
1522 ioaddr = ioremap(pci_resource_start(pdev, 1), R8169_REGS_SIZE);
1523 if (ioaddr == NULL) {
b57b7e5a 1524 if (netif_msg_probe(tp))
9b91cf9d 1525 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1da177e4
LT		 1526 rc = -EIO;
1527 goto err_out_free_res;
1528 }
1529
1530 /* Unneeded ? Don't mess with Mrs. Murphy. */
1531 rtl8169_irq_mask_and_ack(ioaddr);
1532
1533 /* Soft reset the chip. */
1534 RTL_W8(ChipCmd, CmdReset);
1535
1536 /* Check that the chip has finished the reset. */
1537 for (i = 1000; i > 0; i--) {
1538 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1539 break;
1540 udelay(10);
1541 }
1542
1543 /* Identify chip attached to board */
1544 rtl8169_get_mac_version(tp, ioaddr);
1545 rtl8169_get_phy_version(tp, ioaddr);
1546
1547 rtl8169_print_mac_version(tp);
1548 rtl8169_print_phy_version(tp);
1549
1550 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) {
1551 if (tp->mac_version == rtl_chip_info[i].mac_version)
1552 break;
1553 }
1554 if (i < 0) {
1555 /* Unknown chip: assume array element #0, original RTL-8169 */
b57b7e5a 1556 if (netif_msg_probe(tp)) {
2e8a538d 1557 dev_printk(KERN_DEBUG, &pdev->dev,
b57b7e5a 1558 "unknown chip version, assuming %s\n",
2e8a538d 1559 rtl_chip_info[0].name);
b57b7e5a 1560 }
1da177e4
LT		 1561 i++;
1562 }
1563 tp->chipset = i;
1564
5d06a99f
FR		 1565 RTL_W8(Cfg9346, Cfg9346_Unlock);
1566 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1567 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
1568 RTL_W8(Cfg9346, Cfg9346_Lock);
1569
1da177e4
LT		 1570 *ioaddr_out = ioaddr;
1571 *dev_out = dev;
1572out:
1573 return rc;
1574
1575err_out_free_res:
1576 pci_release_regions(pdev);
1577
1578err_out_mwi:
1579 pci_clear_mwi(pdev);
1580
1581err_out_disable:
1582 pci_disable_device(pdev);
1583
1584err_out_free_dev:
1585 free_netdev(dev);
1586err_out:
1587 *ioaddr_out = NULL;
1588 *dev_out = NULL;
1589 goto out;
1590}
1591
1592static int __devinit
1593rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1594{
1595 struct net_device *dev = NULL;
1596 struct rtl8169_private *tp;
1597 void __iomem *ioaddr = NULL;
1598 static int board_idx = -1;
1da177e4
LT		 1599 u8 autoneg, duplex;
1600 u16 speed;
1601 int i, rc;
1602
1603 assert(pdev != NULL);
1604 assert(ent != NULL);
1605
1606 board_idx++;
1607
b57b7e5a 1608 if (netif_msg_drv(&debug)) {
1da177e4
LT		 1609 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1610 MODULENAME, RTL8169_VERSION);
1da177e4
LT		 1611 }
1612
1613 rc = rtl8169_init_board(pdev, &dev, &ioaddr);
1614 if (rc)
1615 return rc;
1616
1617 tp = netdev_priv(dev);
1618 assert(ioaddr != NULL);
1619
1620 if (RTL_R8(PHYstatus) & TBI_Enable) {
1621 tp->set_speed = rtl8169_set_speed_tbi;
1622 tp->get_settings = rtl8169_gset_tbi;
1623 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1624 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1625 tp->link_ok = rtl8169_tbi_link_ok;
1626
1627 tp->phy_1000_ctrl_reg = PHY_Cap_1000_Full; /* Implied by TBI */
1628 } else {
1629 tp->set_speed = rtl8169_set_speed_xmii;
1630 tp->get_settings = rtl8169_gset_xmii;
1631 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1632 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1633 tp->link_ok = rtl8169_xmii_link_ok;
1634 }
1635
1636 /* Get MAC address. FIXME: read EEPROM */
1637 for (i = 0; i < MAC_ADDR_LEN; i++)
1638 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 1639 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 1640
1641 dev->open = rtl8169_open;
1642 dev->hard_start_xmit = rtl8169_start_xmit;
1643 dev->get_stats = rtl8169_get_stats;
1644 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1645 dev->stop = rtl8169_close;
1646 dev->tx_timeout = rtl8169_tx_timeout;
1647 dev->set_multicast_list = rtl8169_set_rx_mode;
a2b98a69 1648 dev->set_mac_address = rtl8169_set_mac_addr;
1da177e4
LT		 1649 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1650 dev->irq = pdev->irq;
1651 dev->base_addr = (unsigned long) ioaddr;
1652 dev->change_mtu = rtl8169_change_mtu;
1653
1654#ifdef CONFIG_R8169_NAPI
1655 dev->poll = rtl8169_poll;
1656 dev->weight = R8169_NAPI_WEIGHT;
1da177e4
LT		 1657#endif
1658
1659#ifdef CONFIG_R8169_VLAN
1660 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1661 dev->vlan_rx_register = rtl8169_vlan_rx_register;
1662 dev->vlan_rx_kill_vid = rtl8169_vlan_rx_kill_vid;
1663#endif
1664
1665#ifdef CONFIG_NET_POLL_CONTROLLER
1666 dev->poll_controller = rtl8169_netpoll;
1667#endif
1668
1669 tp->intr_mask = 0xffff;
1670 tp->pci_dev = pdev;
1671 tp->mmio_addr = ioaddr;
1672
1673 spin_lock_init(&tp->lock);
1674
1675 rc = register_netdev(dev);
1676 if (rc) {
1677 rtl8169_release_board(pdev, dev, ioaddr);
1678 return rc;
1679 }
1680
b57b7e5a
SH		 1681 if (netif_msg_probe(tp)) {
1682 printk(KERN_DEBUG "%s: Identified chip type is '%s'.\n",
1683 dev->name, rtl_chip_info[tp->chipset].name);
1684 }
1da177e4
LT		 1685
1686 pci_set_drvdata(pdev, dev);
1687
b57b7e5a
SH		 1688 if (netif_msg_probe(tp)) {
1689 printk(KERN_INFO "%s: %s at 0x%lx, "
1690 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1691 "IRQ %d\n",
1692 dev->name,
1693 rtl_chip_info[ent->driver_data].name,
1694 dev->base_addr,
1695 dev->dev_addr[0], dev->dev_addr[1],
1696 dev->dev_addr[2], dev->dev_addr[3],
1697 dev->dev_addr[4], dev->dev_addr[5], dev->irq);
1698 }
1da177e4
LT		 1699
1700 rtl8169_hw_phy_config(dev);
1701
1702 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1703 RTL_W8(0x82, 0x01);
1704
1705 if (tp->mac_version < RTL_GIGA_MAC_VER_E) {
1706 dprintk("Set PCI Latency=0x40\n");
1707 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40);
1708 }
1709
1710 if (tp->mac_version == RTL_GIGA_MAC_VER_D) {
1711 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1712 RTL_W8(0x82, 0x01);
1713 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1714 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1715 }
1716
1717 rtl8169_link_option(board_idx, &autoneg, &speed, &duplex);
1718
1719 rtl8169_set_speed(dev, autoneg, speed, duplex);
1720
b57b7e5a 1721 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1da177e4
LT		 1722 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1723
1724 return 0;
1725}
1726
1727static void __devexit
1728rtl8169_remove_one(struct pci_dev *pdev)
1729{
1730 struct net_device *dev = pci_get_drvdata(pdev);
1731 struct rtl8169_private *tp = netdev_priv(dev);
1732
1733 assert(dev != NULL);
1734 assert(tp != NULL);
1735
1736 unregister_netdev(dev);
1737 rtl8169_release_board(pdev, dev, tp->mmio_addr);
1738 pci_set_drvdata(pdev, NULL);
1739}
1740
1da177e4
LT		 1741static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
1742 struct net_device *dev)
1743{
1744 unsigned int mtu = dev->mtu;
1745
1746 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1747}
1748
1749static int rtl8169_open(struct net_device *dev)
1750{
1751 struct rtl8169_private *tp = netdev_priv(dev);
1752 struct pci_dev *pdev = tp->pci_dev;
1753 int retval;
1754
1755 rtl8169_set_rxbufsize(tp, dev);
1756
1757 retval =
1fb9df5d 1758 request_irq(dev->irq, rtl8169_interrupt, IRQF_SHARED, dev->name, dev);
1da177e4
LT		 1759 if (retval < 0)
1760 goto out;
1761
1762 retval = -ENOMEM;
1763
1764 /*
1765 * Rx and Tx desscriptors needs 256 bytes alignment.
1766 * pci_alloc_consistent provides more.
1767 */
1768 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1769 &tp->TxPhyAddr);
1770 if (!tp->TxDescArray)
1771 goto err_free_irq;
1772
1773 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1774 &tp->RxPhyAddr);
1775 if (!tp->RxDescArray)
1776 goto err_free_tx;
1777
1778 retval = rtl8169_init_ring(dev);
1779 if (retval < 0)
1780 goto err_free_rx;
1781
1782 INIT_WORK(&tp->task, NULL, dev);
1783
1784 rtl8169_hw_start(dev);
1785
1786 rtl8169_request_timer(dev);
1787
1788 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1789out:
1790 return retval;
1791
1792err_free_rx:
1793 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1794 tp->RxPhyAddr);
1795err_free_tx:
1796 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1797 tp->TxPhyAddr);
1798err_free_irq:
1799 free_irq(dev->irq, dev);
1800 goto out;
1801}
1802
1803static void rtl8169_hw_reset(void __iomem *ioaddr)
1804{
1805 /* Disable interrupts */
1806 rtl8169_irq_mask_and_ack(ioaddr);
1807
1808 /* Reset the chipset */
1809 RTL_W8(ChipCmd, CmdReset);
1810
1811 /* PCI commit */
1812 RTL_R8(ChipCmd);
1813}
1814
1815static void
1816rtl8169_hw_start(struct net_device *dev)
1817{
1818 struct rtl8169_private *tp = netdev_priv(dev);
1819 void __iomem *ioaddr = tp->mmio_addr;
1820 u32 i;
1821
1822 /* Soft reset the chip. */
1823 RTL_W8(ChipCmd, CmdReset);
1824
1825 /* Check that the chip has finished the reset. */
1826 for (i = 1000; i > 0; i--) {
1827 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1828 break;
1829 udelay(10);
1830 }
1831
1832 RTL_W8(Cfg9346, Cfg9346_Unlock);
1833 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1834 RTL_W8(EarlyTxThres, EarlyTxThld);
1835
126fa4b9
FR		 1836 /* Low hurts. Let's disable the filtering. */
1837 RTL_W16(RxMaxSize, 16383);
1da177e4
LT		 1838
1839 /* Set Rx Config register */
1840 i = rtl8169_rx_config |
1841 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1842 RTL_W32(RxConfig, i);
1843
1844 /* Set DMA burst size and Interframe Gap Time */
1845 RTL_W32(TxConfig,
1846 (TX_DMA_BURST << TxDMAShift) | (InterFrameGap <<
1847 TxInterFrameGapShift));
1848 tp->cp_cmd |= RTL_R16(CPlusCmd);
1849 RTL_W16(CPlusCmd, tp->cp_cmd);
1850
1851 if ((tp->mac_version == RTL_GIGA_MAC_VER_D) ||
1852 (tp->mac_version == RTL_GIGA_MAC_VER_E)) {
1853 dprintk(KERN_INFO PFX "Set MAC Reg C+CR Offset 0xE0. "
1854 "Bit-3 and bit-14 MUST be 1\n");
1855 tp->cp_cmd |= (1 << 14) | PCIMulRW;
1856 RTL_W16(CPlusCmd, tp->cp_cmd);
1857 }
1858
1859 /*
1860 * Undocumented corner. Supposedly:
1861 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
1862 */
1863 RTL_W16(IntrMitigate, 0x0000);
1864
1865 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr & DMA_32BIT_MASK));
1866 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr >> 32));
1867 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr & DMA_32BIT_MASK));
1868 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr >> 32));
1869 RTL_W8(Cfg9346, Cfg9346_Lock);
1870 udelay(10);
1871
1872 RTL_W32(RxMissed, 0);
1873
1874 rtl8169_set_rx_mode(dev);
1875
1876 /* no early-rx interrupts */
1877 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
1878
1879 /* Enable all known interrupts by setting the interrupt mask. */
1880 RTL_W16(IntrMask, rtl8169_intr_mask);
1881
a2b98a69
FR		 1882 __rtl8169_set_mac_addr(dev, ioaddr);
1883
1da177e4
LT		 1884 netif_start_queue(dev);
1885}
1886
1887static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
1888{
1889 struct rtl8169_private *tp = netdev_priv(dev);
1890 int ret = 0;
1891
1892 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
1893 return -EINVAL;
1894
1895 dev->mtu = new_mtu;
1896
1897 if (!netif_running(dev))
1898 goto out;
1899
1900 rtl8169_down(dev);
1901
1902 rtl8169_set_rxbufsize(tp, dev);
1903
1904 ret = rtl8169_init_ring(dev);
1905 if (ret < 0)
1906 goto out;
1907
1908 netif_poll_enable(dev);
1909
1910 rtl8169_hw_start(dev);
1911
1912 rtl8169_request_timer(dev);
1913
1914out:
1915 return ret;
1916}
1917
1918static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
1919{
1920 desc->addr = 0x0badbadbadbadbadull;
1921 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
1922}
1923
1924static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
1925 struct sk_buff **sk_buff, struct RxDesc *desc)
1926{
1927 struct pci_dev *pdev = tp->pci_dev;
1928
1929 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
1930 PCI_DMA_FROMDEVICE);
1931 dev_kfree_skb(*sk_buff);
1932 *sk_buff = NULL;
1933 rtl8169_make_unusable_by_asic(desc);
1934}
1935
1936static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
1937{
1938 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
1939
1940 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
1941}
1942
1943static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
1944 u32 rx_buf_sz)
1945{
1946 desc->addr = cpu_to_le64(mapping);
1947 wmb();
1948 rtl8169_mark_to_asic(desc, rx_buf_sz);
1949}
1950
1951static int rtl8169_alloc_rx_skb(struct pci_dev *pdev, struct sk_buff **sk_buff,
1952 struct RxDesc *desc, int rx_buf_sz)
1953{
1954 struct sk_buff *skb;
1955 dma_addr_t mapping;
1956 int ret = 0;
1957
1958 skb = dev_alloc_skb(rx_buf_sz + NET_IP_ALIGN);
1959 if (!skb)
1960 goto err_out;
1961
1962 skb_reserve(skb, NET_IP_ALIGN);
1963 *sk_buff = skb;
1964
689be439 1965 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
1da177e4
LT		 1966 PCI_DMA_FROMDEVICE);
1967
1968 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
1969
1970out:
1971 return ret;
1972
1973err_out:
1974 ret = -ENOMEM;
1975 rtl8169_make_unusable_by_asic(desc);
1976 goto out;
1977}
1978
1979static void rtl8169_rx_clear(struct rtl8169_private *tp)
1980{
1981 int i;
1982
1983 for (i = 0; i < NUM_RX_DESC; i++) {
1984 if (tp->Rx_skbuff[i]) {
1985 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
1986 tp->RxDescArray + i);
1987 }
1988 }
1989}
1990
1991static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
1992 u32 start, u32 end)
1993{
1994 u32 cur;
1995
1996 for (cur = start; end - cur > 0; cur++) {
1997 int ret, i = cur % NUM_RX_DESC;
1998
1999 if (tp->Rx_skbuff[i])
2000 continue;
2001
2002 ret = rtl8169_alloc_rx_skb(tp->pci_dev, tp->Rx_skbuff + i,
2003 tp->RxDescArray + i, tp->rx_buf_sz);
2004 if (ret < 0)
2005 break;
2006 }
2007 return cur - start;
2008}
2009
2010static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2011{
2012 desc->opts1 |= cpu_to_le32(RingEnd);
2013}
2014
2015static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2016{
2017 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2018}
2019
2020static int rtl8169_init_ring(struct net_device *dev)
2021{
2022 struct rtl8169_private *tp = netdev_priv(dev);
2023
2024 rtl8169_init_ring_indexes(tp);
2025
2026 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2027 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2028
2029 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2030 goto err_out;
2031
2032 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2033
2034 return 0;
2035
2036err_out:
2037 rtl8169_rx_clear(tp);
2038 return -ENOMEM;
2039}
2040
2041static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2042 struct TxDesc *desc)
2043{
2044 unsigned int len = tx_skb->len;
2045
2046 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2047 desc->opts1 = 0x00;
2048 desc->opts2 = 0x00;
2049 desc->addr = 0x00;
2050 tx_skb->len = 0;
2051}
2052
2053static void rtl8169_tx_clear(struct rtl8169_private *tp)
2054{
2055 unsigned int i;
2056
2057 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2058 unsigned int entry = i % NUM_TX_DESC;
2059 struct ring_info *tx_skb = tp->tx_skb + entry;
2060 unsigned int len = tx_skb->len;
2061
2062 if (len) {
2063 struct sk_buff *skb = tx_skb->skb;
2064
2065 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2066 tp->TxDescArray + entry);
2067 if (skb) {
2068 dev_kfree_skb(skb);
2069 tx_skb->skb = NULL;
2070 }
2071 tp->stats.tx_dropped++;
2072 }
2073 }
2074 tp->cur_tx = tp->dirty_tx = 0;
2075}
2076
2077static void rtl8169_schedule_work(struct net_device *dev, void (*task)(void *))
2078{
2079 struct rtl8169_private *tp = netdev_priv(dev);
2080
2081 PREPARE_WORK(&tp->task, task, dev);
2082 schedule_delayed_work(&tp->task, 4);
2083}
2084
2085static void rtl8169_wait_for_quiescence(struct net_device *dev)
2086{
2087 struct rtl8169_private *tp = netdev_priv(dev);
2088 void __iomem *ioaddr = tp->mmio_addr;
2089
2090 synchronize_irq(dev->irq);
2091
2092 /* Wait for any pending NAPI task to complete */
2093 netif_poll_disable(dev);
2094
2095 rtl8169_irq_mask_and_ack(ioaddr);
2096
2097 netif_poll_enable(dev);
2098}
2099
2100static void rtl8169_reinit_task(void *_data)
2101{
2102 struct net_device *dev = _data;
2103 int ret;
2104
2105 if (netif_running(dev)) {
2106 rtl8169_wait_for_quiescence(dev);
2107 rtl8169_close(dev);
2108 }
2109
2110 ret = rtl8169_open(dev);
2111 if (unlikely(ret < 0)) {
2112 if (net_ratelimit()) {
b57b7e5a
SH		 2113 struct rtl8169_private *tp = netdev_priv(dev);
2114
2115 if (netif_msg_drv(tp)) {
2116 printk(PFX KERN_ERR
2117 "%s: reinit failure (status = %d)."
2118 " Rescheduling.\n", dev->name, ret);
2119 }
1da177e4
LT		 2120 }
2121 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2122 }
2123}
2124
2125static void rtl8169_reset_task(void *_data)
2126{
2127 struct net_device *dev = _data;
2128 struct rtl8169_private *tp = netdev_priv(dev);
2129
2130 if (!netif_running(dev))
2131 return;
2132
2133 rtl8169_wait_for_quiescence(dev);
2134
2135 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr);
2136 rtl8169_tx_clear(tp);
2137
2138 if (tp->dirty_rx == tp->cur_rx) {
2139 rtl8169_init_ring_indexes(tp);
2140 rtl8169_hw_start(dev);
2141 netif_wake_queue(dev);
2142 } else {
2143 if (net_ratelimit()) {
b57b7e5a
SH		 2144 struct rtl8169_private *tp = netdev_priv(dev);
2145
2146 if (netif_msg_intr(tp)) {
2147 printk(PFX KERN_EMERG
2148 "%s: Rx buffers shortage\n", dev->name);
2149 }
1da177e4
LT		 2150 }
2151 rtl8169_schedule_work(dev, rtl8169_reset_task);
2152 }
2153}
2154
2155static void rtl8169_tx_timeout(struct net_device *dev)
2156{
2157 struct rtl8169_private *tp = netdev_priv(dev);
2158
2159 rtl8169_hw_reset(tp->mmio_addr);
2160
2161 /* Let's wait a bit while any (async) irq lands on */
2162 rtl8169_schedule_work(dev, rtl8169_reset_task);
2163}
2164
2165static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2166 u32 opts1)
2167{
2168 struct skb_shared_info *info = skb_shinfo(skb);
2169 unsigned int cur_frag, entry;
2170 struct TxDesc *txd;
2171
2172 entry = tp->cur_tx;
2173 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2174 skb_frag_t *frag = info->frags + cur_frag;
2175 dma_addr_t mapping;
2176 u32 status, len;
2177 void *addr;
2178
2179 entry = (entry + 1) % NUM_TX_DESC;
2180
2181 txd = tp->TxDescArray + entry;
2182 len = frag->size;
2183 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2184 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2185
2186 /* anti gcc 2.95.3 bugware (sic) */
2187 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2188
2189 txd->opts1 = cpu_to_le32(status);
2190 txd->addr = cpu_to_le64(mapping);
2191
2192 tp->tx_skb[entry].len = len;
2193 }
2194
2195 if (cur_frag) {
2196 tp->tx_skb[entry].skb = skb;
2197 txd->opts1 |= cpu_to_le32(LastFrag);
2198 }
2199
2200 return cur_frag;
2201}
2202
2203static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2204{
2205 if (dev->features & NETIF_F_TSO) {
7967168c 2206 u32 mss = skb_shinfo(skb)->gso_size;
1da177e4
LT		 2207
2208 if (mss)
2209 return LargeSend | ((mss & MSSMask) << MSSShift);
2210 }
2211 if (skb->ip_summed == CHECKSUM_HW) {
2212 const struct iphdr *ip = skb->nh.iph;
2213
2214 if (ip->protocol == IPPROTO_TCP)
2215 return IPCS | TCPCS;
2216 else if (ip->protocol == IPPROTO_UDP)
2217 return IPCS | UDPCS;
2218 WARN_ON(1); /* we need a WARN() */
2219 }
2220 return 0;
2221}
2222
2223static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2224{
2225 struct rtl8169_private *tp = netdev_priv(dev);
2226 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2227 struct TxDesc *txd = tp->TxDescArray + entry;
2228 void __iomem *ioaddr = tp->mmio_addr;
2229 dma_addr_t mapping;
2230 u32 status, len;
2231 u32 opts1;
2232 int ret = 0;
2233
2234 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
b57b7e5a
SH		 2235 if (netif_msg_drv(tp)) {
2236 printk(KERN_ERR
2237 "%s: BUG! Tx Ring full when queue awake!\n",
2238 dev->name);
2239 }
1da177e4
LT		 2240 goto err_stop;
2241 }
2242
2243 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2244 goto err_stop;
2245
2246 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2247
2248 frags = rtl8169_xmit_frags(tp, skb, opts1);
2249 if (frags) {
2250 len = skb_headlen(skb);
2251 opts1 |= FirstFrag;
2252 } else {
2253 len = skb->len;
2254
2255 if (unlikely(len < ETH_ZLEN)) {
5b057c6b 2256 if (skb_padto(skb, ETH_ZLEN))
1da177e4
LT		 2257 goto err_update_stats;
2258 len = ETH_ZLEN;
2259 }
2260
2261 opts1 |= FirstFrag | LastFrag;
2262 tp->tx_skb[entry].skb = skb;
2263 }
2264
2265 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2266
2267 tp->tx_skb[entry].len = len;
2268 txd->addr = cpu_to_le64(mapping);
2269 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2270
2271 wmb();
2272
2273 /* anti gcc 2.95.3 bugware (sic) */
2274 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2275 txd->opts1 = cpu_to_le32(status);
2276
2277 dev->trans_start = jiffies;
2278
2279 tp->cur_tx += frags + 1;
2280
2281 smp_wmb();
2282
2283 RTL_W8(TxPoll, 0x40); /* set polling bit */
2284
2285 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2286 netif_stop_queue(dev);
2287 smp_rmb();
2288 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2289 netif_wake_queue(dev);
2290 }
2291
2292out:
2293 return ret;
2294
2295err_stop:
2296 netif_stop_queue(dev);
2297 ret = 1;
2298err_update_stats:
2299 tp->stats.tx_dropped++;
2300 goto out;
2301}
2302
2303static void rtl8169_pcierr_interrupt(struct net_device *dev)
2304{
2305 struct rtl8169_private *tp = netdev_priv(dev);
2306 struct pci_dev *pdev = tp->pci_dev;
2307 void __iomem *ioaddr = tp->mmio_addr;
2308 u16 pci_status, pci_cmd;
2309
2310 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2311 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2312
b57b7e5a
SH		 2313 if (netif_msg_intr(tp)) {
2314 printk(KERN_ERR
2315 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2316 dev->name, pci_cmd, pci_status);
2317 }
1da177e4
LT		 2318
2319 /*
2320 * The recovery sequence below admits a very elaborated explanation:
2321 * - it seems to work;
2322 * - I did not see what else could be done.
2323 *
2324 * Feel free to adjust to your needs.
2325 */
2326 pci_write_config_word(pdev, PCI_COMMAND,
2327 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
2328
2329 pci_write_config_word(pdev, PCI_STATUS,
2330 pci_status & (PCI_STATUS_DETECTED_PARITY |
2331 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2332 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2333
2334 /* The infamous DAC f*ckup only happens at boot time */
2335 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
b57b7e5a
SH		 2336 if (netif_msg_intr(tp))
2337 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
1da177e4
LT		 2338 tp->cp_cmd &= ~PCIDAC;
2339 RTL_W16(CPlusCmd, tp->cp_cmd);
2340 dev->features &= ~NETIF_F_HIGHDMA;
2341 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2342 }
2343
2344 rtl8169_hw_reset(ioaddr);
2345}
2346
2347static void
2348rtl8169_tx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
2349 void __iomem *ioaddr)
2350{
2351 unsigned int dirty_tx, tx_left;
2352
2353 assert(dev != NULL);
2354 assert(tp != NULL);
2355 assert(ioaddr != NULL);
2356
2357 dirty_tx = tp->dirty_tx;
2358 smp_rmb();
2359 tx_left = tp->cur_tx - dirty_tx;
2360
2361 while (tx_left > 0) {
2362 unsigned int entry = dirty_tx % NUM_TX_DESC;
2363 struct ring_info *tx_skb = tp->tx_skb + entry;
2364 u32 len = tx_skb->len;
2365 u32 status;
2366
2367 rmb();
2368 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2369 if (status & DescOwn)
2370 break;
2371
2372 tp->stats.tx_bytes += len;
2373 tp->stats.tx_packets++;
2374
2375 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2376
2377 if (status & LastFrag) {
2378 dev_kfree_skb_irq(tx_skb->skb);
2379 tx_skb->skb = NULL;
2380 }
2381 dirty_tx++;
2382 tx_left--;
2383 }
2384
2385 if (tp->dirty_tx != dirty_tx) {
2386 tp->dirty_tx = dirty_tx;
2387 smp_wmb();
2388 if (netif_queue_stopped(dev) &&
2389 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2390 netif_wake_queue(dev);
2391 }
2392 }
2393}
2394
126fa4b9
FR		 2395static inline int rtl8169_fragmented_frame(u32 status)
2396{
2397 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2398}
2399
1da177e4
LT		 2400static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2401{
2402 u32 opts1 = le32_to_cpu(desc->opts1);
2403 u32 status = opts1 & RxProtoMask;
2404
2405 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2406 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2407 ((status == RxProtoIP) && !(opts1 & IPFail)))
2408 skb->ip_summed = CHECKSUM_UNNECESSARY;
2409 else
2410 skb->ip_summed = CHECKSUM_NONE;
2411}
2412
2413static inline int rtl8169_try_rx_copy(struct sk_buff **sk_buff, int pkt_size,
2414 struct RxDesc *desc, int rx_buf_sz)
2415{
2416 int ret = -1;
2417
2418 if (pkt_size < rx_copybreak) {
2419 struct sk_buff *skb;
2420
2421 skb = dev_alloc_skb(pkt_size + NET_IP_ALIGN);
2422 if (skb) {
2423 skb_reserve(skb, NET_IP_ALIGN);
689be439 2424 eth_copy_and_sum(skb, sk_buff[0]->data, pkt_size, 0);
1da177e4
LT		 2425 *sk_buff = skb;
2426 rtl8169_mark_to_asic(desc, rx_buf_sz);
2427 ret = 0;
2428 }
2429 }
2430 return ret;
2431}
2432
2433static int
2434rtl8169_rx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
2435 void __iomem *ioaddr)
2436{
2437 unsigned int cur_rx, rx_left;
2438 unsigned int delta, count;
2439
2440 assert(dev != NULL);
2441 assert(tp != NULL);
2442 assert(ioaddr != NULL);
2443
2444 cur_rx = tp->cur_rx;
2445 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
2446 rx_left = rtl8169_rx_quota(rx_left, (u32) dev->quota);
2447
4dcb7d33 2448 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 2449 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 2450 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 2451 u32 status;
2452
2453 rmb();
126fa4b9 2454 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 2455
2456 if (status & DescOwn)
2457 break;
4dcb7d33 2458 if (unlikely(status & RxRES)) {
b57b7e5a
SH		 2459 if (netif_msg_rx_err(tp)) {
2460 printk(KERN_INFO
2461 "%s: Rx ERROR. status = %08x\n",
2462 dev->name, status);
2463 }
1da177e4
LT		 2464 tp->stats.rx_errors++;
2465 if (status & (RxRWT | RxRUNT))
2466 tp->stats.rx_length_errors++;
2467 if (status & RxCRC)
2468 tp->stats.rx_crc_errors++;
9dccf611
FR		 2469 if (status & RxFOVF) {
2470 rtl8169_schedule_work(dev, rtl8169_reset_task);
2471 tp->stats.rx_fifo_errors++;
2472 }
126fa4b9 2473 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
1da177e4 2474 } else {
1da177e4
LT		 2475 struct sk_buff *skb = tp->Rx_skbuff[entry];
2476 int pkt_size = (status & 0x00001FFF) - 4;
2477 void (*pci_action)(struct pci_dev *, dma_addr_t,
2478 size_t, int) = pci_dma_sync_single_for_device;
2479
126fa4b9
FR		 2480 /*
2481 * The driver does not support incoming fragmented
2482 * frames. They are seen as a symptom of over-mtu
2483 * sized frames.
2484 */
2485 if (unlikely(rtl8169_fragmented_frame(status))) {
2486 tp->stats.rx_dropped++;
2487 tp->stats.rx_length_errors++;
2488 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4dcb7d33 2489 continue;
126fa4b9
FR		 2490 }
2491
1da177e4
LT		 2492 rtl8169_rx_csum(skb, desc);
2493
2494 pci_dma_sync_single_for_cpu(tp->pci_dev,
2495 le64_to_cpu(desc->addr), tp->rx_buf_sz,
2496 PCI_DMA_FROMDEVICE);
2497
2498 if (rtl8169_try_rx_copy(&skb, pkt_size, desc,
2499 tp->rx_buf_sz)) {
2500 pci_action = pci_unmap_single;
2501 tp->Rx_skbuff[entry] = NULL;
2502 }
2503
2504 pci_action(tp->pci_dev, le64_to_cpu(desc->addr),
2505 tp->rx_buf_sz, PCI_DMA_FROMDEVICE);
2506
2507 skb->dev = dev;
2508 skb_put(skb, pkt_size);
2509 skb->protocol = eth_type_trans(skb, dev);
2510
2511 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
2512 rtl8169_rx_skb(skb);
2513
2514 dev->last_rx = jiffies;
2515 tp->stats.rx_bytes += pkt_size;
2516 tp->stats.rx_packets++;
2517 }
1da177e4
LT		 2518 }
2519
2520 count = cur_rx - tp->cur_rx;
2521 tp->cur_rx = cur_rx;
2522
2523 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
b57b7e5a 2524 if (!delta && count && netif_msg_intr(tp))
1da177e4
LT		 2525 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
2526 tp->dirty_rx += delta;
2527
2528 /*
2529 * FIXME: until there is periodic timer to try and refill the ring,
2530 * a temporary shortage may definitely kill the Rx process.
2531 * - disable the asic to try and avoid an overflow and kick it again
2532 * after refill ?
2533 * - how do others driver handle this condition (Uh oh...).
2534 */
b57b7e5a 2535 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
1da177e4
LT		 2536 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
2537
2538 return count;
2539}
2540
2541/* The interrupt handler does all of the Rx thread work and cleans up after the Tx thread. */
2542static irqreturn_t
2543rtl8169_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
2544{
2545 struct net_device *dev = (struct net_device *) dev_instance;
2546 struct rtl8169_private *tp = netdev_priv(dev);
2547 int boguscnt = max_interrupt_work;
2548 void __iomem *ioaddr = tp->mmio_addr;
2549 int status;
2550 int handled = 0;
2551
2552 do {
2553 status = RTL_R16(IntrStatus);
2554
2555 /* hotplug/major error/no more work/shared irq */
2556 if ((status == 0xFFFF) || !status)
2557 break;
2558
2559 handled = 1;
2560
2561 if (unlikely(!netif_running(dev))) {
2562 rtl8169_asic_down(ioaddr);
2563 goto out;
2564 }
2565
2566 status &= tp->intr_mask;
2567 RTL_W16(IntrStatus,
2568 (status & RxFIFOOver) ? (status | RxOverflow) : status);
2569
2570 if (!(status & rtl8169_intr_mask))
2571 break;
2572
2573 if (unlikely(status & SYSErr)) {
2574 rtl8169_pcierr_interrupt(dev);
2575 break;
2576 }
2577
2578 if (status & LinkChg)
2579 rtl8169_check_link_status(dev, tp, ioaddr);
2580
2581#ifdef CONFIG_R8169_NAPI
2582 RTL_W16(IntrMask, rtl8169_intr_mask & ~rtl8169_napi_event);
2583 tp->intr_mask = ~rtl8169_napi_event;
2584
2585 if (likely(netif_rx_schedule_prep(dev)))
2586 __netif_rx_schedule(dev);
b57b7e5a 2587 else if (netif_msg_intr(tp)) {
1da177e4
LT		 2588 printk(KERN_INFO "%s: interrupt %04x taken in poll\n",
2589 dev->name, status);
2590 }
2591 break;
2592#else
2593 /* Rx interrupt */
2594 if (status & (RxOK | RxOverflow | RxFIFOOver)) {
2595 rtl8169_rx_interrupt(dev, tp, ioaddr);
2596 }
2597 /* Tx interrupt */
2598 if (status & (TxOK | TxErr))
2599 rtl8169_tx_interrupt(dev, tp, ioaddr);
2600#endif
2601
2602 boguscnt--;
2603 } while (boguscnt > 0);
2604
2605 if (boguscnt <= 0) {
7c8b2eb4 2606 if (netif_msg_intr(tp) && net_ratelimit() ) {
b57b7e5a
SH		 2607 printk(KERN_WARNING
2608 "%s: Too much work at interrupt!\n", dev->name);
2609 }
1da177e4
LT		 2610 /* Clear all interrupt sources. */
2611 RTL_W16(IntrStatus, 0xffff);
2612 }
2613out:
2614 return IRQ_RETVAL(handled);
2615}
2616
2617#ifdef CONFIG_R8169_NAPI
2618static int rtl8169_poll(struct net_device *dev, int *budget)
2619{
2620 unsigned int work_done, work_to_do = min(*budget, dev->quota);
2621 struct rtl8169_private *tp = netdev_priv(dev);
2622 void __iomem *ioaddr = tp->mmio_addr;
2623
2624 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr);
2625 rtl8169_tx_interrupt(dev, tp, ioaddr);
2626
2627 *budget -= work_done;
2628 dev->quota -= work_done;
2629
2630 if (work_done < work_to_do) {
2631 netif_rx_complete(dev);
2632 tp->intr_mask = 0xffff;
2633 /*
2634 * 20040426: the barrier is not strictly required but the
2635 * behavior of the irq handler could be less predictable
2636 * without it. Btw, the lack of flush for the posted pci
2637 * write is safe - FR
2638 */
2639 smp_wmb();
2640 RTL_W16(IntrMask, rtl8169_intr_mask);
2641 }
2642
2643 return (work_done >= work_to_do);
2644}
2645#endif
2646
2647static void rtl8169_down(struct net_device *dev)
2648{
2649 struct rtl8169_private *tp = netdev_priv(dev);
2650 void __iomem *ioaddr = tp->mmio_addr;
2651 unsigned int poll_locked = 0;
2652
2653 rtl8169_delete_timer(dev);
2654
2655 netif_stop_queue(dev);
2656
2657 flush_scheduled_work();
2658
2659core_down:
2660 spin_lock_irq(&tp->lock);
2661
2662 rtl8169_asic_down(ioaddr);
2663
2664 /* Update the error counts. */
2665 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2666 RTL_W32(RxMissed, 0);
2667
2668 spin_unlock_irq(&tp->lock);
2669
2670 synchronize_irq(dev->irq);
2671
2672 if (!poll_locked) {
2673 netif_poll_disable(dev);
2674 poll_locked++;
2675 }
2676
2677 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 2678 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4
LT		 2679
2680 /*
2681 * And now for the 50k$ question: are IRQ disabled or not ?
2682 *
2683 * Two paths lead here:
2684 * 1) dev->close
2685 * -> netif_running() is available to sync the current code and the
2686 * IRQ handler. See rtl8169_interrupt for details.
2687 * 2) dev->change_mtu
2688 * -> rtl8169_poll can not be issued again and re-enable the
2689 * interruptions. Let's simply issue the IRQ down sequence again.
2690 */
2691 if (RTL_R16(IntrMask))
2692 goto core_down;
2693
2694 rtl8169_tx_clear(tp);
2695
2696 rtl8169_rx_clear(tp);
2697}
2698
2699static int rtl8169_close(struct net_device *dev)
2700{
2701 struct rtl8169_private *tp = netdev_priv(dev);
2702 struct pci_dev *pdev = tp->pci_dev;
2703
2704 rtl8169_down(dev);
2705
2706 free_irq(dev->irq, dev);
2707
2708 netif_poll_enable(dev);
2709
2710 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2711 tp->RxPhyAddr);
2712 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2713 tp->TxPhyAddr);
2714 tp->TxDescArray = NULL;
2715 tp->RxDescArray = NULL;
2716
2717 return 0;
2718}
2719
2720static void
2721rtl8169_set_rx_mode(struct net_device *dev)
2722{
2723 struct rtl8169_private *tp = netdev_priv(dev);
2724 void __iomem *ioaddr = tp->mmio_addr;
2725 unsigned long flags;
2726 u32 mc_filter[2]; /* Multicast hash filter */
2727 int i, rx_mode;
2728 u32 tmp = 0;
2729
2730 if (dev->flags & IFF_PROMISC) {
2731 /* Unconditionally log net taps. */
b57b7e5a
SH		 2732 if (netif_msg_link(tp)) {
2733 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2734 dev->name);
2735 }
1da177e4
LT		 2736 rx_mode =
2737 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2738 AcceptAllPhys;
2739 mc_filter[1] = mc_filter[0] = 0xffffffff;
2740 } else if ((dev->mc_count > multicast_filter_limit)
2741 || (dev->flags & IFF_ALLMULTI)) {
2742 /* Too many to filter perfectly -- accept all multicasts. */
2743 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2744 mc_filter[1] = mc_filter[0] = 0xffffffff;
2745 } else {
2746 struct dev_mc_list *mclist;
2747 rx_mode = AcceptBroadcast | AcceptMyPhys;
2748 mc_filter[1] = mc_filter[0] = 0;
2749 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2750 i++, mclist = mclist->next) {
2751 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2752 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2753 rx_mode |= AcceptMulticast;
2754 }
2755 }
2756
2757 spin_lock_irqsave(&tp->lock, flags);
2758
2759 tmp = rtl8169_rx_config | rx_mode |
2760 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2761
2762 RTL_W32(RxConfig, tmp);
2763 RTL_W32(MAR0 + 0, mc_filter[0]);
2764 RTL_W32(MAR0 + 4, mc_filter[1]);
2765
2766 spin_unlock_irqrestore(&tp->lock, flags);
2767}
2768
2769/**
2770 * rtl8169_get_stats - Get rtl8169 read/write statistics
2771 * @dev: The Ethernet Device to get statistics for
2772 *
2773 * Get TX/RX statistics for rtl8169
2774 */
2775static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
2776{
2777 struct rtl8169_private *tp = netdev_priv(dev);
2778 void __iomem *ioaddr = tp->mmio_addr;
2779 unsigned long flags;
2780
2781 if (netif_running(dev)) {
2782 spin_lock_irqsave(&tp->lock, flags);
2783 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2784 RTL_W32(RxMissed, 0);
2785 spin_unlock_irqrestore(&tp->lock, flags);
2786 }
2787
2788 return &tp->stats;
2789}
2790
5d06a99f
FR		 2791#ifdef CONFIG_PM
2792
2793static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
2794{
2795 struct net_device *dev = pci_get_drvdata(pdev);
2796 struct rtl8169_private *tp = netdev_priv(dev);
2797 void __iomem *ioaddr = tp->mmio_addr;
2798
2799 if (!netif_running(dev))
2800 goto out;
2801
2802 netif_device_detach(dev);
2803 netif_stop_queue(dev);
2804
2805 spin_lock_irq(&tp->lock);
2806
2807 rtl8169_asic_down(ioaddr);
2808
2809 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2810 RTL_W32(RxMissed, 0);
2811
2812 spin_unlock_irq(&tp->lock);
2813
2814 pci_save_state(pdev);
61a4dcc2 2815 pci_enable_wake(pdev, pci_choose_state(pdev, state), tp->wol_enabled);
5d06a99f
FR		 2816 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2817out:
2818 return 0;
2819}
2820
2821static int rtl8169_resume(struct pci_dev *pdev)
2822{
2823 struct net_device *dev = pci_get_drvdata(pdev);
2824
2825 if (!netif_running(dev))
2826 goto out;
2827
2828 netif_device_attach(dev);
2829
2830 pci_set_power_state(pdev, PCI_D0);
2831 pci_restore_state(pdev);
61a4dcc2 2832 pci_enable_wake(pdev, PCI_D0, 0);
5d06a99f
FR		 2833
2834 rtl8169_schedule_work(dev, rtl8169_reset_task);
2835out:
2836 return 0;
2837}
2838
2839#endif /* CONFIG_PM */
2840
1da177e4
LT		 2841static struct pci_driver rtl8169_pci_driver = {
2842 .name = MODULENAME,
2843 .id_table = rtl8169_pci_tbl,
2844 .probe = rtl8169_init_one,
2845 .remove = __devexit_p(rtl8169_remove_one),
2846#ifdef CONFIG_PM
2847 .suspend = rtl8169_suspend,
2848 .resume = rtl8169_resume,
2849#endif
2850};
2851
2852static int __init
2853rtl8169_init_module(void)
2854{
2855 return pci_module_init(&rtl8169_pci_driver);
2856}
2857
2858static void __exit
2859rtl8169_cleanup_module(void)
2860{
2861 pci_unregister_driver(&rtl8169_pci_driver);
2862}
2863
2864module_init(rtl8169_init_module);
2865module_exit(rtl8169_cleanup_module);
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