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r8169: use hardware auto-padding.
[linux-2.6-block.git] / drivers / net / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
25#include <linux/dma-mapping.h>
26
99f252b0 27#include <asm/system.h>
1da177e4
LT		 28#include <asm/io.h>
29#include <asm/irq.h>
30
865c652d 31#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 32#define MODULENAME "r8169"
33#define PFX MODULENAME ": "
34
35#ifdef RTL8169_DEBUG
36#define assert(expr) \
5b0384f4
FR		 37 if (!(expr)) { \
38 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 39 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 40 }
06fa7358
JP		 41#define dprintk(fmt, args...) \
42 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 43#else
44#define assert(expr) do {} while (0)
45#define dprintk(fmt, args...) do {} while (0)
46#endif /* RTL8169_DEBUG */
47
b57b7e5a 48#define R8169_MSG_DEFAULT \
f0e837d9 49 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 50
1da177e4
LT		 51#define TX_BUFFS_AVAIL(tp) \
52 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
53
1da177e4 54/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
f71e1309 55static const int max_interrupt_work = 20;
1da177e4
LT		 56
57/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
58 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 59static const int multicast_filter_limit = 32;
1da177e4
LT		 60
61/* MAC address length */
62#define MAC_ADDR_LEN 6
63
9c14ceaf 64#define MAX_READ_REQUEST_SHIFT 12
1da177e4
LT		 65#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
66#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
67#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
07d3f51f 68#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
1da177e4
LT		 69#define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
70#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
71#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
72
73#define R8169_REGS_SIZE 256
74#define R8169_NAPI_WEIGHT 64
75#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
76#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
77#define RX_BUF_SIZE 1536 /* Rx Buffer size */
78#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
79#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
80
81#define RTL8169_TX_TIMEOUT (6*HZ)
82#define RTL8169_PHY_TIMEOUT (10*HZ)
83
6709fe9a 84#define RTL_EEPROM_SIG 0x8129
e1564ec9 85#define RTL_EEPROM_SIG_ADDR 0x0000
6709fe9a 86#define RTL_EEPROM_MAC_ADDR 0x0007
e1564ec9 87
1da177e4
LT		 88/* write/read MMIO register */
89#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
90#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
91#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
92#define RTL_R8(reg) readb (ioaddr + (reg))
93#define RTL_R16(reg) readw (ioaddr + (reg))
94#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
95
96enum mac_version {
ba6eb6ee
FR		 97 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
98 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
99 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
100 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
101 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
6dccd16b 102 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
2857ffb7
FR		 103 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
104 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
105 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
106 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
2dd99530 107 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
e3cf0cc0
FR		 108 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
109 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
110 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
111 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
112 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
113 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
114 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
115 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
197ff761 116 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
6fb07058 117 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
ef3386f0 118 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
7f3e3d3a 119 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
5b538df9
FR		 120 RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
121 RTL_GIGA_MAC_VER_25 = 0x19 // 8168D
1da177e4
LT		 122};
123
1da177e4
LT		 124#define _R(NAME,MAC,MASK) \
125 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
126
3c6bee1d 127static const struct {
1da177e4
LT		 128 const char *name;
129 u8 mac_version;
130 u32 RxConfigMask; /* Clears the bits supported by this chip */
131} rtl_chip_info[] = {
ba6eb6ee
FR		 132 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
133 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
134 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
135 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
136 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
6dccd16b 137 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
2857ffb7
FR		 138 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
139 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
140 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
141 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
bcf0bf90
FR		 142 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
143 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
144 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
145 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
e3cf0cc0
FR		 146 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
147 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
148 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
149 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
150 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
197ff761 151 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
6fb07058 152 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
ef3386f0 153 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
7f3e3d3a 154 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
5b538df9
FR		 155 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
156 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880) // PCI-E
1da177e4
LT		 157};
158#undef _R
159
bcf0bf90
FR		 160enum cfg_version {
161 RTL_CFG_0 = 0x00,
162 RTL_CFG_1,
163 RTL_CFG_2
164};
165
07ce4064
FR		 166static void rtl_hw_start_8169(struct net_device *);
167static void rtl_hw_start_8168(struct net_device *);
168static void rtl_hw_start_8101(struct net_device *);
169
1da177e4 170static struct pci_device_id rtl8169_pci_tbl[] = {
bcf0bf90 171 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 172 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 173 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 174 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 175 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
176 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
bc1660b5 177 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 178 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
179 { PCI_VENDOR_ID_LINKSYS, 0x1032,
180 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 181 { 0x0001, 0x8168,
182 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 183 {0,},
184};
185
186MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
187
188static int rx_copybreak = 200;
189static int use_dac;
b57b7e5a
SH		 190static struct {
191 u32 msg_enable;
192} debug = { -1 };
1da177e4 193
07d3f51f
FR		 194enum rtl_registers {
195 MAC0 = 0, /* Ethernet hardware address. */
773d2021 196 MAC4 = 4,
07d3f51f
FR		 197 MAR0 = 8, /* Multicast filter. */
198 CounterAddrLow = 0x10,
199 CounterAddrHigh = 0x14,
200 TxDescStartAddrLow = 0x20,
201 TxDescStartAddrHigh = 0x24,
202 TxHDescStartAddrLow = 0x28,
203 TxHDescStartAddrHigh = 0x2c,
204 FLASH = 0x30,
205 ERSR = 0x36,
206 ChipCmd = 0x37,
207 TxPoll = 0x38,
208 IntrMask = 0x3c,
209 IntrStatus = 0x3e,
210 TxConfig = 0x40,
211 RxConfig = 0x44,
212 RxMissed = 0x4c,
213 Cfg9346 = 0x50,
214 Config0 = 0x51,
215 Config1 = 0x52,
216 Config2 = 0x53,
217 Config3 = 0x54,
218 Config4 = 0x55,
219 Config5 = 0x56,
220 MultiIntr = 0x5c,
221 PHYAR = 0x60,
07d3f51f
FR		 222 PHYstatus = 0x6c,
223 RxMaxSize = 0xda,
224 CPlusCmd = 0xe0,
225 IntrMitigate = 0xe2,
226 RxDescAddrLow = 0xe4,
227 RxDescAddrHigh = 0xe8,
228 EarlyTxThres = 0xec,
229 FuncEvent = 0xf0,
230 FuncEventMask = 0xf4,
231 FuncPresetState = 0xf8,
232 FuncForceEvent = 0xfc,
1da177e4
LT		 233};
234
f162a5d1
FR		 235enum rtl8110_registers {
236 TBICSR = 0x64,
237 TBI_ANAR = 0x68,
238 TBI_LPAR = 0x6a,
239};
240
241enum rtl8168_8101_registers {
242 CSIDR = 0x64,
243 CSIAR = 0x68,
244#define CSIAR_FLAG 0x80000000
245#define CSIAR_WRITE_CMD 0x80000000
246#define CSIAR_BYTE_ENABLE 0x0f
247#define CSIAR_BYTE_ENABLE_SHIFT 12
248#define CSIAR_ADDR_MASK 0x0fff
249
250 EPHYAR = 0x80,
251#define EPHYAR_FLAG 0x80000000
252#define EPHYAR_WRITE_CMD 0x80000000
253#define EPHYAR_REG_MASK 0x1f
254#define EPHYAR_REG_SHIFT 16
255#define EPHYAR_DATA_MASK 0xffff
256 DBG_REG = 0xd1,
257#define FIX_NAK_1 (1 << 4)
258#define FIX_NAK_2 (1 << 3)
259};
260
07d3f51f 261enum rtl_register_content {
1da177e4 262 /* InterruptStatusBits */
07d3f51f
FR		 263 SYSErr = 0x8000,
264 PCSTimeout = 0x4000,
265 SWInt = 0x0100,
266 TxDescUnavail = 0x0080,
267 RxFIFOOver = 0x0040,
268 LinkChg = 0x0020,
269 RxOverflow = 0x0010,
270 TxErr = 0x0008,
271 TxOK = 0x0004,
272 RxErr = 0x0002,
273 RxOK = 0x0001,
1da177e4
LT		 274
275 /* RxStatusDesc */
9dccf611
FR		 276 RxFOVF = (1 << 23),
277 RxRWT = (1 << 22),
278 RxRES = (1 << 21),
279 RxRUNT = (1 << 20),
280 RxCRC = (1 << 19),
1da177e4
LT		 281
282 /* ChipCmdBits */
07d3f51f
FR		 283 CmdReset = 0x10,
284 CmdRxEnb = 0x08,
285 CmdTxEnb = 0x04,
286 RxBufEmpty = 0x01,
1da177e4 287
275391a4
FR		 288 /* TXPoll register p.5 */
289 HPQ = 0x80, /* Poll cmd on the high prio queue */
290 NPQ = 0x40, /* Poll cmd on the low prio queue */
291 FSWInt = 0x01, /* Forced software interrupt */
292
1da177e4 293 /* Cfg9346Bits */
07d3f51f
FR		 294 Cfg9346_Lock = 0x00,
295 Cfg9346_Unlock = 0xc0,
6709fe9a
IV		 296 Cfg9346_Program = 0x80, /* Programming mode */
297 Cfg9346_EECS = 0x08, /* Chip select */
298 Cfg9346_EESK = 0x04, /* Serial data clock */
299 Cfg9346_EEDI = 0x02, /* Data input */
300 Cfg9346_EEDO = 0x01, /* Data output */
1da177e4
LT		 301
302 /* rx_mode_bits */
07d3f51f
FR		 303 AcceptErr = 0x20,
304 AcceptRunt = 0x10,
305 AcceptBroadcast = 0x08,
306 AcceptMulticast = 0x04,
307 AcceptMyPhys = 0x02,
308 AcceptAllPhys = 0x01,
1da177e4
LT		 309
310 /* RxConfigBits */
07d3f51f
FR		 311 RxCfgFIFOShift = 13,
312 RxCfgDMAShift = 8,
6709fe9a 313 RxCfg9356SEL = 6, /* EEPROM type: 0 = 9346, 1 = 9356 */
1da177e4
LT		 314
315 /* TxConfigBits */
316 TxInterFrameGapShift = 24,
317 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
318
5d06a99f 319 /* Config1 register p.24 */
f162a5d1
FR		 320 LEDS1 = (1 << 7),
321 LEDS0 = (1 << 6),
fbac58fc 322 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
f162a5d1
FR		 323 Speed_down = (1 << 4),
324 MEMMAP = (1 << 3),
325 IOMAP = (1 << 2),
326 VPD = (1 << 1),
5d06a99f
FR		 327 PMEnable = (1 << 0), /* Power Management Enable */
328
6dccd16b
FR		 329 /* Config2 register p. 25 */
330 PCI_Clock_66MHz = 0x01,
331 PCI_Clock_33MHz = 0x00,
332
61a4dcc2
FR		 333 /* Config3 register p.25 */
334 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
335 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
f162a5d1 336 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 337
5d06a99f 338 /* Config5 register p.27 */
61a4dcc2
FR		 339 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
340 MWF = (1 << 5), /* Accept Multicast wakeup frame */
341 UWF = (1 << 4), /* Accept Unicast wakeup frame */
342 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 343 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
344
1da177e4
LT		 345 /* TBICSR p.28 */
346 TBIReset = 0x80000000,
347 TBILoopback = 0x40000000,
348 TBINwEnable = 0x20000000,
349 TBINwRestart = 0x10000000,
350 TBILinkOk = 0x02000000,
351 TBINwComplete = 0x01000000,
352
353 /* CPlusCmd p.31 */
f162a5d1
FR		 354 EnableBist = (1 << 15), // 8168 8101
355 Mac_dbgo_oe = (1 << 14), // 8168 8101
356 Normal_mode = (1 << 13), // unused
357 Force_half_dup = (1 << 12), // 8168 8101
358 Force_rxflow_en = (1 << 11), // 8168 8101
359 Force_txflow_en = (1 << 10), // 8168 8101
360 Cxpl_dbg_sel = (1 << 9), // 8168 8101
361 ASF = (1 << 8), // 8168 8101
362 PktCntrDisable = (1 << 7), // 8168 8101
363 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 364 RxVlan = (1 << 6),
365 RxChkSum = (1 << 5),
366 PCIDAC = (1 << 4),
367 PCIMulRW = (1 << 3),
0e485150
FR		 368 INTT_0 = 0x0000, // 8168
369 INTT_1 = 0x0001, // 8168
370 INTT_2 = 0x0002, // 8168
371 INTT_3 = 0x0003, // 8168
1da177e4
LT		 372
373 /* rtl8169_PHYstatus */
07d3f51f
FR		 374 TBI_Enable = 0x80,
375 TxFlowCtrl = 0x40,
376 RxFlowCtrl = 0x20,
377 _1000bpsF = 0x10,
378 _100bps = 0x08,
379 _10bps = 0x04,
380 LinkStatus = 0x02,
381 FullDup = 0x01,
1da177e4 382
1da177e4 383 /* _TBICSRBit */
07d3f51f 384 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 385
386 /* DumpCounterCommand */
07d3f51f 387 CounterDump = 0x8,
1da177e4
LT		 388};
389
07d3f51f 390enum desc_status_bit {
1da177e4
LT		 391 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
392 RingEnd = (1 << 30), /* End of descriptor ring */
393 FirstFrag = (1 << 29), /* First segment of a packet */
394 LastFrag = (1 << 28), /* Final segment of a packet */
395
396 /* Tx private */
397 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
398 MSSShift = 16, /* MSS value position */
399 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
400 IPCS = (1 << 18), /* Calculate IP checksum */
401 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
402 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
403 TxVlanTag = (1 << 17), /* Add VLAN tag */
404
405 /* Rx private */
406 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
407 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
408
409#define RxProtoUDP (PID1)
410#define RxProtoTCP (PID0)
411#define RxProtoIP (PID1 | PID0)
412#define RxProtoMask RxProtoIP
413
414 IPFail = (1 << 16), /* IP checksum failed */
415 UDPFail = (1 << 15), /* UDP/IP checksum failed */
416 TCPFail = (1 << 14), /* TCP/IP checksum failed */
417 RxVlanTag = (1 << 16), /* VLAN tag available */
418};
419
420#define RsvdMask 0x3fffc000
421
422struct TxDesc {
6cccd6e7
REB		 423 __le32 opts1;
424 __le32 opts2;
425 __le64 addr;
1da177e4
LT		 426};
427
428struct RxDesc {
6cccd6e7
REB		 429 __le32 opts1;
430 __le32 opts2;
431 __le64 addr;
1da177e4
LT		 432};
433
434struct ring_info {
435 struct sk_buff *skb;
436 u32 len;
437 u8 __pad[sizeof(void *) - sizeof(u32)];
438};
439
f23e7fda 440enum features {
ccdffb9a
FR		 441 RTL_FEATURE_WOL = (1 << 0),
442 RTL_FEATURE_MSI = (1 << 1),
443 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 444};
445
355423d0
IV		 446struct rtl8169_counters {
447 __le64 tx_packets;
448 __le64 rx_packets;
449 __le64 tx_errors;
450 __le32 rx_errors;
451 __le16 rx_missed;
452 __le16 align_errors;
453 __le32 tx_one_collision;
454 __le32 tx_multi_collision;
455 __le64 rx_unicast;
456 __le64 rx_broadcast;
457 __le32 rx_multicast;
458 __le16 tx_aborted;
459 __le16 tx_underun;
460};
461
1da177e4
LT		 462struct rtl8169_private {
463 void __iomem *mmio_addr; /* memory map physical address */
464 struct pci_dev *pci_dev; /* Index of PCI device */
c4028958 465 struct net_device *dev;
bea3348e 466 struct napi_struct napi;
1da177e4 467 spinlock_t lock; /* spin lock flag */
b57b7e5a 468 u32 msg_enable;
1da177e4
LT		 469 int chipset;
470 int mac_version;
1da177e4
LT		 471 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
472 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
473 u32 dirty_rx;
474 u32 dirty_tx;
475 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
476 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
477 dma_addr_t TxPhyAddr;
478 dma_addr_t RxPhyAddr;
479 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
480 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
bcf0bf90 481 unsigned align;
1da177e4
LT		 482 unsigned rx_buf_sz;
483 struct timer_list timer;
484 u16 cp_cmd;
0e485150
FR		 485 u16 intr_event;
486 u16 napi_event;
1da177e4
LT		 487 u16 intr_mask;
488 int phy_auto_nego_reg;
489 int phy_1000_ctrl_reg;
490#ifdef CONFIG_R8169_VLAN
491 struct vlan_group *vlgrp;
492#endif
493 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
ccdffb9a 494 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
1da177e4 495 void (*phy_reset_enable)(void __iomem *);
07ce4064 496 void (*hw_start)(struct net_device *);
1da177e4
LT		 497 unsigned int (*phy_reset_pending)(void __iomem *);
498 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 499 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
9c14ceaf 500 int pcie_cap;
c4028958 501 struct delayed_work task;
f23e7fda 502 unsigned features;
ccdffb9a
FR		 503
504 struct mii_if_info mii;
355423d0 505 struct rtl8169_counters counters;
1da177e4
LT		 506};
507
979b6c13 508MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 509MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 510module_param(rx_copybreak, int, 0);
1b7efd58 511MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
1da177e4
LT		 512module_param(use_dac, int, 0);
513MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 514module_param_named(debug, debug.msg_enable, int, 0);
515MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 516MODULE_LICENSE("GPL");
517MODULE_VERSION(RTL8169_VERSION);
518
519static int rtl8169_open(struct net_device *dev);
520static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
7d12e780 521static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 522static int rtl8169_init_ring(struct net_device *dev);
07ce4064 523static void rtl_hw_start(struct net_device *dev);
1da177e4 524static int rtl8169_close(struct net_device *dev);
07ce4064 525static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 526static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 527static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4 528static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
bea3348e 529 void __iomem *, u32 budget);
4dcb7d33 530static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 531static void rtl8169_down(struct net_device *dev);
99f252b0 532static void rtl8169_rx_clear(struct rtl8169_private *tp);
bea3348e 533static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4 534
1da177e4 535static const unsigned int rtl8169_rx_config =
5b0384f4 536 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4 537
07d3f51f 538static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 539{
540 int i;
541
a6baf3af 542 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
1da177e4 543
2371408c 544 for (i = 20; i > 0; i--) {
07d3f51f
FR		 545 /*
546 * Check if the RTL8169 has completed writing to the specified
547 * MII register.
548 */
5b0384f4 549 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 550 break;
2371408c 551 udelay(25);
1da177e4
LT		 552 }
553}
554
07d3f51f 555static int mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 556{
557 int i, value = -1;
558
a6baf3af 559 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
1da177e4 560
2371408c 561 for (i = 20; i > 0; i--) {
07d3f51f
FR		 562 /*
563 * Check if the RTL8169 has completed retrieving data from
564 * the specified MII register.
565 */
1da177e4 566 if (RTL_R32(PHYAR) & 0x80000000) {
a6baf3af 567 value = RTL_R32(PHYAR) & 0xffff;
1da177e4
LT		 568 break;
569 }
2371408c 570 udelay(25);
1da177e4
LT		 571 }
572 return value;
573}
574
dacf8154
FR		 575static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
576{
577 mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
578}
579
ccdffb9a
FR		 580static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
581 int val)
582{
583 struct rtl8169_private *tp = netdev_priv(dev);
584 void __iomem *ioaddr = tp->mmio_addr;
585
586 mdio_write(ioaddr, location, val);
587}
588
589static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
590{
591 struct rtl8169_private *tp = netdev_priv(dev);
592 void __iomem *ioaddr = tp->mmio_addr;
593
594 return mdio_read(ioaddr, location);
595}
596
dacf8154
FR		 597static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
598{
599 unsigned int i;
600
601 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
602 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
603
604 for (i = 0; i < 100; i++) {
605 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
606 break;
607 udelay(10);
608 }
609}
610
611static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
612{
613 u16 value = 0xffff;
614 unsigned int i;
615
616 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
617
618 for (i = 0; i < 100; i++) {
619 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
620 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
621 break;
622 }
623 udelay(10);
624 }
625
626 return value;
627}
628
629static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
630{
631 unsigned int i;
632
633 RTL_W32(CSIDR, value);
634 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
635 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
636
637 for (i = 0; i < 100; i++) {
638 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
639 break;
640 udelay(10);
641 }
642}
643
644static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
645{
646 u32 value = ~0x00;
647 unsigned int i;
648
649 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
650 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
651
652 for (i = 0; i < 100; i++) {
653 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
654 value = RTL_R32(CSIDR);
655 break;
656 }
657 udelay(10);
658 }
659
660 return value;
661}
662
1da177e4
LT		 663static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
664{
665 RTL_W16(IntrMask, 0x0000);
666
667 RTL_W16(IntrStatus, 0xffff);
668}
669
670static void rtl8169_asic_down(void __iomem *ioaddr)
671{
672 RTL_W8(ChipCmd, 0x00);
673 rtl8169_irq_mask_and_ack(ioaddr);
674 RTL_R16(CPlusCmd);
675}
676
677static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
678{
679 return RTL_R32(TBICSR) & TBIReset;
680}
681
682static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
683{
64e4bfb4 684 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 685}
686
687static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
688{
689 return RTL_R32(TBICSR) & TBILinkOk;
690}
691
692static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
693{
694 return RTL_R8(PHYstatus) & LinkStatus;
695}
696
697static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
698{
699 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
700}
701
702static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
703{
704 unsigned int val;
705
9e0db8ef
FR		 706 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
707 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
1da177e4
LT		 708}
709
710static void rtl8169_check_link_status(struct net_device *dev,
07d3f51f
FR		 711 struct rtl8169_private *tp,
712 void __iomem *ioaddr)
1da177e4
LT		 713{
714 unsigned long flags;
715
716 spin_lock_irqsave(&tp->lock, flags);
717 if (tp->link_ok(ioaddr)) {
718 netif_carrier_on(dev);
b57b7e5a
SH		 719 if (netif_msg_ifup(tp))
720 printk(KERN_INFO PFX "%s: link up\n", dev->name);
721 } else {
722 if (netif_msg_ifdown(tp))
723 printk(KERN_INFO PFX "%s: link down\n", dev->name);
1da177e4 724 netif_carrier_off(dev);
b57b7e5a 725 }
1da177e4
LT		 726 spin_unlock_irqrestore(&tp->lock, flags);
727}
728
61a4dcc2
FR		 729static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
730{
731 struct rtl8169_private *tp = netdev_priv(dev);
732 void __iomem *ioaddr = tp->mmio_addr;
733 u8 options;
734
735 wol->wolopts = 0;
736
737#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
738 wol->supported = WAKE_ANY;
739
740 spin_lock_irq(&tp->lock);
741
742 options = RTL_R8(Config1);
743 if (!(options & PMEnable))
744 goto out_unlock;
745
746 options = RTL_R8(Config3);
747 if (options & LinkUp)
748 wol->wolopts |= WAKE_PHY;
749 if (options & MagicPacket)
750 wol->wolopts |= WAKE_MAGIC;
751
752 options = RTL_R8(Config5);
753 if (options & UWF)
754 wol->wolopts |= WAKE_UCAST;
755 if (options & BWF)
5b0384f4 756 wol->wolopts |= WAKE_BCAST;
61a4dcc2 757 if (options & MWF)
5b0384f4 758 wol->wolopts |= WAKE_MCAST;
61a4dcc2
FR		 759
760out_unlock:
761 spin_unlock_irq(&tp->lock);
762}
763
764static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
765{
766 struct rtl8169_private *tp = netdev_priv(dev);
767 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 768 unsigned int i;
61a4dcc2
FR		 769 static struct {
770 u32 opt;
771 u16 reg;
772 u8 mask;
773 } cfg[] = {
774 { WAKE_ANY, Config1, PMEnable },
775 { WAKE_PHY, Config3, LinkUp },
776 { WAKE_MAGIC, Config3, MagicPacket },
777 { WAKE_UCAST, Config5, UWF },
778 { WAKE_BCAST, Config5, BWF },
779 { WAKE_MCAST, Config5, MWF },
780 { WAKE_ANY, Config5, LanWake }
781 };
782
783 spin_lock_irq(&tp->lock);
784
785 RTL_W8(Cfg9346, Cfg9346_Unlock);
786
787 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
788 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
789 if (wol->wolopts & cfg[i].opt)
790 options |= cfg[i].mask;
791 RTL_W8(cfg[i].reg, options);
792 }
793
794 RTL_W8(Cfg9346, Cfg9346_Lock);
795
f23e7fda
FR		 796 if (wol->wolopts)
797 tp->features |= RTL_FEATURE_WOL;
798 else
799 tp->features &= ~RTL_FEATURE_WOL;
8b76ab39 800 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
61a4dcc2
FR		 801
802 spin_unlock_irq(&tp->lock);
803
804 return 0;
805}
806
1da177e4
LT		 807static void rtl8169_get_drvinfo(struct net_device *dev,
808 struct ethtool_drvinfo *info)
809{
810 struct rtl8169_private *tp = netdev_priv(dev);
811
812 strcpy(info->driver, MODULENAME);
813 strcpy(info->version, RTL8169_VERSION);
814 strcpy(info->bus_info, pci_name(tp->pci_dev));
815}
816
817static int rtl8169_get_regs_len(struct net_device *dev)
818{
819 return R8169_REGS_SIZE;
820}
821
822static int rtl8169_set_speed_tbi(struct net_device *dev,
823 u8 autoneg, u16 speed, u8 duplex)
824{
825 struct rtl8169_private *tp = netdev_priv(dev);
826 void __iomem *ioaddr = tp->mmio_addr;
827 int ret = 0;
828 u32 reg;
829
830 reg = RTL_R32(TBICSR);
831 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
832 (duplex == DUPLEX_FULL)) {
833 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
834 } else if (autoneg == AUTONEG_ENABLE)
835 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
836 else {
b57b7e5a
SH		 837 if (netif_msg_link(tp)) {
838 printk(KERN_WARNING "%s: "
839 "incorrect speed setting refused in TBI mode\n",
840 dev->name);
841 }
1da177e4
LT		 842 ret = -EOPNOTSUPP;
843 }
844
845 return ret;
846}
847
848static int rtl8169_set_speed_xmii(struct net_device *dev,
849 u8 autoneg, u16 speed, u8 duplex)
850{
851 struct rtl8169_private *tp = netdev_priv(dev);
852 void __iomem *ioaddr = tp->mmio_addr;
853 int auto_nego, giga_ctrl;
854
64e4bfb4
FR		 855 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
856 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
857 ADVERTISE_100HALF | ADVERTISE_100FULL);
858 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
859 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 860
861 if (autoneg == AUTONEG_ENABLE) {
64e4bfb4
FR		 862 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
863 ADVERTISE_100HALF | ADVERTISE_100FULL);
864 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 865 } else {
866 if (speed == SPEED_10)
64e4bfb4 867 auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1da177e4 868 else if (speed == SPEED_100)
64e4bfb4 869 auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
1da177e4 870 else if (speed == SPEED_1000)
64e4bfb4 871 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 872
873 if (duplex == DUPLEX_HALF)
64e4bfb4 874 auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
726ecdcf
AG		 875
876 if (duplex == DUPLEX_FULL)
64e4bfb4 877 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
bcf0bf90
FR		 878
879 /* This tweak comes straight from Realtek's driver. */
880 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
e3cf0cc0
FR		 881 ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
882 (tp->mac_version == RTL_GIGA_MAC_VER_16))) {
64e4bfb4 883 auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
bcf0bf90
FR		 884 }
885 }
886
2857ffb7
FR		 887 /* The 8100e/8101e/8102e do Fast Ethernet only. */
888 if ((tp->mac_version == RTL_GIGA_MAC_VER_07) ||
889 (tp->mac_version == RTL_GIGA_MAC_VER_08) ||
890 (tp->mac_version == RTL_GIGA_MAC_VER_09) ||
891 (tp->mac_version == RTL_GIGA_MAC_VER_10) ||
892 (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
bcf0bf90 893 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
e3cf0cc0
FR		 894 (tp->mac_version == RTL_GIGA_MAC_VER_15) ||
895 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
64e4bfb4 896 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
bcf0bf90
FR		 897 netif_msg_link(tp)) {
898 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
899 dev->name);
900 }
64e4bfb4 901 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 902 }
903
623a1593
FR		 904 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
905
a2de6b89
FR		 906 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
907 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
908 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
909 /*
910 * Wake up the PHY.
911 * Vendor specific (0x1f) and reserved (0x0e) MII registers.
912 */
2584fbc3
RS		 913 mdio_write(ioaddr, 0x1f, 0x0000);
914 mdio_write(ioaddr, 0x0e, 0x0000);
915 }
916
1da177e4
LT		 917 tp->phy_auto_nego_reg = auto_nego;
918 tp->phy_1000_ctrl_reg = giga_ctrl;
919
64e4bfb4
FR		 920 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
921 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
922 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
1da177e4
LT		 923 return 0;
924}
925
926static int rtl8169_set_speed(struct net_device *dev,
927 u8 autoneg, u16 speed, u8 duplex)
928{
929 struct rtl8169_private *tp = netdev_priv(dev);
930 int ret;
931
932 ret = tp->set_speed(dev, autoneg, speed, duplex);
933
64e4bfb4 934 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 935 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
936
937 return ret;
938}
939
940static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
941{
942 struct rtl8169_private *tp = netdev_priv(dev);
943 unsigned long flags;
944 int ret;
945
946 spin_lock_irqsave(&tp->lock, flags);
947 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
948 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 949
1da177e4
LT		 950 return ret;
951}
952
953static u32 rtl8169_get_rx_csum(struct net_device *dev)
954{
955 struct rtl8169_private *tp = netdev_priv(dev);
956
957 return tp->cp_cmd & RxChkSum;
958}
959
960static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
961{
962 struct rtl8169_private *tp = netdev_priv(dev);
963 void __iomem *ioaddr = tp->mmio_addr;
964 unsigned long flags;
965
966 spin_lock_irqsave(&tp->lock, flags);
967
968 if (data)
969 tp->cp_cmd |= RxChkSum;
970 else
971 tp->cp_cmd &= ~RxChkSum;
972
973 RTL_W16(CPlusCmd, tp->cp_cmd);
974 RTL_R16(CPlusCmd);
975
976 spin_unlock_irqrestore(&tp->lock, flags);
977
978 return 0;
979}
980
981#ifdef CONFIG_R8169_VLAN
982
983static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
984 struct sk_buff *skb)
985{
986 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
987 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
988}
989
990static void rtl8169_vlan_rx_register(struct net_device *dev,
991 struct vlan_group *grp)
992{
993 struct rtl8169_private *tp = netdev_priv(dev);
994 void __iomem *ioaddr = tp->mmio_addr;
995 unsigned long flags;
996
997 spin_lock_irqsave(&tp->lock, flags);
998 tp->vlgrp = grp;
999 if (tp->vlgrp)
1000 tp->cp_cmd |= RxVlan;
1001 else
1002 tp->cp_cmd &= ~RxVlan;
1003 RTL_W16(CPlusCmd, tp->cp_cmd);
1004 RTL_R16(CPlusCmd);
1005 spin_unlock_irqrestore(&tp->lock, flags);
1006}
1007
1da177e4
LT		 1008static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1009 struct sk_buff *skb)
1010{
1011 u32 opts2 = le32_to_cpu(desc->opts2);
865c652d 1012 struct vlan_group *vlgrp = tp->vlgrp;
1da177e4
LT		 1013 int ret;
1014
865c652d
FR		 1015 if (vlgrp && (opts2 & RxVlanTag)) {
1016 vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff));
1da177e4
LT		 1017 ret = 0;
1018 } else
1019 ret = -1;
1020 desc->opts2 = 0;
1021 return ret;
1022}
1023
1024#else /* !CONFIG_R8169_VLAN */
1025
1026static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1027 struct sk_buff *skb)
1028{
1029 return 0;
1030}
1031
1032static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1033 struct sk_buff *skb)
1034{
1035 return -1;
1036}
1037
1038#endif
1039
ccdffb9a 1040static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1041{
1042 struct rtl8169_private *tp = netdev_priv(dev);
1043 void __iomem *ioaddr = tp->mmio_addr;
1044 u32 status;
1045
1046 cmd->supported =
1047 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1048 cmd->port = PORT_FIBRE;
1049 cmd->transceiver = XCVR_INTERNAL;
1050
1051 status = RTL_R32(TBICSR);
1052 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1053 cmd->autoneg = !!(status & TBINwEnable);
1054
1055 cmd->speed = SPEED_1000;
1056 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1057
1058 return 0;
1da177e4
LT		 1059}
1060
ccdffb9a 1061static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1062{
1063 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1064
1065 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1066}
1067
1068static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1069{
1070 struct rtl8169_private *tp = netdev_priv(dev);
1071 unsigned long flags;
ccdffb9a 1072 int rc;
1da177e4
LT		 1073
1074 spin_lock_irqsave(&tp->lock, flags);
1075
ccdffb9a 1076 rc = tp->get_settings(dev, cmd);
1da177e4
LT		 1077
1078 spin_unlock_irqrestore(&tp->lock, flags);
ccdffb9a 1079 return rc;
1da177e4
LT		 1080}
1081
1082static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1083 void *p)
1084{
5b0384f4
FR		 1085 struct rtl8169_private *tp = netdev_priv(dev);
1086 unsigned long flags;
1da177e4 1087
5b0384f4
FR		 1088 if (regs->len > R8169_REGS_SIZE)
1089 regs->len = R8169_REGS_SIZE;
1da177e4 1090
5b0384f4
FR		 1091 spin_lock_irqsave(&tp->lock, flags);
1092 memcpy_fromio(p, tp->mmio_addr, regs->len);
1093 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 1094}
1095
b57b7e5a
SH		 1096static u32 rtl8169_get_msglevel(struct net_device *dev)
1097{
1098 struct rtl8169_private *tp = netdev_priv(dev);
1099
1100 return tp->msg_enable;
1101}
1102
1103static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1104{
1105 struct rtl8169_private *tp = netdev_priv(dev);
1106
1107 tp->msg_enable = value;
1108}
1109
d4a3a0fc
SH		 1110static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1111 "tx_packets",
1112 "rx_packets",
1113 "tx_errors",
1114 "rx_errors",
1115 "rx_missed",
1116 "align_errors",
1117 "tx_single_collisions",
1118 "tx_multi_collisions",
1119 "unicast",
1120 "broadcast",
1121 "multicast",
1122 "tx_aborted",
1123 "tx_underrun",
1124};
1125
b9f2c044 1126static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1127{
b9f2c044
JG		 1128 switch (sset) {
1129 case ETH_SS_STATS:
1130 return ARRAY_SIZE(rtl8169_gstrings);
1131 default:
1132 return -EOPNOTSUPP;
1133 }
d4a3a0fc
SH		 1134}
1135
355423d0 1136static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1137{
1138 struct rtl8169_private *tp = netdev_priv(dev);
1139 void __iomem *ioaddr = tp->mmio_addr;
1140 struct rtl8169_counters *counters;
1141 dma_addr_t paddr;
1142 u32 cmd;
355423d0 1143 int wait = 1000;
d4a3a0fc 1144
355423d0
IV		 1145 /*
1146 * Some chips are unable to dump tally counters when the receiver
1147 * is disabled.
1148 */
1149 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1150 return;
d4a3a0fc
SH		 1151
1152 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1153 if (!counters)
1154 return;
1155
1156 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1157 cmd = (u64)paddr & DMA_32BIT_MASK;
1158 RTL_W32(CounterAddrLow, cmd);
1159 RTL_W32(CounterAddrLow, cmd | CounterDump);
1160
355423d0
IV		 1161 while (wait--) {
1162 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1163 /* copy updated counters */
1164 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc 1165 break;
355423d0
IV		 1166 }
1167 udelay(10);
d4a3a0fc
SH		 1168 }
1169
1170 RTL_W32(CounterAddrLow, 0);
1171 RTL_W32(CounterAddrHigh, 0);
1172
d4a3a0fc
SH		 1173 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1174}
1175
355423d0
IV		 1176static void rtl8169_get_ethtool_stats(struct net_device *dev,
1177 struct ethtool_stats *stats, u64 *data)
1178{
1179 struct rtl8169_private *tp = netdev_priv(dev);
1180
1181 ASSERT_RTNL();
1182
1183 rtl8169_update_counters(dev);
1184
1185 data[0] = le64_to_cpu(tp->counters.tx_packets);
1186 data[1] = le64_to_cpu(tp->counters.rx_packets);
1187 data[2] = le64_to_cpu(tp->counters.tx_errors);
1188 data[3] = le32_to_cpu(tp->counters.rx_errors);
1189 data[4] = le16_to_cpu(tp->counters.rx_missed);
1190 data[5] = le16_to_cpu(tp->counters.align_errors);
1191 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1192 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1193 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1194 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1195 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1196 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1197 data[12] = le16_to_cpu(tp->counters.tx_underun);
1198}
1199
d4a3a0fc
SH		 1200static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1201{
1202 switch(stringset) {
1203 case ETH_SS_STATS:
1204 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1205 break;
1206 }
1207}
1208
7282d491 1209static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1210 .get_drvinfo = rtl8169_get_drvinfo,
1211 .get_regs_len = rtl8169_get_regs_len,
1212 .get_link = ethtool_op_get_link,
1213 .get_settings = rtl8169_get_settings,
1214 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1215 .get_msglevel = rtl8169_get_msglevel,
1216 .set_msglevel = rtl8169_set_msglevel,
1da177e4
LT		 1217 .get_rx_csum = rtl8169_get_rx_csum,
1218 .set_rx_csum = rtl8169_set_rx_csum,
1da177e4 1219 .set_tx_csum = ethtool_op_set_tx_csum,
1da177e4 1220 .set_sg = ethtool_op_set_sg,
1da177e4
LT		 1221 .set_tso = ethtool_op_set_tso,
1222 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1223 .get_wol = rtl8169_get_wol,
1224 .set_wol = rtl8169_set_wol,
d4a3a0fc 1225 .get_strings = rtl8169_get_strings,
b9f2c044 1226 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1227 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1228};
1229
07d3f51f
FR		 1230static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1231 int bitnum, int bitval)
1da177e4
LT		 1232{
1233 int val;
1234
1235 val = mdio_read(ioaddr, reg);
1236 val = (bitval == 1) ?
1237 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
5b0384f4 1238 mdio_write(ioaddr, reg, val & 0xffff);
1da177e4
LT		 1239}
1240
07d3f51f
FR		 1241static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1242 void __iomem *ioaddr)
1da177e4 1243{
0e485150
FR		 1244 /*
1245 * The driver currently handles the 8168Bf and the 8168Be identically
1246 * but they can be identified more specifically through the test below
1247 * if needed:
1248 *
1249 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1250 *
1251 * Same thing for the 8101Eb and the 8101Ec:
1252 *
1253 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1254 */
1da177e4
LT		 1255 const struct {
1256 u32 mask;
e3cf0cc0 1257 u32 val;
1da177e4
LT		 1258 int mac_version;
1259 } mac_info[] = {
5b538df9
FR		 1260 /* 8168D family. */
1261 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_25 },
1262
ef808d50 1263 /* 8168C family. */
7f3e3d3a 1264 { 0x7cf00000, 0x3ca00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 1265 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 1266 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 1267 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 1268 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1269 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 1270 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 1271 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 1272 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 1273
1274 /* 8168B family. */
1275 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1276 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1277 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1278 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1279
1280 /* 8101 family. */
2857ffb7
FR		 1281 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1282 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1283 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1284 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1285 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1286 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 1287 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 1288 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 1289 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 1290 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1291 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 1292 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1293 /* FIXME: where did these entries come from ? -- FR */
1294 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1295 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1296
1297 /* 8110 family. */
1298 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1299 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1300 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1301 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1302 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1303 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1304
1305 { 0x00000000, 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
1da177e4
LT		 1306 }, *p = mac_info;
1307 u32 reg;
1308
e3cf0cc0
FR		 1309 reg = RTL_R32(TxConfig);
1310 while ((reg & p->mask) != p->val)
1da177e4
LT		 1311 p++;
1312 tp->mac_version = p->mac_version;
e3cf0cc0
FR		 1313
1314 if (p->mask == 0x00000000) {
1315 struct pci_dev *pdev = tp->pci_dev;
1316
1317 dev_info(&pdev->dev, "unknown MAC (%08x)\n", reg);
1318 }
1da177e4
LT		 1319}
1320
1321static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1322{
bcf0bf90 1323 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1324}
1325
867763c1
FR		 1326struct phy_reg {
1327 u16 reg;
1328 u16 val;
1329};
1330
1331static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len)
1332{
1333 while (len-- > 0) {
1334 mdio_write(ioaddr, regs->reg, regs->val);
1335 regs++;
1336 }
1337}
1338
5615d9f1 1339static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1da177e4 1340{
1da177e4
LT		 1341 struct {
1342 u16 regs[5]; /* Beware of bit-sign propagation */
1343 } phy_magic[5] = { {
1344 { 0x0000, //w 4 15 12 0
1345 0x00a1, //w 3 15 0 00a1
1346 0x0008, //w 2 15 0 0008
1347 0x1020, //w 1 15 0 1020
1348 0x1000 } },{ //w 0 15 0 1000
1349 { 0x7000, //w 4 15 12 7
1350 0xff41, //w 3 15 0 ff41
1351 0xde60, //w 2 15 0 de60
1352 0x0140, //w 1 15 0 0140
1353 0x0077 } },{ //w 0 15 0 0077
1354 { 0xa000, //w 4 15 12 a
1355 0xdf01, //w 3 15 0 df01
1356 0xdf20, //w 2 15 0 df20
1357 0xff95, //w 1 15 0 ff95
1358 0xfa00 } },{ //w 0 15 0 fa00
1359 { 0xb000, //w 4 15 12 b
1360 0xff41, //w 3 15 0 ff41
1361 0xde20, //w 2 15 0 de20
1362 0x0140, //w 1 15 0 0140
1363 0x00bb } },{ //w 0 15 0 00bb
1364 { 0xf000, //w 4 15 12 f
1365 0xdf01, //w 3 15 0 df01
1366 0xdf20, //w 2 15 0 df20
1367 0xff95, //w 1 15 0 ff95
1368 0xbf00 } //w 0 15 0 bf00
1369 }
1370 }, *p = phy_magic;
07d3f51f 1371 unsigned int i;
1da177e4 1372
a441d7b6
FR		 1373 mdio_write(ioaddr, 0x1f, 0x0001); //w 31 2 0 1
1374 mdio_write(ioaddr, 0x15, 0x1000); //w 21 15 0 1000
1375 mdio_write(ioaddr, 0x18, 0x65c7); //w 24 15 0 65c7
1da177e4
LT		 1376 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1377
1378 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1379 int val, pos = 4;
1380
1381 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1382 mdio_write(ioaddr, pos, val);
1383 while (--pos >= 0)
1384 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1385 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1386 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1387 }
a441d7b6 1388 mdio_write(ioaddr, 0x1f, 0x0000); //w 31 2 0 0
1da177e4
LT		 1389}
1390
5615d9f1
FR		 1391static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1392{
a441d7b6
FR		 1393 struct phy_reg phy_reg_init[] = {
1394 { 0x1f, 0x0002 },
1395 { 0x01, 0x90d0 },
1396 { 0x1f, 0x0000 }
1397 };
1398
1399 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 1400}
1401
236b8082
FR		 1402static void rtl8168bb_hw_phy_config(void __iomem *ioaddr)
1403{
1404 struct phy_reg phy_reg_init[] = {
1405 { 0x10, 0xf41b },
1406 { 0x1f, 0x0000 }
1407 };
1408
1409 mdio_write(ioaddr, 0x1f, 0x0001);
1410 mdio_patch(ioaddr, 0x16, 1 << 0);
1411
1412 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1413}
1414
1415static void rtl8168bef_hw_phy_config(void __iomem *ioaddr)
1416{
1417 struct phy_reg phy_reg_init[] = {
1418 { 0x1f, 0x0001 },
1419 { 0x10, 0xf41b },
1420 { 0x1f, 0x0000 }
1421 };
1422
1423 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1424}
1425
ef3386f0 1426static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr)
867763c1
FR		 1427{
1428 struct phy_reg phy_reg_init[] = {
1429 { 0x1f, 0x0000 },
1430 { 0x1d, 0x0f00 },
1431 { 0x1f, 0x0002 },
1432 { 0x0c, 0x1ec8 },
1433 { 0x1f, 0x0000 }
1434 };
1435
1436 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1437}
1438
ef3386f0
FR		 1439static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr)
1440{
1441 struct phy_reg phy_reg_init[] = {
1442 { 0x1f, 0x0001 },
1443 { 0x1d, 0x3d98 },
1444 { 0x1f, 0x0000 }
1445 };
1446
1447 mdio_write(ioaddr, 0x1f, 0x0000);
1448 mdio_patch(ioaddr, 0x14, 1 << 5);
1449 mdio_patch(ioaddr, 0x0d, 1 << 5);
1450
1451 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1452}
1453
219a1e9d 1454static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr)
867763c1
FR		 1455{
1456 struct phy_reg phy_reg_init[] = {
a3f80671
FR		 1457 { 0x1f, 0x0001 },
1458 { 0x12, 0x2300 },
867763c1
FR		 1459 { 0x1f, 0x0002 },
1460 { 0x00, 0x88d4 },
1461 { 0x01, 0x82b1 },
1462 { 0x03, 0x7002 },
1463 { 0x08, 0x9e30 },
1464 { 0x09, 0x01f0 },
1465 { 0x0a, 0x5500 },
1466 { 0x0c, 0x00c8 },
1467 { 0x1f, 0x0003 },
1468 { 0x12, 0xc096 },
1469 { 0x16, 0x000a },
f50d4275
FR		 1470 { 0x1f, 0x0000 },
1471 { 0x1f, 0x0000 },
1472 { 0x09, 0x2000 },
1473 { 0x09, 0x0000 }
867763c1
FR		 1474 };
1475
1476 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275
FR		 1477
1478 mdio_patch(ioaddr, 0x14, 1 << 5);
1479 mdio_patch(ioaddr, 0x0d, 1 << 5);
1480 mdio_write(ioaddr, 0x1f, 0x0000);
867763c1
FR		 1481}
1482
219a1e9d 1483static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr)
7da97ec9
FR		 1484{
1485 struct phy_reg phy_reg_init[] = {
f50d4275 1486 { 0x1f, 0x0001 },
7da97ec9 1487 { 0x12, 0x2300 },
f50d4275
FR		 1488 { 0x03, 0x802f },
1489 { 0x02, 0x4f02 },
1490 { 0x01, 0x0409 },
1491 { 0x00, 0xf099 },
1492 { 0x04, 0x9800 },
1493 { 0x04, 0x9000 },
1494 { 0x1d, 0x3d98 },
7da97ec9
FR		 1495 { 0x1f, 0x0002 },
1496 { 0x0c, 0x7eb8 },
f50d4275
FR		 1497 { 0x06, 0x0761 },
1498 { 0x1f, 0x0003 },
1499 { 0x16, 0x0f0a },
7da97ec9
FR		 1500 { 0x1f, 0x0000 }
1501 };
1502
1503 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275
FR		 1504
1505 mdio_patch(ioaddr, 0x16, 1 << 0);
1506 mdio_patch(ioaddr, 0x14, 1 << 5);
1507 mdio_patch(ioaddr, 0x0d, 1 << 5);
1508 mdio_write(ioaddr, 0x1f, 0x0000);
7da97ec9
FR		 1509}
1510
197ff761
FR		 1511static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr)
1512{
1513 struct phy_reg phy_reg_init[] = {
1514 { 0x1f, 0x0001 },
1515 { 0x12, 0x2300 },
1516 { 0x1d, 0x3d98 },
1517 { 0x1f, 0x0002 },
1518 { 0x0c, 0x7eb8 },
1519 { 0x06, 0x5461 },
1520 { 0x1f, 0x0003 },
1521 { 0x16, 0x0f0a },
1522 { 0x1f, 0x0000 }
1523 };
1524
1525 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1526
1527 mdio_patch(ioaddr, 0x16, 1 << 0);
1528 mdio_patch(ioaddr, 0x14, 1 << 5);
1529 mdio_patch(ioaddr, 0x0d, 1 << 5);
1530 mdio_write(ioaddr, 0x1f, 0x0000);
1531}
1532
6fb07058
FR		 1533static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr)
1534{
1535 rtl8168c_3_hw_phy_config(ioaddr);
1536}
1537
5b538df9
FR		 1538static void rtl8168d_hw_phy_config(void __iomem *ioaddr)
1539{
1540 struct phy_reg phy_reg_init_0[] = {
1541 { 0x1f, 0x0001 },
1542 { 0x09, 0x2770 },
1543 { 0x08, 0x04d0 },
1544 { 0x0b, 0xad15 },
1545 { 0x0c, 0x5bf0 },
1546 { 0x1c, 0xf101 },
1547 { 0x1f, 0x0003 },
1548 { 0x14, 0x94d7 },
1549 { 0x12, 0xf4d6 },
1550 { 0x09, 0xca0f },
1551 { 0x1f, 0x0002 },
1552 { 0x0b, 0x0b10 },
1553 { 0x0c, 0xd1f7 },
1554 { 0x1f, 0x0002 },
1555 { 0x06, 0x5461 },
1556 { 0x1f, 0x0002 },
1557 { 0x05, 0x6662 },
1558 { 0x1f, 0x0000 },
1559 { 0x14, 0x0060 },
1560 { 0x1f, 0x0000 },
1561 { 0x0d, 0xf8a0 },
1562 { 0x1f, 0x0005 },
1563 { 0x05, 0xffc2 }
1564 };
1565
1566 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
1567
1568 if (mdio_read(ioaddr, 0x06) == 0xc400) {
1569 struct phy_reg phy_reg_init_1[] = {
1570 { 0x1f, 0x0005 },
1571 { 0x01, 0x0300 },
1572 { 0x1f, 0x0000 },
1573 { 0x11, 0x401c },
1574 { 0x16, 0x4100 },
1575 { 0x1f, 0x0005 },
1576 { 0x07, 0x0010 },
1577 { 0x05, 0x83dc },
1578 { 0x06, 0x087d },
1579 { 0x05, 0x8300 },
1580 { 0x06, 0x0101 },
1581 { 0x06, 0x05f8 },
1582 { 0x06, 0xf9fa },
1583 { 0x06, 0xfbef },
1584 { 0x06, 0x79e2 },
1585 { 0x06, 0x835f },
1586 { 0x06, 0xe0f8 },
1587 { 0x06, 0x9ae1 },
1588 { 0x06, 0xf89b },
1589 { 0x06, 0xef31 },
1590 { 0x06, 0x3b65 },
1591 { 0x06, 0xaa07 },
1592 { 0x06, 0x81e4 },
1593 { 0x06, 0xf89a },
1594 { 0x06, 0xe5f8 },
1595 { 0x06, 0x9baf },
1596 { 0x06, 0x06ae },
1597 { 0x05, 0x83dc },
1598 { 0x06, 0x8300 },
1599 };
1600
1601 rtl_phy_write(ioaddr, phy_reg_init_1,
1602 ARRAY_SIZE(phy_reg_init_1));
1603 }
1604
1605 mdio_write(ioaddr, 0x1f, 0x0000);
1606}
1607
2857ffb7
FR		 1608static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
1609{
1610 struct phy_reg phy_reg_init[] = {
1611 { 0x1f, 0x0003 },
1612 { 0x08, 0x441d },
1613 { 0x01, 0x9100 },
1614 { 0x1f, 0x0000 }
1615 };
1616
1617 mdio_write(ioaddr, 0x1f, 0x0000);
1618 mdio_patch(ioaddr, 0x11, 1 << 12);
1619 mdio_patch(ioaddr, 0x19, 1 << 13);
1620
1621 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1622}
1623
5615d9f1
FR		 1624static void rtl_hw_phy_config(struct net_device *dev)
1625{
1626 struct rtl8169_private *tp = netdev_priv(dev);
1627 void __iomem *ioaddr = tp->mmio_addr;
1628
1629 rtl8169_print_mac_version(tp);
1630
1631 switch (tp->mac_version) {
1632 case RTL_GIGA_MAC_VER_01:
1633 break;
1634 case RTL_GIGA_MAC_VER_02:
1635 case RTL_GIGA_MAC_VER_03:
1636 rtl8169s_hw_phy_config(ioaddr);
1637 break;
1638 case RTL_GIGA_MAC_VER_04:
1639 rtl8169sb_hw_phy_config(ioaddr);
1640 break;
2857ffb7
FR		 1641 case RTL_GIGA_MAC_VER_07:
1642 case RTL_GIGA_MAC_VER_08:
1643 case RTL_GIGA_MAC_VER_09:
1644 rtl8102e_hw_phy_config(ioaddr);
1645 break;
236b8082
FR		 1646 case RTL_GIGA_MAC_VER_11:
1647 rtl8168bb_hw_phy_config(ioaddr);
1648 break;
1649 case RTL_GIGA_MAC_VER_12:
1650 rtl8168bef_hw_phy_config(ioaddr);
1651 break;
1652 case RTL_GIGA_MAC_VER_17:
1653 rtl8168bef_hw_phy_config(ioaddr);
1654 break;
867763c1 1655 case RTL_GIGA_MAC_VER_18:
ef3386f0 1656 rtl8168cp_1_hw_phy_config(ioaddr);
867763c1
FR		 1657 break;
1658 case RTL_GIGA_MAC_VER_19:
219a1e9d 1659 rtl8168c_1_hw_phy_config(ioaddr);
867763c1 1660 break;
7da97ec9 1661 case RTL_GIGA_MAC_VER_20:
219a1e9d 1662 rtl8168c_2_hw_phy_config(ioaddr);
7da97ec9 1663 break;
197ff761
FR		 1664 case RTL_GIGA_MAC_VER_21:
1665 rtl8168c_3_hw_phy_config(ioaddr);
1666 break;
6fb07058
FR		 1667 case RTL_GIGA_MAC_VER_22:
1668 rtl8168c_4_hw_phy_config(ioaddr);
1669 break;
ef3386f0 1670 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 1671 case RTL_GIGA_MAC_VER_24:
ef3386f0
FR		 1672 rtl8168cp_2_hw_phy_config(ioaddr);
1673 break;
5b538df9
FR		 1674 case RTL_GIGA_MAC_VER_25:
1675 rtl8168d_hw_phy_config(ioaddr);
1676 break;
ef3386f0 1677
5615d9f1
FR		 1678 default:
1679 break;
1680 }
1681}
1682
1da177e4
LT		 1683static void rtl8169_phy_timer(unsigned long __opaque)
1684{
1685 struct net_device *dev = (struct net_device *)__opaque;
1686 struct rtl8169_private *tp = netdev_priv(dev);
1687 struct timer_list *timer = &tp->timer;
1688 void __iomem *ioaddr = tp->mmio_addr;
1689 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1690
bcf0bf90 1691 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 1692
64e4bfb4 1693 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 1694 return;
1695
1696 spin_lock_irq(&tp->lock);
1697
1698 if (tp->phy_reset_pending(ioaddr)) {
5b0384f4 1699 /*
1da177e4
LT		 1700 * A busy loop could burn quite a few cycles on nowadays CPU.
1701 * Let's delay the execution of the timer for a few ticks.
1702 */
1703 timeout = HZ/10;
1704 goto out_mod_timer;
1705 }
1706
1707 if (tp->link_ok(ioaddr))
1708 goto out_unlock;
1709
b57b7e5a
SH		 1710 if (netif_msg_link(tp))
1711 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1da177e4
LT		 1712
1713 tp->phy_reset_enable(ioaddr);
1714
1715out_mod_timer:
1716 mod_timer(timer, jiffies + timeout);
1717out_unlock:
1718 spin_unlock_irq(&tp->lock);
1719}
1720
1721static inline void rtl8169_delete_timer(struct net_device *dev)
1722{
1723 struct rtl8169_private *tp = netdev_priv(dev);
1724 struct timer_list *timer = &tp->timer;
1725
e179bb7b 1726 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 1727 return;
1728
1729 del_timer_sync(timer);
1730}
1731
1732static inline void rtl8169_request_timer(struct net_device *dev)
1733{
1734 struct rtl8169_private *tp = netdev_priv(dev);
1735 struct timer_list *timer = &tp->timer;
1736
e179bb7b 1737 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 1738 return;
1739
2efa53f3 1740 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1da177e4
LT		 1741}
1742
1743#ifdef CONFIG_NET_POLL_CONTROLLER
1744/*
1745 * Polling 'interrupt' - used by things like netconsole to send skbs
1746 * without having to re-enable interrupts. It's not called while
1747 * the interrupt routine is executing.
1748 */
1749static void rtl8169_netpoll(struct net_device *dev)
1750{
1751 struct rtl8169_private *tp = netdev_priv(dev);
1752 struct pci_dev *pdev = tp->pci_dev;
1753
1754 disable_irq(pdev->irq);
7d12e780 1755 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 1756 enable_irq(pdev->irq);
1757}
1758#endif
1759
1760static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1761 void __iomem *ioaddr)
1762{
1763 iounmap(ioaddr);
1764 pci_release_regions(pdev);
1765 pci_disable_device(pdev);
1766 free_netdev(dev);
1767}
1768
bf793295
FR		 1769static void rtl8169_phy_reset(struct net_device *dev,
1770 struct rtl8169_private *tp)
1771{
1772 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1773 unsigned int i;
bf793295
FR		 1774
1775 tp->phy_reset_enable(ioaddr);
1776 for (i = 0; i < 100; i++) {
1777 if (!tp->phy_reset_pending(ioaddr))
1778 return;
1779 msleep(1);
1780 }
1781 if (netif_msg_link(tp))
1782 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1783}
1784
4ff96fa6
FR		 1785static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1786{
1787 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 1788
5615d9f1 1789 rtl_hw_phy_config(dev);
4ff96fa6 1790
77332894
MS		 1791 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
1792 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1793 RTL_W8(0x82, 0x01);
1794 }
4ff96fa6 1795
6dccd16b
FR		 1796 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1797
1798 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1799 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 1800
bcf0bf90 1801 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 1802 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1803 RTL_W8(0x82, 0x01);
1804 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1805 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1806 }
1807
bf793295
FR		 1808 rtl8169_phy_reset(dev, tp);
1809
901dda2b
FR		 1810 /*
1811 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1812 * only 8101. Don't panic.
1813 */
1814 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
4ff96fa6
FR		 1815
1816 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1817 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1818}
1819
773d2021
FR		 1820static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1821{
1822 void __iomem *ioaddr = tp->mmio_addr;
1823 u32 high;
1824 u32 low;
1825
1826 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1827 high = addr[4] | (addr[5] << 8);
1828
1829 spin_lock_irq(&tp->lock);
1830
1831 RTL_W8(Cfg9346, Cfg9346_Unlock);
1832 RTL_W32(MAC0, low);
1833 RTL_W32(MAC4, high);
1834 RTL_W8(Cfg9346, Cfg9346_Lock);
1835
1836 spin_unlock_irq(&tp->lock);
1837}
1838
1839static int rtl_set_mac_address(struct net_device *dev, void *p)
1840{
1841 struct rtl8169_private *tp = netdev_priv(dev);
1842 struct sockaddr *addr = p;
1843
1844 if (!is_valid_ether_addr(addr->sa_data))
1845 return -EADDRNOTAVAIL;
1846
1847 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1848
1849 rtl_rar_set(tp, dev->dev_addr);
1850
1851 return 0;
1852}
1853
5f787a1a
FR		 1854static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1855{
1856 struct rtl8169_private *tp = netdev_priv(dev);
1857 struct mii_ioctl_data *data = if_mii(ifr);
1858
8b4ab28d
FR		 1859 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
1860}
5f787a1a 1861
8b4ab28d
FR		 1862static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
1863{
5f787a1a
FR		 1864 switch (cmd) {
1865 case SIOCGMIIPHY:
1866 data->phy_id = 32; /* Internal PHY */
1867 return 0;
1868
1869 case SIOCGMIIREG:
1870 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1871 return 0;
1872
1873 case SIOCSMIIREG:
1874 if (!capable(CAP_NET_ADMIN))
1875 return -EPERM;
1876 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1877 return 0;
1878 }
1879 return -EOPNOTSUPP;
1880}
1881
8b4ab28d
FR		 1882static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
1883{
1884 return -EOPNOTSUPP;
1885}
1886
0e485150
FR		 1887static const struct rtl_cfg_info {
1888 void (*hw_start)(struct net_device *);
1889 unsigned int region;
1890 unsigned int align;
1891 u16 intr_event;
1892 u16 napi_event;
ccdffb9a 1893 unsigned features;
0e485150
FR		 1894} rtl_cfg_infos [] = {
1895 [RTL_CFG_0] = {
1896 .hw_start = rtl_hw_start_8169,
1897 .region = 1,
e9f63f30 1898 .align = 0,
0e485150
FR		 1899 .intr_event = SYSErr | LinkChg | RxOverflow |
1900 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 1901 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
ccdffb9a 1902 .features = RTL_FEATURE_GMII
0e485150
FR		 1903 },
1904 [RTL_CFG_1] = {
1905 .hw_start = rtl_hw_start_8168,
1906 .region = 2,
1907 .align = 8,
1908 .intr_event = SYSErr | LinkChg | RxOverflow |
1909 TxErr | TxOK | RxOK | RxErr,
fbac58fc 1910 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
ccdffb9a 1911 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI
0e485150
FR		 1912 },
1913 [RTL_CFG_2] = {
1914 .hw_start = rtl_hw_start_8101,
1915 .region = 2,
1916 .align = 8,
1917 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1918 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 1919 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
ccdffb9a 1920 .features = RTL_FEATURE_MSI
0e485150
FR		 1921 }
1922};
1923
fbac58fc
FR		 1924/* Cfg9346_Unlock assumed. */
1925static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
1926 const struct rtl_cfg_info *cfg)
1927{
1928 unsigned msi = 0;
1929 u8 cfg2;
1930
1931 cfg2 = RTL_R8(Config2) & ~MSIEnable;
ccdffb9a 1932 if (cfg->features & RTL_FEATURE_MSI) {
fbac58fc
FR		 1933 if (pci_enable_msi(pdev)) {
1934 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
1935 } else {
1936 cfg2 |= MSIEnable;
1937 msi = RTL_FEATURE_MSI;
1938 }
1939 }
1940 RTL_W8(Config2, cfg2);
1941 return msi;
1942}
1943
1944static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
1945{
1946 if (tp->features & RTL_FEATURE_MSI) {
1947 pci_disable_msi(pdev);
1948 tp->features &= ~RTL_FEATURE_MSI;
1949 }
1950}
1951
8b4ab28d
FR		 1952static const struct net_device_ops rtl8169_netdev_ops = {
1953 .ndo_open = rtl8169_open,
1954 .ndo_stop = rtl8169_close,
1955 .ndo_get_stats = rtl8169_get_stats,
00829823 1956 .ndo_start_xmit = rtl8169_start_xmit,
8b4ab28d
FR		 1957 .ndo_tx_timeout = rtl8169_tx_timeout,
1958 .ndo_validate_addr = eth_validate_addr,
1959 .ndo_change_mtu = rtl8169_change_mtu,
1960 .ndo_set_mac_address = rtl_set_mac_address,
1961 .ndo_do_ioctl = rtl8169_ioctl,
1962 .ndo_set_multicast_list = rtl_set_rx_mode,
1963#ifdef CONFIG_R8169_VLAN
1964 .ndo_vlan_rx_register = rtl8169_vlan_rx_register,
1965#endif
1966#ifdef CONFIG_NET_POLL_CONTROLLER
1967 .ndo_poll_controller = rtl8169_netpoll,
1968#endif
1969
1970};
1971
6709fe9a
IV		 1972/* Delay between EEPROM clock transitions. Force out buffered PCI writes. */
1973#define RTL_EEPROM_DELAY() RTL_R8(Cfg9346)
1974#define RTL_EEPROM_READ_CMD 6
1975
1976/* read 16bit word stored in EEPROM. EEPROM is addressed by words. */
1977static u16 rtl_eeprom_read(void __iomem *ioaddr, int addr)
1978{
1979 u16 result = 0;
1980 int cmd, cmd_len, i;
1981
1982 /* check for EEPROM address size (in bits) */
1983 if (RTL_R32(RxConfig) & (1 << RxCfg9356SEL)) {
1984 /* EEPROM is 93C56 */
1985 cmd_len = 3 + 8; /* 3 bits for command id and 8 for address */
1986 cmd = (RTL_EEPROM_READ_CMD << 8) | (addr & 0xff);
1987 } else {
1988 /* EEPROM is 93C46 */
1989 cmd_len = 3 + 6; /* 3 bits for command id and 6 for address */
1990 cmd = (RTL_EEPROM_READ_CMD << 6) | (addr & 0x3f);
1991 }
1992
1993 /* enter programming mode */
1994 RTL_W8(Cfg9346, Cfg9346_Program | Cfg9346_EECS);
1995 RTL_EEPROM_DELAY();
1996
1997 /* write command and requested address */
1998 while (cmd_len--) {
1999 u8 x = Cfg9346_Program | Cfg9346_EECS;
2000
2001 x |= (cmd & (1 << cmd_len)) ? Cfg9346_EEDI : 0;
2002
2003 /* write a bit */
2004 RTL_W8(Cfg9346, x);
2005 RTL_EEPROM_DELAY();
2006
2007 /* raise clock */
2008 RTL_W8(Cfg9346, x | Cfg9346_EESK);
2009 RTL_EEPROM_DELAY();
2010 }
2011
2012 /* lower clock */
2013 RTL_W8(Cfg9346, Cfg9346_Program | Cfg9346_EECS);
2014 RTL_EEPROM_DELAY();
2015
2016 /* read back 16bit value */
2017 for (i = 16; i > 0; i--) {
2018 /* raise clock */
2019 RTL_W8(Cfg9346, Cfg9346_Program | Cfg9346_EECS | Cfg9346_EESK);
2020 RTL_EEPROM_DELAY();
2021
2022 result <<= 1;
2023 result |= (RTL_R8(Cfg9346) & Cfg9346_EEDO) ? 1 : 0;
2024
2025 /* lower clock */
2026 RTL_W8(Cfg9346, Cfg9346_Program | Cfg9346_EECS);
2027 RTL_EEPROM_DELAY();
2028 }
2029
2030 RTL_W8(Cfg9346, Cfg9346_Program);
2031 /* leave programming mode */
2032 RTL_W8(Cfg9346, Cfg9346_Lock);
2033
2034 return result;
2035}
2036
2037static void rtl_init_mac_address(struct rtl8169_private *tp,
2038 void __iomem *ioaddr)
2039{
2040 struct pci_dev *pdev = tp->pci_dev;
2041 u16 x;
2042 u8 mac[8];
2043
2044 /* read EEPROM signature */
2045 x = rtl_eeprom_read(ioaddr, RTL_EEPROM_SIG_ADDR);
2046
2047 if (x != RTL_EEPROM_SIG) {
2048 dev_info(&pdev->dev, "Missing EEPROM signature: %04x\n", x);
2049 return;
2050 }
2051
2052 /* read MAC address */
2053 x = rtl_eeprom_read(ioaddr, RTL_EEPROM_MAC_ADDR);
2054 mac[0] = x & 0xff;
2055 mac[1] = x >> 8;
2056 x = rtl_eeprom_read(ioaddr, RTL_EEPROM_MAC_ADDR + 1);
2057 mac[2] = x & 0xff;
2058 mac[3] = x >> 8;
2059 x = rtl_eeprom_read(ioaddr, RTL_EEPROM_MAC_ADDR + 2);
2060 mac[4] = x & 0xff;
2061 mac[5] = x >> 8;
2062
2063 if (netif_msg_probe(tp)) {
2064 DECLARE_MAC_BUF(buf);
2065
2066 dev_info(&pdev->dev, "MAC address found in EEPROM: %s\n",
2067 print_mac(buf, mac));
2068 }
2069
2070 if (is_valid_ether_addr(mac))
2071 rtl_rar_set(tp, mac);
2072}
2073
1da177e4 2074static int __devinit
4ff96fa6 2075rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 2076{
0e485150
FR		 2077 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
2078 const unsigned int region = cfg->region;
1da177e4 2079 struct rtl8169_private *tp;
ccdffb9a 2080 struct mii_if_info *mii;
4ff96fa6
FR		 2081 struct net_device *dev;
2082 void __iomem *ioaddr;
07d3f51f
FR		 2083 unsigned int i;
2084 int rc;
1da177e4 2085
4ff96fa6
FR		 2086 if (netif_msg_drv(&debug)) {
2087 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
2088 MODULENAME, RTL8169_VERSION);
2089 }
1da177e4 2090
1da177e4 2091 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 2092 if (!dev) {
b57b7e5a 2093 if (netif_msg_drv(&debug))
9b91cf9d 2094 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 2095 rc = -ENOMEM;
2096 goto out;
1da177e4
LT		 2097 }
2098
1da177e4 2099 SET_NETDEV_DEV(dev, &pdev->dev);
8b4ab28d 2100 dev->netdev_ops = &rtl8169_netdev_ops;
1da177e4 2101 tp = netdev_priv(dev);
c4028958 2102 tp->dev = dev;
21e197f2 2103 tp->pci_dev = pdev;
b57b7e5a 2104 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4 2105
ccdffb9a
FR		 2106 mii = &tp->mii;
2107 mii->dev = dev;
2108 mii->mdio_read = rtl_mdio_read;
2109 mii->mdio_write = rtl_mdio_write;
2110 mii->phy_id_mask = 0x1f;
2111 mii->reg_num_mask = 0x1f;
2112 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
2113
1da177e4
LT		 2114 /* enable device (incl. PCI PM wakeup and hotplug setup) */
2115 rc = pci_enable_device(pdev);
b57b7e5a 2116 if (rc < 0) {
2e8a538d 2117 if (netif_msg_probe(tp))
9b91cf9d 2118 dev_err(&pdev->dev, "enable failure\n");
4ff96fa6 2119 goto err_out_free_dev_1;
1da177e4
LT		 2120 }
2121
2122 rc = pci_set_mwi(pdev);
2123 if (rc < 0)
4ff96fa6 2124 goto err_out_disable_2;
1da177e4 2125
1da177e4 2126 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 2127 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
4ff96fa6 2128 if (netif_msg_probe(tp)) {
9b91cf9d 2129 dev_err(&pdev->dev,
bcf0bf90
FR		 2130 "region #%d not an MMIO resource, aborting\n",
2131 region);
4ff96fa6 2132 }
1da177e4 2133 rc = -ENODEV;
4ff96fa6 2134 goto err_out_mwi_3;
1da177e4 2135 }
4ff96fa6 2136
1da177e4 2137 /* check for weird/broken PCI region reporting */
bcf0bf90 2138 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
4ff96fa6 2139 if (netif_msg_probe(tp)) {
9b91cf9d 2140 dev_err(&pdev->dev,
4ff96fa6
FR		 2141 "Invalid PCI region size(s), aborting\n");
2142 }
1da177e4 2143 rc = -ENODEV;
4ff96fa6 2144 goto err_out_mwi_3;
1da177e4
LT		 2145 }
2146
2147 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 2148 if (rc < 0) {
2e8a538d 2149 if (netif_msg_probe(tp))
9b91cf9d 2150 dev_err(&pdev->dev, "could not request regions.\n");
4ff96fa6 2151 goto err_out_mwi_3;
1da177e4
LT		 2152 }
2153
2154 tp->cp_cmd = PCIMulRW | RxChkSum;
2155
2156 if ((sizeof(dma_addr_t) > 4) &&
2157 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
2158 tp->cp_cmd |= PCIDAC;
2159 dev->features |= NETIF_F_HIGHDMA;
2160 } else {
2161 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2162 if (rc < 0) {
4ff96fa6 2163 if (netif_msg_probe(tp)) {
9b91cf9d 2164 dev_err(&pdev->dev,
4ff96fa6
FR		 2165 "DMA configuration failed.\n");
2166 }
2167 goto err_out_free_res_4;
1da177e4
LT		 2168 }
2169 }
2170
2171 pci_set_master(pdev);
2172
2173 /* ioremap MMIO region */
bcf0bf90 2174 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 2175 if (!ioaddr) {
b57b7e5a 2176 if (netif_msg_probe(tp))
9b91cf9d 2177 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1da177e4 2178 rc = -EIO;
4ff96fa6 2179 goto err_out_free_res_4;
1da177e4
LT		 2180 }
2181
9c14ceaf
FR		 2182 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2183 if (!tp->pcie_cap && netif_msg_probe(tp))
2184 dev_info(&pdev->dev, "no PCI Express capability\n");
2185
1da177e4
LT		 2186 /* Unneeded ? Don't mess with Mrs. Murphy. */
2187 rtl8169_irq_mask_and_ack(ioaddr);
2188
2189 /* Soft reset the chip. */
2190 RTL_W8(ChipCmd, CmdReset);
2191
2192 /* Check that the chip has finished the reset. */
07d3f51f 2193 for (i = 0; i < 100; i++) {
1da177e4
LT		 2194 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2195 break;
b518fa8e 2196 msleep_interruptible(1);
1da177e4
LT		 2197 }
2198
2199 /* Identify chip attached to board */
2200 rtl8169_get_mac_version(tp, ioaddr);
1da177e4
LT		 2201
2202 rtl8169_print_mac_version(tp);
1da177e4 2203
cee60c37 2204 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
1da177e4
LT		 2205 if (tp->mac_version == rtl_chip_info[i].mac_version)
2206 break;
2207 }
cee60c37 2208 if (i == ARRAY_SIZE(rtl_chip_info)) {
1da177e4 2209 /* Unknown chip: assume array element #0, original RTL-8169 */
b57b7e5a 2210 if (netif_msg_probe(tp)) {
2e8a538d 2211 dev_printk(KERN_DEBUG, &pdev->dev,
4ff96fa6
FR		 2212 "unknown chip version, assuming %s\n",
2213 rtl_chip_info[0].name);
b57b7e5a 2214 }
cee60c37 2215 i = 0;
1da177e4
LT		 2216 }
2217 tp->chipset = i;
2218
5d06a99f
FR		 2219 RTL_W8(Cfg9346, Cfg9346_Unlock);
2220 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
2221 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
20037fa4
BP		 2222 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
2223 tp->features |= RTL_FEATURE_WOL;
2224 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
2225 tp->features |= RTL_FEATURE_WOL;
fbac58fc 2226 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
5d06a99f
FR		 2227 RTL_W8(Cfg9346, Cfg9346_Lock);
2228
66ec5d4f
FR		 2229 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
2230 (RTL_R8(PHYstatus) & TBI_Enable)) {
1da177e4
LT		 2231 tp->set_speed = rtl8169_set_speed_tbi;
2232 tp->get_settings = rtl8169_gset_tbi;
2233 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
2234 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
2235 tp->link_ok = rtl8169_tbi_link_ok;
8b4ab28d 2236 tp->do_ioctl = rtl_tbi_ioctl;
1da177e4 2237
64e4bfb4 2238 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1da177e4
LT		 2239 } else {
2240 tp->set_speed = rtl8169_set_speed_xmii;
2241 tp->get_settings = rtl8169_gset_xmii;
2242 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
2243 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
2244 tp->link_ok = rtl8169_xmii_link_ok;
8b4ab28d 2245 tp->do_ioctl = rtl_xmii_ioctl;
1da177e4
LT		 2246 }
2247
df58ef51
FR		 2248 spin_lock_init(&tp->lock);
2249
738e1e69
PV		 2250 tp->mmio_addr = ioaddr;
2251
6709fe9a
IV		 2252 rtl_init_mac_address(tp, ioaddr);
2253
7bf6bf48 2254 /* Get MAC address */
1da177e4
LT		 2255 for (i = 0; i < MAC_ADDR_LEN; i++)
2256 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 2257 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4 2258
1da177e4 2259 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1da177e4
LT		 2260 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
2261 dev->irq = pdev->irq;
2262 dev->base_addr = (unsigned long) ioaddr;
1da177e4 2263
bea3348e 2264 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4
LT		 2265
2266#ifdef CONFIG_R8169_VLAN
2267 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4
LT		 2268#endif
2269
2270 tp->intr_mask = 0xffff;
0e485150
FR		 2271 tp->align = cfg->align;
2272 tp->hw_start = cfg->hw_start;
2273 tp->intr_event = cfg->intr_event;
2274 tp->napi_event = cfg->napi_event;
1da177e4 2275
2efa53f3
FR		 2276 init_timer(&tp->timer);
2277 tp->timer.data = (unsigned long) dev;
2278 tp->timer.function = rtl8169_phy_timer;
2279
1da177e4 2280 rc = register_netdev(dev);
4ff96fa6 2281 if (rc < 0)
fbac58fc 2282 goto err_out_msi_5;
1da177e4
LT		 2283
2284 pci_set_drvdata(pdev, dev);
2285
b57b7e5a 2286 if (netif_msg_probe(tp)) {
96b9709c
FR		 2287 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
2288
b57b7e5a
SH		 2289 printk(KERN_INFO "%s: %s at 0x%lx, "
2290 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
96b9709c 2291 "XID %08x IRQ %d\n",
b57b7e5a 2292 dev->name,
bcf0bf90 2293 rtl_chip_info[tp->chipset].name,
b57b7e5a
SH		 2294 dev->base_addr,
2295 dev->dev_addr[0], dev->dev_addr[1],
2296 dev->dev_addr[2], dev->dev_addr[3],
96b9709c 2297 dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
b57b7e5a 2298 }
1da177e4 2299
4ff96fa6 2300 rtl8169_init_phy(dev, tp);
8b76ab39 2301 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
1da177e4 2302
4ff96fa6
FR		 2303out:
2304 return rc;
1da177e4 2305
fbac58fc
FR		 2306err_out_msi_5:
2307 rtl_disable_msi(pdev, tp);
4ff96fa6
FR		 2308 iounmap(ioaddr);
2309err_out_free_res_4:
2310 pci_release_regions(pdev);
2311err_out_mwi_3:
2312 pci_clear_mwi(pdev);
2313err_out_disable_2:
2314 pci_disable_device(pdev);
2315err_out_free_dev_1:
2316 free_netdev(dev);
2317 goto out;
1da177e4
LT		 2318}
2319
07d3f51f 2320static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 2321{
2322 struct net_device *dev = pci_get_drvdata(pdev);
2323 struct rtl8169_private *tp = netdev_priv(dev);
2324
eb2a021c
FR		 2325 flush_scheduled_work();
2326
1da177e4 2327 unregister_netdev(dev);
fbac58fc 2328 rtl_disable_msi(pdev, tp);
1da177e4
LT		 2329 rtl8169_release_board(pdev, dev, tp->mmio_addr);
2330 pci_set_drvdata(pdev, NULL);
2331}
2332
1da177e4
LT		 2333static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
2334 struct net_device *dev)
2335{
2336 unsigned int mtu = dev->mtu;
2337
2338 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
2339}
2340
2341static int rtl8169_open(struct net_device *dev)
2342{
2343 struct rtl8169_private *tp = netdev_priv(dev);
2344 struct pci_dev *pdev = tp->pci_dev;
99f252b0 2345 int retval = -ENOMEM;
1da177e4 2346
1da177e4 2347
99f252b0 2348 rtl8169_set_rxbufsize(tp, dev);
1da177e4
LT		 2349
2350 /*
2351 * Rx and Tx desscriptors needs 256 bytes alignment.
2352 * pci_alloc_consistent provides more.
2353 */
2354 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
2355 &tp->TxPhyAddr);
2356 if (!tp->TxDescArray)
99f252b0 2357 goto out;
1da177e4
LT		 2358
2359 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
2360 &tp->RxPhyAddr);
2361 if (!tp->RxDescArray)
99f252b0 2362 goto err_free_tx_0;
1da177e4
LT		 2363
2364 retval = rtl8169_init_ring(dev);
2365 if (retval < 0)
99f252b0 2366 goto err_free_rx_1;
1da177e4 2367
c4028958 2368 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 2369
99f252b0
FR		 2370 smp_mb();
2371
fbac58fc
FR		 2372 retval = request_irq(dev->irq, rtl8169_interrupt,
2373 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 2374 dev->name, dev);
2375 if (retval < 0)
2376 goto err_release_ring_2;
2377
bea3348e 2378 napi_enable(&tp->napi);
bea3348e 2379
07ce4064 2380 rtl_hw_start(dev);
1da177e4
LT		 2381
2382 rtl8169_request_timer(dev);
2383
2384 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
2385out:
2386 return retval;
2387
99f252b0
FR		 2388err_release_ring_2:
2389 rtl8169_rx_clear(tp);
2390err_free_rx_1:
1da177e4
LT		 2391 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2392 tp->RxPhyAddr);
99f252b0 2393err_free_tx_0:
1da177e4
LT		 2394 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2395 tp->TxPhyAddr);
1da177e4
LT		 2396 goto out;
2397}
2398
2399static void rtl8169_hw_reset(void __iomem *ioaddr)
2400{
2401 /* Disable interrupts */
2402 rtl8169_irq_mask_and_ack(ioaddr);
2403
2404 /* Reset the chipset */
2405 RTL_W8(ChipCmd, CmdReset);
2406
2407 /* PCI commit */
2408 RTL_R8(ChipCmd);
2409}
2410
7f796d83 2411static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 2412{
2413 void __iomem *ioaddr = tp->mmio_addr;
2414 u32 cfg = rtl8169_rx_config;
2415
2416 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2417 RTL_W32(RxConfig, cfg);
2418
2419 /* Set DMA burst size and Interframe Gap Time */
2420 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2421 (InterFrameGap << TxInterFrameGapShift));
2422}
2423
07ce4064 2424static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 2425{
2426 struct rtl8169_private *tp = netdev_priv(dev);
2427 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 2428 unsigned int i;
1da177e4
LT		 2429
2430 /* Soft reset the chip. */
2431 RTL_W8(ChipCmd, CmdReset);
2432
2433 /* Check that the chip has finished the reset. */
07d3f51f 2434 for (i = 0; i < 100; i++) {
1da177e4
LT		 2435 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2436 break;
b518fa8e 2437 msleep_interruptible(1);
1da177e4
LT		 2438 }
2439
07ce4064
FR		 2440 tp->hw_start(dev);
2441
07ce4064
FR		 2442 netif_start_queue(dev);
2443}
2444
2445
7f796d83
FR		 2446static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
2447 void __iomem *ioaddr)
2448{
2449 /*
2450 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2451 * register to be written before TxDescAddrLow to work.
2452 * Switching from MMIO to I/O access fixes the issue as well.
2453 */
2454 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2455 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
2456 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2457 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
2458}
2459
2460static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
2461{
2462 u16 cmd;
2463
2464 cmd = RTL_R16(CPlusCmd);
2465 RTL_W16(CPlusCmd, cmd);
2466 return cmd;
2467}
2468
2469static void rtl_set_rx_max_size(void __iomem *ioaddr)
2470{
2471 /* Low hurts. Let's disable the filtering. */
2472 RTL_W16(RxMaxSize, 16383);
2473}
2474
6dccd16b
FR		 2475static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
2476{
2477 struct {
2478 u32 mac_version;
2479 u32 clk;
2480 u32 val;
2481 } cfg2_info [] = {
2482 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
2483 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
2484 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
2485 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
2486 }, *p = cfg2_info;
2487 unsigned int i;
2488 u32 clk;
2489
2490 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 2491 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 2492 if ((p->mac_version == mac_version) && (p->clk == clk)) {
2493 RTL_W32(0x7c, p->val);
2494 break;
2495 }
2496 }
2497}
2498
07ce4064
FR		 2499static void rtl_hw_start_8169(struct net_device *dev)
2500{
2501 struct rtl8169_private *tp = netdev_priv(dev);
2502 void __iomem *ioaddr = tp->mmio_addr;
2503 struct pci_dev *pdev = tp->pci_dev;
07ce4064 2504
9cb427b6
FR		 2505 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
2506 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
2507 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
2508 }
2509
1da177e4 2510 RTL_W8(Cfg9346, Cfg9346_Unlock);
9cb427b6
FR		 2511 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2512 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2513 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2514 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2515 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2516
1da177e4
LT		 2517 RTL_W8(EarlyTxThres, EarlyTxThld);
2518
7f796d83 2519 rtl_set_rx_max_size(ioaddr);
1da177e4 2520
c946b304
FR		 2521 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2522 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2523 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2524 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2525 rtl_set_rx_tx_config_registers(tp);
1da177e4 2526
7f796d83 2527 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 2528
bcf0bf90
FR		 2529 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2530 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
06fa7358 2531 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 2532 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 2533 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 2534 }
2535
bcf0bf90
FR		 2536 RTL_W16(CPlusCmd, tp->cp_cmd);
2537
6dccd16b
FR		 2538 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
2539
1da177e4
LT		 2540 /*
2541 * Undocumented corner. Supposedly:
2542 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2543 */
2544 RTL_W16(IntrMitigate, 0x0000);
2545
7f796d83 2546 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 2547
c946b304
FR		 2548 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
2549 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
2550 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
2551 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
2552 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2553 rtl_set_rx_tx_config_registers(tp);
2554 }
2555
1da177e4 2556 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 2557
2558 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2559 RTL_R8(IntrMask);
1da177e4
LT		 2560
2561 RTL_W32(RxMissed, 0);
2562
07ce4064 2563 rtl_set_rx_mode(dev);
1da177e4
LT		 2564
2565 /* no early-rx interrupts */
2566 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 2567
2568 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 2569 RTL_W16(IntrMask, tp->intr_event);
07ce4064 2570}
1da177e4 2571
9c14ceaf 2572static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
458a9f61 2573{
9c14ceaf
FR		 2574 struct net_device *dev = pci_get_drvdata(pdev);
2575 struct rtl8169_private *tp = netdev_priv(dev);
2576 int cap = tp->pcie_cap;
2577
2578 if (cap) {
2579 u16 ctl;
458a9f61 2580
9c14ceaf
FR		 2581 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
2582 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
2583 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
2584 }
458a9f61
FR		 2585}
2586
dacf8154
FR		 2587static void rtl_csi_access_enable(void __iomem *ioaddr)
2588{
2589 u32 csi;
2590
2591 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
2592 rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
2593}
2594
2595struct ephy_info {
2596 unsigned int offset;
2597 u16 mask;
2598 u16 bits;
2599};
2600
2601static void rtl_ephy_init(void __iomem *ioaddr, struct ephy_info *e, int len)
2602{
2603 u16 w;
2604
2605 while (len-- > 0) {
2606 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
2607 rtl_ephy_write(ioaddr, e->offset, w);
2608 e++;
2609 }
2610}
2611
b726e493
FR		 2612static void rtl_disable_clock_request(struct pci_dev *pdev)
2613{
2614 struct net_device *dev = pci_get_drvdata(pdev);
2615 struct rtl8169_private *tp = netdev_priv(dev);
2616 int cap = tp->pcie_cap;
2617
2618 if (cap) {
2619 u16 ctl;
2620
2621 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
2622 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
2623 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
2624 }
2625}
2626
2627#define R8168_CPCMD_QUIRK_MASK (\
2628 EnableBist | \
2629 Mac_dbgo_oe | \
2630 Force_half_dup | \
2631 Force_rxflow_en | \
2632 Force_txflow_en | \
2633 Cxpl_dbg_sel | \
2634 ASF | \
2635 PktCntrDisable | \
2636 Mac_dbgo_sel)
2637
219a1e9d
FR		 2638static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
2639{
b726e493
FR		 2640 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2641
2642 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2643
2e68ae44
FR		 2644 rtl_tx_performance_tweak(pdev,
2645 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
219a1e9d
FR		 2646}
2647
2648static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
2649{
2650 rtl_hw_start_8168bb(ioaddr, pdev);
b726e493
FR		 2651
2652 RTL_W8(EarlyTxThres, EarlyTxThld);
2653
2654 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 2655}
2656
2657static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
2658{
b726e493
FR		 2659 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
2660
2661 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2662
219a1e9d 2663 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 2664
2665 rtl_disable_clock_request(pdev);
2666
2667 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 2668}
2669
ef3386f0 2670static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
219a1e9d 2671{
b726e493
FR		 2672 static struct ephy_info e_info_8168cp[] = {
2673 { 0x01, 0, 0x0001 },
2674 { 0x02, 0x0800, 0x1000 },
2675 { 0x03, 0, 0x0042 },
2676 { 0x06, 0x0080, 0x0000 },
2677 { 0x07, 0, 0x2000 }
2678 };
2679
2680 rtl_csi_access_enable(ioaddr);
2681
2682 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
2683
219a1e9d
FR		 2684 __rtl_hw_start_8168cp(ioaddr, pdev);
2685}
2686
ef3386f0
FR		 2687static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
2688{
2689 rtl_csi_access_enable(ioaddr);
2690
2691 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2692
2693 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2694
2695 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2696}
2697
7f3e3d3a
FR		 2698static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
2699{
2700 rtl_csi_access_enable(ioaddr);
2701
2702 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2703
2704 /* Magic. */
2705 RTL_W8(DBG_REG, 0x20);
2706
2707 RTL_W8(EarlyTxThres, EarlyTxThld);
2708
2709 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2710
2711 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2712}
2713
219a1e9d
FR		 2714static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
2715{
b726e493
FR		 2716 static struct ephy_info e_info_8168c_1[] = {
2717 { 0x02, 0x0800, 0x1000 },
2718 { 0x03, 0, 0x0002 },
2719 { 0x06, 0x0080, 0x0000 }
2720 };
2721
2722 rtl_csi_access_enable(ioaddr);
2723
2724 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
2725
2726 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
2727
219a1e9d
FR		 2728 __rtl_hw_start_8168cp(ioaddr, pdev);
2729}
2730
2731static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
2732{
b726e493
FR		 2733 static struct ephy_info e_info_8168c_2[] = {
2734 { 0x01, 0, 0x0001 },
2735 { 0x03, 0x0400, 0x0220 }
2736 };
2737
2738 rtl_csi_access_enable(ioaddr);
2739
2740 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
2741
219a1e9d
FR		 2742 __rtl_hw_start_8168cp(ioaddr, pdev);
2743}
2744
197ff761
FR		 2745static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
2746{
2747 rtl_hw_start_8168c_2(ioaddr, pdev);
2748}
2749
6fb07058
FR		 2750static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
2751{
2752 rtl_csi_access_enable(ioaddr);
2753
2754 __rtl_hw_start_8168cp(ioaddr, pdev);
2755}
2756
5b538df9
FR		 2757static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
2758{
2759 rtl_csi_access_enable(ioaddr);
2760
2761 rtl_disable_clock_request(pdev);
2762
2763 RTL_W8(EarlyTxThres, EarlyTxThld);
2764
2765 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2766
2767 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2768}
2769
07ce4064
FR		 2770static void rtl_hw_start_8168(struct net_device *dev)
2771{
2dd99530
FR		 2772 struct rtl8169_private *tp = netdev_priv(dev);
2773 void __iomem *ioaddr = tp->mmio_addr;
0e485150 2774 struct pci_dev *pdev = tp->pci_dev;
2dd99530
FR		 2775
2776 RTL_W8(Cfg9346, Cfg9346_Unlock);
2777
2778 RTL_W8(EarlyTxThres, EarlyTxThld);
2779
2780 rtl_set_rx_max_size(ioaddr);
2781
0e485150 2782 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 2783
2784 RTL_W16(CPlusCmd, tp->cp_cmd);
2785
0e485150 2786 RTL_W16(IntrMitigate, 0x5151);
2dd99530 2787
0e485150
FR		 2788 /* Work around for RxFIFO overflow. */
2789 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2790 tp->intr_event |= RxFIFOOver | PCSTimeout;
2791 tp->intr_event &= ~RxOverflow;
2792 }
2793
2794 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 2795
b8363901
FR		 2796 rtl_set_rx_mode(dev);
2797
2798 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2799 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 2800
2801 RTL_R8(IntrMask);
2802
219a1e9d
FR		 2803 switch (tp->mac_version) {
2804 case RTL_GIGA_MAC_VER_11:
2805 rtl_hw_start_8168bb(ioaddr, pdev);
2806 break;
2807
2808 case RTL_GIGA_MAC_VER_12:
2809 case RTL_GIGA_MAC_VER_17:
2810 rtl_hw_start_8168bef(ioaddr, pdev);
2811 break;
2812
2813 case RTL_GIGA_MAC_VER_18:
ef3386f0 2814 rtl_hw_start_8168cp_1(ioaddr, pdev);
219a1e9d
FR		 2815 break;
2816
2817 case RTL_GIGA_MAC_VER_19:
2818 rtl_hw_start_8168c_1(ioaddr, pdev);
2819 break;
2820
2821 case RTL_GIGA_MAC_VER_20:
2822 rtl_hw_start_8168c_2(ioaddr, pdev);
2823 break;
2824
197ff761
FR		 2825 case RTL_GIGA_MAC_VER_21:
2826 rtl_hw_start_8168c_3(ioaddr, pdev);
2827 break;
2828
6fb07058
FR		 2829 case RTL_GIGA_MAC_VER_22:
2830 rtl_hw_start_8168c_4(ioaddr, pdev);
2831 break;
2832
ef3386f0
FR		 2833 case RTL_GIGA_MAC_VER_23:
2834 rtl_hw_start_8168cp_2(ioaddr, pdev);
2835 break;
2836
7f3e3d3a
FR		 2837 case RTL_GIGA_MAC_VER_24:
2838 rtl_hw_start_8168cp_3(ioaddr, pdev);
2839 break;
2840
5b538df9
FR		 2841 case RTL_GIGA_MAC_VER_25:
2842 rtl_hw_start_8168d(ioaddr, pdev);
2843 break;
2844
219a1e9d
FR		 2845 default:
2846 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
2847 dev->name, tp->mac_version);
2848 break;
2849 }
2dd99530 2850
0e485150
FR		 2851 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2852
b8363901
FR		 2853 RTL_W8(Cfg9346, Cfg9346_Lock);
2854
2dd99530 2855 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 2856
0e485150 2857 RTL_W16(IntrMask, tp->intr_event);
07ce4064 2858}
1da177e4 2859
2857ffb7
FR		 2860#define R810X_CPCMD_QUIRK_MASK (\
2861 EnableBist | \
2862 Mac_dbgo_oe | \
2863 Force_half_dup | \
2864 Force_half_dup | \
2865 Force_txflow_en | \
2866 Cxpl_dbg_sel | \
2867 ASF | \
2868 PktCntrDisable | \
2869 PCIDAC | \
2870 PCIMulRW)
2871
2872static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
2873{
2874 static struct ephy_info e_info_8102e_1[] = {
2875 { 0x01, 0, 0x6e65 },
2876 { 0x02, 0, 0x091f },
2877 { 0x03, 0, 0xc2f9 },
2878 { 0x06, 0, 0xafb5 },
2879 { 0x07, 0, 0x0e00 },
2880 { 0x19, 0, 0xec80 },
2881 { 0x01, 0, 0x2e65 },
2882 { 0x01, 0, 0x6e65 }
2883 };
2884 u8 cfg1;
2885
2886 rtl_csi_access_enable(ioaddr);
2887
2888 RTL_W8(DBG_REG, FIX_NAK_1);
2889
2890 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2891
2892 RTL_W8(Config1,
2893 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
2894 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2895
2896 cfg1 = RTL_R8(Config1);
2897 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
2898 RTL_W8(Config1, cfg1 & ~LEDS0);
2899
2900 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2901
2902 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2903}
2904
2905static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
2906{
2907 rtl_csi_access_enable(ioaddr);
2908
2909 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2910
2911 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
2912 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2913
2914 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2915}
2916
2917static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
2918{
2919 rtl_hw_start_8102e_2(ioaddr, pdev);
2920
2921 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
2922}
2923
07ce4064
FR		 2924static void rtl_hw_start_8101(struct net_device *dev)
2925{
cdf1a608
FR		 2926 struct rtl8169_private *tp = netdev_priv(dev);
2927 void __iomem *ioaddr = tp->mmio_addr;
2928 struct pci_dev *pdev = tp->pci_dev;
2929
e3cf0cc0
FR		 2930 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2931 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
9c14ceaf
FR		 2932 int cap = tp->pcie_cap;
2933
2934 if (cap) {
2935 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
2936 PCI_EXP_DEVCTL_NOSNOOP_EN);
2937 }
cdf1a608
FR		 2938 }
2939
2857ffb7
FR		 2940 switch (tp->mac_version) {
2941 case RTL_GIGA_MAC_VER_07:
2942 rtl_hw_start_8102e_1(ioaddr, pdev);
2943 break;
2944
2945 case RTL_GIGA_MAC_VER_08:
2946 rtl_hw_start_8102e_3(ioaddr, pdev);
2947 break;
2948
2949 case RTL_GIGA_MAC_VER_09:
2950 rtl_hw_start_8102e_2(ioaddr, pdev);
2951 break;
cdf1a608
FR		 2952 }
2953
2954 RTL_W8(Cfg9346, Cfg9346_Unlock);
2955
2956 RTL_W8(EarlyTxThres, EarlyTxThld);
2957
2958 rtl_set_rx_max_size(ioaddr);
2959
2960 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2961
2962 RTL_W16(CPlusCmd, tp->cp_cmd);
2963
2964 RTL_W16(IntrMitigate, 0x0000);
2965
2966 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2967
2968 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2969 rtl_set_rx_tx_config_registers(tp);
2970
2971 RTL_W8(Cfg9346, Cfg9346_Lock);
2972
2973 RTL_R8(IntrMask);
2974
cdf1a608
FR		 2975 rtl_set_rx_mode(dev);
2976
0e485150
FR		 2977 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2978
cdf1a608 2979 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 2980
0e485150 2981 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 2982}
2983
2984static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2985{
2986 struct rtl8169_private *tp = netdev_priv(dev);
2987 int ret = 0;
2988
2989 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2990 return -EINVAL;
2991
2992 dev->mtu = new_mtu;
2993
2994 if (!netif_running(dev))
2995 goto out;
2996
2997 rtl8169_down(dev);
2998
2999 rtl8169_set_rxbufsize(tp, dev);
3000
3001 ret = rtl8169_init_ring(dev);
3002 if (ret < 0)
3003 goto out;
3004
bea3348e 3005 napi_enable(&tp->napi);
1da177e4 3006
07ce4064 3007 rtl_hw_start(dev);
1da177e4
LT		 3008
3009 rtl8169_request_timer(dev);
3010
3011out:
3012 return ret;
3013}
3014
3015static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
3016{
95e0918d 3017 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 3018 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
3019}
3020
3021static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
3022 struct sk_buff **sk_buff, struct RxDesc *desc)
3023{
3024 struct pci_dev *pdev = tp->pci_dev;
3025
3026 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
3027 PCI_DMA_FROMDEVICE);
3028 dev_kfree_skb(*sk_buff);
3029 *sk_buff = NULL;
3030 rtl8169_make_unusable_by_asic(desc);
3031}
3032
3033static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
3034{
3035 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3036
3037 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
3038}
3039
3040static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
3041 u32 rx_buf_sz)
3042{
3043 desc->addr = cpu_to_le64(mapping);
3044 wmb();
3045 rtl8169_mark_to_asic(desc, rx_buf_sz);
3046}
3047
15d31758
SH		 3048static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
3049 struct net_device *dev,
3050 struct RxDesc *desc, int rx_buf_sz,
3051 unsigned int align)
1da177e4
LT		 3052{
3053 struct sk_buff *skb;
3054 dma_addr_t mapping;
e9f63f30 3055 unsigned int pad;
1da177e4 3056
e9f63f30
FR		 3057 pad = align ? align : NET_IP_ALIGN;
3058
3059 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
1da177e4
LT		 3060 if (!skb)
3061 goto err_out;
3062
e9f63f30 3063 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
1da177e4 3064
689be439 3065 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
1da177e4
LT		 3066 PCI_DMA_FROMDEVICE);
3067
3068 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
1da177e4 3069out:
15d31758 3070 return skb;
1da177e4
LT		 3071
3072err_out:
1da177e4
LT		 3073 rtl8169_make_unusable_by_asic(desc);
3074 goto out;
3075}
3076
3077static void rtl8169_rx_clear(struct rtl8169_private *tp)
3078{
07d3f51f 3079 unsigned int i;
1da177e4
LT		 3080
3081 for (i = 0; i < NUM_RX_DESC; i++) {
3082 if (tp->Rx_skbuff[i]) {
3083 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
3084 tp->RxDescArray + i);
3085 }
3086 }
3087}
3088
3089static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
3090 u32 start, u32 end)
3091{
3092 u32 cur;
5b0384f4 3093
4ae47c2d 3094 for (cur = start; end - cur != 0; cur++) {
15d31758
SH		 3095 struct sk_buff *skb;
3096 unsigned int i = cur % NUM_RX_DESC;
1da177e4 3097
4ae47c2d
FR		 3098 WARN_ON((s32)(end - cur) < 0);
3099
1da177e4
LT		 3100 if (tp->Rx_skbuff[i])
3101 continue;
bcf0bf90 3102
15d31758
SH		 3103 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
3104 tp->RxDescArray + i,
3105 tp->rx_buf_sz, tp->align);
3106 if (!skb)
1da177e4 3107 break;
15d31758
SH		 3108
3109 tp->Rx_skbuff[i] = skb;
1da177e4
LT		 3110 }
3111 return cur - start;
3112}
3113
3114static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
3115{
3116 desc->opts1 |= cpu_to_le32(RingEnd);
3117}
3118
3119static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3120{
3121 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3122}
3123
3124static int rtl8169_init_ring(struct net_device *dev)
3125{
3126 struct rtl8169_private *tp = netdev_priv(dev);
3127
3128 rtl8169_init_ring_indexes(tp);
3129
3130 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
3131 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
3132
3133 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
3134 goto err_out;
3135
3136 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
3137
3138 return 0;
3139
3140err_out:
3141 rtl8169_rx_clear(tp);
3142 return -ENOMEM;
3143}
3144
3145static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
3146 struct TxDesc *desc)
3147{
3148 unsigned int len = tx_skb->len;
3149
3150 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
3151 desc->opts1 = 0x00;
3152 desc->opts2 = 0x00;
3153 desc->addr = 0x00;
3154 tx_skb->len = 0;
3155}
3156
3157static void rtl8169_tx_clear(struct rtl8169_private *tp)
3158{
3159 unsigned int i;
3160
3161 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
3162 unsigned int entry = i % NUM_TX_DESC;
3163 struct ring_info *tx_skb = tp->tx_skb + entry;
3164 unsigned int len = tx_skb->len;
3165
3166 if (len) {
3167 struct sk_buff *skb = tx_skb->skb;
3168
3169 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
3170 tp->TxDescArray + entry);
3171 if (skb) {
3172 dev_kfree_skb(skb);
3173 tx_skb->skb = NULL;
3174 }
cebf8cc7 3175 tp->dev->stats.tx_dropped++;
1da177e4
LT		 3176 }
3177 }
3178 tp->cur_tx = tp->dirty_tx = 0;
3179}
3180
c4028958 3181static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 3182{
3183 struct rtl8169_private *tp = netdev_priv(dev);
3184
c4028958 3185 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 3186 schedule_delayed_work(&tp->task, 4);
3187}
3188
3189static void rtl8169_wait_for_quiescence(struct net_device *dev)
3190{
3191 struct rtl8169_private *tp = netdev_priv(dev);
3192 void __iomem *ioaddr = tp->mmio_addr;
3193
3194 synchronize_irq(dev->irq);
3195
3196 /* Wait for any pending NAPI task to complete */
bea3348e 3197 napi_disable(&tp->napi);
1da177e4
LT		 3198
3199 rtl8169_irq_mask_and_ack(ioaddr);
3200
d1d08d12
DM		 3201 tp->intr_mask = 0xffff;
3202 RTL_W16(IntrMask, tp->intr_event);
bea3348e 3203 napi_enable(&tp->napi);
1da177e4
LT		 3204}
3205
c4028958 3206static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 3207{
c4028958
DH		 3208 struct rtl8169_private *tp =
3209 container_of(work, struct rtl8169_private, task.work);
3210 struct net_device *dev = tp->dev;
1da177e4
LT		 3211 int ret;
3212
eb2a021c
FR		 3213 rtnl_lock();
3214
3215 if (!netif_running(dev))
3216 goto out_unlock;
3217
3218 rtl8169_wait_for_quiescence(dev);
3219 rtl8169_close(dev);
1da177e4
LT		 3220
3221 ret = rtl8169_open(dev);
3222 if (unlikely(ret < 0)) {
07d3f51f 3223 if (net_ratelimit() && netif_msg_drv(tp)) {
53edbecd 3224 printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
07d3f51f 3225 " Rescheduling.\n", dev->name, ret);
1da177e4
LT		 3226 }
3227 rtl8169_schedule_work(dev, rtl8169_reinit_task);
3228 }
eb2a021c
FR		 3229
3230out_unlock:
3231 rtnl_unlock();
1da177e4
LT		 3232}
3233
c4028958 3234static void rtl8169_reset_task(struct work_struct *work)
1da177e4 3235{
c4028958
DH		 3236 struct rtl8169_private *tp =
3237 container_of(work, struct rtl8169_private, task.work);
3238 struct net_device *dev = tp->dev;
1da177e4 3239
eb2a021c
FR		 3240 rtnl_lock();
3241
1da177e4 3242 if (!netif_running(dev))
eb2a021c 3243 goto out_unlock;
1da177e4
LT		 3244
3245 rtl8169_wait_for_quiescence(dev);
3246
bea3348e 3247 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
1da177e4
LT		 3248 rtl8169_tx_clear(tp);
3249
3250 if (tp->dirty_rx == tp->cur_rx) {
3251 rtl8169_init_ring_indexes(tp);
07ce4064 3252 rtl_hw_start(dev);
1da177e4 3253 netif_wake_queue(dev);
cebf8cc7 3254 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4 3255 } else {
07d3f51f 3256 if (net_ratelimit() && netif_msg_intr(tp)) {
53edbecd 3257 printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
07d3f51f 3258 dev->name);
1da177e4
LT		 3259 }
3260 rtl8169_schedule_work(dev, rtl8169_reset_task);
3261 }
eb2a021c
FR		 3262
3263out_unlock:
3264 rtnl_unlock();
1da177e4
LT		 3265}
3266
3267static void rtl8169_tx_timeout(struct net_device *dev)
3268{
3269 struct rtl8169_private *tp = netdev_priv(dev);
3270
3271 rtl8169_hw_reset(tp->mmio_addr);
3272
3273 /* Let's wait a bit while any (async) irq lands on */
3274 rtl8169_schedule_work(dev, rtl8169_reset_task);
3275}
3276
3277static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
3278 u32 opts1)
3279{
3280 struct skb_shared_info *info = skb_shinfo(skb);
3281 unsigned int cur_frag, entry;
a6343afb 3282 struct TxDesc * uninitialized_var(txd);
1da177e4
LT		 3283
3284 entry = tp->cur_tx;
3285 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
3286 skb_frag_t *frag = info->frags + cur_frag;
3287 dma_addr_t mapping;
3288 u32 status, len;
3289 void *addr;
3290
3291 entry = (entry + 1) % NUM_TX_DESC;
3292
3293 txd = tp->TxDescArray + entry;
3294 len = frag->size;
3295 addr = ((void *) page_address(frag->page)) + frag->page_offset;
3296 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
3297
3298 /* anti gcc 2.95.3 bugware (sic) */
3299 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
3300
3301 txd->opts1 = cpu_to_le32(status);
3302 txd->addr = cpu_to_le64(mapping);
3303
3304 tp->tx_skb[entry].len = len;
3305 }
3306
3307 if (cur_frag) {
3308 tp->tx_skb[entry].skb = skb;
3309 txd->opts1 |= cpu_to_le32(LastFrag);
3310 }
3311
3312 return cur_frag;
3313}
3314
3315static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
3316{
3317 if (dev->features & NETIF_F_TSO) {
7967168c 3318 u32 mss = skb_shinfo(skb)->gso_size;
1da177e4
LT		 3319
3320 if (mss)
3321 return LargeSend | ((mss & MSSMask) << MSSShift);
3322 }
84fa7933 3323 if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 3324 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 3325
3326 if (ip->protocol == IPPROTO_TCP)
3327 return IPCS | TCPCS;
3328 else if (ip->protocol == IPPROTO_UDP)
3329 return IPCS | UDPCS;
3330 WARN_ON(1); /* we need a WARN() */
3331 }
3332 return 0;
3333}
3334
3335static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
3336{
3337 struct rtl8169_private *tp = netdev_priv(dev);
3338 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
3339 struct TxDesc *txd = tp->TxDescArray + entry;
3340 void __iomem *ioaddr = tp->mmio_addr;
3341 dma_addr_t mapping;
3342 u32 status, len;
3343 u32 opts1;
188f4af0 3344 int ret = NETDEV_TX_OK;
5b0384f4 3345
1da177e4 3346 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
b57b7e5a
SH		 3347 if (netif_msg_drv(tp)) {
3348 printk(KERN_ERR
3349 "%s: BUG! Tx Ring full when queue awake!\n",
3350 dev->name);
3351 }
1da177e4
LT		 3352 goto err_stop;
3353 }
3354
3355 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3356 goto err_stop;
3357
3358 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
3359
3360 frags = rtl8169_xmit_frags(tp, skb, opts1);
3361 if (frags) {
3362 len = skb_headlen(skb);
3363 opts1 |= FirstFrag;
3364 } else {
3365 len = skb->len;
1da177e4
LT		 3366 opts1 |= FirstFrag | LastFrag;
3367 tp->tx_skb[entry].skb = skb;
3368 }
3369
3370 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
3371
3372 tp->tx_skb[entry].len = len;
3373 txd->addr = cpu_to_le64(mapping);
3374 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
3375
3376 wmb();
3377
3378 /* anti gcc 2.95.3 bugware (sic) */
3379 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
3380 txd->opts1 = cpu_to_le32(status);
3381
3382 dev->trans_start = jiffies;
3383
3384 tp->cur_tx += frags + 1;
3385
3386 smp_wmb();
3387
275391a4 3388 RTL_W8(TxPoll, NPQ); /* set polling bit */
1da177e4
LT		 3389
3390 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
3391 netif_stop_queue(dev);
3392 smp_rmb();
3393 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
3394 netif_wake_queue(dev);
3395 }
3396
3397out:
3398 return ret;
3399
3400err_stop:
3401 netif_stop_queue(dev);
188f4af0 3402 ret = NETDEV_TX_BUSY;
cebf8cc7 3403 dev->stats.tx_dropped++;
1da177e4
LT		 3404 goto out;
3405}
3406
3407static void rtl8169_pcierr_interrupt(struct net_device *dev)
3408{
3409 struct rtl8169_private *tp = netdev_priv(dev);
3410 struct pci_dev *pdev = tp->pci_dev;
3411 void __iomem *ioaddr = tp->mmio_addr;
3412 u16 pci_status, pci_cmd;
3413
3414 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3415 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
3416
b57b7e5a
SH		 3417 if (netif_msg_intr(tp)) {
3418 printk(KERN_ERR
3419 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
3420 dev->name, pci_cmd, pci_status);
3421 }
1da177e4
LT		 3422
3423 /*
3424 * The recovery sequence below admits a very elaborated explanation:
3425 * - it seems to work;
d03902b8
FR		 3426 * - I did not see what else could be done;
3427 * - it makes iop3xx happy.
1da177e4
LT		 3428 *
3429 * Feel free to adjust to your needs.
3430 */
a27993f3 3431 if (pdev->broken_parity_status)
d03902b8
FR		 3432 pci_cmd &= ~PCI_COMMAND_PARITY;
3433 else
3434 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
3435
3436 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 3437
3438 pci_write_config_word(pdev, PCI_STATUS,
3439 pci_status & (PCI_STATUS_DETECTED_PARITY |
3440 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
3441 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
3442
3443 /* The infamous DAC f*ckup only happens at boot time */
3444 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
b57b7e5a
SH		 3445 if (netif_msg_intr(tp))
3446 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
1da177e4
LT		 3447 tp->cp_cmd &= ~PCIDAC;
3448 RTL_W16(CPlusCmd, tp->cp_cmd);
3449 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 3450 }
3451
3452 rtl8169_hw_reset(ioaddr);
d03902b8
FR		 3453
3454 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 3455}
3456
07d3f51f
FR		 3457static void rtl8169_tx_interrupt(struct net_device *dev,
3458 struct rtl8169_private *tp,
3459 void __iomem *ioaddr)
1da177e4
LT		 3460{
3461 unsigned int dirty_tx, tx_left;
3462
1da177e4
LT		 3463 dirty_tx = tp->dirty_tx;
3464 smp_rmb();
3465 tx_left = tp->cur_tx - dirty_tx;
3466
3467 while (tx_left > 0) {
3468 unsigned int entry = dirty_tx % NUM_TX_DESC;
3469 struct ring_info *tx_skb = tp->tx_skb + entry;
3470 u32 len = tx_skb->len;
3471 u32 status;
3472
3473 rmb();
3474 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
3475 if (status & DescOwn)
3476 break;
3477
cebf8cc7
FR		 3478 dev->stats.tx_bytes += len;
3479 dev->stats.tx_packets++;
1da177e4
LT		 3480
3481 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
3482
3483 if (status & LastFrag) {
3484 dev_kfree_skb_irq(tx_skb->skb);
3485 tx_skb->skb = NULL;
3486 }
3487 dirty_tx++;
3488 tx_left--;
3489 }
3490
3491 if (tp->dirty_tx != dirty_tx) {
3492 tp->dirty_tx = dirty_tx;
3493 smp_wmb();
3494 if (netif_queue_stopped(dev) &&
3495 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
3496 netif_wake_queue(dev);
3497 }
d78ae2dc
FR		 3498 /*
3499 * 8168 hack: TxPoll requests are lost when the Tx packets are
3500 * too close. Let's kick an extra TxPoll request when a burst
3501 * of start_xmit activity is detected (if it is not detected,
3502 * it is slow enough). -- FR
3503 */
3504 smp_rmb();
3505 if (tp->cur_tx != dirty_tx)
3506 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 3507 }
3508}
3509
126fa4b9
FR		 3510static inline int rtl8169_fragmented_frame(u32 status)
3511{
3512 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
3513}
3514
1da177e4
LT		 3515static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
3516{
3517 u32 opts1 = le32_to_cpu(desc->opts1);
3518 u32 status = opts1 & RxProtoMask;
3519
3520 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
3521 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
3522 ((status == RxProtoIP) && !(opts1 & IPFail)))
3523 skb->ip_summed = CHECKSUM_UNNECESSARY;
3524 else
3525 skb->ip_summed = CHECKSUM_NONE;
3526}
3527
07d3f51f
FR		 3528static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
3529 struct rtl8169_private *tp, int pkt_size,
3530 dma_addr_t addr)
1da177e4 3531{
b449655f
SH		 3532 struct sk_buff *skb;
3533 bool done = false;
1da177e4 3534
b449655f
SH		 3535 if (pkt_size >= rx_copybreak)
3536 goto out;
1da177e4 3537
07d3f51f 3538 skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
b449655f
SH		 3539 if (!skb)
3540 goto out;
3541
07d3f51f
FR		 3542 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
3543 PCI_DMA_FROMDEVICE);
86402234 3544 skb_reserve(skb, NET_IP_ALIGN);
b449655f
SH		 3545 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
3546 *sk_buff = skb;
3547 done = true;
3548out:
3549 return done;
1da177e4
LT		 3550}
3551
07d3f51f
FR		 3552static int rtl8169_rx_interrupt(struct net_device *dev,
3553 struct rtl8169_private *tp,
bea3348e 3554 void __iomem *ioaddr, u32 budget)
1da177e4
LT		 3555{
3556 unsigned int cur_rx, rx_left;
3557 unsigned int delta, count;
3558
1da177e4
LT		 3559 cur_rx = tp->cur_rx;
3560 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 3561 rx_left = min(rx_left, budget);
1da177e4 3562
4dcb7d33 3563 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 3564 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 3565 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 3566 u32 status;
3567
3568 rmb();
126fa4b9 3569 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 3570
3571 if (status & DescOwn)
3572 break;
4dcb7d33 3573 if (unlikely(status & RxRES)) {
b57b7e5a
SH		 3574 if (netif_msg_rx_err(tp)) {
3575 printk(KERN_INFO
3576 "%s: Rx ERROR. status = %08x\n",
3577 dev->name, status);
3578 }
cebf8cc7 3579 dev->stats.rx_errors++;
1da177e4 3580 if (status & (RxRWT | RxRUNT))
cebf8cc7 3581 dev->stats.rx_length_errors++;
1da177e4 3582 if (status & RxCRC)
cebf8cc7 3583 dev->stats.rx_crc_errors++;
9dccf611
FR		 3584 if (status & RxFOVF) {
3585 rtl8169_schedule_work(dev, rtl8169_reset_task);
cebf8cc7 3586 dev->stats.rx_fifo_errors++;
9dccf611 3587 }
126fa4b9 3588 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
1da177e4 3589 } else {
1da177e4 3590 struct sk_buff *skb = tp->Rx_skbuff[entry];
b449655f 3591 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 3592 int pkt_size = (status & 0x00001FFF) - 4;
b449655f 3593 struct pci_dev *pdev = tp->pci_dev;
1da177e4 3594
126fa4b9
FR		 3595 /*
3596 * The driver does not support incoming fragmented
3597 * frames. They are seen as a symptom of over-mtu
3598 * sized frames.
3599 */
3600 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 3601 dev->stats.rx_dropped++;
3602 dev->stats.rx_length_errors++;
126fa4b9 3603 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4dcb7d33 3604 continue;
126fa4b9
FR		 3605 }
3606
1da177e4 3607 rtl8169_rx_csum(skb, desc);
bcf0bf90 3608
07d3f51f 3609 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
b449655f
SH		 3610 pci_dma_sync_single_for_device(pdev, addr,
3611 pkt_size, PCI_DMA_FROMDEVICE);
3612 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3613 } else {
a866bbf6 3614 pci_unmap_single(pdev, addr, tp->rx_buf_sz,
b449655f 3615 PCI_DMA_FROMDEVICE);
1da177e4
LT		 3616 tp->Rx_skbuff[entry] = NULL;
3617 }
3618
1da177e4
LT		 3619 skb_put(skb, pkt_size);
3620 skb->protocol = eth_type_trans(skb, dev);
3621
3622 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
865c652d 3623 netif_receive_skb(skb);
1da177e4 3624
cebf8cc7
FR		 3625 dev->stats.rx_bytes += pkt_size;
3626 dev->stats.rx_packets++;
1da177e4 3627 }
6dccd16b
FR		 3628
3629 /* Work around for AMD plateform. */
95e0918d 3630 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 3631 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
3632 desc->opts2 = 0;
3633 cur_rx++;
3634 }
1da177e4
LT		 3635 }
3636
3637 count = cur_rx - tp->cur_rx;
3638 tp->cur_rx = cur_rx;
3639
3640 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
b57b7e5a 3641 if (!delta && count && netif_msg_intr(tp))
1da177e4
LT		 3642 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
3643 tp->dirty_rx += delta;
3644
3645 /*
3646 * FIXME: until there is periodic timer to try and refill the ring,
3647 * a temporary shortage may definitely kill the Rx process.
3648 * - disable the asic to try and avoid an overflow and kick it again
3649 * after refill ?
3650 * - how do others driver handle this condition (Uh oh...).
3651 */
b57b7e5a 3652 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
1da177e4
LT		 3653 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
3654
3655 return count;
3656}
3657
07d3f51f 3658static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 3659{
07d3f51f 3660 struct net_device *dev = dev_instance;
1da177e4 3661 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 3662 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 3663 int handled = 0;
865c652d 3664 int status;
1da177e4 3665
865c652d 3666 status = RTL_R16(IntrStatus);
1da177e4 3667
865c652d
FR		 3668 /* hotplug/major error/no more work/shared irq */
3669 if ((status == 0xffff) || !status)
3670 goto out;
1da177e4 3671
865c652d 3672 handled = 1;
1da177e4 3673
865c652d
FR		 3674 if (unlikely(!netif_running(dev))) {
3675 rtl8169_asic_down(ioaddr);
3676 goto out;
3677 }
1da177e4 3678
865c652d
FR		 3679 status &= tp->intr_mask;
3680 RTL_W16(IntrStatus,
3681 (status & RxFIFOOver) ? (status | RxOverflow) : status);
1da177e4 3682
865c652d
FR		 3683 if (!(status & tp->intr_event))
3684 goto out;
0e485150 3685
865c652d
FR		 3686 /* Work around for rx fifo overflow */
3687 if (unlikely(status & RxFIFOOver) &&
3688 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
3689 netif_stop_queue(dev);
3690 rtl8169_tx_timeout(dev);
3691 goto out;
3692 }
1da177e4 3693
865c652d
FR		 3694 if (unlikely(status & SYSErr)) {
3695 rtl8169_pcierr_interrupt(dev);
3696 goto out;
3697 }
1da177e4 3698
865c652d
FR		 3699 if (status & LinkChg)
3700 rtl8169_check_link_status(dev, tp, ioaddr);
1da177e4 3701
865c652d
FR		 3702 if (status & tp->napi_event) {
3703 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
3704 tp->intr_mask = ~tp->napi_event;
313b0305 3705
908a7a16
NH		 3706 if (likely(netif_rx_schedule_prep(&tp->napi)))
3707 __netif_rx_schedule(&tp->napi);
865c652d
FR		 3708 else if (netif_msg_intr(tp)) {
3709 printk(KERN_INFO "%s: interrupt %04x in poll\n",
3710 dev->name, status);
b57b7e5a 3711 }
1da177e4
LT		 3712 }
3713out:
3714 return IRQ_RETVAL(handled);
3715}
3716
bea3348e 3717static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 3718{
bea3348e
SH		 3719 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
3720 struct net_device *dev = tp->dev;
1da177e4 3721 void __iomem *ioaddr = tp->mmio_addr;
bea3348e 3722 int work_done;
1da177e4 3723
bea3348e 3724 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
1da177e4
LT		 3725 rtl8169_tx_interrupt(dev, tp, ioaddr);
3726
bea3348e 3727 if (work_done < budget) {
908a7a16 3728 netif_rx_complete(napi);
1da177e4
LT		 3729 tp->intr_mask = 0xffff;
3730 /*
3731 * 20040426: the barrier is not strictly required but the
3732 * behavior of the irq handler could be less predictable
3733 * without it. Btw, the lack of flush for the posted pci
3734 * write is safe - FR
3735 */
3736 smp_wmb();
0e485150 3737 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 3738 }
3739
bea3348e 3740 return work_done;
1da177e4 3741}
1da177e4 3742
523a6094
FR		 3743static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
3744{
3745 struct rtl8169_private *tp = netdev_priv(dev);
3746
3747 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
3748 return;
3749
3750 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
3751 RTL_W32(RxMissed, 0);
3752}
3753
1da177e4
LT		 3754static void rtl8169_down(struct net_device *dev)
3755{
3756 struct rtl8169_private *tp = netdev_priv(dev);
3757 void __iomem *ioaddr = tp->mmio_addr;
733b736c 3758 unsigned int intrmask;
1da177e4
LT		 3759
3760 rtl8169_delete_timer(dev);
3761
3762 netif_stop_queue(dev);
3763
93dd79e8 3764 napi_disable(&tp->napi);
93dd79e8 3765
1da177e4
LT		 3766core_down:
3767 spin_lock_irq(&tp->lock);
3768
3769 rtl8169_asic_down(ioaddr);
3770
523a6094 3771 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 3772
3773 spin_unlock_irq(&tp->lock);
3774
3775 synchronize_irq(dev->irq);
3776
1da177e4 3777 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 3778 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4
LT		 3779
3780 /*
3781 * And now for the 50k$ question: are IRQ disabled or not ?
3782 *
3783 * Two paths lead here:
3784 * 1) dev->close
3785 * -> netif_running() is available to sync the current code and the
3786 * IRQ handler. See rtl8169_interrupt for details.
3787 * 2) dev->change_mtu
3788 * -> rtl8169_poll can not be issued again and re-enable the
3789 * interruptions. Let's simply issue the IRQ down sequence again.
733b736c
AP		 3790 *
3791 * No loop if hotpluged or major error (0xffff).
1da177e4 3792 */
733b736c
AP		 3793 intrmask = RTL_R16(IntrMask);
3794 if (intrmask && (intrmask != 0xffff))
1da177e4
LT		 3795 goto core_down;
3796
3797 rtl8169_tx_clear(tp);
3798
3799 rtl8169_rx_clear(tp);
3800}
3801
3802static int rtl8169_close(struct net_device *dev)
3803{
3804 struct rtl8169_private *tp = netdev_priv(dev);
3805 struct pci_dev *pdev = tp->pci_dev;
3806
355423d0
IV		 3807 /* update counters before going down */
3808 rtl8169_update_counters(dev);
3809
1da177e4
LT		 3810 rtl8169_down(dev);
3811
3812 free_irq(dev->irq, dev);
3813
1da177e4
LT		 3814 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3815 tp->RxPhyAddr);
3816 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3817 tp->TxPhyAddr);
3818 tp->TxDescArray = NULL;
3819 tp->RxDescArray = NULL;
3820
3821 return 0;
3822}
3823
07ce4064 3824static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 3825{
3826 struct rtl8169_private *tp = netdev_priv(dev);
3827 void __iomem *ioaddr = tp->mmio_addr;
3828 unsigned long flags;
3829 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 3830 int rx_mode;
1da177e4
LT		 3831 u32 tmp = 0;
3832
3833 if (dev->flags & IFF_PROMISC) {
3834 /* Unconditionally log net taps. */
b57b7e5a
SH		 3835 if (netif_msg_link(tp)) {
3836 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
3837 dev->name);
3838 }
1da177e4
LT		 3839 rx_mode =
3840 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
3841 AcceptAllPhys;
3842 mc_filter[1] = mc_filter[0] = 0xffffffff;
3843 } else if ((dev->mc_count > multicast_filter_limit)
3844 || (dev->flags & IFF_ALLMULTI)) {
3845 /* Too many to filter perfectly -- accept all multicasts. */
3846 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
3847 mc_filter[1] = mc_filter[0] = 0xffffffff;
3848 } else {
3849 struct dev_mc_list *mclist;
07d3f51f
FR		 3850 unsigned int i;
3851
1da177e4
LT		 3852 rx_mode = AcceptBroadcast | AcceptMyPhys;
3853 mc_filter[1] = mc_filter[0] = 0;
3854 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3855 i++, mclist = mclist->next) {
3856 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
3857 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
3858 rx_mode |= AcceptMulticast;
3859 }
3860 }
3861
3862 spin_lock_irqsave(&tp->lock, flags);
3863
3864 tmp = rtl8169_rx_config | rx_mode |
3865 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3866
f887cce8 3867 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
1087f4f4
FR		 3868 u32 data = mc_filter[0];
3869
3870 mc_filter[0] = swab32(mc_filter[1]);
3871 mc_filter[1] = swab32(data);
bcf0bf90
FR		 3872 }
3873
1da177e4
LT		 3874 RTL_W32(MAR0 + 0, mc_filter[0]);
3875 RTL_W32(MAR0 + 4, mc_filter[1]);
3876
57a9f236
FR		 3877 RTL_W32(RxConfig, tmp);
3878
1da177e4
LT		 3879 spin_unlock_irqrestore(&tp->lock, flags);
3880}
3881
3882/**
3883 * rtl8169_get_stats - Get rtl8169 read/write statistics
3884 * @dev: The Ethernet Device to get statistics for
3885 *
3886 * Get TX/RX statistics for rtl8169
3887 */
3888static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3889{
3890 struct rtl8169_private *tp = netdev_priv(dev);
3891 void __iomem *ioaddr = tp->mmio_addr;
3892 unsigned long flags;
3893
3894 if (netif_running(dev)) {
3895 spin_lock_irqsave(&tp->lock, flags);
523a6094 3896 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 3897 spin_unlock_irqrestore(&tp->lock, flags);
3898 }
5b0384f4 3899
cebf8cc7 3900 return &dev->stats;
1da177e4
LT		 3901}
3902
5d06a99f
FR		 3903#ifdef CONFIG_PM
3904
3905static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
3906{
3907 struct net_device *dev = pci_get_drvdata(pdev);
3908 struct rtl8169_private *tp = netdev_priv(dev);
3909 void __iomem *ioaddr = tp->mmio_addr;
3910
3911 if (!netif_running(dev))
1371fa6d 3912 goto out_pci_suspend;
5d06a99f
FR		 3913
3914 netif_device_detach(dev);
3915 netif_stop_queue(dev);
3916
3917 spin_lock_irq(&tp->lock);
3918
3919 rtl8169_asic_down(ioaddr);
3920
523a6094 3921 rtl8169_rx_missed(dev, ioaddr);
5d06a99f
FR		 3922
3923 spin_unlock_irq(&tp->lock);
3924
1371fa6d 3925out_pci_suspend:
5d06a99f 3926 pci_save_state(pdev);
f23e7fda
FR		 3927 pci_enable_wake(pdev, pci_choose_state(pdev, state),
3928 (tp->features & RTL_FEATURE_WOL) ? 1 : 0);
5d06a99f 3929 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1371fa6d 3930
5d06a99f
FR		 3931 return 0;
3932}
3933
3934static int rtl8169_resume(struct pci_dev *pdev)
3935{
3936 struct net_device *dev = pci_get_drvdata(pdev);
3937
1371fa6d
FR		 3938 pci_set_power_state(pdev, PCI_D0);
3939 pci_restore_state(pdev);
3940 pci_enable_wake(pdev, PCI_D0, 0);
3941
5d06a99f
FR		 3942 if (!netif_running(dev))
3943 goto out;
3944
3945 netif_device_attach(dev);
3946
5d06a99f
FR		 3947 rtl8169_schedule_work(dev, rtl8169_reset_task);
3948out:
3949 return 0;
3950}
3951
1765f95d
FR		 3952static void rtl_shutdown(struct pci_dev *pdev)
3953{
3954 rtl8169_suspend(pdev, PMSG_SUSPEND);
3955}
3956
5d06a99f
FR		 3957#endif /* CONFIG_PM */
3958
1da177e4
LT		 3959static struct pci_driver rtl8169_pci_driver = {
3960 .name = MODULENAME,
3961 .id_table = rtl8169_pci_tbl,
3962 .probe = rtl8169_init_one,
3963 .remove = __devexit_p(rtl8169_remove_one),
3964#ifdef CONFIG_PM
3965 .suspend = rtl8169_suspend,
3966 .resume = rtl8169_resume,
1765f95d 3967 .shutdown = rtl_shutdown,
1da177e4
LT		 3968#endif
3969};
3970
07d3f51f 3971static int __init rtl8169_init_module(void)
1da177e4 3972{
29917620 3973 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 3974}
3975
07d3f51f 3976static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 3977{
3978 pci_unregister_driver(&rtl8169_pci_driver);
3979}
3980
3981module_init(rtl8169_init_module);
3982module_exit(rtl8169_cleanup_module);
Linux 6.x block layer and io_uring tree(s)