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r8169: confusion between hardware and IP header alignment
[linux-2.6-block.git] / drivers / net / r8169.c
CommitLineData
1da177e4
LT		 1/*
2=========================================================================
3 r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver for Linux kernel 2.4.x.
4 --------------------------------------------------------------------
5
6 History:
7 Feb 4 2002 - created initially by ShuChen <shuchen@realtek.com.tw>.
8 May 20 2002 - Add link status force-mode and TBI mode support.
5b0384f4 9 2004 - Massive updates. See kernel SCM system for details.
1da177e4
LT		 10=========================================================================
11 1. [DEPRECATED: use ethtool instead] The media can be forced in 5 modes.
12 Command: 'insmod r8169 media = SET_MEDIA'
13 Ex: 'insmod r8169 media = 0x04' will force PHY to operate in 100Mpbs Half-duplex.
5b0384f4 14
1da177e4
LT		 15 SET_MEDIA can be:
16 _10_Half = 0x01
17 _10_Full = 0x02
18 _100_Half = 0x04
19 _100_Full = 0x08
20 _1000_Full = 0x10
5b0384f4 21
1da177e4
LT		 22 2. Support TBI mode.
23=========================================================================
24VERSION 1.1 <2002/10/4>
25
26 The bit4:0 of MII register 4 is called "selector field", and have to be
27 00001b to indicate support of IEEE std 802.3 during NWay process of
5b0384f4 28 exchanging Link Code Word (FLP).
1da177e4
LT		 29
30VERSION 1.2 <2002/11/30>
31
32 - Large style cleanup
33 - Use ether_crc in stock kernel (linux/crc32.h)
34 - Copy mc_filter setup code from 8139cp
35 (includes an optimization, and avoids set_bit use)
36
37VERSION 1.6LK <2004/04/14>
38
39 - Merge of Realtek's version 1.6
40 - Conversion to DMA API
41 - Suspend/resume
42 - Endianness
43 - Misc Rx/Tx bugs
44
45VERSION 2.2LK <2005/01/25>
46
47 - RX csum, TX csum/SG, TSO
48 - VLAN
49 - baby (< 7200) Jumbo frames support
50 - Merge of Realtek's version 2.2 (new phy)
51 */
52
53#include <linux/module.h>
54#include <linux/moduleparam.h>
55#include <linux/pci.h>
56#include <linux/netdevice.h>
57#include <linux/etherdevice.h>
58#include <linux/delay.h>
59#include <linux/ethtool.h>
60#include <linux/mii.h>
61#include <linux/if_vlan.h>
62#include <linux/crc32.h>
63#include <linux/in.h>
64#include <linux/ip.h>
65#include <linux/tcp.h>
66#include <linux/init.h>
67#include <linux/dma-mapping.h>
68
99f252b0 69#include <asm/system.h>
1da177e4
LT		 70#include <asm/io.h>
71#include <asm/irq.h>
72
f7ccf420
SH		 73#ifdef CONFIG_R8169_NAPI
74#define NAPI_SUFFIX "-NAPI"
75#else
76#define NAPI_SUFFIX ""
77#endif
78
79#define RTL8169_VERSION "2.2LK" NAPI_SUFFIX
1da177e4
LT		 80#define MODULENAME "r8169"
81#define PFX MODULENAME ": "
82
83#ifdef RTL8169_DEBUG
84#define assert(expr) \
5b0384f4
FR		 85 if (!(expr)) { \
86 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
87 #expr,__FILE__,__FUNCTION__,__LINE__); \
88 }
1da177e4
LT		 89#define dprintk(fmt, args...) do { printk(PFX fmt, ## args); } while (0)
90#else
91#define assert(expr) do {} while (0)
92#define dprintk(fmt, args...) do {} while (0)
93#endif /* RTL8169_DEBUG */
94
b57b7e5a 95#define R8169_MSG_DEFAULT \
f0e837d9 96 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 97
1da177e4
LT		 98#define TX_BUFFS_AVAIL(tp) \
99 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
100
101#ifdef CONFIG_R8169_NAPI
102#define rtl8169_rx_skb netif_receive_skb
0b50f81d 103#define rtl8169_rx_hwaccel_skb vlan_hwaccel_receive_skb
1da177e4
LT		 104#define rtl8169_rx_quota(count, quota) min(count, quota)
105#else
106#define rtl8169_rx_skb netif_rx
0b50f81d 107#define rtl8169_rx_hwaccel_skb vlan_hwaccel_rx
1da177e4
LT		 108#define rtl8169_rx_quota(count, quota) count
109#endif
110
111/* media options */
112#define MAX_UNITS 8
113static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
114static int num_media = 0;
115
116/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
f71e1309 117static const int max_interrupt_work = 20;
1da177e4
LT		 118
119/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
120 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 121static const int multicast_filter_limit = 32;
1da177e4
LT		 122
123/* MAC address length */
124#define MAC_ADDR_LEN 6
125
126#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
127#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
128#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
129#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
130#define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
131#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
132#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
133
134#define R8169_REGS_SIZE 256
135#define R8169_NAPI_WEIGHT 64
136#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
137#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
138#define RX_BUF_SIZE 1536 /* Rx Buffer size */
139#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
140#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
141
142#define RTL8169_TX_TIMEOUT (6*HZ)
143#define RTL8169_PHY_TIMEOUT (10*HZ)
144
145/* write/read MMIO register */
146#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
147#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
148#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
149#define RTL_R8(reg) readb (ioaddr + (reg))
150#define RTL_R16(reg) readw (ioaddr + (reg))
151#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
152
153enum mac_version {
ba6eb6ee
FR		 154 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
155 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
156 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
157 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
158 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
6dccd16b 159 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
2dd99530
FR		 160 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
161 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be 8168Bf
cdf1a608
FR		 162 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb 8101Ec
163 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101
164 RTL_GIGA_MAC_VER_15 = 0x0f // 8101
1da177e4
LT		 165};
166
167enum phy_version {
168 RTL_GIGA_PHY_VER_C = 0x03, /* PHY Reg 0x03 bit0-3 == 0x0000 */
169 RTL_GIGA_PHY_VER_D = 0x04, /* PHY Reg 0x03 bit0-3 == 0x0000 */
170 RTL_GIGA_PHY_VER_E = 0x05, /* PHY Reg 0x03 bit0-3 == 0x0000 */
171 RTL_GIGA_PHY_VER_F = 0x06, /* PHY Reg 0x03 bit0-3 == 0x0001 */
172 RTL_GIGA_PHY_VER_G = 0x07, /* PHY Reg 0x03 bit0-3 == 0x0002 */
173 RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */
174};
175
1da177e4
LT		 176#define _R(NAME,MAC,MASK) \
177 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
178
3c6bee1d 179static const struct {
1da177e4
LT		 180 const char *name;
181 u8 mac_version;
182 u32 RxConfigMask; /* Clears the bits supported by this chip */
183} rtl_chip_info[] = {
ba6eb6ee
FR		 184 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
185 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
186 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
187 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
188 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
6dccd16b 189 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
bcf0bf90
FR		 190 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
191 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
192 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
193 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
194 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880) // PCI-E 8139
1da177e4
LT		 195};
196#undef _R
197
bcf0bf90
FR		 198enum cfg_version {
199 RTL_CFG_0 = 0x00,
200 RTL_CFG_1,
201 RTL_CFG_2
202};
203
07ce4064
FR		 204static void rtl_hw_start_8169(struct net_device *);
205static void rtl_hw_start_8168(struct net_device *);
206static void rtl_hw_start_8101(struct net_device *);
207
1da177e4 208static struct pci_device_id rtl8169_pci_tbl[] = {
bcf0bf90 209 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 210 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 211 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 212 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 213 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
214 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
73f5e28b 215 { PCI_DEVICE(0x1259, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 216 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
217 { PCI_VENDOR_ID_LINKSYS, 0x1032,
218 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
1da177e4
LT		 219 {0,},
220};
221
222MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
223
224static int rx_copybreak = 200;
225static int use_dac;
b57b7e5a
SH		 226static struct {
227 u32 msg_enable;
228} debug = { -1 };
1da177e4
LT		 229
230enum RTL8169_registers {
231 MAC0 = 0, /* Ethernet hardware address. */
232 MAR0 = 8, /* Multicast filter. */
d4a3a0fc
SH		 233 CounterAddrLow = 0x10,
234 CounterAddrHigh = 0x14,
1da177e4
LT		 235 TxDescStartAddrLow = 0x20,
236 TxDescStartAddrHigh = 0x24,
237 TxHDescStartAddrLow = 0x28,
238 TxHDescStartAddrHigh = 0x2c,
239 FLASH = 0x30,
240 ERSR = 0x36,
241 ChipCmd = 0x37,
242 TxPoll = 0x38,
243 IntrMask = 0x3C,
244 IntrStatus = 0x3E,
245 TxConfig = 0x40,
246 RxConfig = 0x44,
247 RxMissed = 0x4C,
248 Cfg9346 = 0x50,
249 Config0 = 0x51,
250 Config1 = 0x52,
251 Config2 = 0x53,
252 Config3 = 0x54,
253 Config4 = 0x55,
254 Config5 = 0x56,
255 MultiIntr = 0x5C,
256 PHYAR = 0x60,
257 TBICSR = 0x64,
258 TBI_ANAR = 0x68,
259 TBI_LPAR = 0x6A,
260 PHYstatus = 0x6C,
261 RxMaxSize = 0xDA,
262 CPlusCmd = 0xE0,
263 IntrMitigate = 0xE2,
264 RxDescAddrLow = 0xE4,
265 RxDescAddrHigh = 0xE8,
266 EarlyTxThres = 0xEC,
267 FuncEvent = 0xF0,
268 FuncEventMask = 0xF4,
269 FuncPresetState = 0xF8,
270 FuncForceEvent = 0xFC,
271};
272
273enum RTL8169_register_content {
274 /* InterruptStatusBits */
275 SYSErr = 0x8000,
276 PCSTimeout = 0x4000,
277 SWInt = 0x0100,
278 TxDescUnavail = 0x80,
279 RxFIFOOver = 0x40,
280 LinkChg = 0x20,
281 RxOverflow = 0x10,
282 TxErr = 0x08,
283 TxOK = 0x04,
284 RxErr = 0x02,
285 RxOK = 0x01,
286
287 /* RxStatusDesc */
9dccf611
FR		 288 RxFOVF = (1 << 23),
289 RxRWT = (1 << 22),
290 RxRES = (1 << 21),
291 RxRUNT = (1 << 20),
292 RxCRC = (1 << 19),
1da177e4
LT		 293
294 /* ChipCmdBits */
295 CmdReset = 0x10,
296 CmdRxEnb = 0x08,
297 CmdTxEnb = 0x04,
298 RxBufEmpty = 0x01,
299
300 /* Cfg9346Bits */
301 Cfg9346_Lock = 0x00,
302 Cfg9346_Unlock = 0xC0,
303
304 /* rx_mode_bits */
305 AcceptErr = 0x20,
306 AcceptRunt = 0x10,
307 AcceptBroadcast = 0x08,
308 AcceptMulticast = 0x04,
309 AcceptMyPhys = 0x02,
310 AcceptAllPhys = 0x01,
311
312 /* RxConfigBits */
313 RxCfgFIFOShift = 13,
314 RxCfgDMAShift = 8,
315
316 /* TxConfigBits */
317 TxInterFrameGapShift = 24,
318 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
319
5d06a99f
FR		 320 /* Config1 register p.24 */
321 PMEnable = (1 << 0), /* Power Management Enable */
322
6dccd16b
FR		 323 /* Config2 register p. 25 */
324 PCI_Clock_66MHz = 0x01,
325 PCI_Clock_33MHz = 0x00,
326
61a4dcc2
FR		 327 /* Config3 register p.25 */
328 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
329 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
330
5d06a99f 331 /* Config5 register p.27 */
61a4dcc2
FR		 332 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
333 MWF = (1 << 5), /* Accept Multicast wakeup frame */
334 UWF = (1 << 4), /* Accept Unicast wakeup frame */
335 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 336 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
337
1da177e4
LT		 338 /* TBICSR p.28 */
339 TBIReset = 0x80000000,
340 TBILoopback = 0x40000000,
341 TBINwEnable = 0x20000000,
342 TBINwRestart = 0x10000000,
343 TBILinkOk = 0x02000000,
344 TBINwComplete = 0x01000000,
345
346 /* CPlusCmd p.31 */
0e485150 347 PktCntrDisable = (1 << 7), // 8168
1da177e4
LT		 348 RxVlan = (1 << 6),
349 RxChkSum = (1 << 5),
350 PCIDAC = (1 << 4),
351 PCIMulRW = (1 << 3),
0e485150
FR		 352 INTT_0 = 0x0000, // 8168
353 INTT_1 = 0x0001, // 8168
354 INTT_2 = 0x0002, // 8168
355 INTT_3 = 0x0003, // 8168
1da177e4
LT		 356
357 /* rtl8169_PHYstatus */
358 TBI_Enable = 0x80,
359 TxFlowCtrl = 0x40,
360 RxFlowCtrl = 0x20,
361 _1000bpsF = 0x10,
362 _100bps = 0x08,
363 _10bps = 0x04,
364 LinkStatus = 0x02,
365 FullDup = 0x01,
366
1da177e4
LT		 367 /* _MediaType */
368 _10_Half = 0x01,
369 _10_Full = 0x02,
370 _100_Half = 0x04,
371 _100_Full = 0x08,
372 _1000_Full = 0x10,
373
374 /* _TBICSRBit */
375 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 376
377 /* DumpCounterCommand */
378 CounterDump = 0x8,
1da177e4
LT		 379};
380
381enum _DescStatusBit {
382 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
383 RingEnd = (1 << 30), /* End of descriptor ring */
384 FirstFrag = (1 << 29), /* First segment of a packet */
385 LastFrag = (1 << 28), /* Final segment of a packet */
386
387 /* Tx private */
388 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
389 MSSShift = 16, /* MSS value position */
390 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
391 IPCS = (1 << 18), /* Calculate IP checksum */
392 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
393 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
394 TxVlanTag = (1 << 17), /* Add VLAN tag */
395
396 /* Rx private */
397 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
398 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
399
400#define RxProtoUDP (PID1)
401#define RxProtoTCP (PID0)
402#define RxProtoIP (PID1 | PID0)
403#define RxProtoMask RxProtoIP
404
405 IPFail = (1 << 16), /* IP checksum failed */
406 UDPFail = (1 << 15), /* UDP/IP checksum failed */
407 TCPFail = (1 << 14), /* TCP/IP checksum failed */
408 RxVlanTag = (1 << 16), /* VLAN tag available */
409};
410
411#define RsvdMask 0x3fffc000
412
413struct TxDesc {
414 u32 opts1;
415 u32 opts2;
416 u64 addr;
417};
418
419struct RxDesc {
420 u32 opts1;
421 u32 opts2;
422 u64 addr;
423};
424
425struct ring_info {
426 struct sk_buff *skb;
427 u32 len;
428 u8 __pad[sizeof(void *) - sizeof(u32)];
429};
430
431struct rtl8169_private {
432 void __iomem *mmio_addr; /* memory map physical address */
433 struct pci_dev *pci_dev; /* Index of PCI device */
c4028958 434 struct net_device *dev;
1da177e4
LT		 435 struct net_device_stats stats; /* statistics of net device */
436 spinlock_t lock; /* spin lock flag */
b57b7e5a 437 u32 msg_enable;
1da177e4
LT		 438 int chipset;
439 int mac_version;
440 int phy_version;
441 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
442 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
443 u32 dirty_rx;
444 u32 dirty_tx;
445 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
446 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
447 dma_addr_t TxPhyAddr;
448 dma_addr_t RxPhyAddr;
449 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
450 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
bcf0bf90 451 unsigned align;
1da177e4
LT		 452 unsigned rx_buf_sz;
453 struct timer_list timer;
454 u16 cp_cmd;
0e485150
FR		 455 u16 intr_event;
456 u16 napi_event;
1da177e4
LT		 457 u16 intr_mask;
458 int phy_auto_nego_reg;
459 int phy_1000_ctrl_reg;
460#ifdef CONFIG_R8169_VLAN
461 struct vlan_group *vlgrp;
462#endif
463 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
464 void (*get_settings)(struct net_device *, struct ethtool_cmd *);
465 void (*phy_reset_enable)(void __iomem *);
07ce4064 466 void (*hw_start)(struct net_device *);
1da177e4
LT		 467 unsigned int (*phy_reset_pending)(void __iomem *);
468 unsigned int (*link_ok)(void __iomem *);
c4028958 469 struct delayed_work task;
61a4dcc2 470 unsigned wol_enabled : 1;
1da177e4
LT		 471};
472
979b6c13 473MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4
LT		 474MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
475module_param_array(media, int, &num_media, 0);
df0a1bf6 476MODULE_PARM_DESC(media, "force phy operation. Deprecated by ethtool (8).");
1da177e4 477module_param(rx_copybreak, int, 0);
1b7efd58 478MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
1da177e4
LT		 479module_param(use_dac, int, 0);
480MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 481module_param_named(debug, debug.msg_enable, int, 0);
482MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 483MODULE_LICENSE("GPL");
484MODULE_VERSION(RTL8169_VERSION);
485
486static int rtl8169_open(struct net_device *dev);
487static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
7d12e780 488static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 489static int rtl8169_init_ring(struct net_device *dev);
07ce4064 490static void rtl_hw_start(struct net_device *dev);
1da177e4 491static int rtl8169_close(struct net_device *dev);
07ce4064 492static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 493static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 494static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4
LT		 495static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
496 void __iomem *);
4dcb7d33 497static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 498static void rtl8169_down(struct net_device *dev);
99f252b0 499static void rtl8169_rx_clear(struct rtl8169_private *tp);
1da177e4
LT		 500
501#ifdef CONFIG_R8169_NAPI
502static int rtl8169_poll(struct net_device *dev, int *budget);
503#endif
504
1da177e4 505static const unsigned int rtl8169_rx_config =
5b0384f4 506 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4
LT		 507
508static void mdio_write(void __iomem *ioaddr, int RegAddr, int value)
509{
510 int i;
511
512 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
1da177e4 513
2371408c 514 for (i = 20; i > 0; i--) {
1da177e4 515 /* Check if the RTL8169 has completed writing to the specified MII register */
5b0384f4 516 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 517 break;
2371408c 518 udelay(25);
1da177e4
LT		 519 }
520}
521
522static int mdio_read(void __iomem *ioaddr, int RegAddr)
523{
524 int i, value = -1;
525
526 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
1da177e4 527
2371408c 528 for (i = 20; i > 0; i--) {
1da177e4
LT		 529 /* Check if the RTL8169 has completed retrieving data from the specified MII register */
530 if (RTL_R32(PHYAR) & 0x80000000) {
531 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
532 break;
533 }
2371408c 534 udelay(25);
1da177e4
LT		 535 }
536 return value;
537}
538
539static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
540{
541 RTL_W16(IntrMask, 0x0000);
542
543 RTL_W16(IntrStatus, 0xffff);
544}
545
546static void rtl8169_asic_down(void __iomem *ioaddr)
547{
548 RTL_W8(ChipCmd, 0x00);
549 rtl8169_irq_mask_and_ack(ioaddr);
550 RTL_R16(CPlusCmd);
551}
552
553static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
554{
555 return RTL_R32(TBICSR) & TBIReset;
556}
557
558static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
559{
64e4bfb4 560 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 561}
562
563static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
564{
565 return RTL_R32(TBICSR) & TBILinkOk;
566}
567
568static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
569{
570 return RTL_R8(PHYstatus) & LinkStatus;
571}
572
573static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
574{
575 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
576}
577
578static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
579{
580 unsigned int val;
581
9e0db8ef
FR		 582 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
583 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
1da177e4
LT		 584}
585
586static void rtl8169_check_link_status(struct net_device *dev,
587 struct rtl8169_private *tp, void __iomem *ioaddr)
588{
589 unsigned long flags;
590
591 spin_lock_irqsave(&tp->lock, flags);
592 if (tp->link_ok(ioaddr)) {
593 netif_carrier_on(dev);
b57b7e5a
SH		 594 if (netif_msg_ifup(tp))
595 printk(KERN_INFO PFX "%s: link up\n", dev->name);
596 } else {
597 if (netif_msg_ifdown(tp))
598 printk(KERN_INFO PFX "%s: link down\n", dev->name);
1da177e4 599 netif_carrier_off(dev);
b57b7e5a 600 }
1da177e4
LT		 601 spin_unlock_irqrestore(&tp->lock, flags);
602}
603
604static void rtl8169_link_option(int idx, u8 *autoneg, u16 *speed, u8 *duplex)
605{
606 struct {
607 u16 speed;
608 u8 duplex;
609 u8 autoneg;
610 u8 media;
611 } link_settings[] = {
612 { SPEED_10, DUPLEX_HALF, AUTONEG_DISABLE, _10_Half },
613 { SPEED_10, DUPLEX_FULL, AUTONEG_DISABLE, _10_Full },
614 { SPEED_100, DUPLEX_HALF, AUTONEG_DISABLE, _100_Half },
615 { SPEED_100, DUPLEX_FULL, AUTONEG_DISABLE, _100_Full },
616 { SPEED_1000, DUPLEX_FULL, AUTONEG_DISABLE, _1000_Full },
617 /* Make TBI happy */
618 { SPEED_1000, DUPLEX_FULL, AUTONEG_ENABLE, 0xff }
619 }, *p;
620 unsigned char option;
5b0384f4 621
1da177e4
LT		 622 option = ((idx < MAX_UNITS) && (idx >= 0)) ? media[idx] : 0xff;
623
b57b7e5a 624 if ((option != 0xff) && !idx && netif_msg_drv(&debug))
1da177e4
LT		 625 printk(KERN_WARNING PFX "media option is deprecated.\n");
626
627 for (p = link_settings; p->media != 0xff; p++) {
628 if (p->media == option)
629 break;
630 }
631 *autoneg = p->autoneg;
632 *speed = p->speed;
633 *duplex = p->duplex;
634}
635
61a4dcc2
FR		 636static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
637{
638 struct rtl8169_private *tp = netdev_priv(dev);
639 void __iomem *ioaddr = tp->mmio_addr;
640 u8 options;
641
642 wol->wolopts = 0;
643
644#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
645 wol->supported = WAKE_ANY;
646
647 spin_lock_irq(&tp->lock);
648
649 options = RTL_R8(Config1);
650 if (!(options & PMEnable))
651 goto out_unlock;
652
653 options = RTL_R8(Config3);
654 if (options & LinkUp)
655 wol->wolopts |= WAKE_PHY;
656 if (options & MagicPacket)
657 wol->wolopts |= WAKE_MAGIC;
658
659 options = RTL_R8(Config5);
660 if (options & UWF)
661 wol->wolopts |= WAKE_UCAST;
662 if (options & BWF)
5b0384f4 663 wol->wolopts |= WAKE_BCAST;
61a4dcc2 664 if (options & MWF)
5b0384f4 665 wol->wolopts |= WAKE_MCAST;
61a4dcc2
FR		 666
667out_unlock:
668 spin_unlock_irq(&tp->lock);
669}
670
671static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
672{
673 struct rtl8169_private *tp = netdev_priv(dev);
674 void __iomem *ioaddr = tp->mmio_addr;
675 int i;
676 static struct {
677 u32 opt;
678 u16 reg;
679 u8 mask;
680 } cfg[] = {
681 { WAKE_ANY, Config1, PMEnable },
682 { WAKE_PHY, Config3, LinkUp },
683 { WAKE_MAGIC, Config3, MagicPacket },
684 { WAKE_UCAST, Config5, UWF },
685 { WAKE_BCAST, Config5, BWF },
686 { WAKE_MCAST, Config5, MWF },
687 { WAKE_ANY, Config5, LanWake }
688 };
689
690 spin_lock_irq(&tp->lock);
691
692 RTL_W8(Cfg9346, Cfg9346_Unlock);
693
694 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
695 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
696 if (wol->wolopts & cfg[i].opt)
697 options |= cfg[i].mask;
698 RTL_W8(cfg[i].reg, options);
699 }
700
701 RTL_W8(Cfg9346, Cfg9346_Lock);
702
703 tp->wol_enabled = (wol->wolopts) ? 1 : 0;
704
705 spin_unlock_irq(&tp->lock);
706
707 return 0;
708}
709
1da177e4
LT		 710static void rtl8169_get_drvinfo(struct net_device *dev,
711 struct ethtool_drvinfo *info)
712{
713 struct rtl8169_private *tp = netdev_priv(dev);
714
715 strcpy(info->driver, MODULENAME);
716 strcpy(info->version, RTL8169_VERSION);
717 strcpy(info->bus_info, pci_name(tp->pci_dev));
718}
719
720static int rtl8169_get_regs_len(struct net_device *dev)
721{
722 return R8169_REGS_SIZE;
723}
724
725static int rtl8169_set_speed_tbi(struct net_device *dev,
726 u8 autoneg, u16 speed, u8 duplex)
727{
728 struct rtl8169_private *tp = netdev_priv(dev);
729 void __iomem *ioaddr = tp->mmio_addr;
730 int ret = 0;
731 u32 reg;
732
733 reg = RTL_R32(TBICSR);
734 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
735 (duplex == DUPLEX_FULL)) {
736 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
737 } else if (autoneg == AUTONEG_ENABLE)
738 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
739 else {
b57b7e5a
SH		 740 if (netif_msg_link(tp)) {
741 printk(KERN_WARNING "%s: "
742 "incorrect speed setting refused in TBI mode\n",
743 dev->name);
744 }
1da177e4
LT		 745 ret = -EOPNOTSUPP;
746 }
747
748 return ret;
749}
750
751static int rtl8169_set_speed_xmii(struct net_device *dev,
752 u8 autoneg, u16 speed, u8 duplex)
753{
754 struct rtl8169_private *tp = netdev_priv(dev);
755 void __iomem *ioaddr = tp->mmio_addr;
756 int auto_nego, giga_ctrl;
757
64e4bfb4
FR		 758 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
759 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
760 ADVERTISE_100HALF | ADVERTISE_100FULL);
761 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
762 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 763
764 if (autoneg == AUTONEG_ENABLE) {
64e4bfb4
FR		 765 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
766 ADVERTISE_100HALF | ADVERTISE_100FULL);
767 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 768 } else {
769 if (speed == SPEED_10)
64e4bfb4 770 auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1da177e4 771 else if (speed == SPEED_100)
64e4bfb4 772 auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
1da177e4 773 else if (speed == SPEED_1000)
64e4bfb4 774 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 775
776 if (duplex == DUPLEX_HALF)
64e4bfb4 777 auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
726ecdcf
AG		 778
779 if (duplex == DUPLEX_FULL)
64e4bfb4 780 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
bcf0bf90
FR		 781
782 /* This tweak comes straight from Realtek's driver. */
783 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
784 (tp->mac_version == RTL_GIGA_MAC_VER_13)) {
64e4bfb4 785 auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
bcf0bf90
FR		 786 }
787 }
788
789 /* The 8100e/8101e do Fast Ethernet only. */
790 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
791 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
792 (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
64e4bfb4 793 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
bcf0bf90
FR		 794 netif_msg_link(tp)) {
795 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
796 dev->name);
797 }
64e4bfb4 798 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 799 }
800
623a1593
FR		 801 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
802
1da177e4
LT		 803 tp->phy_auto_nego_reg = auto_nego;
804 tp->phy_1000_ctrl_reg = giga_ctrl;
805
64e4bfb4
FR		 806 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
807 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
808 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
1da177e4
LT		 809 return 0;
810}
811
812static int rtl8169_set_speed(struct net_device *dev,
813 u8 autoneg, u16 speed, u8 duplex)
814{
815 struct rtl8169_private *tp = netdev_priv(dev);
816 int ret;
817
818 ret = tp->set_speed(dev, autoneg, speed, duplex);
819
64e4bfb4 820 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 821 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
822
823 return ret;
824}
825
826static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
827{
828 struct rtl8169_private *tp = netdev_priv(dev);
829 unsigned long flags;
830 int ret;
831
832 spin_lock_irqsave(&tp->lock, flags);
833 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
834 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 835
1da177e4
LT		 836 return ret;
837}
838
839static u32 rtl8169_get_rx_csum(struct net_device *dev)
840{
841 struct rtl8169_private *tp = netdev_priv(dev);
842
843 return tp->cp_cmd & RxChkSum;
844}
845
846static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
847{
848 struct rtl8169_private *tp = netdev_priv(dev);
849 void __iomem *ioaddr = tp->mmio_addr;
850 unsigned long flags;
851
852 spin_lock_irqsave(&tp->lock, flags);
853
854 if (data)
855 tp->cp_cmd |= RxChkSum;
856 else
857 tp->cp_cmd &= ~RxChkSum;
858
859 RTL_W16(CPlusCmd, tp->cp_cmd);
860 RTL_R16(CPlusCmd);
861
862 spin_unlock_irqrestore(&tp->lock, flags);
863
864 return 0;
865}
866
867#ifdef CONFIG_R8169_VLAN
868
869static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
870 struct sk_buff *skb)
871{
872 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
873 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
874}
875
876static void rtl8169_vlan_rx_register(struct net_device *dev,
877 struct vlan_group *grp)
878{
879 struct rtl8169_private *tp = netdev_priv(dev);
880 void __iomem *ioaddr = tp->mmio_addr;
881 unsigned long flags;
882
883 spin_lock_irqsave(&tp->lock, flags);
884 tp->vlgrp = grp;
885 if (tp->vlgrp)
886 tp->cp_cmd |= RxVlan;
887 else
888 tp->cp_cmd &= ~RxVlan;
889 RTL_W16(CPlusCmd, tp->cp_cmd);
890 RTL_R16(CPlusCmd);
891 spin_unlock_irqrestore(&tp->lock, flags);
892}
893
1da177e4
LT		 894static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
895 struct sk_buff *skb)
896{
897 u32 opts2 = le32_to_cpu(desc->opts2);
898 int ret;
899
900 if (tp->vlgrp && (opts2 & RxVlanTag)) {
901 rtl8169_rx_hwaccel_skb(skb, tp->vlgrp,
902 swab16(opts2 & 0xffff));
903 ret = 0;
904 } else
905 ret = -1;
906 desc->opts2 = 0;
907 return ret;
908}
909
910#else /* !CONFIG_R8169_VLAN */
911
912static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
913 struct sk_buff *skb)
914{
915 return 0;
916}
917
918static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
919 struct sk_buff *skb)
920{
921 return -1;
922}
923
924#endif
925
926static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
927{
928 struct rtl8169_private *tp = netdev_priv(dev);
929 void __iomem *ioaddr = tp->mmio_addr;
930 u32 status;
931
932 cmd->supported =
933 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
934 cmd->port = PORT_FIBRE;
935 cmd->transceiver = XCVR_INTERNAL;
936
937 status = RTL_R32(TBICSR);
938 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
939 cmd->autoneg = !!(status & TBINwEnable);
940
941 cmd->speed = SPEED_1000;
942 cmd->duplex = DUPLEX_FULL; /* Always set */
943}
944
945static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
946{
947 struct rtl8169_private *tp = netdev_priv(dev);
948 void __iomem *ioaddr = tp->mmio_addr;
949 u8 status;
950
951 cmd->supported = SUPPORTED_10baseT_Half |
952 SUPPORTED_10baseT_Full |
953 SUPPORTED_100baseT_Half |
954 SUPPORTED_100baseT_Full |
955 SUPPORTED_1000baseT_Full |
956 SUPPORTED_Autoneg |
5b0384f4 957 SUPPORTED_TP;
1da177e4
LT		 958
959 cmd->autoneg = 1;
960 cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
961
64e4bfb4 962 if (tp->phy_auto_nego_reg & ADVERTISE_10HALF)
1da177e4 963 cmd->advertising |= ADVERTISED_10baseT_Half;
64e4bfb4 964 if (tp->phy_auto_nego_reg & ADVERTISE_10FULL)
1da177e4 965 cmd->advertising |= ADVERTISED_10baseT_Full;
64e4bfb4 966 if (tp->phy_auto_nego_reg & ADVERTISE_100HALF)
1da177e4 967 cmd->advertising |= ADVERTISED_100baseT_Half;
64e4bfb4 968 if (tp->phy_auto_nego_reg & ADVERTISE_100FULL)
1da177e4 969 cmd->advertising |= ADVERTISED_100baseT_Full;
64e4bfb4 970 if (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)
1da177e4
LT		 971 cmd->advertising |= ADVERTISED_1000baseT_Full;
972
973 status = RTL_R8(PHYstatus);
974
975 if (status & _1000bpsF)
976 cmd->speed = SPEED_1000;
977 else if (status & _100bps)
978 cmd->speed = SPEED_100;
979 else if (status & _10bps)
980 cmd->speed = SPEED_10;
981
623a1593
FR		 982 if (status & TxFlowCtrl)
983 cmd->advertising |= ADVERTISED_Asym_Pause;
984 if (status & RxFlowCtrl)
985 cmd->advertising |= ADVERTISED_Pause;
986
1da177e4
LT		 987 cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ?
988 DUPLEX_FULL : DUPLEX_HALF;
989}
990
991static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
992{
993 struct rtl8169_private *tp = netdev_priv(dev);
994 unsigned long flags;
995
996 spin_lock_irqsave(&tp->lock, flags);
997
998 tp->get_settings(dev, cmd);
999
1000 spin_unlock_irqrestore(&tp->lock, flags);
1001 return 0;
1002}
1003
1004static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1005 void *p)
1006{
5b0384f4
FR		 1007 struct rtl8169_private *tp = netdev_priv(dev);
1008 unsigned long flags;
1da177e4 1009
5b0384f4
FR		 1010 if (regs->len > R8169_REGS_SIZE)
1011 regs->len = R8169_REGS_SIZE;
1da177e4 1012
5b0384f4
FR		 1013 spin_lock_irqsave(&tp->lock, flags);
1014 memcpy_fromio(p, tp->mmio_addr, regs->len);
1015 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 1016}
1017
b57b7e5a
SH		 1018static u32 rtl8169_get_msglevel(struct net_device *dev)
1019{
1020 struct rtl8169_private *tp = netdev_priv(dev);
1021
1022 return tp->msg_enable;
1023}
1024
1025static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1026{
1027 struct rtl8169_private *tp = netdev_priv(dev);
1028
1029 tp->msg_enable = value;
1030}
1031
d4a3a0fc
SH		 1032static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1033 "tx_packets",
1034 "rx_packets",
1035 "tx_errors",
1036 "rx_errors",
1037 "rx_missed",
1038 "align_errors",
1039 "tx_single_collisions",
1040 "tx_multi_collisions",
1041 "unicast",
1042 "broadcast",
1043 "multicast",
1044 "tx_aborted",
1045 "tx_underrun",
1046};
1047
1048struct rtl8169_counters {
1049 u64 tx_packets;
1050 u64 rx_packets;
1051 u64 tx_errors;
1052 u32 rx_errors;
1053 u16 rx_missed;
1054 u16 align_errors;
1055 u32 tx_one_collision;
1056 u32 tx_multi_collision;
1057 u64 rx_unicast;
1058 u64 rx_broadcast;
1059 u32 rx_multicast;
1060 u16 tx_aborted;
1061 u16 tx_underun;
1062};
1063
1064static int rtl8169_get_stats_count(struct net_device *dev)
1065{
1066 return ARRAY_SIZE(rtl8169_gstrings);
1067}
1068
1069static void rtl8169_get_ethtool_stats(struct net_device *dev,
1070 struct ethtool_stats *stats, u64 *data)
1071{
1072 struct rtl8169_private *tp = netdev_priv(dev);
1073 void __iomem *ioaddr = tp->mmio_addr;
1074 struct rtl8169_counters *counters;
1075 dma_addr_t paddr;
1076 u32 cmd;
1077
1078 ASSERT_RTNL();
1079
1080 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1081 if (!counters)
1082 return;
1083
1084 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1085 cmd = (u64)paddr & DMA_32BIT_MASK;
1086 RTL_W32(CounterAddrLow, cmd);
1087 RTL_W32(CounterAddrLow, cmd | CounterDump);
1088
1089 while (RTL_R32(CounterAddrLow) & CounterDump) {
1090 if (msleep_interruptible(1))
1091 break;
1092 }
1093
1094 RTL_W32(CounterAddrLow, 0);
1095 RTL_W32(CounterAddrHigh, 0);
1096
5b0384f4 1097 data[0] = le64_to_cpu(counters->tx_packets);
d4a3a0fc
SH		 1098 data[1] = le64_to_cpu(counters->rx_packets);
1099 data[2] = le64_to_cpu(counters->tx_errors);
1100 data[3] = le32_to_cpu(counters->rx_errors);
1101 data[4] = le16_to_cpu(counters->rx_missed);
1102 data[5] = le16_to_cpu(counters->align_errors);
1103 data[6] = le32_to_cpu(counters->tx_one_collision);
1104 data[7] = le32_to_cpu(counters->tx_multi_collision);
1105 data[8] = le64_to_cpu(counters->rx_unicast);
1106 data[9] = le64_to_cpu(counters->rx_broadcast);
1107 data[10] = le32_to_cpu(counters->rx_multicast);
1108 data[11] = le16_to_cpu(counters->tx_aborted);
1109 data[12] = le16_to_cpu(counters->tx_underun);
1110
1111 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1112}
1113
1114static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1115{
1116 switch(stringset) {
1117 case ETH_SS_STATS:
1118 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1119 break;
1120 }
1121}
1122
1123
7282d491 1124static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1125 .get_drvinfo = rtl8169_get_drvinfo,
1126 .get_regs_len = rtl8169_get_regs_len,
1127 .get_link = ethtool_op_get_link,
1128 .get_settings = rtl8169_get_settings,
1129 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1130 .get_msglevel = rtl8169_get_msglevel,
1131 .set_msglevel = rtl8169_set_msglevel,
1da177e4
LT		 1132 .get_rx_csum = rtl8169_get_rx_csum,
1133 .set_rx_csum = rtl8169_set_rx_csum,
1134 .get_tx_csum = ethtool_op_get_tx_csum,
1135 .set_tx_csum = ethtool_op_set_tx_csum,
1136 .get_sg = ethtool_op_get_sg,
1137 .set_sg = ethtool_op_set_sg,
1138 .get_tso = ethtool_op_get_tso,
1139 .set_tso = ethtool_op_set_tso,
1140 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1141 .get_wol = rtl8169_get_wol,
1142 .set_wol = rtl8169_set_wol,
d4a3a0fc
SH		 1143 .get_strings = rtl8169_get_strings,
1144 .get_stats_count = rtl8169_get_stats_count,
1145 .get_ethtool_stats = rtl8169_get_ethtool_stats,
6d6525b7 1146 .get_perm_addr = ethtool_op_get_perm_addr,
1da177e4
LT		 1147};
1148
1149static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg, int bitnum,
1150 int bitval)
1151{
1152 int val;
1153
1154 val = mdio_read(ioaddr, reg);
1155 val = (bitval == 1) ?
1156 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
5b0384f4 1157 mdio_write(ioaddr, reg, val & 0xffff);
1da177e4
LT		 1158}
1159
1160static void rtl8169_get_mac_version(struct rtl8169_private *tp, void __iomem *ioaddr)
1161{
0e485150
FR		 1162 /*
1163 * The driver currently handles the 8168Bf and the 8168Be identically
1164 * but they can be identified more specifically through the test below
1165 * if needed:
1166 *
1167 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1168 */
1da177e4
LT		 1169 const struct {
1170 u32 mask;
1171 int mac_version;
1172 } mac_info[] = {
bcf0bf90
FR		 1173 { 0x38800000, RTL_GIGA_MAC_VER_15 },
1174 { 0x38000000, RTL_GIGA_MAC_VER_12 },
1175 { 0x34000000, RTL_GIGA_MAC_VER_13 },
1176 { 0x30800000, RTL_GIGA_MAC_VER_14 },
5b0384f4 1177 { 0x30000000, RTL_GIGA_MAC_VER_11 },
6dccd16b 1178 { 0x98000000, RTL_GIGA_MAC_VER_06 },
bcf0bf90
FR		 1179 { 0x18000000, RTL_GIGA_MAC_VER_05 },
1180 { 0x10000000, RTL_GIGA_MAC_VER_04 },
1181 { 0x04000000, RTL_GIGA_MAC_VER_03 },
1182 { 0x00800000, RTL_GIGA_MAC_VER_02 },
1183 { 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
1da177e4
LT		 1184 }, *p = mac_info;
1185 u32 reg;
1186
6dccd16b 1187 reg = RTL_R32(TxConfig) & 0xfc800000;
1da177e4
LT		 1188 while ((reg & p->mask) != p->mask)
1189 p++;
1190 tp->mac_version = p->mac_version;
1191}
1192
1193static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1194{
bcf0bf90 1195 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1196}
1197
1198static void rtl8169_get_phy_version(struct rtl8169_private *tp, void __iomem *ioaddr)
1199{
1200 const struct {
1201 u16 mask;
1202 u16 set;
1203 int phy_version;
1204 } phy_info[] = {
1205 { 0x000f, 0x0002, RTL_GIGA_PHY_VER_G },
1206 { 0x000f, 0x0001, RTL_GIGA_PHY_VER_F },
1207 { 0x000f, 0x0000, RTL_GIGA_PHY_VER_E },
1208 { 0x0000, 0x0000, RTL_GIGA_PHY_VER_D } /* Catch-all */
1209 }, *p = phy_info;
1210 u16 reg;
1211
64e4bfb4 1212 reg = mdio_read(ioaddr, MII_PHYSID2) & 0xffff;
1da177e4
LT		 1213 while ((reg & p->mask) != p->set)
1214 p++;
1215 tp->phy_version = p->phy_version;
1216}
1217
1218static void rtl8169_print_phy_version(struct rtl8169_private *tp)
1219{
1220 struct {
1221 int version;
1222 char *msg;
1223 u32 reg;
1224 } phy_print[] = {
1225 { RTL_GIGA_PHY_VER_G, "RTL_GIGA_PHY_VER_G", 0x0002 },
1226 { RTL_GIGA_PHY_VER_F, "RTL_GIGA_PHY_VER_F", 0x0001 },
1227 { RTL_GIGA_PHY_VER_E, "RTL_GIGA_PHY_VER_E", 0x0000 },
1228 { RTL_GIGA_PHY_VER_D, "RTL_GIGA_PHY_VER_D", 0x0000 },
1229 { 0, NULL, 0x0000 }
1230 }, *p;
1231
1232 for (p = phy_print; p->msg; p++) {
1233 if (tp->phy_version == p->version) {
1234 dprintk("phy_version == %s (%04x)\n", p->msg, p->reg);
1235 return;
1236 }
1237 }
1238 dprintk("phy_version == Unknown\n");
1239}
1240
1241static void rtl8169_hw_phy_config(struct net_device *dev)
1242{
1243 struct rtl8169_private *tp = netdev_priv(dev);
1244 void __iomem *ioaddr = tp->mmio_addr;
1245 struct {
1246 u16 regs[5]; /* Beware of bit-sign propagation */
1247 } phy_magic[5] = { {
1248 { 0x0000, //w 4 15 12 0
1249 0x00a1, //w 3 15 0 00a1
1250 0x0008, //w 2 15 0 0008
1251 0x1020, //w 1 15 0 1020
1252 0x1000 } },{ //w 0 15 0 1000
1253 { 0x7000, //w 4 15 12 7
1254 0xff41, //w 3 15 0 ff41
1255 0xde60, //w 2 15 0 de60
1256 0x0140, //w 1 15 0 0140
1257 0x0077 } },{ //w 0 15 0 0077
1258 { 0xa000, //w 4 15 12 a
1259 0xdf01, //w 3 15 0 df01
1260 0xdf20, //w 2 15 0 df20
1261 0xff95, //w 1 15 0 ff95
1262 0xfa00 } },{ //w 0 15 0 fa00
1263 { 0xb000, //w 4 15 12 b
1264 0xff41, //w 3 15 0 ff41
1265 0xde20, //w 2 15 0 de20
1266 0x0140, //w 1 15 0 0140
1267 0x00bb } },{ //w 0 15 0 00bb
1268 { 0xf000, //w 4 15 12 f
1269 0xdf01, //w 3 15 0 df01
1270 0xdf20, //w 2 15 0 df20
1271 0xff95, //w 1 15 0 ff95
1272 0xbf00 } //w 0 15 0 bf00
1273 }
1274 }, *p = phy_magic;
1275 int i;
1276
1277 rtl8169_print_mac_version(tp);
1278 rtl8169_print_phy_version(tp);
1279
bcf0bf90 1280 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 1281 return;
1282 if (tp->phy_version >= RTL_GIGA_PHY_VER_H)
1283 return;
1284
1285 dprintk("MAC version != 0 && PHY version == 0 or 1\n");
1286 dprintk("Do final_reg2.cfg\n");
1287
1288 /* Shazam ! */
1289
bcf0bf90 1290 if (tp->mac_version == RTL_GIGA_MAC_VER_04) {
1da177e4
LT		 1291 mdio_write(ioaddr, 31, 0x0002);
1292 mdio_write(ioaddr, 1, 0x90d0);
1293 mdio_write(ioaddr, 31, 0x0000);
1294 return;
1295 }
1296
1297 /* phy config for RTL8169s mac_version C chip */
1298 mdio_write(ioaddr, 31, 0x0001); //w 31 2 0 1
1299 mdio_write(ioaddr, 21, 0x1000); //w 21 15 0 1000
1300 mdio_write(ioaddr, 24, 0x65c7); //w 24 15 0 65c7
1301 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1302
1303 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1304 int val, pos = 4;
1305
1306 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1307 mdio_write(ioaddr, pos, val);
1308 while (--pos >= 0)
1309 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1310 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1311 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1312 }
1313 mdio_write(ioaddr, 31, 0x0000); //w 31 2 0 0
1314}
1315
1316static void rtl8169_phy_timer(unsigned long __opaque)
1317{
1318 struct net_device *dev = (struct net_device *)__opaque;
1319 struct rtl8169_private *tp = netdev_priv(dev);
1320 struct timer_list *timer = &tp->timer;
1321 void __iomem *ioaddr = tp->mmio_addr;
1322 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1323
bcf0bf90 1324 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4
LT		 1325 assert(tp->phy_version < RTL_GIGA_PHY_VER_H);
1326
64e4bfb4 1327 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 1328 return;
1329
1330 spin_lock_irq(&tp->lock);
1331
1332 if (tp->phy_reset_pending(ioaddr)) {
5b0384f4 1333 /*
1da177e4
LT		 1334 * A busy loop could burn quite a few cycles on nowadays CPU.
1335 * Let's delay the execution of the timer for a few ticks.
1336 */
1337 timeout = HZ/10;
1338 goto out_mod_timer;
1339 }
1340
1341 if (tp->link_ok(ioaddr))
1342 goto out_unlock;
1343
b57b7e5a
SH		 1344 if (netif_msg_link(tp))
1345 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1da177e4
LT		 1346
1347 tp->phy_reset_enable(ioaddr);
1348
1349out_mod_timer:
1350 mod_timer(timer, jiffies + timeout);
1351out_unlock:
1352 spin_unlock_irq(&tp->lock);
1353}
1354
1355static inline void rtl8169_delete_timer(struct net_device *dev)
1356{
1357 struct rtl8169_private *tp = netdev_priv(dev);
1358 struct timer_list *timer = &tp->timer;
1359
bcf0bf90 1360 if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1da177e4
LT		 1361 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1362 return;
1363
1364 del_timer_sync(timer);
1365}
1366
1367static inline void rtl8169_request_timer(struct net_device *dev)
1368{
1369 struct rtl8169_private *tp = netdev_priv(dev);
1370 struct timer_list *timer = &tp->timer;
1371
bcf0bf90 1372 if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1da177e4
LT		 1373 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1374 return;
1375
2efa53f3 1376 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1da177e4
LT		 1377}
1378
1379#ifdef CONFIG_NET_POLL_CONTROLLER
1380/*
1381 * Polling 'interrupt' - used by things like netconsole to send skbs
1382 * without having to re-enable interrupts. It's not called while
1383 * the interrupt routine is executing.
1384 */
1385static void rtl8169_netpoll(struct net_device *dev)
1386{
1387 struct rtl8169_private *tp = netdev_priv(dev);
1388 struct pci_dev *pdev = tp->pci_dev;
1389
1390 disable_irq(pdev->irq);
7d12e780 1391 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 1392 enable_irq(pdev->irq);
1393}
1394#endif
1395
1396static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1397 void __iomem *ioaddr)
1398{
1399 iounmap(ioaddr);
1400 pci_release_regions(pdev);
1401 pci_disable_device(pdev);
1402 free_netdev(dev);
1403}
1404
bf793295
FR		 1405static void rtl8169_phy_reset(struct net_device *dev,
1406 struct rtl8169_private *tp)
1407{
1408 void __iomem *ioaddr = tp->mmio_addr;
1409 int i;
1410
1411 tp->phy_reset_enable(ioaddr);
1412 for (i = 0; i < 100; i++) {
1413 if (!tp->phy_reset_pending(ioaddr))
1414 return;
1415 msleep(1);
1416 }
1417 if (netif_msg_link(tp))
1418 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1419}
1420
4ff96fa6
FR		 1421static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1422{
1423 void __iomem *ioaddr = tp->mmio_addr;
1424 static int board_idx = -1;
1425 u8 autoneg, duplex;
1426 u16 speed;
1427
1428 board_idx++;
1429
1430 rtl8169_hw_phy_config(dev);
1431
1432 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1433 RTL_W8(0x82, 0x01);
1434
6dccd16b
FR		 1435 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1436
1437 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1438 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 1439
bcf0bf90 1440 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 1441 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1442 RTL_W8(0x82, 0x01);
1443 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1444 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1445 }
1446
1447 rtl8169_link_option(board_idx, &autoneg, &speed, &duplex);
1448
bf793295
FR		 1449 rtl8169_phy_reset(dev, tp);
1450
4ff96fa6
FR		 1451 rtl8169_set_speed(dev, autoneg, speed, duplex);
1452
1453 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1454 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1455}
1456
5f787a1a
FR		 1457static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1458{
1459 struct rtl8169_private *tp = netdev_priv(dev);
1460 struct mii_ioctl_data *data = if_mii(ifr);
1461
1462 if (!netif_running(dev))
1463 return -ENODEV;
1464
1465 switch (cmd) {
1466 case SIOCGMIIPHY:
1467 data->phy_id = 32; /* Internal PHY */
1468 return 0;
1469
1470 case SIOCGMIIREG:
1471 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1472 return 0;
1473
1474 case SIOCSMIIREG:
1475 if (!capable(CAP_NET_ADMIN))
1476 return -EPERM;
1477 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1478 return 0;
1479 }
1480 return -EOPNOTSUPP;
1481}
1482
0e485150
FR		 1483static const struct rtl_cfg_info {
1484 void (*hw_start)(struct net_device *);
1485 unsigned int region;
1486 unsigned int align;
1487 u16 intr_event;
1488 u16 napi_event;
1489} rtl_cfg_infos [] = {
1490 [RTL_CFG_0] = {
1491 .hw_start = rtl_hw_start_8169,
1492 .region = 1,
86402234 1493 .align = 2,
0e485150
FR		 1494 .intr_event = SYSErr | LinkChg | RxOverflow |
1495 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1496 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow
1497 },
1498 [RTL_CFG_1] = {
1499 .hw_start = rtl_hw_start_8168,
1500 .region = 2,
1501 .align = 8,
1502 .intr_event = SYSErr | LinkChg | RxOverflow |
1503 TxErr | TxOK | RxOK | RxErr,
1504 .napi_event = TxErr | TxOK | RxOK | RxOverflow
1505 },
1506 [RTL_CFG_2] = {
1507 .hw_start = rtl_hw_start_8101,
1508 .region = 2,
1509 .align = 8,
1510 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1511 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1512 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow
1513 }
1514};
1515
1da177e4 1516static int __devinit
4ff96fa6 1517rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1518{
0e485150
FR		 1519 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1520 const unsigned int region = cfg->region;
1da177e4 1521 struct rtl8169_private *tp;
4ff96fa6
FR		 1522 struct net_device *dev;
1523 void __iomem *ioaddr;
315917d2
FR		 1524 unsigned int pm_cap;
1525 int i, rc;
1da177e4 1526
4ff96fa6
FR		 1527 if (netif_msg_drv(&debug)) {
1528 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1529 MODULENAME, RTL8169_VERSION);
1530 }
1da177e4 1531
1da177e4 1532 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 1533 if (!dev) {
b57b7e5a 1534 if (netif_msg_drv(&debug))
9b91cf9d 1535 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 1536 rc = -ENOMEM;
1537 goto out;
1da177e4
LT		 1538 }
1539
1540 SET_MODULE_OWNER(dev);
1541 SET_NETDEV_DEV(dev, &pdev->dev);
1542 tp = netdev_priv(dev);
c4028958 1543 tp->dev = dev;
b57b7e5a 1544 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4
LT		 1545
1546 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1547 rc = pci_enable_device(pdev);
b57b7e5a 1548 if (rc < 0) {
2e8a538d 1549 if (netif_msg_probe(tp))
9b91cf9d 1550 dev_err(&pdev->dev, "enable failure\n");
4ff96fa6 1551 goto err_out_free_dev_1;
1da177e4
LT		 1552 }
1553
1554 rc = pci_set_mwi(pdev);
1555 if (rc < 0)
4ff96fa6 1556 goto err_out_disable_2;
1da177e4
LT		 1557
1558 /* save power state before pci_enable_device overwrites it */
1559 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
1560 if (pm_cap) {
4ff96fa6 1561 u16 pwr_command, acpi_idle_state;
1da177e4
LT		 1562
1563 pci_read_config_word(pdev, pm_cap + PCI_PM_CTRL, &pwr_command);
1564 acpi_idle_state = pwr_command & PCI_PM_CTRL_STATE_MASK;
1565 } else {
4ff96fa6 1566 if (netif_msg_probe(tp)) {
9b91cf9d 1567 dev_err(&pdev->dev,
4ff96fa6
FR		 1568 "PowerManagement capability not found.\n");
1569 }
1da177e4
LT		 1570 }
1571
1572 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 1573 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
4ff96fa6 1574 if (netif_msg_probe(tp)) {
9b91cf9d 1575 dev_err(&pdev->dev,
bcf0bf90
FR		 1576 "region #%d not an MMIO resource, aborting\n",
1577 region);
4ff96fa6 1578 }
1da177e4 1579 rc = -ENODEV;
4ff96fa6 1580 goto err_out_mwi_3;
1da177e4 1581 }
4ff96fa6 1582
1da177e4 1583 /* check for weird/broken PCI region reporting */
bcf0bf90 1584 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
4ff96fa6 1585 if (netif_msg_probe(tp)) {
9b91cf9d 1586 dev_err(&pdev->dev,
4ff96fa6
FR		 1587 "Invalid PCI region size(s), aborting\n");
1588 }
1da177e4 1589 rc = -ENODEV;
4ff96fa6 1590 goto err_out_mwi_3;
1da177e4
LT		 1591 }
1592
1593 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 1594 if (rc < 0) {
2e8a538d 1595 if (netif_msg_probe(tp))
9b91cf9d 1596 dev_err(&pdev->dev, "could not request regions.\n");
4ff96fa6 1597 goto err_out_mwi_3;
1da177e4
LT		 1598 }
1599
1600 tp->cp_cmd = PCIMulRW | RxChkSum;
1601
1602 if ((sizeof(dma_addr_t) > 4) &&
1603 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1604 tp->cp_cmd |= PCIDAC;
1605 dev->features |= NETIF_F_HIGHDMA;
1606 } else {
1607 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1608 if (rc < 0) {
4ff96fa6 1609 if (netif_msg_probe(tp)) {
9b91cf9d 1610 dev_err(&pdev->dev,
4ff96fa6
FR		 1611 "DMA configuration failed.\n");
1612 }
1613 goto err_out_free_res_4;
1da177e4
LT		 1614 }
1615 }
1616
1617 pci_set_master(pdev);
1618
1619 /* ioremap MMIO region */
bcf0bf90 1620 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 1621 if (!ioaddr) {
b57b7e5a 1622 if (netif_msg_probe(tp))
9b91cf9d 1623 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1da177e4 1624 rc = -EIO;
4ff96fa6 1625 goto err_out_free_res_4;
1da177e4
LT		 1626 }
1627
1628 /* Unneeded ? Don't mess with Mrs. Murphy. */
1629 rtl8169_irq_mask_and_ack(ioaddr);
1630
1631 /* Soft reset the chip. */
1632 RTL_W8(ChipCmd, CmdReset);
1633
1634 /* Check that the chip has finished the reset. */
b518fa8e 1635 for (i = 100; i > 0; i--) {
1da177e4
LT		 1636 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1637 break;
b518fa8e 1638 msleep_interruptible(1);
1da177e4
LT		 1639 }
1640
1641 /* Identify chip attached to board */
1642 rtl8169_get_mac_version(tp, ioaddr);
1643 rtl8169_get_phy_version(tp, ioaddr);
1644
1645 rtl8169_print_mac_version(tp);
1646 rtl8169_print_phy_version(tp);
1647
1648 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) {
1649 if (tp->mac_version == rtl_chip_info[i].mac_version)
1650 break;
1651 }
1652 if (i < 0) {
1653 /* Unknown chip: assume array element #0, original RTL-8169 */
b57b7e5a 1654 if (netif_msg_probe(tp)) {
2e8a538d 1655 dev_printk(KERN_DEBUG, &pdev->dev,
4ff96fa6
FR		 1656 "unknown chip version, assuming %s\n",
1657 rtl_chip_info[0].name);
b57b7e5a 1658 }
1da177e4
LT		 1659 i++;
1660 }
1661 tp->chipset = i;
1662
5d06a99f
FR		 1663 RTL_W8(Cfg9346, Cfg9346_Unlock);
1664 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1665 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
1666 RTL_W8(Cfg9346, Cfg9346_Lock);
1667
1da177e4
LT		 1668 if (RTL_R8(PHYstatus) & TBI_Enable) {
1669 tp->set_speed = rtl8169_set_speed_tbi;
1670 tp->get_settings = rtl8169_gset_tbi;
1671 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1672 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1673 tp->link_ok = rtl8169_tbi_link_ok;
1674
64e4bfb4 1675 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1da177e4
LT		 1676 } else {
1677 tp->set_speed = rtl8169_set_speed_xmii;
1678 tp->get_settings = rtl8169_gset_xmii;
1679 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1680 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1681 tp->link_ok = rtl8169_xmii_link_ok;
5f787a1a
FR		 1682
1683 dev->do_ioctl = rtl8169_ioctl;
1da177e4
LT		 1684 }
1685
1686 /* Get MAC address. FIXME: read EEPROM */
1687 for (i = 0; i < MAC_ADDR_LEN; i++)
1688 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 1689 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 1690
1691 dev->open = rtl8169_open;
1692 dev->hard_start_xmit = rtl8169_start_xmit;
1693 dev->get_stats = rtl8169_get_stats;
1694 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1695 dev->stop = rtl8169_close;
1696 dev->tx_timeout = rtl8169_tx_timeout;
07ce4064 1697 dev->set_multicast_list = rtl_set_rx_mode;
1da177e4
LT		 1698 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1699 dev->irq = pdev->irq;
1700 dev->base_addr = (unsigned long) ioaddr;
1701 dev->change_mtu = rtl8169_change_mtu;
1702
1703#ifdef CONFIG_R8169_NAPI
1704 dev->poll = rtl8169_poll;
1705 dev->weight = R8169_NAPI_WEIGHT;
1da177e4
LT		 1706#endif
1707
1708#ifdef CONFIG_R8169_VLAN
1709 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1710 dev->vlan_rx_register = rtl8169_vlan_rx_register;
1da177e4
LT		 1711#endif
1712
1713#ifdef CONFIG_NET_POLL_CONTROLLER
1714 dev->poll_controller = rtl8169_netpoll;
1715#endif
1716
1717 tp->intr_mask = 0xffff;
1718 tp->pci_dev = pdev;
1719 tp->mmio_addr = ioaddr;
0e485150
FR		 1720 tp->align = cfg->align;
1721 tp->hw_start = cfg->hw_start;
1722 tp->intr_event = cfg->intr_event;
1723 tp->napi_event = cfg->napi_event;
1da177e4 1724
2efa53f3
FR		 1725 init_timer(&tp->timer);
1726 tp->timer.data = (unsigned long) dev;
1727 tp->timer.function = rtl8169_phy_timer;
1728
1da177e4
LT		 1729 spin_lock_init(&tp->lock);
1730
1731 rc = register_netdev(dev);
4ff96fa6
FR		 1732 if (rc < 0)
1733 goto err_out_unmap_5;
1da177e4
LT		 1734
1735 pci_set_drvdata(pdev, dev);
1736
b57b7e5a
SH		 1737 if (netif_msg_probe(tp)) {
1738 printk(KERN_INFO "%s: %s at 0x%lx, "
1739 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1740 "IRQ %d\n",
1741 dev->name,
bcf0bf90 1742 rtl_chip_info[tp->chipset].name,
b57b7e5a
SH		 1743 dev->base_addr,
1744 dev->dev_addr[0], dev->dev_addr[1],
1745 dev->dev_addr[2], dev->dev_addr[3],
1746 dev->dev_addr[4], dev->dev_addr[5], dev->irq);
1747 }
1da177e4 1748
4ff96fa6 1749 rtl8169_init_phy(dev, tp);
1da177e4 1750
4ff96fa6
FR		 1751out:
1752 return rc;
1da177e4 1753
4ff96fa6
FR		 1754err_out_unmap_5:
1755 iounmap(ioaddr);
1756err_out_free_res_4:
1757 pci_release_regions(pdev);
1758err_out_mwi_3:
1759 pci_clear_mwi(pdev);
1760err_out_disable_2:
1761 pci_disable_device(pdev);
1762err_out_free_dev_1:
1763 free_netdev(dev);
1764 goto out;
1da177e4
LT		 1765}
1766
1767static void __devexit
1768rtl8169_remove_one(struct pci_dev *pdev)
1769{
1770 struct net_device *dev = pci_get_drvdata(pdev);
1771 struct rtl8169_private *tp = netdev_priv(dev);
1772
1773 assert(dev != NULL);
1774 assert(tp != NULL);
1775
eb2a021c
FR		 1776 flush_scheduled_work();
1777
1da177e4
LT		 1778 unregister_netdev(dev);
1779 rtl8169_release_board(pdev, dev, tp->mmio_addr);
1780 pci_set_drvdata(pdev, NULL);
1781}
1782
1da177e4
LT		 1783static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
1784 struct net_device *dev)
1785{
1786 unsigned int mtu = dev->mtu;
1787
1788 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1789}
1790
1791static int rtl8169_open(struct net_device *dev)
1792{
1793 struct rtl8169_private *tp = netdev_priv(dev);
1794 struct pci_dev *pdev = tp->pci_dev;
99f252b0 1795 int retval = -ENOMEM;
1da177e4 1796
1da177e4 1797
99f252b0 1798 rtl8169_set_rxbufsize(tp, dev);
1da177e4
LT		 1799
1800 /*
1801 * Rx and Tx desscriptors needs 256 bytes alignment.
1802 * pci_alloc_consistent provides more.
1803 */
1804 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1805 &tp->TxPhyAddr);
1806 if (!tp->TxDescArray)
99f252b0 1807 goto out;
1da177e4
LT		 1808
1809 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1810 &tp->RxPhyAddr);
1811 if (!tp->RxDescArray)
99f252b0 1812 goto err_free_tx_0;
1da177e4
LT		 1813
1814 retval = rtl8169_init_ring(dev);
1815 if (retval < 0)
99f252b0 1816 goto err_free_rx_1;
1da177e4 1817
c4028958 1818 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 1819
99f252b0
FR		 1820 smp_mb();
1821
1822 retval = request_irq(dev->irq, rtl8169_interrupt, IRQF_SHARED,
1823 dev->name, dev);
1824 if (retval < 0)
1825 goto err_release_ring_2;
1826
07ce4064 1827 rtl_hw_start(dev);
1da177e4
LT		 1828
1829 rtl8169_request_timer(dev);
1830
1831 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1832out:
1833 return retval;
1834
99f252b0
FR		 1835err_release_ring_2:
1836 rtl8169_rx_clear(tp);
1837err_free_rx_1:
1da177e4
LT		 1838 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1839 tp->RxPhyAddr);
99f252b0 1840err_free_tx_0:
1da177e4
LT		 1841 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1842 tp->TxPhyAddr);
1da177e4
LT		 1843 goto out;
1844}
1845
1846static void rtl8169_hw_reset(void __iomem *ioaddr)
1847{
1848 /* Disable interrupts */
1849 rtl8169_irq_mask_and_ack(ioaddr);
1850
1851 /* Reset the chipset */
1852 RTL_W8(ChipCmd, CmdReset);
1853
1854 /* PCI commit */
1855 RTL_R8(ChipCmd);
1856}
1857
7f796d83 1858static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 1859{
1860 void __iomem *ioaddr = tp->mmio_addr;
1861 u32 cfg = rtl8169_rx_config;
1862
1863 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1864 RTL_W32(RxConfig, cfg);
1865
1866 /* Set DMA burst size and Interframe Gap Time */
1867 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
1868 (InterFrameGap << TxInterFrameGapShift));
1869}
1870
07ce4064 1871static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 1872{
1873 struct rtl8169_private *tp = netdev_priv(dev);
1874 void __iomem *ioaddr = tp->mmio_addr;
1875 u32 i;
1876
1877 /* Soft reset the chip. */
1878 RTL_W8(ChipCmd, CmdReset);
1879
1880 /* Check that the chip has finished the reset. */
b518fa8e 1881 for (i = 100; i > 0; i--) {
1da177e4
LT		 1882 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1883 break;
b518fa8e 1884 msleep_interruptible(1);
1da177e4
LT		 1885 }
1886
07ce4064
FR		 1887 tp->hw_start(dev);
1888
07ce4064
FR		 1889 netif_start_queue(dev);
1890}
1891
1892
7f796d83
FR		 1893static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
1894 void __iomem *ioaddr)
1895{
1896 /*
1897 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
1898 * register to be written before TxDescAddrLow to work.
1899 * Switching from MMIO to I/O access fixes the issue as well.
1900 */
1901 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
1902 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
1903 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
1904 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
1905}
1906
1907static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
1908{
1909 u16 cmd;
1910
1911 cmd = RTL_R16(CPlusCmd);
1912 RTL_W16(CPlusCmd, cmd);
1913 return cmd;
1914}
1915
1916static void rtl_set_rx_max_size(void __iomem *ioaddr)
1917{
1918 /* Low hurts. Let's disable the filtering. */
1919 RTL_W16(RxMaxSize, 16383);
1920}
1921
6dccd16b
FR		 1922static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
1923{
1924 struct {
1925 u32 mac_version;
1926 u32 clk;
1927 u32 val;
1928 } cfg2_info [] = {
1929 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
1930 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
1931 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
1932 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
1933 }, *p = cfg2_info;
1934 unsigned int i;
1935 u32 clk;
1936
1937 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
1938 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++) {
1939 if ((p->mac_version == mac_version) && (p->clk == clk)) {
1940 RTL_W32(0x7c, p->val);
1941 break;
1942 }
1943 }
1944}
1945
07ce4064
FR		 1946static void rtl_hw_start_8169(struct net_device *dev)
1947{
1948 struct rtl8169_private *tp = netdev_priv(dev);
1949 void __iomem *ioaddr = tp->mmio_addr;
1950 struct pci_dev *pdev = tp->pci_dev;
07ce4064 1951
9cb427b6
FR		 1952 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
1953 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
1954 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
1955 }
1956
1da177e4 1957 RTL_W8(Cfg9346, Cfg9346_Unlock);
9cb427b6
FR		 1958 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
1959 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1960 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
1961 (tp->mac_version == RTL_GIGA_MAC_VER_04))
1962 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1963
1da177e4
LT		 1964 RTL_W8(EarlyTxThres, EarlyTxThld);
1965
7f796d83 1966 rtl_set_rx_max_size(ioaddr);
1da177e4 1967
6dccd16b 1968 rtl_set_rx_tx_config_registers(tp);
1da177e4 1969
7f796d83 1970 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 1971
bcf0bf90
FR		 1972 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1973 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1da177e4
LT		 1974 dprintk(KERN_INFO PFX "Set MAC Reg C+CR Offset 0xE0. "
1975 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 1976 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 1977 }
1978
bcf0bf90
FR		 1979 RTL_W16(CPlusCmd, tp->cp_cmd);
1980
6dccd16b
FR		 1981 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
1982
1da177e4
LT		 1983 /*
1984 * Undocumented corner. Supposedly:
1985 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
1986 */
1987 RTL_W16(IntrMitigate, 0x0000);
1988
7f796d83 1989 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 1990
1da177e4 1991 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 1992
1993 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
1994 RTL_R8(IntrMask);
1da177e4
LT		 1995
1996 RTL_W32(RxMissed, 0);
1997
07ce4064 1998 rtl_set_rx_mode(dev);
1da177e4
LT		 1999
2000 /* no early-rx interrupts */
2001 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 2002
2003 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 2004 RTL_W16(IntrMask, tp->intr_event);
6dccd16b
FR		 2005
2006 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
07ce4064 2007}
1da177e4 2008
07ce4064
FR		 2009static void rtl_hw_start_8168(struct net_device *dev)
2010{
2dd99530
FR		 2011 struct rtl8169_private *tp = netdev_priv(dev);
2012 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 2013 struct pci_dev *pdev = tp->pci_dev;
2014 u8 ctl;
2dd99530
FR		 2015
2016 RTL_W8(Cfg9346, Cfg9346_Unlock);
2017
2018 RTL_W8(EarlyTxThres, EarlyTxThld);
2019
2020 rtl_set_rx_max_size(ioaddr);
2021
0e485150
FR		 2022 rtl_set_rx_tx_config_registers(tp);
2023
2024 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 2025
2026 RTL_W16(CPlusCmd, tp->cp_cmd);
2027
0e485150
FR		 2028 /* Tx performance tweak. */
2029 pci_read_config_byte(pdev, 0x69, &ctl);
2030 ctl = (ctl & ~0x70) | 0x50;
2031 pci_write_config_byte(pdev, 0x69, ctl);
2dd99530 2032
0e485150 2033 RTL_W16(IntrMitigate, 0x5151);
2dd99530 2034
0e485150
FR		 2035 /* Work around for RxFIFO overflow. */
2036 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2037 tp->intr_event |= RxFIFOOver | PCSTimeout;
2038 tp->intr_event &= ~RxOverflow;
2039 }
2040
2041 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530
FR		 2042
2043 RTL_W8(Cfg9346, Cfg9346_Lock);
2044
2045 RTL_R8(IntrMask);
2046
2047 RTL_W32(RxMissed, 0);
2048
2049 rtl_set_rx_mode(dev);
2050
0e485150
FR		 2051 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2052
2dd99530 2053 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 2054
0e485150 2055 RTL_W16(IntrMask, tp->intr_event);
07ce4064 2056}
1da177e4 2057
07ce4064
FR		 2058static void rtl_hw_start_8101(struct net_device *dev)
2059{
cdf1a608
FR		 2060 struct rtl8169_private *tp = netdev_priv(dev);
2061 void __iomem *ioaddr = tp->mmio_addr;
2062 struct pci_dev *pdev = tp->pci_dev;
2063
2064 if (tp->mac_version == RTL_GIGA_MAC_VER_13) {
2065 pci_write_config_word(pdev, 0x68, 0x00);
2066 pci_write_config_word(pdev, 0x69, 0x08);
2067 }
2068
2069 RTL_W8(Cfg9346, Cfg9346_Unlock);
2070
2071 RTL_W8(EarlyTxThres, EarlyTxThld);
2072
2073 rtl_set_rx_max_size(ioaddr);
2074
2075 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2076
2077 RTL_W16(CPlusCmd, tp->cp_cmd);
2078
2079 RTL_W16(IntrMitigate, 0x0000);
2080
2081 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2082
2083 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2084 rtl_set_rx_tx_config_registers(tp);
2085
2086 RTL_W8(Cfg9346, Cfg9346_Lock);
2087
2088 RTL_R8(IntrMask);
2089
2090 RTL_W32(RxMissed, 0);
2091
2092 rtl_set_rx_mode(dev);
2093
0e485150
FR		 2094 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2095
cdf1a608 2096 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 2097
0e485150 2098 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 2099}
2100
2101static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2102{
2103 struct rtl8169_private *tp = netdev_priv(dev);
2104 int ret = 0;
2105
2106 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2107 return -EINVAL;
2108
2109 dev->mtu = new_mtu;
2110
2111 if (!netif_running(dev))
2112 goto out;
2113
2114 rtl8169_down(dev);
2115
2116 rtl8169_set_rxbufsize(tp, dev);
2117
2118 ret = rtl8169_init_ring(dev);
2119 if (ret < 0)
2120 goto out;
2121
2122 netif_poll_enable(dev);
2123
07ce4064 2124 rtl_hw_start(dev);
1da177e4
LT		 2125
2126 rtl8169_request_timer(dev);
2127
2128out:
2129 return ret;
2130}
2131
2132static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2133{
2134 desc->addr = 0x0badbadbadbadbadull;
2135 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2136}
2137
2138static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2139 struct sk_buff **sk_buff, struct RxDesc *desc)
2140{
2141 struct pci_dev *pdev = tp->pci_dev;
2142
2143 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2144 PCI_DMA_FROMDEVICE);
2145 dev_kfree_skb(*sk_buff);
2146 *sk_buff = NULL;
2147 rtl8169_make_unusable_by_asic(desc);
2148}
2149
2150static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2151{
2152 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2153
2154 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2155}
2156
2157static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2158 u32 rx_buf_sz)
2159{
2160 desc->addr = cpu_to_le64(mapping);
2161 wmb();
2162 rtl8169_mark_to_asic(desc, rx_buf_sz);
2163}
2164
15d31758
SH		 2165static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2166 struct net_device *dev,
2167 struct RxDesc *desc, int rx_buf_sz,
2168 unsigned int align)
1da177e4
LT		 2169{
2170 struct sk_buff *skb;
2171 dma_addr_t mapping;
1da177e4 2172
15d31758 2173 skb = netdev_alloc_skb(dev, rx_buf_sz + align);
1da177e4
LT		 2174 if (!skb)
2175 goto err_out;
2176
dcb92f88 2177 skb_reserve(skb, (align - 1) & (unsigned long)skb->data);
1da177e4 2178
689be439 2179 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
1da177e4
LT		 2180 PCI_DMA_FROMDEVICE);
2181
2182 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
1da177e4 2183out:
15d31758 2184 return skb;
1da177e4
LT		 2185
2186err_out:
1da177e4
LT		 2187 rtl8169_make_unusable_by_asic(desc);
2188 goto out;
2189}
2190
2191static void rtl8169_rx_clear(struct rtl8169_private *tp)
2192{
2193 int i;
2194
2195 for (i = 0; i < NUM_RX_DESC; i++) {
2196 if (tp->Rx_skbuff[i]) {
2197 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2198 tp->RxDescArray + i);
2199 }
2200 }
2201}
2202
2203static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2204 u32 start, u32 end)
2205{
2206 u32 cur;
5b0384f4 2207
4ae47c2d 2208 for (cur = start; end - cur != 0; cur++) {
15d31758
SH		 2209 struct sk_buff *skb;
2210 unsigned int i = cur % NUM_RX_DESC;
1da177e4 2211
4ae47c2d
FR		 2212 WARN_ON((s32)(end - cur) < 0);
2213
1da177e4
LT		 2214 if (tp->Rx_skbuff[i])
2215 continue;
bcf0bf90 2216
15d31758
SH		 2217 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2218 tp->RxDescArray + i,
2219 tp->rx_buf_sz, tp->align);
2220 if (!skb)
1da177e4 2221 break;
15d31758
SH		 2222
2223 tp->Rx_skbuff[i] = skb;
1da177e4
LT		 2224 }
2225 return cur - start;
2226}
2227
2228static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2229{
2230 desc->opts1 |= cpu_to_le32(RingEnd);
2231}
2232
2233static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2234{
2235 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2236}
2237
2238static int rtl8169_init_ring(struct net_device *dev)
2239{
2240 struct rtl8169_private *tp = netdev_priv(dev);
2241
2242 rtl8169_init_ring_indexes(tp);
2243
2244 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2245 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2246
2247 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2248 goto err_out;
2249
2250 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2251
2252 return 0;
2253
2254err_out:
2255 rtl8169_rx_clear(tp);
2256 return -ENOMEM;
2257}
2258
2259static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2260 struct TxDesc *desc)
2261{
2262 unsigned int len = tx_skb->len;
2263
2264 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2265 desc->opts1 = 0x00;
2266 desc->opts2 = 0x00;
2267 desc->addr = 0x00;
2268 tx_skb->len = 0;
2269}
2270
2271static void rtl8169_tx_clear(struct rtl8169_private *tp)
2272{
2273 unsigned int i;
2274
2275 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2276 unsigned int entry = i % NUM_TX_DESC;
2277 struct ring_info *tx_skb = tp->tx_skb + entry;
2278 unsigned int len = tx_skb->len;
2279
2280 if (len) {
2281 struct sk_buff *skb = tx_skb->skb;
2282
2283 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2284 tp->TxDescArray + entry);
2285 if (skb) {
2286 dev_kfree_skb(skb);
2287 tx_skb->skb = NULL;
2288 }
2289 tp->stats.tx_dropped++;
2290 }
2291 }
2292 tp->cur_tx = tp->dirty_tx = 0;
2293}
2294
c4028958 2295static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 2296{
2297 struct rtl8169_private *tp = netdev_priv(dev);
2298
c4028958 2299 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 2300 schedule_delayed_work(&tp->task, 4);
2301}
2302
2303static void rtl8169_wait_for_quiescence(struct net_device *dev)
2304{
2305 struct rtl8169_private *tp = netdev_priv(dev);
2306 void __iomem *ioaddr = tp->mmio_addr;
2307
2308 synchronize_irq(dev->irq);
2309
2310 /* Wait for any pending NAPI task to complete */
2311 netif_poll_disable(dev);
2312
2313 rtl8169_irq_mask_and_ack(ioaddr);
2314
2315 netif_poll_enable(dev);
2316}
2317
c4028958 2318static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 2319{
c4028958
DH		 2320 struct rtl8169_private *tp =
2321 container_of(work, struct rtl8169_private, task.work);
2322 struct net_device *dev = tp->dev;
1da177e4
LT		 2323 int ret;
2324
eb2a021c
FR		 2325 rtnl_lock();
2326
2327 if (!netif_running(dev))
2328 goto out_unlock;
2329
2330 rtl8169_wait_for_quiescence(dev);
2331 rtl8169_close(dev);
1da177e4
LT		 2332
2333 ret = rtl8169_open(dev);
2334 if (unlikely(ret < 0)) {
2335 if (net_ratelimit()) {
b57b7e5a
SH		 2336 struct rtl8169_private *tp = netdev_priv(dev);
2337
2338 if (netif_msg_drv(tp)) {
2339 printk(PFX KERN_ERR
2340 "%s: reinit failure (status = %d)."
2341 " Rescheduling.\n", dev->name, ret);
2342 }
1da177e4
LT		 2343 }
2344 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2345 }
eb2a021c
FR		 2346
2347out_unlock:
2348 rtnl_unlock();
1da177e4
LT		 2349}
2350
c4028958 2351static void rtl8169_reset_task(struct work_struct *work)
1da177e4 2352{
c4028958
DH		 2353 struct rtl8169_private *tp =
2354 container_of(work, struct rtl8169_private, task.work);
2355 struct net_device *dev = tp->dev;
1da177e4 2356
eb2a021c
FR		 2357 rtnl_lock();
2358
1da177e4 2359 if (!netif_running(dev))
eb2a021c 2360 goto out_unlock;
1da177e4
LT		 2361
2362 rtl8169_wait_for_quiescence(dev);
2363
2364 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr);
2365 rtl8169_tx_clear(tp);
2366
2367 if (tp->dirty_rx == tp->cur_rx) {
2368 rtl8169_init_ring_indexes(tp);
07ce4064 2369 rtl_hw_start(dev);
1da177e4
LT		 2370 netif_wake_queue(dev);
2371 } else {
2372 if (net_ratelimit()) {
b57b7e5a
SH		 2373 struct rtl8169_private *tp = netdev_priv(dev);
2374
2375 if (netif_msg_intr(tp)) {
2376 printk(PFX KERN_EMERG
2377 "%s: Rx buffers shortage\n", dev->name);
2378 }
1da177e4
LT		 2379 }
2380 rtl8169_schedule_work(dev, rtl8169_reset_task);
2381 }
eb2a021c
FR		 2382
2383out_unlock:
2384 rtnl_unlock();
1da177e4
LT		 2385}
2386
2387static void rtl8169_tx_timeout(struct net_device *dev)
2388{
2389 struct rtl8169_private *tp = netdev_priv(dev);
2390
2391 rtl8169_hw_reset(tp->mmio_addr);
2392
2393 /* Let's wait a bit while any (async) irq lands on */
2394 rtl8169_schedule_work(dev, rtl8169_reset_task);
2395}
2396
2397static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2398 u32 opts1)
2399{
2400 struct skb_shared_info *info = skb_shinfo(skb);
2401 unsigned int cur_frag, entry;
2402 struct TxDesc *txd;
2403
2404 entry = tp->cur_tx;
2405 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2406 skb_frag_t *frag = info->frags + cur_frag;
2407 dma_addr_t mapping;
2408 u32 status, len;
2409 void *addr;
2410
2411 entry = (entry + 1) % NUM_TX_DESC;
2412
2413 txd = tp->TxDescArray + entry;
2414 len = frag->size;
2415 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2416 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2417
2418 /* anti gcc 2.95.3 bugware (sic) */
2419 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2420
2421 txd->opts1 = cpu_to_le32(status);
2422 txd->addr = cpu_to_le64(mapping);
2423
2424 tp->tx_skb[entry].len = len;
2425 }
2426
2427 if (cur_frag) {
2428 tp->tx_skb[entry].skb = skb;
2429 txd->opts1 |= cpu_to_le32(LastFrag);
2430 }
2431
2432 return cur_frag;
2433}
2434
2435static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2436{
2437 if (dev->features & NETIF_F_TSO) {
7967168c 2438 u32 mss = skb_shinfo(skb)->gso_size;
1da177e4
LT		 2439
2440 if (mss)
2441 return LargeSend | ((mss & MSSMask) << MSSShift);
2442 }
84fa7933 2443 if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 2444 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 2445
2446 if (ip->protocol == IPPROTO_TCP)
2447 return IPCS | TCPCS;
2448 else if (ip->protocol == IPPROTO_UDP)
2449 return IPCS | UDPCS;
2450 WARN_ON(1); /* we need a WARN() */
2451 }
2452 return 0;
2453}
2454
2455static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2456{
2457 struct rtl8169_private *tp = netdev_priv(dev);
2458 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2459 struct TxDesc *txd = tp->TxDescArray + entry;
2460 void __iomem *ioaddr = tp->mmio_addr;
2461 dma_addr_t mapping;
2462 u32 status, len;
2463 u32 opts1;
188f4af0 2464 int ret = NETDEV_TX_OK;
5b0384f4 2465
1da177e4 2466 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
b57b7e5a
SH		 2467 if (netif_msg_drv(tp)) {
2468 printk(KERN_ERR
2469 "%s: BUG! Tx Ring full when queue awake!\n",
2470 dev->name);
2471 }
1da177e4
LT		 2472 goto err_stop;
2473 }
2474
2475 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2476 goto err_stop;
2477
2478 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2479
2480 frags = rtl8169_xmit_frags(tp, skb, opts1);
2481 if (frags) {
2482 len = skb_headlen(skb);
2483 opts1 |= FirstFrag;
2484 } else {
2485 len = skb->len;
2486
2487 if (unlikely(len < ETH_ZLEN)) {
5b057c6b 2488 if (skb_padto(skb, ETH_ZLEN))
1da177e4
LT		 2489 goto err_update_stats;
2490 len = ETH_ZLEN;
2491 }
2492
2493 opts1 |= FirstFrag | LastFrag;
2494 tp->tx_skb[entry].skb = skb;
2495 }
2496
2497 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2498
2499 tp->tx_skb[entry].len = len;
2500 txd->addr = cpu_to_le64(mapping);
2501 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2502
2503 wmb();
2504
2505 /* anti gcc 2.95.3 bugware (sic) */
2506 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2507 txd->opts1 = cpu_to_le32(status);
2508
2509 dev->trans_start = jiffies;
2510
2511 tp->cur_tx += frags + 1;
2512
2513 smp_wmb();
2514
2515 RTL_W8(TxPoll, 0x40); /* set polling bit */
2516
2517 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2518 netif_stop_queue(dev);
2519 smp_rmb();
2520 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2521 netif_wake_queue(dev);
2522 }
2523
2524out:
2525 return ret;
2526
2527err_stop:
2528 netif_stop_queue(dev);
188f4af0 2529 ret = NETDEV_TX_BUSY;
1da177e4
LT		 2530err_update_stats:
2531 tp->stats.tx_dropped++;
2532 goto out;
2533}
2534
2535static void rtl8169_pcierr_interrupt(struct net_device *dev)
2536{
2537 struct rtl8169_private *tp = netdev_priv(dev);
2538 struct pci_dev *pdev = tp->pci_dev;
2539 void __iomem *ioaddr = tp->mmio_addr;
2540 u16 pci_status, pci_cmd;
2541
2542 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2543 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2544
b57b7e5a
SH		 2545 if (netif_msg_intr(tp)) {
2546 printk(KERN_ERR
2547 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2548 dev->name, pci_cmd, pci_status);
2549 }
1da177e4
LT		 2550
2551 /*
2552 * The recovery sequence below admits a very elaborated explanation:
2553 * - it seems to work;
d03902b8
FR		 2554 * - I did not see what else could be done;
2555 * - it makes iop3xx happy.
1da177e4
LT		 2556 *
2557 * Feel free to adjust to your needs.
2558 */
a27993f3 2559 if (pdev->broken_parity_status)
d03902b8
FR		 2560 pci_cmd &= ~PCI_COMMAND_PARITY;
2561 else
2562 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
2563
2564 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 2565
2566 pci_write_config_word(pdev, PCI_STATUS,
2567 pci_status & (PCI_STATUS_DETECTED_PARITY |
2568 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2569 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2570
2571 /* The infamous DAC f*ckup only happens at boot time */
2572 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
b57b7e5a
SH		 2573 if (netif_msg_intr(tp))
2574 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
1da177e4
LT		 2575 tp->cp_cmd &= ~PCIDAC;
2576 RTL_W16(CPlusCmd, tp->cp_cmd);
2577 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 2578 }
2579
2580 rtl8169_hw_reset(ioaddr);
d03902b8
FR		 2581
2582 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 2583}
2584
2585static void
2586rtl8169_tx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
2587 void __iomem *ioaddr)
2588{
2589 unsigned int dirty_tx, tx_left;
2590
2591 assert(dev != NULL);
2592 assert(tp != NULL);
2593 assert(ioaddr != NULL);
2594
2595 dirty_tx = tp->dirty_tx;
2596 smp_rmb();
2597 tx_left = tp->cur_tx - dirty_tx;
2598
2599 while (tx_left > 0) {
2600 unsigned int entry = dirty_tx % NUM_TX_DESC;
2601 struct ring_info *tx_skb = tp->tx_skb + entry;
2602 u32 len = tx_skb->len;
2603 u32 status;
2604
2605 rmb();
2606 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2607 if (status & DescOwn)
2608 break;
2609
2610 tp->stats.tx_bytes += len;
2611 tp->stats.tx_packets++;
2612
2613 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2614
2615 if (status & LastFrag) {
2616 dev_kfree_skb_irq(tx_skb->skb);
2617 tx_skb->skb = NULL;
2618 }
2619 dirty_tx++;
2620 tx_left--;
2621 }
2622
2623 if (tp->dirty_tx != dirty_tx) {
2624 tp->dirty_tx = dirty_tx;
2625 smp_wmb();
2626 if (netif_queue_stopped(dev) &&
2627 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2628 netif_wake_queue(dev);
2629 }
2630 }
2631}
2632
126fa4b9
FR		 2633static inline int rtl8169_fragmented_frame(u32 status)
2634{
2635 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2636}
2637
1da177e4
LT		 2638static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2639{
2640 u32 opts1 = le32_to_cpu(desc->opts1);
2641 u32 status = opts1 & RxProtoMask;
2642
2643 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2644 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2645 ((status == RxProtoIP) && !(opts1 & IPFail)))
2646 skb->ip_summed = CHECKSUM_UNNECESSARY;
2647 else
2648 skb->ip_summed = CHECKSUM_NONE;
2649}
2650
b449655f 2651static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff, int pkt_size,
86402234 2652 struct pci_dev *pdev, dma_addr_t addr)
1da177e4 2653{
b449655f
SH		 2654 struct sk_buff *skb;
2655 bool done = false;
1da177e4 2656
b449655f
SH		 2657 if (pkt_size >= rx_copybreak)
2658 goto out;
1da177e4 2659
86402234 2660 skb = dev_alloc_skb(pkt_size + NET_IP_ALIGN);
b449655f
SH		 2661 if (!skb)
2662 goto out;
2663
2664 pci_dma_sync_single_for_cpu(pdev, addr, pkt_size, PCI_DMA_FROMDEVICE);
86402234 2665 skb_reserve(skb, NET_IP_ALIGN);
b449655f
SH		 2666 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
2667 *sk_buff = skb;
2668 done = true;
2669out:
2670 return done;
1da177e4
LT		 2671}
2672
2673static int
2674rtl8169_rx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
2675 void __iomem *ioaddr)
2676{
2677 unsigned int cur_rx, rx_left;
2678 unsigned int delta, count;
2679
2680 assert(dev != NULL);
2681 assert(tp != NULL);
2682 assert(ioaddr != NULL);
2683
2684 cur_rx = tp->cur_rx;
2685 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
2686 rx_left = rtl8169_rx_quota(rx_left, (u32) dev->quota);
2687
4dcb7d33 2688 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 2689 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 2690 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 2691 u32 status;
2692
2693 rmb();
126fa4b9 2694 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 2695
2696 if (status & DescOwn)
2697 break;
4dcb7d33 2698 if (unlikely(status & RxRES)) {
b57b7e5a
SH		 2699 if (netif_msg_rx_err(tp)) {
2700 printk(KERN_INFO
2701 "%s: Rx ERROR. status = %08x\n",
2702 dev->name, status);
2703 }
1da177e4
LT		 2704 tp->stats.rx_errors++;
2705 if (status & (RxRWT | RxRUNT))
2706 tp->stats.rx_length_errors++;
2707 if (status & RxCRC)
2708 tp->stats.rx_crc_errors++;
9dccf611
FR		 2709 if (status & RxFOVF) {
2710 rtl8169_schedule_work(dev, rtl8169_reset_task);
2711 tp->stats.rx_fifo_errors++;
2712 }
126fa4b9 2713 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
1da177e4 2714 } else {
1da177e4 2715 struct sk_buff *skb = tp->Rx_skbuff[entry];
b449655f 2716 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 2717 int pkt_size = (status & 0x00001FFF) - 4;
b449655f 2718 struct pci_dev *pdev = tp->pci_dev;
1da177e4 2719
126fa4b9
FR		 2720 /*
2721 * The driver does not support incoming fragmented
2722 * frames. They are seen as a symptom of over-mtu
2723 * sized frames.
2724 */
2725 if (unlikely(rtl8169_fragmented_frame(status))) {
2726 tp->stats.rx_dropped++;
2727 tp->stats.rx_length_errors++;
2728 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4dcb7d33 2729 continue;
126fa4b9
FR		 2730 }
2731
1da177e4 2732 rtl8169_rx_csum(skb, desc);
bcf0bf90 2733
86402234 2734 if (rtl8169_try_rx_copy(&skb, pkt_size, pdev, addr)) {
b449655f
SH		 2735 pci_dma_sync_single_for_device(pdev, addr,
2736 pkt_size, PCI_DMA_FROMDEVICE);
2737 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2738 } else {
2739 pci_unmap_single(pdev, addr, pkt_size,
2740 PCI_DMA_FROMDEVICE);
1da177e4
LT		 2741 tp->Rx_skbuff[entry] = NULL;
2742 }
2743
1da177e4
LT		 2744 skb_put(skb, pkt_size);
2745 skb->protocol = eth_type_trans(skb, dev);
2746
2747 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
2748 rtl8169_rx_skb(skb);
2749
2750 dev->last_rx = jiffies;
2751 tp->stats.rx_bytes += pkt_size;
2752 tp->stats.rx_packets++;
2753 }
6dccd16b
FR		 2754
2755 /* Work around for AMD plateform. */
2756 if ((desc->opts2 & 0xfffe000) &&
2757 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
2758 desc->opts2 = 0;
2759 cur_rx++;
2760 }
1da177e4
LT		 2761 }
2762
2763 count = cur_rx - tp->cur_rx;
2764 tp->cur_rx = cur_rx;
2765
2766 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
b57b7e5a 2767 if (!delta && count && netif_msg_intr(tp))
1da177e4
LT		 2768 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
2769 tp->dirty_rx += delta;
2770
2771 /*
2772 * FIXME: until there is periodic timer to try and refill the ring,
2773 * a temporary shortage may definitely kill the Rx process.
2774 * - disable the asic to try and avoid an overflow and kick it again
2775 * after refill ?
2776 * - how do others driver handle this condition (Uh oh...).
2777 */
b57b7e5a 2778 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
1da177e4
LT		 2779 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
2780
2781 return count;
2782}
2783
2784/* The interrupt handler does all of the Rx thread work and cleans up after the Tx thread. */
2785static irqreturn_t
7d12e780 2786rtl8169_interrupt(int irq, void *dev_instance)
1da177e4
LT		 2787{
2788 struct net_device *dev = (struct net_device *) dev_instance;
2789 struct rtl8169_private *tp = netdev_priv(dev);
2790 int boguscnt = max_interrupt_work;
2791 void __iomem *ioaddr = tp->mmio_addr;
2792 int status;
2793 int handled = 0;
2794
2795 do {
2796 status = RTL_R16(IntrStatus);
2797
2798 /* hotplug/major error/no more work/shared irq */
2799 if ((status == 0xFFFF) || !status)
2800 break;
2801
2802 handled = 1;
2803
2804 if (unlikely(!netif_running(dev))) {
2805 rtl8169_asic_down(ioaddr);
2806 goto out;
2807 }
2808
2809 status &= tp->intr_mask;
2810 RTL_W16(IntrStatus,
2811 (status & RxFIFOOver) ? (status | RxOverflow) : status);
2812
0e485150
FR		 2813 if (!(status & tp->intr_event))
2814 break;
2815
2816 /* Work around for rx fifo overflow */
2817 if (unlikely(status & RxFIFOOver) &&
2818 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
2819 netif_stop_queue(dev);
2820 rtl8169_tx_timeout(dev);
1da177e4 2821 break;
0e485150 2822 }
1da177e4
LT		 2823
2824 if (unlikely(status & SYSErr)) {
2825 rtl8169_pcierr_interrupt(dev);
2826 break;
2827 }
2828
2829 if (status & LinkChg)
2830 rtl8169_check_link_status(dev, tp, ioaddr);
2831
2832#ifdef CONFIG_R8169_NAPI
0e485150
FR		 2833 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
2834 tp->intr_mask = ~tp->napi_event;
1da177e4
LT		 2835
2836 if (likely(netif_rx_schedule_prep(dev)))
2837 __netif_rx_schedule(dev);
b57b7e5a 2838 else if (netif_msg_intr(tp)) {
1da177e4 2839 printk(KERN_INFO "%s: interrupt %04x taken in poll\n",
5b0384f4 2840 dev->name, status);
1da177e4
LT		 2841 }
2842 break;
2843#else
2844 /* Rx interrupt */
2845 if (status & (RxOK | RxOverflow | RxFIFOOver)) {
2846 rtl8169_rx_interrupt(dev, tp, ioaddr);
2847 }
2848 /* Tx interrupt */
2849 if (status & (TxOK | TxErr))
2850 rtl8169_tx_interrupt(dev, tp, ioaddr);
2851#endif
2852
2853 boguscnt--;
2854 } while (boguscnt > 0);
2855
2856 if (boguscnt <= 0) {
7c8b2eb4 2857 if (netif_msg_intr(tp) && net_ratelimit() ) {
b57b7e5a
SH		 2858 printk(KERN_WARNING
2859 "%s: Too much work at interrupt!\n", dev->name);
2860 }
1da177e4
LT		 2861 /* Clear all interrupt sources. */
2862 RTL_W16(IntrStatus, 0xffff);
2863 }
2864out:
2865 return IRQ_RETVAL(handled);
2866}
2867
2868#ifdef CONFIG_R8169_NAPI
2869static int rtl8169_poll(struct net_device *dev, int *budget)
2870{
2871 unsigned int work_done, work_to_do = min(*budget, dev->quota);
2872 struct rtl8169_private *tp = netdev_priv(dev);
2873 void __iomem *ioaddr = tp->mmio_addr;
2874
2875 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr);
2876 rtl8169_tx_interrupt(dev, tp, ioaddr);
2877
2878 *budget -= work_done;
2879 dev->quota -= work_done;
2880
2881 if (work_done < work_to_do) {
2882 netif_rx_complete(dev);
2883 tp->intr_mask = 0xffff;
2884 /*
2885 * 20040426: the barrier is not strictly required but the
2886 * behavior of the irq handler could be less predictable
2887 * without it. Btw, the lack of flush for the posted pci
2888 * write is safe - FR
2889 */
2890 smp_wmb();
0e485150 2891 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 2892 }
2893
2894 return (work_done >= work_to_do);
2895}
2896#endif
2897
2898static void rtl8169_down(struct net_device *dev)
2899{
2900 struct rtl8169_private *tp = netdev_priv(dev);
2901 void __iomem *ioaddr = tp->mmio_addr;
2902 unsigned int poll_locked = 0;
733b736c 2903 unsigned int intrmask;
1da177e4
LT		 2904
2905 rtl8169_delete_timer(dev);
2906
2907 netif_stop_queue(dev);
2908
1da177e4
LT		 2909core_down:
2910 spin_lock_irq(&tp->lock);
2911
2912 rtl8169_asic_down(ioaddr);
2913
2914 /* Update the error counts. */
2915 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2916 RTL_W32(RxMissed, 0);
2917
2918 spin_unlock_irq(&tp->lock);
2919
2920 synchronize_irq(dev->irq);
2921
2922 if (!poll_locked) {
2923 netif_poll_disable(dev);
2924 poll_locked++;
2925 }
2926
2927 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 2928 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4
LT		 2929
2930 /*
2931 * And now for the 50k$ question: are IRQ disabled or not ?
2932 *
2933 * Two paths lead here:
2934 * 1) dev->close
2935 * -> netif_running() is available to sync the current code and the
2936 * IRQ handler. See rtl8169_interrupt for details.
2937 * 2) dev->change_mtu
2938 * -> rtl8169_poll can not be issued again and re-enable the
2939 * interruptions. Let's simply issue the IRQ down sequence again.
733b736c
AP		 2940 *
2941 * No loop if hotpluged or major error (0xffff).
1da177e4 2942 */
733b736c
AP		 2943 intrmask = RTL_R16(IntrMask);
2944 if (intrmask && (intrmask != 0xffff))
1da177e4
LT		 2945 goto core_down;
2946
2947 rtl8169_tx_clear(tp);
2948
2949 rtl8169_rx_clear(tp);
2950}
2951
2952static int rtl8169_close(struct net_device *dev)
2953{
2954 struct rtl8169_private *tp = netdev_priv(dev);
2955 struct pci_dev *pdev = tp->pci_dev;
2956
2957 rtl8169_down(dev);
2958
2959 free_irq(dev->irq, dev);
2960
2961 netif_poll_enable(dev);
2962
2963 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2964 tp->RxPhyAddr);
2965 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2966 tp->TxPhyAddr);
2967 tp->TxDescArray = NULL;
2968 tp->RxDescArray = NULL;
2969
2970 return 0;
2971}
2972
07ce4064 2973static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 2974{
2975 struct rtl8169_private *tp = netdev_priv(dev);
2976 void __iomem *ioaddr = tp->mmio_addr;
2977 unsigned long flags;
2978 u32 mc_filter[2]; /* Multicast hash filter */
2979 int i, rx_mode;
2980 u32 tmp = 0;
2981
2982 if (dev->flags & IFF_PROMISC) {
2983 /* Unconditionally log net taps. */
b57b7e5a
SH		 2984 if (netif_msg_link(tp)) {
2985 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2986 dev->name);
2987 }
1da177e4
LT		 2988 rx_mode =
2989 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2990 AcceptAllPhys;
2991 mc_filter[1] = mc_filter[0] = 0xffffffff;
2992 } else if ((dev->mc_count > multicast_filter_limit)
2993 || (dev->flags & IFF_ALLMULTI)) {
2994 /* Too many to filter perfectly -- accept all multicasts. */
2995 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2996 mc_filter[1] = mc_filter[0] = 0xffffffff;
2997 } else {
2998 struct dev_mc_list *mclist;
2999 rx_mode = AcceptBroadcast | AcceptMyPhys;
3000 mc_filter[1] = mc_filter[0] = 0;
3001 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3002 i++, mclist = mclist->next) {
3003 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
3004 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
3005 rx_mode |= AcceptMulticast;
3006 }
3007 }
3008
3009 spin_lock_irqsave(&tp->lock, flags);
3010
3011 tmp = rtl8169_rx_config | rx_mode |
3012 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3013
bcf0bf90
FR		 3014 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
3015 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
3016 (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
3017 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
3018 (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
3019 mc_filter[0] = 0xffffffff;
3020 mc_filter[1] = 0xffffffff;
3021 }
3022
1da177e4
LT		 3023 RTL_W32(RxConfig, tmp);
3024 RTL_W32(MAR0 + 0, mc_filter[0]);
3025 RTL_W32(MAR0 + 4, mc_filter[1]);
3026
3027 spin_unlock_irqrestore(&tp->lock, flags);
3028}
3029
3030/**
3031 * rtl8169_get_stats - Get rtl8169 read/write statistics
3032 * @dev: The Ethernet Device to get statistics for
3033 *
3034 * Get TX/RX statistics for rtl8169
3035 */
3036static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3037{
3038 struct rtl8169_private *tp = netdev_priv(dev);
3039 void __iomem *ioaddr = tp->mmio_addr;
3040 unsigned long flags;
3041
3042 if (netif_running(dev)) {
3043 spin_lock_irqsave(&tp->lock, flags);
3044 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
3045 RTL_W32(RxMissed, 0);
3046 spin_unlock_irqrestore(&tp->lock, flags);
3047 }
5b0384f4 3048
1da177e4
LT		 3049 return &tp->stats;
3050}
3051
5d06a99f
FR		 3052#ifdef CONFIG_PM
3053
3054static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
3055{
3056 struct net_device *dev = pci_get_drvdata(pdev);
3057 struct rtl8169_private *tp = netdev_priv(dev);
3058 void __iomem *ioaddr = tp->mmio_addr;
3059
3060 if (!netif_running(dev))
1371fa6d 3061 goto out_pci_suspend;
5d06a99f
FR		 3062
3063 netif_device_detach(dev);
3064 netif_stop_queue(dev);
3065
3066 spin_lock_irq(&tp->lock);
3067
3068 rtl8169_asic_down(ioaddr);
3069
3070 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
3071 RTL_W32(RxMissed, 0);
3072
3073 spin_unlock_irq(&tp->lock);
3074
1371fa6d 3075out_pci_suspend:
5d06a99f 3076 pci_save_state(pdev);
61a4dcc2 3077 pci_enable_wake(pdev, pci_choose_state(pdev, state), tp->wol_enabled);
5d06a99f 3078 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1371fa6d 3079
5d06a99f
FR		 3080 return 0;
3081}
3082
3083static int rtl8169_resume(struct pci_dev *pdev)
3084{
3085 struct net_device *dev = pci_get_drvdata(pdev);
3086
1371fa6d
FR		 3087 pci_set_power_state(pdev, PCI_D0);
3088 pci_restore_state(pdev);
3089 pci_enable_wake(pdev, PCI_D0, 0);
3090
5d06a99f
FR		 3091 if (!netif_running(dev))
3092 goto out;
3093
3094 netif_device_attach(dev);
3095
5d06a99f
FR		 3096 rtl8169_schedule_work(dev, rtl8169_reset_task);
3097out:
3098 return 0;
3099}
3100
3101#endif /* CONFIG_PM */
3102
1da177e4
LT		 3103static struct pci_driver rtl8169_pci_driver = {
3104 .name = MODULENAME,
3105 .id_table = rtl8169_pci_tbl,
3106 .probe = rtl8169_init_one,
3107 .remove = __devexit_p(rtl8169_remove_one),
3108#ifdef CONFIG_PM
3109 .suspend = rtl8169_suspend,
3110 .resume = rtl8169_resume,
3111#endif
3112};
3113
3114static int __init
3115rtl8169_init_module(void)
3116{
29917620 3117 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 3118}
3119
3120static void __exit
3121rtl8169_cleanup_module(void)
3122{
3123 pci_unregister_driver(&rtl8169_pci_driver);
3124}
3125
3126module_init(rtl8169_init_module);
3127module_exit(rtl8169_cleanup_module);
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