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cnic: Do not call bnx2i when bnx2i is calling cnic_unregister_driver()
[linux-2.6-block.git] / drivers / net / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
25#include <linux/dma-mapping.h>
e1759441 26#include <linux/pm_runtime.h>
1da177e4 27
99f252b0 28#include <asm/system.h>
1da177e4
LT		 29#include <asm/io.h>
30#include <asm/irq.h>
31
865c652d 32#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 33#define MODULENAME "r8169"
34#define PFX MODULENAME ": "
35
36#ifdef RTL8169_DEBUG
37#define assert(expr) \
5b0384f4
FR		 38 if (!(expr)) { \
39 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 40 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 41 }
06fa7358
JP		 42#define dprintk(fmt, args...) \
43 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 44#else
45#define assert(expr) do {} while (0)
46#define dprintk(fmt, args...) do {} while (0)
47#endif /* RTL8169_DEBUG */
48
b57b7e5a 49#define R8169_MSG_DEFAULT \
f0e837d9 50 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 51
1da177e4
LT		 52#define TX_BUFFS_AVAIL(tp) \
53 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
54
1da177e4
LT		 55/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
56 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 57static const int multicast_filter_limit = 32;
1da177e4
LT		 58
59/* MAC address length */
60#define MAC_ADDR_LEN 6
61
9c14ceaf 62#define MAX_READ_REQUEST_SHIFT 12
1da177e4
LT		 63#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
64#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
65#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
07d3f51f 66#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
1da177e4
LT		 67#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
68#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
69
70#define R8169_REGS_SIZE 256
71#define R8169_NAPI_WEIGHT 64
72#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
73#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
74#define RX_BUF_SIZE 1536 /* Rx Buffer size */
75#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
76#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
77
78#define RTL8169_TX_TIMEOUT (6*HZ)
79#define RTL8169_PHY_TIMEOUT (10*HZ)
80
ea8dbdd1 81#define RTL_EEPROM_SIG cpu_to_le32(0x8129)
82#define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
e1564ec9
FR		 83#define RTL_EEPROM_SIG_ADDR 0x0000
84
1da177e4
LT		 85/* write/read MMIO register */
86#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
87#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
88#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
89#define RTL_R8(reg) readb (ioaddr + (reg))
90#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 91#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 92
93enum mac_version {
f21b75e9 94 RTL_GIGA_MAC_NONE = 0x00,
ba6eb6ee
FR		 95 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
96 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
97 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
98 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
99 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
6dccd16b 100 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
2857ffb7
FR		 101 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
102 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
103 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
104 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
2dd99530 105 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
e3cf0cc0
FR		 106 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
107 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
108 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
109 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
110 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
111 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
112 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
113 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
197ff761 114 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
6fb07058 115 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
ef3386f0 116 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
7f3e3d3a 117 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
5b538df9 118 RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
daf9df6d 119 RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
120 RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
121 RTL_GIGA_MAC_VER_27 = 0x1b // 8168DP
1da177e4
LT		 122};
123
1da177e4
LT		 124#define _R(NAME,MAC,MASK) \
125 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
126
3c6bee1d 127static const struct {
1da177e4
LT		 128 const char *name;
129 u8 mac_version;
130 u32 RxConfigMask; /* Clears the bits supported by this chip */
131} rtl_chip_info[] = {
ba6eb6ee
FR		 132 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
133 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
134 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
135 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
136 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
6dccd16b 137 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
2857ffb7
FR		 138 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
139 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
140 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
141 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
bcf0bf90
FR		 142 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
143 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
144 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
145 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
e3cf0cc0
FR		 146 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
147 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
148 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
149 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
150 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
197ff761 151 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
6fb07058 152 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
ef3386f0 153 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
7f3e3d3a 154 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
5b538df9 155 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
daf9df6d 156 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E
157 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E
158 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27, 0xff7e1880) // PCI-E
1da177e4
LT		 159};
160#undef _R
161
bcf0bf90
FR		 162enum cfg_version {
163 RTL_CFG_0 = 0x00,
164 RTL_CFG_1,
165 RTL_CFG_2
166};
167
07ce4064
FR		 168static void rtl_hw_start_8169(struct net_device *);
169static void rtl_hw_start_8168(struct net_device *);
170static void rtl_hw_start_8101(struct net_device *);
171
a3aa1884 172static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
bcf0bf90 173 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 174 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 175 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 176 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 177 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
178 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
bc1660b5 179 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 180 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
181 { PCI_VENDOR_ID_LINKSYS, 0x1032,
182 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 183 { 0x0001, 0x8168,
184 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 185 {0,},
186};
187
188MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
189
6f0333b8 190static int rx_buf_sz = 16383;
4300e8c7 191static int use_dac;
b57b7e5a
SH		 192static struct {
193 u32 msg_enable;
194} debug = { -1 };
1da177e4 195
07d3f51f
FR		 196enum rtl_registers {
197 MAC0 = 0, /* Ethernet hardware address. */
773d2021 198 MAC4 = 4,
07d3f51f
FR		 199 MAR0 = 8, /* Multicast filter. */
200 CounterAddrLow = 0x10,
201 CounterAddrHigh = 0x14,
202 TxDescStartAddrLow = 0x20,
203 TxDescStartAddrHigh = 0x24,
204 TxHDescStartAddrLow = 0x28,
205 TxHDescStartAddrHigh = 0x2c,
206 FLASH = 0x30,
207 ERSR = 0x36,
208 ChipCmd = 0x37,
209 TxPoll = 0x38,
210 IntrMask = 0x3c,
211 IntrStatus = 0x3e,
212 TxConfig = 0x40,
213 RxConfig = 0x44,
214 RxMissed = 0x4c,
215 Cfg9346 = 0x50,
216 Config0 = 0x51,
217 Config1 = 0x52,
218 Config2 = 0x53,
219 Config3 = 0x54,
220 Config4 = 0x55,
221 Config5 = 0x56,
222 MultiIntr = 0x5c,
223 PHYAR = 0x60,
07d3f51f
FR		 224 PHYstatus = 0x6c,
225 RxMaxSize = 0xda,
226 CPlusCmd = 0xe0,
227 IntrMitigate = 0xe2,
228 RxDescAddrLow = 0xe4,
229 RxDescAddrHigh = 0xe8,
230 EarlyTxThres = 0xec,
231 FuncEvent = 0xf0,
232 FuncEventMask = 0xf4,
233 FuncPresetState = 0xf8,
234 FuncForceEvent = 0xfc,
1da177e4
LT		 235};
236
f162a5d1
FR		 237enum rtl8110_registers {
238 TBICSR = 0x64,
239 TBI_ANAR = 0x68,
240 TBI_LPAR = 0x6a,
241};
242
243enum rtl8168_8101_registers {
244 CSIDR = 0x64,
245 CSIAR = 0x68,
246#define CSIAR_FLAG 0x80000000
247#define CSIAR_WRITE_CMD 0x80000000
248#define CSIAR_BYTE_ENABLE 0x0f
249#define CSIAR_BYTE_ENABLE_SHIFT 12
250#define CSIAR_ADDR_MASK 0x0fff
251
252 EPHYAR = 0x80,
253#define EPHYAR_FLAG 0x80000000
254#define EPHYAR_WRITE_CMD 0x80000000
255#define EPHYAR_REG_MASK 0x1f
256#define EPHYAR_REG_SHIFT 16
257#define EPHYAR_DATA_MASK 0xffff
258 DBG_REG = 0xd1,
259#define FIX_NAK_1 (1 << 4)
260#define FIX_NAK_2 (1 << 3)
daf9df6d 261 EFUSEAR = 0xdc,
262#define EFUSEAR_FLAG 0x80000000
263#define EFUSEAR_WRITE_CMD 0x80000000
264#define EFUSEAR_READ_CMD 0x00000000
265#define EFUSEAR_REG_MASK 0x03ff
266#define EFUSEAR_REG_SHIFT 8
267#define EFUSEAR_DATA_MASK 0xff
f162a5d1
FR		 268};
269
07d3f51f 270enum rtl_register_content {
1da177e4 271 /* InterruptStatusBits */
07d3f51f
FR		 272 SYSErr = 0x8000,
273 PCSTimeout = 0x4000,
274 SWInt = 0x0100,
275 TxDescUnavail = 0x0080,
276 RxFIFOOver = 0x0040,
277 LinkChg = 0x0020,
278 RxOverflow = 0x0010,
279 TxErr = 0x0008,
280 TxOK = 0x0004,
281 RxErr = 0x0002,
282 RxOK = 0x0001,
1da177e4
LT		 283
284 /* RxStatusDesc */
9dccf611
FR		 285 RxFOVF = (1 << 23),
286 RxRWT = (1 << 22),
287 RxRES = (1 << 21),
288 RxRUNT = (1 << 20),
289 RxCRC = (1 << 19),
1da177e4
LT		 290
291 /* ChipCmdBits */
07d3f51f
FR		 292 CmdReset = 0x10,
293 CmdRxEnb = 0x08,
294 CmdTxEnb = 0x04,
295 RxBufEmpty = 0x01,
1da177e4 296
275391a4
FR		 297 /* TXPoll register p.5 */
298 HPQ = 0x80, /* Poll cmd on the high prio queue */
299 NPQ = 0x40, /* Poll cmd on the low prio queue */
300 FSWInt = 0x01, /* Forced software interrupt */
301
1da177e4 302 /* Cfg9346Bits */
07d3f51f
FR		 303 Cfg9346_Lock = 0x00,
304 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 305
306 /* rx_mode_bits */
07d3f51f
FR		 307 AcceptErr = 0x20,
308 AcceptRunt = 0x10,
309 AcceptBroadcast = 0x08,
310 AcceptMulticast = 0x04,
311 AcceptMyPhys = 0x02,
312 AcceptAllPhys = 0x01,
1da177e4
LT		 313
314 /* RxConfigBits */
07d3f51f
FR		 315 RxCfgFIFOShift = 13,
316 RxCfgDMAShift = 8,
1da177e4
LT		 317
318 /* TxConfigBits */
319 TxInterFrameGapShift = 24,
320 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
321
5d06a99f 322 /* Config1 register p.24 */
f162a5d1
FR		 323 LEDS1 = (1 << 7),
324 LEDS0 = (1 << 6),
fbac58fc 325 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
f162a5d1
FR		 326 Speed_down = (1 << 4),
327 MEMMAP = (1 << 3),
328 IOMAP = (1 << 2),
329 VPD = (1 << 1),
5d06a99f
FR		 330 PMEnable = (1 << 0), /* Power Management Enable */
331
6dccd16b
FR		 332 /* Config2 register p. 25 */
333 PCI_Clock_66MHz = 0x01,
334 PCI_Clock_33MHz = 0x00,
335
61a4dcc2
FR		 336 /* Config3 register p.25 */
337 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
338 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
f162a5d1 339 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 340
5d06a99f 341 /* Config5 register p.27 */
61a4dcc2
FR		 342 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
343 MWF = (1 << 5), /* Accept Multicast wakeup frame */
344 UWF = (1 << 4), /* Accept Unicast wakeup frame */
345 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 346 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
347
1da177e4
LT		 348 /* TBICSR p.28 */
349 TBIReset = 0x80000000,
350 TBILoopback = 0x40000000,
351 TBINwEnable = 0x20000000,
352 TBINwRestart = 0x10000000,
353 TBILinkOk = 0x02000000,
354 TBINwComplete = 0x01000000,
355
356 /* CPlusCmd p.31 */
f162a5d1
FR		 357 EnableBist = (1 << 15), // 8168 8101
358 Mac_dbgo_oe = (1 << 14), // 8168 8101
359 Normal_mode = (1 << 13), // unused
360 Force_half_dup = (1 << 12), // 8168 8101
361 Force_rxflow_en = (1 << 11), // 8168 8101
362 Force_txflow_en = (1 << 10), // 8168 8101
363 Cxpl_dbg_sel = (1 << 9), // 8168 8101
364 ASF = (1 << 8), // 8168 8101
365 PktCntrDisable = (1 << 7), // 8168 8101
366 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 367 RxVlan = (1 << 6),
368 RxChkSum = (1 << 5),
369 PCIDAC = (1 << 4),
370 PCIMulRW = (1 << 3),
0e485150
FR		 371 INTT_0 = 0x0000, // 8168
372 INTT_1 = 0x0001, // 8168
373 INTT_2 = 0x0002, // 8168
374 INTT_3 = 0x0003, // 8168
1da177e4
LT		 375
376 /* rtl8169_PHYstatus */
07d3f51f
FR		 377 TBI_Enable = 0x80,
378 TxFlowCtrl = 0x40,
379 RxFlowCtrl = 0x20,
380 _1000bpsF = 0x10,
381 _100bps = 0x08,
382 _10bps = 0x04,
383 LinkStatus = 0x02,
384 FullDup = 0x01,
1da177e4 385
1da177e4 386 /* _TBICSRBit */
07d3f51f 387 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 388
389 /* DumpCounterCommand */
07d3f51f 390 CounterDump = 0x8,
1da177e4
LT		 391};
392
07d3f51f 393enum desc_status_bit {
1da177e4
LT		 394 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
395 RingEnd = (1 << 30), /* End of descriptor ring */
396 FirstFrag = (1 << 29), /* First segment of a packet */
397 LastFrag = (1 << 28), /* Final segment of a packet */
398
399 /* Tx private */
400 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
401 MSSShift = 16, /* MSS value position */
402 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
403 IPCS = (1 << 18), /* Calculate IP checksum */
404 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
405 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
406 TxVlanTag = (1 << 17), /* Add VLAN tag */
407
408 /* Rx private */
409 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
410 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
411
412#define RxProtoUDP (PID1)
413#define RxProtoTCP (PID0)
414#define RxProtoIP (PID1 | PID0)
415#define RxProtoMask RxProtoIP
416
417 IPFail = (1 << 16), /* IP checksum failed */
418 UDPFail = (1 << 15), /* UDP/IP checksum failed */
419 TCPFail = (1 << 14), /* TCP/IP checksum failed */
420 RxVlanTag = (1 << 16), /* VLAN tag available */
421};
422
423#define RsvdMask 0x3fffc000
424
425struct TxDesc {
6cccd6e7
REB		 426 __le32 opts1;
427 __le32 opts2;
428 __le64 addr;
1da177e4
LT		 429};
430
431struct RxDesc {
6cccd6e7
REB		 432 __le32 opts1;
433 __le32 opts2;
434 __le64 addr;
1da177e4
LT		 435};
436
437struct ring_info {
438 struct sk_buff *skb;
439 u32 len;
440 u8 __pad[sizeof(void *) - sizeof(u32)];
441};
442
f23e7fda 443enum features {
ccdffb9a
FR		 444 RTL_FEATURE_WOL = (1 << 0),
445 RTL_FEATURE_MSI = (1 << 1),
446 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 447};
448
355423d0
IV		 449struct rtl8169_counters {
450 __le64 tx_packets;
451 __le64 rx_packets;
452 __le64 tx_errors;
453 __le32 rx_errors;
454 __le16 rx_missed;
455 __le16 align_errors;
456 __le32 tx_one_collision;
457 __le32 tx_multi_collision;
458 __le64 rx_unicast;
459 __le64 rx_broadcast;
460 __le32 rx_multicast;
461 __le16 tx_aborted;
462 __le16 tx_underun;
463};
464
1da177e4
LT		 465struct rtl8169_private {
466 void __iomem *mmio_addr; /* memory map physical address */
467 struct pci_dev *pci_dev; /* Index of PCI device */
c4028958 468 struct net_device *dev;
bea3348e 469 struct napi_struct napi;
1da177e4 470 spinlock_t lock; /* spin lock flag */
b57b7e5a 471 u32 msg_enable;
1da177e4
LT		 472 int chipset;
473 int mac_version;
1da177e4
LT		 474 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
475 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
476 u32 dirty_rx;
477 u32 dirty_tx;
478 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
479 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
480 dma_addr_t TxPhyAddr;
481 dma_addr_t RxPhyAddr;
6f0333b8 482 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 483 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 484 struct timer_list timer;
485 u16 cp_cmd;
0e485150
FR		 486 u16 intr_event;
487 u16 napi_event;
1da177e4 488 u16 intr_mask;
1da177e4
LT		 489 int phy_1000_ctrl_reg;
490#ifdef CONFIG_R8169_VLAN
491 struct vlan_group *vlgrp;
492#endif
493 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
ccdffb9a 494 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
1da177e4 495 void (*phy_reset_enable)(void __iomem *);
07ce4064 496 void (*hw_start)(struct net_device *);
1da177e4
LT		 497 unsigned int (*phy_reset_pending)(void __iomem *);
498 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 499 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
9c14ceaf 500 int pcie_cap;
c4028958 501 struct delayed_work task;
f23e7fda 502 unsigned features;
ccdffb9a
FR		 503
504 struct mii_if_info mii;
355423d0 505 struct rtl8169_counters counters;
e1759441 506 u32 saved_wolopts;
1da177e4
LT		 507};
508
979b6c13 509MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 510MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 511module_param(use_dac, int, 0);
4300e8c7 512MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 513module_param_named(debug, debug.msg_enable, int, 0);
514MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 515MODULE_LICENSE("GPL");
516MODULE_VERSION(RTL8169_VERSION);
517
518static int rtl8169_open(struct net_device *dev);
61357325
SH		 519static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
520 struct net_device *dev);
7d12e780 521static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 522static int rtl8169_init_ring(struct net_device *dev);
07ce4064 523static void rtl_hw_start(struct net_device *dev);
1da177e4 524static int rtl8169_close(struct net_device *dev);
07ce4064 525static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 526static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 527static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4 528static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
bea3348e 529 void __iomem *, u32 budget);
4dcb7d33 530static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 531static void rtl8169_down(struct net_device *dev);
99f252b0 532static void rtl8169_rx_clear(struct rtl8169_private *tp);
bea3348e 533static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4 534
1da177e4 535static const unsigned int rtl8169_rx_config =
5b0384f4 536 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4 537
07d3f51f 538static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 539{
540 int i;
541
a6baf3af 542 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
1da177e4 543
2371408c 544 for (i = 20; i > 0; i--) {
07d3f51f
FR		 545 /*
546 * Check if the RTL8169 has completed writing to the specified
547 * MII register.
548 */
5b0384f4 549 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 550 break;
2371408c 551 udelay(25);
1da177e4 552 }
024a07ba 553 /*
81a95f04
TT		 554 * According to hardware specs a 20us delay is required after write
555 * complete indication, but before sending next command.
024a07ba 556 */
81a95f04 557 udelay(20);
1da177e4
LT		 558}
559
07d3f51f 560static int mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 561{
562 int i, value = -1;
563
a6baf3af 564 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
1da177e4 565
2371408c 566 for (i = 20; i > 0; i--) {
07d3f51f
FR		 567 /*
568 * Check if the RTL8169 has completed retrieving data from
569 * the specified MII register.
570 */
1da177e4 571 if (RTL_R32(PHYAR) & 0x80000000) {
a6baf3af 572 value = RTL_R32(PHYAR) & 0xffff;
1da177e4
LT		 573 break;
574 }
2371408c 575 udelay(25);
1da177e4 576 }
81a95f04
TT		 577 /*
578 * According to hardware specs a 20us delay is required after read
579 * complete indication, but before sending next command.
580 */
581 udelay(20);
582
1da177e4
LT		 583 return value;
584}
585
dacf8154
FR		 586static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
587{
588 mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
589}
590
daf9df6d 591static void mdio_plus_minus(void __iomem *ioaddr, int reg_addr, int p, int m)
592{
593 int val;
594
595 val = mdio_read(ioaddr, reg_addr);
596 mdio_write(ioaddr, reg_addr, (val | p) & ~m);
597}
598
ccdffb9a
FR		 599static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
600 int val)
601{
602 struct rtl8169_private *tp = netdev_priv(dev);
603 void __iomem *ioaddr = tp->mmio_addr;
604
605 mdio_write(ioaddr, location, val);
606}
607
608static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
609{
610 struct rtl8169_private *tp = netdev_priv(dev);
611 void __iomem *ioaddr = tp->mmio_addr;
612
613 return mdio_read(ioaddr, location);
614}
615
dacf8154
FR		 616static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
617{
618 unsigned int i;
619
620 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
621 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
622
623 for (i = 0; i < 100; i++) {
624 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
625 break;
626 udelay(10);
627 }
628}
629
630static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
631{
632 u16 value = 0xffff;
633 unsigned int i;
634
635 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
636
637 for (i = 0; i < 100; i++) {
638 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
639 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
640 break;
641 }
642 udelay(10);
643 }
644
645 return value;
646}
647
648static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
649{
650 unsigned int i;
651
652 RTL_W32(CSIDR, value);
653 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
654 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
655
656 for (i = 0; i < 100; i++) {
657 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
658 break;
659 udelay(10);
660 }
661}
662
663static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
664{
665 u32 value = ~0x00;
666 unsigned int i;
667
668 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
669 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
670
671 for (i = 0; i < 100; i++) {
672 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
673 value = RTL_R32(CSIDR);
674 break;
675 }
676 udelay(10);
677 }
678
679 return value;
680}
681
daf9df6d 682static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
683{
684 u8 value = 0xff;
685 unsigned int i;
686
687 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
688
689 for (i = 0; i < 300; i++) {
690 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
691 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
692 break;
693 }
694 udelay(100);
695 }
696
697 return value;
698}
699
1da177e4
LT		 700static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
701{
702 RTL_W16(IntrMask, 0x0000);
703
704 RTL_W16(IntrStatus, 0xffff);
705}
706
707static void rtl8169_asic_down(void __iomem *ioaddr)
708{
709 RTL_W8(ChipCmd, 0x00);
710 rtl8169_irq_mask_and_ack(ioaddr);
711 RTL_R16(CPlusCmd);
712}
713
714static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
715{
716 return RTL_R32(TBICSR) & TBIReset;
717}
718
719static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
720{
64e4bfb4 721 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 722}
723
724static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
725{
726 return RTL_R32(TBICSR) & TBILinkOk;
727}
728
729static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
730{
731 return RTL_R8(PHYstatus) & LinkStatus;
732}
733
734static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
735{
736 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
737}
738
739static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
740{
741 unsigned int val;
742
9e0db8ef
FR		 743 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
744 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
1da177e4
LT		 745}
746
e4fbce74 747static void __rtl8169_check_link_status(struct net_device *dev,
07d3f51f 748 struct rtl8169_private *tp,
e4fbce74
RW		 749 void __iomem *ioaddr,
750 bool pm)
1da177e4
LT		 751{
752 unsigned long flags;
753
754 spin_lock_irqsave(&tp->lock, flags);
755 if (tp->link_ok(ioaddr)) {
e1759441 756 /* This is to cancel a scheduled suspend if there's one. */
e4fbce74
RW		 757 if (pm)
758 pm_request_resume(&tp->pci_dev->dev);
1da177e4 759 netif_carrier_on(dev);
bf82c189 760 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 761 } else {
1da177e4 762 netif_carrier_off(dev);
bf82c189 763 netif_info(tp, ifdown, dev, "link down\n");
e4fbce74
RW		 764 if (pm)
765 pm_schedule_suspend(&tp->pci_dev->dev, 100);
b57b7e5a 766 }
1da177e4
LT		 767 spin_unlock_irqrestore(&tp->lock, flags);
768}
769
e4fbce74
RW		 770static void rtl8169_check_link_status(struct net_device *dev,
771 struct rtl8169_private *tp,
772 void __iomem *ioaddr)
773{
774 __rtl8169_check_link_status(dev, tp, ioaddr, false);
775}
776
e1759441
RW		 777#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
778
779static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 780{
61a4dcc2
FR		 781 void __iomem *ioaddr = tp->mmio_addr;
782 u8 options;
e1759441 783 u32 wolopts = 0;
61a4dcc2
FR		 784
785 options = RTL_R8(Config1);
786 if (!(options & PMEnable))
e1759441 787 return 0;
61a4dcc2
FR		 788
789 options = RTL_R8(Config3);
790 if (options & LinkUp)
e1759441 791 wolopts |= WAKE_PHY;
61a4dcc2 792 if (options & MagicPacket)
e1759441 793 wolopts |= WAKE_MAGIC;
61a4dcc2
FR		 794
795 options = RTL_R8(Config5);
796 if (options & UWF)
e1759441 797 wolopts |= WAKE_UCAST;
61a4dcc2 798 if (options & BWF)
e1759441 799 wolopts |= WAKE_BCAST;
61a4dcc2 800 if (options & MWF)
e1759441 801 wolopts |= WAKE_MCAST;
61a4dcc2 802
e1759441 803 return wolopts;
61a4dcc2
FR		 804}
805
e1759441 806static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 807{
808 struct rtl8169_private *tp = netdev_priv(dev);
e1759441
RW		 809
810 spin_lock_irq(&tp->lock);
811
812 wol->supported = WAKE_ANY;
813 wol->wolopts = __rtl8169_get_wol(tp);
814
815 spin_unlock_irq(&tp->lock);
816}
817
818static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
819{
61a4dcc2 820 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 821 unsigned int i;
350f7596 822 static const struct {
61a4dcc2
FR		 823 u32 opt;
824 u16 reg;
825 u8 mask;
826 } cfg[] = {
827 { WAKE_ANY, Config1, PMEnable },
828 { WAKE_PHY, Config3, LinkUp },
829 { WAKE_MAGIC, Config3, MagicPacket },
830 { WAKE_UCAST, Config5, UWF },
831 { WAKE_BCAST, Config5, BWF },
832 { WAKE_MCAST, Config5, MWF },
833 { WAKE_ANY, Config5, LanWake }
834 };
835
61a4dcc2
FR		 836 RTL_W8(Cfg9346, Cfg9346_Unlock);
837
838 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
839 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 840 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 841 options |= cfg[i].mask;
842 RTL_W8(cfg[i].reg, options);
843 }
844
845 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 846}
847
848static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
849{
850 struct rtl8169_private *tp = netdev_priv(dev);
851
852 spin_lock_irq(&tp->lock);
61a4dcc2 853
f23e7fda
FR		 854 if (wol->wolopts)
855 tp->features |= RTL_FEATURE_WOL;
856 else
857 tp->features &= ~RTL_FEATURE_WOL;
e1759441 858 __rtl8169_set_wol(tp, wol->wolopts);
61a4dcc2
FR		 859 spin_unlock_irq(&tp->lock);
860
ea80907f 861 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
862
61a4dcc2
FR		 863 return 0;
864}
865
1da177e4
LT		 866static void rtl8169_get_drvinfo(struct net_device *dev,
867 struct ethtool_drvinfo *info)
868{
869 struct rtl8169_private *tp = netdev_priv(dev);
870
871 strcpy(info->driver, MODULENAME);
872 strcpy(info->version, RTL8169_VERSION);
873 strcpy(info->bus_info, pci_name(tp->pci_dev));
874}
875
876static int rtl8169_get_regs_len(struct net_device *dev)
877{
878 return R8169_REGS_SIZE;
879}
880
881static int rtl8169_set_speed_tbi(struct net_device *dev,
882 u8 autoneg, u16 speed, u8 duplex)
883{
884 struct rtl8169_private *tp = netdev_priv(dev);
885 void __iomem *ioaddr = tp->mmio_addr;
886 int ret = 0;
887 u32 reg;
888
889 reg = RTL_R32(TBICSR);
890 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
891 (duplex == DUPLEX_FULL)) {
892 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
893 } else if (autoneg == AUTONEG_ENABLE)
894 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
895 else {
bf82c189
JP		 896 netif_warn(tp, link, dev,
897 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 898 ret = -EOPNOTSUPP;
899 }
900
901 return ret;
902}
903
904static int rtl8169_set_speed_xmii(struct net_device *dev,
905 u8 autoneg, u16 speed, u8 duplex)
906{
907 struct rtl8169_private *tp = netdev_priv(dev);
908 void __iomem *ioaddr = tp->mmio_addr;
3577aa1b 909 int giga_ctrl, bmcr;
1da177e4
LT		 910
911 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 912 int auto_nego;
913
914 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
64e4bfb4
FR		 915 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
916 ADVERTISE_100HALF | ADVERTISE_100FULL);
3577aa1b 917 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 918
3577aa1b 919 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
920 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 921
3577aa1b 922 /* The 8100e/8101e/8102e do Fast Ethernet only. */
923 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
924 (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
925 (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
926 (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
927 (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
928 (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
929 (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
930 (tp->mac_version != RTL_GIGA_MAC_VER_16)) {
931 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
bf82c189
JP		 932 } else {
933 netif_info(tp, link, dev,
934 "PHY does not support 1000Mbps\n");
bcf0bf90 935 }
1da177e4 936
3577aa1b 937 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
938
939 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
940 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
941 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
942 /*
943 * Wake up the PHY.
944 * Vendor specific (0x1f) and reserved (0x0e) MII
945 * registers.
946 */
947 mdio_write(ioaddr, 0x1f, 0x0000);
948 mdio_write(ioaddr, 0x0e, 0x0000);
949 }
950
951 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
952 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
953 } else {
954 giga_ctrl = 0;
955
956 if (speed == SPEED_10)
957 bmcr = 0;
958 else if (speed == SPEED_100)
959 bmcr = BMCR_SPEED100;
960 else
961 return -EINVAL;
962
963 if (duplex == DUPLEX_FULL)
964 bmcr |= BMCR_FULLDPLX;
623a1593 965
2584fbc3 966 mdio_write(ioaddr, 0x1f, 0x0000);
2584fbc3
RS		 967 }
968
1da177e4
LT		 969 tp->phy_1000_ctrl_reg = giga_ctrl;
970
3577aa1b 971 mdio_write(ioaddr, MII_BMCR, bmcr);
972
973 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
974 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
975 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
976 mdio_write(ioaddr, 0x17, 0x2138);
977 mdio_write(ioaddr, 0x0e, 0x0260);
978 } else {
979 mdio_write(ioaddr, 0x17, 0x2108);
980 mdio_write(ioaddr, 0x0e, 0x0000);
981 }
982 }
983
1da177e4
LT		 984 return 0;
985}
986
987static int rtl8169_set_speed(struct net_device *dev,
988 u8 autoneg, u16 speed, u8 duplex)
989{
990 struct rtl8169_private *tp = netdev_priv(dev);
991 int ret;
992
993 ret = tp->set_speed(dev, autoneg, speed, duplex);
994
64e4bfb4 995 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 996 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
997
998 return ret;
999}
1000
1001static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1002{
1003 struct rtl8169_private *tp = netdev_priv(dev);
1004 unsigned long flags;
1005 int ret;
1006
1007 spin_lock_irqsave(&tp->lock, flags);
1008 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
1009 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 1010
1da177e4
LT		 1011 return ret;
1012}
1013
1014static u32 rtl8169_get_rx_csum(struct net_device *dev)
1015{
1016 struct rtl8169_private *tp = netdev_priv(dev);
1017
1018 return tp->cp_cmd & RxChkSum;
1019}
1020
1021static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
1022{
1023 struct rtl8169_private *tp = netdev_priv(dev);
1024 void __iomem *ioaddr = tp->mmio_addr;
1025 unsigned long flags;
1026
1027 spin_lock_irqsave(&tp->lock, flags);
1028
1029 if (data)
1030 tp->cp_cmd |= RxChkSum;
1031 else
1032 tp->cp_cmd &= ~RxChkSum;
1033
1034 RTL_W16(CPlusCmd, tp->cp_cmd);
1035 RTL_R16(CPlusCmd);
1036
1037 spin_unlock_irqrestore(&tp->lock, flags);
1038
1039 return 0;
1040}
1041
1042#ifdef CONFIG_R8169_VLAN
1043
1044static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1045 struct sk_buff *skb)
1046{
eab6d18d 1047 return (vlan_tx_tag_present(skb)) ?
1da177e4
LT		 1048 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1049}
1050
1051static void rtl8169_vlan_rx_register(struct net_device *dev,
1052 struct vlan_group *grp)
1053{
1054 struct rtl8169_private *tp = netdev_priv(dev);
1055 void __iomem *ioaddr = tp->mmio_addr;
1056 unsigned long flags;
1057
1058 spin_lock_irqsave(&tp->lock, flags);
1059 tp->vlgrp = grp;
05af2142
SW		 1060 /*
1061 * Do not disable RxVlan on 8110SCd.
1062 */
1063 if (tp->vlgrp || (tp->mac_version == RTL_GIGA_MAC_VER_05))
1da177e4
LT		 1064 tp->cp_cmd |= RxVlan;
1065 else
1066 tp->cp_cmd &= ~RxVlan;
1067 RTL_W16(CPlusCmd, tp->cp_cmd);
1068 RTL_R16(CPlusCmd);
1069 spin_unlock_irqrestore(&tp->lock, flags);
1070}
1071
1da177e4 1072static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
630b943c 1073 struct sk_buff *skb, int polling)
1da177e4
LT		 1074{
1075 u32 opts2 = le32_to_cpu(desc->opts2);
865c652d 1076 struct vlan_group *vlgrp = tp->vlgrp;
1da177e4
LT		 1077 int ret;
1078
865c652d 1079 if (vlgrp && (opts2 & RxVlanTag)) {
2edae08e
ED		 1080 u16 vtag = swab16(opts2 & 0xffff);
1081
1082 if (likely(polling))
1083 vlan_gro_receive(&tp->napi, vlgrp, vtag, skb);
1084 else
1085 __vlan_hwaccel_rx(skb, vlgrp, vtag, polling);
1da177e4
LT		 1086 ret = 0;
1087 } else
1088 ret = -1;
1089 desc->opts2 = 0;
1090 return ret;
1091}
1092
1093#else /* !CONFIG_R8169_VLAN */
1094
1095static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1096 struct sk_buff *skb)
1097{
1098 return 0;
1099}
1100
1101static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
630b943c 1102 struct sk_buff *skb, int polling)
1da177e4
LT		 1103{
1104 return -1;
1105}
1106
1107#endif
1108
ccdffb9a 1109static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1110{
1111 struct rtl8169_private *tp = netdev_priv(dev);
1112 void __iomem *ioaddr = tp->mmio_addr;
1113 u32 status;
1114
1115 cmd->supported =
1116 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1117 cmd->port = PORT_FIBRE;
1118 cmd->transceiver = XCVR_INTERNAL;
1119
1120 status = RTL_R32(TBICSR);
1121 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1122 cmd->autoneg = !!(status & TBINwEnable);
1123
1124 cmd->speed = SPEED_1000;
1125 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1126
1127 return 0;
1da177e4
LT		 1128}
1129
ccdffb9a 1130static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1131{
1132 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1133
1134 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1135}
1136
1137static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1138{
1139 struct rtl8169_private *tp = netdev_priv(dev);
1140 unsigned long flags;
ccdffb9a 1141 int rc;
1da177e4
LT		 1142
1143 spin_lock_irqsave(&tp->lock, flags);
1144
ccdffb9a 1145 rc = tp->get_settings(dev, cmd);
1da177e4
LT		 1146
1147 spin_unlock_irqrestore(&tp->lock, flags);
ccdffb9a 1148 return rc;
1da177e4
LT		 1149}
1150
1151static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1152 void *p)
1153{
5b0384f4
FR		 1154 struct rtl8169_private *tp = netdev_priv(dev);
1155 unsigned long flags;
1da177e4 1156
5b0384f4
FR		 1157 if (regs->len > R8169_REGS_SIZE)
1158 regs->len = R8169_REGS_SIZE;
1da177e4 1159
5b0384f4
FR		 1160 spin_lock_irqsave(&tp->lock, flags);
1161 memcpy_fromio(p, tp->mmio_addr, regs->len);
1162 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 1163}
1164
b57b7e5a
SH		 1165static u32 rtl8169_get_msglevel(struct net_device *dev)
1166{
1167 struct rtl8169_private *tp = netdev_priv(dev);
1168
1169 return tp->msg_enable;
1170}
1171
1172static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1173{
1174 struct rtl8169_private *tp = netdev_priv(dev);
1175
1176 tp->msg_enable = value;
1177}
1178
d4a3a0fc
SH		 1179static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1180 "tx_packets",
1181 "rx_packets",
1182 "tx_errors",
1183 "rx_errors",
1184 "rx_missed",
1185 "align_errors",
1186 "tx_single_collisions",
1187 "tx_multi_collisions",
1188 "unicast",
1189 "broadcast",
1190 "multicast",
1191 "tx_aborted",
1192 "tx_underrun",
1193};
1194
b9f2c044 1195static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1196{
b9f2c044
JG		 1197 switch (sset) {
1198 case ETH_SS_STATS:
1199 return ARRAY_SIZE(rtl8169_gstrings);
1200 default:
1201 return -EOPNOTSUPP;
1202 }
d4a3a0fc
SH		 1203}
1204
355423d0 1205static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1206{
1207 struct rtl8169_private *tp = netdev_priv(dev);
1208 void __iomem *ioaddr = tp->mmio_addr;
1209 struct rtl8169_counters *counters;
1210 dma_addr_t paddr;
1211 u32 cmd;
355423d0 1212 int wait = 1000;
48addcc9 1213 struct device *d = &tp->pci_dev->dev;
d4a3a0fc 1214
355423d0
IV		 1215 /*
1216 * Some chips are unable to dump tally counters when the receiver
1217 * is disabled.
1218 */
1219 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1220 return;
d4a3a0fc 1221
48addcc9 1222 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
d4a3a0fc
SH		 1223 if (!counters)
1224 return;
1225
1226 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1227 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1228 RTL_W32(CounterAddrLow, cmd);
1229 RTL_W32(CounterAddrLow, cmd | CounterDump);
1230
355423d0
IV		 1231 while (wait--) {
1232 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1233 /* copy updated counters */
1234 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc 1235 break;
355423d0
IV		 1236 }
1237 udelay(10);
d4a3a0fc
SH		 1238 }
1239
1240 RTL_W32(CounterAddrLow, 0);
1241 RTL_W32(CounterAddrHigh, 0);
1242
48addcc9 1243 dma_free_coherent(d, sizeof(*counters), counters, paddr);
d4a3a0fc
SH		 1244}
1245
355423d0
IV		 1246static void rtl8169_get_ethtool_stats(struct net_device *dev,
1247 struct ethtool_stats *stats, u64 *data)
1248{
1249 struct rtl8169_private *tp = netdev_priv(dev);
1250
1251 ASSERT_RTNL();
1252
1253 rtl8169_update_counters(dev);
1254
1255 data[0] = le64_to_cpu(tp->counters.tx_packets);
1256 data[1] = le64_to_cpu(tp->counters.rx_packets);
1257 data[2] = le64_to_cpu(tp->counters.tx_errors);
1258 data[3] = le32_to_cpu(tp->counters.rx_errors);
1259 data[4] = le16_to_cpu(tp->counters.rx_missed);
1260 data[5] = le16_to_cpu(tp->counters.align_errors);
1261 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1262 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1263 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1264 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1265 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1266 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1267 data[12] = le16_to_cpu(tp->counters.tx_underun);
1268}
1269
d4a3a0fc
SH		 1270static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1271{
1272 switch(stringset) {
1273 case ETH_SS_STATS:
1274 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1275 break;
1276 }
1277}
1278
7282d491 1279static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1280 .get_drvinfo = rtl8169_get_drvinfo,
1281 .get_regs_len = rtl8169_get_regs_len,
1282 .get_link = ethtool_op_get_link,
1283 .get_settings = rtl8169_get_settings,
1284 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1285 .get_msglevel = rtl8169_get_msglevel,
1286 .set_msglevel = rtl8169_set_msglevel,
1da177e4
LT		 1287 .get_rx_csum = rtl8169_get_rx_csum,
1288 .set_rx_csum = rtl8169_set_rx_csum,
1da177e4 1289 .set_tx_csum = ethtool_op_set_tx_csum,
1da177e4 1290 .set_sg = ethtool_op_set_sg,
1da177e4
LT		 1291 .set_tso = ethtool_op_set_tso,
1292 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1293 .get_wol = rtl8169_get_wol,
1294 .set_wol = rtl8169_set_wol,
d4a3a0fc 1295 .get_strings = rtl8169_get_strings,
b9f2c044 1296 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1297 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1298};
1299
07d3f51f
FR		 1300static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1301 void __iomem *ioaddr)
1da177e4 1302{
0e485150
FR		 1303 /*
1304 * The driver currently handles the 8168Bf and the 8168Be identically
1305 * but they can be identified more specifically through the test below
1306 * if needed:
1307 *
1308 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1309 *
1310 * Same thing for the 8101Eb and the 8101Ec:
1311 *
1312 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1313 */
350f7596 1314 static const struct {
1da177e4 1315 u32 mask;
e3cf0cc0 1316 u32 val;
1da177e4
LT		 1317 int mac_version;
1318 } mac_info[] = {
5b538df9 1319 /* 8168D family. */
daf9df6d 1320 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1321 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
1322 { 0x7c800000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1323 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 1324
ef808d50 1325 /* 8168C family. */
17c99297 1326 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 1327 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 1328 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 1329 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 1330 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1331 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 1332 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 1333 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 1334 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 1335
1336 /* 8168B family. */
1337 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1338 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1339 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1340 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1341
1342 /* 8101 family. */
2857ffb7
FR		 1343 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1344 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1345 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1346 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1347 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1348 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 1349 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 1350 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 1351 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 1352 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1353 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 1354 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1355 /* FIXME: where did these entries come from ? -- FR */
1356 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1357 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1358
1359 /* 8110 family. */
1360 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1361 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1362 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1363 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1364 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1365 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1366
f21b75e9
JD		 1367 /* Catch-all */
1368 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1da177e4
LT		 1369 }, *p = mac_info;
1370 u32 reg;
1371
e3cf0cc0
FR		 1372 reg = RTL_R32(TxConfig);
1373 while ((reg & p->mask) != p->val)
1da177e4
LT		 1374 p++;
1375 tp->mac_version = p->mac_version;
1376}
1377
1378static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1379{
bcf0bf90 1380 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1381}
1382
867763c1
FR		 1383struct phy_reg {
1384 u16 reg;
1385 u16 val;
1386};
1387
350f7596 1388static void rtl_phy_write(void __iomem *ioaddr, const struct phy_reg *regs, int len)
867763c1
FR		 1389{
1390 while (len-- > 0) {
1391 mdio_write(ioaddr, regs->reg, regs->val);
1392 regs++;
1393 }
1394}
1395
5615d9f1 1396static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1da177e4 1397{
350f7596 1398 static const struct phy_reg phy_reg_init[] = {
0b9b571d 1399 { 0x1f, 0x0001 },
1400 { 0x06, 0x006e },
1401 { 0x08, 0x0708 },
1402 { 0x15, 0x4000 },
1403 { 0x18, 0x65c7 },
1da177e4 1404
0b9b571d 1405 { 0x1f, 0x0001 },
1406 { 0x03, 0x00a1 },
1407 { 0x02, 0x0008 },
1408 { 0x01, 0x0120 },
1409 { 0x00, 0x1000 },
1410 { 0x04, 0x0800 },
1411 { 0x04, 0x0000 },
1da177e4 1412
0b9b571d 1413 { 0x03, 0xff41 },
1414 { 0x02, 0xdf60 },
1415 { 0x01, 0x0140 },
1416 { 0x00, 0x0077 },
1417 { 0x04, 0x7800 },
1418 { 0x04, 0x7000 },
1419
1420 { 0x03, 0x802f },
1421 { 0x02, 0x4f02 },
1422 { 0x01, 0x0409 },
1423 { 0x00, 0xf0f9 },
1424 { 0x04, 0x9800 },
1425 { 0x04, 0x9000 },
1426
1427 { 0x03, 0xdf01 },
1428 { 0x02, 0xdf20 },
1429 { 0x01, 0xff95 },
1430 { 0x00, 0xba00 },
1431 { 0x04, 0xa800 },
1432 { 0x04, 0xa000 },
1433
1434 { 0x03, 0xff41 },
1435 { 0x02, 0xdf20 },
1436 { 0x01, 0x0140 },
1437 { 0x00, 0x00bb },
1438 { 0x04, 0xb800 },
1439 { 0x04, 0xb000 },
1440
1441 { 0x03, 0xdf41 },
1442 { 0x02, 0xdc60 },
1443 { 0x01, 0x6340 },
1444 { 0x00, 0x007d },
1445 { 0x04, 0xd800 },
1446 { 0x04, 0xd000 },
1447
1448 { 0x03, 0xdf01 },
1449 { 0x02, 0xdf20 },
1450 { 0x01, 0x100a },
1451 { 0x00, 0xa0ff },
1452 { 0x04, 0xf800 },
1453 { 0x04, 0xf000 },
1454
1455 { 0x1f, 0x0000 },
1456 { 0x0b, 0x0000 },
1457 { 0x00, 0x9200 }
1458 };
1da177e4 1459
0b9b571d 1460 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 1461}
1462
5615d9f1
FR		 1463static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1464{
350f7596 1465 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 1466 { 0x1f, 0x0002 },
1467 { 0x01, 0x90d0 },
1468 { 0x1f, 0x0000 }
1469 };
1470
1471 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 1472}
1473
2e955856 1474static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp,
1475 void __iomem *ioaddr)
1476{
1477 struct pci_dev *pdev = tp->pci_dev;
1478 u16 vendor_id, device_id;
1479
1480 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1481 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1482
1483 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1484 return;
1485
1486 mdio_write(ioaddr, 0x1f, 0x0001);
1487 mdio_write(ioaddr, 0x10, 0xf01b);
1488 mdio_write(ioaddr, 0x1f, 0x0000);
1489}
1490
1491static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp,
1492 void __iomem *ioaddr)
1493{
350f7596 1494 static const struct phy_reg phy_reg_init[] = {
2e955856 1495 { 0x1f, 0x0001 },
1496 { 0x04, 0x0000 },
1497 { 0x03, 0x00a1 },
1498 { 0x02, 0x0008 },
1499 { 0x01, 0x0120 },
1500 { 0x00, 0x1000 },
1501 { 0x04, 0x0800 },
1502 { 0x04, 0x9000 },
1503 { 0x03, 0x802f },
1504 { 0x02, 0x4f02 },
1505 { 0x01, 0x0409 },
1506 { 0x00, 0xf099 },
1507 { 0x04, 0x9800 },
1508 { 0x04, 0xa000 },
1509 { 0x03, 0xdf01 },
1510 { 0x02, 0xdf20 },
1511 { 0x01, 0xff95 },
1512 { 0x00, 0xba00 },
1513 { 0x04, 0xa800 },
1514 { 0x04, 0xf000 },
1515 { 0x03, 0xdf01 },
1516 { 0x02, 0xdf20 },
1517 { 0x01, 0x101a },
1518 { 0x00, 0xa0ff },
1519 { 0x04, 0xf800 },
1520 { 0x04, 0x0000 },
1521 { 0x1f, 0x0000 },
1522
1523 { 0x1f, 0x0001 },
1524 { 0x10, 0xf41b },
1525 { 0x14, 0xfb54 },
1526 { 0x18, 0xf5c7 },
1527 { 0x1f, 0x0000 },
1528
1529 { 0x1f, 0x0001 },
1530 { 0x17, 0x0cc0 },
1531 { 0x1f, 0x0000 }
1532 };
1533
1534 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1535
1536 rtl8169scd_hw_phy_config_quirk(tp, ioaddr);
1537}
1538
8c7006aa 1539static void rtl8169sce_hw_phy_config(void __iomem *ioaddr)
1540{
350f7596 1541 static const struct phy_reg phy_reg_init[] = {
8c7006aa 1542 { 0x1f, 0x0001 },
1543 { 0x04, 0x0000 },
1544 { 0x03, 0x00a1 },
1545 { 0x02, 0x0008 },
1546 { 0x01, 0x0120 },
1547 { 0x00, 0x1000 },
1548 { 0x04, 0x0800 },
1549 { 0x04, 0x9000 },
1550 { 0x03, 0x802f },
1551 { 0x02, 0x4f02 },
1552 { 0x01, 0x0409 },
1553 { 0x00, 0xf099 },
1554 { 0x04, 0x9800 },
1555 { 0x04, 0xa000 },
1556 { 0x03, 0xdf01 },
1557 { 0x02, 0xdf20 },
1558 { 0x01, 0xff95 },
1559 { 0x00, 0xba00 },
1560 { 0x04, 0xa800 },
1561 { 0x04, 0xf000 },
1562 { 0x03, 0xdf01 },
1563 { 0x02, 0xdf20 },
1564 { 0x01, 0x101a },
1565 { 0x00, 0xa0ff },
1566 { 0x04, 0xf800 },
1567 { 0x04, 0x0000 },
1568 { 0x1f, 0x0000 },
1569
1570 { 0x1f, 0x0001 },
1571 { 0x0b, 0x8480 },
1572 { 0x1f, 0x0000 },
1573
1574 { 0x1f, 0x0001 },
1575 { 0x18, 0x67c7 },
1576 { 0x04, 0x2000 },
1577 { 0x03, 0x002f },
1578 { 0x02, 0x4360 },
1579 { 0x01, 0x0109 },
1580 { 0x00, 0x3022 },
1581 { 0x04, 0x2800 },
1582 { 0x1f, 0x0000 },
1583
1584 { 0x1f, 0x0001 },
1585 { 0x17, 0x0cc0 },
1586 { 0x1f, 0x0000 }
1587 };
1588
1589 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1590}
1591
236b8082
FR		 1592static void rtl8168bb_hw_phy_config(void __iomem *ioaddr)
1593{
350f7596 1594 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 1595 { 0x10, 0xf41b },
1596 { 0x1f, 0x0000 }
1597 };
1598
1599 mdio_write(ioaddr, 0x1f, 0x0001);
1600 mdio_patch(ioaddr, 0x16, 1 << 0);
1601
1602 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1603}
1604
1605static void rtl8168bef_hw_phy_config(void __iomem *ioaddr)
1606{
350f7596 1607 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 1608 { 0x1f, 0x0001 },
1609 { 0x10, 0xf41b },
1610 { 0x1f, 0x0000 }
1611 };
1612
1613 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1614}
1615
ef3386f0 1616static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr)
867763c1 1617{
350f7596 1618 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 1619 { 0x1f, 0x0000 },
1620 { 0x1d, 0x0f00 },
1621 { 0x1f, 0x0002 },
1622 { 0x0c, 0x1ec8 },
1623 { 0x1f, 0x0000 }
1624 };
1625
1626 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1627}
1628
ef3386f0
FR		 1629static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr)
1630{
350f7596 1631 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 1632 { 0x1f, 0x0001 },
1633 { 0x1d, 0x3d98 },
1634 { 0x1f, 0x0000 }
1635 };
1636
1637 mdio_write(ioaddr, 0x1f, 0x0000);
1638 mdio_patch(ioaddr, 0x14, 1 << 5);
1639 mdio_patch(ioaddr, 0x0d, 1 << 5);
1640
1641 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1642}
1643
219a1e9d 1644static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr)
867763c1 1645{
350f7596 1646 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 1647 { 0x1f, 0x0001 },
1648 { 0x12, 0x2300 },
867763c1
FR		 1649 { 0x1f, 0x0002 },
1650 { 0x00, 0x88d4 },
1651 { 0x01, 0x82b1 },
1652 { 0x03, 0x7002 },
1653 { 0x08, 0x9e30 },
1654 { 0x09, 0x01f0 },
1655 { 0x0a, 0x5500 },
1656 { 0x0c, 0x00c8 },
1657 { 0x1f, 0x0003 },
1658 { 0x12, 0xc096 },
1659 { 0x16, 0x000a },
f50d4275
FR		 1660 { 0x1f, 0x0000 },
1661 { 0x1f, 0x0000 },
1662 { 0x09, 0x2000 },
1663 { 0x09, 0x0000 }
867763c1
FR		 1664 };
1665
1666 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275
FR		 1667
1668 mdio_patch(ioaddr, 0x14, 1 << 5);
1669 mdio_patch(ioaddr, 0x0d, 1 << 5);
1670 mdio_write(ioaddr, 0x1f, 0x0000);
867763c1
FR		 1671}
1672
219a1e9d 1673static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr)
7da97ec9 1674{
350f7596 1675 static const struct phy_reg phy_reg_init[] = {
f50d4275 1676 { 0x1f, 0x0001 },
7da97ec9 1677 { 0x12, 0x2300 },
f50d4275
FR		 1678 { 0x03, 0x802f },
1679 { 0x02, 0x4f02 },
1680 { 0x01, 0x0409 },
1681 { 0x00, 0xf099 },
1682 { 0x04, 0x9800 },
1683 { 0x04, 0x9000 },
1684 { 0x1d, 0x3d98 },
7da97ec9
FR		 1685 { 0x1f, 0x0002 },
1686 { 0x0c, 0x7eb8 },
f50d4275
FR		 1687 { 0x06, 0x0761 },
1688 { 0x1f, 0x0003 },
1689 { 0x16, 0x0f0a },
7da97ec9
FR		 1690 { 0x1f, 0x0000 }
1691 };
1692
1693 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275
FR		 1694
1695 mdio_patch(ioaddr, 0x16, 1 << 0);
1696 mdio_patch(ioaddr, 0x14, 1 << 5);
1697 mdio_patch(ioaddr, 0x0d, 1 << 5);
1698 mdio_write(ioaddr, 0x1f, 0x0000);
7da97ec9
FR		 1699}
1700
197ff761
FR		 1701static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr)
1702{
350f7596 1703 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 1704 { 0x1f, 0x0001 },
1705 { 0x12, 0x2300 },
1706 { 0x1d, 0x3d98 },
1707 { 0x1f, 0x0002 },
1708 { 0x0c, 0x7eb8 },
1709 { 0x06, 0x5461 },
1710 { 0x1f, 0x0003 },
1711 { 0x16, 0x0f0a },
1712 { 0x1f, 0x0000 }
1713 };
1714
1715 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1716
1717 mdio_patch(ioaddr, 0x16, 1 << 0);
1718 mdio_patch(ioaddr, 0x14, 1 << 5);
1719 mdio_patch(ioaddr, 0x0d, 1 << 5);
1720 mdio_write(ioaddr, 0x1f, 0x0000);
1721}
1722
6fb07058
FR		 1723static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr)
1724{
1725 rtl8168c_3_hw_phy_config(ioaddr);
1726}
1727
daf9df6d 1728static void rtl8168d_1_hw_phy_config(void __iomem *ioaddr)
5b538df9 1729{
350f7596 1730 static const struct phy_reg phy_reg_init_0[] = {
5b538df9 1731 { 0x1f, 0x0001 },
daf9df6d 1732 { 0x06, 0x4064 },
1733 { 0x07, 0x2863 },
1734 { 0x08, 0x059c },
1735 { 0x09, 0x26b4 },
1736 { 0x0a, 0x6a19 },
1737 { 0x0b, 0xdcc8 },
1738 { 0x10, 0xf06d },
1739 { 0x14, 0x7f68 },
1740 { 0x18, 0x7fd9 },
1741 { 0x1c, 0xf0ff },
1742 { 0x1d, 0x3d9c },
5b538df9 1743 { 0x1f, 0x0003 },
daf9df6d 1744 { 0x12, 0xf49f },
1745 { 0x13, 0x070b },
1746 { 0x1a, 0x05ad },
1747 { 0x14, 0x94c0 }
1748 };
350f7596 1749 static const struct phy_reg phy_reg_init_1[] = {
5b538df9 1750 { 0x1f, 0x0002 },
daf9df6d 1751 { 0x06, 0x5561 },
1752 { 0x1f, 0x0005 },
1753 { 0x05, 0x8332 },
1754 { 0x06, 0x5561 }
1755 };
350f7596 1756 static const struct phy_reg phy_reg_init_2[] = {
daf9df6d 1757 { 0x1f, 0x0005 },
1758 { 0x05, 0xffc2 },
1759 { 0x1f, 0x0005 },
1760 { 0x05, 0x8000 },
1761 { 0x06, 0xf8f9 },
1762 { 0x06, 0xfaef },
1763 { 0x06, 0x59ee },
1764 { 0x06, 0xf8ea },
1765 { 0x06, 0x00ee },
1766 { 0x06, 0xf8eb },
1767 { 0x06, 0x00e0 },
1768 { 0x06, 0xf87c },
1769 { 0x06, 0xe1f8 },
1770 { 0x06, 0x7d59 },
1771 { 0x06, 0x0fef },
1772 { 0x06, 0x0139 },
1773 { 0x06, 0x029e },
1774 { 0x06, 0x06ef },
1775 { 0x06, 0x1039 },
1776 { 0x06, 0x089f },
1777 { 0x06, 0x2aee },
1778 { 0x06, 0xf8ea },
1779 { 0x06, 0x00ee },
1780 { 0x06, 0xf8eb },
1781 { 0x06, 0x01e0 },
1782 { 0x06, 0xf87c },
1783 { 0x06, 0xe1f8 },
1784 { 0x06, 0x7d58 },
1785 { 0x06, 0x409e },
1786 { 0x06, 0x0f39 },
1787 { 0x06, 0x46aa },
1788 { 0x06, 0x0bbf },
1789 { 0x06, 0x8290 },
1790 { 0x06, 0xd682 },
1791 { 0x06, 0x9802 },
1792 { 0x06, 0x014f },
1793 { 0x06, 0xae09 },
1794 { 0x06, 0xbf82 },
1795 { 0x06, 0x98d6 },
1796 { 0x06, 0x82a0 },
1797 { 0x06, 0x0201 },
1798 { 0x06, 0x4fef },
1799 { 0x06, 0x95fe },
1800 { 0x06, 0xfdfc },
1801 { 0x06, 0x05f8 },
1802 { 0x06, 0xf9fa },
1803 { 0x06, 0xeef8 },
1804 { 0x06, 0xea00 },
1805 { 0x06, 0xeef8 },
1806 { 0x06, 0xeb00 },
1807 { 0x06, 0xe2f8 },
1808 { 0x06, 0x7ce3 },
1809 { 0x06, 0xf87d },
1810 { 0x06, 0xa511 },
1811 { 0x06, 0x1112 },
1812 { 0x06, 0xd240 },
1813 { 0x06, 0xd644 },
1814 { 0x06, 0x4402 },
1815 { 0x06, 0x8217 },
1816 { 0x06, 0xd2a0 },
1817 { 0x06, 0xd6aa },
1818 { 0x06, 0xaa02 },
1819 { 0x06, 0x8217 },
1820 { 0x06, 0xae0f },
1821 { 0x06, 0xa544 },
1822 { 0x06, 0x4402 },
1823 { 0x06, 0xae4d },
1824 { 0x06, 0xa5aa },
1825 { 0x06, 0xaa02 },
1826 { 0x06, 0xae47 },
1827 { 0x06, 0xaf82 },
1828 { 0x06, 0x13ee },
1829 { 0x06, 0x834e },
1830 { 0x06, 0x00ee },
1831 { 0x06, 0x834d },
1832 { 0x06, 0x0fee },
1833 { 0x06, 0x834c },
1834 { 0x06, 0x0fee },
1835 { 0x06, 0x834f },
1836 { 0x06, 0x00ee },
1837 { 0x06, 0x8351 },
1838 { 0x06, 0x00ee },
1839 { 0x06, 0x834a },
1840 { 0x06, 0xffee },
1841 { 0x06, 0x834b },
1842 { 0x06, 0xffe0 },
1843 { 0x06, 0x8330 },
1844 { 0x06, 0xe183 },
1845 { 0x06, 0x3158 },
1846 { 0x06, 0xfee4 },
1847 { 0x06, 0xf88a },
1848 { 0x06, 0xe5f8 },
1849 { 0x06, 0x8be0 },
1850 { 0x06, 0x8332 },
1851 { 0x06, 0xe183 },
1852 { 0x06, 0x3359 },
1853 { 0x06, 0x0fe2 },
1854 { 0x06, 0x834d },
1855 { 0x06, 0x0c24 },
1856 { 0x06, 0x5af0 },
1857 { 0x06, 0x1e12 },
1858 { 0x06, 0xe4f8 },
1859 { 0x06, 0x8ce5 },
1860 { 0x06, 0xf88d },
1861 { 0x06, 0xaf82 },
1862 { 0x06, 0x13e0 },
1863 { 0x06, 0x834f },
1864 { 0x06, 0x10e4 },
1865 { 0x06, 0x834f },
1866 { 0x06, 0xe083 },
1867 { 0x06, 0x4e78 },
1868 { 0x06, 0x009f },
1869 { 0x06, 0x0ae0 },
1870 { 0x06, 0x834f },
1871 { 0x06, 0xa010 },
1872 { 0x06, 0xa5ee },
1873 { 0x06, 0x834e },
1874 { 0x06, 0x01e0 },
1875 { 0x06, 0x834e },
1876 { 0x06, 0x7805 },
1877 { 0x06, 0x9e9a },
1878 { 0x06, 0xe083 },
1879 { 0x06, 0x4e78 },
1880 { 0x06, 0x049e },
1881 { 0x06, 0x10e0 },
1882 { 0x06, 0x834e },
1883 { 0x06, 0x7803 },
1884 { 0x06, 0x9e0f },
1885 { 0x06, 0xe083 },
1886 { 0x06, 0x4e78 },
1887 { 0x06, 0x019e },
1888 { 0x06, 0x05ae },
1889 { 0x06, 0x0caf },
1890 { 0x06, 0x81f8 },
1891 { 0x06, 0xaf81 },
1892 { 0x06, 0xa3af },
1893 { 0x06, 0x81dc },
1894 { 0x06, 0xaf82 },
1895 { 0x06, 0x13ee },
1896 { 0x06, 0x8348 },
1897 { 0x06, 0x00ee },
1898 { 0x06, 0x8349 },
1899 { 0x06, 0x00e0 },
1900 { 0x06, 0x8351 },
1901 { 0x06, 0x10e4 },
1902 { 0x06, 0x8351 },
1903 { 0x06, 0x5801 },
1904 { 0x06, 0x9fea },
1905 { 0x06, 0xd000 },
1906 { 0x06, 0xd180 },
1907 { 0x06, 0x1f66 },
1908 { 0x06, 0xe2f8 },
1909 { 0x06, 0xeae3 },
1910 { 0x06, 0xf8eb },
1911 { 0x06, 0x5af8 },
1912 { 0x06, 0x1e20 },
1913 { 0x06, 0xe6f8 },
1914 { 0x06, 0xeae5 },
1915 { 0x06, 0xf8eb },
1916 { 0x06, 0xd302 },
1917 { 0x06, 0xb3fe },
1918 { 0x06, 0xe2f8 },
1919 { 0x06, 0x7cef },
1920 { 0x06, 0x325b },
1921 { 0x06, 0x80e3 },
1922 { 0x06, 0xf87d },
1923 { 0x06, 0x9e03 },
1924 { 0x06, 0x7dff },
1925 { 0x06, 0xff0d },
1926 { 0x06, 0x581c },
1927 { 0x06, 0x551a },
1928 { 0x06, 0x6511 },
1929 { 0x06, 0xa190 },
1930 { 0x06, 0xd3e2 },
1931 { 0x06, 0x8348 },
1932 { 0x06, 0xe383 },
1933 { 0x06, 0x491b },
1934 { 0x06, 0x56ab },
1935 { 0x06, 0x08ef },
1936 { 0x06, 0x56e6 },
1937 { 0x06, 0x8348 },
1938 { 0x06, 0xe783 },
1939 { 0x06, 0x4910 },
1940 { 0x06, 0xd180 },
1941 { 0x06, 0x1f66 },
1942 { 0x06, 0xa004 },
1943 { 0x06, 0xb9e2 },
1944 { 0x06, 0x8348 },
1945 { 0x06, 0xe383 },
1946 { 0x06, 0x49ef },
1947 { 0x06, 0x65e2 },
1948 { 0x06, 0x834a },
1949 { 0x06, 0xe383 },
1950 { 0x06, 0x4b1b },
1951 { 0x06, 0x56aa },
1952 { 0x06, 0x0eef },
1953 { 0x06, 0x56e6 },
1954 { 0x06, 0x834a },
1955 { 0x06, 0xe783 },
1956 { 0x06, 0x4be2 },
1957 { 0x06, 0x834d },
1958 { 0x06, 0xe683 },
1959 { 0x06, 0x4ce0 },
1960 { 0x06, 0x834d },
1961 { 0x06, 0xa000 },
1962 { 0x06, 0x0caf },
1963 { 0x06, 0x81dc },
1964 { 0x06, 0xe083 },
1965 { 0x06, 0x4d10 },
1966 { 0x06, 0xe483 },
1967 { 0x06, 0x4dae },
1968 { 0x06, 0x0480 },
1969 { 0x06, 0xe483 },
1970 { 0x06, 0x4de0 },
1971 { 0x06, 0x834e },
1972 { 0x06, 0x7803 },
1973 { 0x06, 0x9e0b },
1974 { 0x06, 0xe083 },
1975 { 0x06, 0x4e78 },
1976 { 0x06, 0x049e },
1977 { 0x06, 0x04ee },
1978 { 0x06, 0x834e },
1979 { 0x06, 0x02e0 },
1980 { 0x06, 0x8332 },
1981 { 0x06, 0xe183 },
1982 { 0x06, 0x3359 },
1983 { 0x06, 0x0fe2 },
1984 { 0x06, 0x834d },
1985 { 0x06, 0x0c24 },
1986 { 0x06, 0x5af0 },
1987 { 0x06, 0x1e12 },
1988 { 0x06, 0xe4f8 },
1989 { 0x06, 0x8ce5 },
1990 { 0x06, 0xf88d },
1991 { 0x06, 0xe083 },
1992 { 0x06, 0x30e1 },
1993 { 0x06, 0x8331 },
1994 { 0x06, 0x6801 },
1995 { 0x06, 0xe4f8 },
1996 { 0x06, 0x8ae5 },
1997 { 0x06, 0xf88b },
1998 { 0x06, 0xae37 },
1999 { 0x06, 0xee83 },
2000 { 0x06, 0x4e03 },
2001 { 0x06, 0xe083 },
2002 { 0x06, 0x4ce1 },
2003 { 0x06, 0x834d },
2004 { 0x06, 0x1b01 },
2005 { 0x06, 0x9e04 },
2006 { 0x06, 0xaaa1 },
2007 { 0x06, 0xaea8 },
2008 { 0x06, 0xee83 },
2009 { 0x06, 0x4e04 },
2010 { 0x06, 0xee83 },
2011 { 0x06, 0x4f00 },
2012 { 0x06, 0xaeab },
2013 { 0x06, 0xe083 },
2014 { 0x06, 0x4f78 },
2015 { 0x06, 0x039f },
2016 { 0x06, 0x14ee },
2017 { 0x06, 0x834e },
2018 { 0x06, 0x05d2 },
2019 { 0x06, 0x40d6 },
2020 { 0x06, 0x5554 },
2021 { 0x06, 0x0282 },
2022 { 0x06, 0x17d2 },
2023 { 0x06, 0xa0d6 },
2024 { 0x06, 0xba00 },
2025 { 0x06, 0x0282 },
2026 { 0x06, 0x17fe },
2027 { 0x06, 0xfdfc },
2028 { 0x06, 0x05f8 },
2029 { 0x06, 0xe0f8 },
2030 { 0x06, 0x60e1 },
2031 { 0x06, 0xf861 },
2032 { 0x06, 0x6802 },
2033 { 0x06, 0xe4f8 },
2034 { 0x06, 0x60e5 },
2035 { 0x06, 0xf861 },
2036 { 0x06, 0xe0f8 },
2037 { 0x06, 0x48e1 },
2038 { 0x06, 0xf849 },
2039 { 0x06, 0x580f },
2040 { 0x06, 0x1e02 },
2041 { 0x06, 0xe4f8 },
2042 { 0x06, 0x48e5 },
2043 { 0x06, 0xf849 },
2044 { 0x06, 0xd000 },
2045 { 0x06, 0x0282 },
2046 { 0x06, 0x5bbf },
2047 { 0x06, 0x8350 },
2048 { 0x06, 0xef46 },
2049 { 0x06, 0xdc19 },
2050 { 0x06, 0xddd0 },
2051 { 0x06, 0x0102 },
2052 { 0x06, 0x825b },
2053 { 0x06, 0x0282 },
2054 { 0x06, 0x77e0 },
2055 { 0x06, 0xf860 },
2056 { 0x06, 0xe1f8 },
2057 { 0x06, 0x6158 },
2058 { 0x06, 0xfde4 },
2059 { 0x06, 0xf860 },
2060 { 0x06, 0xe5f8 },
2061 { 0x06, 0x61fc },
2062 { 0x06, 0x04f9 },
2063 { 0x06, 0xfafb },
2064 { 0x06, 0xc6bf },
2065 { 0x06, 0xf840 },
2066 { 0x06, 0xbe83 },
2067 { 0x06, 0x50a0 },
2068 { 0x06, 0x0101 },
2069 { 0x06, 0x071b },
2070 { 0x06, 0x89cf },
2071 { 0x06, 0xd208 },
2072 { 0x06, 0xebdb },
2073 { 0x06, 0x19b2 },
2074 { 0x06, 0xfbff },
2075 { 0x06, 0xfefd },
2076 { 0x06, 0x04f8 },
2077 { 0x06, 0xe0f8 },
2078 { 0x06, 0x48e1 },
2079 { 0x06, 0xf849 },
2080 { 0x06, 0x6808 },
2081 { 0x06, 0xe4f8 },
2082 { 0x06, 0x48e5 },
2083 { 0x06, 0xf849 },
2084 { 0x06, 0x58f7 },
2085 { 0x06, 0xe4f8 },
2086 { 0x06, 0x48e5 },
2087 { 0x06, 0xf849 },
2088 { 0x06, 0xfc04 },
2089 { 0x06, 0x4d20 },
2090 { 0x06, 0x0002 },
2091 { 0x06, 0x4e22 },
2092 { 0x06, 0x0002 },
2093 { 0x06, 0x4ddf },
2094 { 0x06, 0xff01 },
2095 { 0x06, 0x4edd },
2096 { 0x06, 0xff01 },
2097 { 0x05, 0x83d4 },
2098 { 0x06, 0x8000 },
2099 { 0x05, 0x83d8 },
2100 { 0x06, 0x8051 },
2101 { 0x02, 0x6010 },
2102 { 0x03, 0xdc00 },
2103 { 0x05, 0xfff6 },
2104 { 0x06, 0x00fc },
5b538df9 2105 { 0x1f, 0x0000 },
daf9df6d 2106
5b538df9 2107 { 0x1f, 0x0000 },
daf9df6d 2108 { 0x0d, 0xf880 },
2109 { 0x1f, 0x0000 }
2110 };
2111
2112 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2113
2114 mdio_write(ioaddr, 0x1f, 0x0002);
2115 mdio_plus_minus(ioaddr, 0x0b, 0x0010, 0x00ef);
2116 mdio_plus_minus(ioaddr, 0x0c, 0xa200, 0x5d00);
2117
2118 rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1));
2119
2120 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2121 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2122 { 0x1f, 0x0002 },
2123 { 0x05, 0x669a },
2124 { 0x1f, 0x0005 },
2125 { 0x05, 0x8330 },
2126 { 0x06, 0x669a },
2127 { 0x1f, 0x0002 }
2128 };
2129 int val;
2130
2131 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2132
2133 val = mdio_read(ioaddr, 0x0d);
2134
2135 if ((val & 0x00ff) != 0x006c) {
350f7596 2136 static const u32 set[] = {
daf9df6d 2137 0x0065, 0x0066, 0x0067, 0x0068,
2138 0x0069, 0x006a, 0x006b, 0x006c
2139 };
2140 int i;
2141
2142 mdio_write(ioaddr, 0x1f, 0x0002);
2143
2144 val &= 0xff00;
2145 for (i = 0; i < ARRAY_SIZE(set); i++)
2146 mdio_write(ioaddr, 0x0d, val | set[i]);
2147 }
2148 } else {
350f7596 2149 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2150 { 0x1f, 0x0002 },
2151 { 0x05, 0x6662 },
2152 { 0x1f, 0x0005 },
2153 { 0x05, 0x8330 },
2154 { 0x06, 0x6662 }
2155 };
2156
2157 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2158 }
2159
2160 mdio_write(ioaddr, 0x1f, 0x0002);
2161 mdio_patch(ioaddr, 0x0d, 0x0300);
2162 mdio_patch(ioaddr, 0x0f, 0x0010);
2163
2164 mdio_write(ioaddr, 0x1f, 0x0002);
2165 mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600);
2166 mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);
2167
2168 rtl_phy_write(ioaddr, phy_reg_init_2, ARRAY_SIZE(phy_reg_init_2));
2169}
2170
2171static void rtl8168d_2_hw_phy_config(void __iomem *ioaddr)
2172{
350f7596 2173 static const struct phy_reg phy_reg_init_0[] = {
daf9df6d 2174 { 0x1f, 0x0001 },
2175 { 0x06, 0x4064 },
2176 { 0x07, 0x2863 },
2177 { 0x08, 0x059c },
2178 { 0x09, 0x26b4 },
2179 { 0x0a, 0x6a19 },
2180 { 0x0b, 0xdcc8 },
2181 { 0x10, 0xf06d },
2182 { 0x14, 0x7f68 },
2183 { 0x18, 0x7fd9 },
2184 { 0x1c, 0xf0ff },
2185 { 0x1d, 0x3d9c },
2186 { 0x1f, 0x0003 },
2187 { 0x12, 0xf49f },
2188 { 0x13, 0x070b },
2189 { 0x1a, 0x05ad },
2190 { 0x14, 0x94c0 },
2191
2192 { 0x1f, 0x0002 },
2193 { 0x06, 0x5561 },
2194 { 0x1f, 0x0005 },
2195 { 0x05, 0x8332 },
2196 { 0x06, 0x5561 }
2197 };
350f7596 2198 static const struct phy_reg phy_reg_init_1[] = {
daf9df6d 2199 { 0x1f, 0x0005 },
2200 { 0x05, 0xffc2 },
5b538df9 2201 { 0x1f, 0x0005 },
daf9df6d 2202 { 0x05, 0x8000 },
2203 { 0x06, 0xf8f9 },
2204 { 0x06, 0xfaee },
2205 { 0x06, 0xf8ea },
2206 { 0x06, 0x00ee },
2207 { 0x06, 0xf8eb },
2208 { 0x06, 0x00e2 },
2209 { 0x06, 0xf87c },
2210 { 0x06, 0xe3f8 },
2211 { 0x06, 0x7da5 },
2212 { 0x06, 0x1111 },
2213 { 0x06, 0x12d2 },
2214 { 0x06, 0x40d6 },
2215 { 0x06, 0x4444 },
2216 { 0x06, 0x0281 },
2217 { 0x06, 0xc6d2 },
2218 { 0x06, 0xa0d6 },
2219 { 0x06, 0xaaaa },
2220 { 0x06, 0x0281 },
2221 { 0x06, 0xc6ae },
2222 { 0x06, 0x0fa5 },
2223 { 0x06, 0x4444 },
2224 { 0x06, 0x02ae },
2225 { 0x06, 0x4da5 },
2226 { 0x06, 0xaaaa },
2227 { 0x06, 0x02ae },
2228 { 0x06, 0x47af },
2229 { 0x06, 0x81c2 },
2230 { 0x06, 0xee83 },
2231 { 0x06, 0x4e00 },
2232 { 0x06, 0xee83 },
2233 { 0x06, 0x4d0f },
2234 { 0x06, 0xee83 },
2235 { 0x06, 0x4c0f },
2236 { 0x06, 0xee83 },
2237 { 0x06, 0x4f00 },
2238 { 0x06, 0xee83 },
2239 { 0x06, 0x5100 },
2240 { 0x06, 0xee83 },
2241 { 0x06, 0x4aff },
2242 { 0x06, 0xee83 },
2243 { 0x06, 0x4bff },
2244 { 0x06, 0xe083 },
2245 { 0x06, 0x30e1 },
2246 { 0x06, 0x8331 },
2247 { 0x06, 0x58fe },
2248 { 0x06, 0xe4f8 },
2249 { 0x06, 0x8ae5 },
2250 { 0x06, 0xf88b },
2251 { 0x06, 0xe083 },
2252 { 0x06, 0x32e1 },
2253 { 0x06, 0x8333 },
2254 { 0x06, 0x590f },
2255 { 0x06, 0xe283 },
2256 { 0x06, 0x4d0c },
2257 { 0x06, 0x245a },
2258 { 0x06, 0xf01e },
2259 { 0x06, 0x12e4 },
2260 { 0x06, 0xf88c },
2261 { 0x06, 0xe5f8 },
2262 { 0x06, 0x8daf },
2263 { 0x06, 0x81c2 },
2264 { 0x06, 0xe083 },
2265 { 0x06, 0x4f10 },
2266 { 0x06, 0xe483 },
2267 { 0x06, 0x4fe0 },
2268 { 0x06, 0x834e },
2269 { 0x06, 0x7800 },
2270 { 0x06, 0x9f0a },
2271 { 0x06, 0xe083 },
2272 { 0x06, 0x4fa0 },
2273 { 0x06, 0x10a5 },
2274 { 0x06, 0xee83 },
2275 { 0x06, 0x4e01 },
2276 { 0x06, 0xe083 },
2277 { 0x06, 0x4e78 },
2278 { 0x06, 0x059e },
2279 { 0x06, 0x9ae0 },
2280 { 0x06, 0x834e },
2281 { 0x06, 0x7804 },
2282 { 0x06, 0x9e10 },
2283 { 0x06, 0xe083 },
2284 { 0x06, 0x4e78 },
2285 { 0x06, 0x039e },
2286 { 0x06, 0x0fe0 },
2287 { 0x06, 0x834e },
2288 { 0x06, 0x7801 },
2289 { 0x06, 0x9e05 },
2290 { 0x06, 0xae0c },
2291 { 0x06, 0xaf81 },
2292 { 0x06, 0xa7af },
2293 { 0x06, 0x8152 },
2294 { 0x06, 0xaf81 },
2295 { 0x06, 0x8baf },
2296 { 0x06, 0x81c2 },
2297 { 0x06, 0xee83 },
2298 { 0x06, 0x4800 },
2299 { 0x06, 0xee83 },
2300 { 0x06, 0x4900 },
2301 { 0x06, 0xe083 },
2302 { 0x06, 0x5110 },
2303 { 0x06, 0xe483 },
2304 { 0x06, 0x5158 },
2305 { 0x06, 0x019f },
2306 { 0x06, 0xead0 },
2307 { 0x06, 0x00d1 },
2308 { 0x06, 0x801f },
2309 { 0x06, 0x66e2 },
2310 { 0x06, 0xf8ea },
2311 { 0x06, 0xe3f8 },
2312 { 0x06, 0xeb5a },
2313 { 0x06, 0xf81e },
2314 { 0x06, 0x20e6 },
2315 { 0x06, 0xf8ea },
2316 { 0x06, 0xe5f8 },
2317 { 0x06, 0xebd3 },
2318 { 0x06, 0x02b3 },
2319 { 0x06, 0xfee2 },
2320 { 0x06, 0xf87c },
2321 { 0x06, 0xef32 },
2322 { 0x06, 0x5b80 },
2323 { 0x06, 0xe3f8 },
2324 { 0x06, 0x7d9e },
2325 { 0x06, 0x037d },
2326 { 0x06, 0xffff },
2327 { 0x06, 0x0d58 },
2328 { 0x06, 0x1c55 },
2329 { 0x06, 0x1a65 },
2330 { 0x06, 0x11a1 },
2331 { 0x06, 0x90d3 },
2332 { 0x06, 0xe283 },
2333 { 0x06, 0x48e3 },
2334 { 0x06, 0x8349 },
2335 { 0x06, 0x1b56 },
2336 { 0x06, 0xab08 },
2337 { 0x06, 0xef56 },
2338 { 0x06, 0xe683 },
2339 { 0x06, 0x48e7 },
2340 { 0x06, 0x8349 },
2341 { 0x06, 0x10d1 },
2342 { 0x06, 0x801f },
2343 { 0x06, 0x66a0 },
2344 { 0x06, 0x04b9 },
2345 { 0x06, 0xe283 },
2346 { 0x06, 0x48e3 },
2347 { 0x06, 0x8349 },
2348 { 0x06, 0xef65 },
2349 { 0x06, 0xe283 },
2350 { 0x06, 0x4ae3 },
2351 { 0x06, 0x834b },
2352 { 0x06, 0x1b56 },
2353 { 0x06, 0xaa0e },
2354 { 0x06, 0xef56 },
2355 { 0x06, 0xe683 },
2356 { 0x06, 0x4ae7 },
2357 { 0x06, 0x834b },
2358 { 0x06, 0xe283 },
2359 { 0x06, 0x4de6 },
2360 { 0x06, 0x834c },
2361 { 0x06, 0xe083 },
2362 { 0x06, 0x4da0 },
2363 { 0x06, 0x000c },
2364 { 0x06, 0xaf81 },
2365 { 0x06, 0x8be0 },
2366 { 0x06, 0x834d },
2367 { 0x06, 0x10e4 },
2368 { 0x06, 0x834d },
2369 { 0x06, 0xae04 },
2370 { 0x06, 0x80e4 },
2371 { 0x06, 0x834d },
2372 { 0x06, 0xe083 },
2373 { 0x06, 0x4e78 },
2374 { 0x06, 0x039e },
2375 { 0x06, 0x0be0 },
2376 { 0x06, 0x834e },
2377 { 0x06, 0x7804 },
2378 { 0x06, 0x9e04 },
2379 { 0x06, 0xee83 },
2380 { 0x06, 0x4e02 },
2381 { 0x06, 0xe083 },
2382 { 0x06, 0x32e1 },
2383 { 0x06, 0x8333 },
2384 { 0x06, 0x590f },
2385 { 0x06, 0xe283 },
2386 { 0x06, 0x4d0c },
2387 { 0x06, 0x245a },
2388 { 0x06, 0xf01e },
2389 { 0x06, 0x12e4 },
2390 { 0x06, 0xf88c },
2391 { 0x06, 0xe5f8 },
2392 { 0x06, 0x8de0 },
2393 { 0x06, 0x8330 },
2394 { 0x06, 0xe183 },
2395 { 0x06, 0x3168 },
2396 { 0x06, 0x01e4 },
2397 { 0x06, 0xf88a },
2398 { 0x06, 0xe5f8 },
2399 { 0x06, 0x8bae },
2400 { 0x06, 0x37ee },
2401 { 0x06, 0x834e },
2402 { 0x06, 0x03e0 },
2403 { 0x06, 0x834c },
2404 { 0x06, 0xe183 },
2405 { 0x06, 0x4d1b },
2406 { 0x06, 0x019e },
2407 { 0x06, 0x04aa },
2408 { 0x06, 0xa1ae },
2409 { 0x06, 0xa8ee },
2410 { 0x06, 0x834e },
2411 { 0x06, 0x04ee },
2412 { 0x06, 0x834f },
2413 { 0x06, 0x00ae },
2414 { 0x06, 0xabe0 },
2415 { 0x06, 0x834f },
2416 { 0x06, 0x7803 },
2417 { 0x06, 0x9f14 },
2418 { 0x06, 0xee83 },
2419 { 0x06, 0x4e05 },
2420 { 0x06, 0xd240 },
2421 { 0x06, 0xd655 },
2422 { 0x06, 0x5402 },
2423 { 0x06, 0x81c6 },
2424 { 0x06, 0xd2a0 },
2425 { 0x06, 0xd6ba },
2426 { 0x06, 0x0002 },
2427 { 0x06, 0x81c6 },
2428 { 0x06, 0xfefd },
2429 { 0x06, 0xfc05 },
2430 { 0x06, 0xf8e0 },
2431 { 0x06, 0xf860 },
2432 { 0x06, 0xe1f8 },
2433 { 0x06, 0x6168 },
2434 { 0x06, 0x02e4 },
2435 { 0x06, 0xf860 },
2436 { 0x06, 0xe5f8 },
2437 { 0x06, 0x61e0 },
2438 { 0x06, 0xf848 },
2439 { 0x06, 0xe1f8 },
2440 { 0x06, 0x4958 },
2441 { 0x06, 0x0f1e },
2442 { 0x06, 0x02e4 },
2443 { 0x06, 0xf848 },
2444 { 0x06, 0xe5f8 },
2445 { 0x06, 0x49d0 },
2446 { 0x06, 0x0002 },
2447 { 0x06, 0x820a },
2448 { 0x06, 0xbf83 },
2449 { 0x06, 0x50ef },
2450 { 0x06, 0x46dc },
2451 { 0x06, 0x19dd },
2452 { 0x06, 0xd001 },
2453 { 0x06, 0x0282 },
2454 { 0x06, 0x0a02 },
2455 { 0x06, 0x8226 },
2456 { 0x06, 0xe0f8 },
2457 { 0x06, 0x60e1 },
2458 { 0x06, 0xf861 },
2459 { 0x06, 0x58fd },
2460 { 0x06, 0xe4f8 },
2461 { 0x06, 0x60e5 },
2462 { 0x06, 0xf861 },
2463 { 0x06, 0xfc04 },
2464 { 0x06, 0xf9fa },
2465 { 0x06, 0xfbc6 },
2466 { 0x06, 0xbff8 },
2467 { 0x06, 0x40be },
2468 { 0x06, 0x8350 },
2469 { 0x06, 0xa001 },
2470 { 0x06, 0x0107 },
2471 { 0x06, 0x1b89 },
2472 { 0x06, 0xcfd2 },
2473 { 0x06, 0x08eb },
2474 { 0x06, 0xdb19 },
2475 { 0x06, 0xb2fb },
2476 { 0x06, 0xfffe },
2477 { 0x06, 0xfd04 },
2478 { 0x06, 0xf8e0 },
2479 { 0x06, 0xf848 },
2480 { 0x06, 0xe1f8 },
2481 { 0x06, 0x4968 },
2482 { 0x06, 0x08e4 },
2483 { 0x06, 0xf848 },
2484 { 0x06, 0xe5f8 },
2485 { 0x06, 0x4958 },
2486 { 0x06, 0xf7e4 },
2487 { 0x06, 0xf848 },
2488 { 0x06, 0xe5f8 },
2489 { 0x06, 0x49fc },
2490 { 0x06, 0x044d },
2491 { 0x06, 0x2000 },
2492 { 0x06, 0x024e },
2493 { 0x06, 0x2200 },
2494 { 0x06, 0x024d },
2495 { 0x06, 0xdfff },
2496 { 0x06, 0x014e },
2497 { 0x06, 0xddff },
2498 { 0x06, 0x0100 },
2499 { 0x05, 0x83d8 },
2500 { 0x06, 0x8000 },
2501 { 0x03, 0xdc00 },
2502 { 0x05, 0xfff6 },
2503 { 0x06, 0x00fc },
2504 { 0x1f, 0x0000 },
2505
2506 { 0x1f, 0x0000 },
2507 { 0x0d, 0xf880 },
2508 { 0x1f, 0x0000 }
5b538df9
FR		 2509 };
2510
2511 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2512
daf9df6d 2513 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2514 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2515 { 0x1f, 0x0002 },
2516 { 0x05, 0x669a },
5b538df9 2517 { 0x1f, 0x0005 },
daf9df6d 2518 { 0x05, 0x8330 },
2519 { 0x06, 0x669a },
2520
2521 { 0x1f, 0x0002 }
2522 };
2523 int val;
2524
2525 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2526
2527 val = mdio_read(ioaddr, 0x0d);
2528 if ((val & 0x00ff) != 0x006c) {
b6bc7650 2529 static const u32 set[] = {
daf9df6d 2530 0x0065, 0x0066, 0x0067, 0x0068,
2531 0x0069, 0x006a, 0x006b, 0x006c
2532 };
2533 int i;
2534
2535 mdio_write(ioaddr, 0x1f, 0x0002);
2536
2537 val &= 0xff00;
2538 for (i = 0; i < ARRAY_SIZE(set); i++)
2539 mdio_write(ioaddr, 0x0d, val | set[i]);
2540 }
2541 } else {
350f7596 2542 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2543 { 0x1f, 0x0002 },
2544 { 0x05, 0x2642 },
5b538df9 2545 { 0x1f, 0x0005 },
daf9df6d 2546 { 0x05, 0x8330 },
2547 { 0x06, 0x2642 }
5b538df9
FR		 2548 };
2549
daf9df6d 2550 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2551 }
2552
daf9df6d 2553 mdio_write(ioaddr, 0x1f, 0x0002);
2554 mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600);
2555 mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);
2556
2557 mdio_write(ioaddr, 0x1f, 0x0001);
2558 mdio_write(ioaddr, 0x17, 0x0cc0);
2559
2560 mdio_write(ioaddr, 0x1f, 0x0002);
2561 mdio_patch(ioaddr, 0x0f, 0x0017);
2562
2563 rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1));
2564}
2565
2566static void rtl8168d_3_hw_phy_config(void __iomem *ioaddr)
2567{
350f7596 2568 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2569 { 0x1f, 0x0002 },
2570 { 0x10, 0x0008 },
2571 { 0x0d, 0x006c },
2572
2573 { 0x1f, 0x0000 },
2574 { 0x0d, 0xf880 },
2575
2576 { 0x1f, 0x0001 },
2577 { 0x17, 0x0cc0 },
2578
2579 { 0x1f, 0x0001 },
2580 { 0x0b, 0xa4d8 },
2581 { 0x09, 0x281c },
2582 { 0x07, 0x2883 },
2583 { 0x0a, 0x6b35 },
2584 { 0x1d, 0x3da4 },
2585 { 0x1c, 0xeffd },
2586 { 0x14, 0x7f52 },
2587 { 0x18, 0x7fc6 },
2588 { 0x08, 0x0601 },
2589 { 0x06, 0x4063 },
2590 { 0x10, 0xf074 },
2591 { 0x1f, 0x0003 },
2592 { 0x13, 0x0789 },
2593 { 0x12, 0xf4bd },
2594 { 0x1a, 0x04fd },
2595 { 0x14, 0x84b0 },
2596 { 0x1f, 0x0000 },
2597 { 0x00, 0x9200 },
2598
2599 { 0x1f, 0x0005 },
2600 { 0x01, 0x0340 },
2601 { 0x1f, 0x0001 },
2602 { 0x04, 0x4000 },
2603 { 0x03, 0x1d21 },
2604 { 0x02, 0x0c32 },
2605 { 0x01, 0x0200 },
2606 { 0x00, 0x5554 },
2607 { 0x04, 0x4800 },
2608 { 0x04, 0x4000 },
2609 { 0x04, 0xf000 },
2610 { 0x03, 0xdf01 },
2611 { 0x02, 0xdf20 },
2612 { 0x01, 0x101a },
2613 { 0x00, 0xa0ff },
2614 { 0x04, 0xf800 },
2615 { 0x04, 0xf000 },
2616 { 0x1f, 0x0000 },
2617
2618 { 0x1f, 0x0007 },
2619 { 0x1e, 0x0023 },
2620 { 0x16, 0x0000 },
2621 { 0x1f, 0x0000 }
2622 };
2623
2624 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2625}
2626
2857ffb7
FR		 2627static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
2628{
350f7596 2629 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 2630 { 0x1f, 0x0003 },
2631 { 0x08, 0x441d },
2632 { 0x01, 0x9100 },
2633 { 0x1f, 0x0000 }
2634 };
2635
2636 mdio_write(ioaddr, 0x1f, 0x0000);
2637 mdio_patch(ioaddr, 0x11, 1 << 12);
2638 mdio_patch(ioaddr, 0x19, 1 << 13);
85910a8e 2639 mdio_patch(ioaddr, 0x10, 1 << 15);
2857ffb7
FR		 2640
2641 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2642}
2643
5615d9f1
FR		 2644static void rtl_hw_phy_config(struct net_device *dev)
2645{
2646 struct rtl8169_private *tp = netdev_priv(dev);
2647 void __iomem *ioaddr = tp->mmio_addr;
2648
2649 rtl8169_print_mac_version(tp);
2650
2651 switch (tp->mac_version) {
2652 case RTL_GIGA_MAC_VER_01:
2653 break;
2654 case RTL_GIGA_MAC_VER_02:
2655 case RTL_GIGA_MAC_VER_03:
2656 rtl8169s_hw_phy_config(ioaddr);
2657 break;
2658 case RTL_GIGA_MAC_VER_04:
2659 rtl8169sb_hw_phy_config(ioaddr);
2660 break;
2e955856 2661 case RTL_GIGA_MAC_VER_05:
2662 rtl8169scd_hw_phy_config(tp, ioaddr);
2663 break;
8c7006aa 2664 case RTL_GIGA_MAC_VER_06:
2665 rtl8169sce_hw_phy_config(ioaddr);
2666 break;
2857ffb7
FR		 2667 case RTL_GIGA_MAC_VER_07:
2668 case RTL_GIGA_MAC_VER_08:
2669 case RTL_GIGA_MAC_VER_09:
2670 rtl8102e_hw_phy_config(ioaddr);
2671 break;
236b8082
FR		 2672 case RTL_GIGA_MAC_VER_11:
2673 rtl8168bb_hw_phy_config(ioaddr);
2674 break;
2675 case RTL_GIGA_MAC_VER_12:
2676 rtl8168bef_hw_phy_config(ioaddr);
2677 break;
2678 case RTL_GIGA_MAC_VER_17:
2679 rtl8168bef_hw_phy_config(ioaddr);
2680 break;
867763c1 2681 case RTL_GIGA_MAC_VER_18:
ef3386f0 2682 rtl8168cp_1_hw_phy_config(ioaddr);
867763c1
FR		 2683 break;
2684 case RTL_GIGA_MAC_VER_19:
219a1e9d 2685 rtl8168c_1_hw_phy_config(ioaddr);
867763c1 2686 break;
7da97ec9 2687 case RTL_GIGA_MAC_VER_20:
219a1e9d 2688 rtl8168c_2_hw_phy_config(ioaddr);
7da97ec9 2689 break;
197ff761
FR		 2690 case RTL_GIGA_MAC_VER_21:
2691 rtl8168c_3_hw_phy_config(ioaddr);
2692 break;
6fb07058
FR		 2693 case RTL_GIGA_MAC_VER_22:
2694 rtl8168c_4_hw_phy_config(ioaddr);
2695 break;
ef3386f0 2696 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 2697 case RTL_GIGA_MAC_VER_24:
ef3386f0
FR		 2698 rtl8168cp_2_hw_phy_config(ioaddr);
2699 break;
5b538df9 2700 case RTL_GIGA_MAC_VER_25:
daf9df6d 2701 rtl8168d_1_hw_phy_config(ioaddr);
2702 break;
2703 case RTL_GIGA_MAC_VER_26:
2704 rtl8168d_2_hw_phy_config(ioaddr);
2705 break;
2706 case RTL_GIGA_MAC_VER_27:
2707 rtl8168d_3_hw_phy_config(ioaddr);
5b538df9 2708 break;
ef3386f0 2709
5615d9f1
FR		 2710 default:
2711 break;
2712 }
2713}
2714
1da177e4
LT		 2715static void rtl8169_phy_timer(unsigned long __opaque)
2716{
2717 struct net_device *dev = (struct net_device *)__opaque;
2718 struct rtl8169_private *tp = netdev_priv(dev);
2719 struct timer_list *timer = &tp->timer;
2720 void __iomem *ioaddr = tp->mmio_addr;
2721 unsigned long timeout = RTL8169_PHY_TIMEOUT;
2722
bcf0bf90 2723 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 2724
64e4bfb4 2725 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 2726 return;
2727
2728 spin_lock_irq(&tp->lock);
2729
2730 if (tp->phy_reset_pending(ioaddr)) {
5b0384f4 2731 /*
1da177e4
LT		 2732 * A busy loop could burn quite a few cycles on nowadays CPU.
2733 * Let's delay the execution of the timer for a few ticks.
2734 */
2735 timeout = HZ/10;
2736 goto out_mod_timer;
2737 }
2738
2739 if (tp->link_ok(ioaddr))
2740 goto out_unlock;
2741
bf82c189 2742 netif_warn(tp, link, dev, "PHY reset until link up\n");
1da177e4
LT		 2743
2744 tp->phy_reset_enable(ioaddr);
2745
2746out_mod_timer:
2747 mod_timer(timer, jiffies + timeout);
2748out_unlock:
2749 spin_unlock_irq(&tp->lock);
2750}
2751
2752static inline void rtl8169_delete_timer(struct net_device *dev)
2753{
2754 struct rtl8169_private *tp = netdev_priv(dev);
2755 struct timer_list *timer = &tp->timer;
2756
e179bb7b 2757 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 2758 return;
2759
2760 del_timer_sync(timer);
2761}
2762
2763static inline void rtl8169_request_timer(struct net_device *dev)
2764{
2765 struct rtl8169_private *tp = netdev_priv(dev);
2766 struct timer_list *timer = &tp->timer;
2767
e179bb7b 2768 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 2769 return;
2770
2efa53f3 2771 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1da177e4
LT		 2772}
2773
2774#ifdef CONFIG_NET_POLL_CONTROLLER
2775/*
2776 * Polling 'interrupt' - used by things like netconsole to send skbs
2777 * without having to re-enable interrupts. It's not called while
2778 * the interrupt routine is executing.
2779 */
2780static void rtl8169_netpoll(struct net_device *dev)
2781{
2782 struct rtl8169_private *tp = netdev_priv(dev);
2783 struct pci_dev *pdev = tp->pci_dev;
2784
2785 disable_irq(pdev->irq);
7d12e780 2786 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 2787 enable_irq(pdev->irq);
2788}
2789#endif
2790
2791static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2792 void __iomem *ioaddr)
2793{
2794 iounmap(ioaddr);
2795 pci_release_regions(pdev);
87aeec76 2796 pci_clear_mwi(pdev);
1da177e4
LT		 2797 pci_disable_device(pdev);
2798 free_netdev(dev);
2799}
2800
bf793295
FR		 2801static void rtl8169_phy_reset(struct net_device *dev,
2802 struct rtl8169_private *tp)
2803{
2804 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 2805 unsigned int i;
bf793295
FR		 2806
2807 tp->phy_reset_enable(ioaddr);
2808 for (i = 0; i < 100; i++) {
2809 if (!tp->phy_reset_pending(ioaddr))
2810 return;
2811 msleep(1);
2812 }
bf82c189 2813 netif_err(tp, link, dev, "PHY reset failed\n");
bf793295
FR		 2814}
2815
4ff96fa6
FR		 2816static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2817{
2818 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 2819
5615d9f1 2820 rtl_hw_phy_config(dev);
4ff96fa6 2821
77332894
MS		 2822 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2823 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2824 RTL_W8(0x82, 0x01);
2825 }
4ff96fa6 2826
6dccd16b
FR		 2827 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2828
2829 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2830 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 2831
bcf0bf90 2832 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 2833 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2834 RTL_W8(0x82, 0x01);
2835 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2836 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
2837 }
2838
bf793295
FR		 2839 rtl8169_phy_reset(dev, tp);
2840
901dda2b
FR		 2841 /*
2842 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
2843 * only 8101. Don't panic.
2844 */
2845 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
4ff96fa6 2846
bf82c189
JP		 2847 if (RTL_R8(PHYstatus) & TBI_Enable)
2848 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 2849}
2850
773d2021
FR		 2851static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2852{
2853 void __iomem *ioaddr = tp->mmio_addr;
2854 u32 high;
2855 u32 low;
2856
2857 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2858 high = addr[4] | (addr[5] << 8);
2859
2860 spin_lock_irq(&tp->lock);
2861
2862 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 2863
773d2021 2864 RTL_W32(MAC4, high);
908ba2bf 2865 RTL_R32(MAC4);
2866
78f1cd02 2867 RTL_W32(MAC0, low);
908ba2bf 2868 RTL_R32(MAC0);
2869
773d2021
FR		 2870 RTL_W8(Cfg9346, Cfg9346_Lock);
2871
2872 spin_unlock_irq(&tp->lock);
2873}
2874
2875static int rtl_set_mac_address(struct net_device *dev, void *p)
2876{
2877 struct rtl8169_private *tp = netdev_priv(dev);
2878 struct sockaddr *addr = p;
2879
2880 if (!is_valid_ether_addr(addr->sa_data))
2881 return -EADDRNOTAVAIL;
2882
2883 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2884
2885 rtl_rar_set(tp, dev->dev_addr);
2886
2887 return 0;
2888}
2889
5f787a1a
FR		 2890static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2891{
2892 struct rtl8169_private *tp = netdev_priv(dev);
2893 struct mii_ioctl_data *data = if_mii(ifr);
2894
8b4ab28d
FR		 2895 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2896}
5f787a1a 2897
8b4ab28d
FR		 2898static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2899{
5f787a1a
FR		 2900 switch (cmd) {
2901 case SIOCGMIIPHY:
2902 data->phy_id = 32; /* Internal PHY */
2903 return 0;
2904
2905 case SIOCGMIIREG:
2906 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
2907 return 0;
2908
2909 case SIOCSMIIREG:
5f787a1a
FR		 2910 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
2911 return 0;
2912 }
2913 return -EOPNOTSUPP;
2914}
2915
8b4ab28d
FR		 2916static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2917{
2918 return -EOPNOTSUPP;
2919}
2920
0e485150
FR		 2921static const struct rtl_cfg_info {
2922 void (*hw_start)(struct net_device *);
2923 unsigned int region;
2924 unsigned int align;
2925 u16 intr_event;
2926 u16 napi_event;
ccdffb9a 2927 unsigned features;
f21b75e9 2928 u8 default_ver;
0e485150
FR		 2929} rtl_cfg_infos [] = {
2930 [RTL_CFG_0] = {
2931 .hw_start = rtl_hw_start_8169,
2932 .region = 1,
e9f63f30 2933 .align = 0,
0e485150
FR		 2934 .intr_event = SYSErr | LinkChg | RxOverflow |
2935 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 2936 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2937 .features = RTL_FEATURE_GMII,
2938 .default_ver = RTL_GIGA_MAC_VER_01,
0e485150
FR		 2939 },
2940 [RTL_CFG_1] = {
2941 .hw_start = rtl_hw_start_8168,
2942 .region = 2,
2943 .align = 8,
53f57357 2944 .intr_event = SYSErr | LinkChg | RxOverflow |
0e485150 2945 TxErr | TxOK | RxOK | RxErr,
fbac58fc 2946 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2947 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2948 .default_ver = RTL_GIGA_MAC_VER_11,
0e485150
FR		 2949 },
2950 [RTL_CFG_2] = {
2951 .hw_start = rtl_hw_start_8101,
2952 .region = 2,
2953 .align = 8,
2954 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2955 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 2956 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2957 .features = RTL_FEATURE_MSI,
2958 .default_ver = RTL_GIGA_MAC_VER_13,
0e485150
FR		 2959 }
2960};
2961
fbac58fc
FR		 2962/* Cfg9346_Unlock assumed. */
2963static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2964 const struct rtl_cfg_info *cfg)
2965{
2966 unsigned msi = 0;
2967 u8 cfg2;
2968
2969 cfg2 = RTL_R8(Config2) & ~MSIEnable;
ccdffb9a 2970 if (cfg->features & RTL_FEATURE_MSI) {
fbac58fc
FR		 2971 if (pci_enable_msi(pdev)) {
2972 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2973 } else {
2974 cfg2 |= MSIEnable;
2975 msi = RTL_FEATURE_MSI;
2976 }
2977 }
2978 RTL_W8(Config2, cfg2);
2979 return msi;
2980}
2981
2982static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2983{
2984 if (tp->features & RTL_FEATURE_MSI) {
2985 pci_disable_msi(pdev);
2986 tp->features &= ~RTL_FEATURE_MSI;
2987 }
2988}
2989
8b4ab28d
FR		 2990static const struct net_device_ops rtl8169_netdev_ops = {
2991 .ndo_open = rtl8169_open,
2992 .ndo_stop = rtl8169_close,
2993 .ndo_get_stats = rtl8169_get_stats,
00829823 2994 .ndo_start_xmit = rtl8169_start_xmit,
8b4ab28d
FR		 2995 .ndo_tx_timeout = rtl8169_tx_timeout,
2996 .ndo_validate_addr = eth_validate_addr,
2997 .ndo_change_mtu = rtl8169_change_mtu,
2998 .ndo_set_mac_address = rtl_set_mac_address,
2999 .ndo_do_ioctl = rtl8169_ioctl,
3000 .ndo_set_multicast_list = rtl_set_rx_mode,
3001#ifdef CONFIG_R8169_VLAN
3002 .ndo_vlan_rx_register = rtl8169_vlan_rx_register,
3003#endif
3004#ifdef CONFIG_NET_POLL_CONTROLLER
3005 .ndo_poll_controller = rtl8169_netpoll,
3006#endif
3007
3008};
3009
1da177e4 3010static int __devinit
4ff96fa6 3011rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 3012{
0e485150
FR		 3013 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3014 const unsigned int region = cfg->region;
1da177e4 3015 struct rtl8169_private *tp;
ccdffb9a 3016 struct mii_if_info *mii;
4ff96fa6
FR		 3017 struct net_device *dev;
3018 void __iomem *ioaddr;
07d3f51f
FR		 3019 unsigned int i;
3020 int rc;
1da177e4 3021
4ff96fa6
FR		 3022 if (netif_msg_drv(&debug)) {
3023 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3024 MODULENAME, RTL8169_VERSION);
3025 }
1da177e4 3026
1da177e4 3027 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 3028 if (!dev) {
b57b7e5a 3029 if (netif_msg_drv(&debug))
9b91cf9d 3030 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 3031 rc = -ENOMEM;
3032 goto out;
1da177e4
LT		 3033 }
3034
1da177e4 3035 SET_NETDEV_DEV(dev, &pdev->dev);
8b4ab28d 3036 dev->netdev_ops = &rtl8169_netdev_ops;
1da177e4 3037 tp = netdev_priv(dev);
c4028958 3038 tp->dev = dev;
21e197f2 3039 tp->pci_dev = pdev;
b57b7e5a 3040 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4 3041
ccdffb9a
FR		 3042 mii = &tp->mii;
3043 mii->dev = dev;
3044 mii->mdio_read = rtl_mdio_read;
3045 mii->mdio_write = rtl_mdio_write;
3046 mii->phy_id_mask = 0x1f;
3047 mii->reg_num_mask = 0x1f;
3048 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3049
1da177e4
LT		 3050 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3051 rc = pci_enable_device(pdev);
b57b7e5a 3052 if (rc < 0) {
bf82c189 3053 netif_err(tp, probe, dev, "enable failure\n");
4ff96fa6 3054 goto err_out_free_dev_1;
1da177e4
LT		 3055 }
3056
87aeec76 3057 if (pci_set_mwi(pdev) < 0)
3058 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
1da177e4 3059
1da177e4 3060 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 3061 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
bf82c189
JP		 3062 netif_err(tp, probe, dev,
3063 "region #%d not an MMIO resource, aborting\n",
3064 region);
1da177e4 3065 rc = -ENODEV;
87aeec76 3066 goto err_out_mwi_2;
1da177e4 3067 }
4ff96fa6 3068
1da177e4 3069 /* check for weird/broken PCI region reporting */
bcf0bf90 3070 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
bf82c189
JP		 3071 netif_err(tp, probe, dev,
3072 "Invalid PCI region size(s), aborting\n");
1da177e4 3073 rc = -ENODEV;
87aeec76 3074 goto err_out_mwi_2;
1da177e4
LT		 3075 }
3076
3077 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 3078 if (rc < 0) {
bf82c189 3079 netif_err(tp, probe, dev, "could not request regions\n");
87aeec76 3080 goto err_out_mwi_2;
1da177e4
LT		 3081 }
3082
3083 tp->cp_cmd = PCIMulRW | RxChkSum;
3084
3085 if ((sizeof(dma_addr_t) > 4) &&
4300e8c7 3086 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
1da177e4
LT		 3087 tp->cp_cmd |= PCIDAC;
3088 dev->features |= NETIF_F_HIGHDMA;
3089 } else {
284901a9 3090 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 3091 if (rc < 0) {
bf82c189 3092 netif_err(tp, probe, dev, "DMA configuration failed\n");
87aeec76 3093 goto err_out_free_res_3;
1da177e4
LT		 3094 }
3095 }
3096
1da177e4 3097 /* ioremap MMIO region */
bcf0bf90 3098 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 3099 if (!ioaddr) {
bf82c189 3100 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
1da177e4 3101 rc = -EIO;
87aeec76 3102 goto err_out_free_res_3;
1da177e4
LT		 3103 }
3104
4300e8c7
DM		 3105 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3106 if (!tp->pcie_cap)
3107 netif_info(tp, probe, dev, "no PCI Express capability\n");
3108
d78ad8cb 3109 RTL_W16(IntrMask, 0x0000);
1da177e4
LT		 3110
3111 /* Soft reset the chip. */
3112 RTL_W8(ChipCmd, CmdReset);
3113
3114 /* Check that the chip has finished the reset. */
07d3f51f 3115 for (i = 0; i < 100; i++) {
1da177e4
LT		 3116 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3117 break;
b518fa8e 3118 msleep_interruptible(1);
1da177e4
LT		 3119 }
3120
d78ad8cb
KW		 3121 RTL_W16(IntrStatus, 0xffff);
3122
ca52efd5 3123 pci_set_master(pdev);
3124
1da177e4
LT		 3125 /* Identify chip attached to board */
3126 rtl8169_get_mac_version(tp, ioaddr);
1da177e4 3127
f21b75e9
JD		 3128 /* Use appropriate default if unknown */
3129 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
bf82c189
JP		 3130 netif_notice(tp, probe, dev,
3131 "unknown MAC, using family default\n");
f21b75e9
JD		 3132 tp->mac_version = cfg->default_ver;
3133 }
3134
1da177e4 3135 rtl8169_print_mac_version(tp);
1da177e4 3136
cee60c37 3137 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
1da177e4
LT		 3138 if (tp->mac_version == rtl_chip_info[i].mac_version)
3139 break;
3140 }
cee60c37 3141 if (i == ARRAY_SIZE(rtl_chip_info)) {
f21b75e9
JD		 3142 dev_err(&pdev->dev,
3143 "driver bug, MAC version not found in rtl_chip_info\n");
87aeec76 3144 goto err_out_msi_4;
1da177e4
LT		 3145 }
3146 tp->chipset = i;
3147
5d06a99f
FR		 3148 RTL_W8(Cfg9346, Cfg9346_Unlock);
3149 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3150 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
20037fa4
BP		 3151 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3152 tp->features |= RTL_FEATURE_WOL;
3153 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3154 tp->features |= RTL_FEATURE_WOL;
fbac58fc 3155 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
5d06a99f
FR		 3156 RTL_W8(Cfg9346, Cfg9346_Lock);
3157
66ec5d4f
FR		 3158 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3159 (RTL_R8(PHYstatus) & TBI_Enable)) {
1da177e4
LT		 3160 tp->set_speed = rtl8169_set_speed_tbi;
3161 tp->get_settings = rtl8169_gset_tbi;
3162 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3163 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3164 tp->link_ok = rtl8169_tbi_link_ok;
8b4ab28d 3165 tp->do_ioctl = rtl_tbi_ioctl;
1da177e4 3166
64e4bfb4 3167 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1da177e4
LT		 3168 } else {
3169 tp->set_speed = rtl8169_set_speed_xmii;
3170 tp->get_settings = rtl8169_gset_xmii;
3171 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3172 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3173 tp->link_ok = rtl8169_xmii_link_ok;
8b4ab28d 3174 tp->do_ioctl = rtl_xmii_ioctl;
1da177e4
LT		 3175 }
3176
df58ef51
FR		 3177 spin_lock_init(&tp->lock);
3178
738e1e69
PV		 3179 tp->mmio_addr = ioaddr;
3180
7bf6bf48 3181 /* Get MAC address */
1da177e4
LT		 3182 for (i = 0; i < MAC_ADDR_LEN; i++)
3183 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 3184 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4 3185
1da177e4 3186 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1da177e4
LT		 3187 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3188 dev->irq = pdev->irq;
3189 dev->base_addr = (unsigned long) ioaddr;
1da177e4 3190
bea3348e 3191 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4
LT		 3192
3193#ifdef CONFIG_R8169_VLAN
3194 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4 3195#endif
2edae08e 3196 dev->features |= NETIF_F_GRO;
1da177e4
LT		 3197
3198 tp->intr_mask = 0xffff;
0e485150
FR		 3199 tp->hw_start = cfg->hw_start;
3200 tp->intr_event = cfg->intr_event;
3201 tp->napi_event = cfg->napi_event;
1da177e4 3202
2efa53f3
FR		 3203 init_timer(&tp->timer);
3204 tp->timer.data = (unsigned long) dev;
3205 tp->timer.function = rtl8169_phy_timer;
3206
1da177e4 3207 rc = register_netdev(dev);
4ff96fa6 3208 if (rc < 0)
87aeec76 3209 goto err_out_msi_4;
1da177e4
LT		 3210
3211 pci_set_drvdata(pdev, dev);
3212
bf82c189
JP		 3213 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3214 rtl_chip_info[tp->chipset].name,
3215 dev->base_addr, dev->dev_addr,
3216 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
1da177e4 3217
4ff96fa6 3218 rtl8169_init_phy(dev, tp);
05af2142
SW		 3219
3220 /*
3221 * Pretend we are using VLANs; This bypasses a nasty bug where
3222 * Interrupts stop flowing on high load on 8110SCd controllers.
3223 */
3224 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3225 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | RxVlan);
3226
8b76ab39 3227 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
1da177e4 3228
f3ec4f87
AS		 3229 if (pci_dev_run_wake(pdev))
3230 pm_runtime_put_noidle(&pdev->dev);
e1759441 3231
4ff96fa6
FR		 3232out:
3233 return rc;
1da177e4 3234
87aeec76 3235err_out_msi_4:
fbac58fc 3236 rtl_disable_msi(pdev, tp);
4ff96fa6 3237 iounmap(ioaddr);
87aeec76 3238err_out_free_res_3:
4ff96fa6 3239 pci_release_regions(pdev);
87aeec76 3240err_out_mwi_2:
4ff96fa6 3241 pci_clear_mwi(pdev);
4ff96fa6
FR		 3242 pci_disable_device(pdev);
3243err_out_free_dev_1:
3244 free_netdev(dev);
3245 goto out;
1da177e4
LT		 3246}
3247
07d3f51f 3248static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 3249{
3250 struct net_device *dev = pci_get_drvdata(pdev);
3251 struct rtl8169_private *tp = netdev_priv(dev);
3252
23f333a2 3253 cancel_delayed_work_sync(&tp->task);
eb2a021c 3254
1da177e4 3255 unregister_netdev(dev);
cc098dc7 3256
f3ec4f87
AS		 3257 if (pci_dev_run_wake(pdev))
3258 pm_runtime_get_noresume(&pdev->dev);
e1759441 3259
cc098dc7
IV		 3260 /* restore original MAC address */
3261 rtl_rar_set(tp, dev->perm_addr);
3262
fbac58fc 3263 rtl_disable_msi(pdev, tp);
1da177e4
LT		 3264 rtl8169_release_board(pdev, dev, tp->mmio_addr);
3265 pci_set_drvdata(pdev, NULL);
3266}
3267
1da177e4
LT		 3268static int rtl8169_open(struct net_device *dev)
3269{
3270 struct rtl8169_private *tp = netdev_priv(dev);
3271 struct pci_dev *pdev = tp->pci_dev;
99f252b0 3272 int retval = -ENOMEM;
1da177e4 3273
e1759441 3274 pm_runtime_get_sync(&pdev->dev);
1da177e4 3275
1da177e4
LT		 3276 /*
3277 * Rx and Tx desscriptors needs 256 bytes alignment.
82553bb6 3278 * dma_alloc_coherent provides more.
1da177e4 3279 */
82553bb6
SG		 3280 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3281 &tp->TxPhyAddr, GFP_KERNEL);
1da177e4 3282 if (!tp->TxDescArray)
e1759441 3283 goto err_pm_runtime_put;
1da177e4 3284
82553bb6
SG		 3285 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3286 &tp->RxPhyAddr, GFP_KERNEL);
1da177e4 3287 if (!tp->RxDescArray)
99f252b0 3288 goto err_free_tx_0;
1da177e4
LT		 3289
3290 retval = rtl8169_init_ring(dev);
3291 if (retval < 0)
99f252b0 3292 goto err_free_rx_1;
1da177e4 3293
c4028958 3294 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 3295
99f252b0
FR		 3296 smp_mb();
3297
fbac58fc
FR		 3298 retval = request_irq(dev->irq, rtl8169_interrupt,
3299 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 3300 dev->name, dev);
3301 if (retval < 0)
3302 goto err_release_ring_2;
3303
bea3348e 3304 napi_enable(&tp->napi);
bea3348e 3305
07ce4064 3306 rtl_hw_start(dev);
1da177e4
LT		 3307
3308 rtl8169_request_timer(dev);
3309
e1759441
RW		 3310 tp->saved_wolopts = 0;
3311 pm_runtime_put_noidle(&pdev->dev);
3312
1da177e4
LT		 3313 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
3314out:
3315 return retval;
3316
99f252b0
FR		 3317err_release_ring_2:
3318 rtl8169_rx_clear(tp);
3319err_free_rx_1:
82553bb6
SG		 3320 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3321 tp->RxPhyAddr);
e1759441 3322 tp->RxDescArray = NULL;
99f252b0 3323err_free_tx_0:
82553bb6
SG		 3324 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3325 tp->TxPhyAddr);
e1759441
RW		 3326 tp->TxDescArray = NULL;
3327err_pm_runtime_put:
3328 pm_runtime_put_noidle(&pdev->dev);
1da177e4
LT		 3329 goto out;
3330}
3331
3332static void rtl8169_hw_reset(void __iomem *ioaddr)
3333{
3334 /* Disable interrupts */
3335 rtl8169_irq_mask_and_ack(ioaddr);
3336
3337 /* Reset the chipset */
3338 RTL_W8(ChipCmd, CmdReset);
3339
3340 /* PCI commit */
3341 RTL_R8(ChipCmd);
3342}
3343
7f796d83 3344static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 3345{
3346 void __iomem *ioaddr = tp->mmio_addr;
3347 u32 cfg = rtl8169_rx_config;
3348
3349 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3350 RTL_W32(RxConfig, cfg);
3351
3352 /* Set DMA burst size and Interframe Gap Time */
3353 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3354 (InterFrameGap << TxInterFrameGapShift));
3355}
3356
07ce4064 3357static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 3358{
3359 struct rtl8169_private *tp = netdev_priv(dev);
3360 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 3361 unsigned int i;
1da177e4
LT		 3362
3363 /* Soft reset the chip. */
3364 RTL_W8(ChipCmd, CmdReset);
3365
3366 /* Check that the chip has finished the reset. */
07d3f51f 3367 for (i = 0; i < 100; i++) {
1da177e4
LT		 3368 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3369 break;
b518fa8e 3370 msleep_interruptible(1);
1da177e4
LT		 3371 }
3372
07ce4064
FR		 3373 tp->hw_start(dev);
3374
07ce4064
FR		 3375 netif_start_queue(dev);
3376}
3377
3378
7f796d83
FR		 3379static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3380 void __iomem *ioaddr)
3381{
3382 /*
3383 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3384 * register to be written before TxDescAddrLow to work.
3385 * Switching from MMIO to I/O access fixes the issue as well.
3386 */
3387 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 3388 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 3389 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 3390 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 3391}
3392
3393static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3394{
3395 u16 cmd;
3396
3397 cmd = RTL_R16(CPlusCmd);
3398 RTL_W16(CPlusCmd, cmd);
3399 return cmd;
3400}
3401
fdd7b4c3 3402static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 3403{
3404 /* Low hurts. Let's disable the filtering. */
207d6e87 3405 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 3406}
3407
6dccd16b
FR		 3408static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3409{
350f7596 3410 static const struct {
6dccd16b
FR		 3411 u32 mac_version;
3412 u32 clk;
3413 u32 val;
3414 } cfg2_info [] = {
3415 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3416 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3417 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3418 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3419 }, *p = cfg2_info;
3420 unsigned int i;
3421 u32 clk;
3422
3423 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 3424 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 3425 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3426 RTL_W32(0x7c, p->val);
3427 break;
3428 }
3429 }
3430}
3431
07ce4064
FR		 3432static void rtl_hw_start_8169(struct net_device *dev)
3433{
3434 struct rtl8169_private *tp = netdev_priv(dev);
3435 void __iomem *ioaddr = tp->mmio_addr;
3436 struct pci_dev *pdev = tp->pci_dev;
07ce4064 3437
9cb427b6
FR		 3438 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3439 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3440 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3441 }
3442
1da177e4 3443 RTL_W8(Cfg9346, Cfg9346_Unlock);
9cb427b6
FR		 3444 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3445 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3446 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3447 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3448 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3449
1da177e4
LT		 3450 RTL_W8(EarlyTxThres, EarlyTxThld);
3451
6f0333b8 3452 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
1da177e4 3453
c946b304
FR		 3454 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3455 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3456 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3457 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3458 rtl_set_rx_tx_config_registers(tp);
1da177e4 3459
7f796d83 3460 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 3461
bcf0bf90
FR		 3462 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3463 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
06fa7358 3464 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 3465 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 3466 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 3467 }
3468
bcf0bf90
FR		 3469 RTL_W16(CPlusCmd, tp->cp_cmd);
3470
6dccd16b
FR		 3471 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3472
1da177e4
LT		 3473 /*
3474 * Undocumented corner. Supposedly:
3475 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3476 */
3477 RTL_W16(IntrMitigate, 0x0000);
3478
7f796d83 3479 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 3480
c946b304
FR		 3481 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
3482 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
3483 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
3484 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
3485 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3486 rtl_set_rx_tx_config_registers(tp);
3487 }
3488
1da177e4 3489 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 3490
3491 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3492 RTL_R8(IntrMask);
1da177e4
LT		 3493
3494 RTL_W32(RxMissed, 0);
3495
07ce4064 3496 rtl_set_rx_mode(dev);
1da177e4
LT		 3497
3498 /* no early-rx interrupts */
3499 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 3500
3501 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 3502 RTL_W16(IntrMask, tp->intr_event);
07ce4064 3503}
1da177e4 3504
9c14ceaf 3505static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
458a9f61 3506{
9c14ceaf
FR		 3507 struct net_device *dev = pci_get_drvdata(pdev);
3508 struct rtl8169_private *tp = netdev_priv(dev);
3509 int cap = tp->pcie_cap;
3510
3511 if (cap) {
3512 u16 ctl;
458a9f61 3513
9c14ceaf
FR		 3514 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3515 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3516 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3517 }
458a9f61
FR		 3518}
3519
dacf8154
FR		 3520static void rtl_csi_access_enable(void __iomem *ioaddr)
3521{
3522 u32 csi;
3523
3524 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
3525 rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
3526}
3527
3528struct ephy_info {
3529 unsigned int offset;
3530 u16 mask;
3531 u16 bits;
3532};
3533
350f7596 3534static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
dacf8154
FR		 3535{
3536 u16 w;
3537
3538 while (len-- > 0) {
3539 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3540 rtl_ephy_write(ioaddr, e->offset, w);
3541 e++;
3542 }
3543}
3544
b726e493
FR		 3545static void rtl_disable_clock_request(struct pci_dev *pdev)
3546{
3547 struct net_device *dev = pci_get_drvdata(pdev);
3548 struct rtl8169_private *tp = netdev_priv(dev);
3549 int cap = tp->pcie_cap;
3550
3551 if (cap) {
3552 u16 ctl;
3553
3554 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3555 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3556 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3557 }
3558}
3559
3560#define R8168_CPCMD_QUIRK_MASK (\
3561 EnableBist | \
3562 Mac_dbgo_oe | \
3563 Force_half_dup | \
3564 Force_rxflow_en | \
3565 Force_txflow_en | \
3566 Cxpl_dbg_sel | \
3567 ASF | \
3568 PktCntrDisable | \
3569 Mac_dbgo_sel)
3570
219a1e9d
FR		 3571static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3572{
b726e493
FR		 3573 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3574
3575 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3576
2e68ae44
FR		 3577 rtl_tx_performance_tweak(pdev,
3578 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
219a1e9d
FR		 3579}
3580
3581static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3582{
3583 rtl_hw_start_8168bb(ioaddr, pdev);
b726e493
FR		 3584
3585 RTL_W8(EarlyTxThres, EarlyTxThld);
3586
3587 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 3588}
3589
3590static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3591{
b726e493
FR		 3592 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3593
3594 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3595
219a1e9d 3596 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 3597
3598 rtl_disable_clock_request(pdev);
3599
3600 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 3601}
3602
ef3386f0 3603static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
219a1e9d 3604{
350f7596 3605 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 3606 { 0x01, 0, 0x0001 },
3607 { 0x02, 0x0800, 0x1000 },
3608 { 0x03, 0, 0x0042 },
3609 { 0x06, 0x0080, 0x0000 },
3610 { 0x07, 0, 0x2000 }
3611 };
3612
3613 rtl_csi_access_enable(ioaddr);
3614
3615 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3616
219a1e9d
FR		 3617 __rtl_hw_start_8168cp(ioaddr, pdev);
3618}
3619
ef3386f0
FR		 3620static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3621{
3622 rtl_csi_access_enable(ioaddr);
3623
3624 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3625
3626 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3627
3628 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3629}
3630
7f3e3d3a
FR		 3631static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3632{
3633 rtl_csi_access_enable(ioaddr);
3634
3635 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3636
3637 /* Magic. */
3638 RTL_W8(DBG_REG, 0x20);
3639
3640 RTL_W8(EarlyTxThres, EarlyTxThld);
3641
3642 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3643
3644 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3645}
3646
219a1e9d
FR		 3647static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3648{
350f7596 3649 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 3650 { 0x02, 0x0800, 0x1000 },
3651 { 0x03, 0, 0x0002 },
3652 { 0x06, 0x0080, 0x0000 }
3653 };
3654
3655 rtl_csi_access_enable(ioaddr);
3656
3657 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3658
3659 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3660
219a1e9d
FR		 3661 __rtl_hw_start_8168cp(ioaddr, pdev);
3662}
3663
3664static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3665{
350f7596 3666 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 3667 { 0x01, 0, 0x0001 },
3668 { 0x03, 0x0400, 0x0220 }
3669 };
3670
3671 rtl_csi_access_enable(ioaddr);
3672
3673 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3674
219a1e9d
FR		 3675 __rtl_hw_start_8168cp(ioaddr, pdev);
3676}
3677
197ff761
FR		 3678static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3679{
3680 rtl_hw_start_8168c_2(ioaddr, pdev);
3681}
3682
6fb07058
FR		 3683static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3684{
3685 rtl_csi_access_enable(ioaddr);
3686
3687 __rtl_hw_start_8168cp(ioaddr, pdev);
3688}
3689
5b538df9
FR		 3690static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3691{
3692 rtl_csi_access_enable(ioaddr);
3693
3694 rtl_disable_clock_request(pdev);
3695
3696 RTL_W8(EarlyTxThres, EarlyTxThld);
3697
3698 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3699
3700 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3701}
3702
07ce4064
FR		 3703static void rtl_hw_start_8168(struct net_device *dev)
3704{
2dd99530
FR		 3705 struct rtl8169_private *tp = netdev_priv(dev);
3706 void __iomem *ioaddr = tp->mmio_addr;
0e485150 3707 struct pci_dev *pdev = tp->pci_dev;
2dd99530
FR		 3708
3709 RTL_W8(Cfg9346, Cfg9346_Unlock);
3710
3711 RTL_W8(EarlyTxThres, EarlyTxThld);
3712
6f0333b8 3713 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2dd99530 3714
0e485150 3715 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 3716
3717 RTL_W16(CPlusCmd, tp->cp_cmd);
3718
0e485150 3719 RTL_W16(IntrMitigate, 0x5151);
2dd99530 3720
0e485150
FR		 3721 /* Work around for RxFIFO overflow. */
3722 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
3723 tp->intr_event |= RxFIFOOver | PCSTimeout;
3724 tp->intr_event &= ~RxOverflow;
3725 }
3726
3727 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 3728
b8363901
FR		 3729 rtl_set_rx_mode(dev);
3730
3731 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3732 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 3733
3734 RTL_R8(IntrMask);
3735
219a1e9d
FR		 3736 switch (tp->mac_version) {
3737 case RTL_GIGA_MAC_VER_11:
3738 rtl_hw_start_8168bb(ioaddr, pdev);
3739 break;
3740
3741 case RTL_GIGA_MAC_VER_12:
3742 case RTL_GIGA_MAC_VER_17:
3743 rtl_hw_start_8168bef(ioaddr, pdev);
3744 break;
3745
3746 case RTL_GIGA_MAC_VER_18:
ef3386f0 3747 rtl_hw_start_8168cp_1(ioaddr, pdev);
219a1e9d
FR		 3748 break;
3749
3750 case RTL_GIGA_MAC_VER_19:
3751 rtl_hw_start_8168c_1(ioaddr, pdev);
3752 break;
3753
3754 case RTL_GIGA_MAC_VER_20:
3755 rtl_hw_start_8168c_2(ioaddr, pdev);
3756 break;
3757
197ff761
FR		 3758 case RTL_GIGA_MAC_VER_21:
3759 rtl_hw_start_8168c_3(ioaddr, pdev);
3760 break;
3761
6fb07058
FR		 3762 case RTL_GIGA_MAC_VER_22:
3763 rtl_hw_start_8168c_4(ioaddr, pdev);
3764 break;
3765
ef3386f0
FR		 3766 case RTL_GIGA_MAC_VER_23:
3767 rtl_hw_start_8168cp_2(ioaddr, pdev);
3768 break;
3769
7f3e3d3a
FR		 3770 case RTL_GIGA_MAC_VER_24:
3771 rtl_hw_start_8168cp_3(ioaddr, pdev);
3772 break;
3773
5b538df9 3774 case RTL_GIGA_MAC_VER_25:
daf9df6d 3775 case RTL_GIGA_MAC_VER_26:
3776 case RTL_GIGA_MAC_VER_27:
5b538df9
FR		 3777 rtl_hw_start_8168d(ioaddr, pdev);
3778 break;
3779
219a1e9d
FR		 3780 default:
3781 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
3782 dev->name, tp->mac_version);
3783 break;
3784 }
2dd99530 3785
0e485150
FR		 3786 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3787
b8363901
FR		 3788 RTL_W8(Cfg9346, Cfg9346_Lock);
3789
2dd99530 3790 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 3791
0e485150 3792 RTL_W16(IntrMask, tp->intr_event);
07ce4064 3793}
1da177e4 3794
2857ffb7
FR		 3795#define R810X_CPCMD_QUIRK_MASK (\
3796 EnableBist | \
3797 Mac_dbgo_oe | \
3798 Force_half_dup | \
5edcc537 3799 Force_rxflow_en | \
2857ffb7
FR		 3800 Force_txflow_en | \
3801 Cxpl_dbg_sel | \
3802 ASF | \
3803 PktCntrDisable | \
3804 PCIDAC | \
3805 PCIMulRW)
3806
3807static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3808{
350f7596 3809 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 3810 { 0x01, 0, 0x6e65 },
3811 { 0x02, 0, 0x091f },
3812 { 0x03, 0, 0xc2f9 },
3813 { 0x06, 0, 0xafb5 },
3814 { 0x07, 0, 0x0e00 },
3815 { 0x19, 0, 0xec80 },
3816 { 0x01, 0, 0x2e65 },
3817 { 0x01, 0, 0x6e65 }
3818 };
3819 u8 cfg1;
3820
3821 rtl_csi_access_enable(ioaddr);
3822
3823 RTL_W8(DBG_REG, FIX_NAK_1);
3824
3825 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3826
3827 RTL_W8(Config1,
3828 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3829 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3830
3831 cfg1 = RTL_R8(Config1);
3832 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3833 RTL_W8(Config1, cfg1 & ~LEDS0);
3834
3835 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3836
3837 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
3838}
3839
3840static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
3841{
3842 rtl_csi_access_enable(ioaddr);
3843
3844 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3845
3846 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
3847 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3848
3849 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3850}
3851
3852static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
3853{
3854 rtl_hw_start_8102e_2(ioaddr, pdev);
3855
3856 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
3857}
3858
07ce4064
FR		 3859static void rtl_hw_start_8101(struct net_device *dev)
3860{
cdf1a608
FR		 3861 struct rtl8169_private *tp = netdev_priv(dev);
3862 void __iomem *ioaddr = tp->mmio_addr;
3863 struct pci_dev *pdev = tp->pci_dev;
3864
e3cf0cc0
FR		 3865 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
3866 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
9c14ceaf
FR		 3867 int cap = tp->pcie_cap;
3868
3869 if (cap) {
3870 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
3871 PCI_EXP_DEVCTL_NOSNOOP_EN);
3872 }
cdf1a608
FR		 3873 }
3874
2857ffb7
FR		 3875 switch (tp->mac_version) {
3876 case RTL_GIGA_MAC_VER_07:
3877 rtl_hw_start_8102e_1(ioaddr, pdev);
3878 break;
3879
3880 case RTL_GIGA_MAC_VER_08:
3881 rtl_hw_start_8102e_3(ioaddr, pdev);
3882 break;
3883
3884 case RTL_GIGA_MAC_VER_09:
3885 rtl_hw_start_8102e_2(ioaddr, pdev);
3886 break;
cdf1a608
FR		 3887 }
3888
3889 RTL_W8(Cfg9346, Cfg9346_Unlock);
3890
3891 RTL_W8(EarlyTxThres, EarlyTxThld);
3892
6f0333b8 3893 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
cdf1a608
FR		 3894
3895 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3896
3897 RTL_W16(CPlusCmd, tp->cp_cmd);
3898
3899 RTL_W16(IntrMitigate, 0x0000);
3900
3901 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3902
3903 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3904 rtl_set_rx_tx_config_registers(tp);
3905
3906 RTL_W8(Cfg9346, Cfg9346_Lock);
3907
3908 RTL_R8(IntrMask);
3909
cdf1a608
FR		 3910 rtl_set_rx_mode(dev);
3911
0e485150
FR		 3912 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3913
cdf1a608 3914 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 3915
0e485150 3916 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 3917}
3918
3919static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3920{
1da177e4
LT		 3921 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
3922 return -EINVAL;
3923
3924 dev->mtu = new_mtu;
323bb685 3925 return 0;
1da177e4
LT		 3926}
3927
3928static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
3929{
95e0918d 3930 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 3931 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
3932}
3933
6f0333b8
ED		 3934static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
3935 void **data_buff, struct RxDesc *desc)
1da177e4 3936{
48addcc9 3937 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
231aee63 3938 DMA_FROM_DEVICE);
48addcc9 3939
6f0333b8
ED		 3940 kfree(*data_buff);
3941 *data_buff = NULL;
1da177e4
LT		 3942 rtl8169_make_unusable_by_asic(desc);
3943}
3944
3945static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
3946{
3947 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3948
3949 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
3950}
3951
3952static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
3953 u32 rx_buf_sz)
3954{
3955 desc->addr = cpu_to_le64(mapping);
3956 wmb();
3957 rtl8169_mark_to_asic(desc, rx_buf_sz);
3958}
3959
6f0333b8
ED		 3960static inline void *rtl8169_align(void *data)
3961{
3962 return (void *)ALIGN((long)data, 16);
3963}
3964
0ecbe1ca
SG		 3965static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
3966 struct RxDesc *desc)
1da177e4 3967{
6f0333b8 3968 void *data;
1da177e4 3969 dma_addr_t mapping;
48addcc9 3970 struct device *d = &tp->pci_dev->dev;
0ecbe1ca 3971 struct net_device *dev = tp->dev;
6f0333b8 3972 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
1da177e4 3973
6f0333b8
ED		 3974 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
3975 if (!data)
3976 return NULL;
e9f63f30 3977
6f0333b8
ED		 3978 if (rtl8169_align(data) != data) {
3979 kfree(data);
3980 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
3981 if (!data)
3982 return NULL;
3983 }
3eafe507 3984
48addcc9 3985 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
231aee63 3986 DMA_FROM_DEVICE);
d827d86b
SG		 3987 if (unlikely(dma_mapping_error(d, mapping))) {
3988 if (net_ratelimit())
3989 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 3990 goto err_out;
d827d86b 3991 }
1da177e4
LT		 3992
3993 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6f0333b8 3994 return data;
3eafe507
SG		 3995
3996err_out:
3997 kfree(data);
3998 return NULL;
1da177e4
LT		 3999}
4000
4001static void rtl8169_rx_clear(struct rtl8169_private *tp)
4002{
07d3f51f 4003 unsigned int i;
1da177e4
LT		 4004
4005 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 4006 if (tp->Rx_databuff[i]) {
4007 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 4008 tp->RxDescArray + i);
4009 }
4010 }
4011}
4012
0ecbe1ca 4013static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 4014{
0ecbe1ca
SG		 4015 desc->opts1 |= cpu_to_le32(RingEnd);
4016}
5b0384f4 4017
0ecbe1ca
SG		 4018static int rtl8169_rx_fill(struct rtl8169_private *tp)
4019{
4020 unsigned int i;
1da177e4 4021
0ecbe1ca
SG		 4022 for (i = 0; i < NUM_RX_DESC; i++) {
4023 void *data;
4ae47c2d 4024
6f0333b8 4025 if (tp->Rx_databuff[i])
1da177e4 4026 continue;
bcf0bf90 4027
0ecbe1ca 4028 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 4029 if (!data) {
4030 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 4031 goto err_out;
6f0333b8
ED		 4032 }
4033 tp->Rx_databuff[i] = data;
1da177e4 4034 }
1da177e4 4035
0ecbe1ca
SG		 4036 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4037 return 0;
4038
4039err_out:
4040 rtl8169_rx_clear(tp);
4041 return -ENOMEM;
1da177e4
LT		 4042}
4043
4044static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4045{
4046 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4047}
4048
4049static int rtl8169_init_ring(struct net_device *dev)
4050{
4051 struct rtl8169_private *tp = netdev_priv(dev);
4052
4053 rtl8169_init_ring_indexes(tp);
4054
4055 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6f0333b8 4056 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
1da177e4 4057
0ecbe1ca 4058 return rtl8169_rx_fill(tp);
1da177e4
LT		 4059}
4060
48addcc9 4061static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 4062 struct TxDesc *desc)
4063{
4064 unsigned int len = tx_skb->len;
4065
48addcc9
SG		 4066 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4067
1da177e4
LT		 4068 desc->opts1 = 0x00;
4069 desc->opts2 = 0x00;
4070 desc->addr = 0x00;
4071 tx_skb->len = 0;
4072}
4073
3eafe507
SG		 4074static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4075 unsigned int n)
1da177e4
LT		 4076{
4077 unsigned int i;
4078
3eafe507
SG		 4079 for (i = 0; i < n; i++) {
4080 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 4081 struct ring_info *tx_skb = tp->tx_skb + entry;
4082 unsigned int len = tx_skb->len;
4083
4084 if (len) {
4085 struct sk_buff *skb = tx_skb->skb;
4086
48addcc9 4087 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
1da177e4
LT		 4088 tp->TxDescArray + entry);
4089 if (skb) {
cac4b22f 4090 tp->dev->stats.tx_dropped++;
1da177e4
LT		 4091 dev_kfree_skb(skb);
4092 tx_skb->skb = NULL;
4093 }
1da177e4
LT		 4094 }
4095 }
3eafe507
SG		 4096}
4097
4098static void rtl8169_tx_clear(struct rtl8169_private *tp)
4099{
4100 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 4101 tp->cur_tx = tp->dirty_tx = 0;
4102}
4103
c4028958 4104static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 4105{
4106 struct rtl8169_private *tp = netdev_priv(dev);
4107
c4028958 4108 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 4109 schedule_delayed_work(&tp->task, 4);
4110}
4111
4112static void rtl8169_wait_for_quiescence(struct net_device *dev)
4113{
4114 struct rtl8169_private *tp = netdev_priv(dev);
4115 void __iomem *ioaddr = tp->mmio_addr;
4116
4117 synchronize_irq(dev->irq);
4118
4119 /* Wait for any pending NAPI task to complete */
bea3348e 4120 napi_disable(&tp->napi);
1da177e4
LT		 4121
4122 rtl8169_irq_mask_and_ack(ioaddr);
4123
d1d08d12
DM		 4124 tp->intr_mask = 0xffff;
4125 RTL_W16(IntrMask, tp->intr_event);
bea3348e 4126 napi_enable(&tp->napi);
1da177e4
LT		 4127}
4128
c4028958 4129static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 4130{
c4028958
DH		 4131 struct rtl8169_private *tp =
4132 container_of(work, struct rtl8169_private, task.work);
4133 struct net_device *dev = tp->dev;
1da177e4
LT		 4134 int ret;
4135
eb2a021c
FR		 4136 rtnl_lock();
4137
4138 if (!netif_running(dev))
4139 goto out_unlock;
4140
4141 rtl8169_wait_for_quiescence(dev);
4142 rtl8169_close(dev);
1da177e4
LT		 4143
4144 ret = rtl8169_open(dev);
4145 if (unlikely(ret < 0)) {
bf82c189
JP		 4146 if (net_ratelimit())
4147 netif_err(tp, drv, dev,
4148 "reinit failure (status = %d). Rescheduling\n",
4149 ret);
1da177e4
LT		 4150 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4151 }
eb2a021c
FR		 4152
4153out_unlock:
4154 rtnl_unlock();
1da177e4
LT		 4155}
4156
c4028958 4157static void rtl8169_reset_task(struct work_struct *work)
1da177e4 4158{
c4028958
DH		 4159 struct rtl8169_private *tp =
4160 container_of(work, struct rtl8169_private, task.work);
4161 struct net_device *dev = tp->dev;
1da177e4 4162
eb2a021c
FR		 4163 rtnl_lock();
4164
1da177e4 4165 if (!netif_running(dev))
eb2a021c 4166 goto out_unlock;
1da177e4
LT		 4167
4168 rtl8169_wait_for_quiescence(dev);
4169
bea3348e 4170 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
1da177e4
LT		 4171 rtl8169_tx_clear(tp);
4172
4173 if (tp->dirty_rx == tp->cur_rx) {
4174 rtl8169_init_ring_indexes(tp);
07ce4064 4175 rtl_hw_start(dev);
1da177e4 4176 netif_wake_queue(dev);
cebf8cc7 4177 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4 4178 } else {
bf82c189
JP		 4179 if (net_ratelimit())
4180 netif_emerg(tp, intr, dev, "Rx buffers shortage\n");
1da177e4
LT		 4181 rtl8169_schedule_work(dev, rtl8169_reset_task);
4182 }
eb2a021c
FR		 4183
4184out_unlock:
4185 rtnl_unlock();
1da177e4
LT		 4186}
4187
4188static void rtl8169_tx_timeout(struct net_device *dev)
4189{
4190 struct rtl8169_private *tp = netdev_priv(dev);
4191
4192 rtl8169_hw_reset(tp->mmio_addr);
4193
4194 /* Let's wait a bit while any (async) irq lands on */
4195 rtl8169_schedule_work(dev, rtl8169_reset_task);
4196}
4197
4198static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4199 u32 opts1)
4200{
4201 struct skb_shared_info *info = skb_shinfo(skb);
4202 unsigned int cur_frag, entry;
a6343afb 4203 struct TxDesc * uninitialized_var(txd);
48addcc9 4204 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 4205
4206 entry = tp->cur_tx;
4207 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4208 skb_frag_t *frag = info->frags + cur_frag;
4209 dma_addr_t mapping;
4210 u32 status, len;
4211 void *addr;
4212
4213 entry = (entry + 1) % NUM_TX_DESC;
4214
4215 txd = tp->TxDescArray + entry;
4216 len = frag->size;
4217 addr = ((void *) page_address(frag->page)) + frag->page_offset;
48addcc9 4218 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 4219 if (unlikely(dma_mapping_error(d, mapping))) {
4220 if (net_ratelimit())
4221 netif_err(tp, drv, tp->dev,
4222 "Failed to map TX fragments DMA!\n");
3eafe507 4223 goto err_out;
d827d86b 4224 }
1da177e4
LT		 4225
4226 /* anti gcc 2.95.3 bugware (sic) */
4227 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4228
4229 txd->opts1 = cpu_to_le32(status);
4230 txd->addr = cpu_to_le64(mapping);
4231
4232 tp->tx_skb[entry].len = len;
4233 }
4234
4235 if (cur_frag) {
4236 tp->tx_skb[entry].skb = skb;
4237 txd->opts1 |= cpu_to_le32(LastFrag);
4238 }
4239
4240 return cur_frag;
3eafe507
SG		 4241
4242err_out:
4243 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4244 return -EIO;
1da177e4
LT		 4245}
4246
4247static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
4248{
4249 if (dev->features & NETIF_F_TSO) {
7967168c 4250 u32 mss = skb_shinfo(skb)->gso_size;
1da177e4
LT		 4251
4252 if (mss)
4253 return LargeSend | ((mss & MSSMask) << MSSShift);
4254 }
84fa7933 4255 if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 4256 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 4257
4258 if (ip->protocol == IPPROTO_TCP)
4259 return IPCS | TCPCS;
4260 else if (ip->protocol == IPPROTO_UDP)
4261 return IPCS | UDPCS;
4262 WARN_ON(1); /* we need a WARN() */
4263 }
4264 return 0;
4265}
4266
61357325
SH		 4267static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4268 struct net_device *dev)
1da177e4
LT		 4269{
4270 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 4271 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4
LT		 4272 struct TxDesc *txd = tp->TxDescArray + entry;
4273 void __iomem *ioaddr = tp->mmio_addr;
48addcc9 4274 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 4275 dma_addr_t mapping;
4276 u32 status, len;
4277 u32 opts1;
3eafe507 4278 int frags;
5b0384f4 4279
1da177e4 4280 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
bf82c189 4281 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 4282 goto err_stop_0;
1da177e4
LT		 4283 }
4284
4285 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 4286 goto err_stop_0;
4287
4288 len = skb_headlen(skb);
48addcc9 4289 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 4290 if (unlikely(dma_mapping_error(d, mapping))) {
4291 if (net_ratelimit())
4292 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 4293 goto err_dma_0;
d827d86b 4294 }
3eafe507
SG		 4295
4296 tp->tx_skb[entry].len = len;
4297 txd->addr = cpu_to_le64(mapping);
4298 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
1da177e4
LT		 4299
4300 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
4301
4302 frags = rtl8169_xmit_frags(tp, skb, opts1);
3eafe507
SG		 4303 if (frags < 0)
4304 goto err_dma_1;
4305 else if (frags)
1da177e4 4306 opts1 |= FirstFrag;
3eafe507 4307 else {
1da177e4
LT		 4308 opts1 |= FirstFrag | LastFrag;
4309 tp->tx_skb[entry].skb = skb;
4310 }
4311
1da177e4
LT		 4312 wmb();
4313
4314 /* anti gcc 2.95.3 bugware (sic) */
4315 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4316 txd->opts1 = cpu_to_le32(status);
4317
1da177e4
LT		 4318 tp->cur_tx += frags + 1;
4319
4c020a96 4320 wmb();
1da177e4 4321
275391a4 4322 RTL_W8(TxPoll, NPQ); /* set polling bit */
1da177e4
LT		 4323
4324 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4325 netif_stop_queue(dev);
4326 smp_rmb();
4327 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4328 netif_wake_queue(dev);
4329 }
4330
61357325 4331 return NETDEV_TX_OK;
1da177e4 4332
3eafe507 4333err_dma_1:
48addcc9 4334 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507
SG		 4335err_dma_0:
4336 dev_kfree_skb(skb);
4337 dev->stats.tx_dropped++;
4338 return NETDEV_TX_OK;
4339
4340err_stop_0:
1da177e4 4341 netif_stop_queue(dev);
cebf8cc7 4342 dev->stats.tx_dropped++;
61357325 4343 return NETDEV_TX_BUSY;
1da177e4
LT		 4344}
4345
4346static void rtl8169_pcierr_interrupt(struct net_device *dev)
4347{
4348 struct rtl8169_private *tp = netdev_priv(dev);
4349 struct pci_dev *pdev = tp->pci_dev;
4350 void __iomem *ioaddr = tp->mmio_addr;
4351 u16 pci_status, pci_cmd;
4352
4353 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4354 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4355
bf82c189
JP		 4356 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4357 pci_cmd, pci_status);
1da177e4
LT		 4358
4359 /*
4360 * The recovery sequence below admits a very elaborated explanation:
4361 * - it seems to work;
d03902b8
FR		 4362 * - I did not see what else could be done;
4363 * - it makes iop3xx happy.
1da177e4
LT		 4364 *
4365 * Feel free to adjust to your needs.
4366 */
a27993f3 4367 if (pdev->broken_parity_status)
d03902b8
FR		 4368 pci_cmd &= ~PCI_COMMAND_PARITY;
4369 else
4370 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4371
4372 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 4373
4374 pci_write_config_word(pdev, PCI_STATUS,
4375 pci_status & (PCI_STATUS_DETECTED_PARITY |
4376 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4377 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4378
4379 /* The infamous DAC f*ckup only happens at boot time */
4380 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
bf82c189 4381 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 4382 tp->cp_cmd &= ~PCIDAC;
4383 RTL_W16(CPlusCmd, tp->cp_cmd);
4384 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 4385 }
4386
4387 rtl8169_hw_reset(ioaddr);
d03902b8
FR		 4388
4389 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 4390}
4391
07d3f51f
FR		 4392static void rtl8169_tx_interrupt(struct net_device *dev,
4393 struct rtl8169_private *tp,
4394 void __iomem *ioaddr)
1da177e4
LT		 4395{
4396 unsigned int dirty_tx, tx_left;
4397
1da177e4
LT		 4398 dirty_tx = tp->dirty_tx;
4399 smp_rmb();
4400 tx_left = tp->cur_tx - dirty_tx;
4401
4402 while (tx_left > 0) {
4403 unsigned int entry = dirty_tx % NUM_TX_DESC;
4404 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 4405 u32 status;
4406
4407 rmb();
4408 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4409 if (status & DescOwn)
4410 break;
4411
48addcc9
SG		 4412 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4413 tp->TxDescArray + entry);
1da177e4 4414 if (status & LastFrag) {
cac4b22f
SG		 4415 dev->stats.tx_packets++;
4416 dev->stats.tx_bytes += tx_skb->skb->len;
87433bfc 4417 dev_kfree_skb(tx_skb->skb);
1da177e4
LT		 4418 tx_skb->skb = NULL;
4419 }
4420 dirty_tx++;
4421 tx_left--;
4422 }
4423
4424 if (tp->dirty_tx != dirty_tx) {
4425 tp->dirty_tx = dirty_tx;
4426 smp_wmb();
4427 if (netif_queue_stopped(dev) &&
4428 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4429 netif_wake_queue(dev);
4430 }
d78ae2dc
FR		 4431 /*
4432 * 8168 hack: TxPoll requests are lost when the Tx packets are
4433 * too close. Let's kick an extra TxPoll request when a burst
4434 * of start_xmit activity is detected (if it is not detected,
4435 * it is slow enough). -- FR
4436 */
4437 smp_rmb();
4438 if (tp->cur_tx != dirty_tx)
4439 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 4440 }
4441}
4442
126fa4b9
FR		 4443static inline int rtl8169_fragmented_frame(u32 status)
4444{
4445 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4446}
4447
adea1ac7 4448static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 4449{
1da177e4
LT		 4450 u32 status = opts1 & RxProtoMask;
4451
4452 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 4453 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 4454 skb->ip_summed = CHECKSUM_UNNECESSARY;
4455 else
bc8acf2c 4456 skb_checksum_none_assert(skb);
1da177e4
LT		 4457}
4458
6f0333b8
ED		 4459static struct sk_buff *rtl8169_try_rx_copy(void *data,
4460 struct rtl8169_private *tp,
4461 int pkt_size,
4462 dma_addr_t addr)
1da177e4 4463{
b449655f 4464 struct sk_buff *skb;
48addcc9 4465 struct device *d = &tp->pci_dev->dev;
b449655f 4466
6f0333b8 4467 data = rtl8169_align(data);
48addcc9 4468 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8
ED		 4469 prefetch(data);
4470 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
4471 if (skb)
4472 memcpy(skb->data, data, pkt_size);
48addcc9
SG		 4473 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4474
6f0333b8 4475 return skb;
1da177e4
LT		 4476}
4477
630b943c
ED		 4478/*
4479 * Warning : rtl8169_rx_interrupt() might be called :
4480 * 1) from NAPI (softirq) context
4481 * (polling = 1 : we should call netif_receive_skb())
4482 * 2) from process context (rtl8169_reset_task())
4483 * (polling = 0 : we must call netif_rx() instead)
4484 */
07d3f51f
FR		 4485static int rtl8169_rx_interrupt(struct net_device *dev,
4486 struct rtl8169_private *tp,
bea3348e 4487 void __iomem *ioaddr, u32 budget)
1da177e4
LT		 4488{
4489 unsigned int cur_rx, rx_left;
6f0333b8 4490 unsigned int count;
630b943c 4491 int polling = (budget != ~(u32)0) ? 1 : 0;
1da177e4 4492
1da177e4
LT		 4493 cur_rx = tp->cur_rx;
4494 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 4495 rx_left = min(rx_left, budget);
1da177e4 4496
4dcb7d33 4497 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 4498 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 4499 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 4500 u32 status;
4501
4502 rmb();
126fa4b9 4503 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 4504
4505 if (status & DescOwn)
4506 break;
4dcb7d33 4507 if (unlikely(status & RxRES)) {
bf82c189
JP		 4508 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4509 status);
cebf8cc7 4510 dev->stats.rx_errors++;
1da177e4 4511 if (status & (RxRWT | RxRUNT))
cebf8cc7 4512 dev->stats.rx_length_errors++;
1da177e4 4513 if (status & RxCRC)
cebf8cc7 4514 dev->stats.rx_crc_errors++;
9dccf611
FR		 4515 if (status & RxFOVF) {
4516 rtl8169_schedule_work(dev, rtl8169_reset_task);
cebf8cc7 4517 dev->stats.rx_fifo_errors++;
9dccf611 4518 }
6f0333b8 4519 rtl8169_mark_to_asic(desc, rx_buf_sz);
1da177e4 4520 } else {
6f0333b8 4521 struct sk_buff *skb;
b449655f 4522 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 4523 int pkt_size = (status & 0x00001FFF) - 4;
1da177e4 4524
126fa4b9
FR		 4525 /*
4526 * The driver does not support incoming fragmented
4527 * frames. They are seen as a symptom of over-mtu
4528 * sized frames.
4529 */
4530 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 4531 dev->stats.rx_dropped++;
4532 dev->stats.rx_length_errors++;
6f0333b8 4533 rtl8169_mark_to_asic(desc, rx_buf_sz);
4dcb7d33 4534 continue;
126fa4b9
FR		 4535 }
4536
6f0333b8
ED		 4537 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
4538 tp, pkt_size, addr);
4539 rtl8169_mark_to_asic(desc, rx_buf_sz);
4540 if (!skb) {
4541 dev->stats.rx_dropped++;
4542 continue;
1da177e4
LT		 4543 }
4544
adea1ac7 4545 rtl8169_rx_csum(skb, status);
1da177e4
LT		 4546 skb_put(skb, pkt_size);
4547 skb->protocol = eth_type_trans(skb, dev);
4548
630b943c
ED		 4549 if (rtl8169_rx_vlan_skb(tp, desc, skb, polling) < 0) {
4550 if (likely(polling))
2edae08e 4551 napi_gro_receive(&tp->napi, skb);
630b943c
ED		 4552 else
4553 netif_rx(skb);
4554 }
1da177e4 4555
cebf8cc7
FR		 4556 dev->stats.rx_bytes += pkt_size;
4557 dev->stats.rx_packets++;
1da177e4 4558 }
6dccd16b
FR		 4559
4560 /* Work around for AMD plateform. */
95e0918d 4561 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 4562 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4563 desc->opts2 = 0;
4564 cur_rx++;
4565 }
1da177e4
LT		 4566 }
4567
4568 count = cur_rx - tp->cur_rx;
4569 tp->cur_rx = cur_rx;
4570
6f0333b8 4571 tp->dirty_rx += count;
1da177e4
LT		 4572
4573 return count;
4574}
4575
07d3f51f 4576static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 4577{
07d3f51f 4578 struct net_device *dev = dev_instance;
1da177e4 4579 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 4580 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 4581 int handled = 0;
865c652d 4582 int status;
1da177e4 4583
f11a377b
DD		 4584 /* loop handling interrupts until we have no new ones or
4585 * we hit a invalid/hotplug case.
4586 */
865c652d 4587 status = RTL_R16(IntrStatus);
f11a377b
DD		 4588 while (status && status != 0xffff) {
4589 handled = 1;
1da177e4 4590
f11a377b
DD		 4591 /* Handle all of the error cases first. These will reset
4592 * the chip, so just exit the loop.
4593 */
4594 if (unlikely(!netif_running(dev))) {
4595 rtl8169_asic_down(ioaddr);
4596 break;
4597 }
1da177e4 4598
f11a377b 4599 /* Work around for rx fifo overflow */
53f57357 4600 if (unlikely(status & RxFIFOOver) &&
4601 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
f11a377b
DD		 4602 netif_stop_queue(dev);
4603 rtl8169_tx_timeout(dev);
4604 break;
4605 }
1da177e4 4606
f11a377b
DD		 4607 if (unlikely(status & SYSErr)) {
4608 rtl8169_pcierr_interrupt(dev);
4609 break;
4610 }
1da177e4 4611
f11a377b 4612 if (status & LinkChg)
e4fbce74 4613 __rtl8169_check_link_status(dev, tp, ioaddr, true);
0e485150 4614
f11a377b
DD		 4615 /* We need to see the lastest version of tp->intr_mask to
4616 * avoid ignoring an MSI interrupt and having to wait for
4617 * another event which may never come.
4618 */
4619 smp_rmb();
4620 if (status & tp->intr_mask & tp->napi_event) {
4621 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
4622 tp->intr_mask = ~tp->napi_event;
4623
4624 if (likely(napi_schedule_prep(&tp->napi)))
4625 __napi_schedule(&tp->napi);
bf82c189
JP		 4626 else
4627 netif_info(tp, intr, dev,
4628 "interrupt %04x in poll\n", status);
f11a377b 4629 }
1da177e4 4630
f11a377b
DD		 4631 /* We only get a new MSI interrupt when all active irq
4632 * sources on the chip have been acknowledged. So, ack
4633 * everything we've seen and check if new sources have become
4634 * active to avoid blocking all interrupts from the chip.
4635 */
4636 RTL_W16(IntrStatus,
4637 (status & RxFIFOOver) ? (status | RxOverflow) : status);
4638 status = RTL_R16(IntrStatus);
865c652d 4639 }
1da177e4 4640
1da177e4
LT		 4641 return IRQ_RETVAL(handled);
4642}
4643
bea3348e 4644static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 4645{
bea3348e
SH		 4646 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4647 struct net_device *dev = tp->dev;
1da177e4 4648 void __iomem *ioaddr = tp->mmio_addr;
bea3348e 4649 int work_done;
1da177e4 4650
bea3348e 4651 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
1da177e4
LT		 4652 rtl8169_tx_interrupt(dev, tp, ioaddr);
4653
bea3348e 4654 if (work_done < budget) {
288379f0 4655 napi_complete(napi);
f11a377b
DD		 4656
4657 /* We need for force the visibility of tp->intr_mask
4658 * for other CPUs, as we can loose an MSI interrupt
4659 * and potentially wait for a retransmit timeout if we don't.
4660 * The posted write to IntrMask is safe, as it will
4661 * eventually make it to the chip and we won't loose anything
4662 * until it does.
1da177e4 4663 */
f11a377b 4664 tp->intr_mask = 0xffff;
4c020a96 4665 wmb();
0e485150 4666 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 4667 }
4668
bea3348e 4669 return work_done;
1da177e4 4670}
1da177e4 4671
523a6094
FR		 4672static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
4673{
4674 struct rtl8169_private *tp = netdev_priv(dev);
4675
4676 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
4677 return;
4678
4679 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
4680 RTL_W32(RxMissed, 0);
4681}
4682
1da177e4
LT		 4683static void rtl8169_down(struct net_device *dev)
4684{
4685 struct rtl8169_private *tp = netdev_priv(dev);
4686 void __iomem *ioaddr = tp->mmio_addr;
1da177e4
LT		 4687
4688 rtl8169_delete_timer(dev);
4689
4690 netif_stop_queue(dev);
4691
93dd79e8 4692 napi_disable(&tp->napi);
93dd79e8 4693
1da177e4
LT		 4694 spin_lock_irq(&tp->lock);
4695
4696 rtl8169_asic_down(ioaddr);
323bb685
SG		 4697 /*
4698 * At this point device interrupts can not be enabled in any function,
4699 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
4700 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
4701 */
523a6094 4702 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 4703
4704 spin_unlock_irq(&tp->lock);
4705
4706 synchronize_irq(dev->irq);
4707
1da177e4 4708 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 4709 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4 4710
1da177e4
LT		 4711 rtl8169_tx_clear(tp);
4712
4713 rtl8169_rx_clear(tp);
4714}
4715
4716static int rtl8169_close(struct net_device *dev)
4717{
4718 struct rtl8169_private *tp = netdev_priv(dev);
4719 struct pci_dev *pdev = tp->pci_dev;
4720
e1759441
RW		 4721 pm_runtime_get_sync(&pdev->dev);
4722
355423d0
IV		 4723 /* update counters before going down */
4724 rtl8169_update_counters(dev);
4725
1da177e4
LT		 4726 rtl8169_down(dev);
4727
4728 free_irq(dev->irq, dev);
4729
82553bb6
SG		 4730 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4731 tp->RxPhyAddr);
4732 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4733 tp->TxPhyAddr);
1da177e4
LT		 4734 tp->TxDescArray = NULL;
4735 tp->RxDescArray = NULL;
4736
e1759441
RW		 4737 pm_runtime_put_sync(&pdev->dev);
4738
1da177e4
LT		 4739 return 0;
4740}
4741
07ce4064 4742static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 4743{
4744 struct rtl8169_private *tp = netdev_priv(dev);
4745 void __iomem *ioaddr = tp->mmio_addr;
4746 unsigned long flags;
4747 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 4748 int rx_mode;
1da177e4
LT		 4749 u32 tmp = 0;
4750
4751 if (dev->flags & IFF_PROMISC) {
4752 /* Unconditionally log net taps. */
bf82c189 4753 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
1da177e4
LT		 4754 rx_mode =
4755 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4756 AcceptAllPhys;
4757 mc_filter[1] = mc_filter[0] = 0xffffffff;
4cd24eaf 4758 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
8e95a202 4759 (dev->flags & IFF_ALLMULTI)) {
1da177e4
LT		 4760 /* Too many to filter perfectly -- accept all multicasts. */
4761 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4762 mc_filter[1] = mc_filter[0] = 0xffffffff;
4763 } else {
22bedad3 4764 struct netdev_hw_addr *ha;
07d3f51f 4765
1da177e4
LT		 4766 rx_mode = AcceptBroadcast | AcceptMyPhys;
4767 mc_filter[1] = mc_filter[0] = 0;
22bedad3
JP		 4768 netdev_for_each_mc_addr(ha, dev) {
4769 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1da177e4
LT		 4770 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4771 rx_mode |= AcceptMulticast;
4772 }
4773 }
4774
4775 spin_lock_irqsave(&tp->lock, flags);
4776
4777 tmp = rtl8169_rx_config | rx_mode |
4778 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
4779
f887cce8 4780 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
1087f4f4
FR		 4781 u32 data = mc_filter[0];
4782
4783 mc_filter[0] = swab32(mc_filter[1]);
4784 mc_filter[1] = swab32(data);
bcf0bf90
FR		 4785 }
4786
1da177e4 4787 RTL_W32(MAR0 + 4, mc_filter[1]);
78f1cd02 4788 RTL_W32(MAR0 + 0, mc_filter[0]);
1da177e4 4789
57a9f236
FR		 4790 RTL_W32(RxConfig, tmp);
4791
1da177e4
LT		 4792 spin_unlock_irqrestore(&tp->lock, flags);
4793}
4794
4795/**
4796 * rtl8169_get_stats - Get rtl8169 read/write statistics
4797 * @dev: The Ethernet Device to get statistics for
4798 *
4799 * Get TX/RX statistics for rtl8169
4800 */
4801static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
4802{
4803 struct rtl8169_private *tp = netdev_priv(dev);
4804 void __iomem *ioaddr = tp->mmio_addr;
4805 unsigned long flags;
4806
4807 if (netif_running(dev)) {
4808 spin_lock_irqsave(&tp->lock, flags);
523a6094 4809 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 4810 spin_unlock_irqrestore(&tp->lock, flags);
4811 }
5b0384f4 4812
cebf8cc7 4813 return &dev->stats;
1da177e4
LT		 4814}
4815
861ab440 4816static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 4817{
5d06a99f 4818 if (!netif_running(dev))
861ab440 4819 return;
5d06a99f
FR		 4820
4821 netif_device_detach(dev);
4822 netif_stop_queue(dev);
861ab440
RW		 4823}
4824
4825#ifdef CONFIG_PM
4826
4827static int rtl8169_suspend(struct device *device)
4828{
4829 struct pci_dev *pdev = to_pci_dev(device);
4830 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 4831
861ab440 4832 rtl8169_net_suspend(dev);
1371fa6d 4833
5d06a99f
FR		 4834 return 0;
4835}
4836
e1759441
RW		 4837static void __rtl8169_resume(struct net_device *dev)
4838{
4839 netif_device_attach(dev);
4840 rtl8169_schedule_work(dev, rtl8169_reset_task);
4841}
4842
861ab440 4843static int rtl8169_resume(struct device *device)
5d06a99f 4844{
861ab440 4845 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 4846 struct net_device *dev = pci_get_drvdata(pdev);
fccec10b
SG		 4847 struct rtl8169_private *tp = netdev_priv(dev);
4848
4849 rtl8169_init_phy(dev, tp);
5d06a99f 4850
e1759441
RW		 4851 if (netif_running(dev))
4852 __rtl8169_resume(dev);
5d06a99f 4853
e1759441
RW		 4854 return 0;
4855}
4856
4857static int rtl8169_runtime_suspend(struct device *device)
4858{
4859 struct pci_dev *pdev = to_pci_dev(device);
4860 struct net_device *dev = pci_get_drvdata(pdev);
4861 struct rtl8169_private *tp = netdev_priv(dev);
4862
4863 if (!tp->TxDescArray)
4864 return 0;
4865
4866 spin_lock_irq(&tp->lock);
4867 tp->saved_wolopts = __rtl8169_get_wol(tp);
4868 __rtl8169_set_wol(tp, WAKE_ANY);
4869 spin_unlock_irq(&tp->lock);
4870
4871 rtl8169_net_suspend(dev);
4872
4873 return 0;
4874}
4875
4876static int rtl8169_runtime_resume(struct device *device)
4877{
4878 struct pci_dev *pdev = to_pci_dev(device);
4879 struct net_device *dev = pci_get_drvdata(pdev);
4880 struct rtl8169_private *tp = netdev_priv(dev);
4881
4882 if (!tp->TxDescArray)
4883 return 0;
4884
4885 spin_lock_irq(&tp->lock);
4886 __rtl8169_set_wol(tp, tp->saved_wolopts);
4887 tp->saved_wolopts = 0;
4888 spin_unlock_irq(&tp->lock);
4889
fccec10b
SG		 4890 rtl8169_init_phy(dev, tp);
4891
e1759441 4892 __rtl8169_resume(dev);
5d06a99f 4893
5d06a99f
FR		 4894 return 0;
4895}
4896
e1759441
RW		 4897static int rtl8169_runtime_idle(struct device *device)
4898{
4899 struct pci_dev *pdev = to_pci_dev(device);
4900 struct net_device *dev = pci_get_drvdata(pdev);
4901 struct rtl8169_private *tp = netdev_priv(dev);
4902
e4fbce74 4903 return tp->TxDescArray ? -EBUSY : 0;
e1759441
RW		 4904}
4905
47145210 4906static const struct dev_pm_ops rtl8169_pm_ops = {
861ab440
RW		 4907 .suspend = rtl8169_suspend,
4908 .resume = rtl8169_resume,
4909 .freeze = rtl8169_suspend,
4910 .thaw = rtl8169_resume,
4911 .poweroff = rtl8169_suspend,
4912 .restore = rtl8169_resume,
e1759441
RW		 4913 .runtime_suspend = rtl8169_runtime_suspend,
4914 .runtime_resume = rtl8169_runtime_resume,
4915 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 4916};
4917
4918#define RTL8169_PM_OPS (&rtl8169_pm_ops)
4919
4920#else /* !CONFIG_PM */
4921
4922#define RTL8169_PM_OPS NULL
4923
4924#endif /* !CONFIG_PM */
4925
1765f95d
FR		 4926static void rtl_shutdown(struct pci_dev *pdev)
4927{
861ab440 4928 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 4929 struct rtl8169_private *tp = netdev_priv(dev);
4930 void __iomem *ioaddr = tp->mmio_addr;
861ab440
RW		 4931
4932 rtl8169_net_suspend(dev);
1765f95d 4933
cc098dc7
IV		 4934 /* restore original MAC address */
4935 rtl_rar_set(tp, dev->perm_addr);
4936
4bb3f522 4937 spin_lock_irq(&tp->lock);
4938
4939 rtl8169_asic_down(ioaddr);
4940
4941 spin_unlock_irq(&tp->lock);
4942
861ab440 4943 if (system_state == SYSTEM_POWER_OFF) {
ca52efd5 4944 /* WoL fails with some 8168 when the receiver is disabled. */
4945 if (tp->features & RTL_FEATURE_WOL) {
4946 pci_clear_master(pdev);
4947
4948 RTL_W8(ChipCmd, CmdRxEnb);
4949 /* PCI commit */
4950 RTL_R8(ChipCmd);
4951 }
4952
861ab440
RW		 4953 pci_wake_from_d3(pdev, true);
4954 pci_set_power_state(pdev, PCI_D3hot);
4955 }
4956}
5d06a99f 4957
1da177e4
LT		 4958static struct pci_driver rtl8169_pci_driver = {
4959 .name = MODULENAME,
4960 .id_table = rtl8169_pci_tbl,
4961 .probe = rtl8169_init_one,
4962 .remove = __devexit_p(rtl8169_remove_one),
1765f95d 4963 .shutdown = rtl_shutdown,
861ab440 4964 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 4965};
4966
07d3f51f 4967static int __init rtl8169_init_module(void)
1da177e4 4968{
29917620 4969 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 4970}
4971
07d3f51f 4972static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 4973{
4974 pci_unregister_driver(&rtl8169_pci_driver);
4975}
4976
4977module_init(rtl8169_init_module);
4978module_exit(rtl8169_cleanup_module);
Linux 6.x block layer and io_uring tree(s)