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r8169: small 8101 comment
[linux-2.6-block.git] / drivers / net / r8169.c
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1da177e4
LT		 1/*
2=========================================================================
3 r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver for Linux kernel 2.4.x.
4 --------------------------------------------------------------------
5
6 History:
7 Feb 4 2002 - created initially by ShuChen <shuchen@realtek.com.tw>.
8 May 20 2002 - Add link status force-mode and TBI mode support.
5b0384f4 9 2004 - Massive updates. See kernel SCM system for details.
1da177e4
LT		 10=========================================================================
11 1. [DEPRECATED: use ethtool instead] The media can be forced in 5 modes.
12 Command: 'insmod r8169 media = SET_MEDIA'
13 Ex: 'insmod r8169 media = 0x04' will force PHY to operate in 100Mpbs Half-duplex.
5b0384f4 14
1da177e4
LT		 15 SET_MEDIA can be:
16 _10_Half = 0x01
17 _10_Full = 0x02
18 _100_Half = 0x04
19 _100_Full = 0x08
20 _1000_Full = 0x10
5b0384f4 21
1da177e4
LT		 22 2. Support TBI mode.
23=========================================================================
24VERSION 1.1 <2002/10/4>
25
26 The bit4:0 of MII register 4 is called "selector field", and have to be
27 00001b to indicate support of IEEE std 802.3 during NWay process of
5b0384f4 28 exchanging Link Code Word (FLP).
1da177e4
LT		 29
30VERSION 1.2 <2002/11/30>
31
32 - Large style cleanup
33 - Use ether_crc in stock kernel (linux/crc32.h)
34 - Copy mc_filter setup code from 8139cp
35 (includes an optimization, and avoids set_bit use)
36
37VERSION 1.6LK <2004/04/14>
38
39 - Merge of Realtek's version 1.6
40 - Conversion to DMA API
41 - Suspend/resume
42 - Endianness
43 - Misc Rx/Tx bugs
44
45VERSION 2.2LK <2005/01/25>
46
47 - RX csum, TX csum/SG, TSO
48 - VLAN
49 - baby (< 7200) Jumbo frames support
50 - Merge of Realtek's version 2.2 (new phy)
51 */
52
53#include <linux/module.h>
54#include <linux/moduleparam.h>
55#include <linux/pci.h>
56#include <linux/netdevice.h>
57#include <linux/etherdevice.h>
58#include <linux/delay.h>
59#include <linux/ethtool.h>
60#include <linux/mii.h>
61#include <linux/if_vlan.h>
62#include <linux/crc32.h>
63#include <linux/in.h>
64#include <linux/ip.h>
65#include <linux/tcp.h>
66#include <linux/init.h>
67#include <linux/dma-mapping.h>
68
99f252b0 69#include <asm/system.h>
1da177e4
LT		 70#include <asm/io.h>
71#include <asm/irq.h>
72
f7ccf420
SH		 73#ifdef CONFIG_R8169_NAPI
74#define NAPI_SUFFIX "-NAPI"
75#else
76#define NAPI_SUFFIX ""
77#endif
78
79#define RTL8169_VERSION "2.2LK" NAPI_SUFFIX
1da177e4
LT		 80#define MODULENAME "r8169"
81#define PFX MODULENAME ": "
82
83#ifdef RTL8169_DEBUG
84#define assert(expr) \
5b0384f4
FR		 85 if (!(expr)) { \
86 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
87 #expr,__FILE__,__FUNCTION__,__LINE__); \
88 }
1da177e4
LT		 89#define dprintk(fmt, args...) do { printk(PFX fmt, ## args); } while (0)
90#else
91#define assert(expr) do {} while (0)
92#define dprintk(fmt, args...) do {} while (0)
93#endif /* RTL8169_DEBUG */
94
b57b7e5a 95#define R8169_MSG_DEFAULT \
f0e837d9 96 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 97
1da177e4
LT		 98#define TX_BUFFS_AVAIL(tp) \
99 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
100
101#ifdef CONFIG_R8169_NAPI
102#define rtl8169_rx_skb netif_receive_skb
0b50f81d 103#define rtl8169_rx_hwaccel_skb vlan_hwaccel_receive_skb
1da177e4
LT		 104#define rtl8169_rx_quota(count, quota) min(count, quota)
105#else
106#define rtl8169_rx_skb netif_rx
0b50f81d 107#define rtl8169_rx_hwaccel_skb vlan_hwaccel_rx
1da177e4
LT		 108#define rtl8169_rx_quota(count, quota) count
109#endif
110
111/* media options */
112#define MAX_UNITS 8
113static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
114static int num_media = 0;
115
116/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
f71e1309 117static const int max_interrupt_work = 20;
1da177e4
LT		 118
119/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
120 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 121static const int multicast_filter_limit = 32;
1da177e4
LT		 122
123/* MAC address length */
124#define MAC_ADDR_LEN 6
125
126#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
127#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
128#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
129#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
130#define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
131#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
132#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
133
134#define R8169_REGS_SIZE 256
135#define R8169_NAPI_WEIGHT 64
136#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
137#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
138#define RX_BUF_SIZE 1536 /* Rx Buffer size */
139#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
140#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
141
142#define RTL8169_TX_TIMEOUT (6*HZ)
143#define RTL8169_PHY_TIMEOUT (10*HZ)
144
145/* write/read MMIO register */
146#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
147#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
148#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
149#define RTL_R8(reg) readb (ioaddr + (reg))
150#define RTL_R16(reg) readw (ioaddr + (reg))
151#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
152
153enum mac_version {
ba6eb6ee
FR		 154 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
155 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
156 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
157 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
158 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
6dccd16b 159 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
2dd99530
FR		 160 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
161 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be 8168Bf
cdf1a608
FR		 162 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb 8101Ec
163 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101
164 RTL_GIGA_MAC_VER_15 = 0x0f // 8101
1da177e4
LT		 165};
166
167enum phy_version {
168 RTL_GIGA_PHY_VER_C = 0x03, /* PHY Reg 0x03 bit0-3 == 0x0000 */
169 RTL_GIGA_PHY_VER_D = 0x04, /* PHY Reg 0x03 bit0-3 == 0x0000 */
170 RTL_GIGA_PHY_VER_E = 0x05, /* PHY Reg 0x03 bit0-3 == 0x0000 */
171 RTL_GIGA_PHY_VER_F = 0x06, /* PHY Reg 0x03 bit0-3 == 0x0001 */
172 RTL_GIGA_PHY_VER_G = 0x07, /* PHY Reg 0x03 bit0-3 == 0x0002 */
173 RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */
174};
175
1da177e4
LT		 176#define _R(NAME,MAC,MASK) \
177 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
178
3c6bee1d 179static const struct {
1da177e4
LT		 180 const char *name;
181 u8 mac_version;
182 u32 RxConfigMask; /* Clears the bits supported by this chip */
183} rtl_chip_info[] = {
ba6eb6ee
FR		 184 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
185 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
186 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
187 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
188 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
6dccd16b 189 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
bcf0bf90
FR		 190 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
191 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
192 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
193 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
194 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880) // PCI-E 8139
1da177e4
LT		 195};
196#undef _R
197
bcf0bf90
FR		 198enum cfg_version {
199 RTL_CFG_0 = 0x00,
200 RTL_CFG_1,
201 RTL_CFG_2
202};
203
07ce4064
FR		 204static void rtl_hw_start_8169(struct net_device *);
205static void rtl_hw_start_8168(struct net_device *);
206static void rtl_hw_start_8101(struct net_device *);
207
1da177e4 208static struct pci_device_id rtl8169_pci_tbl[] = {
bcf0bf90 209 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 210 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 211 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 212 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 213 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
214 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
73f5e28b 215 { PCI_DEVICE(0x1259, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 216 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
217 { PCI_VENDOR_ID_LINKSYS, 0x1032,
218 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
1da177e4
LT		 219 {0,},
220};
221
222MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
223
224static int rx_copybreak = 200;
225static int use_dac;
b57b7e5a
SH		 226static struct {
227 u32 msg_enable;
228} debug = { -1 };
1da177e4
LT		 229
230enum RTL8169_registers {
231 MAC0 = 0, /* Ethernet hardware address. */
232 MAR0 = 8, /* Multicast filter. */
d4a3a0fc
SH		 233 CounterAddrLow = 0x10,
234 CounterAddrHigh = 0x14,
1da177e4
LT		 235 TxDescStartAddrLow = 0x20,
236 TxDescStartAddrHigh = 0x24,
237 TxHDescStartAddrLow = 0x28,
238 TxHDescStartAddrHigh = 0x2c,
239 FLASH = 0x30,
240 ERSR = 0x36,
241 ChipCmd = 0x37,
242 TxPoll = 0x38,
243 IntrMask = 0x3C,
244 IntrStatus = 0x3E,
245 TxConfig = 0x40,
246 RxConfig = 0x44,
247 RxMissed = 0x4C,
248 Cfg9346 = 0x50,
249 Config0 = 0x51,
250 Config1 = 0x52,
251 Config2 = 0x53,
252 Config3 = 0x54,
253 Config4 = 0x55,
254 Config5 = 0x56,
255 MultiIntr = 0x5C,
256 PHYAR = 0x60,
257 TBICSR = 0x64,
258 TBI_ANAR = 0x68,
259 TBI_LPAR = 0x6A,
260 PHYstatus = 0x6C,
261 RxMaxSize = 0xDA,
262 CPlusCmd = 0xE0,
263 IntrMitigate = 0xE2,
264 RxDescAddrLow = 0xE4,
265 RxDescAddrHigh = 0xE8,
266 EarlyTxThres = 0xEC,
267 FuncEvent = 0xF0,
268 FuncEventMask = 0xF4,
269 FuncPresetState = 0xF8,
270 FuncForceEvent = 0xFC,
271};
272
273enum RTL8169_register_content {
274 /* InterruptStatusBits */
275 SYSErr = 0x8000,
276 PCSTimeout = 0x4000,
277 SWInt = 0x0100,
278 TxDescUnavail = 0x80,
279 RxFIFOOver = 0x40,
280 LinkChg = 0x20,
281 RxOverflow = 0x10,
282 TxErr = 0x08,
283 TxOK = 0x04,
284 RxErr = 0x02,
285 RxOK = 0x01,
286
287 /* RxStatusDesc */
9dccf611
FR		 288 RxFOVF = (1 << 23),
289 RxRWT = (1 << 22),
290 RxRES = (1 << 21),
291 RxRUNT = (1 << 20),
292 RxCRC = (1 << 19),
1da177e4
LT		 293
294 /* ChipCmdBits */
295 CmdReset = 0x10,
296 CmdRxEnb = 0x08,
297 CmdTxEnb = 0x04,
298 RxBufEmpty = 0x01,
299
300 /* Cfg9346Bits */
301 Cfg9346_Lock = 0x00,
302 Cfg9346_Unlock = 0xC0,
303
304 /* rx_mode_bits */
305 AcceptErr = 0x20,
306 AcceptRunt = 0x10,
307 AcceptBroadcast = 0x08,
308 AcceptMulticast = 0x04,
309 AcceptMyPhys = 0x02,
310 AcceptAllPhys = 0x01,
311
312 /* RxConfigBits */
313 RxCfgFIFOShift = 13,
314 RxCfgDMAShift = 8,
315
316 /* TxConfigBits */
317 TxInterFrameGapShift = 24,
318 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
319
5d06a99f
FR		 320 /* Config1 register p.24 */
321 PMEnable = (1 << 0), /* Power Management Enable */
322
6dccd16b
FR		 323 /* Config2 register p. 25 */
324 PCI_Clock_66MHz = 0x01,
325 PCI_Clock_33MHz = 0x00,
326
61a4dcc2
FR		 327 /* Config3 register p.25 */
328 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
329 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
330
5d06a99f 331 /* Config5 register p.27 */
61a4dcc2
FR		 332 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
333 MWF = (1 << 5), /* Accept Multicast wakeup frame */
334 UWF = (1 << 4), /* Accept Unicast wakeup frame */
335 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 336 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
337
1da177e4
LT		 338 /* TBICSR p.28 */
339 TBIReset = 0x80000000,
340 TBILoopback = 0x40000000,
341 TBINwEnable = 0x20000000,
342 TBINwRestart = 0x10000000,
343 TBILinkOk = 0x02000000,
344 TBINwComplete = 0x01000000,
345
346 /* CPlusCmd p.31 */
0e485150 347 PktCntrDisable = (1 << 7), // 8168
1da177e4
LT		 348 RxVlan = (1 << 6),
349 RxChkSum = (1 << 5),
350 PCIDAC = (1 << 4),
351 PCIMulRW = (1 << 3),
0e485150
FR		 352 INTT_0 = 0x0000, // 8168
353 INTT_1 = 0x0001, // 8168
354 INTT_2 = 0x0002, // 8168
355 INTT_3 = 0x0003, // 8168
1da177e4
LT		 356
357 /* rtl8169_PHYstatus */
358 TBI_Enable = 0x80,
359 TxFlowCtrl = 0x40,
360 RxFlowCtrl = 0x20,
361 _1000bpsF = 0x10,
362 _100bps = 0x08,
363 _10bps = 0x04,
364 LinkStatus = 0x02,
365 FullDup = 0x01,
366
1da177e4
LT		 367 /* _MediaType */
368 _10_Half = 0x01,
369 _10_Full = 0x02,
370 _100_Half = 0x04,
371 _100_Full = 0x08,
372 _1000_Full = 0x10,
373
374 /* _TBICSRBit */
375 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 376
377 /* DumpCounterCommand */
378 CounterDump = 0x8,
1da177e4
LT		 379};
380
381enum _DescStatusBit {
382 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
383 RingEnd = (1 << 30), /* End of descriptor ring */
384 FirstFrag = (1 << 29), /* First segment of a packet */
385 LastFrag = (1 << 28), /* Final segment of a packet */
386
387 /* Tx private */
388 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
389 MSSShift = 16, /* MSS value position */
390 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
391 IPCS = (1 << 18), /* Calculate IP checksum */
392 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
393 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
394 TxVlanTag = (1 << 17), /* Add VLAN tag */
395
396 /* Rx private */
397 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
398 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
399
400#define RxProtoUDP (PID1)
401#define RxProtoTCP (PID0)
402#define RxProtoIP (PID1 | PID0)
403#define RxProtoMask RxProtoIP
404
405 IPFail = (1 << 16), /* IP checksum failed */
406 UDPFail = (1 << 15), /* UDP/IP checksum failed */
407 TCPFail = (1 << 14), /* TCP/IP checksum failed */
408 RxVlanTag = (1 << 16), /* VLAN tag available */
409};
410
411#define RsvdMask 0x3fffc000
412
413struct TxDesc {
414 u32 opts1;
415 u32 opts2;
416 u64 addr;
417};
418
419struct RxDesc {
420 u32 opts1;
421 u32 opts2;
422 u64 addr;
423};
424
425struct ring_info {
426 struct sk_buff *skb;
427 u32 len;
428 u8 __pad[sizeof(void *) - sizeof(u32)];
429};
430
431struct rtl8169_private {
432 void __iomem *mmio_addr; /* memory map physical address */
433 struct pci_dev *pci_dev; /* Index of PCI device */
c4028958 434 struct net_device *dev;
1da177e4
LT		 435 struct net_device_stats stats; /* statistics of net device */
436 spinlock_t lock; /* spin lock flag */
b57b7e5a 437 u32 msg_enable;
1da177e4
LT		 438 int chipset;
439 int mac_version;
440 int phy_version;
441 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
442 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
443 u32 dirty_rx;
444 u32 dirty_tx;
445 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
446 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
447 dma_addr_t TxPhyAddr;
448 dma_addr_t RxPhyAddr;
449 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
450 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
bcf0bf90 451 unsigned align;
1da177e4
LT		 452 unsigned rx_buf_sz;
453 struct timer_list timer;
454 u16 cp_cmd;
0e485150
FR		 455 u16 intr_event;
456 u16 napi_event;
1da177e4
LT		 457 u16 intr_mask;
458 int phy_auto_nego_reg;
459 int phy_1000_ctrl_reg;
460#ifdef CONFIG_R8169_VLAN
461 struct vlan_group *vlgrp;
462#endif
463 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
464 void (*get_settings)(struct net_device *, struct ethtool_cmd *);
465 void (*phy_reset_enable)(void __iomem *);
07ce4064 466 void (*hw_start)(struct net_device *);
1da177e4
LT		 467 unsigned int (*phy_reset_pending)(void __iomem *);
468 unsigned int (*link_ok)(void __iomem *);
c4028958 469 struct delayed_work task;
61a4dcc2 470 unsigned wol_enabled : 1;
1da177e4
LT		 471};
472
979b6c13 473MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4
LT		 474MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
475module_param_array(media, int, &num_media, 0);
df0a1bf6 476MODULE_PARM_DESC(media, "force phy operation. Deprecated by ethtool (8).");
1da177e4 477module_param(rx_copybreak, int, 0);
1b7efd58 478MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
1da177e4
LT		 479module_param(use_dac, int, 0);
480MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 481module_param_named(debug, debug.msg_enable, int, 0);
482MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 483MODULE_LICENSE("GPL");
484MODULE_VERSION(RTL8169_VERSION);
485
486static int rtl8169_open(struct net_device *dev);
487static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
7d12e780 488static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 489static int rtl8169_init_ring(struct net_device *dev);
07ce4064 490static void rtl_hw_start(struct net_device *dev);
1da177e4 491static int rtl8169_close(struct net_device *dev);
07ce4064 492static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 493static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 494static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4
LT		 495static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
496 void __iomem *);
4dcb7d33 497static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 498static void rtl8169_down(struct net_device *dev);
99f252b0 499static void rtl8169_rx_clear(struct rtl8169_private *tp);
1da177e4
LT		 500
501#ifdef CONFIG_R8169_NAPI
502static int rtl8169_poll(struct net_device *dev, int *budget);
503#endif
504
1da177e4 505static const unsigned int rtl8169_rx_config =
5b0384f4 506 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4
LT		 507
508static void mdio_write(void __iomem *ioaddr, int RegAddr, int value)
509{
510 int i;
511
512 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
1da177e4 513
2371408c 514 for (i = 20; i > 0; i--) {
1da177e4 515 /* Check if the RTL8169 has completed writing to the specified MII register */
5b0384f4 516 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 517 break;
2371408c 518 udelay(25);
1da177e4
LT		 519 }
520}
521
522static int mdio_read(void __iomem *ioaddr, int RegAddr)
523{
524 int i, value = -1;
525
526 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
1da177e4 527
2371408c 528 for (i = 20; i > 0; i--) {
1da177e4
LT		 529 /* Check if the RTL8169 has completed retrieving data from the specified MII register */
530 if (RTL_R32(PHYAR) & 0x80000000) {
531 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
532 break;
533 }
2371408c 534 udelay(25);
1da177e4
LT		 535 }
536 return value;
537}
538
539static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
540{
541 RTL_W16(IntrMask, 0x0000);
542
543 RTL_W16(IntrStatus, 0xffff);
544}
545
546static void rtl8169_asic_down(void __iomem *ioaddr)
547{
548 RTL_W8(ChipCmd, 0x00);
549 rtl8169_irq_mask_and_ack(ioaddr);
550 RTL_R16(CPlusCmd);
551}
552
553static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
554{
555 return RTL_R32(TBICSR) & TBIReset;
556}
557
558static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
559{
64e4bfb4 560 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 561}
562
563static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
564{
565 return RTL_R32(TBICSR) & TBILinkOk;
566}
567
568static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
569{
570 return RTL_R8(PHYstatus) & LinkStatus;
571}
572
573static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
574{
575 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
576}
577
578static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
579{
580 unsigned int val;
581
9e0db8ef
FR		 582 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
583 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
1da177e4
LT		 584}
585
586static void rtl8169_check_link_status(struct net_device *dev,
587 struct rtl8169_private *tp, void __iomem *ioaddr)
588{
589 unsigned long flags;
590
591 spin_lock_irqsave(&tp->lock, flags);
592 if (tp->link_ok(ioaddr)) {
593 netif_carrier_on(dev);
b57b7e5a
SH		 594 if (netif_msg_ifup(tp))
595 printk(KERN_INFO PFX "%s: link up\n", dev->name);
596 } else {
597 if (netif_msg_ifdown(tp))
598 printk(KERN_INFO PFX "%s: link down\n", dev->name);
1da177e4 599 netif_carrier_off(dev);
b57b7e5a 600 }
1da177e4
LT		 601 spin_unlock_irqrestore(&tp->lock, flags);
602}
603
604static void rtl8169_link_option(int idx, u8 *autoneg, u16 *speed, u8 *duplex)
605{
606 struct {
607 u16 speed;
608 u8 duplex;
609 u8 autoneg;
610 u8 media;
611 } link_settings[] = {
612 { SPEED_10, DUPLEX_HALF, AUTONEG_DISABLE, _10_Half },
613 { SPEED_10, DUPLEX_FULL, AUTONEG_DISABLE, _10_Full },
614 { SPEED_100, DUPLEX_HALF, AUTONEG_DISABLE, _100_Half },
615 { SPEED_100, DUPLEX_FULL, AUTONEG_DISABLE, _100_Full },
616 { SPEED_1000, DUPLEX_FULL, AUTONEG_DISABLE, _1000_Full },
617 /* Make TBI happy */
618 { SPEED_1000, DUPLEX_FULL, AUTONEG_ENABLE, 0xff }
619 }, *p;
620 unsigned char option;
5b0384f4 621
1da177e4
LT		 622 option = ((idx < MAX_UNITS) && (idx >= 0)) ? media[idx] : 0xff;
623
b57b7e5a 624 if ((option != 0xff) && !idx && netif_msg_drv(&debug))
1da177e4
LT		 625 printk(KERN_WARNING PFX "media option is deprecated.\n");
626
627 for (p = link_settings; p->media != 0xff; p++) {
628 if (p->media == option)
629 break;
630 }
631 *autoneg = p->autoneg;
632 *speed = p->speed;
633 *duplex = p->duplex;
634}
635
61a4dcc2
FR		 636static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
637{
638 struct rtl8169_private *tp = netdev_priv(dev);
639 void __iomem *ioaddr = tp->mmio_addr;
640 u8 options;
641
642 wol->wolopts = 0;
643
644#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
645 wol->supported = WAKE_ANY;
646
647 spin_lock_irq(&tp->lock);
648
649 options = RTL_R8(Config1);
650 if (!(options & PMEnable))
651 goto out_unlock;
652
653 options = RTL_R8(Config3);
654 if (options & LinkUp)
655 wol->wolopts |= WAKE_PHY;
656 if (options & MagicPacket)
657 wol->wolopts |= WAKE_MAGIC;
658
659 options = RTL_R8(Config5);
660 if (options & UWF)
661 wol->wolopts |= WAKE_UCAST;
662 if (options & BWF)
5b0384f4 663 wol->wolopts |= WAKE_BCAST;
61a4dcc2 664 if (options & MWF)
5b0384f4 665 wol->wolopts |= WAKE_MCAST;
61a4dcc2
FR		 666
667out_unlock:
668 spin_unlock_irq(&tp->lock);
669}
670
671static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
672{
673 struct rtl8169_private *tp = netdev_priv(dev);
674 void __iomem *ioaddr = tp->mmio_addr;
675 int i;
676 static struct {
677 u32 opt;
678 u16 reg;
679 u8 mask;
680 } cfg[] = {
681 { WAKE_ANY, Config1, PMEnable },
682 { WAKE_PHY, Config3, LinkUp },
683 { WAKE_MAGIC, Config3, MagicPacket },
684 { WAKE_UCAST, Config5, UWF },
685 { WAKE_BCAST, Config5, BWF },
686 { WAKE_MCAST, Config5, MWF },
687 { WAKE_ANY, Config5, LanWake }
688 };
689
690 spin_lock_irq(&tp->lock);
691
692 RTL_W8(Cfg9346, Cfg9346_Unlock);
693
694 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
695 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
696 if (wol->wolopts & cfg[i].opt)
697 options |= cfg[i].mask;
698 RTL_W8(cfg[i].reg, options);
699 }
700
701 RTL_W8(Cfg9346, Cfg9346_Lock);
702
703 tp->wol_enabled = (wol->wolopts) ? 1 : 0;
704
705 spin_unlock_irq(&tp->lock);
706
707 return 0;
708}
709
1da177e4
LT		 710static void rtl8169_get_drvinfo(struct net_device *dev,
711 struct ethtool_drvinfo *info)
712{
713 struct rtl8169_private *tp = netdev_priv(dev);
714
715 strcpy(info->driver, MODULENAME);
716 strcpy(info->version, RTL8169_VERSION);
717 strcpy(info->bus_info, pci_name(tp->pci_dev));
718}
719
720static int rtl8169_get_regs_len(struct net_device *dev)
721{
722 return R8169_REGS_SIZE;
723}
724
725static int rtl8169_set_speed_tbi(struct net_device *dev,
726 u8 autoneg, u16 speed, u8 duplex)
727{
728 struct rtl8169_private *tp = netdev_priv(dev);
729 void __iomem *ioaddr = tp->mmio_addr;
730 int ret = 0;
731 u32 reg;
732
733 reg = RTL_R32(TBICSR);
734 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
735 (duplex == DUPLEX_FULL)) {
736 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
737 } else if (autoneg == AUTONEG_ENABLE)
738 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
739 else {
b57b7e5a
SH		 740 if (netif_msg_link(tp)) {
741 printk(KERN_WARNING "%s: "
742 "incorrect speed setting refused in TBI mode\n",
743 dev->name);
744 }
1da177e4
LT		 745 ret = -EOPNOTSUPP;
746 }
747
748 return ret;
749}
750
751static int rtl8169_set_speed_xmii(struct net_device *dev,
752 u8 autoneg, u16 speed, u8 duplex)
753{
754 struct rtl8169_private *tp = netdev_priv(dev);
755 void __iomem *ioaddr = tp->mmio_addr;
756 int auto_nego, giga_ctrl;
757
64e4bfb4
FR		 758 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
759 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
760 ADVERTISE_100HALF | ADVERTISE_100FULL);
761 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
762 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 763
764 if (autoneg == AUTONEG_ENABLE) {
64e4bfb4
FR		 765 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
766 ADVERTISE_100HALF | ADVERTISE_100FULL);
767 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 768 } else {
769 if (speed == SPEED_10)
64e4bfb4 770 auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1da177e4 771 else if (speed == SPEED_100)
64e4bfb4 772 auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
1da177e4 773 else if (speed == SPEED_1000)
64e4bfb4 774 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 775
776 if (duplex == DUPLEX_HALF)
64e4bfb4 777 auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
726ecdcf
AG		 778
779 if (duplex == DUPLEX_FULL)
64e4bfb4 780 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
bcf0bf90
FR		 781
782 /* This tweak comes straight from Realtek's driver. */
783 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
784 (tp->mac_version == RTL_GIGA_MAC_VER_13)) {
64e4bfb4 785 auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
bcf0bf90
FR		 786 }
787 }
788
789 /* The 8100e/8101e do Fast Ethernet only. */
790 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
791 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
792 (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
64e4bfb4 793 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
bcf0bf90
FR		 794 netif_msg_link(tp)) {
795 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
796 dev->name);
797 }
64e4bfb4 798 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 799 }
800
623a1593
FR		 801 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
802
1da177e4
LT		 803 tp->phy_auto_nego_reg = auto_nego;
804 tp->phy_1000_ctrl_reg = giga_ctrl;
805
64e4bfb4
FR		 806 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
807 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
808 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
1da177e4
LT		 809 return 0;
810}
811
812static int rtl8169_set_speed(struct net_device *dev,
813 u8 autoneg, u16 speed, u8 duplex)
814{
815 struct rtl8169_private *tp = netdev_priv(dev);
816 int ret;
817
818 ret = tp->set_speed(dev, autoneg, speed, duplex);
819
64e4bfb4 820 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 821 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
822
823 return ret;
824}
825
826static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
827{
828 struct rtl8169_private *tp = netdev_priv(dev);
829 unsigned long flags;
830 int ret;
831
832 spin_lock_irqsave(&tp->lock, flags);
833 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
834 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 835
1da177e4
LT		 836 return ret;
837}
838
839static u32 rtl8169_get_rx_csum(struct net_device *dev)
840{
841 struct rtl8169_private *tp = netdev_priv(dev);
842
843 return tp->cp_cmd & RxChkSum;
844}
845
846static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
847{
848 struct rtl8169_private *tp = netdev_priv(dev);
849 void __iomem *ioaddr = tp->mmio_addr;
850 unsigned long flags;
851
852 spin_lock_irqsave(&tp->lock, flags);
853
854 if (data)
855 tp->cp_cmd |= RxChkSum;
856 else
857 tp->cp_cmd &= ~RxChkSum;
858
859 RTL_W16(CPlusCmd, tp->cp_cmd);
860 RTL_R16(CPlusCmd);
861
862 spin_unlock_irqrestore(&tp->lock, flags);
863
864 return 0;
865}
866
867#ifdef CONFIG_R8169_VLAN
868
869static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
870 struct sk_buff *skb)
871{
872 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
873 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
874}
875
876static void rtl8169_vlan_rx_register(struct net_device *dev,
877 struct vlan_group *grp)
878{
879 struct rtl8169_private *tp = netdev_priv(dev);
880 void __iomem *ioaddr = tp->mmio_addr;
881 unsigned long flags;
882
883 spin_lock_irqsave(&tp->lock, flags);
884 tp->vlgrp = grp;
885 if (tp->vlgrp)
886 tp->cp_cmd |= RxVlan;
887 else
888 tp->cp_cmd &= ~RxVlan;
889 RTL_W16(CPlusCmd, tp->cp_cmd);
890 RTL_R16(CPlusCmd);
891 spin_unlock_irqrestore(&tp->lock, flags);
892}
893
1da177e4
LT		 894static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
895 struct sk_buff *skb)
896{
897 u32 opts2 = le32_to_cpu(desc->opts2);
898 int ret;
899
900 if (tp->vlgrp && (opts2 & RxVlanTag)) {
901 rtl8169_rx_hwaccel_skb(skb, tp->vlgrp,
902 swab16(opts2 & 0xffff));
903 ret = 0;
904 } else
905 ret = -1;
906 desc->opts2 = 0;
907 return ret;
908}
909
910#else /* !CONFIG_R8169_VLAN */
911
912static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
913 struct sk_buff *skb)
914{
915 return 0;
916}
917
918static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
919 struct sk_buff *skb)
920{
921 return -1;
922}
923
924#endif
925
926static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
927{
928 struct rtl8169_private *tp = netdev_priv(dev);
929 void __iomem *ioaddr = tp->mmio_addr;
930 u32 status;
931
932 cmd->supported =
933 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
934 cmd->port = PORT_FIBRE;
935 cmd->transceiver = XCVR_INTERNAL;
936
937 status = RTL_R32(TBICSR);
938 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
939 cmd->autoneg = !!(status & TBINwEnable);
940
941 cmd->speed = SPEED_1000;
942 cmd->duplex = DUPLEX_FULL; /* Always set */
943}
944
945static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
946{
947 struct rtl8169_private *tp = netdev_priv(dev);
948 void __iomem *ioaddr = tp->mmio_addr;
949 u8 status;
950
951 cmd->supported = SUPPORTED_10baseT_Half |
952 SUPPORTED_10baseT_Full |
953 SUPPORTED_100baseT_Half |
954 SUPPORTED_100baseT_Full |
955 SUPPORTED_1000baseT_Full |
956 SUPPORTED_Autoneg |
5b0384f4 957 SUPPORTED_TP;
1da177e4
LT		 958
959 cmd->autoneg = 1;
960 cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
961
64e4bfb4 962 if (tp->phy_auto_nego_reg & ADVERTISE_10HALF)
1da177e4 963 cmd->advertising |= ADVERTISED_10baseT_Half;
64e4bfb4 964 if (tp->phy_auto_nego_reg & ADVERTISE_10FULL)
1da177e4 965 cmd->advertising |= ADVERTISED_10baseT_Full;
64e4bfb4 966 if (tp->phy_auto_nego_reg & ADVERTISE_100HALF)
1da177e4 967 cmd->advertising |= ADVERTISED_100baseT_Half;
64e4bfb4 968 if (tp->phy_auto_nego_reg & ADVERTISE_100FULL)
1da177e4 969 cmd->advertising |= ADVERTISED_100baseT_Full;
64e4bfb4 970 if (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)
1da177e4
LT		 971 cmd->advertising |= ADVERTISED_1000baseT_Full;
972
973 status = RTL_R8(PHYstatus);
974
975 if (status & _1000bpsF)
976 cmd->speed = SPEED_1000;
977 else if (status & _100bps)
978 cmd->speed = SPEED_100;
979 else if (status & _10bps)
980 cmd->speed = SPEED_10;
981
623a1593
FR		 982 if (status & TxFlowCtrl)
983 cmd->advertising |= ADVERTISED_Asym_Pause;
984 if (status & RxFlowCtrl)
985 cmd->advertising |= ADVERTISED_Pause;
986
1da177e4
LT		 987 cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ?
988 DUPLEX_FULL : DUPLEX_HALF;
989}
990
991static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
992{
993 struct rtl8169_private *tp = netdev_priv(dev);
994 unsigned long flags;
995
996 spin_lock_irqsave(&tp->lock, flags);
997
998 tp->get_settings(dev, cmd);
999
1000 spin_unlock_irqrestore(&tp->lock, flags);
1001 return 0;
1002}
1003
1004static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1005 void *p)
1006{
5b0384f4
FR		 1007 struct rtl8169_private *tp = netdev_priv(dev);
1008 unsigned long flags;
1da177e4 1009
5b0384f4
FR		 1010 if (regs->len > R8169_REGS_SIZE)
1011 regs->len = R8169_REGS_SIZE;
1da177e4 1012
5b0384f4
FR		 1013 spin_lock_irqsave(&tp->lock, flags);
1014 memcpy_fromio(p, tp->mmio_addr, regs->len);
1015 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 1016}
1017
b57b7e5a
SH		 1018static u32 rtl8169_get_msglevel(struct net_device *dev)
1019{
1020 struct rtl8169_private *tp = netdev_priv(dev);
1021
1022 return tp->msg_enable;
1023}
1024
1025static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1026{
1027 struct rtl8169_private *tp = netdev_priv(dev);
1028
1029 tp->msg_enable = value;
1030}
1031
d4a3a0fc
SH		 1032static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1033 "tx_packets",
1034 "rx_packets",
1035 "tx_errors",
1036 "rx_errors",
1037 "rx_missed",
1038 "align_errors",
1039 "tx_single_collisions",
1040 "tx_multi_collisions",
1041 "unicast",
1042 "broadcast",
1043 "multicast",
1044 "tx_aborted",
1045 "tx_underrun",
1046};
1047
1048struct rtl8169_counters {
1049 u64 tx_packets;
1050 u64 rx_packets;
1051 u64 tx_errors;
1052 u32 rx_errors;
1053 u16 rx_missed;
1054 u16 align_errors;
1055 u32 tx_one_collision;
1056 u32 tx_multi_collision;
1057 u64 rx_unicast;
1058 u64 rx_broadcast;
1059 u32 rx_multicast;
1060 u16 tx_aborted;
1061 u16 tx_underun;
1062};
1063
1064static int rtl8169_get_stats_count(struct net_device *dev)
1065{
1066 return ARRAY_SIZE(rtl8169_gstrings);
1067}
1068
1069static void rtl8169_get_ethtool_stats(struct net_device *dev,
1070 struct ethtool_stats *stats, u64 *data)
1071{
1072 struct rtl8169_private *tp = netdev_priv(dev);
1073 void __iomem *ioaddr = tp->mmio_addr;
1074 struct rtl8169_counters *counters;
1075 dma_addr_t paddr;
1076 u32 cmd;
1077
1078 ASSERT_RTNL();
1079
1080 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1081 if (!counters)
1082 return;
1083
1084 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1085 cmd = (u64)paddr & DMA_32BIT_MASK;
1086 RTL_W32(CounterAddrLow, cmd);
1087 RTL_W32(CounterAddrLow, cmd | CounterDump);
1088
1089 while (RTL_R32(CounterAddrLow) & CounterDump) {
1090 if (msleep_interruptible(1))
1091 break;
1092 }
1093
1094 RTL_W32(CounterAddrLow, 0);
1095 RTL_W32(CounterAddrHigh, 0);
1096
5b0384f4 1097 data[0] = le64_to_cpu(counters->tx_packets);
d4a3a0fc
SH		 1098 data[1] = le64_to_cpu(counters->rx_packets);
1099 data[2] = le64_to_cpu(counters->tx_errors);
1100 data[3] = le32_to_cpu(counters->rx_errors);
1101 data[4] = le16_to_cpu(counters->rx_missed);
1102 data[5] = le16_to_cpu(counters->align_errors);
1103 data[6] = le32_to_cpu(counters->tx_one_collision);
1104 data[7] = le32_to_cpu(counters->tx_multi_collision);
1105 data[8] = le64_to_cpu(counters->rx_unicast);
1106 data[9] = le64_to_cpu(counters->rx_broadcast);
1107 data[10] = le32_to_cpu(counters->rx_multicast);
1108 data[11] = le16_to_cpu(counters->tx_aborted);
1109 data[12] = le16_to_cpu(counters->tx_underun);
1110
1111 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1112}
1113
1114static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1115{
1116 switch(stringset) {
1117 case ETH_SS_STATS:
1118 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1119 break;
1120 }
1121}
1122
1123
7282d491 1124static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1125 .get_drvinfo = rtl8169_get_drvinfo,
1126 .get_regs_len = rtl8169_get_regs_len,
1127 .get_link = ethtool_op_get_link,
1128 .get_settings = rtl8169_get_settings,
1129 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1130 .get_msglevel = rtl8169_get_msglevel,
1131 .set_msglevel = rtl8169_set_msglevel,
1da177e4
LT		 1132 .get_rx_csum = rtl8169_get_rx_csum,
1133 .set_rx_csum = rtl8169_set_rx_csum,
1134 .get_tx_csum = ethtool_op_get_tx_csum,
1135 .set_tx_csum = ethtool_op_set_tx_csum,
1136 .get_sg = ethtool_op_get_sg,
1137 .set_sg = ethtool_op_set_sg,
1138 .get_tso = ethtool_op_get_tso,
1139 .set_tso = ethtool_op_set_tso,
1140 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1141 .get_wol = rtl8169_get_wol,
1142 .set_wol = rtl8169_set_wol,
d4a3a0fc
SH		 1143 .get_strings = rtl8169_get_strings,
1144 .get_stats_count = rtl8169_get_stats_count,
1145 .get_ethtool_stats = rtl8169_get_ethtool_stats,
6d6525b7 1146 .get_perm_addr = ethtool_op_get_perm_addr,
1da177e4
LT		 1147};
1148
1149static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg, int bitnum,
1150 int bitval)
1151{
1152 int val;
1153
1154 val = mdio_read(ioaddr, reg);
1155 val = (bitval == 1) ?
1156 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
5b0384f4 1157 mdio_write(ioaddr, reg, val & 0xffff);
1da177e4
LT		 1158}
1159
1160static void rtl8169_get_mac_version(struct rtl8169_private *tp, void __iomem *ioaddr)
1161{
0e485150
FR		 1162 /*
1163 * The driver currently handles the 8168Bf and the 8168Be identically
1164 * but they can be identified more specifically through the test below
1165 * if needed:
1166 *
1167 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1168 *
1169 * Same thing for the 8101Eb and the 8101Ec:
1170 *
1171 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1172 */
1da177e4
LT		 1173 const struct {
1174 u32 mask;
1175 int mac_version;
1176 } mac_info[] = {
bcf0bf90
FR		 1177 { 0x38800000, RTL_GIGA_MAC_VER_15 },
1178 { 0x38000000, RTL_GIGA_MAC_VER_12 },
1179 { 0x34000000, RTL_GIGA_MAC_VER_13 },
1180 { 0x30800000, RTL_GIGA_MAC_VER_14 },
5b0384f4 1181 { 0x30000000, RTL_GIGA_MAC_VER_11 },
6dccd16b 1182 { 0x98000000, RTL_GIGA_MAC_VER_06 },
bcf0bf90
FR		 1183 { 0x18000000, RTL_GIGA_MAC_VER_05 },
1184 { 0x10000000, RTL_GIGA_MAC_VER_04 },
1185 { 0x04000000, RTL_GIGA_MAC_VER_03 },
1186 { 0x00800000, RTL_GIGA_MAC_VER_02 },
1187 { 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
1da177e4
LT		 1188 }, *p = mac_info;
1189 u32 reg;
1190
6dccd16b 1191 reg = RTL_R32(TxConfig) & 0xfc800000;
1da177e4
LT		 1192 while ((reg & p->mask) != p->mask)
1193 p++;
1194 tp->mac_version = p->mac_version;
1195}
1196
1197static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1198{
bcf0bf90 1199 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1200}
1201
1202static void rtl8169_get_phy_version(struct rtl8169_private *tp, void __iomem *ioaddr)
1203{
1204 const struct {
1205 u16 mask;
1206 u16 set;
1207 int phy_version;
1208 } phy_info[] = {
1209 { 0x000f, 0x0002, RTL_GIGA_PHY_VER_G },
1210 { 0x000f, 0x0001, RTL_GIGA_PHY_VER_F },
1211 { 0x000f, 0x0000, RTL_GIGA_PHY_VER_E },
1212 { 0x0000, 0x0000, RTL_GIGA_PHY_VER_D } /* Catch-all */
1213 }, *p = phy_info;
1214 u16 reg;
1215
64e4bfb4 1216 reg = mdio_read(ioaddr, MII_PHYSID2) & 0xffff;
1da177e4
LT		 1217 while ((reg & p->mask) != p->set)
1218 p++;
1219 tp->phy_version = p->phy_version;
1220}
1221
1222static void rtl8169_print_phy_version(struct rtl8169_private *tp)
1223{
1224 struct {
1225 int version;
1226 char *msg;
1227 u32 reg;
1228 } phy_print[] = {
1229 { RTL_GIGA_PHY_VER_G, "RTL_GIGA_PHY_VER_G", 0x0002 },
1230 { RTL_GIGA_PHY_VER_F, "RTL_GIGA_PHY_VER_F", 0x0001 },
1231 { RTL_GIGA_PHY_VER_E, "RTL_GIGA_PHY_VER_E", 0x0000 },
1232 { RTL_GIGA_PHY_VER_D, "RTL_GIGA_PHY_VER_D", 0x0000 },
1233 { 0, NULL, 0x0000 }
1234 }, *p;
1235
1236 for (p = phy_print; p->msg; p++) {
1237 if (tp->phy_version == p->version) {
1238 dprintk("phy_version == %s (%04x)\n", p->msg, p->reg);
1239 return;
1240 }
1241 }
1242 dprintk("phy_version == Unknown\n");
1243}
1244
1245static void rtl8169_hw_phy_config(struct net_device *dev)
1246{
1247 struct rtl8169_private *tp = netdev_priv(dev);
1248 void __iomem *ioaddr = tp->mmio_addr;
1249 struct {
1250 u16 regs[5]; /* Beware of bit-sign propagation */
1251 } phy_magic[5] = { {
1252 { 0x0000, //w 4 15 12 0
1253 0x00a1, //w 3 15 0 00a1
1254 0x0008, //w 2 15 0 0008
1255 0x1020, //w 1 15 0 1020
1256 0x1000 } },{ //w 0 15 0 1000
1257 { 0x7000, //w 4 15 12 7
1258 0xff41, //w 3 15 0 ff41
1259 0xde60, //w 2 15 0 de60
1260 0x0140, //w 1 15 0 0140
1261 0x0077 } },{ //w 0 15 0 0077
1262 { 0xa000, //w 4 15 12 a
1263 0xdf01, //w 3 15 0 df01
1264 0xdf20, //w 2 15 0 df20
1265 0xff95, //w 1 15 0 ff95
1266 0xfa00 } },{ //w 0 15 0 fa00
1267 { 0xb000, //w 4 15 12 b
1268 0xff41, //w 3 15 0 ff41
1269 0xde20, //w 2 15 0 de20
1270 0x0140, //w 1 15 0 0140
1271 0x00bb } },{ //w 0 15 0 00bb
1272 { 0xf000, //w 4 15 12 f
1273 0xdf01, //w 3 15 0 df01
1274 0xdf20, //w 2 15 0 df20
1275 0xff95, //w 1 15 0 ff95
1276 0xbf00 } //w 0 15 0 bf00
1277 }
1278 }, *p = phy_magic;
1279 int i;
1280
1281 rtl8169_print_mac_version(tp);
1282 rtl8169_print_phy_version(tp);
1283
bcf0bf90 1284 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 1285 return;
1286 if (tp->phy_version >= RTL_GIGA_PHY_VER_H)
1287 return;
1288
1289 dprintk("MAC version != 0 && PHY version == 0 or 1\n");
1290 dprintk("Do final_reg2.cfg\n");
1291
1292 /* Shazam ! */
1293
bcf0bf90 1294 if (tp->mac_version == RTL_GIGA_MAC_VER_04) {
1da177e4
LT		 1295 mdio_write(ioaddr, 31, 0x0002);
1296 mdio_write(ioaddr, 1, 0x90d0);
1297 mdio_write(ioaddr, 31, 0x0000);
1298 return;
1299 }
1300
1301 /* phy config for RTL8169s mac_version C chip */
1302 mdio_write(ioaddr, 31, 0x0001); //w 31 2 0 1
1303 mdio_write(ioaddr, 21, 0x1000); //w 21 15 0 1000
1304 mdio_write(ioaddr, 24, 0x65c7); //w 24 15 0 65c7
1305 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1306
1307 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1308 int val, pos = 4;
1309
1310 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1311 mdio_write(ioaddr, pos, val);
1312 while (--pos >= 0)
1313 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1314 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1315 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1316 }
1317 mdio_write(ioaddr, 31, 0x0000); //w 31 2 0 0
1318}
1319
1320static void rtl8169_phy_timer(unsigned long __opaque)
1321{
1322 struct net_device *dev = (struct net_device *)__opaque;
1323 struct rtl8169_private *tp = netdev_priv(dev);
1324 struct timer_list *timer = &tp->timer;
1325 void __iomem *ioaddr = tp->mmio_addr;
1326 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1327
bcf0bf90 1328 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4
LT		 1329 assert(tp->phy_version < RTL_GIGA_PHY_VER_H);
1330
64e4bfb4 1331 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 1332 return;
1333
1334 spin_lock_irq(&tp->lock);
1335
1336 if (tp->phy_reset_pending(ioaddr)) {
5b0384f4 1337 /*
1da177e4
LT		 1338 * A busy loop could burn quite a few cycles on nowadays CPU.
1339 * Let's delay the execution of the timer for a few ticks.
1340 */
1341 timeout = HZ/10;
1342 goto out_mod_timer;
1343 }
1344
1345 if (tp->link_ok(ioaddr))
1346 goto out_unlock;
1347
b57b7e5a
SH		 1348 if (netif_msg_link(tp))
1349 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1da177e4
LT		 1350
1351 tp->phy_reset_enable(ioaddr);
1352
1353out_mod_timer:
1354 mod_timer(timer, jiffies + timeout);
1355out_unlock:
1356 spin_unlock_irq(&tp->lock);
1357}
1358
1359static inline void rtl8169_delete_timer(struct net_device *dev)
1360{
1361 struct rtl8169_private *tp = netdev_priv(dev);
1362 struct timer_list *timer = &tp->timer;
1363
bcf0bf90 1364 if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1da177e4
LT		 1365 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1366 return;
1367
1368 del_timer_sync(timer);
1369}
1370
1371static inline void rtl8169_request_timer(struct net_device *dev)
1372{
1373 struct rtl8169_private *tp = netdev_priv(dev);
1374 struct timer_list *timer = &tp->timer;
1375
bcf0bf90 1376 if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1da177e4
LT		 1377 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1378 return;
1379
2efa53f3 1380 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1da177e4
LT		 1381}
1382
1383#ifdef CONFIG_NET_POLL_CONTROLLER
1384/*
1385 * Polling 'interrupt' - used by things like netconsole to send skbs
1386 * without having to re-enable interrupts. It's not called while
1387 * the interrupt routine is executing.
1388 */
1389static void rtl8169_netpoll(struct net_device *dev)
1390{
1391 struct rtl8169_private *tp = netdev_priv(dev);
1392 struct pci_dev *pdev = tp->pci_dev;
1393
1394 disable_irq(pdev->irq);
7d12e780 1395 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 1396 enable_irq(pdev->irq);
1397}
1398#endif
1399
1400static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1401 void __iomem *ioaddr)
1402{
1403 iounmap(ioaddr);
1404 pci_release_regions(pdev);
1405 pci_disable_device(pdev);
1406 free_netdev(dev);
1407}
1408
bf793295
FR		 1409static void rtl8169_phy_reset(struct net_device *dev,
1410 struct rtl8169_private *tp)
1411{
1412 void __iomem *ioaddr = tp->mmio_addr;
1413 int i;
1414
1415 tp->phy_reset_enable(ioaddr);
1416 for (i = 0; i < 100; i++) {
1417 if (!tp->phy_reset_pending(ioaddr))
1418 return;
1419 msleep(1);
1420 }
1421 if (netif_msg_link(tp))
1422 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1423}
1424
4ff96fa6
FR		 1425static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1426{
1427 void __iomem *ioaddr = tp->mmio_addr;
1428 static int board_idx = -1;
1429 u8 autoneg, duplex;
1430 u16 speed;
1431
1432 board_idx++;
1433
1434 rtl8169_hw_phy_config(dev);
1435
1436 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1437 RTL_W8(0x82, 0x01);
1438
6dccd16b
FR		 1439 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1440
1441 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1442 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 1443
bcf0bf90 1444 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 1445 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1446 RTL_W8(0x82, 0x01);
1447 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1448 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1449 }
1450
1451 rtl8169_link_option(board_idx, &autoneg, &speed, &duplex);
1452
bf793295
FR		 1453 rtl8169_phy_reset(dev, tp);
1454
4ff96fa6
FR		 1455 rtl8169_set_speed(dev, autoneg, speed, duplex);
1456
1457 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1458 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1459}
1460
5f787a1a
FR		 1461static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1462{
1463 struct rtl8169_private *tp = netdev_priv(dev);
1464 struct mii_ioctl_data *data = if_mii(ifr);
1465
1466 if (!netif_running(dev))
1467 return -ENODEV;
1468
1469 switch (cmd) {
1470 case SIOCGMIIPHY:
1471 data->phy_id = 32; /* Internal PHY */
1472 return 0;
1473
1474 case SIOCGMIIREG:
1475 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1476 return 0;
1477
1478 case SIOCSMIIREG:
1479 if (!capable(CAP_NET_ADMIN))
1480 return -EPERM;
1481 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1482 return 0;
1483 }
1484 return -EOPNOTSUPP;
1485}
1486
0e485150
FR		 1487static const struct rtl_cfg_info {
1488 void (*hw_start)(struct net_device *);
1489 unsigned int region;
1490 unsigned int align;
1491 u16 intr_event;
1492 u16 napi_event;
1493} rtl_cfg_infos [] = {
1494 [RTL_CFG_0] = {
1495 .hw_start = rtl_hw_start_8169,
1496 .region = 1,
86402234 1497 .align = 2,
0e485150
FR		 1498 .intr_event = SYSErr | LinkChg | RxOverflow |
1499 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1500 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow
1501 },
1502 [RTL_CFG_1] = {
1503 .hw_start = rtl_hw_start_8168,
1504 .region = 2,
1505 .align = 8,
1506 .intr_event = SYSErr | LinkChg | RxOverflow |
1507 TxErr | TxOK | RxOK | RxErr,
1508 .napi_event = TxErr | TxOK | RxOK | RxOverflow
1509 },
1510 [RTL_CFG_2] = {
1511 .hw_start = rtl_hw_start_8101,
1512 .region = 2,
1513 .align = 8,
1514 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1515 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1516 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow
1517 }
1518};
1519
1da177e4 1520static int __devinit
4ff96fa6 1521rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1522{
0e485150
FR		 1523 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1524 const unsigned int region = cfg->region;
1da177e4 1525 struct rtl8169_private *tp;
4ff96fa6
FR		 1526 struct net_device *dev;
1527 void __iomem *ioaddr;
315917d2
FR		 1528 unsigned int pm_cap;
1529 int i, rc;
1da177e4 1530
4ff96fa6
FR		 1531 if (netif_msg_drv(&debug)) {
1532 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1533 MODULENAME, RTL8169_VERSION);
1534 }
1da177e4 1535
1da177e4 1536 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 1537 if (!dev) {
b57b7e5a 1538 if (netif_msg_drv(&debug))
9b91cf9d 1539 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 1540 rc = -ENOMEM;
1541 goto out;
1da177e4
LT		 1542 }
1543
1544 SET_MODULE_OWNER(dev);
1545 SET_NETDEV_DEV(dev, &pdev->dev);
1546 tp = netdev_priv(dev);
c4028958 1547 tp->dev = dev;
b57b7e5a 1548 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4
LT		 1549
1550 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1551 rc = pci_enable_device(pdev);
b57b7e5a 1552 if (rc < 0) {
2e8a538d 1553 if (netif_msg_probe(tp))
9b91cf9d 1554 dev_err(&pdev->dev, "enable failure\n");
4ff96fa6 1555 goto err_out_free_dev_1;
1da177e4
LT		 1556 }
1557
1558 rc = pci_set_mwi(pdev);
1559 if (rc < 0)
4ff96fa6 1560 goto err_out_disable_2;
1da177e4
LT		 1561
1562 /* save power state before pci_enable_device overwrites it */
1563 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
1564 if (pm_cap) {
4ff96fa6 1565 u16 pwr_command, acpi_idle_state;
1da177e4
LT		 1566
1567 pci_read_config_word(pdev, pm_cap + PCI_PM_CTRL, &pwr_command);
1568 acpi_idle_state = pwr_command & PCI_PM_CTRL_STATE_MASK;
1569 } else {
4ff96fa6 1570 if (netif_msg_probe(tp)) {
9b91cf9d 1571 dev_err(&pdev->dev,
4ff96fa6
FR		 1572 "PowerManagement capability not found.\n");
1573 }
1da177e4
LT		 1574 }
1575
1576 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 1577 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
4ff96fa6 1578 if (netif_msg_probe(tp)) {
9b91cf9d 1579 dev_err(&pdev->dev,
bcf0bf90
FR		 1580 "region #%d not an MMIO resource, aborting\n",
1581 region);
4ff96fa6 1582 }
1da177e4 1583 rc = -ENODEV;
4ff96fa6 1584 goto err_out_mwi_3;
1da177e4 1585 }
4ff96fa6 1586
1da177e4 1587 /* check for weird/broken PCI region reporting */
bcf0bf90 1588 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
4ff96fa6 1589 if (netif_msg_probe(tp)) {
9b91cf9d 1590 dev_err(&pdev->dev,
4ff96fa6
FR		 1591 "Invalid PCI region size(s), aborting\n");
1592 }
1da177e4 1593 rc = -ENODEV;
4ff96fa6 1594 goto err_out_mwi_3;
1da177e4
LT		 1595 }
1596
1597 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 1598 if (rc < 0) {
2e8a538d 1599 if (netif_msg_probe(tp))
9b91cf9d 1600 dev_err(&pdev->dev, "could not request regions.\n");
4ff96fa6 1601 goto err_out_mwi_3;
1da177e4
LT		 1602 }
1603
1604 tp->cp_cmd = PCIMulRW | RxChkSum;
1605
1606 if ((sizeof(dma_addr_t) > 4) &&
1607 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1608 tp->cp_cmd |= PCIDAC;
1609 dev->features |= NETIF_F_HIGHDMA;
1610 } else {
1611 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1612 if (rc < 0) {
4ff96fa6 1613 if (netif_msg_probe(tp)) {
9b91cf9d 1614 dev_err(&pdev->dev,
4ff96fa6
FR		 1615 "DMA configuration failed.\n");
1616 }
1617 goto err_out_free_res_4;
1da177e4
LT		 1618 }
1619 }
1620
1621 pci_set_master(pdev);
1622
1623 /* ioremap MMIO region */
bcf0bf90 1624 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 1625 if (!ioaddr) {
b57b7e5a 1626 if (netif_msg_probe(tp))
9b91cf9d 1627 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1da177e4 1628 rc = -EIO;
4ff96fa6 1629 goto err_out_free_res_4;
1da177e4
LT		 1630 }
1631
1632 /* Unneeded ? Don't mess with Mrs. Murphy. */
1633 rtl8169_irq_mask_and_ack(ioaddr);
1634
1635 /* Soft reset the chip. */
1636 RTL_W8(ChipCmd, CmdReset);
1637
1638 /* Check that the chip has finished the reset. */
b518fa8e 1639 for (i = 100; i > 0; i--) {
1da177e4
LT		 1640 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1641 break;
b518fa8e 1642 msleep_interruptible(1);
1da177e4
LT		 1643 }
1644
1645 /* Identify chip attached to board */
1646 rtl8169_get_mac_version(tp, ioaddr);
1647 rtl8169_get_phy_version(tp, ioaddr);
1648
1649 rtl8169_print_mac_version(tp);
1650 rtl8169_print_phy_version(tp);
1651
1652 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) {
1653 if (tp->mac_version == rtl_chip_info[i].mac_version)
1654 break;
1655 }
1656 if (i < 0) {
1657 /* Unknown chip: assume array element #0, original RTL-8169 */
b57b7e5a 1658 if (netif_msg_probe(tp)) {
2e8a538d 1659 dev_printk(KERN_DEBUG, &pdev->dev,
4ff96fa6
FR		 1660 "unknown chip version, assuming %s\n",
1661 rtl_chip_info[0].name);
b57b7e5a 1662 }
1da177e4
LT		 1663 i++;
1664 }
1665 tp->chipset = i;
1666
5d06a99f
FR		 1667 RTL_W8(Cfg9346, Cfg9346_Unlock);
1668 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1669 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
1670 RTL_W8(Cfg9346, Cfg9346_Lock);
1671
1da177e4
LT		 1672 if (RTL_R8(PHYstatus) & TBI_Enable) {
1673 tp->set_speed = rtl8169_set_speed_tbi;
1674 tp->get_settings = rtl8169_gset_tbi;
1675 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1676 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1677 tp->link_ok = rtl8169_tbi_link_ok;
1678
64e4bfb4 1679 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1da177e4
LT		 1680 } else {
1681 tp->set_speed = rtl8169_set_speed_xmii;
1682 tp->get_settings = rtl8169_gset_xmii;
1683 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1684 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1685 tp->link_ok = rtl8169_xmii_link_ok;
5f787a1a
FR		 1686
1687 dev->do_ioctl = rtl8169_ioctl;
1da177e4
LT		 1688 }
1689
1690 /* Get MAC address. FIXME: read EEPROM */
1691 for (i = 0; i < MAC_ADDR_LEN; i++)
1692 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 1693 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 1694
1695 dev->open = rtl8169_open;
1696 dev->hard_start_xmit = rtl8169_start_xmit;
1697 dev->get_stats = rtl8169_get_stats;
1698 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1699 dev->stop = rtl8169_close;
1700 dev->tx_timeout = rtl8169_tx_timeout;
07ce4064 1701 dev->set_multicast_list = rtl_set_rx_mode;
1da177e4
LT		 1702 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1703 dev->irq = pdev->irq;
1704 dev->base_addr = (unsigned long) ioaddr;
1705 dev->change_mtu = rtl8169_change_mtu;
1706
1707#ifdef CONFIG_R8169_NAPI
1708 dev->poll = rtl8169_poll;
1709 dev->weight = R8169_NAPI_WEIGHT;
1da177e4
LT		 1710#endif
1711
1712#ifdef CONFIG_R8169_VLAN
1713 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1714 dev->vlan_rx_register = rtl8169_vlan_rx_register;
1da177e4
LT		 1715#endif
1716
1717#ifdef CONFIG_NET_POLL_CONTROLLER
1718 dev->poll_controller = rtl8169_netpoll;
1719#endif
1720
1721 tp->intr_mask = 0xffff;
1722 tp->pci_dev = pdev;
1723 tp->mmio_addr = ioaddr;
0e485150
FR		 1724 tp->align = cfg->align;
1725 tp->hw_start = cfg->hw_start;
1726 tp->intr_event = cfg->intr_event;
1727 tp->napi_event = cfg->napi_event;
1da177e4 1728
2efa53f3
FR		 1729 init_timer(&tp->timer);
1730 tp->timer.data = (unsigned long) dev;
1731 tp->timer.function = rtl8169_phy_timer;
1732
1da177e4
LT		 1733 spin_lock_init(&tp->lock);
1734
1735 rc = register_netdev(dev);
4ff96fa6
FR		 1736 if (rc < 0)
1737 goto err_out_unmap_5;
1da177e4
LT		 1738
1739 pci_set_drvdata(pdev, dev);
1740
b57b7e5a
SH		 1741 if (netif_msg_probe(tp)) {
1742 printk(KERN_INFO "%s: %s at 0x%lx, "
1743 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1744 "IRQ %d\n",
1745 dev->name,
bcf0bf90 1746 rtl_chip_info[tp->chipset].name,
b57b7e5a
SH		 1747 dev->base_addr,
1748 dev->dev_addr[0], dev->dev_addr[1],
1749 dev->dev_addr[2], dev->dev_addr[3],
1750 dev->dev_addr[4], dev->dev_addr[5], dev->irq);
1751 }
1da177e4 1752
4ff96fa6 1753 rtl8169_init_phy(dev, tp);
1da177e4 1754
4ff96fa6
FR		 1755out:
1756 return rc;
1da177e4 1757
4ff96fa6
FR		 1758err_out_unmap_5:
1759 iounmap(ioaddr);
1760err_out_free_res_4:
1761 pci_release_regions(pdev);
1762err_out_mwi_3:
1763 pci_clear_mwi(pdev);
1764err_out_disable_2:
1765 pci_disable_device(pdev);
1766err_out_free_dev_1:
1767 free_netdev(dev);
1768 goto out;
1da177e4
LT		 1769}
1770
1771static void __devexit
1772rtl8169_remove_one(struct pci_dev *pdev)
1773{
1774 struct net_device *dev = pci_get_drvdata(pdev);
1775 struct rtl8169_private *tp = netdev_priv(dev);
1776
1777 assert(dev != NULL);
1778 assert(tp != NULL);
1779
eb2a021c
FR		 1780 flush_scheduled_work();
1781
1da177e4
LT		 1782 unregister_netdev(dev);
1783 rtl8169_release_board(pdev, dev, tp->mmio_addr);
1784 pci_set_drvdata(pdev, NULL);
1785}
1786
1da177e4
LT		 1787static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
1788 struct net_device *dev)
1789{
1790 unsigned int mtu = dev->mtu;
1791
1792 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1793}
1794
1795static int rtl8169_open(struct net_device *dev)
1796{
1797 struct rtl8169_private *tp = netdev_priv(dev);
1798 struct pci_dev *pdev = tp->pci_dev;
99f252b0 1799 int retval = -ENOMEM;
1da177e4 1800
1da177e4 1801
99f252b0 1802 rtl8169_set_rxbufsize(tp, dev);
1da177e4
LT		 1803
1804 /*
1805 * Rx and Tx desscriptors needs 256 bytes alignment.
1806 * pci_alloc_consistent provides more.
1807 */
1808 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1809 &tp->TxPhyAddr);
1810 if (!tp->TxDescArray)
99f252b0 1811 goto out;
1da177e4
LT		 1812
1813 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1814 &tp->RxPhyAddr);
1815 if (!tp->RxDescArray)
99f252b0 1816 goto err_free_tx_0;
1da177e4
LT		 1817
1818 retval = rtl8169_init_ring(dev);
1819 if (retval < 0)
99f252b0 1820 goto err_free_rx_1;
1da177e4 1821
c4028958 1822 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 1823
99f252b0
FR		 1824 smp_mb();
1825
1826 retval = request_irq(dev->irq, rtl8169_interrupt, IRQF_SHARED,
1827 dev->name, dev);
1828 if (retval < 0)
1829 goto err_release_ring_2;
1830
07ce4064 1831 rtl_hw_start(dev);
1da177e4
LT		 1832
1833 rtl8169_request_timer(dev);
1834
1835 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1836out:
1837 return retval;
1838
99f252b0
FR		 1839err_release_ring_2:
1840 rtl8169_rx_clear(tp);
1841err_free_rx_1:
1da177e4
LT		 1842 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1843 tp->RxPhyAddr);
99f252b0 1844err_free_tx_0:
1da177e4
LT		 1845 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1846 tp->TxPhyAddr);
1da177e4
LT		 1847 goto out;
1848}
1849
1850static void rtl8169_hw_reset(void __iomem *ioaddr)
1851{
1852 /* Disable interrupts */
1853 rtl8169_irq_mask_and_ack(ioaddr);
1854
1855 /* Reset the chipset */
1856 RTL_W8(ChipCmd, CmdReset);
1857
1858 /* PCI commit */
1859 RTL_R8(ChipCmd);
1860}
1861
7f796d83 1862static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 1863{
1864 void __iomem *ioaddr = tp->mmio_addr;
1865 u32 cfg = rtl8169_rx_config;
1866
1867 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1868 RTL_W32(RxConfig, cfg);
1869
1870 /* Set DMA burst size and Interframe Gap Time */
1871 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
1872 (InterFrameGap << TxInterFrameGapShift));
1873}
1874
07ce4064 1875static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 1876{
1877 struct rtl8169_private *tp = netdev_priv(dev);
1878 void __iomem *ioaddr = tp->mmio_addr;
1879 u32 i;
1880
1881 /* Soft reset the chip. */
1882 RTL_W8(ChipCmd, CmdReset);
1883
1884 /* Check that the chip has finished the reset. */
b518fa8e 1885 for (i = 100; i > 0; i--) {
1da177e4
LT		 1886 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1887 break;
b518fa8e 1888 msleep_interruptible(1);
1da177e4
LT		 1889 }
1890
07ce4064
FR		 1891 tp->hw_start(dev);
1892
07ce4064
FR		 1893 netif_start_queue(dev);
1894}
1895
1896
7f796d83
FR		 1897static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
1898 void __iomem *ioaddr)
1899{
1900 /*
1901 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
1902 * register to be written before TxDescAddrLow to work.
1903 * Switching from MMIO to I/O access fixes the issue as well.
1904 */
1905 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
1906 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
1907 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
1908 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
1909}
1910
1911static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
1912{
1913 u16 cmd;
1914
1915 cmd = RTL_R16(CPlusCmd);
1916 RTL_W16(CPlusCmd, cmd);
1917 return cmd;
1918}
1919
1920static void rtl_set_rx_max_size(void __iomem *ioaddr)
1921{
1922 /* Low hurts. Let's disable the filtering. */
1923 RTL_W16(RxMaxSize, 16383);
1924}
1925
6dccd16b
FR		 1926static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
1927{
1928 struct {
1929 u32 mac_version;
1930 u32 clk;
1931 u32 val;
1932 } cfg2_info [] = {
1933 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
1934 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
1935 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
1936 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
1937 }, *p = cfg2_info;
1938 unsigned int i;
1939 u32 clk;
1940
1941 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
1942 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++) {
1943 if ((p->mac_version == mac_version) && (p->clk == clk)) {
1944 RTL_W32(0x7c, p->val);
1945 break;
1946 }
1947 }
1948}
1949
07ce4064
FR		 1950static void rtl_hw_start_8169(struct net_device *dev)
1951{
1952 struct rtl8169_private *tp = netdev_priv(dev);
1953 void __iomem *ioaddr = tp->mmio_addr;
1954 struct pci_dev *pdev = tp->pci_dev;
07ce4064 1955
9cb427b6
FR		 1956 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
1957 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
1958 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
1959 }
1960
1da177e4 1961 RTL_W8(Cfg9346, Cfg9346_Unlock);
9cb427b6
FR		 1962 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
1963 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1964 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
1965 (tp->mac_version == RTL_GIGA_MAC_VER_04))
1966 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1967
1da177e4
LT		 1968 RTL_W8(EarlyTxThres, EarlyTxThld);
1969
7f796d83 1970 rtl_set_rx_max_size(ioaddr);
1da177e4 1971
6dccd16b 1972 rtl_set_rx_tx_config_registers(tp);
1da177e4 1973
7f796d83 1974 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 1975
bcf0bf90
FR		 1976 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1977 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1da177e4
LT		 1978 dprintk(KERN_INFO PFX "Set MAC Reg C+CR Offset 0xE0. "
1979 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 1980 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 1981 }
1982
bcf0bf90
FR		 1983 RTL_W16(CPlusCmd, tp->cp_cmd);
1984
6dccd16b
FR		 1985 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
1986
1da177e4
LT		 1987 /*
1988 * Undocumented corner. Supposedly:
1989 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
1990 */
1991 RTL_W16(IntrMitigate, 0x0000);
1992
7f796d83 1993 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 1994
1da177e4 1995 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 1996
1997 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
1998 RTL_R8(IntrMask);
1da177e4
LT		 1999
2000 RTL_W32(RxMissed, 0);
2001
07ce4064 2002 rtl_set_rx_mode(dev);
1da177e4
LT		 2003
2004 /* no early-rx interrupts */
2005 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 2006
2007 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 2008 RTL_W16(IntrMask, tp->intr_event);
6dccd16b
FR		 2009
2010 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
07ce4064 2011}
1da177e4 2012
07ce4064
FR		 2013static void rtl_hw_start_8168(struct net_device *dev)
2014{
2dd99530
FR		 2015 struct rtl8169_private *tp = netdev_priv(dev);
2016 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 2017 struct pci_dev *pdev = tp->pci_dev;
2018 u8 ctl;
2dd99530
FR		 2019
2020 RTL_W8(Cfg9346, Cfg9346_Unlock);
2021
2022 RTL_W8(EarlyTxThres, EarlyTxThld);
2023
2024 rtl_set_rx_max_size(ioaddr);
2025
0e485150
FR		 2026 rtl_set_rx_tx_config_registers(tp);
2027
2028 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 2029
2030 RTL_W16(CPlusCmd, tp->cp_cmd);
2031
0e485150
FR		 2032 /* Tx performance tweak. */
2033 pci_read_config_byte(pdev, 0x69, &ctl);
2034 ctl = (ctl & ~0x70) | 0x50;
2035 pci_write_config_byte(pdev, 0x69, ctl);
2dd99530 2036
0e485150 2037 RTL_W16(IntrMitigate, 0x5151);
2dd99530 2038
0e485150
FR		 2039 /* Work around for RxFIFO overflow. */
2040 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2041 tp->intr_event |= RxFIFOOver | PCSTimeout;
2042 tp->intr_event &= ~RxOverflow;
2043 }
2044
2045 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530
FR		 2046
2047 RTL_W8(Cfg9346, Cfg9346_Lock);
2048
2049 RTL_R8(IntrMask);
2050
2051 RTL_W32(RxMissed, 0);
2052
2053 rtl_set_rx_mode(dev);
2054
0e485150
FR		 2055 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2056
2dd99530 2057 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 2058
0e485150 2059 RTL_W16(IntrMask, tp->intr_event);
07ce4064 2060}
1da177e4 2061
07ce4064
FR		 2062static void rtl_hw_start_8101(struct net_device *dev)
2063{
cdf1a608
FR		 2064 struct rtl8169_private *tp = netdev_priv(dev);
2065 void __iomem *ioaddr = tp->mmio_addr;
2066 struct pci_dev *pdev = tp->pci_dev;
2067
2068 if (tp->mac_version == RTL_GIGA_MAC_VER_13) {
2069 pci_write_config_word(pdev, 0x68, 0x00);
2070 pci_write_config_word(pdev, 0x69, 0x08);
2071 }
2072
2073 RTL_W8(Cfg9346, Cfg9346_Unlock);
2074
2075 RTL_W8(EarlyTxThres, EarlyTxThld);
2076
2077 rtl_set_rx_max_size(ioaddr);
2078
2079 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2080
2081 RTL_W16(CPlusCmd, tp->cp_cmd);
2082
2083 RTL_W16(IntrMitigate, 0x0000);
2084
2085 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2086
2087 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2088 rtl_set_rx_tx_config_registers(tp);
2089
2090 RTL_W8(Cfg9346, Cfg9346_Lock);
2091
2092 RTL_R8(IntrMask);
2093
2094 RTL_W32(RxMissed, 0);
2095
2096 rtl_set_rx_mode(dev);
2097
0e485150
FR		 2098 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2099
cdf1a608 2100 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 2101
0e485150 2102 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 2103}
2104
2105static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2106{
2107 struct rtl8169_private *tp = netdev_priv(dev);
2108 int ret = 0;
2109
2110 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2111 return -EINVAL;
2112
2113 dev->mtu = new_mtu;
2114
2115 if (!netif_running(dev))
2116 goto out;
2117
2118 rtl8169_down(dev);
2119
2120 rtl8169_set_rxbufsize(tp, dev);
2121
2122 ret = rtl8169_init_ring(dev);
2123 if (ret < 0)
2124 goto out;
2125
2126 netif_poll_enable(dev);
2127
07ce4064 2128 rtl_hw_start(dev);
1da177e4
LT		 2129
2130 rtl8169_request_timer(dev);
2131
2132out:
2133 return ret;
2134}
2135
2136static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2137{
2138 desc->addr = 0x0badbadbadbadbadull;
2139 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2140}
2141
2142static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2143 struct sk_buff **sk_buff, struct RxDesc *desc)
2144{
2145 struct pci_dev *pdev = tp->pci_dev;
2146
2147 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2148 PCI_DMA_FROMDEVICE);
2149 dev_kfree_skb(*sk_buff);
2150 *sk_buff = NULL;
2151 rtl8169_make_unusable_by_asic(desc);
2152}
2153
2154static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2155{
2156 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2157
2158 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2159}
2160
2161static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2162 u32 rx_buf_sz)
2163{
2164 desc->addr = cpu_to_le64(mapping);
2165 wmb();
2166 rtl8169_mark_to_asic(desc, rx_buf_sz);
2167}
2168
15d31758
SH		 2169static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2170 struct net_device *dev,
2171 struct RxDesc *desc, int rx_buf_sz,
2172 unsigned int align)
1da177e4
LT		 2173{
2174 struct sk_buff *skb;
2175 dma_addr_t mapping;
1da177e4 2176
15d31758 2177 skb = netdev_alloc_skb(dev, rx_buf_sz + align);
1da177e4
LT		 2178 if (!skb)
2179 goto err_out;
2180
dcb92f88 2181 skb_reserve(skb, (align - 1) & (unsigned long)skb->data);
1da177e4 2182
689be439 2183 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
1da177e4
LT		 2184 PCI_DMA_FROMDEVICE);
2185
2186 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
1da177e4 2187out:
15d31758 2188 return skb;
1da177e4
LT		 2189
2190err_out:
1da177e4
LT		 2191 rtl8169_make_unusable_by_asic(desc);
2192 goto out;
2193}
2194
2195static void rtl8169_rx_clear(struct rtl8169_private *tp)
2196{
2197 int i;
2198
2199 for (i = 0; i < NUM_RX_DESC; i++) {
2200 if (tp->Rx_skbuff[i]) {
2201 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2202 tp->RxDescArray + i);
2203 }
2204 }
2205}
2206
2207static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2208 u32 start, u32 end)
2209{
2210 u32 cur;
5b0384f4 2211
4ae47c2d 2212 for (cur = start; end - cur != 0; cur++) {
15d31758
SH		 2213 struct sk_buff *skb;
2214 unsigned int i = cur % NUM_RX_DESC;
1da177e4 2215
4ae47c2d
FR		 2216 WARN_ON((s32)(end - cur) < 0);
2217
1da177e4
LT		 2218 if (tp->Rx_skbuff[i])
2219 continue;
bcf0bf90 2220
15d31758
SH		 2221 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2222 tp->RxDescArray + i,
2223 tp->rx_buf_sz, tp->align);
2224 if (!skb)
1da177e4 2225 break;
15d31758
SH		 2226
2227 tp->Rx_skbuff[i] = skb;
1da177e4
LT		 2228 }
2229 return cur - start;
2230}
2231
2232static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2233{
2234 desc->opts1 |= cpu_to_le32(RingEnd);
2235}
2236
2237static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2238{
2239 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2240}
2241
2242static int rtl8169_init_ring(struct net_device *dev)
2243{
2244 struct rtl8169_private *tp = netdev_priv(dev);
2245
2246 rtl8169_init_ring_indexes(tp);
2247
2248 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2249 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2250
2251 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2252 goto err_out;
2253
2254 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2255
2256 return 0;
2257
2258err_out:
2259 rtl8169_rx_clear(tp);
2260 return -ENOMEM;
2261}
2262
2263static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2264 struct TxDesc *desc)
2265{
2266 unsigned int len = tx_skb->len;
2267
2268 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2269 desc->opts1 = 0x00;
2270 desc->opts2 = 0x00;
2271 desc->addr = 0x00;
2272 tx_skb->len = 0;
2273}
2274
2275static void rtl8169_tx_clear(struct rtl8169_private *tp)
2276{
2277 unsigned int i;
2278
2279 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2280 unsigned int entry = i % NUM_TX_DESC;
2281 struct ring_info *tx_skb = tp->tx_skb + entry;
2282 unsigned int len = tx_skb->len;
2283
2284 if (len) {
2285 struct sk_buff *skb = tx_skb->skb;
2286
2287 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2288 tp->TxDescArray + entry);
2289 if (skb) {
2290 dev_kfree_skb(skb);
2291 tx_skb->skb = NULL;
2292 }
2293 tp->stats.tx_dropped++;
2294 }
2295 }
2296 tp->cur_tx = tp->dirty_tx = 0;
2297}
2298
c4028958 2299static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 2300{
2301 struct rtl8169_private *tp = netdev_priv(dev);
2302
c4028958 2303 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 2304 schedule_delayed_work(&tp->task, 4);
2305}
2306
2307static void rtl8169_wait_for_quiescence(struct net_device *dev)
2308{
2309 struct rtl8169_private *tp = netdev_priv(dev);
2310 void __iomem *ioaddr = tp->mmio_addr;
2311
2312 synchronize_irq(dev->irq);
2313
2314 /* Wait for any pending NAPI task to complete */
2315 netif_poll_disable(dev);
2316
2317 rtl8169_irq_mask_and_ack(ioaddr);
2318
2319 netif_poll_enable(dev);
2320}
2321
c4028958 2322static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 2323{
c4028958
DH		 2324 struct rtl8169_private *tp =
2325 container_of(work, struct rtl8169_private, task.work);
2326 struct net_device *dev = tp->dev;
1da177e4
LT		 2327 int ret;
2328
eb2a021c
FR		 2329 rtnl_lock();
2330
2331 if (!netif_running(dev))
2332 goto out_unlock;
2333
2334 rtl8169_wait_for_quiescence(dev);
2335 rtl8169_close(dev);
1da177e4
LT		 2336
2337 ret = rtl8169_open(dev);
2338 if (unlikely(ret < 0)) {
2339 if (net_ratelimit()) {
b57b7e5a
SH		 2340 struct rtl8169_private *tp = netdev_priv(dev);
2341
2342 if (netif_msg_drv(tp)) {
2343 printk(PFX KERN_ERR
2344 "%s: reinit failure (status = %d)."
2345 " Rescheduling.\n", dev->name, ret);
2346 }
1da177e4
LT		 2347 }
2348 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2349 }
eb2a021c
FR		 2350
2351out_unlock:
2352 rtnl_unlock();
1da177e4
LT		 2353}
2354
c4028958 2355static void rtl8169_reset_task(struct work_struct *work)
1da177e4 2356{
c4028958
DH		 2357 struct rtl8169_private *tp =
2358 container_of(work, struct rtl8169_private, task.work);
2359 struct net_device *dev = tp->dev;
1da177e4 2360
eb2a021c
FR		 2361 rtnl_lock();
2362
1da177e4 2363 if (!netif_running(dev))
eb2a021c 2364 goto out_unlock;
1da177e4
LT		 2365
2366 rtl8169_wait_for_quiescence(dev);
2367
2368 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr);
2369 rtl8169_tx_clear(tp);
2370
2371 if (tp->dirty_rx == tp->cur_rx) {
2372 rtl8169_init_ring_indexes(tp);
07ce4064 2373 rtl_hw_start(dev);
1da177e4
LT		 2374 netif_wake_queue(dev);
2375 } else {
2376 if (net_ratelimit()) {
b57b7e5a
SH		 2377 struct rtl8169_private *tp = netdev_priv(dev);
2378
2379 if (netif_msg_intr(tp)) {
2380 printk(PFX KERN_EMERG
2381 "%s: Rx buffers shortage\n", dev->name);
2382 }
1da177e4
LT		 2383 }
2384 rtl8169_schedule_work(dev, rtl8169_reset_task);
2385 }
eb2a021c
FR		 2386
2387out_unlock:
2388 rtnl_unlock();
1da177e4
LT		 2389}
2390
2391static void rtl8169_tx_timeout(struct net_device *dev)
2392{
2393 struct rtl8169_private *tp = netdev_priv(dev);
2394
2395 rtl8169_hw_reset(tp->mmio_addr);
2396
2397 /* Let's wait a bit while any (async) irq lands on */
2398 rtl8169_schedule_work(dev, rtl8169_reset_task);
2399}
2400
2401static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2402 u32 opts1)
2403{
2404 struct skb_shared_info *info = skb_shinfo(skb);
2405 unsigned int cur_frag, entry;
2406 struct TxDesc *txd;
2407
2408 entry = tp->cur_tx;
2409 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2410 skb_frag_t *frag = info->frags + cur_frag;
2411 dma_addr_t mapping;
2412 u32 status, len;
2413 void *addr;
2414
2415 entry = (entry + 1) % NUM_TX_DESC;
2416
2417 txd = tp->TxDescArray + entry;
2418 len = frag->size;
2419 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2420 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2421
2422 /* anti gcc 2.95.3 bugware (sic) */
2423 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2424
2425 txd->opts1 = cpu_to_le32(status);
2426 txd->addr = cpu_to_le64(mapping);
2427
2428 tp->tx_skb[entry].len = len;
2429 }
2430
2431 if (cur_frag) {
2432 tp->tx_skb[entry].skb = skb;
2433 txd->opts1 |= cpu_to_le32(LastFrag);
2434 }
2435
2436 return cur_frag;
2437}
2438
2439static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2440{
2441 if (dev->features & NETIF_F_TSO) {
7967168c 2442 u32 mss = skb_shinfo(skb)->gso_size;
1da177e4
LT		 2443
2444 if (mss)
2445 return LargeSend | ((mss & MSSMask) << MSSShift);
2446 }
84fa7933 2447 if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 2448 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 2449
2450 if (ip->protocol == IPPROTO_TCP)
2451 return IPCS | TCPCS;
2452 else if (ip->protocol == IPPROTO_UDP)
2453 return IPCS | UDPCS;
2454 WARN_ON(1); /* we need a WARN() */
2455 }
2456 return 0;
2457}
2458
2459static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2460{
2461 struct rtl8169_private *tp = netdev_priv(dev);
2462 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2463 struct TxDesc *txd = tp->TxDescArray + entry;
2464 void __iomem *ioaddr = tp->mmio_addr;
2465 dma_addr_t mapping;
2466 u32 status, len;
2467 u32 opts1;
188f4af0 2468 int ret = NETDEV_TX_OK;
5b0384f4 2469
1da177e4 2470 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
b57b7e5a
SH		 2471 if (netif_msg_drv(tp)) {
2472 printk(KERN_ERR
2473 "%s: BUG! Tx Ring full when queue awake!\n",
2474 dev->name);
2475 }
1da177e4
LT		 2476 goto err_stop;
2477 }
2478
2479 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2480 goto err_stop;
2481
2482 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2483
2484 frags = rtl8169_xmit_frags(tp, skb, opts1);
2485 if (frags) {
2486 len = skb_headlen(skb);
2487 opts1 |= FirstFrag;
2488 } else {
2489 len = skb->len;
2490
2491 if (unlikely(len < ETH_ZLEN)) {
5b057c6b 2492 if (skb_padto(skb, ETH_ZLEN))
1da177e4
LT		 2493 goto err_update_stats;
2494 len = ETH_ZLEN;
2495 }
2496
2497 opts1 |= FirstFrag | LastFrag;
2498 tp->tx_skb[entry].skb = skb;
2499 }
2500
2501 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2502
2503 tp->tx_skb[entry].len = len;
2504 txd->addr = cpu_to_le64(mapping);
2505 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2506
2507 wmb();
2508
2509 /* anti gcc 2.95.3 bugware (sic) */
2510 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2511 txd->opts1 = cpu_to_le32(status);
2512
2513 dev->trans_start = jiffies;
2514
2515 tp->cur_tx += frags + 1;
2516
2517 smp_wmb();
2518
2519 RTL_W8(TxPoll, 0x40); /* set polling bit */
2520
2521 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2522 netif_stop_queue(dev);
2523 smp_rmb();
2524 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2525 netif_wake_queue(dev);
2526 }
2527
2528out:
2529 return ret;
2530
2531err_stop:
2532 netif_stop_queue(dev);
188f4af0 2533 ret = NETDEV_TX_BUSY;
1da177e4
LT		 2534err_update_stats:
2535 tp->stats.tx_dropped++;
2536 goto out;
2537}
2538
2539static void rtl8169_pcierr_interrupt(struct net_device *dev)
2540{
2541 struct rtl8169_private *tp = netdev_priv(dev);
2542 struct pci_dev *pdev = tp->pci_dev;
2543 void __iomem *ioaddr = tp->mmio_addr;
2544 u16 pci_status, pci_cmd;
2545
2546 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2547 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2548
b57b7e5a
SH		 2549 if (netif_msg_intr(tp)) {
2550 printk(KERN_ERR
2551 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2552 dev->name, pci_cmd, pci_status);
2553 }
1da177e4
LT		 2554
2555 /*
2556 * The recovery sequence below admits a very elaborated explanation:
2557 * - it seems to work;
d03902b8
FR		 2558 * - I did not see what else could be done;
2559 * - it makes iop3xx happy.
1da177e4
LT		 2560 *
2561 * Feel free to adjust to your needs.
2562 */
a27993f3 2563 if (pdev->broken_parity_status)
d03902b8
FR		 2564 pci_cmd &= ~PCI_COMMAND_PARITY;
2565 else
2566 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
2567
2568 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 2569
2570 pci_write_config_word(pdev, PCI_STATUS,
2571 pci_status & (PCI_STATUS_DETECTED_PARITY |
2572 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2573 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2574
2575 /* The infamous DAC f*ckup only happens at boot time */
2576 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
b57b7e5a
SH		 2577 if (netif_msg_intr(tp))
2578 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
1da177e4
LT		 2579 tp->cp_cmd &= ~PCIDAC;
2580 RTL_W16(CPlusCmd, tp->cp_cmd);
2581 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 2582 }
2583
2584 rtl8169_hw_reset(ioaddr);
d03902b8
FR		 2585
2586 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 2587}
2588
2589static void
2590rtl8169_tx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
2591 void __iomem *ioaddr)
2592{
2593 unsigned int dirty_tx, tx_left;
2594
2595 assert(dev != NULL);
2596 assert(tp != NULL);
2597 assert(ioaddr != NULL);
2598
2599 dirty_tx = tp->dirty_tx;
2600 smp_rmb();
2601 tx_left = tp->cur_tx - dirty_tx;
2602
2603 while (tx_left > 0) {
2604 unsigned int entry = dirty_tx % NUM_TX_DESC;
2605 struct ring_info *tx_skb = tp->tx_skb + entry;
2606 u32 len = tx_skb->len;
2607 u32 status;
2608
2609 rmb();
2610 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2611 if (status & DescOwn)
2612 break;
2613
2614 tp->stats.tx_bytes += len;
2615 tp->stats.tx_packets++;
2616
2617 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2618
2619 if (status & LastFrag) {
2620 dev_kfree_skb_irq(tx_skb->skb);
2621 tx_skb->skb = NULL;
2622 }
2623 dirty_tx++;
2624 tx_left--;
2625 }
2626
2627 if (tp->dirty_tx != dirty_tx) {
2628 tp->dirty_tx = dirty_tx;
2629 smp_wmb();
2630 if (netif_queue_stopped(dev) &&
2631 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2632 netif_wake_queue(dev);
2633 }
2634 }
2635}
2636
126fa4b9
FR		 2637static inline int rtl8169_fragmented_frame(u32 status)
2638{
2639 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2640}
2641
1da177e4
LT		 2642static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2643{
2644 u32 opts1 = le32_to_cpu(desc->opts1);
2645 u32 status = opts1 & RxProtoMask;
2646
2647 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2648 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2649 ((status == RxProtoIP) && !(opts1 & IPFail)))
2650 skb->ip_summed = CHECKSUM_UNNECESSARY;
2651 else
2652 skb->ip_summed = CHECKSUM_NONE;
2653}
2654
b449655f 2655static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff, int pkt_size,
86402234 2656 struct pci_dev *pdev, dma_addr_t addr)
1da177e4 2657{
b449655f
SH		 2658 struct sk_buff *skb;
2659 bool done = false;
1da177e4 2660
b449655f
SH		 2661 if (pkt_size >= rx_copybreak)
2662 goto out;
1da177e4 2663
86402234 2664 skb = dev_alloc_skb(pkt_size + NET_IP_ALIGN);
b449655f
SH		 2665 if (!skb)
2666 goto out;
2667
2668 pci_dma_sync_single_for_cpu(pdev, addr, pkt_size, PCI_DMA_FROMDEVICE);
86402234 2669 skb_reserve(skb, NET_IP_ALIGN);
b449655f
SH		 2670 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
2671 *sk_buff = skb;
2672 done = true;
2673out:
2674 return done;
1da177e4
LT		 2675}
2676
2677static int
2678rtl8169_rx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
2679 void __iomem *ioaddr)
2680{
2681 unsigned int cur_rx, rx_left;
2682 unsigned int delta, count;
2683
2684 assert(dev != NULL);
2685 assert(tp != NULL);
2686 assert(ioaddr != NULL);
2687
2688 cur_rx = tp->cur_rx;
2689 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
2690 rx_left = rtl8169_rx_quota(rx_left, (u32) dev->quota);
2691
4dcb7d33 2692 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 2693 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 2694 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 2695 u32 status;
2696
2697 rmb();
126fa4b9 2698 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 2699
2700 if (status & DescOwn)
2701 break;
4dcb7d33 2702 if (unlikely(status & RxRES)) {
b57b7e5a
SH		 2703 if (netif_msg_rx_err(tp)) {
2704 printk(KERN_INFO
2705 "%s: Rx ERROR. status = %08x\n",
2706 dev->name, status);
2707 }
1da177e4
LT		 2708 tp->stats.rx_errors++;
2709 if (status & (RxRWT | RxRUNT))
2710 tp->stats.rx_length_errors++;
2711 if (status & RxCRC)
2712 tp->stats.rx_crc_errors++;
9dccf611
FR		 2713 if (status & RxFOVF) {
2714 rtl8169_schedule_work(dev, rtl8169_reset_task);
2715 tp->stats.rx_fifo_errors++;
2716 }
126fa4b9 2717 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
1da177e4 2718 } else {
1da177e4 2719 struct sk_buff *skb = tp->Rx_skbuff[entry];
b449655f 2720 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 2721 int pkt_size = (status & 0x00001FFF) - 4;
b449655f 2722 struct pci_dev *pdev = tp->pci_dev;
1da177e4 2723
126fa4b9
FR		 2724 /*
2725 * The driver does not support incoming fragmented
2726 * frames. They are seen as a symptom of over-mtu
2727 * sized frames.
2728 */
2729 if (unlikely(rtl8169_fragmented_frame(status))) {
2730 tp->stats.rx_dropped++;
2731 tp->stats.rx_length_errors++;
2732 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4dcb7d33 2733 continue;
126fa4b9
FR		 2734 }
2735
1da177e4 2736 rtl8169_rx_csum(skb, desc);
bcf0bf90 2737
86402234 2738 if (rtl8169_try_rx_copy(&skb, pkt_size, pdev, addr)) {
b449655f
SH		 2739 pci_dma_sync_single_for_device(pdev, addr,
2740 pkt_size, PCI_DMA_FROMDEVICE);
2741 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2742 } else {
2743 pci_unmap_single(pdev, addr, pkt_size,
2744 PCI_DMA_FROMDEVICE);
1da177e4
LT		 2745 tp->Rx_skbuff[entry] = NULL;
2746 }
2747
1da177e4
LT		 2748 skb_put(skb, pkt_size);
2749 skb->protocol = eth_type_trans(skb, dev);
2750
2751 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
2752 rtl8169_rx_skb(skb);
2753
2754 dev->last_rx = jiffies;
2755 tp->stats.rx_bytes += pkt_size;
2756 tp->stats.rx_packets++;
2757 }
6dccd16b
FR		 2758
2759 /* Work around for AMD plateform. */
2760 if ((desc->opts2 & 0xfffe000) &&
2761 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
2762 desc->opts2 = 0;
2763 cur_rx++;
2764 }
1da177e4
LT		 2765 }
2766
2767 count = cur_rx - tp->cur_rx;
2768 tp->cur_rx = cur_rx;
2769
2770 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
b57b7e5a 2771 if (!delta && count && netif_msg_intr(tp))
1da177e4
LT		 2772 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
2773 tp->dirty_rx += delta;
2774
2775 /*
2776 * FIXME: until there is periodic timer to try and refill the ring,
2777 * a temporary shortage may definitely kill the Rx process.
2778 * - disable the asic to try and avoid an overflow and kick it again
2779 * after refill ?
2780 * - how do others driver handle this condition (Uh oh...).
2781 */
b57b7e5a 2782 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
1da177e4
LT		 2783 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
2784
2785 return count;
2786}
2787
2788/* The interrupt handler does all of the Rx thread work and cleans up after the Tx thread. */
2789static irqreturn_t
7d12e780 2790rtl8169_interrupt(int irq, void *dev_instance)
1da177e4
LT		 2791{
2792 struct net_device *dev = (struct net_device *) dev_instance;
2793 struct rtl8169_private *tp = netdev_priv(dev);
2794 int boguscnt = max_interrupt_work;
2795 void __iomem *ioaddr = tp->mmio_addr;
2796 int status;
2797 int handled = 0;
2798
2799 do {
2800 status = RTL_R16(IntrStatus);
2801
2802 /* hotplug/major error/no more work/shared irq */
2803 if ((status == 0xFFFF) || !status)
2804 break;
2805
2806 handled = 1;
2807
2808 if (unlikely(!netif_running(dev))) {
2809 rtl8169_asic_down(ioaddr);
2810 goto out;
2811 }
2812
2813 status &= tp->intr_mask;
2814 RTL_W16(IntrStatus,
2815 (status & RxFIFOOver) ? (status | RxOverflow) : status);
2816
0e485150
FR		 2817 if (!(status & tp->intr_event))
2818 break;
2819
2820 /* Work around for rx fifo overflow */
2821 if (unlikely(status & RxFIFOOver) &&
2822 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
2823 netif_stop_queue(dev);
2824 rtl8169_tx_timeout(dev);
1da177e4 2825 break;
0e485150 2826 }
1da177e4
LT		 2827
2828 if (unlikely(status & SYSErr)) {
2829 rtl8169_pcierr_interrupt(dev);
2830 break;
2831 }
2832
2833 if (status & LinkChg)
2834 rtl8169_check_link_status(dev, tp, ioaddr);
2835
2836#ifdef CONFIG_R8169_NAPI
0e485150
FR		 2837 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
2838 tp->intr_mask = ~tp->napi_event;
1da177e4
LT		 2839
2840 if (likely(netif_rx_schedule_prep(dev)))
2841 __netif_rx_schedule(dev);
b57b7e5a 2842 else if (netif_msg_intr(tp)) {
1da177e4 2843 printk(KERN_INFO "%s: interrupt %04x taken in poll\n",
5b0384f4 2844 dev->name, status);
1da177e4
LT		 2845 }
2846 break;
2847#else
2848 /* Rx interrupt */
2849 if (status & (RxOK | RxOverflow | RxFIFOOver)) {
2850 rtl8169_rx_interrupt(dev, tp, ioaddr);
2851 }
2852 /* Tx interrupt */
2853 if (status & (TxOK | TxErr))
2854 rtl8169_tx_interrupt(dev, tp, ioaddr);
2855#endif
2856
2857 boguscnt--;
2858 } while (boguscnt > 0);
2859
2860 if (boguscnt <= 0) {
7c8b2eb4 2861 if (netif_msg_intr(tp) && net_ratelimit() ) {
b57b7e5a
SH		 2862 printk(KERN_WARNING
2863 "%s: Too much work at interrupt!\n", dev->name);
2864 }
1da177e4
LT		 2865 /* Clear all interrupt sources. */
2866 RTL_W16(IntrStatus, 0xffff);
2867 }
2868out:
2869 return IRQ_RETVAL(handled);
2870}
2871
2872#ifdef CONFIG_R8169_NAPI
2873static int rtl8169_poll(struct net_device *dev, int *budget)
2874{
2875 unsigned int work_done, work_to_do = min(*budget, dev->quota);
2876 struct rtl8169_private *tp = netdev_priv(dev);
2877 void __iomem *ioaddr = tp->mmio_addr;
2878
2879 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr);
2880 rtl8169_tx_interrupt(dev, tp, ioaddr);
2881
2882 *budget -= work_done;
2883 dev->quota -= work_done;
2884
2885 if (work_done < work_to_do) {
2886 netif_rx_complete(dev);
2887 tp->intr_mask = 0xffff;
2888 /*
2889 * 20040426: the barrier is not strictly required but the
2890 * behavior of the irq handler could be less predictable
2891 * without it. Btw, the lack of flush for the posted pci
2892 * write is safe - FR
2893 */
2894 smp_wmb();
0e485150 2895 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 2896 }
2897
2898 return (work_done >= work_to_do);
2899}
2900#endif
2901
2902static void rtl8169_down(struct net_device *dev)
2903{
2904 struct rtl8169_private *tp = netdev_priv(dev);
2905 void __iomem *ioaddr = tp->mmio_addr;
2906 unsigned int poll_locked = 0;
733b736c 2907 unsigned int intrmask;
1da177e4
LT		 2908
2909 rtl8169_delete_timer(dev);
2910
2911 netif_stop_queue(dev);
2912
1da177e4
LT		 2913core_down:
2914 spin_lock_irq(&tp->lock);
2915
2916 rtl8169_asic_down(ioaddr);
2917
2918 /* Update the error counts. */
2919 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2920 RTL_W32(RxMissed, 0);
2921
2922 spin_unlock_irq(&tp->lock);
2923
2924 synchronize_irq(dev->irq);
2925
2926 if (!poll_locked) {
2927 netif_poll_disable(dev);
2928 poll_locked++;
2929 }
2930
2931 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 2932 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4
LT		 2933
2934 /*
2935 * And now for the 50k$ question: are IRQ disabled or not ?
2936 *
2937 * Two paths lead here:
2938 * 1) dev->close
2939 * -> netif_running() is available to sync the current code and the
2940 * IRQ handler. See rtl8169_interrupt for details.
2941 * 2) dev->change_mtu
2942 * -> rtl8169_poll can not be issued again and re-enable the
2943 * interruptions. Let's simply issue the IRQ down sequence again.
733b736c
AP		 2944 *
2945 * No loop if hotpluged or major error (0xffff).
1da177e4 2946 */
733b736c
AP		 2947 intrmask = RTL_R16(IntrMask);
2948 if (intrmask && (intrmask != 0xffff))
1da177e4
LT		 2949 goto core_down;
2950
2951 rtl8169_tx_clear(tp);
2952
2953 rtl8169_rx_clear(tp);
2954}
2955
2956static int rtl8169_close(struct net_device *dev)
2957{
2958 struct rtl8169_private *tp = netdev_priv(dev);
2959 struct pci_dev *pdev = tp->pci_dev;
2960
2961 rtl8169_down(dev);
2962
2963 free_irq(dev->irq, dev);
2964
2965 netif_poll_enable(dev);
2966
2967 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2968 tp->RxPhyAddr);
2969 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2970 tp->TxPhyAddr);
2971 tp->TxDescArray = NULL;
2972 tp->RxDescArray = NULL;
2973
2974 return 0;
2975}
2976
07ce4064 2977static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 2978{
2979 struct rtl8169_private *tp = netdev_priv(dev);
2980 void __iomem *ioaddr = tp->mmio_addr;
2981 unsigned long flags;
2982 u32 mc_filter[2]; /* Multicast hash filter */
2983 int i, rx_mode;
2984 u32 tmp = 0;
2985
2986 if (dev->flags & IFF_PROMISC) {
2987 /* Unconditionally log net taps. */
b57b7e5a
SH		 2988 if (netif_msg_link(tp)) {
2989 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2990 dev->name);
2991 }
1da177e4
LT		 2992 rx_mode =
2993 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2994 AcceptAllPhys;
2995 mc_filter[1] = mc_filter[0] = 0xffffffff;
2996 } else if ((dev->mc_count > multicast_filter_limit)
2997 || (dev->flags & IFF_ALLMULTI)) {
2998 /* Too many to filter perfectly -- accept all multicasts. */
2999 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
3000 mc_filter[1] = mc_filter[0] = 0xffffffff;
3001 } else {
3002 struct dev_mc_list *mclist;
3003 rx_mode = AcceptBroadcast | AcceptMyPhys;
3004 mc_filter[1] = mc_filter[0] = 0;
3005 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3006 i++, mclist = mclist->next) {
3007 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
3008 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
3009 rx_mode |= AcceptMulticast;
3010 }
3011 }
3012
3013 spin_lock_irqsave(&tp->lock, flags);
3014
3015 tmp = rtl8169_rx_config | rx_mode |
3016 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3017
bcf0bf90
FR		 3018 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
3019 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
3020 (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
3021 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
3022 (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
3023 mc_filter[0] = 0xffffffff;
3024 mc_filter[1] = 0xffffffff;
3025 }
3026
1da177e4
LT		 3027 RTL_W32(RxConfig, tmp);
3028 RTL_W32(MAR0 + 0, mc_filter[0]);
3029 RTL_W32(MAR0 + 4, mc_filter[1]);
3030
3031 spin_unlock_irqrestore(&tp->lock, flags);
3032}
3033
3034/**
3035 * rtl8169_get_stats - Get rtl8169 read/write statistics
3036 * @dev: The Ethernet Device to get statistics for
3037 *
3038 * Get TX/RX statistics for rtl8169
3039 */
3040static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3041{
3042 struct rtl8169_private *tp = netdev_priv(dev);
3043 void __iomem *ioaddr = tp->mmio_addr;
3044 unsigned long flags;
3045
3046 if (netif_running(dev)) {
3047 spin_lock_irqsave(&tp->lock, flags);
3048 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
3049 RTL_W32(RxMissed, 0);
3050 spin_unlock_irqrestore(&tp->lock, flags);
3051 }
5b0384f4 3052
1da177e4
LT		 3053 return &tp->stats;
3054}
3055
5d06a99f
FR		 3056#ifdef CONFIG_PM
3057
3058static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
3059{
3060 struct net_device *dev = pci_get_drvdata(pdev);
3061 struct rtl8169_private *tp = netdev_priv(dev);
3062 void __iomem *ioaddr = tp->mmio_addr;
3063
3064 if (!netif_running(dev))
1371fa6d 3065 goto out_pci_suspend;
5d06a99f
FR		 3066
3067 netif_device_detach(dev);
3068 netif_stop_queue(dev);
3069
3070 spin_lock_irq(&tp->lock);
3071
3072 rtl8169_asic_down(ioaddr);
3073
3074 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
3075 RTL_W32(RxMissed, 0);
3076
3077 spin_unlock_irq(&tp->lock);
3078
1371fa6d 3079out_pci_suspend:
5d06a99f 3080 pci_save_state(pdev);
61a4dcc2 3081 pci_enable_wake(pdev, pci_choose_state(pdev, state), tp->wol_enabled);
5d06a99f 3082 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1371fa6d 3083
5d06a99f
FR		 3084 return 0;
3085}
3086
3087static int rtl8169_resume(struct pci_dev *pdev)
3088{
3089 struct net_device *dev = pci_get_drvdata(pdev);
3090
1371fa6d
FR		 3091 pci_set_power_state(pdev, PCI_D0);
3092 pci_restore_state(pdev);
3093 pci_enable_wake(pdev, PCI_D0, 0);
3094
5d06a99f
FR		 3095 if (!netif_running(dev))
3096 goto out;
3097
3098 netif_device_attach(dev);
3099
5d06a99f
FR		 3100 rtl8169_schedule_work(dev, rtl8169_reset_task);
3101out:
3102 return 0;
3103}
3104
3105#endif /* CONFIG_PM */
3106
1da177e4
LT		 3107static struct pci_driver rtl8169_pci_driver = {
3108 .name = MODULENAME,
3109 .id_table = rtl8169_pci_tbl,
3110 .probe = rtl8169_init_one,
3111 .remove = __devexit_p(rtl8169_remove_one),
3112#ifdef CONFIG_PM
3113 .suspend = rtl8169_suspend,
3114 .resume = rtl8169_resume,
3115#endif
3116};
3117
3118static int __init
3119rtl8169_init_module(void)
3120{
29917620 3121 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 3122}
3123
3124static void __exit
3125rtl8169_cleanup_module(void)
3126{
3127 pci_unregister_driver(&rtl8169_pci_driver);
3128}
3129
3130module_init(rtl8169_init_module);
3131module_exit(rtl8169_cleanup_module);
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