[linux-2.6-block.git] / drivers / net / phy / at803x.c

/*
 * drivers/net/phy/at803x.c
 *
 * Driver for Atheros 803x PHY
 *
 * Author: Matus Ujhelyi <ujhelyi.m@gmail.com>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <linux/phy.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/of_gpio.h>
#include <linux/gpio/consumer.h>

#define AT803X_INTR_ENABLE			0x12
#define AT803X_INTR_STATUS			0x13
#define AT803X_SMART_SPEED			0x14
#define AT803X_LED_CONTROL			0x18
#define AT803X_WOL_ENABLE			0x01
#define AT803X_DEVICE_ADDR			0x03
#define AT803X_LOC_MAC_ADDR_0_15_OFFSET		0x804C
#define AT803X_LOC_MAC_ADDR_16_31_OFFSET	0x804B
#define AT803X_LOC_MAC_ADDR_32_47_OFFSET	0x804A
#define AT803X_MMD_ACCESS_CONTROL		0x0D
#define AT803X_MMD_ACCESS_CONTROL_DATA		0x0E
#define AT803X_FUNC_DATA			0x4003
#define AT803X_INER				0x0012
#define AT803X_INER_INIT			0xec00
#define AT803X_INSR				0x0013
#define AT803X_DEBUG_ADDR			0x1D
#define AT803X_DEBUG_DATA			0x1E
#define AT803X_DEBUG_SYSTEM_MODE_CTRL		0x05
#define AT803X_DEBUG_RGMII_TX_CLK_DLY		BIT(8)

#define ATH8030_PHY_ID 0x004dd076
#define ATH8031_PHY_ID 0x004dd074
#define ATH8035_PHY_ID 0x004dd072

MODULE_DESCRIPTION("Atheros 803x PHY driver");
MODULE_AUTHOR("Matus Ujhelyi");
MODULE_LICENSE("GPL");

struct at803x_priv {
	bool phy_reset:1;
	struct gpio_desc *gpiod_reset;
};

struct at803x_context {
	u16 bmcr;
	u16 advertise;
	u16 control1000;
	u16 int_enable;
	u16 smart_speed;
	u16 led_control;
};

/* save relevant PHY registers to private copy */
static void at803x_context_save(struct phy_device *phydev,
				struct at803x_context *context)
{
	context->bmcr = phy_read(phydev, MII_BMCR);
	context->advertise = phy_read(phydev, MII_ADVERTISE);
	context->control1000 = phy_read(phydev, MII_CTRL1000);
	context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE);
	context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED);
	context->led_control = phy_read(phydev, AT803X_LED_CONTROL);
}

/* restore relevant PHY registers from private copy */
static void at803x_context_restore(struct phy_device *phydev,
				   const struct at803x_context *context)
{
	phy_write(phydev, MII_BMCR, context->bmcr);
	phy_write(phydev, MII_ADVERTISE, context->advertise);
	phy_write(phydev, MII_CTRL1000, context->control1000);
	phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable);
	phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed);
	phy_write(phydev, AT803X_LED_CONTROL, context->led_control);
}

static int at803x_set_wol(struct phy_device *phydev,
			  struct ethtool_wolinfo *wol)
{
	struct net_device *ndev = phydev->attached_dev;
	const u8 *mac;
	int ret;
	u32 value;
	unsigned int i, offsets[] = {
		AT803X_LOC_MAC_ADDR_32_47_OFFSET,
		AT803X_LOC_MAC_ADDR_16_31_OFFSET,
		AT803X_LOC_MAC_ADDR_0_15_OFFSET,
	};

	if (!ndev)
		return -ENODEV;

	if (wol->wolopts & WAKE_MAGIC) {
		mac = (const u8 *) ndev->dev_addr;

		if (!is_valid_ether_addr(mac))
			return -EFAULT;

		for (i = 0; i < 3; i++) {
			phy_write(phydev, AT803X_MMD_ACCESS_CONTROL,
				  AT803X_DEVICE_ADDR);
			phy_write(phydev, AT803X_MMD_ACCESS_CONTROL_DATA,
				  offsets[i]);
			phy_write(phydev, AT803X_MMD_ACCESS_CONTROL,
				  AT803X_FUNC_DATA);
			phy_write(phydev, AT803X_MMD_ACCESS_CONTROL_DATA,
				  mac[(i * 2) + 1] | (mac[(i * 2)] << 8));
		}

		value = phy_read(phydev, AT803X_INTR_ENABLE);
		value |= AT803X_WOL_ENABLE;
		ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
		if (ret)
			return ret;
		value = phy_read(phydev, AT803X_INTR_STATUS);
	} else {
		value = phy_read(phydev, AT803X_INTR_ENABLE);
		value &= (~AT803X_WOL_ENABLE);
		ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
		if (ret)
			return ret;
		value = phy_read(phydev, AT803X_INTR_STATUS);
	}

	return ret;
}

static void at803x_get_wol(struct phy_device *phydev,
			   struct ethtool_wolinfo *wol)
{
	u32 value;

	wol->supported = WAKE_MAGIC;
	wol->wolopts = 0;

	value = phy_read(phydev, AT803X_INTR_ENABLE);
	if (value & AT803X_WOL_ENABLE)
		wol->wolopts |= WAKE_MAGIC;
}

static int at803x_suspend(struct phy_device *phydev)
{
	int value;
	int wol_enabled;

	mutex_lock(&phydev->lock);

	value = phy_read(phydev, AT803X_INTR_ENABLE);
	wol_enabled = value & AT803X_WOL_ENABLE;

	value = phy_read(phydev, MII_BMCR);

	if (wol_enabled)
		value |= BMCR_ISOLATE;
	else
		value |= BMCR_PDOWN;

	phy_write(phydev, MII_BMCR, value);

	mutex_unlock(&phydev->lock);

	return 0;
}

static int at803x_resume(struct phy_device *phydev)
{
	int value;

	mutex_lock(&phydev->lock);

	value = phy_read(phydev, MII_BMCR);
	value &= ~(BMCR_PDOWN | BMCR_ISOLATE);
	phy_write(phydev, MII_BMCR, value);

	mutex_unlock(&phydev->lock);

	return 0;
}

static int at803x_probe(struct phy_device *phydev)
{
	struct device *dev = &phydev->dev;
	struct at803x_priv *priv;
	struct gpio_desc *gpiod_reset;

	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	gpiod_reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
	if (IS_ERR(gpiod_reset))
		return PTR_ERR(gpiod_reset);

	priv->gpiod_reset = gpiod_reset;

	phydev->priv = priv;

	return 0;
}

static int at803x_config_init(struct phy_device *phydev)
{
	int ret;

	ret = genphy_config_init(phydev);
	if (ret < 0)
		return ret;

	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
		ret = phy_write(phydev, AT803X_DEBUG_ADDR,
				AT803X_DEBUG_SYSTEM_MODE_CTRL);
		if (ret)
			return ret;
		ret = phy_write(phydev, AT803X_DEBUG_DATA,
				AT803X_DEBUG_RGMII_TX_CLK_DLY);
		if (ret)
			return ret;
	}

	return 0;
}

static int at803x_ack_interrupt(struct phy_device *phydev)
{
	int err;

	err = phy_read(phydev, AT803X_INSR);

	return (err < 0) ? err : 0;
}

static int at803x_config_intr(struct phy_device *phydev)
{
	int err;
	int value;

	value = phy_read(phydev, AT803X_INER);

	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
		err = phy_write(phydev, AT803X_INER,
				value | AT803X_INER_INIT);
	else
		err = phy_write(phydev, AT803X_INER, 0);

	return err;
}

static void at803x_link_change_notify(struct phy_device *phydev)
{
	struct at803x_priv *priv = phydev->priv;

	/*
	 * Conduct a hardware reset for AT8030 every time a link loss is
	 * signalled. This is necessary to circumvent a hardware bug that
	 * occurs when the cable is unplugged while TX packets are pending
	 * in the FIFO. In such cases, the FIFO enters an error mode it
	 * cannot recover from by software.
	 */
	if (phydev->drv->phy_id == ATH8030_PHY_ID) {
		if (phydev->state == PHY_NOLINK) {
			if (priv->gpiod_reset && !priv->phy_reset) {
				struct at803x_context context;

				at803x_context_save(phydev, &context);

				gpiod_set_value(priv->gpiod_reset, 0);
				msleep(1);
				gpiod_set_value(priv->gpiod_reset, 1);
				msleep(1);

				at803x_context_restore(phydev, &context);

				dev_dbg(&phydev->dev, "%s(): phy was reset\n",
					__func__);
				priv->phy_reset = true;
			}
		} else {
			priv->phy_reset = false;
		}
	}
}

static struct phy_driver at803x_driver[] = {
{
	/* ATHEROS 8035 */
	.phy_id			= ATH8035_PHY_ID,
	.name			= "Atheros 8035 ethernet",
	.phy_id_mask		= 0xffffffef,
	.probe			= at803x_probe,
	.config_init		= at803x_config_init,
	.link_change_notify	= at803x_link_change_notify,
	.set_wol		= at803x_set_wol,
	.get_wol		= at803x_get_wol,
	.suspend		= at803x_suspend,
	.resume			= at803x_resume,
	.features		= PHY_GBIT_FEATURES,
	.flags			= PHY_HAS_INTERRUPT,
	.config_aneg		= genphy_config_aneg,
	.read_status		= genphy_read_status,
	.ack_interrupt		= at803x_ack_interrupt,
	.config_intr		= at803x_config_intr,
	.driver			= {
		.owner = THIS_MODULE,
	},
}, {
	/* ATHEROS 8030 */
	.phy_id			= ATH8030_PHY_ID,
	.name			= "Atheros 8030 ethernet",
	.phy_id_mask		= 0xffffffef,
	.probe			= at803x_probe,
	.config_init		= at803x_config_init,
	.link_change_notify	= at803x_link_change_notify,
	.set_wol		= at803x_set_wol,
	.get_wol		= at803x_get_wol,
	.suspend		= at803x_suspend,
	.resume			= at803x_resume,
	.features		= PHY_GBIT_FEATURES,
	.flags			= PHY_HAS_INTERRUPT,
	.config_aneg		= genphy_config_aneg,
	.read_status		= genphy_read_status,
	.ack_interrupt		= at803x_ack_interrupt,
	.config_intr		= at803x_config_intr,
	.driver			= {
		.owner = THIS_MODULE,
	},
}, {
	/* ATHEROS 8031 */
	.phy_id			= ATH8031_PHY_ID,
	.name			= "Atheros 8031 ethernet",
	.phy_id_mask		= 0xffffffef,
	.probe			= at803x_probe,
	.config_init		= at803x_config_init,
	.link_change_notify	= at803x_link_change_notify,
	.set_wol		= at803x_set_wol,
	.get_wol		= at803x_get_wol,
	.suspend		= at803x_suspend,
	.resume			= at803x_resume,
	.features		= PHY_GBIT_FEATURES,
	.flags			= PHY_HAS_INTERRUPT,
	.config_aneg		= genphy_config_aneg,
	.read_status		= genphy_read_status,
	.ack_interrupt		= &at803x_ack_interrupt,
	.config_intr		= &at803x_config_intr,
	.driver			= {
		.owner = THIS_MODULE,
	},
} };

module_phy_driver(at803x_driver);

static struct mdio_device_id __maybe_unused atheros_tbl[] = {
	{ ATH8030_PHY_ID, 0xffffffef },
	{ ATH8031_PHY_ID, 0xffffffef },
	{ ATH8035_PHY_ID, 0xffffffef },
	{ }
};

MODULE_DEVICE_TABLE(mdio, atheros_tbl);
Commit	Line	Data
0ca7111a MU	1	/*
	2	* drivers/net/phy/at803x.c
	3	*
	4	* Driver for Atheros 803x PHY
	5	*
	6	* Author: Matus Ujhelyi <ujhelyi.m@gmail.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
	12	*/
	13
	14	#include <linux/phy.h>
	15	#include <linux/module.h>
	16	#include <linux/string.h>
	17	#include <linux/netdevice.h>
	18	#include <linux/etherdevice.h>
13a56b44 DM	19	#include <linux/of_gpio.h>
13a56b44 DM	20	#include <linux/gpio/consumer.h>
0ca7111a MU	21
	22	#define AT803X_INTR_ENABLE 0x12
	23	#define AT803X_INTR_STATUS 0x13
13a56b44 DM	24	#define AT803X_SMART_SPEED 0x14
13a56b44 DM	25	#define AT803X_LED_CONTROL 0x18
0ca7111a MU	26	#define AT803X_WOL_ENABLE 0x01
	27	#define AT803X_DEVICE_ADDR 0x03
	28	#define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C
	29	#define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B
	30	#define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A
	31	#define AT803X_MMD_ACCESS_CONTROL 0x0D
	32	#define AT803X_MMD_ACCESS_CONTROL_DATA 0x0E
	33	#define AT803X_FUNC_DATA 0x4003
77a99394 ZQ	34	#define AT803X_INER 0x0012
	35	#define AT803X_INER_INIT 0xec00
	36	#define AT803X_INSR 0x0013
1ca6d1b1 M	37	#define AT803X_DEBUG_ADDR 0x1D
	38	#define AT803X_DEBUG_DATA 0x1E
	39	#define AT803X_DEBUG_SYSTEM_MODE_CTRL 0x05
	40	#define AT803X_DEBUG_RGMII_TX_CLK_DLY BIT(8)
0ca7111a	41
bd8ca17f DM	42	#define ATH8030_PHY_ID 0x004dd076
	43	#define ATH8031_PHY_ID 0x004dd074
	44	#define ATH8035_PHY_ID 0x004dd072
	45
0ca7111a MU	46	MODULE_DESCRIPTION("Atheros 803x PHY driver");
	47	MODULE_AUTHOR("Matus Ujhelyi");
	48	MODULE_LICENSE("GPL");
	49
13a56b44 DM	50	struct at803x_priv {
	51	bool phy_reset:1;
	52	struct gpio_desc *gpiod_reset;
	53	};
	54
	55	struct at803x_context {
	56	u16 bmcr;
	57	u16 advertise;
	58	u16 control1000;
	59	u16 int_enable;
	60	u16 smart_speed;
	61	u16 led_control;
	62	};
	63
	64	/* save relevant PHY registers to private copy */
	65	static void at803x_context_save(struct phy_device *phydev,
	66	struct at803x_context *context)
	67	{
	68	context->bmcr = phy_read(phydev, MII_BMCR);
	69	context->advertise = phy_read(phydev, MII_ADVERTISE);
	70	context->control1000 = phy_read(phydev, MII_CTRL1000);
	71	context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE);
	72	context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED);
	73	context->led_control = phy_read(phydev, AT803X_LED_CONTROL);
	74	}
	75
	76	/* restore relevant PHY registers from private copy */
	77	static void at803x_context_restore(struct phy_device *phydev,
	78	const struct at803x_context *context)
	79	{
	80	phy_write(phydev, MII_BMCR, context->bmcr);
	81	phy_write(phydev, MII_ADVERTISE, context->advertise);
	82	phy_write(phydev, MII_CTRL1000, context->control1000);
	83	phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable);
	84	phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed);
	85	phy_write(phydev, AT803X_LED_CONTROL, context->led_control);
	86	}
	87
ea13c9ee M	88	static int at803x_set_wol(struct phy_device *phydev,
ea13c9ee M	89	struct ethtool_wolinfo *wol)
0ca7111a MU	90	{
	91	struct net_device *ndev = phydev->attached_dev;
	92	const u8 *mac;
ea13c9ee M	93	int ret;
ea13c9ee M	94	u32 value;
0ca7111a MU	95	unsigned int i, offsets[] = {
	96	AT803X_LOC_MAC_ADDR_32_47_OFFSET,
	97	AT803X_LOC_MAC_ADDR_16_31_OFFSET,
	98	AT803X_LOC_MAC_ADDR_0_15_OFFSET,
	99	};
	100
	101	if (!ndev)
ea13c9ee	102	return -ENODEV;
0ca7111a	103
ea13c9ee M	104	if (wol->wolopts & WAKE_MAGIC) {
ea13c9ee M	105	mac = (const u8 *) ndev->dev_addr;
0ca7111a	106
ea13c9ee M	107	if (!is_valid_ether_addr(mac))
ea13c9ee M	108	return -EFAULT;
0ca7111a	109
ea13c9ee M	110	for (i = 0; i < 3; i++) {
ea13c9ee M	111	phy_write(phydev, AT803X_MMD_ACCESS_CONTROL,
0ca7111a	112	AT803X_DEVICE_ADDR);
ea13c9ee	113	phy_write(phydev, AT803X_MMD_ACCESS_CONTROL_DATA,
0ca7111a	114	offsets[i]);
ea13c9ee	115	phy_write(phydev, AT803X_MMD_ACCESS_CONTROL,
0ca7111a	116	AT803X_FUNC_DATA);
ea13c9ee	117	phy_write(phydev, AT803X_MMD_ACCESS_CONTROL_DATA,
0ca7111a	118	mac[(i * 2) + 1] \| (mac[(i * 2)] << 8));
ea13c9ee M	119	}
	120
	121	value = phy_read(phydev, AT803X_INTR_ENABLE);
	122	value \|= AT803X_WOL_ENABLE;
	123	ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
	124	if (ret)
	125	return ret;
	126	value = phy_read(phydev, AT803X_INTR_STATUS);
	127	} else {
	128	value = phy_read(phydev, AT803X_INTR_ENABLE);
	129	value &= (~AT803X_WOL_ENABLE);
	130	ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
	131	if (ret)
	132	return ret;
	133	value = phy_read(phydev, AT803X_INTR_STATUS);
0ca7111a	134	}
ea13c9ee M	135
	136	return ret;
	137	}
	138
	139	static void at803x_get_wol(struct phy_device *phydev,
	140	struct ethtool_wolinfo *wol)
	141	{
	142	u32 value;
	143
	144	wol->supported = WAKE_MAGIC;
	145	wol->wolopts = 0;
	146
	147	value = phy_read(phydev, AT803X_INTR_ENABLE);
	148	if (value & AT803X_WOL_ENABLE)
	149	wol->wolopts \|= WAKE_MAGIC;
0ca7111a MU	150	}
0ca7111a MU	151
6229ed1f DM	152	static int at803x_suspend(struct phy_device *phydev)
	153	{
	154	int value;
	155	int wol_enabled;
	156
	157	mutex_lock(&phydev->lock);
	158
	159	value = phy_read(phydev, AT803X_INTR_ENABLE);
	160	wol_enabled = value & AT803X_WOL_ENABLE;
	161
	162	value = phy_read(phydev, MII_BMCR);
	163
	164	if (wol_enabled)
	165	value \|= BMCR_ISOLATE;
	166	else
	167	value \|= BMCR_PDOWN;
	168
	169	phy_write(phydev, MII_BMCR, value);
	170
	171	mutex_unlock(&phydev->lock);
	172
	173	return 0;
	174	}
	175
	176	static int at803x_resume(struct phy_device *phydev)
	177	{
	178	int value;
	179
	180	mutex_lock(&phydev->lock);
	181
	182	value = phy_read(phydev, MII_BMCR);
	183	value &= ~(BMCR_PDOWN \| BMCR_ISOLATE);
	184	phy_write(phydev, MII_BMCR, value);
	185
	186	mutex_unlock(&phydev->lock);
	187
	188	return 0;
	189	}
	190
13a56b44 DM	191	static int at803x_probe(struct phy_device *phydev)
	192	{
	193	struct device *dev = &phydev->dev;
	194	struct at803x_priv *priv;
687908c2	195	struct gpio_desc *gpiod_reset;
13a56b44	196
8f2877ca	197	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
13a56b44 DM	198	if (!priv)
	199	return -ENOMEM;
	200
687908c2 UKK	201	gpiod_reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
	202	if (IS_ERR(gpiod_reset))
	203	return PTR_ERR(gpiod_reset);
	204
	205	priv->gpiod_reset = gpiod_reset;
13a56b44 DM	206
	207	phydev->priv = priv;
	208
	209	return 0;
	210	}
	211
0ca7111a MU	212	static int at803x_config_init(struct phy_device *phydev)
0ca7111a MU	213	{
1ca6d1b1	214	int ret;
0ca7111a	215
6ff01dbb DM	216	ret = genphy_config_init(phydev);
	217	if (ret < 0)
	218	return ret;
0ca7111a	219
1ca6d1b1 M	220	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
	221	ret = phy_write(phydev, AT803X_DEBUG_ADDR,
	222	AT803X_DEBUG_SYSTEM_MODE_CTRL);
	223	if (ret)
	224	return ret;
	225	ret = phy_write(phydev, AT803X_DEBUG_DATA,
	226	AT803X_DEBUG_RGMII_TX_CLK_DLY);
	227	if (ret)
	228	return ret;
	229	}
	230
0ca7111a MU	231	return 0;
	232	}
	233
77a99394 ZQ	234	static int at803x_ack_interrupt(struct phy_device *phydev)
	235	{
	236	int err;
	237
	238	err = phy_read(phydev, AT803X_INSR);
	239
	240	return (err < 0) ? err : 0;
	241	}
	242
	243	static int at803x_config_intr(struct phy_device *phydev)
	244	{
	245	int err;
	246	int value;
	247
	248	value = phy_read(phydev, AT803X_INER);
	249
	250	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
	251	err = phy_write(phydev, AT803X_INER,
	252	value \| AT803X_INER_INIT);
	253	else
	254	err = phy_write(phydev, AT803X_INER, 0);
	255
	256	return err;
	257	}
	258
13a56b44 DM	259	static void at803x_link_change_notify(struct phy_device *phydev)
	260	{
	261	struct at803x_priv *priv = phydev->priv;
	262
	263	/*
	264	* Conduct a hardware reset for AT8030 every time a link loss is
	265	* signalled. This is necessary to circumvent a hardware bug that
	266	* occurs when the cable is unplugged while TX packets are pending
	267	* in the FIFO. In such cases, the FIFO enters an error mode it
	268	* cannot recover from by software.
	269	*/
	270	if (phydev->drv->phy_id == ATH8030_PHY_ID) {
	271	if (phydev->state == PHY_NOLINK) {
	272	if (priv->gpiod_reset && !priv->phy_reset) {
	273	struct at803x_context context;
	274
	275	at803x_context_save(phydev, &context);
	276
	277	gpiod_set_value(priv->gpiod_reset, 0);
	278	msleep(1);
	279	gpiod_set_value(priv->gpiod_reset, 1);
	280	msleep(1);
	281
	282	at803x_context_restore(phydev, &context);
	283
	284	dev_dbg(&phydev->dev, "%s(): phy was reset\n",
	285	__func__);
	286	priv->phy_reset = true;
	287	}
	288	} else {
	289	priv->phy_reset = false;
	290	}
	291	}
	292	}
	293
317420ab M	294	static struct phy_driver at803x_driver[] = {
	295	{
	296	/* ATHEROS 8035 */
13a56b44 DM	297	.phy_id = ATH8035_PHY_ID,
	298	.name = "Atheros 8035 ethernet",
	299	.phy_id_mask = 0xffffffef,
	300	.probe = at803x_probe,
	301	.config_init = at803x_config_init,
	302	.link_change_notify = at803x_link_change_notify,
	303	.set_wol = at803x_set_wol,
	304	.get_wol = at803x_get_wol,
	305	.suspend = at803x_suspend,
	306	.resume = at803x_resume,
	307	.features = PHY_GBIT_FEATURES,
	308	.flags = PHY_HAS_INTERRUPT,
	309	.config_aneg = genphy_config_aneg,
	310	.read_status = genphy_read_status,
0eae5982 MR	311	.ack_interrupt = at803x_ack_interrupt,
0eae5982 MR	312	.config_intr = at803x_config_intr,
13a56b44	313	.driver = {
0ca7111a MU	314	.owner = THIS_MODULE,
0ca7111a MU	315	},
317420ab M	316	}, {
317420ab M	317	/* ATHEROS 8030 */
13a56b44 DM	318	.phy_id = ATH8030_PHY_ID,
	319	.name = "Atheros 8030 ethernet",
	320	.phy_id_mask = 0xffffffef,
	321	.probe = at803x_probe,
	322	.config_init = at803x_config_init,
	323	.link_change_notify = at803x_link_change_notify,
	324	.set_wol = at803x_set_wol,
	325	.get_wol = at803x_get_wol,
	326	.suspend = at803x_suspend,
	327	.resume = at803x_resume,
	328	.features = PHY_GBIT_FEATURES,
	329	.flags = PHY_HAS_INTERRUPT,
	330	.config_aneg = genphy_config_aneg,
	331	.read_status = genphy_read_status,
0eae5982 MR	332	.ack_interrupt = at803x_ack_interrupt,
0eae5982 MR	333	.config_intr = at803x_config_intr,
13a56b44	334	.driver = {
0ca7111a MU	335	.owner = THIS_MODULE,
0ca7111a MU	336	},
05d7cce8 M	337	}, {
05d7cce8 M	338	/* ATHEROS 8031 */
13a56b44 DM	339	.phy_id = ATH8031_PHY_ID,
	340	.name = "Atheros 8031 ethernet",
	341	.phy_id_mask = 0xffffffef,
	342	.probe = at803x_probe,
	343	.config_init = at803x_config_init,
	344	.link_change_notify = at803x_link_change_notify,
	345	.set_wol = at803x_set_wol,
	346	.get_wol = at803x_get_wol,
	347	.suspend = at803x_suspend,
	348	.resume = at803x_resume,
	349	.features = PHY_GBIT_FEATURES,
	350	.flags = PHY_HAS_INTERRUPT,
	351	.config_aneg = genphy_config_aneg,
	352	.read_status = genphy_read_status,
	353	.ack_interrupt = &at803x_ack_interrupt,
	354	.config_intr = &at803x_config_intr,
	355	.driver = {
05d7cce8 M	356	.owner = THIS_MODULE,
05d7cce8 M	357	},
317420ab	358	} };
0ca7111a	359
50fd7150	360	module_phy_driver(at803x_driver);
0ca7111a MU	361
0ca7111a MU	362	static struct mdio_device_id __maybe_unused atheros_tbl[] = {
bd8ca17f DM	363	{ ATH8030_PHY_ID, 0xffffffef },
	364	{ ATH8031_PHY_ID, 0xffffffef },
	365	{ ATH8035_PHY_ID, 0xffffffef },
0ca7111a MU	366	{ }
	367	};
	368
	369	MODULE_DEVICE_TABLE(mdio, atheros_tbl);