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qlcnic: update version 5.0.2
[linux-2.6-block.git] / drivers / net / niu.c
CommitLineData
a3138df9
DM		 1/* niu.c: Neptune ethernet driver.
2 *
be0c007a 3 * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
a3138df9
DM		 4 */
5
f10a1f2e
JP		 6#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
7
a3138df9
DM		 8#include <linux/module.h>
9#include <linux/init.h>
10#include <linux/pci.h>
11#include <linux/dma-mapping.h>
12#include <linux/netdevice.h>
13#include <linux/ethtool.h>
14#include <linux/etherdevice.h>
15#include <linux/platform_device.h>
16#include <linux/delay.h>
17#include <linux/bitops.h>
18#include <linux/mii.h>
19#include <linux/if_ether.h>
20#include <linux/if_vlan.h>
21#include <linux/ip.h>
22#include <linux/in.h>
23#include <linux/ipv6.h>
24#include <linux/log2.h>
25#include <linux/jiffies.h>
26#include <linux/crc32.h>
ccffad25 27#include <linux/list.h>
5a0e3ad6 28#include <linux/slab.h>
a3138df9
DM		 29
30#include <linux/io.h>
31
32#ifdef CONFIG_SPARC64
33#include <linux/of_device.h>
34#endif
35
36#include "niu.h"
37
38#define DRV_MODULE_NAME "niu"
d8c3e23d
DM		 39#define DRV_MODULE_VERSION "1.0"
40#define DRV_MODULE_RELDATE "Nov 14, 2008"
a3138df9
DM		 41
42static char version[] __devinitdata =
43 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
44
45MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
46MODULE_DESCRIPTION("NIU ethernet driver");
47MODULE_LICENSE("GPL");
48MODULE_VERSION(DRV_MODULE_VERSION);
49
a3138df9
DM		 50#ifndef readq
51static u64 readq(void __iomem *reg)
52{
e23a59e1 53 return ((u64) readl(reg)) | (((u64) readl(reg + 4UL)) << 32);
a3138df9
DM		 54}
55
56static void writeq(u64 val, void __iomem *reg)
57{
58 writel(val & 0xffffffff, reg);
59 writel(val >> 32, reg + 0x4UL);
60}
61#endif
62
a3aa1884 63static DEFINE_PCI_DEVICE_TABLE(niu_pci_tbl) = {
a3138df9
DM		 64 {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)},
65 {}
66};
67
68MODULE_DEVICE_TABLE(pci, niu_pci_tbl);
69
70#define NIU_TX_TIMEOUT (5 * HZ)
71
72#define nr64(reg) readq(np->regs + (reg))
73#define nw64(reg, val) writeq((val), np->regs + (reg))
74
75#define nr64_mac(reg) readq(np->mac_regs + (reg))
76#define nw64_mac(reg, val) writeq((val), np->mac_regs + (reg))
77
78#define nr64_ipp(reg) readq(np->regs + np->ipp_off + (reg))
79#define nw64_ipp(reg, val) writeq((val), np->regs + np->ipp_off + (reg))
80
81#define nr64_pcs(reg) readq(np->regs + np->pcs_off + (reg))
82#define nw64_pcs(reg, val) writeq((val), np->regs + np->pcs_off + (reg))
83
84#define nr64_xpcs(reg) readq(np->regs + np->xpcs_off + (reg))
85#define nw64_xpcs(reg, val) writeq((val), np->regs + np->xpcs_off + (reg))
86
87#define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
88
89static int niu_debug;
90static int debug = -1;
91module_param(debug, int, 0);
92MODULE_PARM_DESC(debug, "NIU debug level");
93
a3138df9
DM		 94#define niu_lock_parent(np, flags) \
95 spin_lock_irqsave(&np->parent->lock, flags)
96#define niu_unlock_parent(np, flags) \
97 spin_unlock_irqrestore(&np->parent->lock, flags)
98
5fbd7e24
MW		 99static int serdes_init_10g_serdes(struct niu *np);
100
a3138df9
DM		 101static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg,
102 u64 bits, int limit, int delay)
103{
104 while (--limit >= 0) {
105 u64 val = nr64_mac(reg);
106
107 if (!(val & bits))
108 break;
109 udelay(delay);
110 }
111 if (limit < 0)
112 return -ENODEV;
113 return 0;
114}
115
116static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg,
117 u64 bits, int limit, int delay,
118 const char *reg_name)
119{
120 int err;
121
122 nw64_mac(reg, bits);
123 err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay);
124 if (err)
f10a1f2e
JP		 125 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
126 (unsigned long long)bits, reg_name,
127 (unsigned long long)nr64_mac(reg));
a3138df9
DM		 128 return err;
129}
130
131#define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
132({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
133 __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
134})
135
136static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg,
137 u64 bits, int limit, int delay)
138{
139 while (--limit >= 0) {
140 u64 val = nr64_ipp(reg);
141
142 if (!(val & bits))
143 break;
144 udelay(delay);
145 }
146 if (limit < 0)
147 return -ENODEV;
148 return 0;
149}
150
151static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg,
152 u64 bits, int limit, int delay,
153 const char *reg_name)
154{
155 int err;
156 u64 val;
157
158 val = nr64_ipp(reg);
159 val |= bits;
160 nw64_ipp(reg, val);
161
162 err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay);
163 if (err)
f10a1f2e
JP		 164 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
165 (unsigned long long)bits, reg_name,
166 (unsigned long long)nr64_ipp(reg));
a3138df9
DM		 167 return err;
168}
169
170#define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
171({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
172 __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
173})
174
175static int __niu_wait_bits_clear(struct niu *np, unsigned long reg,
176 u64 bits, int limit, int delay)
177{
178 while (--limit >= 0) {
179 u64 val = nr64(reg);
180
181 if (!(val & bits))
182 break;
183 udelay(delay);
184 }
185 if (limit < 0)
186 return -ENODEV;
187 return 0;
188}
189
190#define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
191({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
192 __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
193})
194
195static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg,
196 u64 bits, int limit, int delay,
197 const char *reg_name)
198{
199 int err;
200
201 nw64(reg, bits);
202 err = __niu_wait_bits_clear(np, reg, bits, limit, delay);
203 if (err)
f10a1f2e
JP		 204 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
205 (unsigned long long)bits, reg_name,
206 (unsigned long long)nr64(reg));
a3138df9
DM		 207 return err;
208}
209
210#define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
211({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
212 __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
213})
214
215static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on)
216{
217 u64 val = (u64) lp->timer;
218
219 if (on)
220 val |= LDG_IMGMT_ARM;
221
222 nw64(LDG_IMGMT(lp->ldg_num), val);
223}
224
225static int niu_ldn_irq_enable(struct niu *np, int ldn, int on)
226{
227 unsigned long mask_reg, bits;
228 u64 val;
229
230 if (ldn < 0 || ldn > LDN_MAX)
231 return -EINVAL;
232
233 if (ldn < 64) {
234 mask_reg = LD_IM0(ldn);
235 bits = LD_IM0_MASK;
236 } else {
237 mask_reg = LD_IM1(ldn - 64);
238 bits = LD_IM1_MASK;
239 }
240
241 val = nr64(mask_reg);
242 if (on)
243 val &= ~bits;
244 else
245 val |= bits;
246 nw64(mask_reg, val);
247
248 return 0;
249}
250
251static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on)
252{
253 struct niu_parent *parent = np->parent;
254 int i;
255
256 for (i = 0; i <= LDN_MAX; i++) {
257 int err;
258
259 if (parent->ldg_map[i] != lp->ldg_num)
260 continue;
261
262 err = niu_ldn_irq_enable(np, i, on);
263 if (err)
264 return err;
265 }
266 return 0;
267}
268
269static int niu_enable_interrupts(struct niu *np, int on)
270{
271 int i;
272
273 for (i = 0; i < np->num_ldg; i++) {
274 struct niu_ldg *lp = &np->ldg[i];
275 int err;
276
277 err = niu_enable_ldn_in_ldg(np, lp, on);
278 if (err)
279 return err;
280 }
281 for (i = 0; i < np->num_ldg; i++)
282 niu_ldg_rearm(np, &np->ldg[i], on);
283
284 return 0;
285}
286
287static u32 phy_encode(u32 type, int port)
288{
289 return (type << (port * 2));
290}
291
292static u32 phy_decode(u32 val, int port)
293{
294 return (val >> (port * 2)) & PORT_TYPE_MASK;
295}
296
297static int mdio_wait(struct niu *np)
298{
299 int limit = 1000;
300 u64 val;
301
302 while (--limit > 0) {
303 val = nr64(MIF_FRAME_OUTPUT);
304 if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1)
305 return val & MIF_FRAME_OUTPUT_DATA;
306
307 udelay(10);
308 }
309
310 return -ENODEV;
311}
312
313static int mdio_read(struct niu *np, int port, int dev, int reg)
314{
315 int err;
316
317 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
318 err = mdio_wait(np);
319 if (err < 0)
320 return err;
321
322 nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev));
323 return mdio_wait(np);
324}
325
326static int mdio_write(struct niu *np, int port, int dev, int reg, int data)
327{
328 int err;
329
330 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
331 err = mdio_wait(np);
332 if (err < 0)
333 return err;
334
335 nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data));
336 err = mdio_wait(np);
337 if (err < 0)
338 return err;
339
340 return 0;
341}
342
343static int mii_read(struct niu *np, int port, int reg)
344{
345 nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg));
346 return mdio_wait(np);
347}
348
349static int mii_write(struct niu *np, int port, int reg, int data)
350{
351 int err;
352
353 nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data));
354 err = mdio_wait(np);
355 if (err < 0)
356 return err;
357
358 return 0;
359}
360
361static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val)
362{
363 int err;
364
365 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
366 ESR2_TI_PLL_TX_CFG_L(channel),
367 val & 0xffff);
368 if (!err)
369 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
370 ESR2_TI_PLL_TX_CFG_H(channel),
371 val >> 16);
372 return err;
373}
374
375static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val)
376{
377 int err;
378
379 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
380 ESR2_TI_PLL_RX_CFG_L(channel),
381 val & 0xffff);
382 if (!err)
383 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
384 ESR2_TI_PLL_RX_CFG_H(channel),
385 val >> 16);
386 return err;
387}
388
389/* Mode is always 10G fiber. */
e3e081e1 390static int serdes_init_niu_10g_fiber(struct niu *np)
a3138df9
DM		 391{
392 struct niu_link_config *lp = &np->link_config;
393 u32 tx_cfg, rx_cfg;
394 unsigned long i;
395
396 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
397 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
398 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
399 PLL_RX_CFG_EQ_LP_ADAPTIVE);
400
401 if (lp->loopback_mode == LOOPBACK_PHY) {
402 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
403
404 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
405 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
406
407 tx_cfg |= PLL_TX_CFG_ENTEST;
408 rx_cfg |= PLL_RX_CFG_ENTEST;
409 }
410
411 /* Initialize all 4 lanes of the SERDES. */
412 for (i = 0; i < 4; i++) {
413 int err = esr2_set_tx_cfg(np, i, tx_cfg);
414 if (err)
415 return err;
416 }
417
418 for (i = 0; i < 4; i++) {
419 int err = esr2_set_rx_cfg(np, i, rx_cfg);
420 if (err)
421 return err;
422 }
423
424 return 0;
425}
426
e3e081e1
SB		 427static int serdes_init_niu_1g_serdes(struct niu *np)
428{
429 struct niu_link_config *lp = &np->link_config;
430 u16 pll_cfg, pll_sts;
431 int max_retry = 100;
51e0f058 432 u64 uninitialized_var(sig), mask, val;
e3e081e1
SB		 433 u32 tx_cfg, rx_cfg;
434 unsigned long i;
435 int err;
436
437 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV |
438 PLL_TX_CFG_RATE_HALF);
439 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
440 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
441 PLL_RX_CFG_RATE_HALF);
442
443 if (np->port == 0)
444 rx_cfg |= PLL_RX_CFG_EQ_LP_ADAPTIVE;
445
446 if (lp->loopback_mode == LOOPBACK_PHY) {
447 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
448
449 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
450 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
451
452 tx_cfg |= PLL_TX_CFG_ENTEST;
453 rx_cfg |= PLL_RX_CFG_ENTEST;
454 }
455
456 /* Initialize PLL for 1G */
457 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_8X);
458
459 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
460 ESR2_TI_PLL_CFG_L, pll_cfg);
461 if (err) {
f10a1f2e
JP		 462 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
463 np->port, __func__);
e3e081e1
SB		 464 return err;
465 }
466
467 pll_sts = PLL_CFG_ENPLL;
468
469 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
470 ESR2_TI_PLL_STS_L, pll_sts);
471 if (err) {
f10a1f2e
JP		 472 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
473 np->port, __func__);
e3e081e1
SB		 474 return err;
475 }
476
477 udelay(200);
478
479 /* Initialize all 4 lanes of the SERDES. */
480 for (i = 0; i < 4; i++) {
481 err = esr2_set_tx_cfg(np, i, tx_cfg);
482 if (err)
483 return err;
484 }
485
486 for (i = 0; i < 4; i++) {
487 err = esr2_set_rx_cfg(np, i, rx_cfg);
488 if (err)
489 return err;
490 }
491
492 switch (np->port) {
493 case 0:
494 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
495 mask = val;
496 break;
497
498 case 1:
499 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
500 mask = val;
501 break;
502
503 default:
504 return -EINVAL;
505 }
506
507 while (max_retry--) {
508 sig = nr64(ESR_INT_SIGNALS);
509 if ((sig & mask) == val)
510 break;
511
512 mdelay(500);
513 }
514
515 if ((sig & mask) != val) {
f10a1f2e
JP		 516 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
517 np->port, (int)(sig & mask), (int)val);
e3e081e1
SB		 518 return -ENODEV;
519 }
520
521 return 0;
522}
523
524static int serdes_init_niu_10g_serdes(struct niu *np)
525{
526 struct niu_link_config *lp = &np->link_config;
527 u32 tx_cfg, rx_cfg, pll_cfg, pll_sts;
528 int max_retry = 100;
51e0f058 529 u64 uninitialized_var(sig), mask, val;
e3e081e1
SB		 530 unsigned long i;
531 int err;
532
533 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
534 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
535 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
536 PLL_RX_CFG_EQ_LP_ADAPTIVE);
537
538 if (lp->loopback_mode == LOOPBACK_PHY) {
539 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
540
541 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
542 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
543
544 tx_cfg |= PLL_TX_CFG_ENTEST;
545 rx_cfg |= PLL_RX_CFG_ENTEST;
546 }
547
548 /* Initialize PLL for 10G */
549 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_10X);
550
551 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
552 ESR2_TI_PLL_CFG_L, pll_cfg & 0xffff);
553 if (err) {
f10a1f2e
JP		 554 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
555 np->port, __func__);
e3e081e1
SB		 556 return err;
557 }
558
559 pll_sts = PLL_CFG_ENPLL;
560
561 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
562 ESR2_TI_PLL_STS_L, pll_sts & 0xffff);
563 if (err) {
f10a1f2e
JP		 564 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
565 np->port, __func__);
e3e081e1
SB		 566 return err;
567 }
568
569 udelay(200);
570
571 /* Initialize all 4 lanes of the SERDES. */
572 for (i = 0; i < 4; i++) {
573 err = esr2_set_tx_cfg(np, i, tx_cfg);
574 if (err)
575 return err;
576 }
577
578 for (i = 0; i < 4; i++) {
579 err = esr2_set_rx_cfg(np, i, rx_cfg);
580 if (err)
581 return err;
582 }
583
584 /* check if serdes is ready */
585
586 switch (np->port) {
587 case 0:
588 mask = ESR_INT_SIGNALS_P0_BITS;
589 val = (ESR_INT_SRDY0_P0 |
590 ESR_INT_DET0_P0 |
591 ESR_INT_XSRDY_P0 |
592 ESR_INT_XDP_P0_CH3 |
593 ESR_INT_XDP_P0_CH2 |
594 ESR_INT_XDP_P0_CH1 |
595 ESR_INT_XDP_P0_CH0);
596 break;
597
598 case 1:
599 mask = ESR_INT_SIGNALS_P1_BITS;
600 val = (ESR_INT_SRDY0_P1 |
601 ESR_INT_DET0_P1 |
602 ESR_INT_XSRDY_P1 |
603 ESR_INT_XDP_P1_CH3 |
604 ESR_INT_XDP_P1_CH2 |
605 ESR_INT_XDP_P1_CH1 |
606 ESR_INT_XDP_P1_CH0);
607 break;
608
609 default:
610 return -EINVAL;
611 }
612
613 while (max_retry--) {
614 sig = nr64(ESR_INT_SIGNALS);
615 if ((sig & mask) == val)
616 break;
617
618 mdelay(500);
619 }
620
621 if ((sig & mask) != val) {
f10a1f2e
JP		 622 pr_info("NIU Port %u signal bits [%08x] are not [%08x] for 10G...trying 1G\n",
623 np->port, (int)(sig & mask), (int)val);
e3e081e1
SB		 624
625 /* 10G failed, try initializing at 1G */
626 err = serdes_init_niu_1g_serdes(np);
627 if (!err) {
628 np->flags &= ~NIU_FLAGS_10G;
629 np->mac_xcvr = MAC_XCVR_PCS;
630 } else {
f10a1f2e
JP		 631 netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n",
632 np->port);
e3e081e1
SB		 633 return -ENODEV;
634 }
635 }
636 return 0;
637}
638
a3138df9
DM		 639static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val)
640{
641 int err;
642
643 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan));
644 if (err >= 0) {
645 *val = (err & 0xffff);
646 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
647 ESR_RXTX_CTRL_H(chan));
648 if (err >= 0)
649 *val |= ((err & 0xffff) << 16);
650 err = 0;
651 }
652 return err;
653}
654
655static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val)
656{
657 int err;
658
659 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
660 ESR_GLUE_CTRL0_L(chan));
661 if (err >= 0) {
662 *val = (err & 0xffff);
663 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
664 ESR_GLUE_CTRL0_H(chan));
665 if (err >= 0) {
666 *val |= ((err & 0xffff) << 16);
667 err = 0;
668 }
669 }
670 return err;
671}
672
673static int esr_read_reset(struct niu *np, u32 *val)
674{
675 int err;
676
677 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
678 ESR_RXTX_RESET_CTRL_L);
679 if (err >= 0) {
680 *val = (err & 0xffff);
681 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
682 ESR_RXTX_RESET_CTRL_H);
683 if (err >= 0) {
684 *val |= ((err & 0xffff) << 16);
685 err = 0;
686 }
687 }
688 return err;
689}
690
691static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val)
692{
693 int err;
694
695 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
696 ESR_RXTX_CTRL_L(chan), val & 0xffff);
697 if (!err)
698 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
699 ESR_RXTX_CTRL_H(chan), (val >> 16));
700 return err;
701}
702
703static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val)
704{
705 int err;
706
707 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
708 ESR_GLUE_CTRL0_L(chan), val & 0xffff);
709 if (!err)
710 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
711 ESR_GLUE_CTRL0_H(chan), (val >> 16));
712 return err;
713}
714
715static int esr_reset(struct niu *np)
716{
f166400b 717 u32 uninitialized_var(reset);
a3138df9
DM		 718 int err;
719
720 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
721 ESR_RXTX_RESET_CTRL_L, 0x0000);
722 if (err)
723 return err;
724 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
725 ESR_RXTX_RESET_CTRL_H, 0xffff);
726 if (err)
727 return err;
728 udelay(200);
729
730 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
731 ESR_RXTX_RESET_CTRL_L, 0xffff);
732 if (err)
733 return err;
734 udelay(200);
735
736 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
737 ESR_RXTX_RESET_CTRL_H, 0x0000);
738 if (err)
739 return err;
740 udelay(200);
741
742 err = esr_read_reset(np, &reset);
743 if (err)
744 return err;
745 if (reset != 0) {
f10a1f2e
JP		 746 netdev_err(np->dev, "Port %u ESR_RESET did not clear [%08x]\n",
747 np->port, reset);
a3138df9
DM		 748 return -ENODEV;
749 }
750
751 return 0;
752}
753
754static int serdes_init_10g(struct niu *np)
755{
756 struct niu_link_config *lp = &np->link_config;
757 unsigned long ctrl_reg, test_cfg_reg, i;
758 u64 ctrl_val, test_cfg_val, sig, mask, val;
759 int err;
760
761 switch (np->port) {
762 case 0:
763 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
764 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
765 break;
766 case 1:
767 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
768 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
769 break;
770
771 default:
772 return -EINVAL;
773 }
774 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
775 ENET_SERDES_CTRL_SDET_1 |
776 ENET_SERDES_CTRL_SDET_2 |
777 ENET_SERDES_CTRL_SDET_3 |
778 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
779 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
780 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
781 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
782 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
783 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
784 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
785 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
786 test_cfg_val = 0;
787
788 if (lp->loopback_mode == LOOPBACK_PHY) {
789 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
790 ENET_SERDES_TEST_MD_0_SHIFT) |
791 (ENET_TEST_MD_PAD_LOOPBACK <<
792 ENET_SERDES_TEST_MD_1_SHIFT) |
793 (ENET_TEST_MD_PAD_LOOPBACK <<
794 ENET_SERDES_TEST_MD_2_SHIFT) |
795 (ENET_TEST_MD_PAD_LOOPBACK <<
796 ENET_SERDES_TEST_MD_3_SHIFT));
797 }
798
799 nw64(ctrl_reg, ctrl_val);
800 nw64(test_cfg_reg, test_cfg_val);
801
802 /* Initialize all 4 lanes of the SERDES. */
803 for (i = 0; i < 4; i++) {
804 u32 rxtx_ctrl, glue0;
805
806 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
807 if (err)
808 return err;
809 err = esr_read_glue0(np, i, &glue0);
810 if (err)
811 return err;
812
813 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
814 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
815 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
816
817 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
818 ESR_GLUE_CTRL0_THCNT |
819 ESR_GLUE_CTRL0_BLTIME);
820 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
821 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
822 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
823 (BLTIME_300_CYCLES <<
824 ESR_GLUE_CTRL0_BLTIME_SHIFT));
825
826 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
827 if (err)
828 return err;
829 err = esr_write_glue0(np, i, glue0);
830 if (err)
831 return err;
832 }
833
834 err = esr_reset(np);
835 if (err)
836 return err;
837
838 sig = nr64(ESR_INT_SIGNALS);
839 switch (np->port) {
840 case 0:
841 mask = ESR_INT_SIGNALS_P0_BITS;
842 val = (ESR_INT_SRDY0_P0 |
843 ESR_INT_DET0_P0 |
844 ESR_INT_XSRDY_P0 |
845 ESR_INT_XDP_P0_CH3 |
846 ESR_INT_XDP_P0_CH2 |
847 ESR_INT_XDP_P0_CH1 |
848 ESR_INT_XDP_P0_CH0);
849 break;
850
851 case 1:
852 mask = ESR_INT_SIGNALS_P1_BITS;
853 val = (ESR_INT_SRDY0_P1 |
854 ESR_INT_DET0_P1 |
855 ESR_INT_XSRDY_P1 |
856 ESR_INT_XDP_P1_CH3 |
857 ESR_INT_XDP_P1_CH2 |
858 ESR_INT_XDP_P1_CH1 |
859 ESR_INT_XDP_P1_CH0);
860 break;
861
862 default:
863 return -EINVAL;
864 }
865
866 if ((sig & mask) != val) {
a5d6ab56
MW		 867 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
868 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
869 return 0;
870 }
f10a1f2e
JP		 871 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
872 np->port, (int)(sig & mask), (int)val);
a3138df9
DM		 873 return -ENODEV;
874 }
a5d6ab56
MW		 875 if (np->flags & NIU_FLAGS_HOTPLUG_PHY)
876 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
a3138df9
DM		 877 return 0;
878}
879
880static int serdes_init_1g(struct niu *np)
881{
882 u64 val;
883
884 val = nr64(ENET_SERDES_1_PLL_CFG);
885 val &= ~ENET_SERDES_PLL_FBDIV2;
886 switch (np->port) {
887 case 0:
888 val |= ENET_SERDES_PLL_HRATE0;
889 break;
890 case 1:
891 val |= ENET_SERDES_PLL_HRATE1;
892 break;
893 case 2:
894 val |= ENET_SERDES_PLL_HRATE2;
895 break;
896 case 3:
897 val |= ENET_SERDES_PLL_HRATE3;
898 break;
899 default:
900 return -EINVAL;
901 }
902 nw64(ENET_SERDES_1_PLL_CFG, val);
903
904 return 0;
905}
906
5fbd7e24
MW		 907static int serdes_init_1g_serdes(struct niu *np)
908{
909 struct niu_link_config *lp = &np->link_config;
910 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
911 u64 ctrl_val, test_cfg_val, sig, mask, val;
912 int err;
913 u64 reset_val, val_rd;
914
915 val = ENET_SERDES_PLL_HRATE0 | ENET_SERDES_PLL_HRATE1 |
916 ENET_SERDES_PLL_HRATE2 | ENET_SERDES_PLL_HRATE3 |
917 ENET_SERDES_PLL_FBDIV0;
918 switch (np->port) {
919 case 0:
920 reset_val = ENET_SERDES_RESET_0;
921 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
922 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
923 pll_cfg = ENET_SERDES_0_PLL_CFG;
924 break;
925 case 1:
926 reset_val = ENET_SERDES_RESET_1;
927 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
928 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
929 pll_cfg = ENET_SERDES_1_PLL_CFG;
930 break;
931
932 default:
933 return -EINVAL;
934 }
935 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
936 ENET_SERDES_CTRL_SDET_1 |
937 ENET_SERDES_CTRL_SDET_2 |
938 ENET_SERDES_CTRL_SDET_3 |
939 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
940 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
941 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
942 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
943 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
944 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
945 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
946 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
947 test_cfg_val = 0;
948
949 if (lp->loopback_mode == LOOPBACK_PHY) {
950 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
951 ENET_SERDES_TEST_MD_0_SHIFT) |
952 (ENET_TEST_MD_PAD_LOOPBACK <<
953 ENET_SERDES_TEST_MD_1_SHIFT) |
954 (ENET_TEST_MD_PAD_LOOPBACK <<
955 ENET_SERDES_TEST_MD_2_SHIFT) |
956 (ENET_TEST_MD_PAD_LOOPBACK <<
957 ENET_SERDES_TEST_MD_3_SHIFT));
958 }
959
960 nw64(ENET_SERDES_RESET, reset_val);
961 mdelay(20);
962 val_rd = nr64(ENET_SERDES_RESET);
963 val_rd &= ~reset_val;
964 nw64(pll_cfg, val);
965 nw64(ctrl_reg, ctrl_val);
966 nw64(test_cfg_reg, test_cfg_val);
967 nw64(ENET_SERDES_RESET, val_rd);
968 mdelay(2000);
969
970 /* Initialize all 4 lanes of the SERDES. */
971 for (i = 0; i < 4; i++) {
972 u32 rxtx_ctrl, glue0;
973
974 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
975 if (err)
976 return err;
977 err = esr_read_glue0(np, i, &glue0);
978 if (err)
979 return err;
980
981 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
982 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
983 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
984
985 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
986 ESR_GLUE_CTRL0_THCNT |
987 ESR_GLUE_CTRL0_BLTIME);
988 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
989 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
990 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
991 (BLTIME_300_CYCLES <<
992 ESR_GLUE_CTRL0_BLTIME_SHIFT));
993
994 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
995 if (err)
996 return err;
997 err = esr_write_glue0(np, i, glue0);
998 if (err)
999 return err;
1000 }
1001
1002
1003 sig = nr64(ESR_INT_SIGNALS);
1004 switch (np->port) {
1005 case 0:
1006 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
1007 mask = val;
1008 break;
1009
1010 case 1:
1011 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
1012 mask = val;
1013 break;
1014
1015 default:
1016 return -EINVAL;
1017 }
1018
1019 if ((sig & mask) != val) {
f10a1f2e
JP		 1020 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
1021 np->port, (int)(sig & mask), (int)val);
5fbd7e24
MW		 1022 return -ENODEV;
1023 }
1024
1025 return 0;
1026}
1027
1028static int link_status_1g_serdes(struct niu *np, int *link_up_p)
1029{
1030 struct niu_link_config *lp = &np->link_config;
1031 int link_up;
1032 u64 val;
1033 u16 current_speed;
1034 unsigned long flags;
1035 u8 current_duplex;
1036
1037 link_up = 0;
1038 current_speed = SPEED_INVALID;
1039 current_duplex = DUPLEX_INVALID;
1040
1041 spin_lock_irqsave(&np->lock, flags);
1042
1043 val = nr64_pcs(PCS_MII_STAT);
1044
1045 if (val & PCS_MII_STAT_LINK_STATUS) {
1046 link_up = 1;
1047 current_speed = SPEED_1000;
1048 current_duplex = DUPLEX_FULL;
1049 }
1050
1051 lp->active_speed = current_speed;
1052 lp->active_duplex = current_duplex;
1053 spin_unlock_irqrestore(&np->lock, flags);
1054
1055 *link_up_p = link_up;
1056 return 0;
1057}
1058
5fbd7e24
MW		 1059static int link_status_10g_serdes(struct niu *np, int *link_up_p)
1060{
1061 unsigned long flags;
1062 struct niu_link_config *lp = &np->link_config;
1063 int link_up = 0;
1064 int link_ok = 1;
1065 u64 val, val2;
1066 u16 current_speed;
1067 u8 current_duplex;
1068
1069 if (!(np->flags & NIU_FLAGS_10G))
1070 return link_status_1g_serdes(np, link_up_p);
1071
1072 current_speed = SPEED_INVALID;
1073 current_duplex = DUPLEX_INVALID;
1074 spin_lock_irqsave(&np->lock, flags);
1075
1076 val = nr64_xpcs(XPCS_STATUS(0));
1077 val2 = nr64_mac(XMAC_INTER2);
1078 if (val2 & 0x01000000)
1079 link_ok = 0;
1080
1081 if ((val & 0x1000ULL) && link_ok) {
1082 link_up = 1;
1083 current_speed = SPEED_10000;
1084 current_duplex = DUPLEX_FULL;
1085 }
1086 lp->active_speed = current_speed;
1087 lp->active_duplex = current_duplex;
1088 spin_unlock_irqrestore(&np->lock, flags);
1089 *link_up_p = link_up;
1090 return 0;
1091}
1092
38bb045d
CB		 1093static int link_status_mii(struct niu *np, int *link_up_p)
1094{
1095 struct niu_link_config *lp = &np->link_config;
1096 int err;
1097 int bmsr, advert, ctrl1000, stat1000, lpa, bmcr, estatus;
1098 int supported, advertising, active_speed, active_duplex;
1099
1100 err = mii_read(np, np->phy_addr, MII_BMCR);
1101 if (unlikely(err < 0))
1102 return err;
1103 bmcr = err;
1104
1105 err = mii_read(np, np->phy_addr, MII_BMSR);
1106 if (unlikely(err < 0))
1107 return err;
1108 bmsr = err;
1109
1110 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1111 if (unlikely(err < 0))
1112 return err;
1113 advert = err;
1114
1115 err = mii_read(np, np->phy_addr, MII_LPA);
1116 if (unlikely(err < 0))
1117 return err;
1118 lpa = err;
1119
1120 if (likely(bmsr & BMSR_ESTATEN)) {
1121 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1122 if (unlikely(err < 0))
1123 return err;
1124 estatus = err;
1125
1126 err = mii_read(np, np->phy_addr, MII_CTRL1000);
1127 if (unlikely(err < 0))
1128 return err;
1129 ctrl1000 = err;
1130
1131 err = mii_read(np, np->phy_addr, MII_STAT1000);
1132 if (unlikely(err < 0))
1133 return err;
1134 stat1000 = err;
1135 } else
1136 estatus = ctrl1000 = stat1000 = 0;
1137
1138 supported = 0;
1139 if (bmsr & BMSR_ANEGCAPABLE)
1140 supported |= SUPPORTED_Autoneg;
1141 if (bmsr & BMSR_10HALF)
1142 supported |= SUPPORTED_10baseT_Half;
1143 if (bmsr & BMSR_10FULL)
1144 supported |= SUPPORTED_10baseT_Full;
1145 if (bmsr & BMSR_100HALF)
1146 supported |= SUPPORTED_100baseT_Half;
1147 if (bmsr & BMSR_100FULL)
1148 supported |= SUPPORTED_100baseT_Full;
1149 if (estatus & ESTATUS_1000_THALF)
1150 supported |= SUPPORTED_1000baseT_Half;
1151 if (estatus & ESTATUS_1000_TFULL)
1152 supported |= SUPPORTED_1000baseT_Full;
1153 lp->supported = supported;
1154
1155 advertising = 0;
1156 if (advert & ADVERTISE_10HALF)
1157 advertising |= ADVERTISED_10baseT_Half;
1158 if (advert & ADVERTISE_10FULL)
1159 advertising |= ADVERTISED_10baseT_Full;
1160 if (advert & ADVERTISE_100HALF)
1161 advertising |= ADVERTISED_100baseT_Half;
1162 if (advert & ADVERTISE_100FULL)
1163 advertising |= ADVERTISED_100baseT_Full;
1164 if (ctrl1000 & ADVERTISE_1000HALF)
1165 advertising |= ADVERTISED_1000baseT_Half;
1166 if (ctrl1000 & ADVERTISE_1000FULL)
1167 advertising |= ADVERTISED_1000baseT_Full;
1168
1169 if (bmcr & BMCR_ANENABLE) {
1170 int neg, neg1000;
1171
1172 lp->active_autoneg = 1;
1173 advertising |= ADVERTISED_Autoneg;
1174
1175 neg = advert & lpa;
1176 neg1000 = (ctrl1000 << 2) & stat1000;
1177
1178 if (neg1000 & (LPA_1000FULL | LPA_1000HALF))
1179 active_speed = SPEED_1000;
1180 else if (neg & LPA_100)
1181 active_speed = SPEED_100;
1182 else if (neg & (LPA_10HALF | LPA_10FULL))
1183 active_speed = SPEED_10;
1184 else
1185 active_speed = SPEED_INVALID;
1186
1187 if ((neg1000 & LPA_1000FULL) || (neg & LPA_DUPLEX))
1188 active_duplex = DUPLEX_FULL;
1189 else if (active_speed != SPEED_INVALID)
1190 active_duplex = DUPLEX_HALF;
1191 else
1192 active_duplex = DUPLEX_INVALID;
1193 } else {
1194 lp->active_autoneg = 0;
1195
1196 if ((bmcr & BMCR_SPEED1000) && !(bmcr & BMCR_SPEED100))
1197 active_speed = SPEED_1000;
1198 else if (bmcr & BMCR_SPEED100)
1199 active_speed = SPEED_100;
1200 else
1201 active_speed = SPEED_10;
1202
1203 if (bmcr & BMCR_FULLDPLX)
1204 active_duplex = DUPLEX_FULL;
1205 else
1206 active_duplex = DUPLEX_HALF;
1207 }
1208
1209 lp->active_advertising = advertising;
1210 lp->active_speed = active_speed;
1211 lp->active_duplex = active_duplex;
1212 *link_up_p = !!(bmsr & BMSR_LSTATUS);
1213
1214 return 0;
1215}
1216
5fbd7e24
MW		 1217static int link_status_1g_rgmii(struct niu *np, int *link_up_p)
1218{
1219 struct niu_link_config *lp = &np->link_config;
1220 u16 current_speed, bmsr;
1221 unsigned long flags;
1222 u8 current_duplex;
1223 int err, link_up;
1224
1225 link_up = 0;
1226 current_speed = SPEED_INVALID;
1227 current_duplex = DUPLEX_INVALID;
1228
1229 spin_lock_irqsave(&np->lock, flags);
1230
1231 err = -EINVAL;
1232
1233 err = mii_read(np, np->phy_addr, MII_BMSR);
1234 if (err < 0)
1235 goto out;
1236
1237 bmsr = err;
1238 if (bmsr & BMSR_LSTATUS) {
1239 u16 adv, lpa, common, estat;
1240
1241 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1242 if (err < 0)
1243 goto out;
1244 adv = err;
1245
1246 err = mii_read(np, np->phy_addr, MII_LPA);
1247 if (err < 0)
1248 goto out;
1249 lpa = err;
1250
1251 common = adv & lpa;
1252
1253 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1254 if (err < 0)
1255 goto out;
1256 estat = err;
1257 link_up = 1;
1258 current_speed = SPEED_1000;
1259 current_duplex = DUPLEX_FULL;
1260
1261 }
1262 lp->active_speed = current_speed;
1263 lp->active_duplex = current_duplex;
1264 err = 0;
1265
1266out:
1267 spin_unlock_irqrestore(&np->lock, flags);
1268
1269 *link_up_p = link_up;
1270 return err;
1271}
1272
38bb045d
CB		 1273static int link_status_1g(struct niu *np, int *link_up_p)
1274{
1275 struct niu_link_config *lp = &np->link_config;
1276 unsigned long flags;
1277 int err;
1278
1279 spin_lock_irqsave(&np->lock, flags);
1280
1281 err = link_status_mii(np, link_up_p);
1282 lp->supported |= SUPPORTED_TP;
1283 lp->active_advertising |= ADVERTISED_TP;
1284
1285 spin_unlock_irqrestore(&np->lock, flags);
1286 return err;
1287}
1288
a3138df9
DM		 1289static int bcm8704_reset(struct niu *np)
1290{
1291 int err, limit;
1292
1293 err = mdio_read(np, np->phy_addr,
1294 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
9c5cd670 1295 if (err < 0 || err == 0xffff)
a3138df9
DM		 1296 return err;
1297 err |= BMCR_RESET;
1298 err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1299 MII_BMCR, err);
1300 if (err)
1301 return err;
1302
1303 limit = 1000;
1304 while (--limit >= 0) {
1305 err = mdio_read(np, np->phy_addr,
1306 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1307 if (err < 0)
1308 return err;
1309 if (!(err & BMCR_RESET))
1310 break;
1311 }
1312 if (limit < 0) {
f10a1f2e
JP		 1313 netdev_err(np->dev, "Port %u PHY will not reset (bmcr=%04x)\n",
1314 np->port, (err & 0xffff));
a3138df9
DM		 1315 return -ENODEV;
1316 }
1317 return 0;
1318}
1319
1320/* When written, certain PHY registers need to be read back twice
1321 * in order for the bits to settle properly.
1322 */
1323static int bcm8704_user_dev3_readback(struct niu *np, int reg)
1324{
1325 int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1326 if (err < 0)
1327 return err;
1328 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1329 if (err < 0)
1330 return err;
1331 return 0;
1332}
1333
a5d6ab56
MW		 1334static int bcm8706_init_user_dev3(struct niu *np)
1335{
1336 int err;
1337
1338
1339 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1340 BCM8704_USER_OPT_DIGITAL_CTRL);
1341 if (err < 0)
1342 return err;
1343 err &= ~USER_ODIG_CTRL_GPIOS;
1344 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1345 err |= USER_ODIG_CTRL_RESV2;
1346 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1347 BCM8704_USER_OPT_DIGITAL_CTRL, err);
1348 if (err)
1349 return err;
1350
1351 mdelay(1000);
1352
1353 return 0;
1354}
1355
a3138df9
DM		 1356static int bcm8704_init_user_dev3(struct niu *np)
1357{
1358 int err;
1359
1360 err = mdio_write(np, np->phy_addr,
1361 BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL,
1362 (USER_CONTROL_OPTXRST_LVL |
1363 USER_CONTROL_OPBIASFLT_LVL |
1364 USER_CONTROL_OBTMPFLT_LVL |
1365 USER_CONTROL_OPPRFLT_LVL |
1366 USER_CONTROL_OPTXFLT_LVL |
1367 USER_CONTROL_OPRXLOS_LVL |
1368 USER_CONTROL_OPRXFLT_LVL |
1369 USER_CONTROL_OPTXON_LVL |
1370 (0x3f << USER_CONTROL_RES1_SHIFT)));
1371 if (err)
1372 return err;
1373
1374 err = mdio_write(np, np->phy_addr,
1375 BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL,
1376 (USER_PMD_TX_CTL_XFP_CLKEN |
1377 (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) |
1378 (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) |
1379 USER_PMD_TX_CTL_TSCK_LPWREN));
1380 if (err)
1381 return err;
1382
1383 err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL);
1384 if (err)
1385 return err;
1386 err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL);
1387 if (err)
1388 return err;
1389
1390 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1391 BCM8704_USER_OPT_DIGITAL_CTRL);
1392 if (err < 0)
1393 return err;
1394 err &= ~USER_ODIG_CTRL_GPIOS;
1395 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1396 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1397 BCM8704_USER_OPT_DIGITAL_CTRL, err);
1398 if (err)
1399 return err;
1400
1401 mdelay(1000);
1402
1403 return 0;
1404}
1405
b0de8e40
ML		 1406static int mrvl88x2011_act_led(struct niu *np, int val)
1407{
1408 int err;
1409
1410 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1411 MRVL88X2011_LED_8_TO_11_CTL);
1412 if (err < 0)
1413 return err;
1414
1415 err &= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT,MRVL88X2011_LED_CTL_MASK);
1416 err |= MRVL88X2011_LED(MRVL88X2011_LED_ACT,val);
1417
1418 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1419 MRVL88X2011_LED_8_TO_11_CTL, err);
1420}
1421
1422static int mrvl88x2011_led_blink_rate(struct niu *np, int rate)
1423{
1424 int err;
1425
1426 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1427 MRVL88X2011_LED_BLINK_CTL);
1428 if (err >= 0) {
1429 err &= ~MRVL88X2011_LED_BLKRATE_MASK;
1430 err |= (rate << 4);
1431
1432 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1433 MRVL88X2011_LED_BLINK_CTL, err);
1434 }
1435
1436 return err;
1437}
1438
1439static int xcvr_init_10g_mrvl88x2011(struct niu *np)
1440{
1441 int err;
1442
1443 /* Set LED functions */
1444 err = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS);
1445 if (err)
1446 return err;
1447
1448 /* led activity */
1449 err = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF);
1450 if (err)
1451 return err;
1452
1453 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1454 MRVL88X2011_GENERAL_CTL);
1455 if (err < 0)
1456 return err;
1457
1458 err |= MRVL88X2011_ENA_XFPREFCLK;
1459
1460 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1461 MRVL88X2011_GENERAL_CTL, err);
1462 if (err < 0)
1463 return err;
1464
1465 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1466 MRVL88X2011_PMA_PMD_CTL_1);
1467 if (err < 0)
1468 return err;
1469
1470 if (np->link_config.loopback_mode == LOOPBACK_MAC)
1471 err |= MRVL88X2011_LOOPBACK;
1472 else
1473 err &= ~MRVL88X2011_LOOPBACK;
1474
1475 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1476 MRVL88X2011_PMA_PMD_CTL_1, err);
1477 if (err < 0)
1478 return err;
1479
1480 /* Enable PMD */
1481 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1482 MRVL88X2011_10G_PMD_TX_DIS, MRVL88X2011_ENA_PMDTX);
1483}
1484
a5d6ab56
MW		 1485
1486static int xcvr_diag_bcm870x(struct niu *np)
a3138df9 1487{
a3138df9 1488 u16 analog_stat0, tx_alarm_status;
a5d6ab56 1489 int err = 0;
a3138df9
DM		 1490
1491#if 1
1492 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1493 MII_STAT1000);
1494 if (err < 0)
1495 return err;
f10a1f2e 1496 pr_info("Port %u PMA_PMD(MII_STAT1000) [%04x]\n", np->port, err);
a3138df9
DM		 1497
1498 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20);
1499 if (err < 0)
1500 return err;
f10a1f2e 1501 pr_info("Port %u USER_DEV3(0x20) [%04x]\n", np->port, err);
a3138df9
DM		 1502
1503 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1504 MII_NWAYTEST);
1505 if (err < 0)
1506 return err;
f10a1f2e 1507 pr_info("Port %u PHYXS(MII_NWAYTEST) [%04x]\n", np->port, err);
a3138df9
DM		 1508#endif
1509
1510 /* XXX dig this out it might not be so useful XXX */
1511 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1512 BCM8704_USER_ANALOG_STATUS0);
1513 if (err < 0)
1514 return err;
1515 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1516 BCM8704_USER_ANALOG_STATUS0);
1517 if (err < 0)
1518 return err;
1519 analog_stat0 = err;
1520
1521 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1522 BCM8704_USER_TX_ALARM_STATUS);
1523 if (err < 0)
1524 return err;
1525 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1526 BCM8704_USER_TX_ALARM_STATUS);
1527 if (err < 0)
1528 return err;
1529 tx_alarm_status = err;
1530
1531 if (analog_stat0 != 0x03fc) {
1532 if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) {
f10a1f2e
JP		 1533 pr_info("Port %u cable not connected or bad cable\n",
1534 np->port);
a3138df9 1535 } else if (analog_stat0 == 0x639c) {
f10a1f2e
JP		 1536 pr_info("Port %u optical module is bad or missing\n",
1537 np->port);
a3138df9
DM		 1538 }
1539 }
1540
1541 return 0;
1542}
1543
a5d6ab56
MW		 1544static int xcvr_10g_set_lb_bcm870x(struct niu *np)
1545{
1546 struct niu_link_config *lp = &np->link_config;
1547 int err;
1548
1549 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1550 MII_BMCR);
1551 if (err < 0)
1552 return err;
1553
1554 err &= ~BMCR_LOOPBACK;
1555
1556 if (lp->loopback_mode == LOOPBACK_MAC)
1557 err |= BMCR_LOOPBACK;
1558
1559 err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1560 MII_BMCR, err);
1561 if (err)
1562 return err;
1563
1564 return 0;
1565}
1566
1567static int xcvr_init_10g_bcm8706(struct niu *np)
1568{
1569 int err = 0;
1570 u64 val;
1571
1572 if ((np->flags & NIU_FLAGS_HOTPLUG_PHY) &&
1573 (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) == 0)
1574 return err;
1575
1576 val = nr64_mac(XMAC_CONFIG);
1577 val &= ~XMAC_CONFIG_LED_POLARITY;
1578 val |= XMAC_CONFIG_FORCE_LED_ON;
1579 nw64_mac(XMAC_CONFIG, val);
1580
1581 val = nr64(MIF_CONFIG);
1582 val |= MIF_CONFIG_INDIRECT_MODE;
1583 nw64(MIF_CONFIG, val);
1584
1585 err = bcm8704_reset(np);
1586 if (err)
1587 return err;
1588
1589 err = xcvr_10g_set_lb_bcm870x(np);
1590 if (err)
1591 return err;
1592
1593 err = bcm8706_init_user_dev3(np);
1594 if (err)
1595 return err;
1596
1597 err = xcvr_diag_bcm870x(np);
1598 if (err)
1599 return err;
1600
1601 return 0;
1602}
1603
1604static int xcvr_init_10g_bcm8704(struct niu *np)
1605{
1606 int err;
1607
1608 err = bcm8704_reset(np);
1609 if (err)
1610 return err;
1611
1612 err = bcm8704_init_user_dev3(np);
1613 if (err)
1614 return err;
1615
1616 err = xcvr_10g_set_lb_bcm870x(np);
1617 if (err)
1618 return err;
1619
1620 err = xcvr_diag_bcm870x(np);
1621 if (err)
1622 return err;
1623
1624 return 0;
1625}
1626
b0de8e40
ML		 1627static int xcvr_init_10g(struct niu *np)
1628{
1629 int phy_id, err;
1630 u64 val;
1631
1632 val = nr64_mac(XMAC_CONFIG);
1633 val &= ~XMAC_CONFIG_LED_POLARITY;
1634 val |= XMAC_CONFIG_FORCE_LED_ON;
1635 nw64_mac(XMAC_CONFIG, val);
1636
1637 /* XXX shared resource, lock parent XXX */
1638 val = nr64(MIF_CONFIG);
1639 val |= MIF_CONFIG_INDIRECT_MODE;
1640 nw64(MIF_CONFIG, val);
1641
1642 phy_id = phy_decode(np->parent->port_phy, np->port);
1643 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
1644
1645 /* handle different phy types */
1646 switch (phy_id & NIU_PHY_ID_MASK) {
1647 case NIU_PHY_ID_MRVL88X2011:
1648 err = xcvr_init_10g_mrvl88x2011(np);
1649 break;
1650
1651 default: /* bcom 8704 */
1652 err = xcvr_init_10g_bcm8704(np);
1653 break;
1654 }
1655
1656 return 0;
1657}
1658
a3138df9
DM		 1659static int mii_reset(struct niu *np)
1660{
1661 int limit, err;
1662
1663 err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET);
1664 if (err)
1665 return err;
1666
1667 limit = 1000;
1668 while (--limit >= 0) {
1669 udelay(500);
1670 err = mii_read(np, np->phy_addr, MII_BMCR);
1671 if (err < 0)
1672 return err;
1673 if (!(err & BMCR_RESET))
1674 break;
1675 }
1676 if (limit < 0) {
f10a1f2e
JP		 1677 netdev_err(np->dev, "Port %u MII would not reset, bmcr[%04x]\n",
1678 np->port, err);
a3138df9
DM		 1679 return -ENODEV;
1680 }
1681
1682 return 0;
1683}
1684
5fbd7e24
MW		 1685static int xcvr_init_1g_rgmii(struct niu *np)
1686{
1687 int err;
1688 u64 val;
1689 u16 bmcr, bmsr, estat;
1690
1691 val = nr64(MIF_CONFIG);
1692 val &= ~MIF_CONFIG_INDIRECT_MODE;
1693 nw64(MIF_CONFIG, val);
1694
1695 err = mii_reset(np);
1696 if (err)
1697 return err;
1698
1699 err = mii_read(np, np->phy_addr, MII_BMSR);
1700 if (err < 0)
1701 return err;
1702 bmsr = err;
1703
1704 estat = 0;
1705 if (bmsr & BMSR_ESTATEN) {
1706 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1707 if (err < 0)
1708 return err;
1709 estat = err;
1710 }
1711
1712 bmcr = 0;
1713 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1714 if (err)
1715 return err;
1716
1717 if (bmsr & BMSR_ESTATEN) {
1718 u16 ctrl1000 = 0;
1719
1720 if (estat & ESTATUS_1000_TFULL)
1721 ctrl1000 |= ADVERTISE_1000FULL;
1722 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
1723 if (err)
1724 return err;
1725 }
1726
1727 bmcr = (BMCR_SPEED1000 | BMCR_FULLDPLX);
1728
1729 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1730 if (err)
1731 return err;
1732
1733 err = mii_read(np, np->phy_addr, MII_BMCR);
1734 if (err < 0)
1735 return err;
1736 bmcr = mii_read(np, np->phy_addr, MII_BMCR);
1737
1738 err = mii_read(np, np->phy_addr, MII_BMSR);
1739 if (err < 0)
1740 return err;
1741
1742 return 0;
1743}
1744
a3138df9
DM		 1745static int mii_init_common(struct niu *np)
1746{
1747 struct niu_link_config *lp = &np->link_config;
1748 u16 bmcr, bmsr, adv, estat;
1749 int err;
1750
1751 err = mii_reset(np);
1752 if (err)
1753 return err;
1754
1755 err = mii_read(np, np->phy_addr, MII_BMSR);
1756 if (err < 0)
1757 return err;
1758 bmsr = err;
1759
1760 estat = 0;
1761 if (bmsr & BMSR_ESTATEN) {
1762 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1763 if (err < 0)
1764 return err;
1765 estat = err;
1766 }
1767
1768 bmcr = 0;
1769 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1770 if (err)
1771 return err;
1772
1773 if (lp->loopback_mode == LOOPBACK_MAC) {
1774 bmcr |= BMCR_LOOPBACK;
1775 if (lp->active_speed == SPEED_1000)
1776 bmcr |= BMCR_SPEED1000;
1777 if (lp->active_duplex == DUPLEX_FULL)
1778 bmcr |= BMCR_FULLDPLX;
1779 }
1780
1781 if (lp->loopback_mode == LOOPBACK_PHY) {
1782 u16 aux;
1783
1784 aux = (BCM5464R_AUX_CTL_EXT_LB |
1785 BCM5464R_AUX_CTL_WRITE_1);
1786 err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux);
1787 if (err)
1788 return err;
1789 }
1790
38bb045d
CB		 1791 if (lp->autoneg) {
1792 u16 ctrl1000;
1793
1794 adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1795 if ((bmsr & BMSR_10HALF) &&
1796 (lp->advertising & ADVERTISED_10baseT_Half))
1797 adv |= ADVERTISE_10HALF;
1798 if ((bmsr & BMSR_10FULL) &&
1799 (lp->advertising & ADVERTISED_10baseT_Full))
1800 adv |= ADVERTISE_10FULL;
1801 if ((bmsr & BMSR_100HALF) &&
1802 (lp->advertising & ADVERTISED_100baseT_Half))
1803 adv |= ADVERTISE_100HALF;
1804 if ((bmsr & BMSR_100FULL) &&
1805 (lp->advertising & ADVERTISED_100baseT_Full))
1806 adv |= ADVERTISE_100FULL;
1807 err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv);
a3138df9
DM		 1808 if (err)
1809 return err;
38bb045d
CB		 1810
1811 if (likely(bmsr & BMSR_ESTATEN)) {
1812 ctrl1000 = 0;
1813 if ((estat & ESTATUS_1000_THALF) &&
1814 (lp->advertising & ADVERTISED_1000baseT_Half))
1815 ctrl1000 |= ADVERTISE_1000HALF;
1816 if ((estat & ESTATUS_1000_TFULL) &&
1817 (lp->advertising & ADVERTISED_1000baseT_Full))
1818 ctrl1000 |= ADVERTISE_1000FULL;
1819 err = mii_write(np, np->phy_addr,
1820 MII_CTRL1000, ctrl1000);
1821 if (err)
1822 return err;
1823 }
1824
1825 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1826 } else {
1827 /* !lp->autoneg */
1828 int fulldpx;
1829
1830 if (lp->duplex == DUPLEX_FULL) {
1831 bmcr |= BMCR_FULLDPLX;
1832 fulldpx = 1;
1833 } else if (lp->duplex == DUPLEX_HALF)
1834 fulldpx = 0;
1835 else
1836 return -EINVAL;
1837
1838 if (lp->speed == SPEED_1000) {
1839 /* if X-full requested while not supported, or
1840 X-half requested while not supported... */
1841 if ((fulldpx && !(estat & ESTATUS_1000_TFULL)) ||
1842 (!fulldpx && !(estat & ESTATUS_1000_THALF)))
1843 return -EINVAL;
1844 bmcr |= BMCR_SPEED1000;
1845 } else if (lp->speed == SPEED_100) {
1846 if ((fulldpx && !(bmsr & BMSR_100FULL)) ||
1847 (!fulldpx && !(bmsr & BMSR_100HALF)))
1848 return -EINVAL;
1849 bmcr |= BMCR_SPEED100;
1850 } else if (lp->speed == SPEED_10) {
1851 if ((fulldpx && !(bmsr & BMSR_10FULL)) ||
1852 (!fulldpx && !(bmsr & BMSR_10HALF)))
1853 return -EINVAL;
1854 } else
1855 return -EINVAL;
a3138df9 1856 }
a3138df9
DM		 1857
1858 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1859 if (err)
1860 return err;
1861
38bb045d 1862#if 0
a3138df9
DM		 1863 err = mii_read(np, np->phy_addr, MII_BMCR);
1864 if (err < 0)
1865 return err;
38bb045d
CB		 1866 bmcr = err;
1867
a3138df9
DM		 1868 err = mii_read(np, np->phy_addr, MII_BMSR);
1869 if (err < 0)
1870 return err;
38bb045d
CB		 1871 bmsr = err;
1872
f10a1f2e 1873 pr_info("Port %u after MII init bmcr[%04x] bmsr[%04x]\n",
a3138df9
DM		 1874 np->port, bmcr, bmsr);
1875#endif
1876
1877 return 0;
1878}
1879
1880static int xcvr_init_1g(struct niu *np)
1881{
1882 u64 val;
1883
1884 /* XXX shared resource, lock parent XXX */
1885 val = nr64(MIF_CONFIG);
1886 val &= ~MIF_CONFIG_INDIRECT_MODE;
1887 nw64(MIF_CONFIG, val);
1888
1889 return mii_init_common(np);
1890}
1891
1892static int niu_xcvr_init(struct niu *np)
1893{
1894 const struct niu_phy_ops *ops = np->phy_ops;
1895 int err;
1896
1897 err = 0;
1898 if (ops->xcvr_init)
1899 err = ops->xcvr_init(np);
1900
1901 return err;
1902}
1903
1904static int niu_serdes_init(struct niu *np)
1905{
1906 const struct niu_phy_ops *ops = np->phy_ops;
1907 int err;
1908
1909 err = 0;
1910 if (ops->serdes_init)
1911 err = ops->serdes_init(np);
1912
1913 return err;
1914}
1915
1916static void niu_init_xif(struct niu *);
0c3b091b 1917static void niu_handle_led(struct niu *, int status);
a3138df9
DM		 1918
1919static int niu_link_status_common(struct niu *np, int link_up)
1920{
1921 struct niu_link_config *lp = &np->link_config;
1922 struct net_device *dev = np->dev;
1923 unsigned long flags;
1924
1925 if (!netif_carrier_ok(dev) && link_up) {
f10a1f2e
JP		 1926 netif_info(np, link, dev, "Link is up at %s, %s duplex\n",
1927 lp->active_speed == SPEED_10000 ? "10Gb/sec" :
1928 lp->active_speed == SPEED_1000 ? "1Gb/sec" :
1929 lp->active_speed == SPEED_100 ? "100Mbit/sec" :
1930 "10Mbit/sec",
1931 lp->active_duplex == DUPLEX_FULL ? "full" : "half");
a3138df9
DM		 1932
1933 spin_lock_irqsave(&np->lock, flags);
1934 niu_init_xif(np);
0c3b091b 1935 niu_handle_led(np, 1);
a3138df9
DM		 1936 spin_unlock_irqrestore(&np->lock, flags);
1937
1938 netif_carrier_on(dev);
1939 } else if (netif_carrier_ok(dev) && !link_up) {
f10a1f2e 1940 netif_warn(np, link, dev, "Link is down\n");
0c3b091b
ML		 1941 spin_lock_irqsave(&np->lock, flags);
1942 niu_handle_led(np, 0);
1943 spin_unlock_irqrestore(&np->lock, flags);
a3138df9
DM		 1944 netif_carrier_off(dev);
1945 }
1946
1947 return 0;
1948}
1949
b0de8e40 1950static int link_status_10g_mrvl(struct niu *np, int *link_up_p)
a3138df9 1951{
b0de8e40 1952 int err, link_up, pma_status, pcs_status;
a3138df9
DM		 1953
1954 link_up = 0;
1955
b0de8e40
ML		 1956 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1957 MRVL88X2011_10G_PMD_STATUS_2);
1958 if (err < 0)
1959 goto out;
a3138df9 1960
b0de8e40
ML		 1961 /* Check PMA/PMD Register: 1.0001.2 == 1 */
1962 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1963 MRVL88X2011_PMA_PMD_STATUS_1);
1964 if (err < 0)
1965 goto out;
1966
1967 pma_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1968
1969 /* Check PMC Register : 3.0001.2 == 1: read twice */
1970 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1971 MRVL88X2011_PMA_PMD_STATUS_1);
1972 if (err < 0)
1973 goto out;
1974
1975 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1976 MRVL88X2011_PMA_PMD_STATUS_1);
1977 if (err < 0)
1978 goto out;
1979
1980 pcs_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1981
1982 /* Check XGXS Register : 4.0018.[0-3,12] */
1983 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV4_ADDR,
1984 MRVL88X2011_10G_XGXS_LANE_STAT);
1985 if (err < 0)
a3138df9
DM		 1986 goto out;
1987
b0de8e40
ML		 1988 if (err == (PHYXS_XGXS_LANE_STAT_ALINGED | PHYXS_XGXS_LANE_STAT_LANE3 |
1989 PHYXS_XGXS_LANE_STAT_LANE2 | PHYXS_XGXS_LANE_STAT_LANE1 |
1990 PHYXS_XGXS_LANE_STAT_LANE0 | PHYXS_XGXS_LANE_STAT_MAGIC |
1991 0x800))
1992 link_up = (pma_status && pcs_status) ? 1 : 0;
1993
1994 np->link_config.active_speed = SPEED_10000;
1995 np->link_config.active_duplex = DUPLEX_FULL;
1996 err = 0;
1997out:
1998 mrvl88x2011_act_led(np, (link_up ?
1999 MRVL88X2011_LED_CTL_PCS_ACT :
2000 MRVL88X2011_LED_CTL_OFF));
2001
2002 *link_up_p = link_up;
2003 return err;
2004}
2005
a5d6ab56
MW		 2006static int link_status_10g_bcm8706(struct niu *np, int *link_up_p)
2007{
2008 int err, link_up;
2009 link_up = 0;
2010
2011 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2012 BCM8704_PMD_RCV_SIGDET);
9c5cd670 2013 if (err < 0 || err == 0xffff)
a5d6ab56
MW		 2014 goto out;
2015 if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2016 err = 0;
2017 goto out;
2018 }
2019
2020 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2021 BCM8704_PCS_10G_R_STATUS);
2022 if (err < 0)
2023 goto out;
2024
2025 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2026 err = 0;
2027 goto out;
2028 }
2029
2030 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2031 BCM8704_PHYXS_XGXS_LANE_STAT);
2032 if (err < 0)
2033 goto out;
2034 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2035 PHYXS_XGXS_LANE_STAT_MAGIC |
2036 PHYXS_XGXS_LANE_STAT_PATTEST |
2037 PHYXS_XGXS_LANE_STAT_LANE3 |
2038 PHYXS_XGXS_LANE_STAT_LANE2 |
2039 PHYXS_XGXS_LANE_STAT_LANE1 |
2040 PHYXS_XGXS_LANE_STAT_LANE0)) {
2041 err = 0;
2042 np->link_config.active_speed = SPEED_INVALID;
2043 np->link_config.active_duplex = DUPLEX_INVALID;
2044 goto out;
2045 }
2046
2047 link_up = 1;
2048 np->link_config.active_speed = SPEED_10000;
2049 np->link_config.active_duplex = DUPLEX_FULL;
2050 err = 0;
2051
2052out:
2053 *link_up_p = link_up;
a5d6ab56
MW		 2054 return err;
2055}
2056
b0de8e40
ML		 2057static int link_status_10g_bcom(struct niu *np, int *link_up_p)
2058{
2059 int err, link_up;
2060
2061 link_up = 0;
2062
a3138df9
DM		 2063 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2064 BCM8704_PMD_RCV_SIGDET);
2065 if (err < 0)
2066 goto out;
2067 if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2068 err = 0;
2069 goto out;
2070 }
2071
2072 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2073 BCM8704_PCS_10G_R_STATUS);
2074 if (err < 0)
2075 goto out;
2076 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2077 err = 0;
2078 goto out;
2079 }
2080
2081 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2082 BCM8704_PHYXS_XGXS_LANE_STAT);
2083 if (err < 0)
2084 goto out;
2085
2086 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2087 PHYXS_XGXS_LANE_STAT_MAGIC |
2088 PHYXS_XGXS_LANE_STAT_LANE3 |
2089 PHYXS_XGXS_LANE_STAT_LANE2 |
2090 PHYXS_XGXS_LANE_STAT_LANE1 |
2091 PHYXS_XGXS_LANE_STAT_LANE0)) {
2092 err = 0;
2093 goto out;
2094 }
2095
2096 link_up = 1;
2097 np->link_config.active_speed = SPEED_10000;
2098 np->link_config.active_duplex = DUPLEX_FULL;
2099 err = 0;
2100
2101out:
b0de8e40
ML		 2102 *link_up_p = link_up;
2103 return err;
2104}
2105
2106static int link_status_10g(struct niu *np, int *link_up_p)
2107{
2108 unsigned long flags;
2109 int err = -EINVAL;
2110
2111 spin_lock_irqsave(&np->lock, flags);
2112
2113 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2114 int phy_id;
2115
2116 phy_id = phy_decode(np->parent->port_phy, np->port);
2117 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
2118
2119 /* handle different phy types */
2120 switch (phy_id & NIU_PHY_ID_MASK) {
2121 case NIU_PHY_ID_MRVL88X2011:
2122 err = link_status_10g_mrvl(np, link_up_p);
2123 break;
2124
2125 default: /* bcom 8704 */
2126 err = link_status_10g_bcom(np, link_up_p);
2127 break;
2128 }
2129 }
2130
a3138df9
DM		 2131 spin_unlock_irqrestore(&np->lock, flags);
2132
a3138df9
DM		 2133 return err;
2134}
2135
a5d6ab56
MW		 2136static int niu_10g_phy_present(struct niu *np)
2137{
2138 u64 sig, mask, val;
2139
2140 sig = nr64(ESR_INT_SIGNALS);
2141 switch (np->port) {
2142 case 0:
2143 mask = ESR_INT_SIGNALS_P0_BITS;
2144 val = (ESR_INT_SRDY0_P0 |
2145 ESR_INT_DET0_P0 |
2146 ESR_INT_XSRDY_P0 |
2147 ESR_INT_XDP_P0_CH3 |
2148 ESR_INT_XDP_P0_CH2 |
2149 ESR_INT_XDP_P0_CH1 |
2150 ESR_INT_XDP_P0_CH0);
2151 break;
2152
2153 case 1:
2154 mask = ESR_INT_SIGNALS_P1_BITS;
2155 val = (ESR_INT_SRDY0_P1 |
2156 ESR_INT_DET0_P1 |
2157 ESR_INT_XSRDY_P1 |
2158 ESR_INT_XDP_P1_CH3 |
2159 ESR_INT_XDP_P1_CH2 |
2160 ESR_INT_XDP_P1_CH1 |
2161 ESR_INT_XDP_P1_CH0);
2162 break;
2163
2164 default:
2165 return 0;
2166 }
2167
2168 if ((sig & mask) != val)
2169 return 0;
2170 return 1;
2171}
2172
2173static int link_status_10g_hotplug(struct niu *np, int *link_up_p)
2174{
2175 unsigned long flags;
2176 int err = 0;
2177 int phy_present;
2178 int phy_present_prev;
2179
2180 spin_lock_irqsave(&np->lock, flags);
2181
2182 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2183 phy_present_prev = (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) ?
2184 1 : 0;
2185 phy_present = niu_10g_phy_present(np);
2186 if (phy_present != phy_present_prev) {
2187 /* state change */
2188 if (phy_present) {
9c5cd670 2189 /* A NEM was just plugged in */
a5d6ab56
MW		 2190 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2191 if (np->phy_ops->xcvr_init)
2192 err = np->phy_ops->xcvr_init(np);
2193 if (err) {
9c5cd670
TC		 2194 err = mdio_read(np, np->phy_addr,
2195 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
2196 if (err == 0xffff) {
2197 /* No mdio, back-to-back XAUI */
2198 goto out;
2199 }
a5d6ab56
MW		 2200 /* debounce */
2201 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2202 }
2203 } else {
2204 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2205 *link_up_p = 0;
f10a1f2e
JP		 2206 netif_warn(np, link, np->dev,
2207 "Hotplug PHY Removed\n");
a5d6ab56
MW		 2208 }
2209 }
9c5cd670
TC		 2210out:
2211 if (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) {
a5d6ab56 2212 err = link_status_10g_bcm8706(np, link_up_p);
9c5cd670
TC		 2213 if (err == 0xffff) {
2214 /* No mdio, back-to-back XAUI: it is C10NEM */
2215 *link_up_p = 1;
2216 np->link_config.active_speed = SPEED_10000;
2217 np->link_config.active_duplex = DUPLEX_FULL;
2218 }
2219 }
a5d6ab56
MW		 2220 }
2221
2222 spin_unlock_irqrestore(&np->lock, flags);
2223
9c5cd670 2224 return 0;
a5d6ab56
MW		 2225}
2226
a3138df9
DM		 2227static int niu_link_status(struct niu *np, int *link_up_p)
2228{
2229 const struct niu_phy_ops *ops = np->phy_ops;
2230 int err;
2231
2232 err = 0;
2233 if (ops->link_status)
2234 err = ops->link_status(np, link_up_p);
2235
2236 return err;
2237}
2238
2239static void niu_timer(unsigned long __opaque)
2240{
2241 struct niu *np = (struct niu *) __opaque;
2242 unsigned long off;
2243 int err, link_up;
2244
2245 err = niu_link_status(np, &link_up);
2246 if (!err)
2247 niu_link_status_common(np, link_up);
2248
2249 if (netif_carrier_ok(np->dev))
2250 off = 5 * HZ;
2251 else
2252 off = 1 * HZ;
2253 np->timer.expires = jiffies + off;
2254
2255 add_timer(&np->timer);
2256}
2257
5fbd7e24
MW		 2258static const struct niu_phy_ops phy_ops_10g_serdes = {
2259 .serdes_init = serdes_init_10g_serdes,
2260 .link_status = link_status_10g_serdes,
2261};
2262
e3e081e1
SB		 2263static const struct niu_phy_ops phy_ops_10g_serdes_niu = {
2264 .serdes_init = serdes_init_niu_10g_serdes,
2265 .link_status = link_status_10g_serdes,
2266};
2267
2268static const struct niu_phy_ops phy_ops_1g_serdes_niu = {
2269 .serdes_init = serdes_init_niu_1g_serdes,
2270 .link_status = link_status_1g_serdes,
2271};
2272
5fbd7e24
MW		 2273static const struct niu_phy_ops phy_ops_1g_rgmii = {
2274 .xcvr_init = xcvr_init_1g_rgmii,
2275 .link_status = link_status_1g_rgmii,
2276};
2277
a3138df9 2278static const struct niu_phy_ops phy_ops_10g_fiber_niu = {
e3e081e1 2279 .serdes_init = serdes_init_niu_10g_fiber,
a3138df9
DM		 2280 .xcvr_init = xcvr_init_10g,
2281 .link_status = link_status_10g,
2282};
2283
2284static const struct niu_phy_ops phy_ops_10g_fiber = {
2285 .serdes_init = serdes_init_10g,
2286 .xcvr_init = xcvr_init_10g,
2287 .link_status = link_status_10g,
2288};
2289
a5d6ab56
MW		 2290static const struct niu_phy_ops phy_ops_10g_fiber_hotplug = {
2291 .serdes_init = serdes_init_10g,
2292 .xcvr_init = xcvr_init_10g_bcm8706,
2293 .link_status = link_status_10g_hotplug,
2294};
2295
9c5cd670
TC		 2296static const struct niu_phy_ops phy_ops_niu_10g_hotplug = {
2297 .serdes_init = serdes_init_niu_10g_fiber,
2298 .xcvr_init = xcvr_init_10g_bcm8706,
2299 .link_status = link_status_10g_hotplug,
2300};
2301
a3138df9
DM		 2302static const struct niu_phy_ops phy_ops_10g_copper = {
2303 .serdes_init = serdes_init_10g,
2304 .link_status = link_status_10g, /* XXX */
2305};
2306
2307static const struct niu_phy_ops phy_ops_1g_fiber = {
2308 .serdes_init = serdes_init_1g,
2309 .xcvr_init = xcvr_init_1g,
2310 .link_status = link_status_1g,
2311};
2312
2313static const struct niu_phy_ops phy_ops_1g_copper = {
2314 .xcvr_init = xcvr_init_1g,
2315 .link_status = link_status_1g,
2316};
2317
2318struct niu_phy_template {
2319 const struct niu_phy_ops *ops;
2320 u32 phy_addr_base;
2321};
2322
e3e081e1 2323static const struct niu_phy_template phy_template_niu_10g_fiber = {
a3138df9
DM		 2324 .ops = &phy_ops_10g_fiber_niu,
2325 .phy_addr_base = 16,
2326};
2327
e3e081e1
SB		 2328static const struct niu_phy_template phy_template_niu_10g_serdes = {
2329 .ops = &phy_ops_10g_serdes_niu,
2330 .phy_addr_base = 0,
2331};
2332
2333static const struct niu_phy_template phy_template_niu_1g_serdes = {
2334 .ops = &phy_ops_1g_serdes_niu,
2335 .phy_addr_base = 0,
2336};
2337
a3138df9
DM		 2338static const struct niu_phy_template phy_template_10g_fiber = {
2339 .ops = &phy_ops_10g_fiber,
2340 .phy_addr_base = 8,
2341};
2342
a5d6ab56
MW		 2343static const struct niu_phy_template phy_template_10g_fiber_hotplug = {
2344 .ops = &phy_ops_10g_fiber_hotplug,
2345 .phy_addr_base = 8,
2346};
2347
9c5cd670
TC		 2348static const struct niu_phy_template phy_template_niu_10g_hotplug = {
2349 .ops = &phy_ops_niu_10g_hotplug,
2350 .phy_addr_base = 8,
2351};
2352
a3138df9
DM		 2353static const struct niu_phy_template phy_template_10g_copper = {
2354 .ops = &phy_ops_10g_copper,
2355 .phy_addr_base = 10,
2356};
2357
2358static const struct niu_phy_template phy_template_1g_fiber = {
2359 .ops = &phy_ops_1g_fiber,
2360 .phy_addr_base = 0,
2361};
2362
2363static const struct niu_phy_template phy_template_1g_copper = {
2364 .ops = &phy_ops_1g_copper,
2365 .phy_addr_base = 0,
2366};
2367
5fbd7e24
MW		 2368static const struct niu_phy_template phy_template_1g_rgmii = {
2369 .ops = &phy_ops_1g_rgmii,
2370 .phy_addr_base = 0,
2371};
2372
2373static const struct niu_phy_template phy_template_10g_serdes = {
2374 .ops = &phy_ops_10g_serdes,
2375 .phy_addr_base = 0,
2376};
2377
2378static int niu_atca_port_num[4] = {
2379 0, 0, 11, 10
2380};
2381
2382static int serdes_init_10g_serdes(struct niu *np)
2383{
2384 struct niu_link_config *lp = &np->link_config;
2385 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
2386 u64 ctrl_val, test_cfg_val, sig, mask, val;
5fbd7e24
MW		 2387 u64 reset_val;
2388
2389 switch (np->port) {
2390 case 0:
2391 reset_val = ENET_SERDES_RESET_0;
2392 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
2393 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
2394 pll_cfg = ENET_SERDES_0_PLL_CFG;
2395 break;
2396 case 1:
2397 reset_val = ENET_SERDES_RESET_1;
2398 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
2399 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
2400 pll_cfg = ENET_SERDES_1_PLL_CFG;
2401 break;
2402
2403 default:
2404 return -EINVAL;
2405 }
2406 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
2407 ENET_SERDES_CTRL_SDET_1 |
2408 ENET_SERDES_CTRL_SDET_2 |
2409 ENET_SERDES_CTRL_SDET_3 |
2410 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
2411 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
2412 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
2413 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
2414 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
2415 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
2416 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
2417 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
2418 test_cfg_val = 0;
2419
2420 if (lp->loopback_mode == LOOPBACK_PHY) {
2421 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
2422 ENET_SERDES_TEST_MD_0_SHIFT) |
2423 (ENET_TEST_MD_PAD_LOOPBACK <<
2424 ENET_SERDES_TEST_MD_1_SHIFT) |
2425 (ENET_TEST_MD_PAD_LOOPBACK <<
2426 ENET_SERDES_TEST_MD_2_SHIFT) |
2427 (ENET_TEST_MD_PAD_LOOPBACK <<
2428 ENET_SERDES_TEST_MD_3_SHIFT));
2429 }
2430
2431 esr_reset(np);
2432 nw64(pll_cfg, ENET_SERDES_PLL_FBDIV2);
2433 nw64(ctrl_reg, ctrl_val);
2434 nw64(test_cfg_reg, test_cfg_val);
2435
2436 /* Initialize all 4 lanes of the SERDES. */
2437 for (i = 0; i < 4; i++) {
2438 u32 rxtx_ctrl, glue0;
7c34eb89 2439 int err;
5fbd7e24
MW		 2440
2441 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
2442 if (err)
2443 return err;
2444 err = esr_read_glue0(np, i, &glue0);
2445 if (err)
2446 return err;
2447
2448 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
2449 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
2450 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
2451
2452 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
2453 ESR_GLUE_CTRL0_THCNT |
2454 ESR_GLUE_CTRL0_BLTIME);
2455 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
2456 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
2457 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
2458 (BLTIME_300_CYCLES <<
2459 ESR_GLUE_CTRL0_BLTIME_SHIFT));
2460
2461 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
2462 if (err)
2463 return err;
2464 err = esr_write_glue0(np, i, glue0);
2465 if (err)
2466 return err;
2467 }
2468
2469
2470 sig = nr64(ESR_INT_SIGNALS);
2471 switch (np->port) {
2472 case 0:
2473 mask = ESR_INT_SIGNALS_P0_BITS;
2474 val = (ESR_INT_SRDY0_P0 |
2475 ESR_INT_DET0_P0 |
2476 ESR_INT_XSRDY_P0 |
2477 ESR_INT_XDP_P0_CH3 |
2478 ESR_INT_XDP_P0_CH2 |
2479 ESR_INT_XDP_P0_CH1 |
2480 ESR_INT_XDP_P0_CH0);
2481 break;
2482
2483 case 1:
2484 mask = ESR_INT_SIGNALS_P1_BITS;
2485 val = (ESR_INT_SRDY0_P1 |
2486 ESR_INT_DET0_P1 |
2487 ESR_INT_XSRDY_P1 |
2488 ESR_INT_XDP_P1_CH3 |
2489 ESR_INT_XDP_P1_CH2 |
2490 ESR_INT_XDP_P1_CH1 |
2491 ESR_INT_XDP_P1_CH0);
2492 break;
2493
2494 default:
2495 return -EINVAL;
2496 }
2497
2498 if ((sig & mask) != val) {
2499 int err;
2500 err = serdes_init_1g_serdes(np);
2501 if (!err) {
2502 np->flags &= ~NIU_FLAGS_10G;
2503 np->mac_xcvr = MAC_XCVR_PCS;
2504 } else {
f10a1f2e
JP		 2505 netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n",
2506 np->port);
5fbd7e24
MW		 2507 return -ENODEV;
2508 }
2509 }
2510
2511 return 0;
2512}
2513
a3138df9
DM		 2514static int niu_determine_phy_disposition(struct niu *np)
2515{
2516 struct niu_parent *parent = np->parent;
2517 u8 plat_type = parent->plat_type;
2518 const struct niu_phy_template *tp;
2519 u32 phy_addr_off = 0;
2520
2521 if (plat_type == PLAT_TYPE_NIU) {
e3e081e1
SB		 2522 switch (np->flags &
2523 (NIU_FLAGS_10G |
2524 NIU_FLAGS_FIBER |
2525 NIU_FLAGS_XCVR_SERDES)) {
2526 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2527 /* 10G Serdes */
2528 tp = &phy_template_niu_10g_serdes;
2529 break;
2530 case NIU_FLAGS_XCVR_SERDES:
2531 /* 1G Serdes */
2532 tp = &phy_template_niu_1g_serdes;
2533 break;
2534 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2535 /* 10G Fiber */
2536 default:
9c5cd670
TC		 2537 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2538 tp = &phy_template_niu_10g_hotplug;
2539 if (np->port == 0)
2540 phy_addr_off = 8;
2541 if (np->port == 1)
2542 phy_addr_off = 12;
2543 } else {
2544 tp = &phy_template_niu_10g_fiber;
2545 phy_addr_off += np->port;
2546 }
e3e081e1
SB		 2547 break;
2548 }
a3138df9 2549 } else {
5fbd7e24
MW		 2550 switch (np->flags &
2551 (NIU_FLAGS_10G |
2552 NIU_FLAGS_FIBER |
2553 NIU_FLAGS_XCVR_SERDES)) {
a3138df9
DM		 2554 case 0:
2555 /* 1G copper */
2556 tp = &phy_template_1g_copper;
2557 if (plat_type == PLAT_TYPE_VF_P0)
2558 phy_addr_off = 10;
2559 else if (plat_type == PLAT_TYPE_VF_P1)
2560 phy_addr_off = 26;
2561
2562 phy_addr_off += (np->port ^ 0x3);
2563 break;
2564
2565 case NIU_FLAGS_10G:
2566 /* 10G copper */
e0d8496a 2567 tp = &phy_template_10g_copper;
a3138df9
DM		 2568 break;
2569
2570 case NIU_FLAGS_FIBER:
2571 /* 1G fiber */
2572 tp = &phy_template_1g_fiber;
2573 break;
2574
2575 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2576 /* 10G fiber */
2577 tp = &phy_template_10g_fiber;
2578 if (plat_type == PLAT_TYPE_VF_P0 ||
2579 plat_type == PLAT_TYPE_VF_P1)
2580 phy_addr_off = 8;
2581 phy_addr_off += np->port;
a5d6ab56
MW		 2582 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2583 tp = &phy_template_10g_fiber_hotplug;
2584 if (np->port == 0)
2585 phy_addr_off = 8;
2586 if (np->port == 1)
2587 phy_addr_off = 12;
2588 }
a3138df9
DM		 2589 break;
2590
5fbd7e24
MW		 2591 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2592 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
2593 case NIU_FLAGS_XCVR_SERDES:
2594 switch(np->port) {
2595 case 0:
2596 case 1:
2597 tp = &phy_template_10g_serdes;
2598 break;
2599 case 2:
2600 case 3:
2601 tp = &phy_template_1g_rgmii;
2602 break;
2603 default:
2604 return -EINVAL;
2605 break;
2606 }
2607 phy_addr_off = niu_atca_port_num[np->port];
2608 break;
2609
a3138df9
DM		 2610 default:
2611 return -EINVAL;
2612 }
2613 }
2614
2615 np->phy_ops = tp->ops;
2616 np->phy_addr = tp->phy_addr_base + phy_addr_off;
2617
2618 return 0;
2619}
2620
2621static int niu_init_link(struct niu *np)
2622{
2623 struct niu_parent *parent = np->parent;
2624 int err, ignore;
2625
2626 if (parent->plat_type == PLAT_TYPE_NIU) {
2627 err = niu_xcvr_init(np);
2628 if (err)
2629 return err;
2630 msleep(200);
2631 }
2632 err = niu_serdes_init(np);
9c5cd670 2633 if (err && !(np->flags & NIU_FLAGS_HOTPLUG_PHY))
a3138df9
DM		 2634 return err;
2635 msleep(200);
2636 err = niu_xcvr_init(np);
9c5cd670 2637 if (!err || (np->flags & NIU_FLAGS_HOTPLUG_PHY))
a3138df9
DM		 2638 niu_link_status(np, &ignore);
2639 return 0;
2640}
2641
2642static void niu_set_primary_mac(struct niu *np, unsigned char *addr)
2643{
2644 u16 reg0 = addr[4] << 8 | addr[5];
2645 u16 reg1 = addr[2] << 8 | addr[3];
2646 u16 reg2 = addr[0] << 8 | addr[1];
2647
2648 if (np->flags & NIU_FLAGS_XMAC) {
2649 nw64_mac(XMAC_ADDR0, reg0);
2650 nw64_mac(XMAC_ADDR1, reg1);
2651 nw64_mac(XMAC_ADDR2, reg2);
2652 } else {
2653 nw64_mac(BMAC_ADDR0, reg0);
2654 nw64_mac(BMAC_ADDR1, reg1);
2655 nw64_mac(BMAC_ADDR2, reg2);
2656 }
2657}
2658
2659static int niu_num_alt_addr(struct niu *np)
2660{
2661 if (np->flags & NIU_FLAGS_XMAC)
2662 return XMAC_NUM_ALT_ADDR;
2663 else
2664 return BMAC_NUM_ALT_ADDR;
2665}
2666
2667static int niu_set_alt_mac(struct niu *np, int index, unsigned char *addr)
2668{
2669 u16 reg0 = addr[4] << 8 | addr[5];
2670 u16 reg1 = addr[2] << 8 | addr[3];
2671 u16 reg2 = addr[0] << 8 | addr[1];
2672
2673 if (index >= niu_num_alt_addr(np))
2674 return -EINVAL;
2675
2676 if (np->flags & NIU_FLAGS_XMAC) {
2677 nw64_mac(XMAC_ALT_ADDR0(index), reg0);
2678 nw64_mac(XMAC_ALT_ADDR1(index), reg1);
2679 nw64_mac(XMAC_ALT_ADDR2(index), reg2);
2680 } else {
2681 nw64_mac(BMAC_ALT_ADDR0(index), reg0);
2682 nw64_mac(BMAC_ALT_ADDR1(index), reg1);
2683 nw64_mac(BMAC_ALT_ADDR2(index), reg2);
2684 }
2685
2686 return 0;
2687}
2688
2689static int niu_enable_alt_mac(struct niu *np, int index, int on)
2690{
2691 unsigned long reg;
2692 u64 val, mask;
2693
2694 if (index >= niu_num_alt_addr(np))
2695 return -EINVAL;
2696
fa907895 2697 if (np->flags & NIU_FLAGS_XMAC) {
a3138df9 2698 reg = XMAC_ADDR_CMPEN;
fa907895
MW		 2699 mask = 1 << index;
2700 } else {
a3138df9 2701 reg = BMAC_ADDR_CMPEN;
fa907895
MW		 2702 mask = 1 << (index + 1);
2703 }
a3138df9
DM		 2704
2705 val = nr64_mac(reg);
2706 if (on)
2707 val |= mask;
2708 else
2709 val &= ~mask;
2710 nw64_mac(reg, val);
2711
2712 return 0;
2713}
2714
2715static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg,
2716 int num, int mac_pref)
2717{
2718 u64 val = nr64_mac(reg);
2719 val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR);
2720 val |= num;
2721 if (mac_pref)
2722 val |= HOST_INFO_MPR;
2723 nw64_mac(reg, val);
2724}
2725
2726static int __set_rdc_table_num(struct niu *np,
2727 int xmac_index, int bmac_index,
2728 int rdc_table_num, int mac_pref)
2729{
2730 unsigned long reg;
2731
2732 if (rdc_table_num & ~HOST_INFO_MACRDCTBLN)
2733 return -EINVAL;
2734 if (np->flags & NIU_FLAGS_XMAC)
2735 reg = XMAC_HOST_INFO(xmac_index);
2736 else
2737 reg = BMAC_HOST_INFO(bmac_index);
2738 __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref);
2739 return 0;
2740}
2741
2742static int niu_set_primary_mac_rdc_table(struct niu *np, int table_num,
2743 int mac_pref)
2744{
2745 return __set_rdc_table_num(np, 17, 0, table_num, mac_pref);
2746}
2747
2748static int niu_set_multicast_mac_rdc_table(struct niu *np, int table_num,
2749 int mac_pref)
2750{
2751 return __set_rdc_table_num(np, 16, 8, table_num, mac_pref);
2752}
2753
2754static int niu_set_alt_mac_rdc_table(struct niu *np, int idx,
2755 int table_num, int mac_pref)
2756{
2757 if (idx >= niu_num_alt_addr(np))
2758 return -EINVAL;
2759 return __set_rdc_table_num(np, idx, idx + 1, table_num, mac_pref);
2760}
2761
2762static u64 vlan_entry_set_parity(u64 reg_val)
2763{
2764 u64 port01_mask;
2765 u64 port23_mask;
2766
2767 port01_mask = 0x00ff;
2768 port23_mask = 0xff00;
2769
2770 if (hweight64(reg_val & port01_mask) & 1)
2771 reg_val |= ENET_VLAN_TBL_PARITY0;
2772 else
2773 reg_val &= ~ENET_VLAN_TBL_PARITY0;
2774
2775 if (hweight64(reg_val & port23_mask) & 1)
2776 reg_val |= ENET_VLAN_TBL_PARITY1;
2777 else
2778 reg_val &= ~ENET_VLAN_TBL_PARITY1;
2779
2780 return reg_val;
2781}
2782
2783static void vlan_tbl_write(struct niu *np, unsigned long index,
2784 int port, int vpr, int rdc_table)
2785{
2786 u64 reg_val = nr64(ENET_VLAN_TBL(index));
2787
2788 reg_val &= ~((ENET_VLAN_TBL_VPR |
2789 ENET_VLAN_TBL_VLANRDCTBLN) <<
2790 ENET_VLAN_TBL_SHIFT(port));
2791 if (vpr)
2792 reg_val |= (ENET_VLAN_TBL_VPR <<
2793 ENET_VLAN_TBL_SHIFT(port));
2794 reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port));
2795
2796 reg_val = vlan_entry_set_parity(reg_val);
2797
2798 nw64(ENET_VLAN_TBL(index), reg_val);
2799}
2800
2801static void vlan_tbl_clear(struct niu *np)
2802{
2803 int i;
2804
2805 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++)
2806 nw64(ENET_VLAN_TBL(i), 0);
2807}
2808
2809static int tcam_wait_bit(struct niu *np, u64 bit)
2810{
2811 int limit = 1000;
2812
2813 while (--limit > 0) {
2814 if (nr64(TCAM_CTL) & bit)
2815 break;
2816 udelay(1);
2817 }
d2a928e4 2818 if (limit <= 0)
a3138df9
DM		 2819 return -ENODEV;
2820
2821 return 0;
2822}
2823
2824static int tcam_flush(struct niu *np, int index)
2825{
2826 nw64(TCAM_KEY_0, 0x00);
2827 nw64(TCAM_KEY_MASK_0, 0xff);
2828 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2829
2830 return tcam_wait_bit(np, TCAM_CTL_STAT);
2831}
2832
2833#if 0
2834static int tcam_read(struct niu *np, int index,
2835 u64 *key, u64 *mask)
2836{
2837 int err;
2838
2839 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index));
2840 err = tcam_wait_bit(np, TCAM_CTL_STAT);
2841 if (!err) {
2842 key[0] = nr64(TCAM_KEY_0);
2843 key[1] = nr64(TCAM_KEY_1);
2844 key[2] = nr64(TCAM_KEY_2);
2845 key[3] = nr64(TCAM_KEY_3);
2846 mask[0] = nr64(TCAM_KEY_MASK_0);
2847 mask[1] = nr64(TCAM_KEY_MASK_1);
2848 mask[2] = nr64(TCAM_KEY_MASK_2);
2849 mask[3] = nr64(TCAM_KEY_MASK_3);
2850 }
2851 return err;
2852}
2853#endif
2854
2855static int tcam_write(struct niu *np, int index,
2856 u64 *key, u64 *mask)
2857{
2858 nw64(TCAM_KEY_0, key[0]);
2859 nw64(TCAM_KEY_1, key[1]);
2860 nw64(TCAM_KEY_2, key[2]);
2861 nw64(TCAM_KEY_3, key[3]);
2862 nw64(TCAM_KEY_MASK_0, mask[0]);
2863 nw64(TCAM_KEY_MASK_1, mask[1]);
2864 nw64(TCAM_KEY_MASK_2, mask[2]);
2865 nw64(TCAM_KEY_MASK_3, mask[3]);
2866 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2867
2868 return tcam_wait_bit(np, TCAM_CTL_STAT);
2869}
2870
2871#if 0
2872static int tcam_assoc_read(struct niu *np, int index, u64 *data)
2873{
2874 int err;
2875
2876 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index));
2877 err = tcam_wait_bit(np, TCAM_CTL_STAT);
2878 if (!err)
2879 *data = nr64(TCAM_KEY_1);
2880
2881 return err;
2882}
2883#endif
2884
2885static int tcam_assoc_write(struct niu *np, int index, u64 assoc_data)
2886{
2887 nw64(TCAM_KEY_1, assoc_data);
2888 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index));
2889
2890 return tcam_wait_bit(np, TCAM_CTL_STAT);
2891}
2892
2893static void tcam_enable(struct niu *np, int on)
2894{
2895 u64 val = nr64(FFLP_CFG_1);
2896
2897 if (on)
2898 val &= ~FFLP_CFG_1_TCAM_DIS;
2899 else
2900 val |= FFLP_CFG_1_TCAM_DIS;
2901 nw64(FFLP_CFG_1, val);
2902}
2903
2904static void tcam_set_lat_and_ratio(struct niu *np, u64 latency, u64 ratio)
2905{
2906 u64 val = nr64(FFLP_CFG_1);
2907
2908 val &= ~(FFLP_CFG_1_FFLPINITDONE |
2909 FFLP_CFG_1_CAMLAT |
2910 FFLP_CFG_1_CAMRATIO);
2911 val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT);
2912 val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT);
2913 nw64(FFLP_CFG_1, val);
2914
2915 val = nr64(FFLP_CFG_1);
2916 val |= FFLP_CFG_1_FFLPINITDONE;
2917 nw64(FFLP_CFG_1, val);
2918}
2919
2920static int tcam_user_eth_class_enable(struct niu *np, unsigned long class,
2921 int on)
2922{
2923 unsigned long reg;
2924 u64 val;
2925
2926 if (class < CLASS_CODE_ETHERTYPE1 ||
2927 class > CLASS_CODE_ETHERTYPE2)
2928 return -EINVAL;
2929
2930 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2931 val = nr64(reg);
2932 if (on)
2933 val |= L2_CLS_VLD;
2934 else
2935 val &= ~L2_CLS_VLD;
2936 nw64(reg, val);
2937
2938 return 0;
2939}
2940
2941#if 0
2942static int tcam_user_eth_class_set(struct niu *np, unsigned long class,
2943 u64 ether_type)
2944{
2945 unsigned long reg;
2946 u64 val;
2947
2948 if (class < CLASS_CODE_ETHERTYPE1 ||
2949 class > CLASS_CODE_ETHERTYPE2 ||
2950 (ether_type & ~(u64)0xffff) != 0)
2951 return -EINVAL;
2952
2953 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2954 val = nr64(reg);
2955 val &= ~L2_CLS_ETYPE;
2956 val |= (ether_type << L2_CLS_ETYPE_SHIFT);
2957 nw64(reg, val);
2958
2959 return 0;
2960}
2961#endif
2962
2963static int tcam_user_ip_class_enable(struct niu *np, unsigned long class,
2964 int on)
2965{
2966 unsigned long reg;
2967 u64 val;
2968
2969 if (class < CLASS_CODE_USER_PROG1 ||
2970 class > CLASS_CODE_USER_PROG4)
2971 return -EINVAL;
2972
2973 reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2974 val = nr64(reg);
2975 if (on)
2976 val |= L3_CLS_VALID;
2977 else
2978 val &= ~L3_CLS_VALID;
2979 nw64(reg, val);
2980
2981 return 0;
2982}
2983
a3138df9
DM		 2984static int tcam_user_ip_class_set(struct niu *np, unsigned long class,
2985 int ipv6, u64 protocol_id,
2986 u64 tos_mask, u64 tos_val)
2987{
2988 unsigned long reg;
2989 u64 val;
2990
2991 if (class < CLASS_CODE_USER_PROG1 ||
2992 class > CLASS_CODE_USER_PROG4 ||
2993 (protocol_id & ~(u64)0xff) != 0 ||
2994 (tos_mask & ~(u64)0xff) != 0 ||
2995 (tos_val & ~(u64)0xff) != 0)
2996 return -EINVAL;
2997
2998 reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2999 val = nr64(reg);
3000 val &= ~(L3_CLS_IPVER | L3_CLS_PID |
3001 L3_CLS_TOSMASK | L3_CLS_TOS);
3002 if (ipv6)
3003 val |= L3_CLS_IPVER;
3004 val |= (protocol_id << L3_CLS_PID_SHIFT);
3005 val |= (tos_mask << L3_CLS_TOSMASK_SHIFT);
3006 val |= (tos_val << L3_CLS_TOS_SHIFT);
3007 nw64(reg, val);
3008
3009 return 0;
3010}
a3138df9
DM		 3011
3012static int tcam_early_init(struct niu *np)
3013{
3014 unsigned long i;
3015 int err;
3016
3017 tcam_enable(np, 0);
3018 tcam_set_lat_and_ratio(np,
3019 DEFAULT_TCAM_LATENCY,
3020 DEFAULT_TCAM_ACCESS_RATIO);
3021 for (i = CLASS_CODE_ETHERTYPE1; i <= CLASS_CODE_ETHERTYPE2; i++) {
3022 err = tcam_user_eth_class_enable(np, i, 0);
3023 if (err)
3024 return err;
3025 }
3026 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_USER_PROG4; i++) {
3027 err = tcam_user_ip_class_enable(np, i, 0);
3028 if (err)
3029 return err;
3030 }
3031
3032 return 0;
3033}
3034
3035static int tcam_flush_all(struct niu *np)
3036{
3037 unsigned long i;
3038
3039 for (i = 0; i < np->parent->tcam_num_entries; i++) {
3040 int err = tcam_flush(np, i);
3041 if (err)
3042 return err;
3043 }
3044 return 0;
3045}
3046
3047static u64 hash_addr_regval(unsigned long index, unsigned long num_entries)
3048{
3049 return ((u64)index | (num_entries == 1 ?
3050 HASH_TBL_ADDR_AUTOINC : 0));
3051}
3052
3053#if 0
3054static int hash_read(struct niu *np, unsigned long partition,
3055 unsigned long index, unsigned long num_entries,
3056 u64 *data)
3057{
3058 u64 val = hash_addr_regval(index, num_entries);
3059 unsigned long i;
3060
3061 if (partition >= FCRAM_NUM_PARTITIONS ||
3062 index + num_entries > FCRAM_SIZE)
3063 return -EINVAL;
3064
3065 nw64(HASH_TBL_ADDR(partition), val);
3066 for (i = 0; i < num_entries; i++)
3067 data[i] = nr64(HASH_TBL_DATA(partition));
3068
3069 return 0;
3070}
3071#endif
3072
3073static int hash_write(struct niu *np, unsigned long partition,
3074 unsigned long index, unsigned long num_entries,
3075 u64 *data)
3076{
3077 u64 val = hash_addr_regval(index, num_entries);
3078 unsigned long i;
3079
3080 if (partition >= FCRAM_NUM_PARTITIONS ||
3081 index + (num_entries * 8) > FCRAM_SIZE)
3082 return -EINVAL;
3083
3084 nw64(HASH_TBL_ADDR(partition), val);
3085 for (i = 0; i < num_entries; i++)
3086 nw64(HASH_TBL_DATA(partition), data[i]);
3087
3088 return 0;
3089}
3090
3091static void fflp_reset(struct niu *np)
3092{
3093 u64 val;
3094
3095 nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST);
3096 udelay(10);
3097 nw64(FFLP_CFG_1, 0);
3098
3099 val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE;
3100 nw64(FFLP_CFG_1, val);
3101}
3102
3103static void fflp_set_timings(struct niu *np)
3104{
3105 u64 val = nr64(FFLP_CFG_1);
3106
3107 val &= ~FFLP_CFG_1_FFLPINITDONE;
3108 val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT);
3109 nw64(FFLP_CFG_1, val);
3110
3111 val = nr64(FFLP_CFG_1);
3112 val |= FFLP_CFG_1_FFLPINITDONE;
3113 nw64(FFLP_CFG_1, val);
3114
3115 val = nr64(FCRAM_REF_TMR);
3116 val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN);
3117 val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT);
3118 val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT);
3119 nw64(FCRAM_REF_TMR, val);
3120}
3121
3122static int fflp_set_partition(struct niu *np, u64 partition,
3123 u64 mask, u64 base, int enable)
3124{
3125 unsigned long reg;
3126 u64 val;
3127
3128 if (partition >= FCRAM_NUM_PARTITIONS ||
3129 (mask & ~(u64)0x1f) != 0 ||
3130 (base & ~(u64)0x1f) != 0)
3131 return -EINVAL;
3132
3133 reg = FLW_PRT_SEL(partition);
3134
3135 val = nr64(reg);
3136 val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE);
3137 val |= (mask << FLW_PRT_SEL_MASK_SHIFT);
3138 val |= (base << FLW_PRT_SEL_BASE_SHIFT);
3139 if (enable)
3140 val |= FLW_PRT_SEL_EXT;
3141 nw64(reg, val);
3142
3143 return 0;
3144}
3145
3146static int fflp_disable_all_partitions(struct niu *np)
3147{
3148 unsigned long i;
3149
3150 for (i = 0; i < FCRAM_NUM_PARTITIONS; i++) {
3151 int err = fflp_set_partition(np, 0, 0, 0, 0);
3152 if (err)
3153 return err;
3154 }
3155 return 0;
3156}
3157
3158static void fflp_llcsnap_enable(struct niu *np, int on)
3159{
3160 u64 val = nr64(FFLP_CFG_1);
3161
3162 if (on)
3163 val |= FFLP_CFG_1_LLCSNAP;
3164 else
3165 val &= ~FFLP_CFG_1_LLCSNAP;
3166 nw64(FFLP_CFG_1, val);
3167}
3168
3169static void fflp_errors_enable(struct niu *np, int on)
3170{
3171 u64 val = nr64(FFLP_CFG_1);
3172
3173 if (on)
3174 val &= ~FFLP_CFG_1_ERRORDIS;
3175 else
3176 val |= FFLP_CFG_1_ERRORDIS;
3177 nw64(FFLP_CFG_1, val);
3178}
3179
3180static int fflp_hash_clear(struct niu *np)
3181{
3182 struct fcram_hash_ipv4 ent;
3183 unsigned long i;
3184
3185 /* IPV4 hash entry with valid bit clear, rest is don't care. */
3186 memset(&ent, 0, sizeof(ent));
3187 ent.header = HASH_HEADER_EXT;
3188
3189 for (i = 0; i < FCRAM_SIZE; i += sizeof(ent)) {
3190 int err = hash_write(np, 0, i, 1, (u64 *) &ent);
3191 if (err)
3192 return err;
3193 }
3194 return 0;
3195}
3196
3197static int fflp_early_init(struct niu *np)
3198{
3199 struct niu_parent *parent;
3200 unsigned long flags;
3201 int err;
3202
3203 niu_lock_parent(np, flags);
3204
3205 parent = np->parent;
3206 err = 0;
3207 if (!(parent->flags & PARENT_FLGS_CLS_HWINIT)) {
a3138df9
DM		 3208 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3209 fflp_reset(np);
3210 fflp_set_timings(np);
3211 err = fflp_disable_all_partitions(np);
3212 if (err) {
f10a1f2e
JP		 3213 netif_printk(np, probe, KERN_DEBUG, np->dev,
3214 "fflp_disable_all_partitions failed, err=%d\n",
3215 err);
a3138df9
DM		 3216 goto out;
3217 }
3218 }
3219
3220 err = tcam_early_init(np);
3221 if (err) {
f10a1f2e
JP		 3222 netif_printk(np, probe, KERN_DEBUG, np->dev,
3223 "tcam_early_init failed, err=%d\n", err);
a3138df9
DM		 3224 goto out;
3225 }
3226 fflp_llcsnap_enable(np, 1);
3227 fflp_errors_enable(np, 0);
3228 nw64(H1POLY, 0);
3229 nw64(H2POLY, 0);
3230
3231 err = tcam_flush_all(np);
3232 if (err) {
f10a1f2e
JP		 3233 netif_printk(np, probe, KERN_DEBUG, np->dev,
3234 "tcam_flush_all failed, err=%d\n", err);
a3138df9
DM		 3235 goto out;
3236 }
3237 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3238 err = fflp_hash_clear(np);
3239 if (err) {
f10a1f2e
JP		 3240 netif_printk(np, probe, KERN_DEBUG, np->dev,
3241 "fflp_hash_clear failed, err=%d\n",
3242 err);
a3138df9
DM		 3243 goto out;
3244 }
3245 }
3246
3247 vlan_tbl_clear(np);
3248
a3138df9
DM		 3249 parent->flags |= PARENT_FLGS_CLS_HWINIT;
3250 }
3251out:
3252 niu_unlock_parent(np, flags);
3253 return err;
3254}
3255
3256static int niu_set_flow_key(struct niu *np, unsigned long class_code, u64 key)
3257{
3258 if (class_code < CLASS_CODE_USER_PROG1 ||
3259 class_code > CLASS_CODE_SCTP_IPV6)
3260 return -EINVAL;
3261
3262 nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3263 return 0;
3264}
3265
3266static int niu_set_tcam_key(struct niu *np, unsigned long class_code, u64 key)
3267{
3268 if (class_code < CLASS_CODE_USER_PROG1 ||
3269 class_code > CLASS_CODE_SCTP_IPV6)
3270 return -EINVAL;
3271
3272 nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3273 return 0;
3274}
3275
2d96cf8c
SB		 3276/* Entries for the ports are interleaved in the TCAM */
3277static u16 tcam_get_index(struct niu *np, u16 idx)
3278{
3279 /* One entry reserved for IP fragment rule */
3280 if (idx >= (np->clas.tcam_sz - 1))
3281 idx = 0;
3282 return (np->clas.tcam_top + ((idx+1) * np->parent->num_ports));
3283}
3284
3285static u16 tcam_get_size(struct niu *np)
3286{
3287 /* One entry reserved for IP fragment rule */
3288 return np->clas.tcam_sz - 1;
3289}
3290
3291static u16 tcam_get_valid_entry_cnt(struct niu *np)
3292{
3293 /* One entry reserved for IP fragment rule */
3294 return np->clas.tcam_valid_entries - 1;
3295}
3296
a3138df9
DM		 3297static void niu_rx_skb_append(struct sk_buff *skb, struct page *page,
3298 u32 offset, u32 size)
3299{
3300 int i = skb_shinfo(skb)->nr_frags;
3301 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3302
3303 frag->page = page;
3304 frag->page_offset = offset;
3305 frag->size = size;
3306
3307 skb->len += size;
3308 skb->data_len += size;
3309 skb->truesize += size;
3310
3311 skb_shinfo(skb)->nr_frags = i + 1;
3312}
3313
3314static unsigned int niu_hash_rxaddr(struct rx_ring_info *rp, u64 a)
3315{
3316 a >>= PAGE_SHIFT;
3317 a ^= (a >> ilog2(MAX_RBR_RING_SIZE));
3318
3319 return (a & (MAX_RBR_RING_SIZE - 1));
3320}
3321
3322static struct page *niu_find_rxpage(struct rx_ring_info *rp, u64 addr,
3323 struct page ***link)
3324{
3325 unsigned int h = niu_hash_rxaddr(rp, addr);
3326 struct page *p, **pp;
3327
3328 addr &= PAGE_MASK;
3329 pp = &rp->rxhash[h];
3330 for (; (p = *pp) != NULL; pp = (struct page **) &p->mapping) {
3331 if (p->index == addr) {
3332 *link = pp;
3333 break;
3334 }
3335 }
3336
3337 return p;
3338}
3339
3340static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base)
3341{
3342 unsigned int h = niu_hash_rxaddr(rp, base);
3343
3344 page->index = base;
3345 page->mapping = (struct address_space *) rp->rxhash[h];
3346 rp->rxhash[h] = page;
3347}
3348
3349static int niu_rbr_add_page(struct niu *np, struct rx_ring_info *rp,
3350 gfp_t mask, int start_index)
3351{
3352 struct page *page;
3353 u64 addr;
3354 int i;
3355
3356 page = alloc_page(mask);
3357 if (!page)
3358 return -ENOMEM;
3359
3360 addr = np->ops->map_page(np->device, page, 0,
3361 PAGE_SIZE, DMA_FROM_DEVICE);
3362
3363 niu_hash_page(rp, page, addr);
3364 if (rp->rbr_blocks_per_page > 1)
3365 atomic_add(rp->rbr_blocks_per_page - 1,
3366 &compound_head(page)->_count);
3367
3368 for (i = 0; i < rp->rbr_blocks_per_page; i++) {
3369 __le32 *rbr = &rp->rbr[start_index + i];
3370
3371 *rbr = cpu_to_le32(addr >> RBR_DESCR_ADDR_SHIFT);
3372 addr += rp->rbr_block_size;
3373 }
3374
3375 return 0;
3376}
3377
3378static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3379{
3380 int index = rp->rbr_index;
3381
3382 rp->rbr_pending++;
3383 if ((rp->rbr_pending % rp->rbr_blocks_per_page) == 0) {
3384 int err = niu_rbr_add_page(np, rp, mask, index);
3385
3386 if (unlikely(err)) {
3387 rp->rbr_pending--;
3388 return;
3389 }
3390
3391 rp->rbr_index += rp->rbr_blocks_per_page;
3392 BUG_ON(rp->rbr_index > rp->rbr_table_size);
3393 if (rp->rbr_index == rp->rbr_table_size)
3394 rp->rbr_index = 0;
3395
3396 if (rp->rbr_pending >= rp->rbr_kick_thresh) {
3397 nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending);
3398 rp->rbr_pending = 0;
3399 }
3400 }
3401}
3402
3403static int niu_rx_pkt_ignore(struct niu *np, struct rx_ring_info *rp)
3404{
3405 unsigned int index = rp->rcr_index;
3406 int num_rcr = 0;
3407
3408 rp->rx_dropped++;
3409 while (1) {
3410 struct page *page, **link;
3411 u64 addr, val;
3412 u32 rcr_size;
3413
3414 num_rcr++;
3415
3416 val = le64_to_cpup(&rp->rcr[index]);
3417 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3418 RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3419 page = niu_find_rxpage(rp, addr, &link);
3420
3421 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3422 RCR_ENTRY_PKTBUFSZ_SHIFT];
3423 if ((page->index + PAGE_SIZE) - rcr_size == addr) {
3424 *link = (struct page *) page->mapping;
3425 np->ops->unmap_page(np->device, page->index,
3426 PAGE_SIZE, DMA_FROM_DEVICE);
3427 page->index = 0;
3428 page->mapping = NULL;
3429 __free_page(page);
3430 rp->rbr_refill_pending++;
3431 }
3432
3433 index = NEXT_RCR(rp, index);
3434 if (!(val & RCR_ENTRY_MULTI))
3435 break;
3436
3437 }
3438 rp->rcr_index = index;
3439
3440 return num_rcr;
3441}
3442
4099e012
DM		 3443static int niu_process_rx_pkt(struct napi_struct *napi, struct niu *np,
3444 struct rx_ring_info *rp)
a3138df9
DM		 3445{
3446 unsigned int index = rp->rcr_index;
3447 struct sk_buff *skb;
3448 int len, num_rcr;
3449
3450 skb = netdev_alloc_skb(np->dev, RX_SKB_ALLOC_SIZE);
3451 if (unlikely(!skb))
3452 return niu_rx_pkt_ignore(np, rp);
3453
3454 num_rcr = 0;
3455 while (1) {
3456 struct page *page, **link;
3457 u32 rcr_size, append_size;
3458 u64 addr, val, off;
3459
3460 num_rcr++;
3461
3462 val = le64_to_cpup(&rp->rcr[index]);
3463
3464 len = (val & RCR_ENTRY_L2_LEN) >>
3465 RCR_ENTRY_L2_LEN_SHIFT;
3466 len -= ETH_FCS_LEN;
3467
3468 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3469 RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3470 page = niu_find_rxpage(rp, addr, &link);
3471
3472 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3473 RCR_ENTRY_PKTBUFSZ_SHIFT];
3474
3475 off = addr & ~PAGE_MASK;
3476 append_size = rcr_size;
3477 if (num_rcr == 1) {
3478 int ptype;
3479
3480 off += 2;
3481 append_size -= 2;
3482
3483 ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT);
3484 if ((ptype == RCR_PKT_TYPE_TCP ||
3485 ptype == RCR_PKT_TYPE_UDP) &&
3486 !(val & (RCR_ENTRY_NOPORT |
3487 RCR_ENTRY_ERROR)))
3488 skb->ip_summed = CHECKSUM_UNNECESSARY;
3489 else
3490 skb->ip_summed = CHECKSUM_NONE;
3491 }
3492 if (!(val & RCR_ENTRY_MULTI))
3493 append_size = len - skb->len;
3494
3495 niu_rx_skb_append(skb, page, off, append_size);
3496 if ((page->index + rp->rbr_block_size) - rcr_size == addr) {
3497 *link = (struct page *) page->mapping;
3498 np->ops->unmap_page(np->device, page->index,
3499 PAGE_SIZE, DMA_FROM_DEVICE);
3500 page->index = 0;
3501 page->mapping = NULL;
3502 rp->rbr_refill_pending++;
3503 } else
3504 get_page(page);
3505
3506 index = NEXT_RCR(rp, index);
3507 if (!(val & RCR_ENTRY_MULTI))
3508 break;
3509
3510 }
3511 rp->rcr_index = index;
3512
3513 skb_reserve(skb, NET_IP_ALIGN);
845de8af 3514 __pskb_pull_tail(skb, min(len, VLAN_ETH_HLEN));
a3138df9
DM		 3515
3516 rp->rx_packets++;
3517 rp->rx_bytes += skb->len;
3518
3519 skb->protocol = eth_type_trans(skb, np->dev);
0c8dfc83 3520 skb_record_rx_queue(skb, rp->rx_channel);
4099e012 3521 napi_gro_receive(napi, skb);
a3138df9
DM		 3522
3523 return num_rcr;
3524}
3525
3526static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3527{
3528 int blocks_per_page = rp->rbr_blocks_per_page;
3529 int err, index = rp->rbr_index;
3530
3531 err = 0;
3532 while (index < (rp->rbr_table_size - blocks_per_page)) {
3533 err = niu_rbr_add_page(np, rp, mask, index);
3534 if (err)
3535 break;
3536
3537 index += blocks_per_page;
3538 }
3539
3540 rp->rbr_index = index;
3541 return err;
3542}
3543
3544static void niu_rbr_free(struct niu *np, struct rx_ring_info *rp)
3545{
3546 int i;
3547
3548 for (i = 0; i < MAX_RBR_RING_SIZE; i++) {
3549 struct page *page;
3550
3551 page = rp->rxhash[i];
3552 while (page) {
3553 struct page *next = (struct page *) page->mapping;
3554 u64 base = page->index;
3555
3556 np->ops->unmap_page(np->device, base, PAGE_SIZE,
3557 DMA_FROM_DEVICE);
3558 page->index = 0;
3559 page->mapping = NULL;
3560
3561 __free_page(page);
3562
3563 page = next;
3564 }
3565 }
3566
3567 for (i = 0; i < rp->rbr_table_size; i++)
3568 rp->rbr[i] = cpu_to_le32(0);
3569 rp->rbr_index = 0;
3570}
3571
3572static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx)
3573{
3574 struct tx_buff_info *tb = &rp->tx_buffs[idx];
3575 struct sk_buff *skb = tb->skb;
3576 struct tx_pkt_hdr *tp;
3577 u64 tx_flags;
3578 int i, len;
3579
3580 tp = (struct tx_pkt_hdr *) skb->data;
3581 tx_flags = le64_to_cpup(&tp->flags);
3582
3583 rp->tx_packets++;
3584 rp->tx_bytes += (((tx_flags & TXHDR_LEN) >> TXHDR_LEN_SHIFT) -
3585 ((tx_flags & TXHDR_PAD) / 2));
3586
3587 len = skb_headlen(skb);
3588 np->ops->unmap_single(np->device, tb->mapping,
3589 len, DMA_TO_DEVICE);
3590
3591 if (le64_to_cpu(rp->descr[idx]) & TX_DESC_MARK)
3592 rp->mark_pending--;
3593
3594 tb->skb = NULL;
3595 do {
3596 idx = NEXT_TX(rp, idx);
3597 len -= MAX_TX_DESC_LEN;
3598 } while (len > 0);
3599
3600 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3601 tb = &rp->tx_buffs[idx];
3602 BUG_ON(tb->skb != NULL);
3603 np->ops->unmap_page(np->device, tb->mapping,
3604 skb_shinfo(skb)->frags[i].size,
3605 DMA_TO_DEVICE);
3606 idx = NEXT_TX(rp, idx);
3607 }
3608
3609 dev_kfree_skb(skb);
3610
3611 return idx;
3612}
3613
3614#define NIU_TX_WAKEUP_THRESH(rp) ((rp)->pending / 4)
3615
3616static void niu_tx_work(struct niu *np, struct tx_ring_info *rp)
3617{
b4c21639 3618 struct netdev_queue *txq;
a3138df9 3619 u16 pkt_cnt, tmp;
b4c21639 3620 int cons, index;
a3138df9
DM		 3621 u64 cs;
3622
b4c21639
DM		 3623 index = (rp - np->tx_rings);
3624 txq = netdev_get_tx_queue(np->dev, index);
3625
a3138df9
DM		 3626 cs = rp->tx_cs;
3627 if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK))))
3628 goto out;
3629
3630 tmp = pkt_cnt = (cs & TX_CS_PKT_CNT) >> TX_CS_PKT_CNT_SHIFT;
3631 pkt_cnt = (pkt_cnt - rp->last_pkt_cnt) &
3632 (TX_CS_PKT_CNT >> TX_CS_PKT_CNT_SHIFT);
3633
3634 rp->last_pkt_cnt = tmp;
3635
3636 cons = rp->cons;
3637
f10a1f2e
JP		 3638 netif_printk(np, tx_done, KERN_DEBUG, np->dev,
3639 "%s() pkt_cnt[%u] cons[%d]\n", __func__, pkt_cnt, cons);
a3138df9
DM		 3640
3641 while (pkt_cnt--)
3642 cons = release_tx_packet(np, rp, cons);
3643
3644 rp->cons = cons;
3645 smp_mb();
3646
3647out:
b4c21639 3648 if (unlikely(netif_tx_queue_stopped(txq) &&
a3138df9 3649 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) {
b4c21639
DM		 3650 __netif_tx_lock(txq, smp_processor_id());
3651 if (netif_tx_queue_stopped(txq) &&
a3138df9 3652 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))
b4c21639
DM		 3653 netif_tx_wake_queue(txq);
3654 __netif_tx_unlock(txq);
a3138df9
DM		 3655 }
3656}
3657
b8a606b8
JDB		 3658static inline void niu_sync_rx_discard_stats(struct niu *np,
3659 struct rx_ring_info *rp,
3660 const int limit)
3661{
3662 /* This elaborate scheme is needed for reading the RX discard
3663 * counters, as they are only 16-bit and can overflow quickly,
3664 * and because the overflow indication bit is not usable as
3665 * the counter value does not wrap, but remains at max value
3666 * 0xFFFF.
3667 *
3668 * In theory and in practice counters can be lost in between
3669 * reading nr64() and clearing the counter nw64(). For this
3670 * reason, the number of counter clearings nw64() is
3671 * limited/reduced though the limit parameter.
3672 */
3673 int rx_channel = rp->rx_channel;
3674 u32 misc, wred;
3675
3676 /* RXMISC (Receive Miscellaneous Discard Count), covers the
3677 * following discard events: IPP (Input Port Process),
3678 * FFLP/TCAM, Full RCR (Receive Completion Ring) RBR (Receive
3679 * Block Ring) prefetch buffer is empty.
3680 */
3681 misc = nr64(RXMISC(rx_channel));
3682 if (unlikely((misc & RXMISC_COUNT) > limit)) {
3683 nw64(RXMISC(rx_channel), 0);
3684 rp->rx_errors += misc & RXMISC_COUNT;
3685
3686 if (unlikely(misc & RXMISC_OFLOW))
f10a1f2e
JP		 3687 dev_err(np->device, "rx-%d: Counter overflow RXMISC discard\n",
3688 rx_channel);
d231776f 3689
f10a1f2e
JP		 3690 netif_printk(np, rx_err, KERN_DEBUG, np->dev,
3691 "rx-%d: MISC drop=%u over=%u\n",
3692 rx_channel, misc, misc-limit);
b8a606b8
JDB		 3693 }
3694
3695 /* WRED (Weighted Random Early Discard) by hardware */
3696 wred = nr64(RED_DIS_CNT(rx_channel));
3697 if (unlikely((wred & RED_DIS_CNT_COUNT) > limit)) {
3698 nw64(RED_DIS_CNT(rx_channel), 0);
3699 rp->rx_dropped += wred & RED_DIS_CNT_COUNT;
3700
3701 if (unlikely(wred & RED_DIS_CNT_OFLOW))
f10a1f2e 3702 dev_err(np->device, "rx-%d: Counter overflow WRED discard\n", rx_channel);
d231776f 3703
f10a1f2e
JP		 3704 netif_printk(np, rx_err, KERN_DEBUG, np->dev,
3705 "rx-%d: WRED drop=%u over=%u\n",
3706 rx_channel, wred, wred-limit);
b8a606b8
JDB		 3707 }
3708}
3709
4099e012
DM		 3710static int niu_rx_work(struct napi_struct *napi, struct niu *np,
3711 struct rx_ring_info *rp, int budget)
a3138df9
DM		 3712{
3713 int qlen, rcr_done = 0, work_done = 0;
3714 struct rxdma_mailbox *mbox = rp->mbox;
3715 u64 stat;
3716
3717#if 1
3718 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3719 qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN;
3720#else
3721 stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
3722 qlen = (le64_to_cpup(&mbox->rcrstat_a) & RCRSTAT_A_QLEN);
3723#endif
3724 mbox->rx_dma_ctl_stat = 0;
3725 mbox->rcrstat_a = 0;
3726
f10a1f2e
JP		 3727 netif_printk(np, rx_status, KERN_DEBUG, np->dev,
3728 "%s(chan[%d]), stat[%llx] qlen=%d\n",
3729 __func__, rp->rx_channel, (unsigned long long)stat, qlen);
a3138df9
DM		 3730
3731 rcr_done = work_done = 0;
3732 qlen = min(qlen, budget);
3733 while (work_done < qlen) {
4099e012 3734 rcr_done += niu_process_rx_pkt(napi, np, rp);
a3138df9
DM		 3735 work_done++;
3736 }
3737
3738 if (rp->rbr_refill_pending >= rp->rbr_kick_thresh) {
3739 unsigned int i;
3740
3741 for (i = 0; i < rp->rbr_refill_pending; i++)
3742 niu_rbr_refill(np, rp, GFP_ATOMIC);
3743 rp->rbr_refill_pending = 0;
3744 }
3745
3746 stat = (RX_DMA_CTL_STAT_MEX |
3747 ((u64)work_done << RX_DMA_CTL_STAT_PKTREAD_SHIFT) |
3748 ((u64)rcr_done << RX_DMA_CTL_STAT_PTRREAD_SHIFT));
3749
3750 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat);
3751
e98def1f
JDB		 3752 /* Only sync discards stats when qlen indicate potential for drops */
3753 if (qlen > 10)
3754 niu_sync_rx_discard_stats(np, rp, 0x7FFF);
b8a606b8 3755
a3138df9
DM		 3756 return work_done;
3757}
3758
3759static int niu_poll_core(struct niu *np, struct niu_ldg *lp, int budget)
3760{
3761 u64 v0 = lp->v0;
3762 u32 tx_vec = (v0 >> 32);
3763 u32 rx_vec = (v0 & 0xffffffff);
3764 int i, work_done = 0;
3765
f10a1f2e
JP		 3766 netif_printk(np, intr, KERN_DEBUG, np->dev,
3767 "%s() v0[%016llx]\n", __func__, (unsigned long long)v0);
a3138df9
DM		 3768
3769 for (i = 0; i < np->num_tx_rings; i++) {
3770 struct tx_ring_info *rp = &np->tx_rings[i];
3771 if (tx_vec & (1 << rp->tx_channel))
3772 niu_tx_work(np, rp);
3773 nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0);
3774 }
3775
3776 for (i = 0; i < np->num_rx_rings; i++) {
3777 struct rx_ring_info *rp = &np->rx_rings[i];
3778
3779 if (rx_vec & (1 << rp->rx_channel)) {
3780 int this_work_done;
3781
4099e012 3782 this_work_done = niu_rx_work(&lp->napi, np, rp,
a3138df9
DM		 3783 budget);
3784
3785 budget -= this_work_done;
3786 work_done += this_work_done;
3787 }
3788 nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0);
3789 }
3790
3791 return work_done;
3792}
3793
3794static int niu_poll(struct napi_struct *napi, int budget)
3795{
3796 struct niu_ldg *lp = container_of(napi, struct niu_ldg, napi);
3797 struct niu *np = lp->np;
3798 int work_done;
3799
3800 work_done = niu_poll_core(np, lp, budget);
3801
3802 if (work_done < budget) {
288379f0 3803 napi_complete(napi);
a3138df9
DM		 3804 niu_ldg_rearm(np, lp, 1);
3805 }
3806 return work_done;
3807}
3808
3809static void niu_log_rxchan_errors(struct niu *np, struct rx_ring_info *rp,
3810 u64 stat)
3811{
f10a1f2e 3812 netdev_err(np->dev, "RX channel %u errors ( ", rp->rx_channel);
a3138df9
DM		 3813
3814 if (stat & RX_DMA_CTL_STAT_RBR_TMOUT)
f10a1f2e 3815 pr_cont("RBR_TMOUT ");
a3138df9 3816 if (stat & RX_DMA_CTL_STAT_RSP_CNT_ERR)
f10a1f2e 3817 pr_cont("RSP_CNT ");
a3138df9 3818 if (stat & RX_DMA_CTL_STAT_BYTE_EN_BUS)
f10a1f2e 3819 pr_cont("BYTE_EN_BUS ");
a3138df9 3820 if (stat & RX_DMA_CTL_STAT_RSP_DAT_ERR)
f10a1f2e 3821 pr_cont("RSP_DAT ");
a3138df9 3822 if (stat & RX_DMA_CTL_STAT_RCR_ACK_ERR)
f10a1f2e 3823 pr_cont("RCR_ACK ");
a3138df9 3824 if (stat & RX_DMA_CTL_STAT_RCR_SHA_PAR)
f10a1f2e 3825 pr_cont("RCR_SHA_PAR ");
a3138df9 3826 if (stat & RX_DMA_CTL_STAT_RBR_PRE_PAR)
f10a1f2e 3827 pr_cont("RBR_PRE_PAR ");
a3138df9 3828 if (stat & RX_DMA_CTL_STAT_CONFIG_ERR)
f10a1f2e 3829 pr_cont("CONFIG ");
a3138df9 3830 if (stat & RX_DMA_CTL_STAT_RCRINCON)
f10a1f2e 3831 pr_cont("RCRINCON ");
a3138df9 3832 if (stat & RX_DMA_CTL_STAT_RCRFULL)
f10a1f2e 3833 pr_cont("RCRFULL ");
a3138df9 3834 if (stat & RX_DMA_CTL_STAT_RBRFULL)
f10a1f2e 3835 pr_cont("RBRFULL ");
a3138df9 3836 if (stat & RX_DMA_CTL_STAT_RBRLOGPAGE)
f10a1f2e 3837 pr_cont("RBRLOGPAGE ");
a3138df9 3838 if (stat & RX_DMA_CTL_STAT_CFIGLOGPAGE)
f10a1f2e 3839 pr_cont("CFIGLOGPAGE ");
a3138df9 3840 if (stat & RX_DMA_CTL_STAT_DC_FIFO_ERR)
f10a1f2e 3841 pr_cont("DC_FIDO ");
a3138df9 3842
f10a1f2e 3843 pr_cont(")\n");
a3138df9
DM		 3844}
3845
3846static int niu_rx_error(struct niu *np, struct rx_ring_info *rp)
3847{
3848 u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3849 int err = 0;
3850
a3138df9
DM		 3851
3852 if (stat & (RX_DMA_CTL_STAT_CHAN_FATAL |
3853 RX_DMA_CTL_STAT_PORT_FATAL))
3854 err = -EINVAL;
3855
406f353c 3856 if (err) {
f10a1f2e
JP		 3857 netdev_err(np->dev, "RX channel %u error, stat[%llx]\n",
3858 rp->rx_channel,
3859 (unsigned long long) stat);
406f353c
MW		 3860
3861 niu_log_rxchan_errors(np, rp, stat);
3862 }
3863
a3138df9
DM		 3864 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
3865 stat & RX_DMA_CTL_WRITE_CLEAR_ERRS);
3866
3867 return err;
3868}
3869
3870static void niu_log_txchan_errors(struct niu *np, struct tx_ring_info *rp,
3871 u64 cs)
3872{
f10a1f2e 3873 netdev_err(np->dev, "TX channel %u errors ( ", rp->tx_channel);
a3138df9
DM		 3874
3875 if (cs & TX_CS_MBOX_ERR)
f10a1f2e 3876 pr_cont("MBOX ");
a3138df9 3877 if (cs & TX_CS_PKT_SIZE_ERR)
f10a1f2e 3878 pr_cont("PKT_SIZE ");
a3138df9 3879 if (cs & TX_CS_TX_RING_OFLOW)
f10a1f2e 3880 pr_cont("TX_RING_OFLOW ");
a3138df9 3881 if (cs & TX_CS_PREF_BUF_PAR_ERR)
f10a1f2e 3882 pr_cont("PREF_BUF_PAR ");
a3138df9 3883 if (cs & TX_CS_NACK_PREF)
f10a1f2e 3884 pr_cont("NACK_PREF ");
a3138df9 3885 if (cs & TX_CS_NACK_PKT_RD)
f10a1f2e 3886 pr_cont("NACK_PKT_RD ");
a3138df9 3887 if (cs & TX_CS_CONF_PART_ERR)
f10a1f2e 3888 pr_cont("CONF_PART ");
a3138df9 3889 if (cs & TX_CS_PKT_PRT_ERR)
f10a1f2e 3890 pr_cont("PKT_PTR ");
a3138df9 3891
f10a1f2e 3892 pr_cont(")\n");
a3138df9
DM		 3893}
3894
3895static int niu_tx_error(struct niu *np, struct tx_ring_info *rp)
3896{
3897 u64 cs, logh, logl;
3898
3899 cs = nr64(TX_CS(rp->tx_channel));
3900 logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel));
3901 logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel));
3902
f10a1f2e
JP		 3903 netdev_err(np->dev, "TX channel %u error, cs[%llx] logh[%llx] logl[%llx]\n",
3904 rp->tx_channel,
3905 (unsigned long long)cs,
3906 (unsigned long long)logh,
3907 (unsigned long long)logl);
a3138df9
DM		 3908
3909 niu_log_txchan_errors(np, rp, cs);
3910
3911 return -ENODEV;
3912}
3913
3914static int niu_mif_interrupt(struct niu *np)
3915{
3916 u64 mif_status = nr64(MIF_STATUS);
3917 int phy_mdint = 0;
3918
3919 if (np->flags & NIU_FLAGS_XMAC) {
3920 u64 xrxmac_stat = nr64_mac(XRXMAC_STATUS);
3921
3922 if (xrxmac_stat & XRXMAC_STATUS_PHY_MDINT)
3923 phy_mdint = 1;
3924 }
3925
f10a1f2e
JP		 3926 netdev_err(np->dev, "MIF interrupt, stat[%llx] phy_mdint(%d)\n",
3927 (unsigned long long)mif_status, phy_mdint);
a3138df9
DM		 3928
3929 return -ENODEV;
3930}
3931
3932static void niu_xmac_interrupt(struct niu *np)
3933{
3934 struct niu_xmac_stats *mp = &np->mac_stats.xmac;
3935 u64 val;
3936
3937 val = nr64_mac(XTXMAC_STATUS);
3938 if (val & XTXMAC_STATUS_FRAME_CNT_EXP)
3939 mp->tx_frames += TXMAC_FRM_CNT_COUNT;
3940 if (val & XTXMAC_STATUS_BYTE_CNT_EXP)
3941 mp->tx_bytes += TXMAC_BYTE_CNT_COUNT;
3942 if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR)
3943 mp->tx_fifo_errors++;
3944 if (val & XTXMAC_STATUS_TXMAC_OFLOW)
3945 mp->tx_overflow_errors++;
3946 if (val & XTXMAC_STATUS_MAX_PSIZE_ERR)
3947 mp->tx_max_pkt_size_errors++;
3948 if (val & XTXMAC_STATUS_TXMAC_UFLOW)
3949 mp->tx_underflow_errors++;
3950
3951 val = nr64_mac(XRXMAC_STATUS);
3952 if (val & XRXMAC_STATUS_LCL_FLT_STATUS)
3953 mp->rx_local_faults++;
3954 if (val & XRXMAC_STATUS_RFLT_DET)
3955 mp->rx_remote_faults++;
3956 if (val & XRXMAC_STATUS_LFLT_CNT_EXP)
3957 mp->rx_link_faults += LINK_FAULT_CNT_COUNT;
3958 if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP)
3959 mp->rx_align_errors += RXMAC_ALIGN_ERR_CNT_COUNT;
3960 if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP)
3961 mp->rx_frags += RXMAC_FRAG_CNT_COUNT;
3962 if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP)
3963 mp->rx_mcasts += RXMAC_MC_FRM_CNT_COUNT;
3964 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3965 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3966 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3967 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3968 if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP)
3969 mp->rx_hist_cnt1 += RXMAC_HIST_CNT1_COUNT;
3970 if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP)
3971 mp->rx_hist_cnt2 += RXMAC_HIST_CNT2_COUNT;
3972 if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP)
3973 mp->rx_hist_cnt3 += RXMAC_HIST_CNT3_COUNT;
3974 if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP)
3975 mp->rx_hist_cnt4 += RXMAC_HIST_CNT4_COUNT;
3976 if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP)
3977 mp->rx_hist_cnt5 += RXMAC_HIST_CNT5_COUNT;
3978 if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP)
3979 mp->rx_hist_cnt6 += RXMAC_HIST_CNT6_COUNT;
3980 if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP)
3981 mp->rx_hist_cnt7 += RXMAC_HIST_CNT7_COUNT;
176edd52 3982 if (val & XRXMAC_STATUS_RXOCTET_CNT_EXP)
a3138df9
DM		 3983 mp->rx_octets += RXMAC_BT_CNT_COUNT;
3984 if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP)
3985 mp->rx_code_violations += RXMAC_CD_VIO_CNT_COUNT;
3986 if (val & XRXMAC_STATUS_LENERR_CNT_EXP)
3987 mp->rx_len_errors += RXMAC_MPSZER_CNT_COUNT;
3988 if (val & XRXMAC_STATUS_CRCERR_CNT_EXP)
3989 mp->rx_crc_errors += RXMAC_CRC_ER_CNT_COUNT;
3990 if (val & XRXMAC_STATUS_RXUFLOW)
3991 mp->rx_underflows++;
3992 if (val & XRXMAC_STATUS_RXOFLOW)
3993 mp->rx_overflows++;
3994
3995 val = nr64_mac(XMAC_FC_STAT);
3996 if (val & XMAC_FC_STAT_TX_MAC_NPAUSE)
3997 mp->pause_off_state++;
3998 if (val & XMAC_FC_STAT_TX_MAC_PAUSE)
3999 mp->pause_on_state++;
4000 if (val & XMAC_FC_STAT_RX_MAC_RPAUSE)
4001 mp->pause_received++;
4002}
4003
4004static void niu_bmac_interrupt(struct niu *np)
4005{
4006 struct niu_bmac_stats *mp = &np->mac_stats.bmac;
4007 u64 val;
4008
4009 val = nr64_mac(BTXMAC_STATUS);
4010 if (val & BTXMAC_STATUS_UNDERRUN)
4011 mp->tx_underflow_errors++;
4012 if (val & BTXMAC_STATUS_MAX_PKT_ERR)
4013 mp->tx_max_pkt_size_errors++;
4014 if (val & BTXMAC_STATUS_BYTE_CNT_EXP)
4015 mp->tx_bytes += BTXMAC_BYTE_CNT_COUNT;
4016 if (val & BTXMAC_STATUS_FRAME_CNT_EXP)
4017 mp->tx_frames += BTXMAC_FRM_CNT_COUNT;
4018
4019 val = nr64_mac(BRXMAC_STATUS);
4020 if (val & BRXMAC_STATUS_OVERFLOW)
4021 mp->rx_overflows++;
4022 if (val & BRXMAC_STATUS_FRAME_CNT_EXP)
4023 mp->rx_frames += BRXMAC_FRAME_CNT_COUNT;
4024 if (val & BRXMAC_STATUS_ALIGN_ERR_EXP)
4025 mp->rx_align_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4026 if (val & BRXMAC_STATUS_CRC_ERR_EXP)
4027 mp->rx_crc_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4028 if (val & BRXMAC_STATUS_LEN_ERR_EXP)
4029 mp->rx_len_errors += BRXMAC_CODE_VIOL_ERR_CNT_COUNT;
4030
4031 val = nr64_mac(BMAC_CTRL_STATUS);
4032 if (val & BMAC_CTRL_STATUS_NOPAUSE)
4033 mp->pause_off_state++;
4034 if (val & BMAC_CTRL_STATUS_PAUSE)
4035 mp->pause_on_state++;
4036 if (val & BMAC_CTRL_STATUS_PAUSE_RECV)
4037 mp->pause_received++;
4038}
4039
4040static int niu_mac_interrupt(struct niu *np)
4041{
4042 if (np->flags & NIU_FLAGS_XMAC)
4043 niu_xmac_interrupt(np);
4044 else
4045 niu_bmac_interrupt(np);
4046
4047 return 0;
4048}
4049
4050static void niu_log_device_error(struct niu *np, u64 stat)
4051{
f10a1f2e 4052 netdev_err(np->dev, "Core device errors ( ");
a3138df9
DM		 4053
4054 if (stat & SYS_ERR_MASK_META2)
f10a1f2e 4055 pr_cont("META2 ");
a3138df9 4056 if (stat & SYS_ERR_MASK_META1)
f10a1f2e 4057 pr_cont("META1 ");
a3138df9 4058 if (stat & SYS_ERR_MASK_PEU)
f10a1f2e 4059 pr_cont("PEU ");
a3138df9 4060 if (stat & SYS_ERR_MASK_TXC)
f10a1f2e 4061 pr_cont("TXC ");
a3138df9 4062 if (stat & SYS_ERR_MASK_RDMC)
f10a1f2e 4063 pr_cont("RDMC ");
a3138df9 4064 if (stat & SYS_ERR_MASK_TDMC)
f10a1f2e 4065 pr_cont("TDMC ");
a3138df9 4066 if (stat & SYS_ERR_MASK_ZCP)
f10a1f2e 4067 pr_cont("ZCP ");
a3138df9 4068 if (stat & SYS_ERR_MASK_FFLP)
f10a1f2e 4069 pr_cont("FFLP ");
a3138df9 4070 if (stat & SYS_ERR_MASK_IPP)
f10a1f2e 4071 pr_cont("IPP ");
a3138df9 4072 if (stat & SYS_ERR_MASK_MAC)
f10a1f2e 4073 pr_cont("MAC ");
a3138df9 4074 if (stat & SYS_ERR_MASK_SMX)
f10a1f2e 4075 pr_cont("SMX ");
a3138df9 4076
f10a1f2e 4077 pr_cont(")\n");
a3138df9
DM		 4078}
4079
4080static int niu_device_error(struct niu *np)
4081{
4082 u64 stat = nr64(SYS_ERR_STAT);
4083
f10a1f2e
JP		 4084 netdev_err(np->dev, "Core device error, stat[%llx]\n",
4085 (unsigned long long)stat);
a3138df9
DM		 4086
4087 niu_log_device_error(np, stat);
4088
4089 return -ENODEV;
4090}
4091
406f353c
MW		 4092static int niu_slowpath_interrupt(struct niu *np, struct niu_ldg *lp,
4093 u64 v0, u64 v1, u64 v2)
a3138df9 4094{
406f353c 4095
a3138df9
DM		 4096 int i, err = 0;
4097
406f353c
MW		 4098 lp->v0 = v0;
4099 lp->v1 = v1;
4100 lp->v2 = v2;
4101
a3138df9
DM		 4102 if (v1 & 0x00000000ffffffffULL) {
4103 u32 rx_vec = (v1 & 0xffffffff);
4104
4105 for (i = 0; i < np->num_rx_rings; i++) {
4106 struct rx_ring_info *rp = &np->rx_rings[i];
4107
4108 if (rx_vec & (1 << rp->rx_channel)) {
4109 int r = niu_rx_error(np, rp);
406f353c 4110 if (r) {
a3138df9 4111 err = r;
406f353c
MW		 4112 } else {
4113 if (!v0)
4114 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
4115 RX_DMA_CTL_STAT_MEX);
4116 }
a3138df9
DM		 4117 }
4118 }
4119 }
4120 if (v1 & 0x7fffffff00000000ULL) {
4121 u32 tx_vec = (v1 >> 32) & 0x7fffffff;
4122
4123 for (i = 0; i < np->num_tx_rings; i++) {
4124 struct tx_ring_info *rp = &np->tx_rings[i];
4125
4126 if (tx_vec & (1 << rp->tx_channel)) {
4127 int r = niu_tx_error(np, rp);
4128 if (r)
4129 err = r;
4130 }
4131 }
4132 }
4133 if ((v0 | v1) & 0x8000000000000000ULL) {
4134 int r = niu_mif_interrupt(np);
4135 if (r)
4136 err = r;
4137 }
4138 if (v2) {
4139 if (v2 & 0x01ef) {
4140 int r = niu_mac_interrupt(np);
4141 if (r)
4142 err = r;
4143 }
4144 if (v2 & 0x0210) {
4145 int r = niu_device_error(np);
4146 if (r)
4147 err = r;
4148 }
4149 }
4150
4151 if (err)
4152 niu_enable_interrupts(np, 0);
4153
406f353c 4154 return err;
a3138df9
DM		 4155}
4156
4157static void niu_rxchan_intr(struct niu *np, struct rx_ring_info *rp,
4158 int ldn)
4159{
4160 struct rxdma_mailbox *mbox = rp->mbox;
4161 u64 stat_write, stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
4162
4163 stat_write = (RX_DMA_CTL_STAT_RCRTHRES |
4164 RX_DMA_CTL_STAT_RCRTO);
4165 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write);
4166
f10a1f2e
JP		 4167 netif_printk(np, intr, KERN_DEBUG, np->dev,
4168 "%s() stat[%llx]\n", __func__, (unsigned long long)stat);
a3138df9
DM		 4169}
4170
4171static void niu_txchan_intr(struct niu *np, struct tx_ring_info *rp,
4172 int ldn)
4173{
4174 rp->tx_cs = nr64(TX_CS(rp->tx_channel));
4175
f10a1f2e
JP		 4176 netif_printk(np, intr, KERN_DEBUG, np->dev,
4177 "%s() cs[%llx]\n", __func__, (unsigned long long)rp->tx_cs);
a3138df9
DM		 4178}
4179
4180static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0)
4181{
4182 struct niu_parent *parent = np->parent;
4183 u32 rx_vec, tx_vec;
4184 int i;
4185
4186 tx_vec = (v0 >> 32);
4187 rx_vec = (v0 & 0xffffffff);
4188
4189 for (i = 0; i < np->num_rx_rings; i++) {
4190 struct rx_ring_info *rp = &np->rx_rings[i];
4191 int ldn = LDN_RXDMA(rp->rx_channel);
4192
4193 if (parent->ldg_map[ldn] != ldg)
4194 continue;
4195
4196 nw64(LD_IM0(ldn), LD_IM0_MASK);
4197 if (rx_vec & (1 << rp->rx_channel))
4198 niu_rxchan_intr(np, rp, ldn);
4199 }
4200
4201 for (i = 0; i < np->num_tx_rings; i++) {
4202 struct tx_ring_info *rp = &np->tx_rings[i];
4203 int ldn = LDN_TXDMA(rp->tx_channel);
4204
4205 if (parent->ldg_map[ldn] != ldg)
4206 continue;
4207
4208 nw64(LD_IM0(ldn), LD_IM0_MASK);
4209 if (tx_vec & (1 << rp->tx_channel))
4210 niu_txchan_intr(np, rp, ldn);
4211 }
4212}
4213
4214static void niu_schedule_napi(struct niu *np, struct niu_ldg *lp,
4215 u64 v0, u64 v1, u64 v2)
4216{
288379f0 4217 if (likely(napi_schedule_prep(&lp->napi))) {
a3138df9
DM		 4218 lp->v0 = v0;
4219 lp->v1 = v1;
4220 lp->v2 = v2;
4221 __niu_fastpath_interrupt(np, lp->ldg_num, v0);
288379f0 4222 __napi_schedule(&lp->napi);
a3138df9
DM		 4223 }
4224}
4225
4226static irqreturn_t niu_interrupt(int irq, void *dev_id)
4227{
4228 struct niu_ldg *lp = dev_id;
4229 struct niu *np = lp->np;
4230 int ldg = lp->ldg_num;
4231 unsigned long flags;
4232 u64 v0, v1, v2;
4233
4234 if (netif_msg_intr(np))
f10a1f2e
JP		 4235 printk(KERN_DEBUG KBUILD_MODNAME ": " "%s() ldg[%p](%d)",
4236 __func__, lp, ldg);
a3138df9
DM		 4237
4238 spin_lock_irqsave(&np->lock, flags);
4239
4240 v0 = nr64(LDSV0(ldg));
4241 v1 = nr64(LDSV1(ldg));
4242 v2 = nr64(LDSV2(ldg));
4243
4244 if (netif_msg_intr(np))
02b1bae5 4245 pr_cont(" v0[%llx] v1[%llx] v2[%llx]\n",
a3138df9
DM		 4246 (unsigned long long) v0,
4247 (unsigned long long) v1,
4248 (unsigned long long) v2);
4249
4250 if (unlikely(!v0 && !v1 && !v2)) {
4251 spin_unlock_irqrestore(&np->lock, flags);
4252 return IRQ_NONE;
4253 }
4254
4255 if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) {
406f353c 4256 int err = niu_slowpath_interrupt(np, lp, v0, v1, v2);
a3138df9
DM		 4257 if (err)
4258 goto out;
4259 }
4260 if (likely(v0 & ~((u64)1 << LDN_MIF)))
4261 niu_schedule_napi(np, lp, v0, v1, v2);
4262 else
4263 niu_ldg_rearm(np, lp, 1);
4264out:
4265 spin_unlock_irqrestore(&np->lock, flags);
4266
4267 return IRQ_HANDLED;
4268}
4269
4270static void niu_free_rx_ring_info(struct niu *np, struct rx_ring_info *rp)
4271{
4272 if (rp->mbox) {
4273 np->ops->free_coherent(np->device,
4274 sizeof(struct rxdma_mailbox),
4275 rp->mbox, rp->mbox_dma);
4276 rp->mbox = NULL;
4277 }
4278 if (rp->rcr) {
4279 np->ops->free_coherent(np->device,
4280 MAX_RCR_RING_SIZE * sizeof(__le64),
4281 rp->rcr, rp->rcr_dma);
4282 rp->rcr = NULL;
4283 rp->rcr_table_size = 0;
4284 rp->rcr_index = 0;
4285 }
4286 if (rp->rbr) {
4287 niu_rbr_free(np, rp);
4288
4289 np->ops->free_coherent(np->device,
4290 MAX_RBR_RING_SIZE * sizeof(__le32),
4291 rp->rbr, rp->rbr_dma);
4292 rp->rbr = NULL;
4293 rp->rbr_table_size = 0;
4294 rp->rbr_index = 0;
4295 }
4296 kfree(rp->rxhash);
4297 rp->rxhash = NULL;
4298}
4299
4300static void niu_free_tx_ring_info(struct niu *np, struct tx_ring_info *rp)
4301{
4302 if (rp->mbox) {
4303 np->ops->free_coherent(np->device,
4304 sizeof(struct txdma_mailbox),
4305 rp->mbox, rp->mbox_dma);
4306 rp->mbox = NULL;
4307 }
4308 if (rp->descr) {
4309 int i;
4310
4311 for (i = 0; i < MAX_TX_RING_SIZE; i++) {
4312 if (rp->tx_buffs[i].skb)
4313 (void) release_tx_packet(np, rp, i);
4314 }
4315
4316 np->ops->free_coherent(np->device,
4317 MAX_TX_RING_SIZE * sizeof(__le64),
4318 rp->descr, rp->descr_dma);
4319 rp->descr = NULL;
4320 rp->pending = 0;
4321 rp->prod = 0;
4322 rp->cons = 0;
4323 rp->wrap_bit = 0;
4324 }
4325}
4326
4327static void niu_free_channels(struct niu *np)
4328{
4329 int i;
4330
4331 if (np->rx_rings) {
4332 for (i = 0; i < np->num_rx_rings; i++) {
4333 struct rx_ring_info *rp = &np->rx_rings[i];
4334
4335 niu_free_rx_ring_info(np, rp);
4336 }
4337 kfree(np->rx_rings);
4338 np->rx_rings = NULL;
4339 np->num_rx_rings = 0;
4340 }
4341
4342 if (np->tx_rings) {
4343 for (i = 0; i < np->num_tx_rings; i++) {
4344 struct tx_ring_info *rp = &np->tx_rings[i];
4345
4346 niu_free_tx_ring_info(np, rp);
4347 }
4348 kfree(np->tx_rings);
4349 np->tx_rings = NULL;
4350 np->num_tx_rings = 0;
4351 }
4352}
4353
4354static int niu_alloc_rx_ring_info(struct niu *np,
4355 struct rx_ring_info *rp)
4356{
4357 BUILD_BUG_ON(sizeof(struct rxdma_mailbox) != 64);
4358
4359 rp->rxhash = kzalloc(MAX_RBR_RING_SIZE * sizeof(struct page *),
4360 GFP_KERNEL);
4361 if (!rp->rxhash)
4362 return -ENOMEM;
4363
4364 rp->mbox = np->ops->alloc_coherent(np->device,
4365 sizeof(struct rxdma_mailbox),
4366 &rp->mbox_dma, GFP_KERNEL);
4367 if (!rp->mbox)
4368 return -ENOMEM;
4369 if ((unsigned long)rp->mbox & (64UL - 1)) {
f10a1f2e
JP		 4370 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA mailbox %p\n",
4371 rp->mbox);
a3138df9
DM		 4372 return -EINVAL;
4373 }
4374
4375 rp->rcr = np->ops->alloc_coherent(np->device,
4376 MAX_RCR_RING_SIZE * sizeof(__le64),
4377 &rp->rcr_dma, GFP_KERNEL);
4378 if (!rp->rcr)
4379 return -ENOMEM;
4380 if ((unsigned long)rp->rcr & (64UL - 1)) {
f10a1f2e
JP		 4381 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RCR table %p\n",
4382 rp->rcr);
a3138df9
DM		 4383 return -EINVAL;
4384 }
4385 rp->rcr_table_size = MAX_RCR_RING_SIZE;
4386 rp->rcr_index = 0;
4387
4388 rp->rbr = np->ops->alloc_coherent(np->device,
4389 MAX_RBR_RING_SIZE * sizeof(__le32),
4390 &rp->rbr_dma, GFP_KERNEL);
4391 if (!rp->rbr)
4392 return -ENOMEM;
4393 if ((unsigned long)rp->rbr & (64UL - 1)) {
f10a1f2e
JP		 4394 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RBR table %p\n",
4395 rp->rbr);
a3138df9
DM		 4396 return -EINVAL;
4397 }
4398 rp->rbr_table_size = MAX_RBR_RING_SIZE;
4399 rp->rbr_index = 0;
4400 rp->rbr_pending = 0;
4401
4402 return 0;
4403}
4404
4405static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp)
4406{
4407 int mtu = np->dev->mtu;
4408
4409 /* These values are recommended by the HW designers for fair
4410 * utilization of DRR amongst the rings.
4411 */
4412 rp->max_burst = mtu + 32;
4413 if (rp->max_burst > 4096)
4414 rp->max_burst = 4096;
4415}
4416
4417static int niu_alloc_tx_ring_info(struct niu *np,
4418 struct tx_ring_info *rp)
4419{
4420 BUILD_BUG_ON(sizeof(struct txdma_mailbox) != 64);
4421
4422 rp->mbox = np->ops->alloc_coherent(np->device,
4423 sizeof(struct txdma_mailbox),
4424 &rp->mbox_dma, GFP_KERNEL);
4425 if (!rp->mbox)
4426 return -ENOMEM;
4427 if ((unsigned long)rp->mbox & (64UL - 1)) {
f10a1f2e
JP		 4428 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA mailbox %p\n",
4429 rp->mbox);
a3138df9
DM		 4430 return -EINVAL;
4431 }
4432
4433 rp->descr = np->ops->alloc_coherent(np->device,
4434 MAX_TX_RING_SIZE * sizeof(__le64),
4435 &rp->descr_dma, GFP_KERNEL);
4436 if (!rp->descr)
4437 return -ENOMEM;
4438 if ((unsigned long)rp->descr & (64UL - 1)) {
f10a1f2e
JP		 4439 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA descr table %p\n",
4440 rp->descr);
a3138df9
DM		 4441 return -EINVAL;
4442 }
4443
4444 rp->pending = MAX_TX_RING_SIZE;
4445 rp->prod = 0;
4446 rp->cons = 0;
4447 rp->wrap_bit = 0;
4448
4449 /* XXX make these configurable... XXX */
4450 rp->mark_freq = rp->pending / 4;
4451
4452 niu_set_max_burst(np, rp);
4453
4454 return 0;
4455}
4456
4457static void niu_size_rbr(struct niu *np, struct rx_ring_info *rp)
4458{
81429973 4459 u16 bss;
a3138df9 4460
81429973 4461 bss = min(PAGE_SHIFT, 15);
a3138df9 4462
81429973
OJ		 4463 rp->rbr_block_size = 1 << bss;
4464 rp->rbr_blocks_per_page = 1 << (PAGE_SHIFT-bss);
a3138df9
DM		 4465
4466 rp->rbr_sizes[0] = 256;
4467 rp->rbr_sizes[1] = 1024;
4468 if (np->dev->mtu > ETH_DATA_LEN) {
4469 switch (PAGE_SIZE) {
4470 case 4 * 1024:
4471 rp->rbr_sizes[2] = 4096;
4472 break;
4473
4474 default:
4475 rp->rbr_sizes[2] = 8192;
4476 break;
4477 }
4478 } else {
4479 rp->rbr_sizes[2] = 2048;
4480 }
4481 rp->rbr_sizes[3] = rp->rbr_block_size;
4482}
4483
4484static int niu_alloc_channels(struct niu *np)
4485{
4486 struct niu_parent *parent = np->parent;
4487 int first_rx_channel, first_tx_channel;
4488 int i, port, err;
4489
4490 port = np->port;
4491 first_rx_channel = first_tx_channel = 0;
4492 for (i = 0; i < port; i++) {
4493 first_rx_channel += parent->rxchan_per_port[i];
4494 first_tx_channel += parent->txchan_per_port[i];
4495 }
4496
4497 np->num_rx_rings = parent->rxchan_per_port[port];
4498 np->num_tx_rings = parent->txchan_per_port[port];
4499
b4c21639
DM		 4500 np->dev->real_num_tx_queues = np->num_tx_rings;
4501
a3138df9
DM		 4502 np->rx_rings = kzalloc(np->num_rx_rings * sizeof(struct rx_ring_info),
4503 GFP_KERNEL);
4504 err = -ENOMEM;
4505 if (!np->rx_rings)
4506 goto out_err;
4507
4508 for (i = 0; i < np->num_rx_rings; i++) {
4509 struct rx_ring_info *rp = &np->rx_rings[i];
4510
4511 rp->np = np;
4512 rp->rx_channel = first_rx_channel + i;
4513
4514 err = niu_alloc_rx_ring_info(np, rp);
4515 if (err)
4516 goto out_err;
4517
4518 niu_size_rbr(np, rp);
4519
4520 /* XXX better defaults, configurable, etc... XXX */
4521 rp->nonsyn_window = 64;
4522 rp->nonsyn_threshold = rp->rcr_table_size - 64;
4523 rp->syn_window = 64;
4524 rp->syn_threshold = rp->rcr_table_size - 64;
4525 rp->rcr_pkt_threshold = 16;
4526 rp->rcr_timeout = 8;
4527 rp->rbr_kick_thresh = RBR_REFILL_MIN;
4528 if (rp->rbr_kick_thresh < rp->rbr_blocks_per_page)
4529 rp->rbr_kick_thresh = rp->rbr_blocks_per_page;
4530
4531 err = niu_rbr_fill(np, rp, GFP_KERNEL);
4532 if (err)
4533 return err;
4534 }
4535
4536 np->tx_rings = kzalloc(np->num_tx_rings * sizeof(struct tx_ring_info),
4537 GFP_KERNEL);
4538 err = -ENOMEM;
4539 if (!np->tx_rings)
4540 goto out_err;
4541
4542 for (i = 0; i < np->num_tx_rings; i++) {
4543 struct tx_ring_info *rp = &np->tx_rings[i];
4544
4545 rp->np = np;
4546 rp->tx_channel = first_tx_channel + i;
4547
4548 err = niu_alloc_tx_ring_info(np, rp);
4549 if (err)
4550 goto out_err;
4551 }
4552
4553 return 0;
4554
4555out_err:
4556 niu_free_channels(np);
4557 return err;
4558}
4559
4560static int niu_tx_cs_sng_poll(struct niu *np, int channel)
4561{
4562 int limit = 1000;
4563
4564 while (--limit > 0) {
4565 u64 val = nr64(TX_CS(channel));
4566 if (val & TX_CS_SNG_STATE)
4567 return 0;
4568 }
4569 return -ENODEV;
4570}
4571
4572static int niu_tx_channel_stop(struct niu *np, int channel)
4573{
4574 u64 val = nr64(TX_CS(channel));
4575
4576 val |= TX_CS_STOP_N_GO;
4577 nw64(TX_CS(channel), val);
4578
4579 return niu_tx_cs_sng_poll(np, channel);
4580}
4581
4582static int niu_tx_cs_reset_poll(struct niu *np, int channel)
4583{
4584 int limit = 1000;
4585
4586 while (--limit > 0) {
4587 u64 val = nr64(TX_CS(channel));
4588 if (!(val & TX_CS_RST))
4589 return 0;
4590 }
4591 return -ENODEV;
4592}
4593
4594static int niu_tx_channel_reset(struct niu *np, int channel)
4595{
4596 u64 val = nr64(TX_CS(channel));
4597 int err;
4598
4599 val |= TX_CS_RST;
4600 nw64(TX_CS(channel), val);
4601
4602 err = niu_tx_cs_reset_poll(np, channel);
4603 if (!err)
4604 nw64(TX_RING_KICK(channel), 0);
4605
4606 return err;
4607}
4608
4609static int niu_tx_channel_lpage_init(struct niu *np, int channel)
4610{
4611 u64 val;
4612
4613 nw64(TX_LOG_MASK1(channel), 0);
4614 nw64(TX_LOG_VAL1(channel), 0);
4615 nw64(TX_LOG_MASK2(channel), 0);
4616 nw64(TX_LOG_VAL2(channel), 0);
4617 nw64(TX_LOG_PAGE_RELO1(channel), 0);
4618 nw64(TX_LOG_PAGE_RELO2(channel), 0);
4619 nw64(TX_LOG_PAGE_HDL(channel), 0);
4620
4621 val = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT;
4622 val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1);
4623 nw64(TX_LOG_PAGE_VLD(channel), val);
4624
4625 /* XXX TXDMA 32bit mode? XXX */
4626
4627 return 0;
4628}
4629
4630static void niu_txc_enable_port(struct niu *np, int on)
4631{
4632 unsigned long flags;
4633 u64 val, mask;
4634
4635 niu_lock_parent(np, flags);
4636 val = nr64(TXC_CONTROL);
4637 mask = (u64)1 << np->port;
4638 if (on) {
4639 val |= TXC_CONTROL_ENABLE | mask;
4640 } else {
4641 val &= ~mask;
4642 if ((val & ~TXC_CONTROL_ENABLE) == 0)
4643 val &= ~TXC_CONTROL_ENABLE;
4644 }
4645 nw64(TXC_CONTROL, val);
4646 niu_unlock_parent(np, flags);
4647}
4648
4649static void niu_txc_set_imask(struct niu *np, u64 imask)
4650{
4651 unsigned long flags;
4652 u64 val;
4653
4654 niu_lock_parent(np, flags);
4655 val = nr64(TXC_INT_MASK);
4656 val &= ~TXC_INT_MASK_VAL(np->port);
4657 val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port));
4658 niu_unlock_parent(np, flags);
4659}
4660
4661static void niu_txc_port_dma_enable(struct niu *np, int on)
4662{
4663 u64 val = 0;
4664
4665 if (on) {
4666 int i;
4667
4668 for (i = 0; i < np->num_tx_rings; i++)
4669 val |= (1 << np->tx_rings[i].tx_channel);
4670 }
4671 nw64(TXC_PORT_DMA(np->port), val);
4672}
4673
4674static int niu_init_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
4675{
4676 int err, channel = rp->tx_channel;
4677 u64 val, ring_len;
4678
4679 err = niu_tx_channel_stop(np, channel);
4680 if (err)
4681 return err;
4682
4683 err = niu_tx_channel_reset(np, channel);
4684 if (err)
4685 return err;
4686
4687 err = niu_tx_channel_lpage_init(np, channel);
4688 if (err)
4689 return err;
4690
4691 nw64(TXC_DMA_MAX(channel), rp->max_burst);
4692 nw64(TX_ENT_MSK(channel), 0);
4693
4694 if (rp->descr_dma & ~(TX_RNG_CFIG_STADDR_BASE |
4695 TX_RNG_CFIG_STADDR)) {
f10a1f2e
JP		 4696 netdev_err(np->dev, "TX ring channel %d DMA addr (%llx) is not aligned\n",
4697 channel, (unsigned long long)rp->descr_dma);
a3138df9
DM		 4698 return -EINVAL;
4699 }
4700
4701 /* The length field in TX_RNG_CFIG is measured in 64-byte
4702 * blocks. rp->pending is the number of TX descriptors in
4703 * our ring, 8 bytes each, thus we divide by 8 bytes more
4704 * to get the proper value the chip wants.
4705 */
4706 ring_len = (rp->pending / 8);
4707
4708 val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) |
4709 rp->descr_dma);
4710 nw64(TX_RNG_CFIG(channel), val);
4711
4712 if (((rp->mbox_dma >> 32) & ~TXDMA_MBH_MBADDR) ||
4713 ((u32)rp->mbox_dma & ~TXDMA_MBL_MBADDR)) {
f10a1f2e
JP		 4714 netdev_err(np->dev, "TX ring channel %d MBOX addr (%llx) has invalid bits\n",
4715 channel, (unsigned long long)rp->mbox_dma);
a3138df9
DM		 4716 return -EINVAL;
4717 }
4718 nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32);
4719 nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR);
4720
4721 nw64(TX_CS(channel), 0);
4722
4723 rp->last_pkt_cnt = 0;
4724
4725 return 0;
4726}
4727
4728static void niu_init_rdc_groups(struct niu *np)
4729{
4730 struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port];
4731 int i, first_table_num = tp->first_table_num;
4732
4733 for (i = 0; i < tp->num_tables; i++) {
4734 struct rdc_table *tbl = &tp->tables[i];
4735 int this_table = first_table_num + i;
4736 int slot;
4737
4738 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++)
4739 nw64(RDC_TBL(this_table, slot),
4740 tbl->rxdma_channel[slot]);
4741 }
4742
4743 nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]);
4744}
4745
4746static void niu_init_drr_weight(struct niu *np)
4747{
4748 int type = phy_decode(np->parent->port_phy, np->port);
4749 u64 val;
4750
4751 switch (type) {
4752 case PORT_TYPE_10G:
4753 val = PT_DRR_WEIGHT_DEFAULT_10G;
4754 break;
4755
4756 case PORT_TYPE_1G:
4757 default:
4758 val = PT_DRR_WEIGHT_DEFAULT_1G;
4759 break;
4760 }
4761 nw64(PT_DRR_WT(np->port), val);
4762}
4763
4764static int niu_init_hostinfo(struct niu *np)
4765{
4766 struct niu_parent *parent = np->parent;
4767 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
4768 int i, err, num_alt = niu_num_alt_addr(np);
4769 int first_rdc_table = tp->first_table_num;
4770
4771 err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
4772 if (err)
4773 return err;
4774
4775 err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
4776 if (err)
4777 return err;
4778
4779 for (i = 0; i < num_alt; i++) {
4780 err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1);
4781 if (err)
4782 return err;
4783 }
4784
4785 return 0;
4786}
4787
4788static int niu_rx_channel_reset(struct niu *np, int channel)
4789{
4790 return niu_set_and_wait_clear(np, RXDMA_CFIG1(channel),
4791 RXDMA_CFIG1_RST, 1000, 10,
4792 "RXDMA_CFIG1");
4793}
4794
4795static int niu_rx_channel_lpage_init(struct niu *np, int channel)
4796{
4797 u64 val;
4798
4799 nw64(RX_LOG_MASK1(channel), 0);
4800 nw64(RX_LOG_VAL1(channel), 0);
4801 nw64(RX_LOG_MASK2(channel), 0);
4802 nw64(RX_LOG_VAL2(channel), 0);
4803 nw64(RX_LOG_PAGE_RELO1(channel), 0);
4804 nw64(RX_LOG_PAGE_RELO2(channel), 0);
4805 nw64(RX_LOG_PAGE_HDL(channel), 0);
4806
4807 val = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT;
4808 val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1);
4809 nw64(RX_LOG_PAGE_VLD(channel), val);
4810
4811 return 0;
4812}
4813
4814static void niu_rx_channel_wred_init(struct niu *np, struct rx_ring_info *rp)
4815{
4816 u64 val;
4817
4818 val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) |
4819 ((u64)rp->nonsyn_threshold << RDC_RED_PARA_THRE_SHIFT) |
4820 ((u64)rp->syn_window << RDC_RED_PARA_WIN_SYN_SHIFT) |
4821 ((u64)rp->syn_threshold << RDC_RED_PARA_THRE_SYN_SHIFT));
4822 nw64(RDC_RED_PARA(rp->rx_channel), val);
4823}
4824
4825static int niu_compute_rbr_cfig_b(struct rx_ring_info *rp, u64 *ret)
4826{
4827 u64 val = 0;
4828
efb6c736 4829 *ret = 0;
a3138df9
DM		 4830 switch (rp->rbr_block_size) {
4831 case 4 * 1024:
4832 val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT);
4833 break;
4834 case 8 * 1024:
4835 val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT);
4836 break;
4837 case 16 * 1024:
4838 val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT);
4839 break;
4840 case 32 * 1024:
4841 val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT);
4842 break;
4843 default:
4844 return -EINVAL;
4845 }
4846 val |= RBR_CFIG_B_VLD2;
4847 switch (rp->rbr_sizes[2]) {
4848 case 2 * 1024:
4849 val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT);
4850 break;
4851 case 4 * 1024:
4852 val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT);
4853 break;
4854 case 8 * 1024:
4855 val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT);
4856 break;
4857 case 16 * 1024:
4858 val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT);
4859 break;
4860
4861 default:
4862 return -EINVAL;
4863 }
4864 val |= RBR_CFIG_B_VLD1;
4865 switch (rp->rbr_sizes[1]) {
4866 case 1 * 1024:
4867 val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT);
4868 break;
4869 case 2 * 1024:
4870 val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT);
4871 break;
4872 case 4 * 1024:
4873 val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT);
4874 break;
4875 case 8 * 1024:
4876 val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT);
4877 break;
4878
4879 default:
4880 return -EINVAL;
4881 }
4882 val |= RBR_CFIG_B_VLD0;
4883 switch (rp->rbr_sizes[0]) {
4884 case 256:
4885 val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT);
4886 break;
4887 case 512:
4888 val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT);
4889 break;
4890 case 1 * 1024:
4891 val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT);
4892 break;
4893 case 2 * 1024:
4894 val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT);
4895 break;
4896
4897 default:
4898 return -EINVAL;
4899 }
4900
4901 *ret = val;
4902 return 0;
4903}
4904
4905static int niu_enable_rx_channel(struct niu *np, int channel, int on)
4906{
4907 u64 val = nr64(RXDMA_CFIG1(channel));
4908 int limit;
4909
4910 if (on)
4911 val |= RXDMA_CFIG1_EN;
4912 else
4913 val &= ~RXDMA_CFIG1_EN;
4914 nw64(RXDMA_CFIG1(channel), val);
4915
4916 limit = 1000;
4917 while (--limit > 0) {
4918 if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST)
4919 break;
4920 udelay(10);
4921 }
4922 if (limit <= 0)
4923 return -ENODEV;
4924 return 0;
4925}
4926
4927static int niu_init_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
4928{
4929 int err, channel = rp->rx_channel;
4930 u64 val;
4931
4932 err = niu_rx_channel_reset(np, channel);
4933 if (err)
4934 return err;
4935
4936 err = niu_rx_channel_lpage_init(np, channel);
4937 if (err)
4938 return err;
4939
4940 niu_rx_channel_wred_init(np, rp);
4941
4942 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY);
4943 nw64(RX_DMA_CTL_STAT(channel),
4944 (RX_DMA_CTL_STAT_MEX |
4945 RX_DMA_CTL_STAT_RCRTHRES |
4946 RX_DMA_CTL_STAT_RCRTO |
4947 RX_DMA_CTL_STAT_RBR_EMPTY));
4948 nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32);
4949 nw64(RXDMA_CFIG2(channel), (rp->mbox_dma & 0x00000000ffffffc0));
4950 nw64(RBR_CFIG_A(channel),
4951 ((u64)rp->rbr_table_size << RBR_CFIG_A_LEN_SHIFT) |
4952 (rp->rbr_dma & (RBR_CFIG_A_STADDR_BASE | RBR_CFIG_A_STADDR)));
4953 err = niu_compute_rbr_cfig_b(rp, &val);
4954 if (err)
4955 return err;
4956 nw64(RBR_CFIG_B(channel), val);
4957 nw64(RCRCFIG_A(channel),
4958 ((u64)rp->rcr_table_size << RCRCFIG_A_LEN_SHIFT) |
4959 (rp->rcr_dma & (RCRCFIG_A_STADDR_BASE | RCRCFIG_A_STADDR)));
4960 nw64(RCRCFIG_B(channel),
4961 ((u64)rp->rcr_pkt_threshold << RCRCFIG_B_PTHRES_SHIFT) |
4962 RCRCFIG_B_ENTOUT |
4963 ((u64)rp->rcr_timeout << RCRCFIG_B_TIMEOUT_SHIFT));
4964
4965 err = niu_enable_rx_channel(np, channel, 1);
4966 if (err)
4967 return err;
4968
4969 nw64(RBR_KICK(channel), rp->rbr_index);
4970
4971 val = nr64(RX_DMA_CTL_STAT(channel));
4972 val |= RX_DMA_CTL_STAT_RBR_EMPTY;
4973 nw64(RX_DMA_CTL_STAT(channel), val);
4974
4975 return 0;
4976}
4977
4978static int niu_init_rx_channels(struct niu *np)
4979{
4980 unsigned long flags;
4981 u64 seed = jiffies_64;
4982 int err, i;
4983
4984 niu_lock_parent(np, flags);
4985 nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider);
4986 nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL));
4987 niu_unlock_parent(np, flags);
4988
4989 /* XXX RXDMA 32bit mode? XXX */
4990
4991 niu_init_rdc_groups(np);
4992 niu_init_drr_weight(np);
4993
4994 err = niu_init_hostinfo(np);
4995 if (err)
4996 return err;
4997
4998 for (i = 0; i < np->num_rx_rings; i++) {
4999 struct rx_ring_info *rp = &np->rx_rings[i];
5000
5001 err = niu_init_one_rx_channel(np, rp);
5002 if (err)
5003 return err;
5004 }
5005
5006 return 0;
5007}
5008
5009static int niu_set_ip_frag_rule(struct niu *np)
5010{
5011 struct niu_parent *parent = np->parent;
5012 struct niu_classifier *cp = &np->clas;
5013 struct niu_tcam_entry *tp;
5014 int index, err;
5015
2d96cf8c 5016 index = cp->tcam_top;
a3138df9
DM		 5017 tp = &parent->tcam[index];
5018
5019 /* Note that the noport bit is the same in both ipv4 and
5020 * ipv6 format TCAM entries.
5021 */
5022 memset(tp, 0, sizeof(*tp));
5023 tp->key[1] = TCAM_V4KEY1_NOPORT;
5024 tp->key_mask[1] = TCAM_V4KEY1_NOPORT;
5025 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
5026 ((u64)0 << TCAM_ASSOCDATA_OFFSET_SHIFT));
5027 err = tcam_write(np, index, tp->key, tp->key_mask);
5028 if (err)
5029 return err;
5030 err = tcam_assoc_write(np, index, tp->assoc_data);
5031 if (err)
5032 return err;
2d96cf8c
SB		 5033 tp->valid = 1;
5034 cp->tcam_valid_entries++;
a3138df9
DM		 5035
5036 return 0;
5037}
5038
5039static int niu_init_classifier_hw(struct niu *np)
5040{
5041 struct niu_parent *parent = np->parent;
5042 struct niu_classifier *cp = &np->clas;
5043 int i, err;
5044
5045 nw64(H1POLY, cp->h1_init);
5046 nw64(H2POLY, cp->h2_init);
5047
5048 err = niu_init_hostinfo(np);
5049 if (err)
5050 return err;
5051
5052 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) {
5053 struct niu_vlan_rdc *vp = &cp->vlan_mappings[i];
5054
5055 vlan_tbl_write(np, i, np->port,
5056 vp->vlan_pref, vp->rdc_num);
5057 }
5058
5059 for (i = 0; i < cp->num_alt_mac_mappings; i++) {
5060 struct niu_altmac_rdc *ap = &cp->alt_mac_mappings[i];
5061
5062 err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num,
5063 ap->rdc_num, ap->mac_pref);
5064 if (err)
5065 return err;
5066 }
5067
5068 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
5069 int index = i - CLASS_CODE_USER_PROG1;
5070
5071 err = niu_set_tcam_key(np, i, parent->tcam_key[index]);
5072 if (err)
5073 return err;
5074 err = niu_set_flow_key(np, i, parent->flow_key[index]);
5075 if (err)
5076 return err;
5077 }
5078
5079 err = niu_set_ip_frag_rule(np);
5080 if (err)
5081 return err;
5082
5083 tcam_enable(np, 1);
5084
5085 return 0;
5086}
5087
5088static int niu_zcp_write(struct niu *np, int index, u64 *data)
5089{
5090 nw64(ZCP_RAM_DATA0, data[0]);
5091 nw64(ZCP_RAM_DATA1, data[1]);
5092 nw64(ZCP_RAM_DATA2, data[2]);
5093 nw64(ZCP_RAM_DATA3, data[3]);
5094 nw64(ZCP_RAM_DATA4, data[4]);
5095 nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL);
5096 nw64(ZCP_RAM_ACC,
5097 (ZCP_RAM_ACC_WRITE |
5098 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5099 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5100
5101 return niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5102 1000, 100);
5103}
5104
5105static int niu_zcp_read(struct niu *np, int index, u64 *data)
5106{
5107 int err;
5108
5109 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5110 1000, 100);
5111 if (err) {
f10a1f2e
JP		 5112 netdev_err(np->dev, "ZCP read busy won't clear, ZCP_RAM_ACC[%llx]\n",
5113 (unsigned long long)nr64(ZCP_RAM_ACC));
a3138df9
DM		 5114 return err;
5115 }
5116
5117 nw64(ZCP_RAM_ACC,
5118 (ZCP_RAM_ACC_READ |
5119 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5120 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5121
5122 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5123 1000, 100);
5124 if (err) {
f10a1f2e
JP		 5125 netdev_err(np->dev, "ZCP read busy2 won't clear, ZCP_RAM_ACC[%llx]\n",
5126 (unsigned long long)nr64(ZCP_RAM_ACC));
a3138df9
DM		 5127 return err;
5128 }
5129
5130 data[0] = nr64(ZCP_RAM_DATA0);
5131 data[1] = nr64(ZCP_RAM_DATA1);
5132 data[2] = nr64(ZCP_RAM_DATA2);
5133 data[3] = nr64(ZCP_RAM_DATA3);
5134 data[4] = nr64(ZCP_RAM_DATA4);
5135
5136 return 0;
5137}
5138
5139static void niu_zcp_cfifo_reset(struct niu *np)
5140{
5141 u64 val = nr64(RESET_CFIFO);
5142
5143 val |= RESET_CFIFO_RST(np->port);
5144 nw64(RESET_CFIFO, val);
5145 udelay(10);
5146
5147 val &= ~RESET_CFIFO_RST(np->port);
5148 nw64(RESET_CFIFO, val);
5149}
5150
5151static int niu_init_zcp(struct niu *np)
5152{
5153 u64 data[5], rbuf[5];
5154 int i, max, err;
5155
5156 if (np->parent->plat_type != PLAT_TYPE_NIU) {
5157 if (np->port == 0 || np->port == 1)
5158 max = ATLAS_P0_P1_CFIFO_ENTRIES;
5159 else
5160 max = ATLAS_P2_P3_CFIFO_ENTRIES;
5161 } else
5162 max = NIU_CFIFO_ENTRIES;
5163
5164 data[0] = 0;
5165 data[1] = 0;
5166 data[2] = 0;
5167 data[3] = 0;
5168 data[4] = 0;
5169
5170 for (i = 0; i < max; i++) {
5171 err = niu_zcp_write(np, i, data);
5172 if (err)
5173 return err;
5174 err = niu_zcp_read(np, i, rbuf);
5175 if (err)
5176 return err;
5177 }
5178
5179 niu_zcp_cfifo_reset(np);
5180 nw64(CFIFO_ECC(np->port), 0);
5181 nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL);
5182 (void) nr64(ZCP_INT_STAT);
5183 nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL);
5184
5185 return 0;
5186}
5187
5188static void niu_ipp_write(struct niu *np, int index, u64 *data)
5189{
5190 u64 val = nr64_ipp(IPP_CFIG);
5191
5192 nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W);
5193 nw64_ipp(IPP_DFIFO_WR_PTR, index);
5194 nw64_ipp(IPP_DFIFO_WR0, data[0]);
5195 nw64_ipp(IPP_DFIFO_WR1, data[1]);
5196 nw64_ipp(IPP_DFIFO_WR2, data[2]);
5197 nw64_ipp(IPP_DFIFO_WR3, data[3]);
5198 nw64_ipp(IPP_DFIFO_WR4, data[4]);
5199 nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W);
5200}
5201
5202static void niu_ipp_read(struct niu *np, int index, u64 *data)
5203{
5204 nw64_ipp(IPP_DFIFO_RD_PTR, index);
5205 data[0] = nr64_ipp(IPP_DFIFO_RD0);
5206 data[1] = nr64_ipp(IPP_DFIFO_RD1);
5207 data[2] = nr64_ipp(IPP_DFIFO_RD2);
5208 data[3] = nr64_ipp(IPP_DFIFO_RD3);
5209 data[4] = nr64_ipp(IPP_DFIFO_RD4);
5210}
5211
5212static int niu_ipp_reset(struct niu *np)
5213{
5214 return niu_set_and_wait_clear_ipp(np, IPP_CFIG, IPP_CFIG_SOFT_RST,
5215 1000, 100, "IPP_CFIG");
5216}
5217
5218static int niu_init_ipp(struct niu *np)
5219{
5220 u64 data[5], rbuf[5], val;
5221 int i, max, err;
5222
5223 if (np->parent->plat_type != PLAT_TYPE_NIU) {
5224 if (np->port == 0 || np->port == 1)
5225 max = ATLAS_P0_P1_DFIFO_ENTRIES;
5226 else
5227 max = ATLAS_P2_P3_DFIFO_ENTRIES;
5228 } else
5229 max = NIU_DFIFO_ENTRIES;
5230
5231 data[0] = 0;
5232 data[1] = 0;
5233 data[2] = 0;
5234 data[3] = 0;
5235 data[4] = 0;
5236
5237 for (i = 0; i < max; i++) {
5238 niu_ipp_write(np, i, data);
5239 niu_ipp_read(np, i, rbuf);
5240 }
5241
5242 (void) nr64_ipp(IPP_INT_STAT);
5243 (void) nr64_ipp(IPP_INT_STAT);
5244
5245 err = niu_ipp_reset(np);
5246 if (err)
5247 return err;
5248
5249 (void) nr64_ipp(IPP_PKT_DIS);
5250 (void) nr64_ipp(IPP_BAD_CS_CNT);
5251 (void) nr64_ipp(IPP_ECC);
5252
5253 (void) nr64_ipp(IPP_INT_STAT);
5254
5255 nw64_ipp(IPP_MSK, ~IPP_MSK_ALL);
5256
5257 val = nr64_ipp(IPP_CFIG);
5258 val &= ~IPP_CFIG_IP_MAX_PKT;
5259 val |= (IPP_CFIG_IPP_ENABLE |
5260 IPP_CFIG_DFIFO_ECC_EN |
5261 IPP_CFIG_DROP_BAD_CRC |
5262 IPP_CFIG_CKSUM_EN |
5263 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT));
5264 nw64_ipp(IPP_CFIG, val);
5265
5266 return 0;
5267}
5268
0c3b091b 5269static void niu_handle_led(struct niu *np, int status)
a3138df9 5270{
a3138df9 5271 u64 val;
a3138df9
DM		 5272 val = nr64_mac(XMAC_CONFIG);
5273
5274 if ((np->flags & NIU_FLAGS_10G) != 0 &&
5275 (np->flags & NIU_FLAGS_FIBER) != 0) {
0c3b091b 5276 if (status) {
a3138df9
DM		 5277 val |= XMAC_CONFIG_LED_POLARITY;
5278 val &= ~XMAC_CONFIG_FORCE_LED_ON;
5279 } else {
5280 val |= XMAC_CONFIG_FORCE_LED_ON;
5281 val &= ~XMAC_CONFIG_LED_POLARITY;
5282 }
5283 }
5284
0c3b091b
ML		 5285 nw64_mac(XMAC_CONFIG, val);
5286}
5287
5288static void niu_init_xif_xmac(struct niu *np)
5289{
5290 struct niu_link_config *lp = &np->link_config;
5291 u64 val;
5292
5fbd7e24
MW		 5293 if (np->flags & NIU_FLAGS_XCVR_SERDES) {
5294 val = nr64(MIF_CONFIG);
5295 val |= MIF_CONFIG_ATCA_GE;
5296 nw64(MIF_CONFIG, val);
5297 }
5298
0c3b091b 5299 val = nr64_mac(XMAC_CONFIG);
a3138df9
DM		 5300 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5301
5302 val |= XMAC_CONFIG_TX_OUTPUT_EN;
5303
5304 if (lp->loopback_mode == LOOPBACK_MAC) {
5305 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5306 val |= XMAC_CONFIG_LOOPBACK;
5307 } else {
5308 val &= ~XMAC_CONFIG_LOOPBACK;
5309 }
5310
5311 if (np->flags & NIU_FLAGS_10G) {
5312 val &= ~XMAC_CONFIG_LFS_DISABLE;
5313 } else {
5314 val |= XMAC_CONFIG_LFS_DISABLE;
5fbd7e24
MW		 5315 if (!(np->flags & NIU_FLAGS_FIBER) &&
5316 !(np->flags & NIU_FLAGS_XCVR_SERDES))
a3138df9
DM		 5317 val |= XMAC_CONFIG_1G_PCS_BYPASS;
5318 else
5319 val &= ~XMAC_CONFIG_1G_PCS_BYPASS;
5320 }
5321
5322 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5323
5324 if (lp->active_speed == SPEED_100)
5325 val |= XMAC_CONFIG_SEL_CLK_25MHZ;
5326 else
5327 val &= ~XMAC_CONFIG_SEL_CLK_25MHZ;
5328
5329 nw64_mac(XMAC_CONFIG, val);
5330
5331 val = nr64_mac(XMAC_CONFIG);
5332 val &= ~XMAC_CONFIG_MODE_MASK;
5333 if (np->flags & NIU_FLAGS_10G) {
5334 val |= XMAC_CONFIG_MODE_XGMII;
5335 } else {
38bb045d 5336 if (lp->active_speed == SPEED_1000)
a3138df9 5337 val |= XMAC_CONFIG_MODE_GMII;
38bb045d
CB		 5338 else
5339 val |= XMAC_CONFIG_MODE_MII;
a3138df9
DM		 5340 }
5341
5342 nw64_mac(XMAC_CONFIG, val);
5343}
5344
5345static void niu_init_xif_bmac(struct niu *np)
5346{
5347 struct niu_link_config *lp = &np->link_config;
5348 u64 val;
5349
5350 val = BMAC_XIF_CONFIG_TX_OUTPUT_EN;
5351
5352 if (lp->loopback_mode == LOOPBACK_MAC)
5353 val |= BMAC_XIF_CONFIG_MII_LOOPBACK;
5354 else
5355 val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK;
5356
5357 if (lp->active_speed == SPEED_1000)
5358 val |= BMAC_XIF_CONFIG_GMII_MODE;
5359 else
5360 val &= ~BMAC_XIF_CONFIG_GMII_MODE;
5361
5362 val &= ~(BMAC_XIF_CONFIG_LINK_LED |
5363 BMAC_XIF_CONFIG_LED_POLARITY);
5364
5365 if (!(np->flags & NIU_FLAGS_10G) &&
5366 !(np->flags & NIU_FLAGS_FIBER) &&
5367 lp->active_speed == SPEED_100)
5368 val |= BMAC_XIF_CONFIG_25MHZ_CLOCK;
5369 else
5370 val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK;
5371
5372 nw64_mac(BMAC_XIF_CONFIG, val);
5373}
5374
5375static void niu_init_xif(struct niu *np)
5376{
5377 if (np->flags & NIU_FLAGS_XMAC)
5378 niu_init_xif_xmac(np);
5379 else
5380 niu_init_xif_bmac(np);
5381}
5382
5383static void niu_pcs_mii_reset(struct niu *np)
5384{
5fbd7e24 5385 int limit = 1000;
a3138df9
DM		 5386 u64 val = nr64_pcs(PCS_MII_CTL);
5387 val |= PCS_MII_CTL_RST;
5388 nw64_pcs(PCS_MII_CTL, val);
5fbd7e24
MW		 5389 while ((--limit >= 0) && (val & PCS_MII_CTL_RST)) {
5390 udelay(100);
5391 val = nr64_pcs(PCS_MII_CTL);
5392 }
a3138df9
DM		 5393}
5394
5395static void niu_xpcs_reset(struct niu *np)
5396{
5fbd7e24 5397 int limit = 1000;
a3138df9
DM		 5398 u64 val = nr64_xpcs(XPCS_CONTROL1);
5399 val |= XPCS_CONTROL1_RESET;
5400 nw64_xpcs(XPCS_CONTROL1, val);
5fbd7e24
MW		 5401 while ((--limit >= 0) && (val & XPCS_CONTROL1_RESET)) {
5402 udelay(100);
5403 val = nr64_xpcs(XPCS_CONTROL1);
5404 }
a3138df9
DM		 5405}
5406
5407static int niu_init_pcs(struct niu *np)
5408{
5409 struct niu_link_config *lp = &np->link_config;
5410 u64 val;
5411
5fbd7e24
MW		 5412 switch (np->flags & (NIU_FLAGS_10G |
5413 NIU_FLAGS_FIBER |
5414 NIU_FLAGS_XCVR_SERDES)) {
a3138df9
DM		 5415 case NIU_FLAGS_FIBER:
5416 /* 1G fiber */
5417 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5418 nw64_pcs(PCS_DPATH_MODE, 0);
5419 niu_pcs_mii_reset(np);
5420 break;
5421
5422 case NIU_FLAGS_10G:
5423 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
5fbd7e24
MW		 5424 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
5425 /* 10G SERDES */
a3138df9
DM		 5426 if (!(np->flags & NIU_FLAGS_XMAC))
5427 return -EINVAL;
5428
5429 /* 10G copper or fiber */
5430 val = nr64_mac(XMAC_CONFIG);
5431 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5432 nw64_mac(XMAC_CONFIG, val);
5433
5434 niu_xpcs_reset(np);
5435
5436 val = nr64_xpcs(XPCS_CONTROL1);
5437 if (lp->loopback_mode == LOOPBACK_PHY)
5438 val |= XPCS_CONTROL1_LOOPBACK;
5439 else
5440 val &= ~XPCS_CONTROL1_LOOPBACK;
5441 nw64_xpcs(XPCS_CONTROL1, val);
5442
5443 nw64_xpcs(XPCS_DESKEW_ERR_CNT, 0);
5444 (void) nr64_xpcs(XPCS_SYMERR_CNT01);
5445 (void) nr64_xpcs(XPCS_SYMERR_CNT23);
5446 break;
5447
5fbd7e24
MW		 5448
5449 case NIU_FLAGS_XCVR_SERDES:
5450 /* 1G SERDES */
5451 niu_pcs_mii_reset(np);
5452 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5453 nw64_pcs(PCS_DPATH_MODE, 0);
5454 break;
5455
a3138df9
DM		 5456 case 0:
5457 /* 1G copper */
5fbd7e24
MW		 5458 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
5459 /* 1G RGMII FIBER */
a3138df9
DM		 5460 nw64_pcs(PCS_DPATH_MODE, PCS_DPATH_MODE_MII);
5461 niu_pcs_mii_reset(np);
5462 break;
5463
5464 default:
5465 return -EINVAL;
5466 }
5467
5468 return 0;
5469}
5470
5471static int niu_reset_tx_xmac(struct niu *np)
5472{
5473 return niu_set_and_wait_clear_mac(np, XTXMAC_SW_RST,
5474 (XTXMAC_SW_RST_REG_RS |
5475 XTXMAC_SW_RST_SOFT_RST),
5476 1000, 100, "XTXMAC_SW_RST");
5477}
5478
5479static int niu_reset_tx_bmac(struct niu *np)
5480{
5481 int limit;
5482
5483 nw64_mac(BTXMAC_SW_RST, BTXMAC_SW_RST_RESET);
5484 limit = 1000;
5485 while (--limit >= 0) {
5486 if (!(nr64_mac(BTXMAC_SW_RST) & BTXMAC_SW_RST_RESET))
5487 break;
5488 udelay(100);
5489 }
5490 if (limit < 0) {
f10a1f2e 5491 dev_err(np->device, "Port %u TX BMAC would not reset, BTXMAC_SW_RST[%llx]\n",
a3138df9
DM		 5492 np->port,
5493 (unsigned long long) nr64_mac(BTXMAC_SW_RST));
5494 return -ENODEV;
5495 }
5496
5497 return 0;
5498}
5499
5500static int niu_reset_tx_mac(struct niu *np)
5501{
5502 if (np->flags & NIU_FLAGS_XMAC)
5503 return niu_reset_tx_xmac(np);
5504 else
5505 return niu_reset_tx_bmac(np);
5506}
5507
5508static void niu_init_tx_xmac(struct niu *np, u64 min, u64 max)
5509{
5510 u64 val;
5511
5512 val = nr64_mac(XMAC_MIN);
5513 val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE |
5514 XMAC_MIN_RX_MIN_PKT_SIZE);
5515 val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT);
5516 val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT);
5517 nw64_mac(XMAC_MIN, val);
5518
5519 nw64_mac(XMAC_MAX, max);
5520
5521 nw64_mac(XTXMAC_STAT_MSK, ~(u64)0);
5522
5523 val = nr64_mac(XMAC_IPG);
5524 if (np->flags & NIU_FLAGS_10G) {
5525 val &= ~XMAC_IPG_IPG_XGMII;
5526 val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT);
5527 } else {
5528 val &= ~XMAC_IPG_IPG_MII_GMII;
5529 val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT);
5530 }
5531 nw64_mac(XMAC_IPG, val);
5532
5533 val = nr64_mac(XMAC_CONFIG);
5534 val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC |
5535 XMAC_CONFIG_STRETCH_MODE |
5536 XMAC_CONFIG_VAR_MIN_IPG_EN |
5537 XMAC_CONFIG_TX_ENABLE);
5538 nw64_mac(XMAC_CONFIG, val);
5539
5540 nw64_mac(TXMAC_FRM_CNT, 0);
5541 nw64_mac(TXMAC_BYTE_CNT, 0);
5542}
5543
5544static void niu_init_tx_bmac(struct niu *np, u64 min, u64 max)
5545{
5546 u64 val;
5547
5548 nw64_mac(BMAC_MIN_FRAME, min);
5549 nw64_mac(BMAC_MAX_FRAME, max);
5550
5551 nw64_mac(BTXMAC_STATUS_MASK, ~(u64)0);
5552 nw64_mac(BMAC_CTRL_TYPE, 0x8808);
5553 nw64_mac(BMAC_PREAMBLE_SIZE, 7);
5554
5555 val = nr64_mac(BTXMAC_CONFIG);
5556 val &= ~(BTXMAC_CONFIG_FCS_DISABLE |
5557 BTXMAC_CONFIG_ENABLE);
5558 nw64_mac(BTXMAC_CONFIG, val);
5559}
5560
5561static void niu_init_tx_mac(struct niu *np)
5562{
5563 u64 min, max;
5564
5565 min = 64;
5566 if (np->dev->mtu > ETH_DATA_LEN)
5567 max = 9216;
5568 else
5569 max = 1522;
5570
5571 /* The XMAC_MIN register only accepts values for TX min which
5572 * have the low 3 bits cleared.
5573 */
8c87df45 5574 BUG_ON(min & 0x7);
a3138df9
DM		 5575
5576 if (np->flags & NIU_FLAGS_XMAC)
5577 niu_init_tx_xmac(np, min, max);
5578 else
5579 niu_init_tx_bmac(np, min, max);
5580}
5581
5582static int niu_reset_rx_xmac(struct niu *np)
5583{
5584 int limit;
5585
5586 nw64_mac(XRXMAC_SW_RST,
5587 XRXMAC_SW_RST_REG_RS | XRXMAC_SW_RST_SOFT_RST);
5588 limit = 1000;
5589 while (--limit >= 0) {
5590 if (!(nr64_mac(XRXMAC_SW_RST) & (XRXMAC_SW_RST_REG_RS |
5591 XRXMAC_SW_RST_SOFT_RST)))
f10a1f2e 5592 break;
a3138df9
DM		 5593 udelay(100);
5594 }
5595 if (limit < 0) {
f10a1f2e 5596 dev_err(np->device, "Port %u RX XMAC would not reset, XRXMAC_SW_RST[%llx]\n",
a3138df9
DM		 5597 np->port,
5598 (unsigned long long) nr64_mac(XRXMAC_SW_RST));
5599 return -ENODEV;
5600 }
5601
5602 return 0;
5603}
5604
5605static int niu_reset_rx_bmac(struct niu *np)
5606{
5607 int limit;
5608
5609 nw64_mac(BRXMAC_SW_RST, BRXMAC_SW_RST_RESET);
5610 limit = 1000;
5611 while (--limit >= 0) {
5612 if (!(nr64_mac(BRXMAC_SW_RST) & BRXMAC_SW_RST_RESET))
5613 break;
5614 udelay(100);
5615 }
5616 if (limit < 0) {
f10a1f2e 5617 dev_err(np->device, "Port %u RX BMAC would not reset, BRXMAC_SW_RST[%llx]\n",
a3138df9
DM		 5618 np->port,
5619 (unsigned long long) nr64_mac(BRXMAC_SW_RST));
5620 return -ENODEV;
5621 }
5622
5623 return 0;
5624}
5625
5626static int niu_reset_rx_mac(struct niu *np)
5627{
5628 if (np->flags & NIU_FLAGS_XMAC)
5629 return niu_reset_rx_xmac(np);
5630 else
5631 return niu_reset_rx_bmac(np);
5632}
5633
5634static void niu_init_rx_xmac(struct niu *np)
5635{
5636 struct niu_parent *parent = np->parent;
5637 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5638 int first_rdc_table = tp->first_table_num;
5639 unsigned long i;
5640 u64 val;
5641
5642 nw64_mac(XMAC_ADD_FILT0, 0);
5643 nw64_mac(XMAC_ADD_FILT1, 0);
5644 nw64_mac(XMAC_ADD_FILT2, 0);
5645 nw64_mac(XMAC_ADD_FILT12_MASK, 0);
5646 nw64_mac(XMAC_ADD_FILT00_MASK, 0);
5647 for (i = 0; i < MAC_NUM_HASH; i++)
5648 nw64_mac(XMAC_HASH_TBL(i), 0);
5649 nw64_mac(XRXMAC_STAT_MSK, ~(u64)0);
5650 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5651 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5652
5653 val = nr64_mac(XMAC_CONFIG);
5654 val &= ~(XMAC_CONFIG_RX_MAC_ENABLE |
5655 XMAC_CONFIG_PROMISCUOUS |
5656 XMAC_CONFIG_PROMISC_GROUP |
5657 XMAC_CONFIG_ERR_CHK_DIS |
5658 XMAC_CONFIG_RX_CRC_CHK_DIS |
5659 XMAC_CONFIG_RESERVED_MULTICAST |
5660 XMAC_CONFIG_RX_CODEV_CHK_DIS |
5661 XMAC_CONFIG_ADDR_FILTER_EN |
5662 XMAC_CONFIG_RCV_PAUSE_ENABLE |
5663 XMAC_CONFIG_STRIP_CRC |
5664 XMAC_CONFIG_PASS_FLOW_CTRL |
5665 XMAC_CONFIG_MAC2IPP_PKT_CNT_EN);
5666 val |= (XMAC_CONFIG_HASH_FILTER_EN);
5667 nw64_mac(XMAC_CONFIG, val);
5668
5669 nw64_mac(RXMAC_BT_CNT, 0);
5670 nw64_mac(RXMAC_BC_FRM_CNT, 0);
5671 nw64_mac(RXMAC_MC_FRM_CNT, 0);
5672 nw64_mac(RXMAC_FRAG_CNT, 0);
5673 nw64_mac(RXMAC_HIST_CNT1, 0);
5674 nw64_mac(RXMAC_HIST_CNT2, 0);
5675 nw64_mac(RXMAC_HIST_CNT3, 0);
5676 nw64_mac(RXMAC_HIST_CNT4, 0);
5677 nw64_mac(RXMAC_HIST_CNT5, 0);
5678 nw64_mac(RXMAC_HIST_CNT6, 0);
5679 nw64_mac(RXMAC_HIST_CNT7, 0);
5680 nw64_mac(RXMAC_MPSZER_CNT, 0);
5681 nw64_mac(RXMAC_CRC_ER_CNT, 0);
5682 nw64_mac(RXMAC_CD_VIO_CNT, 0);
5683 nw64_mac(LINK_FAULT_CNT, 0);
5684}
5685
5686static void niu_init_rx_bmac(struct niu *np)
5687{
5688 struct niu_parent *parent = np->parent;
5689 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5690 int first_rdc_table = tp->first_table_num;
5691 unsigned long i;
5692 u64 val;
5693
5694 nw64_mac(BMAC_ADD_FILT0, 0);
5695 nw64_mac(BMAC_ADD_FILT1, 0);
5696 nw64_mac(BMAC_ADD_FILT2, 0);
5697 nw64_mac(BMAC_ADD_FILT12_MASK, 0);
5698 nw64_mac(BMAC_ADD_FILT00_MASK, 0);
5699 for (i = 0; i < MAC_NUM_HASH; i++)
5700 nw64_mac(BMAC_HASH_TBL(i), 0);
5701 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5702 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5703 nw64_mac(BRXMAC_STATUS_MASK, ~(u64)0);
5704
5705 val = nr64_mac(BRXMAC_CONFIG);
5706 val &= ~(BRXMAC_CONFIG_ENABLE |
5707 BRXMAC_CONFIG_STRIP_PAD |
5708 BRXMAC_CONFIG_STRIP_FCS |
5709 BRXMAC_CONFIG_PROMISC |
5710 BRXMAC_CONFIG_PROMISC_GRP |
5711 BRXMAC_CONFIG_ADDR_FILT_EN |
5712 BRXMAC_CONFIG_DISCARD_DIS);
5713 val |= (BRXMAC_CONFIG_HASH_FILT_EN);
5714 nw64_mac(BRXMAC_CONFIG, val);
5715
5716 val = nr64_mac(BMAC_ADDR_CMPEN);
5717 val |= BMAC_ADDR_CMPEN_EN0;
5718 nw64_mac(BMAC_ADDR_CMPEN, val);
5719}
5720
5721static void niu_init_rx_mac(struct niu *np)
5722{
5723 niu_set_primary_mac(np, np->dev->dev_addr);
5724
5725 if (np->flags & NIU_FLAGS_XMAC)
5726 niu_init_rx_xmac(np);
5727 else
5728 niu_init_rx_bmac(np);
5729}
5730
5731static void niu_enable_tx_xmac(struct niu *np, int on)
5732{
5733 u64 val = nr64_mac(XMAC_CONFIG);
5734
5735 if (on)
5736 val |= XMAC_CONFIG_TX_ENABLE;
5737 else
5738 val &= ~XMAC_CONFIG_TX_ENABLE;
5739 nw64_mac(XMAC_CONFIG, val);
5740}
5741
5742static void niu_enable_tx_bmac(struct niu *np, int on)
5743{
5744 u64 val = nr64_mac(BTXMAC_CONFIG);
5745
5746 if (on)
5747 val |= BTXMAC_CONFIG_ENABLE;
5748 else
5749 val &= ~BTXMAC_CONFIG_ENABLE;
5750 nw64_mac(BTXMAC_CONFIG, val);
5751}
5752
5753static void niu_enable_tx_mac(struct niu *np, int on)
5754{
5755 if (np->flags & NIU_FLAGS_XMAC)
5756 niu_enable_tx_xmac(np, on);
5757 else
5758 niu_enable_tx_bmac(np, on);
5759}
5760
5761static void niu_enable_rx_xmac(struct niu *np, int on)
5762{
5763 u64 val = nr64_mac(XMAC_CONFIG);
5764
5765 val &= ~(XMAC_CONFIG_HASH_FILTER_EN |
5766 XMAC_CONFIG_PROMISCUOUS);
5767
5768 if (np->flags & NIU_FLAGS_MCAST)
5769 val |= XMAC_CONFIG_HASH_FILTER_EN;
5770 if (np->flags & NIU_FLAGS_PROMISC)
5771 val |= XMAC_CONFIG_PROMISCUOUS;
5772
5773 if (on)
5774 val |= XMAC_CONFIG_RX_MAC_ENABLE;
5775 else
5776 val &= ~XMAC_CONFIG_RX_MAC_ENABLE;
5777 nw64_mac(XMAC_CONFIG, val);
5778}
5779
5780static void niu_enable_rx_bmac(struct niu *np, int on)
5781{
5782 u64 val = nr64_mac(BRXMAC_CONFIG);
5783
5784 val &= ~(BRXMAC_CONFIG_HASH_FILT_EN |
5785 BRXMAC_CONFIG_PROMISC);
5786
5787 if (np->flags & NIU_FLAGS_MCAST)
5788 val |= BRXMAC_CONFIG_HASH_FILT_EN;
5789 if (np->flags & NIU_FLAGS_PROMISC)
5790 val |= BRXMAC_CONFIG_PROMISC;
5791
5792 if (on)
5793 val |= BRXMAC_CONFIG_ENABLE;
5794 else
5795 val &= ~BRXMAC_CONFIG_ENABLE;
5796 nw64_mac(BRXMAC_CONFIG, val);
5797}
5798
5799static void niu_enable_rx_mac(struct niu *np, int on)
5800{
5801 if (np->flags & NIU_FLAGS_XMAC)
5802 niu_enable_rx_xmac(np, on);
5803 else
5804 niu_enable_rx_bmac(np, on);
5805}
5806
5807static int niu_init_mac(struct niu *np)
5808{
5809 int err;
5810
5811 niu_init_xif(np);
5812 err = niu_init_pcs(np);
5813 if (err)
5814 return err;
5815
5816 err = niu_reset_tx_mac(np);
5817 if (err)
5818 return err;
5819 niu_init_tx_mac(np);
5820 err = niu_reset_rx_mac(np);
5821 if (err)
5822 return err;
5823 niu_init_rx_mac(np);
5824
5825 /* This looks hookey but the RX MAC reset we just did will
5826 * undo some of the state we setup in niu_init_tx_mac() so we
5827 * have to call it again. In particular, the RX MAC reset will
5828 * set the XMAC_MAX register back to it's default value.
5829 */
5830 niu_init_tx_mac(np);
5831 niu_enable_tx_mac(np, 1);
5832
5833 niu_enable_rx_mac(np, 1);
5834
5835 return 0;
5836}
5837
5838static void niu_stop_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5839{
5840 (void) niu_tx_channel_stop(np, rp->tx_channel);
5841}
5842
5843static void niu_stop_tx_channels(struct niu *np)
5844{
5845 int i;
5846
5847 for (i = 0; i < np->num_tx_rings; i++) {
5848 struct tx_ring_info *rp = &np->tx_rings[i];
5849
5850 niu_stop_one_tx_channel(np, rp);
5851 }
5852}
5853
5854static void niu_reset_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5855{
5856 (void) niu_tx_channel_reset(np, rp->tx_channel);
5857}
5858
5859static void niu_reset_tx_channels(struct niu *np)
5860{
5861 int i;
5862
5863 for (i = 0; i < np->num_tx_rings; i++) {
5864 struct tx_ring_info *rp = &np->tx_rings[i];
5865
5866 niu_reset_one_tx_channel(np, rp);
5867 }
5868}
5869
5870static void niu_stop_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5871{
5872 (void) niu_enable_rx_channel(np, rp->rx_channel, 0);
5873}
5874
5875static void niu_stop_rx_channels(struct niu *np)
5876{
5877 int i;
5878
5879 for (i = 0; i < np->num_rx_rings; i++) {
5880 struct rx_ring_info *rp = &np->rx_rings[i];
5881
5882 niu_stop_one_rx_channel(np, rp);
5883 }
5884}
5885
5886static void niu_reset_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5887{
5888 int channel = rp->rx_channel;
5889
5890 (void) niu_rx_channel_reset(np, channel);
5891 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL);
5892 nw64(RX_DMA_CTL_STAT(channel), 0);
5893 (void) niu_enable_rx_channel(np, channel, 0);
5894}
5895
5896static void niu_reset_rx_channels(struct niu *np)
5897{
5898 int i;
5899
5900 for (i = 0; i < np->num_rx_rings; i++) {
5901 struct rx_ring_info *rp = &np->rx_rings[i];
5902
5903 niu_reset_one_rx_channel(np, rp);
5904 }
5905}
5906
5907static void niu_disable_ipp(struct niu *np)
5908{
5909 u64 rd, wr, val;
5910 int limit;
5911
5912 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5913 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5914 limit = 100;
5915 while (--limit >= 0 && (rd != wr)) {
5916 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5917 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5918 }
5919 if (limit < 0 &&
5920 (rd != 0 && wr != 1)) {
f10a1f2e
JP		 5921 netdev_err(np->dev, "IPP would not quiesce, rd_ptr[%llx] wr_ptr[%llx]\n",
5922 (unsigned long long)nr64_ipp(IPP_DFIFO_RD_PTR),
5923 (unsigned long long)nr64_ipp(IPP_DFIFO_WR_PTR));
a3138df9
DM		 5924 }
5925
5926 val = nr64_ipp(IPP_CFIG);
5927 val &= ~(IPP_CFIG_IPP_ENABLE |
5928 IPP_CFIG_DFIFO_ECC_EN |
5929 IPP_CFIG_DROP_BAD_CRC |
5930 IPP_CFIG_CKSUM_EN);
5931 nw64_ipp(IPP_CFIG, val);
5932
5933 (void) niu_ipp_reset(np);
5934}
5935
5936static int niu_init_hw(struct niu *np)
5937{
5938 int i, err;
5939
f10a1f2e 5940 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TXC\n");
a3138df9
DM		 5941 niu_txc_enable_port(np, 1);
5942 niu_txc_port_dma_enable(np, 1);
5943 niu_txc_set_imask(np, 0);
5944
f10a1f2e 5945 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TX channels\n");
a3138df9
DM		 5946 for (i = 0; i < np->num_tx_rings; i++) {
5947 struct tx_ring_info *rp = &np->tx_rings[i];
5948
5949 err = niu_init_one_tx_channel(np, rp);
5950 if (err)
5951 return err;
5952 }
5953
f10a1f2e 5954 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize RX channels\n");
a3138df9
DM		 5955 err = niu_init_rx_channels(np);
5956 if (err)
5957 goto out_uninit_tx_channels;
5958
f10a1f2e 5959 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize classifier\n");
a3138df9
DM		 5960 err = niu_init_classifier_hw(np);
5961 if (err)
5962 goto out_uninit_rx_channels;
5963
f10a1f2e 5964 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize ZCP\n");
a3138df9
DM		 5965 err = niu_init_zcp(np);
5966 if (err)
5967 goto out_uninit_rx_channels;
5968
f10a1f2e 5969 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize IPP\n");
a3138df9
DM		 5970 err = niu_init_ipp(np);
5971 if (err)
5972 goto out_uninit_rx_channels;
5973
f10a1f2e 5974 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize MAC\n");
a3138df9
DM		 5975 err = niu_init_mac(np);
5976 if (err)
5977 goto out_uninit_ipp;
5978
5979 return 0;
5980
5981out_uninit_ipp:
f10a1f2e 5982 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit IPP\n");
a3138df9
DM		 5983 niu_disable_ipp(np);
5984
5985out_uninit_rx_channels:
f10a1f2e 5986 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit RX channels\n");
a3138df9
DM		 5987 niu_stop_rx_channels(np);
5988 niu_reset_rx_channels(np);
5989
5990out_uninit_tx_channels:
f10a1f2e 5991 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit TX channels\n");
a3138df9
DM		 5992 niu_stop_tx_channels(np);
5993 niu_reset_tx_channels(np);
5994
5995 return err;
5996}
5997
5998static void niu_stop_hw(struct niu *np)
5999{
f10a1f2e 6000 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable interrupts\n");
a3138df9
DM		 6001 niu_enable_interrupts(np, 0);
6002
f10a1f2e 6003 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable RX MAC\n");
a3138df9
DM		 6004 niu_enable_rx_mac(np, 0);
6005
f10a1f2e 6006 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable IPP\n");
a3138df9
DM		 6007 niu_disable_ipp(np);
6008
f10a1f2e 6009 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop TX channels\n");
a3138df9
DM		 6010 niu_stop_tx_channels(np);
6011
f10a1f2e 6012 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop RX channels\n");
a3138df9
DM		 6013 niu_stop_rx_channels(np);
6014
f10a1f2e 6015 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset TX channels\n");
a3138df9
DM		 6016 niu_reset_tx_channels(np);
6017
f10a1f2e 6018 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset RX channels\n");
a3138df9
DM		 6019 niu_reset_rx_channels(np);
6020}
6021
70340d72
RO		 6022static void niu_set_irq_name(struct niu *np)
6023{
6024 int port = np->port;
6025 int i, j = 1;
6026
6027 sprintf(np->irq_name[0], "%s:MAC", np->dev->name);
6028
6029 if (port == 0) {
6030 sprintf(np->irq_name[1], "%s:MIF", np->dev->name);
6031 sprintf(np->irq_name[2], "%s:SYSERR", np->dev->name);
6032 j = 3;
6033 }
6034
6035 for (i = 0; i < np->num_ldg - j; i++) {
6036 if (i < np->num_rx_rings)
6037 sprintf(np->irq_name[i+j], "%s-rx-%d",
6038 np->dev->name, i);
6039 else if (i < np->num_tx_rings + np->num_rx_rings)
6040 sprintf(np->irq_name[i+j], "%s-tx-%d", np->dev->name,
6041 i - np->num_rx_rings);
6042 }
6043}
6044
a3138df9
DM		 6045static int niu_request_irq(struct niu *np)
6046{
6047 int i, j, err;
6048
70340d72
RO		 6049 niu_set_irq_name(np);
6050
a3138df9
DM		 6051 err = 0;
6052 for (i = 0; i < np->num_ldg; i++) {
6053 struct niu_ldg *lp = &np->ldg[i];
6054
6055 err = request_irq(lp->irq, niu_interrupt,
6056 IRQF_SHARED | IRQF_SAMPLE_RANDOM,
70340d72 6057 np->irq_name[i], lp);
a3138df9
DM		 6058 if (err)
6059 goto out_free_irqs;
6060
6061 }
6062
6063 return 0;
6064
6065out_free_irqs:
6066 for (j = 0; j < i; j++) {
6067 struct niu_ldg *lp = &np->ldg[j];
6068
6069 free_irq(lp->irq, lp);
6070 }
6071 return err;
6072}
6073
6074static void niu_free_irq(struct niu *np)
6075{
6076 int i;
6077
6078 for (i = 0; i < np->num_ldg; i++) {
6079 struct niu_ldg *lp = &np->ldg[i];
6080
6081 free_irq(lp->irq, lp);
6082 }
6083}
6084
6085static void niu_enable_napi(struct niu *np)
6086{
6087 int i;
6088
6089 for (i = 0; i < np->num_ldg; i++)
6090 napi_enable(&np->ldg[i].napi);
6091}
6092
6093static void niu_disable_napi(struct niu *np)
6094{
6095 int i;
6096
6097 for (i = 0; i < np->num_ldg; i++)
6098 napi_disable(&np->ldg[i].napi);
6099}
6100
6101static int niu_open(struct net_device *dev)
6102{
6103 struct niu *np = netdev_priv(dev);
6104 int err;
6105
6106 netif_carrier_off(dev);
6107
6108 err = niu_alloc_channels(np);
6109 if (err)
6110 goto out_err;
6111
6112 err = niu_enable_interrupts(np, 0);
6113 if (err)
6114 goto out_free_channels;
6115
6116 err = niu_request_irq(np);
6117 if (err)
6118 goto out_free_channels;
6119
6120 niu_enable_napi(np);
6121
6122 spin_lock_irq(&np->lock);
6123
6124 err = niu_init_hw(np);
6125 if (!err) {
6126 init_timer(&np->timer);
6127 np->timer.expires = jiffies + HZ;
6128 np->timer.data = (unsigned long) np;
6129 np->timer.function = niu_timer;
6130
6131 err = niu_enable_interrupts(np, 1);
6132 if (err)
6133 niu_stop_hw(np);
6134 }
6135
6136 spin_unlock_irq(&np->lock);
6137
6138 if (err) {
6139 niu_disable_napi(np);
6140 goto out_free_irq;
6141 }
6142
b4c21639 6143 netif_tx_start_all_queues(dev);
a3138df9
DM		 6144
6145 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6146 netif_carrier_on(dev);
6147
6148 add_timer(&np->timer);
6149
6150 return 0;
6151
6152out_free_irq:
6153 niu_free_irq(np);
6154
6155out_free_channels:
6156 niu_free_channels(np);
6157
6158out_err:
6159 return err;
6160}
6161
6162static void niu_full_shutdown(struct niu *np, struct net_device *dev)
6163{
6164 cancel_work_sync(&np->reset_task);
6165
6166 niu_disable_napi(np);
b4c21639 6167 netif_tx_stop_all_queues(dev);
a3138df9
DM		 6168
6169 del_timer_sync(&np->timer);
6170
6171 spin_lock_irq(&np->lock);
6172
6173 niu_stop_hw(np);
6174
6175 spin_unlock_irq(&np->lock);
6176}
6177
6178static int niu_close(struct net_device *dev)
6179{
6180 struct niu *np = netdev_priv(dev);
6181
6182 niu_full_shutdown(np, dev);
6183
6184 niu_free_irq(np);
6185
6186 niu_free_channels(np);
6187
0c3b091b
ML		 6188 niu_handle_led(np, 0);
6189
a3138df9
DM		 6190 return 0;
6191}
6192
6193static void niu_sync_xmac_stats(struct niu *np)
6194{
6195 struct niu_xmac_stats *mp = &np->mac_stats.xmac;
6196
6197 mp->tx_frames += nr64_mac(TXMAC_FRM_CNT);
6198 mp->tx_bytes += nr64_mac(TXMAC_BYTE_CNT);
6199
6200 mp->rx_link_faults += nr64_mac(LINK_FAULT_CNT);
6201 mp->rx_align_errors += nr64_mac(RXMAC_ALIGN_ERR_CNT);
6202 mp->rx_frags += nr64_mac(RXMAC_FRAG_CNT);
6203 mp->rx_mcasts += nr64_mac(RXMAC_MC_FRM_CNT);
6204 mp->rx_bcasts += nr64_mac(RXMAC_BC_FRM_CNT);
6205 mp->rx_hist_cnt1 += nr64_mac(RXMAC_HIST_CNT1);
6206 mp->rx_hist_cnt2 += nr64_mac(RXMAC_HIST_CNT2);
6207 mp->rx_hist_cnt3 += nr64_mac(RXMAC_HIST_CNT3);
6208 mp->rx_hist_cnt4 += nr64_mac(RXMAC_HIST_CNT4);
6209 mp->rx_hist_cnt5 += nr64_mac(RXMAC_HIST_CNT5);
6210 mp->rx_hist_cnt6 += nr64_mac(RXMAC_HIST_CNT6);
6211 mp->rx_hist_cnt7 += nr64_mac(RXMAC_HIST_CNT7);
6212 mp->rx_octets += nr64_mac(RXMAC_BT_CNT);
6213 mp->rx_code_violations += nr64_mac(RXMAC_CD_VIO_CNT);
6214 mp->rx_len_errors += nr64_mac(RXMAC_MPSZER_CNT);
6215 mp->rx_crc_errors += nr64_mac(RXMAC_CRC_ER_CNT);
6216}
6217
6218static void niu_sync_bmac_stats(struct niu *np)
6219{
6220 struct niu_bmac_stats *mp = &np->mac_stats.bmac;
6221
6222 mp->tx_bytes += nr64_mac(BTXMAC_BYTE_CNT);
6223 mp->tx_frames += nr64_mac(BTXMAC_FRM_CNT);
6224
6225 mp->rx_frames += nr64_mac(BRXMAC_FRAME_CNT);
6226 mp->rx_align_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6227 mp->rx_crc_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6228 mp->rx_len_errors += nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT);
6229}
6230
6231static void niu_sync_mac_stats(struct niu *np)
6232{
6233 if (np->flags & NIU_FLAGS_XMAC)
6234 niu_sync_xmac_stats(np);
6235 else
6236 niu_sync_bmac_stats(np);
6237}
6238
6239static void niu_get_rx_stats(struct niu *np)
6240{
6241 unsigned long pkts, dropped, errors, bytes;
6242 int i;
6243
6244 pkts = dropped = errors = bytes = 0;
6245 for (i = 0; i < np->num_rx_rings; i++) {
6246 struct rx_ring_info *rp = &np->rx_rings[i];
6247
b8a606b8
JDB		 6248 niu_sync_rx_discard_stats(np, rp, 0);
6249
a3138df9
DM		 6250 pkts += rp->rx_packets;
6251 bytes += rp->rx_bytes;
6252 dropped += rp->rx_dropped;
6253 errors += rp->rx_errors;
6254 }
9fd42876
IJ		 6255 np->dev->stats.rx_packets = pkts;
6256 np->dev->stats.rx_bytes = bytes;
6257 np->dev->stats.rx_dropped = dropped;
6258 np->dev->stats.rx_errors = errors;
a3138df9
DM		 6259}
6260
6261static void niu_get_tx_stats(struct niu *np)
6262{
6263 unsigned long pkts, errors, bytes;
6264 int i;
6265
6266 pkts = errors = bytes = 0;
6267 for (i = 0; i < np->num_tx_rings; i++) {
6268 struct tx_ring_info *rp = &np->tx_rings[i];
6269
6270 pkts += rp->tx_packets;
6271 bytes += rp->tx_bytes;
6272 errors += rp->tx_errors;
6273 }
9fd42876
IJ		 6274 np->dev->stats.tx_packets = pkts;
6275 np->dev->stats.tx_bytes = bytes;
6276 np->dev->stats.tx_errors = errors;
a3138df9
DM		 6277}
6278
6279static struct net_device_stats *niu_get_stats(struct net_device *dev)
6280{
6281 struct niu *np = netdev_priv(dev);
6282
6283 niu_get_rx_stats(np);
6284 niu_get_tx_stats(np);
6285
9fd42876 6286 return &dev->stats;
a3138df9
DM		 6287}
6288
6289static void niu_load_hash_xmac(struct niu *np, u16 *hash)
6290{
6291 int i;
6292
6293 for (i = 0; i < 16; i++)
6294 nw64_mac(XMAC_HASH_TBL(i), hash[i]);
6295}
6296
6297static void niu_load_hash_bmac(struct niu *np, u16 *hash)
6298{
6299 int i;
6300
6301 for (i = 0; i < 16; i++)
6302 nw64_mac(BMAC_HASH_TBL(i), hash[i]);
6303}
6304
6305static void niu_load_hash(struct niu *np, u16 *hash)
6306{
6307 if (np->flags & NIU_FLAGS_XMAC)
6308 niu_load_hash_xmac(np, hash);
6309 else
6310 niu_load_hash_bmac(np, hash);
6311}
6312
6313static void niu_set_rx_mode(struct net_device *dev)
6314{
6315 struct niu *np = netdev_priv(dev);
6316 int i, alt_cnt, err;
ccffad25 6317 struct netdev_hw_addr *ha;
a3138df9
DM		 6318 unsigned long flags;
6319 u16 hash[16] = { 0, };
6320
6321 spin_lock_irqsave(&np->lock, flags);
6322 niu_enable_rx_mac(np, 0);
6323
6324 np->flags &= ~(NIU_FLAGS_MCAST | NIU_FLAGS_PROMISC);
6325 if (dev->flags & IFF_PROMISC)
6326 np->flags |= NIU_FLAGS_PROMISC;
4cd24eaf 6327 if ((dev->flags & IFF_ALLMULTI) || (!netdev_mc_empty(dev)))
a3138df9
DM		 6328 np->flags |= NIU_FLAGS_MCAST;
6329
32e7bfc4 6330 alt_cnt = netdev_uc_count(dev);
a3138df9
DM		 6331 if (alt_cnt > niu_num_alt_addr(np)) {
6332 alt_cnt = 0;
6333 np->flags |= NIU_FLAGS_PROMISC;
6334 }
6335
6336 if (alt_cnt) {
6337 int index = 0;
6338
32e7bfc4 6339 netdev_for_each_uc_addr(ha, dev) {
ccffad25 6340 err = niu_set_alt_mac(np, index, ha->addr);
a3138df9 6341 if (err)
f10a1f2e
JP		 6342 netdev_warn(dev, "Error %d adding alt mac %d\n",
6343 err, index);
a3138df9
DM		 6344 err = niu_enable_alt_mac(np, index, 1);
6345 if (err)
f10a1f2e
JP		 6346 netdev_warn(dev, "Error %d enabling alt mac %d\n",
6347 err, index);
a3138df9
DM		 6348
6349 index++;
6350 }
6351 } else {
3b5bcede
MW		 6352 int alt_start;
6353 if (np->flags & NIU_FLAGS_XMAC)
6354 alt_start = 0;
6355 else
6356 alt_start = 1;
6357 for (i = alt_start; i < niu_num_alt_addr(np); i++) {
a3138df9
DM		 6358 err = niu_enable_alt_mac(np, i, 0);
6359 if (err)
f10a1f2e
JP		 6360 netdev_warn(dev, "Error %d disabling alt mac %d\n",
6361 err, i);
a3138df9
DM		 6362 }
6363 }
6364 if (dev->flags & IFF_ALLMULTI) {
6365 for (i = 0; i < 16; i++)
6366 hash[i] = 0xffff;
4cd24eaf 6367 } else if (!netdev_mc_empty(dev)) {
22bedad3
JP		 6368 netdev_for_each_mc_addr(ha, dev) {
6369 u32 crc = ether_crc_le(ETH_ALEN, ha->addr);
a3138df9
DM		 6370
6371 crc >>= 24;
6372 hash[crc >> 4] |= (1 << (15 - (crc & 0xf)));
6373 }
6374 }
6375
6376 if (np->flags & NIU_FLAGS_MCAST)
6377 niu_load_hash(np, hash);
6378
6379 niu_enable_rx_mac(np, 1);
6380 spin_unlock_irqrestore(&np->lock, flags);
6381}
6382
6383static int niu_set_mac_addr(struct net_device *dev, void *p)
6384{
6385 struct niu *np = netdev_priv(dev);
6386 struct sockaddr *addr = p;
6387 unsigned long flags;
6388
6389 if (!is_valid_ether_addr(addr->sa_data))
6390 return -EINVAL;
6391
6392 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
6393
6394 if (!netif_running(dev))
6395 return 0;
6396
6397 spin_lock_irqsave(&np->lock, flags);
6398 niu_enable_rx_mac(np, 0);
6399 niu_set_primary_mac(np, dev->dev_addr);
6400 niu_enable_rx_mac(np, 1);
6401 spin_unlock_irqrestore(&np->lock, flags);
6402
6403 return 0;
6404}
6405
6406static int niu_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6407{
6408 return -EOPNOTSUPP;
6409}
6410
6411static void niu_netif_stop(struct niu *np)
6412{
6413 np->dev->trans_start = jiffies; /* prevent tx timeout */
6414
6415 niu_disable_napi(np);
6416
6417 netif_tx_disable(np->dev);
6418}
6419
6420static void niu_netif_start(struct niu *np)
6421{
6422 /* NOTE: unconditional netif_wake_queue is only appropriate
6423 * so long as all callers are assured to have free tx slots
6424 * (such as after niu_init_hw).
6425 */
b4c21639 6426 netif_tx_wake_all_queues(np->dev);
a3138df9
DM		 6427
6428 niu_enable_napi(np);
6429
6430 niu_enable_interrupts(np, 1);
6431}
6432
cff502a3
SB		 6433static void niu_reset_buffers(struct niu *np)
6434{
6435 int i, j, k, err;
6436
6437 if (np->rx_rings) {
6438 for (i = 0; i < np->num_rx_rings; i++) {
6439 struct rx_ring_info *rp = &np->rx_rings[i];
6440
6441 for (j = 0, k = 0; j < MAX_RBR_RING_SIZE; j++) {
6442 struct page *page;
6443
6444 page = rp->rxhash[j];
6445 while (page) {
6446 struct page *next =
6447 (struct page *) page->mapping;
6448 u64 base = page->index;
6449 base = base >> RBR_DESCR_ADDR_SHIFT;
6450 rp->rbr[k++] = cpu_to_le32(base);
6451 page = next;
6452 }
6453 }
6454 for (; k < MAX_RBR_RING_SIZE; k++) {
6455 err = niu_rbr_add_page(np, rp, GFP_ATOMIC, k);
6456 if (unlikely(err))
6457 break;
6458 }
6459
6460 rp->rbr_index = rp->rbr_table_size - 1;
6461 rp->rcr_index = 0;
6462 rp->rbr_pending = 0;
6463 rp->rbr_refill_pending = 0;
6464 }
6465 }
6466 if (np->tx_rings) {
6467 for (i = 0; i < np->num_tx_rings; i++) {
6468 struct tx_ring_info *rp = &np->tx_rings[i];
6469
6470 for (j = 0; j < MAX_TX_RING_SIZE; j++) {
6471 if (rp->tx_buffs[j].skb)
6472 (void) release_tx_packet(np, rp, j);
6473 }
6474
6475 rp->pending = MAX_TX_RING_SIZE;
6476 rp->prod = 0;
6477 rp->cons = 0;
6478 rp->wrap_bit = 0;
6479 }
6480 }
6481}
6482
a3138df9
DM		 6483static void niu_reset_task(struct work_struct *work)
6484{
6485 struct niu *np = container_of(work, struct niu, reset_task);
6486 unsigned long flags;
6487 int err;
6488
6489 spin_lock_irqsave(&np->lock, flags);
6490 if (!netif_running(np->dev)) {
6491 spin_unlock_irqrestore(&np->lock, flags);
6492 return;
6493 }
6494
6495 spin_unlock_irqrestore(&np->lock, flags);
6496
6497 del_timer_sync(&np->timer);
6498
6499 niu_netif_stop(np);
6500
6501 spin_lock_irqsave(&np->lock, flags);
6502
6503 niu_stop_hw(np);
6504
cff502a3
SB		 6505 spin_unlock_irqrestore(&np->lock, flags);
6506
6507 niu_reset_buffers(np);
6508
6509 spin_lock_irqsave(&np->lock, flags);
6510
a3138df9
DM		 6511 err = niu_init_hw(np);
6512 if (!err) {
6513 np->timer.expires = jiffies + HZ;
6514 add_timer(&np->timer);
6515 niu_netif_start(np);
6516 }
6517
6518 spin_unlock_irqrestore(&np->lock, flags);
6519}
6520
6521static void niu_tx_timeout(struct net_device *dev)
6522{
6523 struct niu *np = netdev_priv(dev);
6524
f10a1f2e 6525 dev_err(np->device, "%s: Transmit timed out, resetting\n",
a3138df9
DM		 6526 dev->name);
6527
6528 schedule_work(&np->reset_task);
6529}
6530
6531static void niu_set_txd(struct tx_ring_info *rp, int index,
6532 u64 mapping, u64 len, u64 mark,
6533 u64 n_frags)
6534{
6535 __le64 *desc = &rp->descr[index];
6536
6537 *desc = cpu_to_le64(mark |
6538 (n_frags << TX_DESC_NUM_PTR_SHIFT) |
6539 (len << TX_DESC_TR_LEN_SHIFT) |
6540 (mapping & TX_DESC_SAD));
6541}
6542
6543static u64 niu_compute_tx_flags(struct sk_buff *skb, struct ethhdr *ehdr,
6544 u64 pad_bytes, u64 len)
6545{
6546 u16 eth_proto, eth_proto_inner;
6547 u64 csum_bits, l3off, ihl, ret;
6548 u8 ip_proto;
6549 int ipv6;
6550
6551 eth_proto = be16_to_cpu(ehdr->h_proto);
6552 eth_proto_inner = eth_proto;
6553 if (eth_proto == ETH_P_8021Q) {
6554 struct vlan_ethhdr *vp = (struct vlan_ethhdr *) ehdr;
6555 __be16 val = vp->h_vlan_encapsulated_proto;
6556
6557 eth_proto_inner = be16_to_cpu(val);
6558 }
6559
6560 ipv6 = ihl = 0;
6561 switch (skb->protocol) {
09640e63 6562 case cpu_to_be16(ETH_P_IP):
a3138df9
DM		 6563 ip_proto = ip_hdr(skb)->protocol;
6564 ihl = ip_hdr(skb)->ihl;
6565 break;
09640e63 6566 case cpu_to_be16(ETH_P_IPV6):
a3138df9
DM		 6567 ip_proto = ipv6_hdr(skb)->nexthdr;
6568 ihl = (40 >> 2);
6569 ipv6 = 1;
6570 break;
6571 default:
6572 ip_proto = ihl = 0;
6573 break;
6574 }
6575
6576 csum_bits = TXHDR_CSUM_NONE;
6577 if (skb->ip_summed == CHECKSUM_PARTIAL) {
6578 u64 start, stuff;
6579
6580 csum_bits = (ip_proto == IPPROTO_TCP ?
6581 TXHDR_CSUM_TCP :
6582 (ip_proto == IPPROTO_UDP ?
6583 TXHDR_CSUM_UDP : TXHDR_CSUM_SCTP));
6584
6585 start = skb_transport_offset(skb) -
6586 (pad_bytes + sizeof(struct tx_pkt_hdr));
6587 stuff = start + skb->csum_offset;
6588
6589 csum_bits |= (start / 2) << TXHDR_L4START_SHIFT;
6590 csum_bits |= (stuff / 2) << TXHDR_L4STUFF_SHIFT;
6591 }
6592
6593 l3off = skb_network_offset(skb) -
6594 (pad_bytes + sizeof(struct tx_pkt_hdr));
6595
6596 ret = (((pad_bytes / 2) << TXHDR_PAD_SHIFT) |
6597 (len << TXHDR_LEN_SHIFT) |
6598 ((l3off / 2) << TXHDR_L3START_SHIFT) |
6599 (ihl << TXHDR_IHL_SHIFT) |
6600 ((eth_proto_inner < 1536) ? TXHDR_LLC : 0) |
6601 ((eth_proto == ETH_P_8021Q) ? TXHDR_VLAN : 0) |
6602 (ipv6 ? TXHDR_IP_VER : 0) |
6603 csum_bits);
6604
6605 return ret;
6606}
6607
61357325
SH		 6608static netdev_tx_t niu_start_xmit(struct sk_buff *skb,
6609 struct net_device *dev)
a3138df9
DM		 6610{
6611 struct niu *np = netdev_priv(dev);
6612 unsigned long align, headroom;
b4c21639 6613 struct netdev_queue *txq;
a3138df9
DM		 6614 struct tx_ring_info *rp;
6615 struct tx_pkt_hdr *tp;
6616 unsigned int len, nfg;
6617 struct ethhdr *ehdr;
6618 int prod, i, tlen;
6619 u64 mapping, mrk;
6620
b4c21639
DM		 6621 i = skb_get_queue_mapping(skb);
6622 rp = &np->tx_rings[i];
6623 txq = netdev_get_tx_queue(dev, i);
a3138df9
DM		 6624
6625 if (niu_tx_avail(rp) <= (skb_shinfo(skb)->nr_frags + 1)) {
b4c21639 6626 netif_tx_stop_queue(txq);
f10a1f2e 6627 dev_err(np->device, "%s: BUG! Tx ring full when queue awake!\n", dev->name);
a3138df9
DM		 6628 rp->tx_errors++;
6629 return NETDEV_TX_BUSY;
6630 }
6631
6632 if (skb->len < ETH_ZLEN) {
6633 unsigned int pad_bytes = ETH_ZLEN - skb->len;
6634
6635 if (skb_pad(skb, pad_bytes))
6636 goto out;
6637 skb_put(skb, pad_bytes);
6638 }
6639
6640 len = sizeof(struct tx_pkt_hdr) + 15;
6641 if (skb_headroom(skb) < len) {
6642 struct sk_buff *skb_new;
6643
6644 skb_new = skb_realloc_headroom(skb, len);
6645 if (!skb_new) {
6646 rp->tx_errors++;
6647 goto out_drop;
6648 }
6649 kfree_skb(skb);
6650 skb = skb_new;
3ebebccf
DM		 6651 } else
6652 skb_orphan(skb);
a3138df9
DM		 6653
6654 align = ((unsigned long) skb->data & (16 - 1));
6655 headroom = align + sizeof(struct tx_pkt_hdr);
6656
6657 ehdr = (struct ethhdr *) skb->data;
6658 tp = (struct tx_pkt_hdr *) skb_push(skb, headroom);
6659
6660 len = skb->len - sizeof(struct tx_pkt_hdr);
6661 tp->flags = cpu_to_le64(niu_compute_tx_flags(skb, ehdr, align, len));
6662 tp->resv = 0;
6663
6664 len = skb_headlen(skb);
6665 mapping = np->ops->map_single(np->device, skb->data,
6666 len, DMA_TO_DEVICE);
6667
6668 prod = rp->prod;
6669
6670 rp->tx_buffs[prod].skb = skb;
6671 rp->tx_buffs[prod].mapping = mapping;
6672
6673 mrk = TX_DESC_SOP;
6674 if (++rp->mark_counter == rp->mark_freq) {
6675 rp->mark_counter = 0;
6676 mrk |= TX_DESC_MARK;
6677 rp->mark_pending++;
6678 }
6679
6680 tlen = len;
6681 nfg = skb_shinfo(skb)->nr_frags;
6682 while (tlen > 0) {
6683 tlen -= MAX_TX_DESC_LEN;
6684 nfg++;
6685 }
6686
6687 while (len > 0) {
6688 unsigned int this_len = len;
6689
6690 if (this_len > MAX_TX_DESC_LEN)
6691 this_len = MAX_TX_DESC_LEN;
6692
6693 niu_set_txd(rp, prod, mapping, this_len, mrk, nfg);
6694 mrk = nfg = 0;
6695
6696 prod = NEXT_TX(rp, prod);
6697 mapping += this_len;
6698 len -= this_len;
6699 }
6700
6701 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6702 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6703
6704 len = frag->size;
6705 mapping = np->ops->map_page(np->device, frag->page,
6706 frag->page_offset, len,
6707 DMA_TO_DEVICE);
6708
6709 rp->tx_buffs[prod].skb = NULL;
6710 rp->tx_buffs[prod].mapping = mapping;
6711
6712 niu_set_txd(rp, prod, mapping, len, 0, 0);
6713
6714 prod = NEXT_TX(rp, prod);
6715 }
6716
6717 if (prod < rp->prod)
6718 rp->wrap_bit ^= TX_RING_KICK_WRAP;
6719 rp->prod = prod;
6720
6721 nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3));
6722
6723 if (unlikely(niu_tx_avail(rp) <= (MAX_SKB_FRAGS + 1))) {
b4c21639 6724 netif_tx_stop_queue(txq);
a3138df9 6725 if (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp))
b4c21639 6726 netif_tx_wake_queue(txq);
a3138df9
DM		 6727 }
6728
a3138df9
DM		 6729out:
6730 return NETDEV_TX_OK;
6731
6732out_drop:
6733 rp->tx_errors++;
6734 kfree_skb(skb);
6735 goto out;
6736}
6737
6738static int niu_change_mtu(struct net_device *dev, int new_mtu)
6739{
6740 struct niu *np = netdev_priv(dev);
6741 int err, orig_jumbo, new_jumbo;
6742
6743 if (new_mtu < 68 || new_mtu > NIU_MAX_MTU)
6744 return -EINVAL;
6745
6746 orig_jumbo = (dev->mtu > ETH_DATA_LEN);
6747 new_jumbo = (new_mtu > ETH_DATA_LEN);
6748
6749 dev->mtu = new_mtu;
6750
6751 if (!netif_running(dev) ||
6752 (orig_jumbo == new_jumbo))
6753 return 0;
6754
6755 niu_full_shutdown(np, dev);
6756
6757 niu_free_channels(np);
6758
6759 niu_enable_napi(np);
6760
6761 err = niu_alloc_channels(np);
6762 if (err)
6763 return err;
6764
6765 spin_lock_irq(&np->lock);
6766
6767 err = niu_init_hw(np);
6768 if (!err) {
6769 init_timer(&np->timer);
6770 np->timer.expires = jiffies + HZ;
6771 np->timer.data = (unsigned long) np;
6772 np->timer.function = niu_timer;
6773
6774 err = niu_enable_interrupts(np, 1);
6775 if (err)
6776 niu_stop_hw(np);
6777 }
6778
6779 spin_unlock_irq(&np->lock);
6780
6781 if (!err) {
b4c21639 6782 netif_tx_start_all_queues(dev);
a3138df9
DM		 6783 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6784 netif_carrier_on(dev);
6785
6786 add_timer(&np->timer);
6787 }
6788
6789 return err;
6790}
6791
6792static void niu_get_drvinfo(struct net_device *dev,
6793 struct ethtool_drvinfo *info)
6794{
6795 struct niu *np = netdev_priv(dev);
6796 struct niu_vpd *vpd = &np->vpd;
6797
6798 strcpy(info->driver, DRV_MODULE_NAME);
6799 strcpy(info->version, DRV_MODULE_VERSION);
6800 sprintf(info->fw_version, "%d.%d",
6801 vpd->fcode_major, vpd->fcode_minor);
6802 if (np->parent->plat_type != PLAT_TYPE_NIU)
6803 strcpy(info->bus_info, pci_name(np->pdev));
6804}
6805
6806static int niu_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6807{
6808 struct niu *np = netdev_priv(dev);
6809 struct niu_link_config *lp;
6810
6811 lp = &np->link_config;
6812
6813 memset(cmd, 0, sizeof(*cmd));
6814 cmd->phy_address = np->phy_addr;
6815 cmd->supported = lp->supported;
38bb045d
CB		 6816 cmd->advertising = lp->active_advertising;
6817 cmd->autoneg = lp->active_autoneg;
a3138df9
DM		 6818 cmd->speed = lp->active_speed;
6819 cmd->duplex = lp->active_duplex;
38bb045d
CB		 6820 cmd->port = (np->flags & NIU_FLAGS_FIBER) ? PORT_FIBRE : PORT_TP;
6821 cmd->transceiver = (np->flags & NIU_FLAGS_XCVR_SERDES) ?
6822 XCVR_EXTERNAL : XCVR_INTERNAL;
a3138df9
DM		 6823
6824 return 0;
6825}
6826
6827static int niu_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6828{
38bb045d
CB		 6829 struct niu *np = netdev_priv(dev);
6830 struct niu_link_config *lp = &np->link_config;
6831
6832 lp->advertising = cmd->advertising;
6833 lp->speed = cmd->speed;
6834 lp->duplex = cmd->duplex;
6835 lp->autoneg = cmd->autoneg;
6836 return niu_init_link(np);
a3138df9
DM		 6837}
6838
6839static u32 niu_get_msglevel(struct net_device *dev)
6840{
6841 struct niu *np = netdev_priv(dev);
6842 return np->msg_enable;
6843}
6844
6845static void niu_set_msglevel(struct net_device *dev, u32 value)
6846{
6847 struct niu *np = netdev_priv(dev);
6848 np->msg_enable = value;
6849}
6850
38bb045d
CB		 6851static int niu_nway_reset(struct net_device *dev)
6852{
6853 struct niu *np = netdev_priv(dev);
6854
6855 if (np->link_config.autoneg)
6856 return niu_init_link(np);
6857
6858 return 0;
6859}
6860
a3138df9
DM		 6861static int niu_get_eeprom_len(struct net_device *dev)
6862{
6863 struct niu *np = netdev_priv(dev);
6864
6865 return np->eeprom_len;
6866}
6867
6868static int niu_get_eeprom(struct net_device *dev,
6869 struct ethtool_eeprom *eeprom, u8 *data)
6870{
6871 struct niu *np = netdev_priv(dev);
6872 u32 offset, len, val;
6873
6874 offset = eeprom->offset;
6875 len = eeprom->len;
6876
6877 if (offset + len < offset)
6878 return -EINVAL;
6879 if (offset >= np->eeprom_len)
6880 return -EINVAL;
6881 if (offset + len > np->eeprom_len)
6882 len = eeprom->len = np->eeprom_len - offset;
6883
6884 if (offset & 3) {
6885 u32 b_offset, b_count;
6886
6887 b_offset = offset & 3;
6888 b_count = 4 - b_offset;
6889 if (b_count > len)
6890 b_count = len;
6891
6892 val = nr64(ESPC_NCR((offset - b_offset) / 4));
6893 memcpy(data, ((char *)&val) + b_offset, b_count);
6894 data += b_count;
6895 len -= b_count;
6896 offset += b_count;
6897 }
6898 while (len >= 4) {
6899 val = nr64(ESPC_NCR(offset / 4));
6900 memcpy(data, &val, 4);
6901 data += 4;
6902 len -= 4;
6903 offset += 4;
6904 }
6905 if (len) {
6906 val = nr64(ESPC_NCR(offset / 4));
6907 memcpy(data, &val, len);
6908 }
6909 return 0;
6910}
6911
2d96cf8c
SB		 6912static void niu_ethflow_to_l3proto(int flow_type, u8 *pid)
6913{
6914 switch (flow_type) {
6915 case TCP_V4_FLOW:
6916 case TCP_V6_FLOW:
6917 *pid = IPPROTO_TCP;
6918 break;
6919 case UDP_V4_FLOW:
6920 case UDP_V6_FLOW:
6921 *pid = IPPROTO_UDP;
6922 break;
6923 case SCTP_V4_FLOW:
6924 case SCTP_V6_FLOW:
6925 *pid = IPPROTO_SCTP;
6926 break;
6927 case AH_V4_FLOW:
6928 case AH_V6_FLOW:
6929 *pid = IPPROTO_AH;
6930 break;
6931 case ESP_V4_FLOW:
6932 case ESP_V6_FLOW:
6933 *pid = IPPROTO_ESP;
6934 break;
6935 default:
6936 *pid = 0;
6937 break;
6938 }
6939}
6940
6941static int niu_class_to_ethflow(u64 class, int *flow_type)
6942{
6943 switch (class) {
6944 case CLASS_CODE_TCP_IPV4:
6945 *flow_type = TCP_V4_FLOW;
6946 break;
6947 case CLASS_CODE_UDP_IPV4:
6948 *flow_type = UDP_V4_FLOW;
6949 break;
6950 case CLASS_CODE_AH_ESP_IPV4:
6951 *flow_type = AH_V4_FLOW;
6952 break;
6953 case CLASS_CODE_SCTP_IPV4:
6954 *flow_type = SCTP_V4_FLOW;
6955 break;
6956 case CLASS_CODE_TCP_IPV6:
6957 *flow_type = TCP_V6_FLOW;
6958 break;
6959 case CLASS_CODE_UDP_IPV6:
6960 *flow_type = UDP_V6_FLOW;
6961 break;
6962 case CLASS_CODE_AH_ESP_IPV6:
6963 *flow_type = AH_V6_FLOW;
6964 break;
6965 case CLASS_CODE_SCTP_IPV6:
6966 *flow_type = SCTP_V6_FLOW;
6967 break;
6968 case CLASS_CODE_USER_PROG1:
6969 case CLASS_CODE_USER_PROG2:
6970 case CLASS_CODE_USER_PROG3:
6971 case CLASS_CODE_USER_PROG4:
6972 *flow_type = IP_USER_FLOW;
6973 break;
6974 default:
6975 return 0;
6976 }
6977
6978 return 1;
6979}
6980
b4653e99
SB		 6981static int niu_ethflow_to_class(int flow_type, u64 *class)
6982{
6983 switch (flow_type) {
6984 case TCP_V4_FLOW:
6985 *class = CLASS_CODE_TCP_IPV4;
6986 break;
6987 case UDP_V4_FLOW:
6988 *class = CLASS_CODE_UDP_IPV4;
6989 break;
2d96cf8c
SB		 6990 case AH_V4_FLOW:
6991 case ESP_V4_FLOW:
b4653e99
SB		 6992 *class = CLASS_CODE_AH_ESP_IPV4;
6993 break;
6994 case SCTP_V4_FLOW:
6995 *class = CLASS_CODE_SCTP_IPV4;
6996 break;
6997 case TCP_V6_FLOW:
6998 *class = CLASS_CODE_TCP_IPV6;
6999 break;
7000 case UDP_V6_FLOW:
7001 *class = CLASS_CODE_UDP_IPV6;
7002 break;
2d96cf8c
SB		 7003 case AH_V6_FLOW:
7004 case ESP_V6_FLOW:
b4653e99
SB		 7005 *class = CLASS_CODE_AH_ESP_IPV6;
7006 break;
7007 case SCTP_V6_FLOW:
7008 *class = CLASS_CODE_SCTP_IPV6;
7009 break;
7010 default:
38c080ff 7011 return 0;
b4653e99
SB		 7012 }
7013
7014 return 1;
7015}
7016
7017static u64 niu_flowkey_to_ethflow(u64 flow_key)
7018{
7019 u64 ethflow = 0;
7020
b4653e99
SB		 7021 if (flow_key & FLOW_KEY_L2DA)
7022 ethflow |= RXH_L2DA;
7023 if (flow_key & FLOW_KEY_VLAN)
7024 ethflow |= RXH_VLAN;
7025 if (flow_key & FLOW_KEY_IPSA)
7026 ethflow |= RXH_IP_SRC;
7027 if (flow_key & FLOW_KEY_IPDA)
7028 ethflow |= RXH_IP_DST;
7029 if (flow_key & FLOW_KEY_PROTO)
7030 ethflow |= RXH_L3_PROTO;
7031 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT))
7032 ethflow |= RXH_L4_B_0_1;
7033 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT))
7034 ethflow |= RXH_L4_B_2_3;
7035
7036 return ethflow;
7037
7038}
7039
7040static int niu_ethflow_to_flowkey(u64 ethflow, u64 *flow_key)
7041{
7042 u64 key = 0;
7043
b4653e99
SB		 7044 if (ethflow & RXH_L2DA)
7045 key |= FLOW_KEY_L2DA;
7046 if (ethflow & RXH_VLAN)
7047 key |= FLOW_KEY_VLAN;
7048 if (ethflow & RXH_IP_SRC)
7049 key |= FLOW_KEY_IPSA;
7050 if (ethflow & RXH_IP_DST)
7051 key |= FLOW_KEY_IPDA;
7052 if (ethflow & RXH_L3_PROTO)
7053 key |= FLOW_KEY_PROTO;
7054 if (ethflow & RXH_L4_B_0_1)
7055 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT);
7056 if (ethflow & RXH_L4_B_2_3)
7057 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT);
7058
7059 *flow_key = key;
7060
7061 return 1;
7062
7063}
7064
2d96cf8c 7065static int niu_get_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc)
b4653e99 7066{
b4653e99
SB		 7067 u64 class;
7068
2d96cf8c 7069 nfc->data = 0;
b4653e99 7070
2d96cf8c 7071 if (!niu_ethflow_to_class(nfc->flow_type, &class))
b4653e99
SB		 7072 return -EINVAL;
7073
7074 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
7075 TCAM_KEY_DISC)
2d96cf8c 7076 nfc->data = RXH_DISCARD;
b4653e99 7077 else
2d96cf8c 7078 nfc->data = niu_flowkey_to_ethflow(np->parent->flow_key[class -
b4653e99
SB		 7079 CLASS_CODE_USER_PROG1]);
7080 return 0;
7081}
7082
2d96cf8c
SB		 7083static void niu_get_ip4fs_from_tcam_key(struct niu_tcam_entry *tp,
7084 struct ethtool_rx_flow_spec *fsp)
7085{
7086
7087 fsp->h_u.tcp_ip4_spec.ip4src = (tp->key[3] & TCAM_V4KEY3_SADDR) >>
7088 TCAM_V4KEY3_SADDR_SHIFT;
7089 fsp->h_u.tcp_ip4_spec.ip4dst = (tp->key[3] & TCAM_V4KEY3_DADDR) >>
7090 TCAM_V4KEY3_DADDR_SHIFT;
7091 fsp->m_u.tcp_ip4_spec.ip4src = (tp->key_mask[3] & TCAM_V4KEY3_SADDR) >>
7092 TCAM_V4KEY3_SADDR_SHIFT;
7093 fsp->m_u.tcp_ip4_spec.ip4dst = (tp->key_mask[3] & TCAM_V4KEY3_DADDR) >>
7094 TCAM_V4KEY3_DADDR_SHIFT;
7095
7096 fsp->h_u.tcp_ip4_spec.ip4src =
7097 cpu_to_be32(fsp->h_u.tcp_ip4_spec.ip4src);
7098 fsp->m_u.tcp_ip4_spec.ip4src =
7099 cpu_to_be32(fsp->m_u.tcp_ip4_spec.ip4src);
7100 fsp->h_u.tcp_ip4_spec.ip4dst =
7101 cpu_to_be32(fsp->h_u.tcp_ip4_spec.ip4dst);
7102 fsp->m_u.tcp_ip4_spec.ip4dst =
7103 cpu_to_be32(fsp->m_u.tcp_ip4_spec.ip4dst);
7104
7105 fsp->h_u.tcp_ip4_spec.tos = (tp->key[2] & TCAM_V4KEY2_TOS) >>
7106 TCAM_V4KEY2_TOS_SHIFT;
7107 fsp->m_u.tcp_ip4_spec.tos = (tp->key_mask[2] & TCAM_V4KEY2_TOS) >>
7108 TCAM_V4KEY2_TOS_SHIFT;
7109
7110 switch (fsp->flow_type) {
7111 case TCP_V4_FLOW:
7112 case UDP_V4_FLOW:
7113 case SCTP_V4_FLOW:
7114 fsp->h_u.tcp_ip4_spec.psrc =
7115 ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7116 TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16;
7117 fsp->h_u.tcp_ip4_spec.pdst =
7118 ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7119 TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff;
7120 fsp->m_u.tcp_ip4_spec.psrc =
7121 ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7122 TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16;
7123 fsp->m_u.tcp_ip4_spec.pdst =
7124 ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7125 TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff;
7126
7127 fsp->h_u.tcp_ip4_spec.psrc =
7128 cpu_to_be16(fsp->h_u.tcp_ip4_spec.psrc);
7129 fsp->h_u.tcp_ip4_spec.pdst =
7130 cpu_to_be16(fsp->h_u.tcp_ip4_spec.pdst);
7131 fsp->m_u.tcp_ip4_spec.psrc =
7132 cpu_to_be16(fsp->m_u.tcp_ip4_spec.psrc);
7133 fsp->m_u.tcp_ip4_spec.pdst =
7134 cpu_to_be16(fsp->m_u.tcp_ip4_spec.pdst);
7135 break;
7136 case AH_V4_FLOW:
7137 case ESP_V4_FLOW:
7138 fsp->h_u.ah_ip4_spec.spi =
7139 (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7140 TCAM_V4KEY2_PORT_SPI_SHIFT;
7141 fsp->m_u.ah_ip4_spec.spi =
7142 (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7143 TCAM_V4KEY2_PORT_SPI_SHIFT;
7144
7145 fsp->h_u.ah_ip4_spec.spi =
7146 cpu_to_be32(fsp->h_u.ah_ip4_spec.spi);
7147 fsp->m_u.ah_ip4_spec.spi =
7148 cpu_to_be32(fsp->m_u.ah_ip4_spec.spi);
7149 break;
7150 case IP_USER_FLOW:
7151 fsp->h_u.usr_ip4_spec.l4_4_bytes =
7152 (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7153 TCAM_V4KEY2_PORT_SPI_SHIFT;
7154 fsp->m_u.usr_ip4_spec.l4_4_bytes =
7155 (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7156 TCAM_V4KEY2_PORT_SPI_SHIFT;
7157
7158 fsp->h_u.usr_ip4_spec.l4_4_bytes =
7159 cpu_to_be32(fsp->h_u.usr_ip4_spec.l4_4_bytes);
7160 fsp->m_u.usr_ip4_spec.l4_4_bytes =
7161 cpu_to_be32(fsp->m_u.usr_ip4_spec.l4_4_bytes);
7162
7163 fsp->h_u.usr_ip4_spec.proto =
7164 (tp->key[2] & TCAM_V4KEY2_PROTO) >>
7165 TCAM_V4KEY2_PROTO_SHIFT;
7166 fsp->m_u.usr_ip4_spec.proto =
7167 (tp->key_mask[2] & TCAM_V4KEY2_PROTO) >>
7168 TCAM_V4KEY2_PROTO_SHIFT;
7169
7170 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
7171 break;
7172 default:
7173 break;
7174 }
7175}
7176
7177static int niu_get_ethtool_tcam_entry(struct niu *np,
7178 struct ethtool_rxnfc *nfc)
7179{
7180 struct niu_parent *parent = np->parent;
7181 struct niu_tcam_entry *tp;
7182 struct ethtool_rx_flow_spec *fsp = &nfc->fs;
7183 u16 idx;
7184 u64 class;
7185 int ret = 0;
7186
7187 idx = tcam_get_index(np, (u16)nfc->fs.location);
7188
7189 tp = &parent->tcam[idx];
7190 if (!tp->valid) {
f10a1f2e
JP		 7191 netdev_info(np->dev, "niu%d: entry [%d] invalid for idx[%d]\n",
7192 parent->index, (u16)nfc->fs.location, idx);
2d96cf8c
SB		 7193 return -EINVAL;
7194 }
7195
7196 /* fill the flow spec entry */
7197 class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >>
7198 TCAM_V4KEY0_CLASS_CODE_SHIFT;
7199 ret = niu_class_to_ethflow(class, &fsp->flow_type);
7200
7201 if (ret < 0) {
f10a1f2e
JP		 7202 netdev_info(np->dev, "niu%d: niu_class_to_ethflow failed\n",
7203 parent->index);
2d96cf8c
SB		 7204 ret = -EINVAL;
7205 goto out;
7206 }
7207
7208 if (fsp->flow_type == AH_V4_FLOW || fsp->flow_type == AH_V6_FLOW) {
7209 u32 proto = (tp->key[2] & TCAM_V4KEY2_PROTO) >>
7210 TCAM_V4KEY2_PROTO_SHIFT;
7211 if (proto == IPPROTO_ESP) {
7212 if (fsp->flow_type == AH_V4_FLOW)
7213 fsp->flow_type = ESP_V4_FLOW;
7214 else
7215 fsp->flow_type = ESP_V6_FLOW;
7216 }
7217 }
7218
7219 switch (fsp->flow_type) {
7220 case TCP_V4_FLOW:
7221 case UDP_V4_FLOW:
7222 case SCTP_V4_FLOW:
7223 case AH_V4_FLOW:
7224 case ESP_V4_FLOW:
7225 niu_get_ip4fs_from_tcam_key(tp, fsp);
7226 break;
7227 case TCP_V6_FLOW:
7228 case UDP_V6_FLOW:
7229 case SCTP_V6_FLOW:
7230 case AH_V6_FLOW:
7231 case ESP_V6_FLOW:
7232 /* Not yet implemented */
7233 ret = -EINVAL;
7234 break;
7235 case IP_USER_FLOW:
7236 niu_get_ip4fs_from_tcam_key(tp, fsp);
7237 break;
7238 default:
7239 ret = -EINVAL;
7240 break;
7241 }
7242
7243 if (ret < 0)
7244 goto out;
7245
7246 if (tp->assoc_data & TCAM_ASSOCDATA_DISC)
7247 fsp->ring_cookie = RX_CLS_FLOW_DISC;
7248 else
7249 fsp->ring_cookie = (tp->assoc_data & TCAM_ASSOCDATA_OFFSET) >>
7250 TCAM_ASSOCDATA_OFFSET_SHIFT;
7251
7252 /* put the tcam size here */
7253 nfc->data = tcam_get_size(np);
7254out:
7255 return ret;
7256}
7257
7258static int niu_get_ethtool_tcam_all(struct niu *np,
7259 struct ethtool_rxnfc *nfc,
7260 u32 *rule_locs)
7261{
7262 struct niu_parent *parent = np->parent;
7263 struct niu_tcam_entry *tp;
7264 int i, idx, cnt;
7265 u16 n_entries;
7266 unsigned long flags;
7267
7268
7269 /* put the tcam size here */
7270 nfc->data = tcam_get_size(np);
7271
7272 niu_lock_parent(np, flags);
7273 n_entries = nfc->rule_cnt;
7274 for (cnt = 0, i = 0; i < nfc->data; i++) {
7275 idx = tcam_get_index(np, i);
7276 tp = &parent->tcam[idx];
7277 if (!tp->valid)
7278 continue;
7279 rule_locs[cnt] = i;
7280 cnt++;
7281 }
7282 niu_unlock_parent(np, flags);
7283
7284 if (n_entries != cnt) {
7285 /* print warning, this should not happen */
f10a1f2e
JP		 7286 netdev_info(np->dev, "niu%d: In %s(): n_entries[%d] != cnt[%d]!!!\n",
7287 np->parent->index, __func__, n_entries, cnt);
2d96cf8c
SB		 7288 }
7289
7290 return 0;
7291}
7292
7293static int niu_get_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
7294 void *rule_locs)
b4653e99
SB		 7295{
7296 struct niu *np = netdev_priv(dev);
2d96cf8c
SB		 7297 int ret = 0;
7298
7299 switch (cmd->cmd) {
7300 case ETHTOOL_GRXFH:
7301 ret = niu_get_hash_opts(np, cmd);
7302 break;
7303 case ETHTOOL_GRXRINGS:
7304 cmd->data = np->num_rx_rings;
7305 break;
7306 case ETHTOOL_GRXCLSRLCNT:
7307 cmd->rule_cnt = tcam_get_valid_entry_cnt(np);
7308 break;
7309 case ETHTOOL_GRXCLSRULE:
7310 ret = niu_get_ethtool_tcam_entry(np, cmd);
7311 break;
7312 case ETHTOOL_GRXCLSRLALL:
7313 ret = niu_get_ethtool_tcam_all(np, cmd, (u32 *)rule_locs);
7314 break;
7315 default:
7316 ret = -EINVAL;
7317 break;
7318 }
7319
7320 return ret;
7321}
7322
7323static int niu_set_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc)
7324{
b4653e99
SB		 7325 u64 class;
7326 u64 flow_key = 0;
7327 unsigned long flags;
7328
2d96cf8c 7329 if (!niu_ethflow_to_class(nfc->flow_type, &class))
b4653e99
SB		 7330 return -EINVAL;
7331
7332 if (class < CLASS_CODE_USER_PROG1 ||
7333 class > CLASS_CODE_SCTP_IPV6)
7334 return -EINVAL;
7335
2d96cf8c 7336 if (nfc->data & RXH_DISCARD) {
b4653e99
SB		 7337 niu_lock_parent(np, flags);
7338 flow_key = np->parent->tcam_key[class -
7339 CLASS_CODE_USER_PROG1];
7340 flow_key |= TCAM_KEY_DISC;
7341 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7342 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] = flow_key;
7343 niu_unlock_parent(np, flags);
7344 return 0;
7345 } else {
7346 /* Discard was set before, but is not set now */
7347 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
7348 TCAM_KEY_DISC) {
7349 niu_lock_parent(np, flags);
7350 flow_key = np->parent->tcam_key[class -
7351 CLASS_CODE_USER_PROG1];
7352 flow_key &= ~TCAM_KEY_DISC;
7353 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1),
7354 flow_key);
7355 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] =
7356 flow_key;
7357 niu_unlock_parent(np, flags);
7358 }
7359 }
7360
2d96cf8c 7361 if (!niu_ethflow_to_flowkey(nfc->data, &flow_key))
b4653e99
SB		 7362 return -EINVAL;
7363
7364 niu_lock_parent(np, flags);
7365 nw64(FLOW_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7366 np->parent->flow_key[class - CLASS_CODE_USER_PROG1] = flow_key;
7367 niu_unlock_parent(np, flags);
7368
7369 return 0;
7370}
7371
2d96cf8c
SB		 7372static void niu_get_tcamkey_from_ip4fs(struct ethtool_rx_flow_spec *fsp,
7373 struct niu_tcam_entry *tp,
7374 int l2_rdc_tab, u64 class)
7375{
7376 u8 pid = 0;
7377 u32 sip, dip, sipm, dipm, spi, spim;
7378 u16 sport, dport, spm, dpm;
7379
7380 sip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4src);
7381 sipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4src);
7382 dip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4dst);
7383 dipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4dst);
7384
7385 tp->key[0] = class << TCAM_V4KEY0_CLASS_CODE_SHIFT;
7386 tp->key_mask[0] = TCAM_V4KEY0_CLASS_CODE;
7387 tp->key[1] = (u64)l2_rdc_tab << TCAM_V4KEY1_L2RDCNUM_SHIFT;
7388 tp->key_mask[1] = TCAM_V4KEY1_L2RDCNUM;
7389
7390 tp->key[3] = (u64)sip << TCAM_V4KEY3_SADDR_SHIFT;
7391 tp->key[3] |= dip;
7392
7393 tp->key_mask[3] = (u64)sipm << TCAM_V4KEY3_SADDR_SHIFT;
7394 tp->key_mask[3] |= dipm;
7395
7396 tp->key[2] |= ((u64)fsp->h_u.tcp_ip4_spec.tos <<
7397 TCAM_V4KEY2_TOS_SHIFT);
7398 tp->key_mask[2] |= ((u64)fsp->m_u.tcp_ip4_spec.tos <<
7399 TCAM_V4KEY2_TOS_SHIFT);
7400 switch (fsp->flow_type) {
7401 case TCP_V4_FLOW:
7402 case UDP_V4_FLOW:
7403 case SCTP_V4_FLOW:
7404 sport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.psrc);
7405 spm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.psrc);
7406 dport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.pdst);
7407 dpm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.pdst);
7408
7409 tp->key[2] |= (((u64)sport << 16) | dport);
7410 tp->key_mask[2] |= (((u64)spm << 16) | dpm);
7411 niu_ethflow_to_l3proto(fsp->flow_type, &pid);
7412 break;
7413 case AH_V4_FLOW:
7414 case ESP_V4_FLOW:
7415 spi = be32_to_cpu(fsp->h_u.ah_ip4_spec.spi);
7416 spim = be32_to_cpu(fsp->m_u.ah_ip4_spec.spi);
7417
7418 tp->key[2] |= spi;
7419 tp->key_mask[2] |= spim;
7420 niu_ethflow_to_l3proto(fsp->flow_type, &pid);
7421 break;
7422 case IP_USER_FLOW:
7423 spi = be32_to_cpu(fsp->h_u.usr_ip4_spec.l4_4_bytes);
7424 spim = be32_to_cpu(fsp->m_u.usr_ip4_spec.l4_4_bytes);
7425
7426 tp->key[2] |= spi;
7427 tp->key_mask[2] |= spim;
7428 pid = fsp->h_u.usr_ip4_spec.proto;
7429 break;
7430 default:
7431 break;
7432 }
7433
7434 tp->key[2] |= ((u64)pid << TCAM_V4KEY2_PROTO_SHIFT);
7435 if (pid) {
7436 tp->key_mask[2] |= TCAM_V4KEY2_PROTO;
7437 }
7438}
7439
7440static int niu_add_ethtool_tcam_entry(struct niu *np,
7441 struct ethtool_rxnfc *nfc)
7442{
7443 struct niu_parent *parent = np->parent;
7444 struct niu_tcam_entry *tp;
7445 struct ethtool_rx_flow_spec *fsp = &nfc->fs;
7446 struct niu_rdc_tables *rdc_table = &parent->rdc_group_cfg[np->port];
7447 int l2_rdc_table = rdc_table->first_table_num;
7448 u16 idx;
7449 u64 class;
7450 unsigned long flags;
7451 int err, ret;
7452
7453 ret = 0;
7454
7455 idx = nfc->fs.location;
7456 if (idx >= tcam_get_size(np))
7457 return -EINVAL;
7458
7459 if (fsp->flow_type == IP_USER_FLOW) {
7460 int i;
7461 int add_usr_cls = 0;
7462 int ipv6 = 0;
7463 struct ethtool_usrip4_spec *uspec = &fsp->h_u.usr_ip4_spec;
7464 struct ethtool_usrip4_spec *umask = &fsp->m_u.usr_ip4_spec;
7465
7466 niu_lock_parent(np, flags);
7467
7468 for (i = 0; i < NIU_L3_PROG_CLS; i++) {
7469 if (parent->l3_cls[i]) {
7470 if (uspec->proto == parent->l3_cls_pid[i]) {
7471 class = parent->l3_cls[i];
7472 parent->l3_cls_refcnt[i]++;
7473 add_usr_cls = 1;
7474 break;
7475 }
7476 } else {
7477 /* Program new user IP class */
7478 switch (i) {
7479 case 0:
7480 class = CLASS_CODE_USER_PROG1;
7481 break;
7482 case 1:
7483 class = CLASS_CODE_USER_PROG2;
7484 break;
7485 case 2:
7486 class = CLASS_CODE_USER_PROG3;
7487 break;
7488 case 3:
7489 class = CLASS_CODE_USER_PROG4;
7490 break;
7491 default:
7492 break;
7493 }
7494 if (uspec->ip_ver == ETH_RX_NFC_IP6)
7495 ipv6 = 1;
7496 ret = tcam_user_ip_class_set(np, class, ipv6,
7497 uspec->proto,
7498 uspec->tos,
7499 umask->tos);
7500 if (ret)
7501 goto out;
7502
7503 ret = tcam_user_ip_class_enable(np, class, 1);
7504 if (ret)
7505 goto out;
7506 parent->l3_cls[i] = class;
7507 parent->l3_cls_pid[i] = uspec->proto;
7508 parent->l3_cls_refcnt[i]++;
7509 add_usr_cls = 1;
7510 break;
7511 }
7512 }
7513 if (!add_usr_cls) {
f10a1f2e
JP		 7514 netdev_info(np->dev, "niu%d: %s(): Could not find/insert class for pid %d\n",
7515 parent->index, __func__, uspec->proto);
2d96cf8c
SB		 7516 ret = -EINVAL;
7517 goto out;
7518 }
7519 niu_unlock_parent(np, flags);
7520 } else {
7521 if (!niu_ethflow_to_class(fsp->flow_type, &class)) {
7522 return -EINVAL;
7523 }
7524 }
7525
7526 niu_lock_parent(np, flags);
7527
7528 idx = tcam_get_index(np, idx);
7529 tp = &parent->tcam[idx];
7530
7531 memset(tp, 0, sizeof(*tp));
7532
7533 /* fill in the tcam key and mask */
7534 switch (fsp->flow_type) {
7535 case TCP_V4_FLOW:
7536 case UDP_V4_FLOW:
7537 case SCTP_V4_FLOW:
7538 case AH_V4_FLOW:
7539 case ESP_V4_FLOW:
7540 niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table, class);
7541 break;
7542 case TCP_V6_FLOW:
7543 case UDP_V6_FLOW:
7544 case SCTP_V6_FLOW:
7545 case AH_V6_FLOW:
7546 case ESP_V6_FLOW:
7547 /* Not yet implemented */
f10a1f2e
JP		 7548 netdev_info(np->dev, "niu%d: In %s(): flow %d for IPv6 not implemented\n",
7549 parent->index, __func__, fsp->flow_type);
2d96cf8c
SB		 7550 ret = -EINVAL;
7551 goto out;
7552 case IP_USER_FLOW:
7553 if (fsp->h_u.usr_ip4_spec.ip_ver == ETH_RX_NFC_IP4) {
7554 niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table,
7555 class);
7556 } else {
7557 /* Not yet implemented */
f10a1f2e
JP		 7558 netdev_info(np->dev, "niu%d: In %s(): usr flow for IPv6 not implemented\n",
7559 parent->index, __func__);
2d96cf8c
SB		 7560 ret = -EINVAL;
7561 goto out;
7562 }
7563 break;
7564 default:
f10a1f2e
JP		 7565 netdev_info(np->dev, "niu%d: In %s(): Unknown flow type %d\n",
7566 parent->index, __func__, fsp->flow_type);
2d96cf8c
SB		 7567 ret = -EINVAL;
7568 goto out;
7569 }
7570
7571 /* fill in the assoc data */
7572 if (fsp->ring_cookie == RX_CLS_FLOW_DISC) {
7573 tp->assoc_data = TCAM_ASSOCDATA_DISC;
7574 } else {
7575 if (fsp->ring_cookie >= np->num_rx_rings) {
f10a1f2e
JP		 7576 netdev_info(np->dev, "niu%d: In %s(): Invalid RX ring %lld\n",
7577 parent->index, __func__,
7578 (long long)fsp->ring_cookie);
2d96cf8c
SB		 7579 ret = -EINVAL;
7580 goto out;
7581 }
7582 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
7583 (fsp->ring_cookie <<
7584 TCAM_ASSOCDATA_OFFSET_SHIFT));
7585 }
7586
7587 err = tcam_write(np, idx, tp->key, tp->key_mask);
7588 if (err) {
7589 ret = -EINVAL;
7590 goto out;
7591 }
7592 err = tcam_assoc_write(np, idx, tp->assoc_data);
7593 if (err) {
7594 ret = -EINVAL;
7595 goto out;
7596 }
7597
7598 /* validate the entry */
7599 tp->valid = 1;
7600 np->clas.tcam_valid_entries++;
7601out:
7602 niu_unlock_parent(np, flags);
7603
7604 return ret;
7605}
7606
7607static int niu_del_ethtool_tcam_entry(struct niu *np, u32 loc)
7608{
7609 struct niu_parent *parent = np->parent;
7610 struct niu_tcam_entry *tp;
7611 u16 idx;
7612 unsigned long flags;
7613 u64 class;
7614 int ret = 0;
7615
7616 if (loc >= tcam_get_size(np))
7617 return -EINVAL;
7618
7619 niu_lock_parent(np, flags);
7620
7621 idx = tcam_get_index(np, loc);
7622 tp = &parent->tcam[idx];
7623
7624 /* if the entry is of a user defined class, then update*/
7625 class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >>
7626 TCAM_V4KEY0_CLASS_CODE_SHIFT;
7627
7628 if (class >= CLASS_CODE_USER_PROG1 && class <= CLASS_CODE_USER_PROG4) {
7629 int i;
7630 for (i = 0; i < NIU_L3_PROG_CLS; i++) {
7631 if (parent->l3_cls[i] == class) {
7632 parent->l3_cls_refcnt[i]--;
7633 if (!parent->l3_cls_refcnt[i]) {
7634 /* disable class */
7635 ret = tcam_user_ip_class_enable(np,
7636 class,
7637 0);
7638 if (ret)
7639 goto out;
7640 parent->l3_cls[i] = 0;
7641 parent->l3_cls_pid[i] = 0;
7642 }
7643 break;
7644 }
7645 }
7646 if (i == NIU_L3_PROG_CLS) {
f10a1f2e
JP		 7647 netdev_info(np->dev, "niu%d: In %s(): Usr class 0x%llx not found\n",
7648 parent->index, __func__,
7649 (unsigned long long)class);
2d96cf8c
SB		 7650 ret = -EINVAL;
7651 goto out;
7652 }
7653 }
7654
7655 ret = tcam_flush(np, idx);
7656 if (ret)
7657 goto out;
7658
7659 /* invalidate the entry */
7660 tp->valid = 0;
7661 np->clas.tcam_valid_entries--;
7662out:
7663 niu_unlock_parent(np, flags);
7664
7665 return ret;
7666}
7667
7668static int niu_set_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
7669{
7670 struct niu *np = netdev_priv(dev);
7671 int ret = 0;
7672
7673 switch (cmd->cmd) {
7674 case ETHTOOL_SRXFH:
7675 ret = niu_set_hash_opts(np, cmd);
7676 break;
7677 case ETHTOOL_SRXCLSRLINS:
7678 ret = niu_add_ethtool_tcam_entry(np, cmd);
7679 break;
7680 case ETHTOOL_SRXCLSRLDEL:
7681 ret = niu_del_ethtool_tcam_entry(np, cmd->fs.location);
7682 break;
7683 default:
7684 ret = -EINVAL;
7685 break;
7686 }
7687
7688 return ret;
7689}
7690
a3138df9
DM		 7691static const struct {
7692 const char string[ETH_GSTRING_LEN];
7693} niu_xmac_stat_keys[] = {
7694 { "tx_frames" },
7695 { "tx_bytes" },
7696 { "tx_fifo_errors" },
7697 { "tx_overflow_errors" },
7698 { "tx_max_pkt_size_errors" },
7699 { "tx_underflow_errors" },
7700 { "rx_local_faults" },
7701 { "rx_remote_faults" },
7702 { "rx_link_faults" },
7703 { "rx_align_errors" },
7704 { "rx_frags" },
7705 { "rx_mcasts" },
7706 { "rx_bcasts" },
7707 { "rx_hist_cnt1" },
7708 { "rx_hist_cnt2" },
7709 { "rx_hist_cnt3" },
7710 { "rx_hist_cnt4" },
7711 { "rx_hist_cnt5" },
7712 { "rx_hist_cnt6" },
7713 { "rx_hist_cnt7" },
7714 { "rx_octets" },
7715 { "rx_code_violations" },
7716 { "rx_len_errors" },
7717 { "rx_crc_errors" },
7718 { "rx_underflows" },
7719 { "rx_overflows" },
7720 { "pause_off_state" },
7721 { "pause_on_state" },
7722 { "pause_received" },
7723};
7724
7725#define NUM_XMAC_STAT_KEYS ARRAY_SIZE(niu_xmac_stat_keys)
7726
7727static const struct {
7728 const char string[ETH_GSTRING_LEN];
7729} niu_bmac_stat_keys[] = {
7730 { "tx_underflow_errors" },
7731 { "tx_max_pkt_size_errors" },
7732 { "tx_bytes" },
7733 { "tx_frames" },
7734 { "rx_overflows" },
7735 { "rx_frames" },
7736 { "rx_align_errors" },
7737 { "rx_crc_errors" },
7738 { "rx_len_errors" },
7739 { "pause_off_state" },
7740 { "pause_on_state" },
7741 { "pause_received" },
7742};
7743
7744#define NUM_BMAC_STAT_KEYS ARRAY_SIZE(niu_bmac_stat_keys)
7745
7746static const struct {
7747 const char string[ETH_GSTRING_LEN];
7748} niu_rxchan_stat_keys[] = {
7749 { "rx_channel" },
7750 { "rx_packets" },
7751 { "rx_bytes" },
7752 { "rx_dropped" },
7753 { "rx_errors" },
7754};
7755
7756#define NUM_RXCHAN_STAT_KEYS ARRAY_SIZE(niu_rxchan_stat_keys)
7757
7758static const struct {
7759 const char string[ETH_GSTRING_LEN];
7760} niu_txchan_stat_keys[] = {
7761 { "tx_channel" },
7762 { "tx_packets" },
7763 { "tx_bytes" },
7764 { "tx_errors" },
7765};
7766
7767#define NUM_TXCHAN_STAT_KEYS ARRAY_SIZE(niu_txchan_stat_keys)
7768
7769static void niu_get_strings(struct net_device *dev, u32 stringset, u8 *data)
7770{
7771 struct niu *np = netdev_priv(dev);
7772 int i;
7773
7774 if (stringset != ETH_SS_STATS)
7775 return;
7776
7777 if (np->flags & NIU_FLAGS_XMAC) {
7778 memcpy(data, niu_xmac_stat_keys,
7779 sizeof(niu_xmac_stat_keys));
7780 data += sizeof(niu_xmac_stat_keys);
7781 } else {
7782 memcpy(data, niu_bmac_stat_keys,
7783 sizeof(niu_bmac_stat_keys));
7784 data += sizeof(niu_bmac_stat_keys);
7785 }
7786 for (i = 0; i < np->num_rx_rings; i++) {
7787 memcpy(data, niu_rxchan_stat_keys,
7788 sizeof(niu_rxchan_stat_keys));
7789 data += sizeof(niu_rxchan_stat_keys);
7790 }
7791 for (i = 0; i < np->num_tx_rings; i++) {
7792 memcpy(data, niu_txchan_stat_keys,
7793 sizeof(niu_txchan_stat_keys));
7794 data += sizeof(niu_txchan_stat_keys);
7795 }
7796}
7797
15f0a394 7798static int niu_get_sset_count(struct net_device *dev, int stringset)
a3138df9
DM		 7799{
7800 struct niu *np = netdev_priv(dev);
7801
15f0a394
BH		 7802 if (stringset != ETH_SS_STATS)
7803 return -EINVAL;
7804
a3138df9
DM		 7805 return ((np->flags & NIU_FLAGS_XMAC ?
7806 NUM_XMAC_STAT_KEYS :
7807 NUM_BMAC_STAT_KEYS) +
7808 (np->num_rx_rings * NUM_RXCHAN_STAT_KEYS) +
7809 (np->num_tx_rings * NUM_TXCHAN_STAT_KEYS));
7810}
7811
7812static void niu_get_ethtool_stats(struct net_device *dev,
7813 struct ethtool_stats *stats, u64 *data)
7814{
7815 struct niu *np = netdev_priv(dev);
7816 int i;
7817
7818 niu_sync_mac_stats(np);
7819 if (np->flags & NIU_FLAGS_XMAC) {
7820 memcpy(data, &np->mac_stats.xmac,
7821 sizeof(struct niu_xmac_stats));
7822 data += (sizeof(struct niu_xmac_stats) / sizeof(u64));
7823 } else {
7824 memcpy(data, &np->mac_stats.bmac,
7825 sizeof(struct niu_bmac_stats));
7826 data += (sizeof(struct niu_bmac_stats) / sizeof(u64));
7827 }
7828 for (i = 0; i < np->num_rx_rings; i++) {
7829 struct rx_ring_info *rp = &np->rx_rings[i];
7830
b8a606b8
JDB		 7831 niu_sync_rx_discard_stats(np, rp, 0);
7832
a3138df9
DM		 7833 data[0] = rp->rx_channel;
7834 data[1] = rp->rx_packets;
7835 data[2] = rp->rx_bytes;
7836 data[3] = rp->rx_dropped;
7837 data[4] = rp->rx_errors;
7838 data += 5;
7839 }
7840 for (i = 0; i < np->num_tx_rings; i++) {
7841 struct tx_ring_info *rp = &np->tx_rings[i];
7842
7843 data[0] = rp->tx_channel;
7844 data[1] = rp->tx_packets;
7845 data[2] = rp->tx_bytes;
7846 data[3] = rp->tx_errors;
7847 data += 4;
7848 }
7849}
7850
7851static u64 niu_led_state_save(struct niu *np)
7852{
7853 if (np->flags & NIU_FLAGS_XMAC)
7854 return nr64_mac(XMAC_CONFIG);
7855 else
7856 return nr64_mac(BMAC_XIF_CONFIG);
7857}
7858
7859static void niu_led_state_restore(struct niu *np, u64 val)
7860{
7861 if (np->flags & NIU_FLAGS_XMAC)
7862 nw64_mac(XMAC_CONFIG, val);
7863 else
7864 nw64_mac(BMAC_XIF_CONFIG, val);
7865}
7866
7867static void niu_force_led(struct niu *np, int on)
7868{
7869 u64 val, reg, bit;
7870
7871 if (np->flags & NIU_FLAGS_XMAC) {
7872 reg = XMAC_CONFIG;
7873 bit = XMAC_CONFIG_FORCE_LED_ON;
7874 } else {
7875 reg = BMAC_XIF_CONFIG;
7876 bit = BMAC_XIF_CONFIG_LINK_LED;
7877 }
7878
7879 val = nr64_mac(reg);
7880 if (on)
7881 val |= bit;
7882 else
7883 val &= ~bit;
7884 nw64_mac(reg, val);
7885}
7886
7887static int niu_phys_id(struct net_device *dev, u32 data)
7888{
7889 struct niu *np = netdev_priv(dev);
7890 u64 orig_led_state;
7891 int i;
7892
7893 if (!netif_running(dev))
7894 return -EAGAIN;
7895
7896 if (data == 0)
7897 data = 2;
7898
7899 orig_led_state = niu_led_state_save(np);
7900 for (i = 0; i < (data * 2); i++) {
7901 int on = ((i % 2) == 0);
7902
7903 niu_force_led(np, on);
7904
7905 if (msleep_interruptible(500))
7906 break;
7907 }
7908 niu_led_state_restore(np, orig_led_state);
7909
7910 return 0;
7911}
7912
7913static const struct ethtool_ops niu_ethtool_ops = {
7914 .get_drvinfo = niu_get_drvinfo,
7915 .get_link = ethtool_op_get_link,
7916 .get_msglevel = niu_get_msglevel,
7917 .set_msglevel = niu_set_msglevel,
38bb045d 7918 .nway_reset = niu_nway_reset,
a3138df9
DM		 7919 .get_eeprom_len = niu_get_eeprom_len,
7920 .get_eeprom = niu_get_eeprom,
7921 .get_settings = niu_get_settings,
7922 .set_settings = niu_set_settings,
7923 .get_strings = niu_get_strings,
15f0a394 7924 .get_sset_count = niu_get_sset_count,
a3138df9
DM		 7925 .get_ethtool_stats = niu_get_ethtool_stats,
7926 .phys_id = niu_phys_id,
2d96cf8c
SB		 7927 .get_rxnfc = niu_get_nfc,
7928 .set_rxnfc = niu_set_nfc,
a3138df9
DM		 7929};
7930
7931static int niu_ldg_assign_ldn(struct niu *np, struct niu_parent *parent,
7932 int ldg, int ldn)
7933{
7934 if (ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX)
7935 return -EINVAL;
7936 if (ldn < 0 || ldn > LDN_MAX)
7937 return -EINVAL;
7938
7939 parent->ldg_map[ldn] = ldg;
7940
7941 if (np->parent->plat_type == PLAT_TYPE_NIU) {
7942 /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by
7943 * the firmware, and we're not supposed to change them.
7944 * Validate the mapping, because if it's wrong we probably
7945 * won't get any interrupts and that's painful to debug.
7946 */
7947 if (nr64(LDG_NUM(ldn)) != ldg) {
f10a1f2e 7948 dev_err(np->device, "Port %u, mis-matched LDG assignment for ldn %d, should be %d is %llu\n",
a3138df9
DM		 7949 np->port, ldn, ldg,
7950 (unsigned long long) nr64(LDG_NUM(ldn)));
7951 return -EINVAL;
7952 }
7953 } else
7954 nw64(LDG_NUM(ldn), ldg);
7955
7956 return 0;
7957}
7958
7959static int niu_set_ldg_timer_res(struct niu *np, int res)
7960{
7961 if (res < 0 || res > LDG_TIMER_RES_VAL)
7962 return -EINVAL;
7963
7964
7965 nw64(LDG_TIMER_RES, res);
7966
7967 return 0;
7968}
7969
7970static int niu_set_ldg_sid(struct niu *np, int ldg, int func, int vector)
7971{
7972 if ((ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) ||
7973 (func < 0 || func > 3) ||
7974 (vector < 0 || vector > 0x1f))
7975 return -EINVAL;
7976
7977 nw64(SID(ldg), (func << SID_FUNC_SHIFT) | vector);
7978
7979 return 0;
7980}
7981
7982static int __devinit niu_pci_eeprom_read(struct niu *np, u32 addr)
7983{
7984 u64 frame, frame_base = (ESPC_PIO_STAT_READ_START |
7985 (addr << ESPC_PIO_STAT_ADDR_SHIFT));
7986 int limit;
7987
7988 if (addr > (ESPC_PIO_STAT_ADDR >> ESPC_PIO_STAT_ADDR_SHIFT))
7989 return -EINVAL;
7990
7991 frame = frame_base;
7992 nw64(ESPC_PIO_STAT, frame);
7993 limit = 64;
7994 do {
7995 udelay(5);
7996 frame = nr64(ESPC_PIO_STAT);
7997 if (frame & ESPC_PIO_STAT_READ_END)
7998 break;
7999 } while (limit--);
8000 if (!(frame & ESPC_PIO_STAT_READ_END)) {
f10a1f2e 8001 dev_err(np->device, "EEPROM read timeout frame[%llx]\n",
a3138df9
DM		 8002 (unsigned long long) frame);
8003 return -ENODEV;
8004 }
8005
8006 frame = frame_base;
8007 nw64(ESPC_PIO_STAT, frame);
8008 limit = 64;
8009 do {
8010 udelay(5);
8011 frame = nr64(ESPC_PIO_STAT);
8012 if (frame & ESPC_PIO_STAT_READ_END)
8013 break;
8014 } while (limit--);
8015 if (!(frame & ESPC_PIO_STAT_READ_END)) {
f10a1f2e 8016 dev_err(np->device, "EEPROM read timeout frame[%llx]\n",
a3138df9
DM		 8017 (unsigned long long) frame);
8018 return -ENODEV;
8019 }
8020
8021 frame = nr64(ESPC_PIO_STAT);
8022 return (frame & ESPC_PIO_STAT_DATA) >> ESPC_PIO_STAT_DATA_SHIFT;
8023}
8024
8025static int __devinit niu_pci_eeprom_read16(struct niu *np, u32 off)
8026{
8027 int err = niu_pci_eeprom_read(np, off);
8028 u16 val;
8029
8030 if (err < 0)
8031 return err;
8032 val = (err << 8);
8033 err = niu_pci_eeprom_read(np, off + 1);
8034 if (err < 0)
8035 return err;
8036 val |= (err & 0xff);
8037
8038 return val;
8039}
8040
8041static int __devinit niu_pci_eeprom_read16_swp(struct niu *np, u32 off)
8042{
8043 int err = niu_pci_eeprom_read(np, off);
8044 u16 val;
8045
8046 if (err < 0)
8047 return err;
8048
8049 val = (err & 0xff);
8050 err = niu_pci_eeprom_read(np, off + 1);
8051 if (err < 0)
8052 return err;
8053
8054 val |= (err & 0xff) << 8;
8055
8056 return val;
8057}
8058
8059static int __devinit niu_pci_vpd_get_propname(struct niu *np,
8060 u32 off,
8061 char *namebuf,
8062 int namebuf_len)
8063{
8064 int i;
8065
8066 for (i = 0; i < namebuf_len; i++) {
8067 int err = niu_pci_eeprom_read(np, off + i);
8068 if (err < 0)
8069 return err;
8070 *namebuf++ = err;
8071 if (!err)
8072 break;
8073 }
8074 if (i >= namebuf_len)
8075 return -EINVAL;
8076
8077 return i + 1;
8078}
8079
8080static void __devinit niu_vpd_parse_version(struct niu *np)
8081{
8082 struct niu_vpd *vpd = &np->vpd;
8083 int len = strlen(vpd->version) + 1;
8084 const char *s = vpd->version;
8085 int i;
8086
8087 for (i = 0; i < len - 5; i++) {
9ea2bdab 8088 if (!strncmp(s + i, "FCode ", 6))
a3138df9
DM		 8089 break;
8090 }
8091 if (i >= len - 5)
8092 return;
8093
8094 s += i + 5;
8095 sscanf(s, "%d.%d", &vpd->fcode_major, &vpd->fcode_minor);
8096
f10a1f2e
JP		 8097 netif_printk(np, probe, KERN_DEBUG, np->dev,
8098 "VPD_SCAN: FCODE major(%d) minor(%d)\n",
8099 vpd->fcode_major, vpd->fcode_minor);
a3138df9
DM		 8100 if (vpd->fcode_major > NIU_VPD_MIN_MAJOR ||
8101 (vpd->fcode_major == NIU_VPD_MIN_MAJOR &&
8102 vpd->fcode_minor >= NIU_VPD_MIN_MINOR))
8103 np->flags |= NIU_FLAGS_VPD_VALID;
8104}
8105
8106/* ESPC_PIO_EN_ENABLE must be set */
8107static int __devinit niu_pci_vpd_scan_props(struct niu *np,
8108 u32 start, u32 end)
8109{
8110 unsigned int found_mask = 0;
8111#define FOUND_MASK_MODEL 0x00000001
8112#define FOUND_MASK_BMODEL 0x00000002
8113#define FOUND_MASK_VERS 0x00000004
8114#define FOUND_MASK_MAC 0x00000008
8115#define FOUND_MASK_NMAC 0x00000010
8116#define FOUND_MASK_PHY 0x00000020
8117#define FOUND_MASK_ALL 0x0000003f
8118
f10a1f2e
JP		 8119 netif_printk(np, probe, KERN_DEBUG, np->dev,
8120 "VPD_SCAN: start[%x] end[%x]\n", start, end);
a3138df9
DM		 8121 while (start < end) {
8122 int len, err, instance, type, prop_len;
8123 char namebuf[64];
8124 u8 *prop_buf;
8125 int max_len;
8126
8127 if (found_mask == FOUND_MASK_ALL) {
8128 niu_vpd_parse_version(np);
8129 return 1;
8130 }
8131
8132 err = niu_pci_eeprom_read(np, start + 2);
8133 if (err < 0)
8134 return err;
8135 len = err;
8136 start += 3;
8137
8138 instance = niu_pci_eeprom_read(np, start);
8139 type = niu_pci_eeprom_read(np, start + 3);
8140 prop_len = niu_pci_eeprom_read(np, start + 4);
8141 err = niu_pci_vpd_get_propname(np, start + 5, namebuf, 64);
8142 if (err < 0)
8143 return err;
8144
8145 prop_buf = NULL;
8146 max_len = 0;
8147 if (!strcmp(namebuf, "model")) {
8148 prop_buf = np->vpd.model;
8149 max_len = NIU_VPD_MODEL_MAX;
8150 found_mask |= FOUND_MASK_MODEL;
8151 } else if (!strcmp(namebuf, "board-model")) {
8152 prop_buf = np->vpd.board_model;
8153 max_len = NIU_VPD_BD_MODEL_MAX;
8154 found_mask |= FOUND_MASK_BMODEL;
8155 } else if (!strcmp(namebuf, "version")) {
8156 prop_buf = np->vpd.version;
8157 max_len = NIU_VPD_VERSION_MAX;
8158 found_mask |= FOUND_MASK_VERS;
8159 } else if (!strcmp(namebuf, "local-mac-address")) {
8160 prop_buf = np->vpd.local_mac;
8161 max_len = ETH_ALEN;
8162 found_mask |= FOUND_MASK_MAC;
8163 } else if (!strcmp(namebuf, "num-mac-addresses")) {
8164 prop_buf = &np->vpd.mac_num;
8165 max_len = 1;
8166 found_mask |= FOUND_MASK_NMAC;
8167 } else if (!strcmp(namebuf, "phy-type")) {
8168 prop_buf = np->vpd.phy_type;
8169 max_len = NIU_VPD_PHY_TYPE_MAX;
8170 found_mask |= FOUND_MASK_PHY;
8171 }
8172
8173 if (max_len && prop_len > max_len) {
f10a1f2e 8174 dev_err(np->device, "Property '%s' length (%d) is too long\n", namebuf, prop_len);
a3138df9
DM		 8175 return -EINVAL;
8176 }
8177
8178 if (prop_buf) {
8179 u32 off = start + 5 + err;
8180 int i;
8181
f10a1f2e
JP		 8182 netif_printk(np, probe, KERN_DEBUG, np->dev,
8183 "VPD_SCAN: Reading in property [%s] len[%d]\n",
8184 namebuf, prop_len);
a3138df9
DM		 8185 for (i = 0; i < prop_len; i++)
8186 *prop_buf++ = niu_pci_eeprom_read(np, off + i);
8187 }
8188
8189 start += len;
8190 }
8191
8192 return 0;
8193}
8194
8195/* ESPC_PIO_EN_ENABLE must be set */
8196static void __devinit niu_pci_vpd_fetch(struct niu *np, u32 start)
8197{
8198 u32 offset;
8199 int err;
8200
8201 err = niu_pci_eeprom_read16_swp(np, start + 1);
8202 if (err < 0)
8203 return;
8204
8205 offset = err + 3;
8206
8207 while (start + offset < ESPC_EEPROM_SIZE) {
8208 u32 here = start + offset;
8209 u32 end;
8210
8211 err = niu_pci_eeprom_read(np, here);
8212 if (err != 0x90)
8213 return;
8214
8215 err = niu_pci_eeprom_read16_swp(np, here + 1);
8216 if (err < 0)
8217 return;
8218
8219 here = start + offset + 3;
8220 end = start + offset + err;
8221
8222 offset += err;
8223
8224 err = niu_pci_vpd_scan_props(np, here, end);
8225 if (err < 0 || err == 1)
8226 return;
8227 }
8228}
8229
8230/* ESPC_PIO_EN_ENABLE must be set */
8231static u32 __devinit niu_pci_vpd_offset(struct niu *np)
8232{
8233 u32 start = 0, end = ESPC_EEPROM_SIZE, ret;
8234 int err;
8235
8236 while (start < end) {
8237 ret = start;
8238
8239 /* ROM header signature? */
8240 err = niu_pci_eeprom_read16(np, start + 0);
8241 if (err != 0x55aa)
8242 return 0;
8243
8244 /* Apply offset to PCI data structure. */
8245 err = niu_pci_eeprom_read16(np, start + 23);
8246 if (err < 0)
8247 return 0;
8248 start += err;
8249
8250 /* Check for "PCIR" signature. */
8251 err = niu_pci_eeprom_read16(np, start + 0);
8252 if (err != 0x5043)
8253 return 0;
8254 err = niu_pci_eeprom_read16(np, start + 2);
8255 if (err != 0x4952)
8256 return 0;
8257
8258 /* Check for OBP image type. */
8259 err = niu_pci_eeprom_read(np, start + 20);
8260 if (err < 0)
8261 return 0;
8262 if (err != 0x01) {
8263 err = niu_pci_eeprom_read(np, ret + 2);
8264 if (err < 0)
8265 return 0;
8266
8267 start = ret + (err * 512);
8268 continue;
8269 }
8270
8271 err = niu_pci_eeprom_read16_swp(np, start + 8);
8272 if (err < 0)
8273 return err;
8274 ret += err;
8275
8276 err = niu_pci_eeprom_read(np, ret + 0);
8277 if (err != 0x82)
8278 return 0;
8279
8280 return ret;
8281 }
8282
8283 return 0;
8284}
8285
8286static int __devinit niu_phy_type_prop_decode(struct niu *np,
8287 const char *phy_prop)
8288{
8289 if (!strcmp(phy_prop, "mif")) {
8290 /* 1G copper, MII */
8291 np->flags &= ~(NIU_FLAGS_FIBER |
8292 NIU_FLAGS_10G);
8293 np->mac_xcvr = MAC_XCVR_MII;
8294 } else if (!strcmp(phy_prop, "xgf")) {
8295 /* 10G fiber, XPCS */
8296 np->flags |= (NIU_FLAGS_10G |
8297 NIU_FLAGS_FIBER);
8298 np->mac_xcvr = MAC_XCVR_XPCS;
8299 } else if (!strcmp(phy_prop, "pcs")) {
8300 /* 1G fiber, PCS */
8301 np->flags &= ~NIU_FLAGS_10G;
8302 np->flags |= NIU_FLAGS_FIBER;
8303 np->mac_xcvr = MAC_XCVR_PCS;
8304 } else if (!strcmp(phy_prop, "xgc")) {
8305 /* 10G copper, XPCS */
8306 np->flags |= NIU_FLAGS_10G;
8307 np->flags &= ~NIU_FLAGS_FIBER;
8308 np->mac_xcvr = MAC_XCVR_XPCS;
e3e081e1
SB		 8309 } else if (!strcmp(phy_prop, "xgsd") || !strcmp(phy_prop, "gsd")) {
8310 /* 10G Serdes or 1G Serdes, default to 10G */
8311 np->flags |= NIU_FLAGS_10G;
8312 np->flags &= ~NIU_FLAGS_FIBER;
8313 np->flags |= NIU_FLAGS_XCVR_SERDES;
8314 np->mac_xcvr = MAC_XCVR_XPCS;
a3138df9
DM		 8315 } else {
8316 return -EINVAL;
8317 }
8318 return 0;
8319}
8320
7f7c4072
MW		 8321static int niu_pci_vpd_get_nports(struct niu *np)
8322{
8323 int ports = 0;
8324
f9af8574
MW		 8325 if ((!strcmp(np->vpd.model, NIU_QGC_LP_MDL_STR)) ||
8326 (!strcmp(np->vpd.model, NIU_QGC_PEM_MDL_STR)) ||
8327 (!strcmp(np->vpd.model, NIU_MARAMBA_MDL_STR)) ||
8328 (!strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) ||
8329 (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR))) {
7f7c4072 8330 ports = 4;
f9af8574
MW		 8331 } else if ((!strcmp(np->vpd.model, NIU_2XGF_LP_MDL_STR)) ||
8332 (!strcmp(np->vpd.model, NIU_2XGF_PEM_MDL_STR)) ||
8333 (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) ||
8334 (!strcmp(np->vpd.model, NIU_2XGF_MRVL_MDL_STR))) {
7f7c4072
MW		 8335 ports = 2;
8336 }
8337
8338 return ports;
8339}
8340
a3138df9
DM		 8341static void __devinit niu_pci_vpd_validate(struct niu *np)
8342{
8343 struct net_device *dev = np->dev;
8344 struct niu_vpd *vpd = &np->vpd;
8345 u8 val8;
8346
8347 if (!is_valid_ether_addr(&vpd->local_mac[0])) {
f10a1f2e 8348 dev_err(np->device, "VPD MAC invalid, falling back to SPROM\n");
a3138df9
DM		 8349
8350 np->flags &= ~NIU_FLAGS_VPD_VALID;
8351 return;
8352 }
8353
f9af8574
MW		 8354 if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
8355 !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
5fbd7e24
MW		 8356 np->flags |= NIU_FLAGS_10G;
8357 np->flags &= ~NIU_FLAGS_FIBER;
8358 np->flags |= NIU_FLAGS_XCVR_SERDES;
8359 np->mac_xcvr = MAC_XCVR_PCS;
8360 if (np->port > 1) {
8361 np->flags |= NIU_FLAGS_FIBER;
8362 np->flags &= ~NIU_FLAGS_10G;
8363 }
8364 if (np->flags & NIU_FLAGS_10G)
f10a1f2e 8365 np->mac_xcvr = MAC_XCVR_XPCS;
f9af8574 8366 } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
a5d6ab56
MW		 8367 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
8368 NIU_FLAGS_HOTPLUG_PHY);
5fbd7e24 8369 } else if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
f10a1f2e 8370 dev_err(np->device, "Illegal phy string [%s]\n",
a3138df9 8371 np->vpd.phy_type);
f10a1f2e 8372 dev_err(np->device, "Falling back to SPROM\n");
a3138df9
DM		 8373 np->flags &= ~NIU_FLAGS_VPD_VALID;
8374 return;
8375 }
8376
8377 memcpy(dev->perm_addr, vpd->local_mac, ETH_ALEN);
8378
8379 val8 = dev->perm_addr[5];
8380 dev->perm_addr[5] += np->port;
8381 if (dev->perm_addr[5] < val8)
8382 dev->perm_addr[4]++;
8383
8384 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
8385}
8386
8387static int __devinit niu_pci_probe_sprom(struct niu *np)
8388{
8389 struct net_device *dev = np->dev;
8390 int len, i;
8391 u64 val, sum;
8392 u8 val8;
8393
8394 val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ);
8395 val >>= ESPC_VER_IMGSZ_IMGSZ_SHIFT;
8396 len = val / 4;
8397
8398 np->eeprom_len = len;
8399
f10a1f2e
JP		 8400 netif_printk(np, probe, KERN_DEBUG, np->dev,
8401 "SPROM: Image size %llu\n", (unsigned long long)val);
a3138df9
DM		 8402
8403 sum = 0;
8404 for (i = 0; i < len; i++) {
8405 val = nr64(ESPC_NCR(i));
8406 sum += (val >> 0) & 0xff;
8407 sum += (val >> 8) & 0xff;
8408 sum += (val >> 16) & 0xff;
8409 sum += (val >> 24) & 0xff;
8410 }
f10a1f2e
JP		 8411 netif_printk(np, probe, KERN_DEBUG, np->dev,
8412 "SPROM: Checksum %x\n", (int)(sum & 0xff));
a3138df9 8413 if ((sum & 0xff) != 0xab) {
f10a1f2e 8414 dev_err(np->device, "Bad SPROM checksum (%x, should be 0xab)\n", (int)(sum & 0xff));
a3138df9
DM		 8415 return -EINVAL;
8416 }
8417
8418 val = nr64(ESPC_PHY_TYPE);
8419 switch (np->port) {
8420 case 0:
a9d41192 8421 val8 = (val & ESPC_PHY_TYPE_PORT0) >>
a3138df9
DM		 8422 ESPC_PHY_TYPE_PORT0_SHIFT;
8423 break;
8424 case 1:
a9d41192 8425 val8 = (val & ESPC_PHY_TYPE_PORT1) >>
a3138df9
DM		 8426 ESPC_PHY_TYPE_PORT1_SHIFT;
8427 break;
8428 case 2:
a9d41192 8429 val8 = (val & ESPC_PHY_TYPE_PORT2) >>
a3138df9
DM		 8430 ESPC_PHY_TYPE_PORT2_SHIFT;
8431 break;
8432 case 3:
a9d41192 8433 val8 = (val & ESPC_PHY_TYPE_PORT3) >>
a3138df9
DM		 8434 ESPC_PHY_TYPE_PORT3_SHIFT;
8435 break;
8436 default:
f10a1f2e 8437 dev_err(np->device, "Bogus port number %u\n",
a3138df9
DM		 8438 np->port);
8439 return -EINVAL;
8440 }
f10a1f2e
JP		 8441 netif_printk(np, probe, KERN_DEBUG, np->dev,
8442 "SPROM: PHY type %x\n", val8);
a3138df9 8443
a9d41192 8444 switch (val8) {
a3138df9
DM		 8445 case ESPC_PHY_TYPE_1G_COPPER:
8446 /* 1G copper, MII */
8447 np->flags &= ~(NIU_FLAGS_FIBER |
8448 NIU_FLAGS_10G);
8449 np->mac_xcvr = MAC_XCVR_MII;
8450 break;
8451
8452 case ESPC_PHY_TYPE_1G_FIBER:
8453 /* 1G fiber, PCS */
8454 np->flags &= ~NIU_FLAGS_10G;
8455 np->flags |= NIU_FLAGS_FIBER;
8456 np->mac_xcvr = MAC_XCVR_PCS;
8457 break;
8458
8459 case ESPC_PHY_TYPE_10G_COPPER:
8460 /* 10G copper, XPCS */
8461 np->flags |= NIU_FLAGS_10G;
8462 np->flags &= ~NIU_FLAGS_FIBER;
8463 np->mac_xcvr = MAC_XCVR_XPCS;
8464 break;
8465
8466 case ESPC_PHY_TYPE_10G_FIBER:
8467 /* 10G fiber, XPCS */
8468 np->flags |= (NIU_FLAGS_10G |
8469 NIU_FLAGS_FIBER);
8470 np->mac_xcvr = MAC_XCVR_XPCS;
8471 break;
8472
8473 default:
f10a1f2e 8474 dev_err(np->device, "Bogus SPROM phy type %u\n", val8);
a3138df9
DM		 8475 return -EINVAL;
8476 }
8477
8478 val = nr64(ESPC_MAC_ADDR0);
f10a1f2e
JP		 8479 netif_printk(np, probe, KERN_DEBUG, np->dev,
8480 "SPROM: MAC_ADDR0[%08llx]\n", (unsigned long long)val);
a3138df9
DM		 8481 dev->perm_addr[0] = (val >> 0) & 0xff;
8482 dev->perm_addr[1] = (val >> 8) & 0xff;
8483 dev->perm_addr[2] = (val >> 16) & 0xff;
8484 dev->perm_addr[3] = (val >> 24) & 0xff;
8485
8486 val = nr64(ESPC_MAC_ADDR1);
f10a1f2e
JP		 8487 netif_printk(np, probe, KERN_DEBUG, np->dev,
8488 "SPROM: MAC_ADDR1[%08llx]\n", (unsigned long long)val);
a3138df9
DM		 8489 dev->perm_addr[4] = (val >> 0) & 0xff;
8490 dev->perm_addr[5] = (val >> 8) & 0xff;
8491
8492 if (!is_valid_ether_addr(&dev->perm_addr[0])) {
f10a1f2e
JP		 8493 dev_err(np->device, "SPROM MAC address invalid [ %pM ]\n",
8494 dev->perm_addr);
a3138df9
DM		 8495 return -EINVAL;
8496 }
8497
8498 val8 = dev->perm_addr[5];
8499 dev->perm_addr[5] += np->port;
8500 if (dev->perm_addr[5] < val8)
8501 dev->perm_addr[4]++;
8502
8503 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
8504
8505 val = nr64(ESPC_MOD_STR_LEN);
f10a1f2e
JP		 8506 netif_printk(np, probe, KERN_DEBUG, np->dev,
8507 "SPROM: MOD_STR_LEN[%llu]\n", (unsigned long long)val);
e6a5fdf5 8508 if (val >= 8 * 4)
a3138df9
DM		 8509 return -EINVAL;
8510
8511 for (i = 0; i < val; i += 4) {
8512 u64 tmp = nr64(ESPC_NCR(5 + (i / 4)));
8513
8514 np->vpd.model[i + 3] = (tmp >> 0) & 0xff;
8515 np->vpd.model[i + 2] = (tmp >> 8) & 0xff;
8516 np->vpd.model[i + 1] = (tmp >> 16) & 0xff;
8517 np->vpd.model[i + 0] = (tmp >> 24) & 0xff;
8518 }
8519 np->vpd.model[val] = '\0';
8520
8521 val = nr64(ESPC_BD_MOD_STR_LEN);
f10a1f2e
JP		 8522 netif_printk(np, probe, KERN_DEBUG, np->dev,
8523 "SPROM: BD_MOD_STR_LEN[%llu]\n", (unsigned long long)val);
e6a5fdf5 8524 if (val >= 4 * 4)
a3138df9
DM		 8525 return -EINVAL;
8526
8527 for (i = 0; i < val; i += 4) {
8528 u64 tmp = nr64(ESPC_NCR(14 + (i / 4)));
8529
8530 np->vpd.board_model[i + 3] = (tmp >> 0) & 0xff;
8531 np->vpd.board_model[i + 2] = (tmp >> 8) & 0xff;
8532 np->vpd.board_model[i + 1] = (tmp >> 16) & 0xff;
8533 np->vpd.board_model[i + 0] = (tmp >> 24) & 0xff;
8534 }
8535 np->vpd.board_model[val] = '\0';
8536
8537 np->vpd.mac_num =
8538 nr64(ESPC_NUM_PORTS_MACS) & ESPC_NUM_PORTS_MACS_VAL;
f10a1f2e
JP		 8539 netif_printk(np, probe, KERN_DEBUG, np->dev,
8540 "SPROM: NUM_PORTS_MACS[%d]\n", np->vpd.mac_num);
a3138df9
DM		 8541
8542 return 0;
8543}
8544
8545static int __devinit niu_get_and_validate_port(struct niu *np)
8546{
8547 struct niu_parent *parent = np->parent;
8548
8549 if (np->port <= 1)
8550 np->flags |= NIU_FLAGS_XMAC;
8551
8552 if (!parent->num_ports) {
8553 if (parent->plat_type == PLAT_TYPE_NIU) {
8554 parent->num_ports = 2;
8555 } else {
7f7c4072
MW		 8556 parent->num_ports = niu_pci_vpd_get_nports(np);
8557 if (!parent->num_ports) {
8558 /* Fall back to SPROM as last resort.
8559 * This will fail on most cards.
8560 */
8561 parent->num_ports = nr64(ESPC_NUM_PORTS_MACS) &
8562 ESPC_NUM_PORTS_MACS_VAL;
8563
be0c007a
DM		 8564 /* All of the current probing methods fail on
8565 * Maramba on-board parts.
8566 */
7f7c4072 8567 if (!parent->num_ports)
be0c007a 8568 parent->num_ports = 4;
7f7c4072 8569 }
a3138df9
DM		 8570 }
8571 }
8572
a3138df9
DM		 8573 if (np->port >= parent->num_ports)
8574 return -ENODEV;
8575
8576 return 0;
8577}
8578
8579static int __devinit phy_record(struct niu_parent *parent,
8580 struct phy_probe_info *p,
8581 int dev_id_1, int dev_id_2, u8 phy_port,
8582 int type)
8583{
8584 u32 id = (dev_id_1 << 16) | dev_id_2;
8585 u8 idx;
8586
8587 if (dev_id_1 < 0 || dev_id_2 < 0)
8588 return 0;
8589 if (type == PHY_TYPE_PMA_PMD || type == PHY_TYPE_PCS) {
b0de8e40 8590 if (((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8704) &&
a5d6ab56
MW		 8591 ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_MRVL88X2011) &&
8592 ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8706))
a3138df9
DM		 8593 return 0;
8594 } else {
8595 if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM5464R)
8596 return 0;
8597 }
8598
8599 pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n",
8600 parent->index, id,
f10a1f2e
JP		 8601 type == PHY_TYPE_PMA_PMD ? "PMA/PMD" :
8602 type == PHY_TYPE_PCS ? "PCS" : "MII",
a3138df9
DM		 8603 phy_port);
8604
8605 if (p->cur[type] >= NIU_MAX_PORTS) {
f10a1f2e 8606 pr_err("Too many PHY ports\n");
a3138df9
DM		 8607 return -EINVAL;
8608 }
8609 idx = p->cur[type];
8610 p->phy_id[type][idx] = id;
8611 p->phy_port[type][idx] = phy_port;
8612 p->cur[type] = idx + 1;
8613 return 0;
8614}
8615
8616static int __devinit port_has_10g(struct phy_probe_info *p, int port)
8617{
8618 int i;
8619
8620 for (i = 0; i < p->cur[PHY_TYPE_PMA_PMD]; i++) {
8621 if (p->phy_port[PHY_TYPE_PMA_PMD][i] == port)
8622 return 1;
8623 }
8624 for (i = 0; i < p->cur[PHY_TYPE_PCS]; i++) {
8625 if (p->phy_port[PHY_TYPE_PCS][i] == port)
8626 return 1;
8627 }
8628
8629 return 0;
8630}
8631
8632static int __devinit count_10g_ports(struct phy_probe_info *p, int *lowest)
8633{
8634 int port, cnt;
8635
8636 cnt = 0;
8637 *lowest = 32;
8638 for (port = 8; port < 32; port++) {
8639 if (port_has_10g(p, port)) {
8640 if (!cnt)
8641 *lowest = port;
8642 cnt++;
8643 }
8644 }
8645
8646 return cnt;
8647}
8648
8649static int __devinit count_1g_ports(struct phy_probe_info *p, int *lowest)
8650{
8651 *lowest = 32;
8652 if (p->cur[PHY_TYPE_MII])
8653 *lowest = p->phy_port[PHY_TYPE_MII][0];
8654
8655 return p->cur[PHY_TYPE_MII];
8656}
8657
8658static void __devinit niu_n2_divide_channels(struct niu_parent *parent)
8659{
8660 int num_ports = parent->num_ports;
8661 int i;
8662
8663 for (i = 0; i < num_ports; i++) {
8664 parent->rxchan_per_port[i] = (16 / num_ports);
8665 parent->txchan_per_port[i] = (16 / num_ports);
8666
f10a1f2e 8667 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n",
a3138df9
DM		 8668 parent->index, i,
8669 parent->rxchan_per_port[i],
8670 parent->txchan_per_port[i]);
8671 }
8672}
8673
8674static void __devinit niu_divide_channels(struct niu_parent *parent,
8675 int num_10g, int num_1g)
8676{
8677 int num_ports = parent->num_ports;
8678 int rx_chans_per_10g, rx_chans_per_1g;
8679 int tx_chans_per_10g, tx_chans_per_1g;
8680 int i, tot_rx, tot_tx;
8681
8682 if (!num_10g || !num_1g) {
8683 rx_chans_per_10g = rx_chans_per_1g =
8684 (NIU_NUM_RXCHAN / num_ports);
8685 tx_chans_per_10g = tx_chans_per_1g =
8686 (NIU_NUM_TXCHAN / num_ports);
8687 } else {
8688 rx_chans_per_1g = NIU_NUM_RXCHAN / 8;
8689 rx_chans_per_10g = (NIU_NUM_RXCHAN -
8690 (rx_chans_per_1g * num_1g)) /
8691 num_10g;
8692
8693 tx_chans_per_1g = NIU_NUM_TXCHAN / 6;
8694 tx_chans_per_10g = (NIU_NUM_TXCHAN -
8695 (tx_chans_per_1g * num_1g)) /
8696 num_10g;
8697 }
8698
8699 tot_rx = tot_tx = 0;
8700 for (i = 0; i < num_ports; i++) {
8701 int type = phy_decode(parent->port_phy, i);
8702
8703 if (type == PORT_TYPE_10G) {
8704 parent->rxchan_per_port[i] = rx_chans_per_10g;
8705 parent->txchan_per_port[i] = tx_chans_per_10g;
8706 } else {
8707 parent->rxchan_per_port[i] = rx_chans_per_1g;
8708 parent->txchan_per_port[i] = tx_chans_per_1g;
8709 }
f10a1f2e 8710 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n",
a3138df9
DM		 8711 parent->index, i,
8712 parent->rxchan_per_port[i],
8713 parent->txchan_per_port[i]);
8714 tot_rx += parent->rxchan_per_port[i];
8715 tot_tx += parent->txchan_per_port[i];
8716 }
8717
8718 if (tot_rx > NIU_NUM_RXCHAN) {
f10a1f2e 8719 pr_err("niu%d: Too many RX channels (%d), resetting to one per port\n",
a3138df9
DM		 8720 parent->index, tot_rx);
8721 for (i = 0; i < num_ports; i++)
8722 parent->rxchan_per_port[i] = 1;
8723 }
8724 if (tot_tx > NIU_NUM_TXCHAN) {
f10a1f2e 8725 pr_err("niu%d: Too many TX channels (%d), resetting to one per port\n",
a3138df9
DM		 8726 parent->index, tot_tx);
8727 for (i = 0; i < num_ports; i++)
8728 parent->txchan_per_port[i] = 1;
8729 }
8730 if (tot_rx < NIU_NUM_RXCHAN || tot_tx < NIU_NUM_TXCHAN) {
f10a1f2e
JP		 8731 pr_warning("niu%d: Driver bug, wasted channels, RX[%d] TX[%d]\n",
8732 parent->index, tot_rx, tot_tx);
a3138df9
DM		 8733 }
8734}
8735
8736static void __devinit niu_divide_rdc_groups(struct niu_parent *parent,
8737 int num_10g, int num_1g)
8738{
8739 int i, num_ports = parent->num_ports;
8740 int rdc_group, rdc_groups_per_port;
8741 int rdc_channel_base;
8742
8743 rdc_group = 0;
8744 rdc_groups_per_port = NIU_NUM_RDC_TABLES / num_ports;
8745
8746 rdc_channel_base = 0;
8747
8748 for (i = 0; i < num_ports; i++) {
8749 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[i];
8750 int grp, num_channels = parent->rxchan_per_port[i];
8751 int this_channel_offset;
8752
8753 tp->first_table_num = rdc_group;
8754 tp->num_tables = rdc_groups_per_port;
8755 this_channel_offset = 0;
8756 for (grp = 0; grp < tp->num_tables; grp++) {
8757 struct rdc_table *rt = &tp->tables[grp];
8758 int slot;
8759
f10a1f2e 8760 pr_info("niu%d: Port %d RDC tbl(%d) [ ",
a3138df9
DM		 8761 parent->index, i, tp->first_table_num + grp);
8762 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) {
8763 rt->rxdma_channel[slot] =
8764 rdc_channel_base + this_channel_offset;
8765
f10a1f2e 8766 pr_cont("%d ", rt->rxdma_channel[slot]);
a3138df9
DM		 8767
8768 if (++this_channel_offset == num_channels)
8769 this_channel_offset = 0;
8770 }
f10a1f2e 8771 pr_cont("]\n");
a3138df9
DM		 8772 }
8773
8774 parent->rdc_default[i] = rdc_channel_base;
8775
8776 rdc_channel_base += num_channels;
8777 rdc_group += rdc_groups_per_port;
8778 }
8779}
8780
8781static int __devinit fill_phy_probe_info(struct niu *np,
8782 struct niu_parent *parent,
8783 struct phy_probe_info *info)
8784{
8785 unsigned long flags;
8786 int port, err;
8787
8788 memset(info, 0, sizeof(*info));
8789
8790 /* Port 0 to 7 are reserved for onboard Serdes, probe the rest. */
8791 niu_lock_parent(np, flags);
8792 err = 0;
8793 for (port = 8; port < 32; port++) {
8794 int dev_id_1, dev_id_2;
8795
8796 dev_id_1 = mdio_read(np, port,
8797 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID1);
8798 dev_id_2 = mdio_read(np, port,
8799 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID2);
8800 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8801 PHY_TYPE_PMA_PMD);
8802 if (err)
8803 break;
8804 dev_id_1 = mdio_read(np, port,
8805 NIU_PCS_DEV_ADDR, MII_PHYSID1);
8806 dev_id_2 = mdio_read(np, port,
8807 NIU_PCS_DEV_ADDR, MII_PHYSID2);
8808 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8809 PHY_TYPE_PCS);
8810 if (err)
8811 break;
8812 dev_id_1 = mii_read(np, port, MII_PHYSID1);
8813 dev_id_2 = mii_read(np, port, MII_PHYSID2);
8814 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8815 PHY_TYPE_MII);
8816 if (err)
8817 break;
8818 }
8819 niu_unlock_parent(np, flags);
8820
8821 return err;
8822}
8823
8824static int __devinit walk_phys(struct niu *np, struct niu_parent *parent)
8825{
8826 struct phy_probe_info *info = &parent->phy_probe_info;
8827 int lowest_10g, lowest_1g;
8828 int num_10g, num_1g;
8829 u32 val;
8830 int err;
8831
e3e081e1
SB		 8832 num_10g = num_1g = 0;
8833
f9af8574
MW		 8834 if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
8835 !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
5fbd7e24
MW		 8836 num_10g = 0;
8837 num_1g = 2;
8838 parent->plat_type = PLAT_TYPE_ATCA_CP3220;
8839 parent->num_ports = 4;
8840 val = (phy_encode(PORT_TYPE_1G, 0) |
8841 phy_encode(PORT_TYPE_1G, 1) |
a3138df9
DM		 8842 phy_encode(PORT_TYPE_1G, 2) |
8843 phy_encode(PORT_TYPE_1G, 3));
f9af8574 8844 } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
a5d6ab56
MW		 8845 num_10g = 2;
8846 num_1g = 0;
8847 parent->num_ports = 2;
8848 val = (phy_encode(PORT_TYPE_10G, 0) |
8849 phy_encode(PORT_TYPE_10G, 1));
e3e081e1
SB		 8850 } else if ((np->flags & NIU_FLAGS_XCVR_SERDES) &&
8851 (parent->plat_type == PLAT_TYPE_NIU)) {
8852 /* this is the Monza case */
8853 if (np->flags & NIU_FLAGS_10G) {
8854 val = (phy_encode(PORT_TYPE_10G, 0) |
8855 phy_encode(PORT_TYPE_10G, 1));
8856 } else {
8857 val = (phy_encode(PORT_TYPE_1G, 0) |
8858 phy_encode(PORT_TYPE_1G, 1));
8859 }
5fbd7e24
MW		 8860 } else {
8861 err = fill_phy_probe_info(np, parent, info);
8862 if (err)
8863 return err;
a3138df9 8864
5fbd7e24
MW		 8865 num_10g = count_10g_ports(info, &lowest_10g);
8866 num_1g = count_1g_ports(info, &lowest_1g);
a3138df9 8867
5fbd7e24
MW		 8868 switch ((num_10g << 4) | num_1g) {
8869 case 0x24:
8870 if (lowest_1g == 10)
8871 parent->plat_type = PLAT_TYPE_VF_P0;
8872 else if (lowest_1g == 26)
8873 parent->plat_type = PLAT_TYPE_VF_P1;
8874 else
8875 goto unknown_vg_1g_port;
a3138df9 8876
5fbd7e24
MW		 8877 /* fallthru */
8878 case 0x22:
a3138df9 8879 val = (phy_encode(PORT_TYPE_10G, 0) |
a3138df9
DM		 8880 phy_encode(PORT_TYPE_10G, 1) |
8881 phy_encode(PORT_TYPE_1G, 2) |
8882 phy_encode(PORT_TYPE_1G, 3));
5fbd7e24 8883 break;
a3138df9 8884
5fbd7e24
MW		 8885 case 0x20:
8886 val = (phy_encode(PORT_TYPE_10G, 0) |
8887 phy_encode(PORT_TYPE_10G, 1));
8888 break;
a3138df9 8889
5fbd7e24
MW		 8890 case 0x10:
8891 val = phy_encode(PORT_TYPE_10G, np->port);
8892 break;
a3138df9 8893
5fbd7e24
MW		 8894 case 0x14:
8895 if (lowest_1g == 10)
8896 parent->plat_type = PLAT_TYPE_VF_P0;
8897 else if (lowest_1g == 26)
8898 parent->plat_type = PLAT_TYPE_VF_P1;
8899 else
8900 goto unknown_vg_1g_port;
8901
8902 /* fallthru */
8903 case 0x13:
8904 if ((lowest_10g & 0x7) == 0)
8905 val = (phy_encode(PORT_TYPE_10G, 0) |
8906 phy_encode(PORT_TYPE_1G, 1) |
8907 phy_encode(PORT_TYPE_1G, 2) |
8908 phy_encode(PORT_TYPE_1G, 3));
8909 else
8910 val = (phy_encode(PORT_TYPE_1G, 0) |
8911 phy_encode(PORT_TYPE_10G, 1) |
8912 phy_encode(PORT_TYPE_1G, 2) |
8913 phy_encode(PORT_TYPE_1G, 3));
8914 break;
8915
8916 case 0x04:
8917 if (lowest_1g == 10)
8918 parent->plat_type = PLAT_TYPE_VF_P0;
8919 else if (lowest_1g == 26)
8920 parent->plat_type = PLAT_TYPE_VF_P1;
8921 else
8922 goto unknown_vg_1g_port;
8923
8924 val = (phy_encode(PORT_TYPE_1G, 0) |
8925 phy_encode(PORT_TYPE_1G, 1) |
8926 phy_encode(PORT_TYPE_1G, 2) |
8927 phy_encode(PORT_TYPE_1G, 3));
8928 break;
8929
8930 default:
f10a1f2e 8931 pr_err("Unsupported port config 10G[%d] 1G[%d]\n",
5fbd7e24
MW		 8932 num_10g, num_1g);
8933 return -EINVAL;
8934 }
a3138df9
DM		 8935 }
8936
8937 parent->port_phy = val;
8938
8939 if (parent->plat_type == PLAT_TYPE_NIU)
8940 niu_n2_divide_channels(parent);
8941 else
8942 niu_divide_channels(parent, num_10g, num_1g);
8943
8944 niu_divide_rdc_groups(parent, num_10g, num_1g);
8945
8946 return 0;
8947
8948unknown_vg_1g_port:
f10a1f2e 8949 pr_err("Cannot identify platform type, 1gport=%d\n", lowest_1g);
a3138df9
DM		 8950 return -EINVAL;
8951}
8952
8953static int __devinit niu_probe_ports(struct niu *np)
8954{
8955 struct niu_parent *parent = np->parent;
8956 int err, i;
8957
a3138df9
DM		 8958 if (parent->port_phy == PORT_PHY_UNKNOWN) {
8959 err = walk_phys(np, parent);
8960 if (err)
8961 return err;
8962
8963 niu_set_ldg_timer_res(np, 2);
8964 for (i = 0; i <= LDN_MAX; i++)
8965 niu_ldn_irq_enable(np, i, 0);
8966 }
8967
8968 if (parent->port_phy == PORT_PHY_INVALID)
8969 return -EINVAL;
8970
8971 return 0;
8972}
8973
8974static int __devinit niu_classifier_swstate_init(struct niu *np)
8975{
8976 struct niu_classifier *cp = &np->clas;
8977
2d96cf8c
SB		 8978 cp->tcam_top = (u16) np->port;
8979 cp->tcam_sz = np->parent->tcam_num_entries / np->parent->num_ports;
a3138df9
DM		 8980 cp->h1_init = 0xffffffff;
8981 cp->h2_init = 0xffff;
8982
8983 return fflp_early_init(np);
8984}
8985
8986static void __devinit niu_link_config_init(struct niu *np)
8987{
8988 struct niu_link_config *lp = &np->link_config;
8989
8990 lp->advertising = (ADVERTISED_10baseT_Half |
8991 ADVERTISED_10baseT_Full |
8992 ADVERTISED_100baseT_Half |
8993 ADVERTISED_100baseT_Full |
8994 ADVERTISED_1000baseT_Half |
8995 ADVERTISED_1000baseT_Full |
8996 ADVERTISED_10000baseT_Full |
8997 ADVERTISED_Autoneg);
8998 lp->speed = lp->active_speed = SPEED_INVALID;
38bb045d
CB		 8999 lp->duplex = DUPLEX_FULL;
9000 lp->active_duplex = DUPLEX_INVALID;
9001 lp->autoneg = 1;
a3138df9
DM		 9002#if 0
9003 lp->loopback_mode = LOOPBACK_MAC;
9004 lp->active_speed = SPEED_10000;
9005 lp->active_duplex = DUPLEX_FULL;
9006#else
9007 lp->loopback_mode = LOOPBACK_DISABLED;
9008#endif
9009}
9010
9011static int __devinit niu_init_mac_ipp_pcs_base(struct niu *np)
9012{
9013 switch (np->port) {
9014 case 0:
9015 np->mac_regs = np->regs + XMAC_PORT0_OFF;
9016 np->ipp_off = 0x00000;
9017 np->pcs_off = 0x04000;
9018 np->xpcs_off = 0x02000;
9019 break;
9020
9021 case 1:
9022 np->mac_regs = np->regs + XMAC_PORT1_OFF;
9023 np->ipp_off = 0x08000;
9024 np->pcs_off = 0x0a000;
9025 np->xpcs_off = 0x08000;
9026 break;
9027
9028 case 2:
9029 np->mac_regs = np->regs + BMAC_PORT2_OFF;
9030 np->ipp_off = 0x04000;
9031 np->pcs_off = 0x0e000;
9032 np->xpcs_off = ~0UL;
9033 break;
9034
9035 case 3:
9036 np->mac_regs = np->regs + BMAC_PORT3_OFF;
9037 np->ipp_off = 0x0c000;
9038 np->pcs_off = 0x12000;
9039 np->xpcs_off = ~0UL;
9040 break;
9041
9042 default:
f10a1f2e 9043 dev_err(np->device, "Port %u is invalid, cannot compute MAC block offset\n", np->port);
a3138df9
DM		 9044 return -EINVAL;
9045 }
9046
9047 return 0;
9048}
9049
9050static void __devinit niu_try_msix(struct niu *np, u8 *ldg_num_map)
9051{
9052 struct msix_entry msi_vec[NIU_NUM_LDG];
9053 struct niu_parent *parent = np->parent;
9054 struct pci_dev *pdev = np->pdev;
9055 int i, num_irqs, err;
9056 u8 first_ldg;
9057
9058 first_ldg = (NIU_NUM_LDG / parent->num_ports) * np->port;
9059 for (i = 0; i < (NIU_NUM_LDG / parent->num_ports); i++)
9060 ldg_num_map[i] = first_ldg + i;
9061
9062 num_irqs = (parent->rxchan_per_port[np->port] +
9063 parent->txchan_per_port[np->port] +
9064 (np->port == 0 ? 3 : 1));
9065 BUG_ON(num_irqs > (NIU_NUM_LDG / parent->num_ports));
9066
9067retry:
9068 for (i = 0; i < num_irqs; i++) {
9069 msi_vec[i].vector = 0;
9070 msi_vec[i].entry = i;
9071 }
9072
9073 err = pci_enable_msix(pdev, msi_vec, num_irqs);
9074 if (err < 0) {
9075 np->flags &= ~NIU_FLAGS_MSIX;
9076 return;
9077 }
9078 if (err > 0) {
9079 num_irqs = err;
9080 goto retry;
9081 }
9082
9083 np->flags |= NIU_FLAGS_MSIX;
9084 for (i = 0; i < num_irqs; i++)
9085 np->ldg[i].irq = msi_vec[i].vector;
9086 np->num_ldg = num_irqs;
9087}
9088
9089static int __devinit niu_n2_irq_init(struct niu *np, u8 *ldg_num_map)
9090{
9091#ifdef CONFIG_SPARC64
9092 struct of_device *op = np->op;
9093 const u32 *int_prop;
9094 int i;
9095
9096 int_prop = of_get_property(op->node, "interrupts", NULL);
9097 if (!int_prop)
9098 return -ENODEV;
9099
9100 for (i = 0; i < op->num_irqs; i++) {
9101 ldg_num_map[i] = int_prop[i];
9102 np->ldg[i].irq = op->irqs[i];
9103 }
9104
9105 np->num_ldg = op->num_irqs;
9106
9107 return 0;
9108#else
9109 return -EINVAL;
9110#endif
9111}
9112
9113static int __devinit niu_ldg_init(struct niu *np)
9114{
9115 struct niu_parent *parent = np->parent;
9116 u8 ldg_num_map[NIU_NUM_LDG];
9117 int first_chan, num_chan;
9118 int i, err, ldg_rotor;
9119 u8 port;
9120
9121 np->num_ldg = 1;
9122 np->ldg[0].irq = np->dev->irq;
9123 if (parent->plat_type == PLAT_TYPE_NIU) {
9124 err = niu_n2_irq_init(np, ldg_num_map);
9125 if (err)
9126 return err;
9127 } else
9128 niu_try_msix(np, ldg_num_map);
9129
9130 port = np->port;
9131 for (i = 0; i < np->num_ldg; i++) {
9132 struct niu_ldg *lp = &np->ldg[i];
9133
9134 netif_napi_add(np->dev, &lp->napi, niu_poll, 64);
9135
9136 lp->np = np;
9137 lp->ldg_num = ldg_num_map[i];
9138 lp->timer = 2; /* XXX */
9139
9140 /* On N2 NIU the firmware has setup the SID mappings so they go
9141 * to the correct values that will route the LDG to the proper
9142 * interrupt in the NCU interrupt table.
9143 */
9144 if (np->parent->plat_type != PLAT_TYPE_NIU) {
9145 err = niu_set_ldg_sid(np, lp->ldg_num, port, i);
9146 if (err)
9147 return err;
9148 }
9149 }
9150
9151 /* We adopt the LDG assignment ordering used by the N2 NIU
9152 * 'interrupt' properties because that simplifies a lot of
9153 * things. This ordering is:
9154 *
9155 * MAC
9156 * MIF (if port zero)
9157 * SYSERR (if port zero)
9158 * RX channels
9159 * TX channels
9160 */
9161
9162 ldg_rotor = 0;
9163
9164 err = niu_ldg_assign_ldn(np, parent, ldg_num_map[ldg_rotor],
9165 LDN_MAC(port));
9166 if (err)
9167 return err;
9168
9169 ldg_rotor++;
9170 if (ldg_rotor == np->num_ldg)
9171 ldg_rotor = 0;
9172
9173 if (port == 0) {
9174 err = niu_ldg_assign_ldn(np, parent,
9175 ldg_num_map[ldg_rotor],
9176 LDN_MIF);
9177 if (err)
9178 return err;
9179
9180 ldg_rotor++;
9181 if (ldg_rotor == np->num_ldg)
9182 ldg_rotor = 0;
9183
9184 err = niu_ldg_assign_ldn(np, parent,
9185 ldg_num_map[ldg_rotor],
9186 LDN_DEVICE_ERROR);
9187 if (err)
9188 return err;
9189
9190 ldg_rotor++;
9191 if (ldg_rotor == np->num_ldg)
9192 ldg_rotor = 0;
9193
9194 }
9195
9196 first_chan = 0;
9197 for (i = 0; i < port; i++)
9198 first_chan += parent->rxchan_per_port[port];
9199 num_chan = parent->rxchan_per_port[port];
9200
9201 for (i = first_chan; i < (first_chan + num_chan); i++) {
9202 err = niu_ldg_assign_ldn(np, parent,
9203 ldg_num_map[ldg_rotor],
9204 LDN_RXDMA(i));
9205 if (err)
9206 return err;
9207 ldg_rotor++;
9208 if (ldg_rotor == np->num_ldg)
9209 ldg_rotor = 0;
9210 }
9211
9212 first_chan = 0;
9213 for (i = 0; i < port; i++)
9214 first_chan += parent->txchan_per_port[port];
9215 num_chan = parent->txchan_per_port[port];
9216 for (i = first_chan; i < (first_chan + num_chan); i++) {
9217 err = niu_ldg_assign_ldn(np, parent,
9218 ldg_num_map[ldg_rotor],
9219 LDN_TXDMA(i));
9220 if (err)
9221 return err;
9222 ldg_rotor++;
9223 if (ldg_rotor == np->num_ldg)
9224 ldg_rotor = 0;
9225 }
9226
9227 return 0;
9228}
9229
9230static void __devexit niu_ldg_free(struct niu *np)
9231{
9232 if (np->flags & NIU_FLAGS_MSIX)
9233 pci_disable_msix(np->pdev);
9234}
9235
9236static int __devinit niu_get_of_props(struct niu *np)
9237{
9238#ifdef CONFIG_SPARC64
9239 struct net_device *dev = np->dev;
9240 struct device_node *dp;
9241 const char *phy_type;
9242 const u8 *mac_addr;
f9af8574 9243 const char *model;
a3138df9
DM		 9244 int prop_len;
9245
9246 if (np->parent->plat_type == PLAT_TYPE_NIU)
9247 dp = np->op->node;
9248 else
9249 dp = pci_device_to_OF_node(np->pdev);
9250
9251 phy_type = of_get_property(dp, "phy-type", &prop_len);
9252 if (!phy_type) {
f10a1f2e
JP		 9253 netdev_err(dev, "%s: OF node lacks phy-type property\n",
9254 dp->full_name);
a3138df9
DM		 9255 return -EINVAL;
9256 }
9257
9258 if (!strcmp(phy_type, "none"))
9259 return -ENODEV;
9260
9261 strcpy(np->vpd.phy_type, phy_type);
9262
9263 if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
f10a1f2e
JP		 9264 netdev_err(dev, "%s: Illegal phy string [%s]\n",
9265 dp->full_name, np->vpd.phy_type);
a3138df9
DM		 9266 return -EINVAL;
9267 }
9268
9269 mac_addr = of_get_property(dp, "local-mac-address", &prop_len);
9270 if (!mac_addr) {
f10a1f2e
JP		 9271 netdev_err(dev, "%s: OF node lacks local-mac-address property\n",
9272 dp->full_name);
a3138df9
DM		 9273 return -EINVAL;
9274 }
9275 if (prop_len != dev->addr_len) {
f10a1f2e
JP		 9276 netdev_err(dev, "%s: OF MAC address prop len (%d) is wrong\n",
9277 dp->full_name, prop_len);
a3138df9
DM		 9278 }
9279 memcpy(dev->perm_addr, mac_addr, dev->addr_len);
9280 if (!is_valid_ether_addr(&dev->perm_addr[0])) {
f10a1f2e
JP		 9281 netdev_err(dev, "%s: OF MAC address is invalid\n",
9282 dp->full_name);
9283 netdev_err(dev, "%s: [ %pM ]\n", dp->full_name, dev->perm_addr);
a3138df9
DM		 9284 return -EINVAL;
9285 }
9286
9287 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
f9af8574
MW		 9288
9289 model = of_get_property(dp, "model", &prop_len);
9290
9291 if (model)
9292 strcpy(np->vpd.model, model);
a3138df9 9293
9c5cd670
TC		 9294 if (of_find_property(dp, "hot-swappable-phy", &prop_len)) {
9295 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
9296 NIU_FLAGS_HOTPLUG_PHY);
9297 }
9298
a3138df9
DM		 9299 return 0;
9300#else
9301 return -EINVAL;
9302#endif
9303}
9304
9305static int __devinit niu_get_invariants(struct niu *np)
9306{
9307 int err, have_props;
9308 u32 offset;
9309
9310 err = niu_get_of_props(np);
9311 if (err == -ENODEV)
9312 return err;
9313
9314 have_props = !err;
9315
a3138df9
DM		 9316 err = niu_init_mac_ipp_pcs_base(np);
9317 if (err)
9318 return err;
9319
7f7c4072
MW		 9320 if (have_props) {
9321 err = niu_get_and_validate_port(np);
9322 if (err)
9323 return err;
9324
9325 } else {
a3138df9
DM		 9326 if (np->parent->plat_type == PLAT_TYPE_NIU)
9327 return -EINVAL;
9328
9329 nw64(ESPC_PIO_EN, ESPC_PIO_EN_ENABLE);
9330 offset = niu_pci_vpd_offset(np);
f10a1f2e
JP		 9331 netif_printk(np, probe, KERN_DEBUG, np->dev,
9332 "%s() VPD offset [%08x]\n", __func__, offset);
a3138df9
DM		 9333 if (offset)
9334 niu_pci_vpd_fetch(np, offset);
9335 nw64(ESPC_PIO_EN, 0);
9336
7f7c4072 9337 if (np->flags & NIU_FLAGS_VPD_VALID) {
a3138df9 9338 niu_pci_vpd_validate(np);
7f7c4072
MW		 9339 err = niu_get_and_validate_port(np);
9340 if (err)
9341 return err;
9342 }
a3138df9
DM		 9343
9344 if (!(np->flags & NIU_FLAGS_VPD_VALID)) {
7f7c4072
MW		 9345 err = niu_get_and_validate_port(np);
9346 if (err)
9347 return err;
a3138df9
DM		 9348 err = niu_pci_probe_sprom(np);
9349 if (err)
9350 return err;
9351 }
9352 }
9353
9354 err = niu_probe_ports(np);
9355 if (err)
9356 return err;
9357
9358 niu_ldg_init(np);
9359
9360 niu_classifier_swstate_init(np);
9361 niu_link_config_init(np);
9362
9363 err = niu_determine_phy_disposition(np);
9364 if (!err)
9365 err = niu_init_link(np);
9366
9367 return err;
9368}
9369
9370static LIST_HEAD(niu_parent_list);
9371static DEFINE_MUTEX(niu_parent_lock);
9372static int niu_parent_index;
9373
9374static ssize_t show_port_phy(struct device *dev,
9375 struct device_attribute *attr, char *buf)
9376{
9377 struct platform_device *plat_dev = to_platform_device(dev);
9378 struct niu_parent *p = plat_dev->dev.platform_data;
9379 u32 port_phy = p->port_phy;
9380 char *orig_buf = buf;
9381 int i;
9382
9383 if (port_phy == PORT_PHY_UNKNOWN ||
9384 port_phy == PORT_PHY_INVALID)
9385 return 0;
9386
9387 for (i = 0; i < p->num_ports; i++) {
9388 const char *type_str;
9389 int type;
9390
9391 type = phy_decode(port_phy, i);
9392 if (type == PORT_TYPE_10G)
9393 type_str = "10G";
9394 else
9395 type_str = "1G";
9396 buf += sprintf(buf,
9397 (i == 0) ? "%s" : " %s",
9398 type_str);
9399 }
9400 buf += sprintf(buf, "\n");
9401 return buf - orig_buf;
9402}
9403
9404static ssize_t show_plat_type(struct device *dev,
9405 struct device_attribute *attr, char *buf)
9406{
9407 struct platform_device *plat_dev = to_platform_device(dev);
9408 struct niu_parent *p = plat_dev->dev.platform_data;
9409 const char *type_str;
9410
9411 switch (p->plat_type) {
9412 case PLAT_TYPE_ATLAS:
9413 type_str = "atlas";
9414 break;
9415 case PLAT_TYPE_NIU:
9416 type_str = "niu";
9417 break;
9418 case PLAT_TYPE_VF_P0:
9419 type_str = "vf_p0";
9420 break;
9421 case PLAT_TYPE_VF_P1:
9422 type_str = "vf_p1";
9423 break;
9424 default:
9425 type_str = "unknown";
9426 break;
9427 }
9428
9429 return sprintf(buf, "%s\n", type_str);
9430}
9431
9432static ssize_t __show_chan_per_port(struct device *dev,
9433 struct device_attribute *attr, char *buf,
9434 int rx)
9435{
9436 struct platform_device *plat_dev = to_platform_device(dev);
9437 struct niu_parent *p = plat_dev->dev.platform_data;
9438 char *orig_buf = buf;
9439 u8 *arr;
9440 int i;
9441
9442 arr = (rx ? p->rxchan_per_port : p->txchan_per_port);
9443
9444 for (i = 0; i < p->num_ports; i++) {
9445 buf += sprintf(buf,
9446 (i == 0) ? "%d" : " %d",
9447 arr[i]);
9448 }
9449 buf += sprintf(buf, "\n");
9450
9451 return buf - orig_buf;
9452}
9453
9454static ssize_t show_rxchan_per_port(struct device *dev,
9455 struct device_attribute *attr, char *buf)
9456{
9457 return __show_chan_per_port(dev, attr, buf, 1);
9458}
9459
9460static ssize_t show_txchan_per_port(struct device *dev,
9461 struct device_attribute *attr, char *buf)
9462{
9463 return __show_chan_per_port(dev, attr, buf, 1);
9464}
9465
9466static ssize_t show_num_ports(struct device *dev,
9467 struct device_attribute *attr, char *buf)
9468{
9469 struct platform_device *plat_dev = to_platform_device(dev);
9470 struct niu_parent *p = plat_dev->dev.platform_data;
9471
9472 return sprintf(buf, "%d\n", p->num_ports);
9473}
9474
9475static struct device_attribute niu_parent_attributes[] = {
9476 __ATTR(port_phy, S_IRUGO, show_port_phy, NULL),
9477 __ATTR(plat_type, S_IRUGO, show_plat_type, NULL),
9478 __ATTR(rxchan_per_port, S_IRUGO, show_rxchan_per_port, NULL),
9479 __ATTR(txchan_per_port, S_IRUGO, show_txchan_per_port, NULL),
9480 __ATTR(num_ports, S_IRUGO, show_num_ports, NULL),
9481 {}
9482};
9483
9484static struct niu_parent * __devinit niu_new_parent(struct niu *np,
9485 union niu_parent_id *id,
9486 u8 ptype)
9487{
9488 struct platform_device *plat_dev;
9489 struct niu_parent *p;
9490 int i;
9491
a3138df9
DM		 9492 plat_dev = platform_device_register_simple("niu", niu_parent_index,
9493 NULL, 0);
58f3e0a8 9494 if (IS_ERR(plat_dev))
a3138df9
DM		 9495 return NULL;
9496
9497 for (i = 0; attr_name(niu_parent_attributes[i]); i++) {
9498 int err = device_create_file(&plat_dev->dev,
9499 &niu_parent_attributes[i]);
9500 if (err)
9501 goto fail_unregister;
9502 }
9503
9504 p = kzalloc(sizeof(*p), GFP_KERNEL);
9505 if (!p)
9506 goto fail_unregister;
9507
9508 p->index = niu_parent_index++;
9509
9510 plat_dev->dev.platform_data = p;
9511 p->plat_dev = plat_dev;
9512
9513 memcpy(&p->id, id, sizeof(*id));
9514 p->plat_type = ptype;
9515 INIT_LIST_HEAD(&p->list);
9516 atomic_set(&p->refcnt, 0);
9517 list_add(&p->list, &niu_parent_list);
9518 spin_lock_init(&p->lock);
9519
9520 p->rxdma_clock_divider = 7500;
9521
9522 p->tcam_num_entries = NIU_PCI_TCAM_ENTRIES;
9523 if (p->plat_type == PLAT_TYPE_NIU)
9524 p->tcam_num_entries = NIU_NONPCI_TCAM_ENTRIES;
9525
9526 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
9527 int index = i - CLASS_CODE_USER_PROG1;
9528
9529 p->tcam_key[index] = TCAM_KEY_TSEL;
9530 p->flow_key[index] = (FLOW_KEY_IPSA |
9531 FLOW_KEY_IPDA |
9532 FLOW_KEY_PROTO |
9533 (FLOW_KEY_L4_BYTE12 <<
9534 FLOW_KEY_L4_0_SHIFT) |
9535 (FLOW_KEY_L4_BYTE12 <<
9536 FLOW_KEY_L4_1_SHIFT));
9537 }
9538
9539 for (i = 0; i < LDN_MAX + 1; i++)
9540 p->ldg_map[i] = LDG_INVALID;
9541
9542 return p;
9543
9544fail_unregister:
9545 platform_device_unregister(plat_dev);
9546 return NULL;
9547}
9548
9549static struct niu_parent * __devinit niu_get_parent(struct niu *np,
9550 union niu_parent_id *id,
9551 u8 ptype)
9552{
9553 struct niu_parent *p, *tmp;
9554 int port = np->port;
9555
a3138df9
DM		 9556 mutex_lock(&niu_parent_lock);
9557 p = NULL;
9558 list_for_each_entry(tmp, &niu_parent_list, list) {
9559 if (!memcmp(id, &tmp->id, sizeof(*id))) {
9560 p = tmp;
9561 break;
9562 }
9563 }
9564 if (!p)
9565 p = niu_new_parent(np, id, ptype);
9566
9567 if (p) {
9568 char port_name[6];
9569 int err;
9570
9571 sprintf(port_name, "port%d", port);
9572 err = sysfs_create_link(&p->plat_dev->dev.kobj,
9573 &np->device->kobj,
9574 port_name);
9575 if (!err) {
9576 p->ports[port] = np;
9577 atomic_inc(&p->refcnt);
9578 }
9579 }
9580 mutex_unlock(&niu_parent_lock);
9581
9582 return p;
9583}
9584
9585static void niu_put_parent(struct niu *np)
9586{
9587 struct niu_parent *p = np->parent;
9588 u8 port = np->port;
9589 char port_name[6];
9590
9591 BUG_ON(!p || p->ports[port] != np);
9592
f10a1f2e
JP		 9593 netif_printk(np, probe, KERN_DEBUG, np->dev,
9594 "%s() port[%u]\n", __func__, port);
a3138df9
DM		 9595
9596 sprintf(port_name, "port%d", port);
9597
9598 mutex_lock(&niu_parent_lock);
9599
9600 sysfs_remove_link(&p->plat_dev->dev.kobj, port_name);
9601
9602 p->ports[port] = NULL;
9603 np->parent = NULL;
9604
9605 if (atomic_dec_and_test(&p->refcnt)) {
9606 list_del(&p->list);
9607 platform_device_unregister(p->plat_dev);
9608 }
9609
9610 mutex_unlock(&niu_parent_lock);
9611}
9612
9613static void *niu_pci_alloc_coherent(struct device *dev, size_t size,
9614 u64 *handle, gfp_t flag)
9615{
9616 dma_addr_t dh;
9617 void *ret;
9618
9619 ret = dma_alloc_coherent(dev, size, &dh, flag);
9620 if (ret)
9621 *handle = dh;
9622 return ret;
9623}
9624
9625static void niu_pci_free_coherent(struct device *dev, size_t size,
9626 void *cpu_addr, u64 handle)
9627{
9628 dma_free_coherent(dev, size, cpu_addr, handle);
9629}
9630
9631static u64 niu_pci_map_page(struct device *dev, struct page *page,
9632 unsigned long offset, size_t size,
9633 enum dma_data_direction direction)
9634{
9635 return dma_map_page(dev, page, offset, size, direction);
9636}
9637
9638static void niu_pci_unmap_page(struct device *dev, u64 dma_address,
9639 size_t size, enum dma_data_direction direction)
9640{
a08b32df 9641 dma_unmap_page(dev, dma_address, size, direction);
a3138df9
DM		 9642}
9643
9644static u64 niu_pci_map_single(struct device *dev, void *cpu_addr,
9645 size_t size,
9646 enum dma_data_direction direction)
9647{
9648 return dma_map_single(dev, cpu_addr, size, direction);
9649}
9650
9651static void niu_pci_unmap_single(struct device *dev, u64 dma_address,
9652 size_t size,
9653 enum dma_data_direction direction)
9654{
9655 dma_unmap_single(dev, dma_address, size, direction);
9656}
9657
9658static const struct niu_ops niu_pci_ops = {
9659 .alloc_coherent = niu_pci_alloc_coherent,
9660 .free_coherent = niu_pci_free_coherent,
9661 .map_page = niu_pci_map_page,
9662 .unmap_page = niu_pci_unmap_page,
9663 .map_single = niu_pci_map_single,
9664 .unmap_single = niu_pci_unmap_single,
9665};
9666
9667static void __devinit niu_driver_version(void)
9668{
9669 static int niu_version_printed;
9670
9671 if (niu_version_printed++ == 0)
9672 pr_info("%s", version);
9673}
9674
9675static struct net_device * __devinit niu_alloc_and_init(
9676 struct device *gen_dev, struct pci_dev *pdev,
9677 struct of_device *op, const struct niu_ops *ops,
9678 u8 port)
9679{
b4c21639 9680 struct net_device *dev;
a3138df9
DM		 9681 struct niu *np;
9682
b4c21639 9683 dev = alloc_etherdev_mq(sizeof(struct niu), NIU_NUM_TXCHAN);
a3138df9 9684 if (!dev) {
f10a1f2e 9685 dev_err(gen_dev, "Etherdev alloc failed, aborting\n");
a3138df9
DM		 9686 return NULL;
9687 }
9688
9689 SET_NETDEV_DEV(dev, gen_dev);
9690
9691 np = netdev_priv(dev);
9692 np->dev = dev;
9693 np->pdev = pdev;
9694 np->op = op;
9695 np->device = gen_dev;
9696 np->ops = ops;
9697
9698 np->msg_enable = niu_debug;
9699
9700 spin_lock_init(&np->lock);
9701 INIT_WORK(&np->reset_task, niu_reset_task);
9702
9703 np->port = port;
9704
9705 return dev;
9706}
9707
2c9171d4
SH		 9708static const struct net_device_ops niu_netdev_ops = {
9709 .ndo_open = niu_open,
9710 .ndo_stop = niu_close,
00829823 9711 .ndo_start_xmit = niu_start_xmit,
2c9171d4
SH		 9712 .ndo_get_stats = niu_get_stats,
9713 .ndo_set_multicast_list = niu_set_rx_mode,
9714 .ndo_validate_addr = eth_validate_addr,
9715 .ndo_set_mac_address = niu_set_mac_addr,
9716 .ndo_do_ioctl = niu_ioctl,
9717 .ndo_tx_timeout = niu_tx_timeout,
9718 .ndo_change_mtu = niu_change_mtu,
9719};
9720
a3138df9
DM		 9721static void __devinit niu_assign_netdev_ops(struct net_device *dev)
9722{
2c9171d4 9723 dev->netdev_ops = &niu_netdev_ops;
a3138df9
DM		 9724 dev->ethtool_ops = &niu_ethtool_ops;
9725 dev->watchdog_timeo = NIU_TX_TIMEOUT;
a3138df9
DM		 9726}
9727
9728static void __devinit niu_device_announce(struct niu *np)
9729{
9730 struct net_device *dev = np->dev;
a3138df9 9731
e174961c 9732 pr_info("%s: NIU Ethernet %pM\n", dev->name, dev->dev_addr);
a3138df9 9733
5fbd7e24
MW		 9734 if (np->parent->plat_type == PLAT_TYPE_ATCA_CP3220) {
9735 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9736 dev->name,
9737 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9738 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
9739 (np->flags & NIU_FLAGS_FIBER ? "RGMII FIBER" : "SERDES"),
9740 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9741 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9742 np->vpd.phy_type);
9743 } else {
9744 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9745 dev->name,
9746 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9747 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
e3e081e1
SB		 9748 (np->flags & NIU_FLAGS_FIBER ? "FIBER" :
9749 (np->flags & NIU_FLAGS_XCVR_SERDES ? "SERDES" :
9750 "COPPER")),
5fbd7e24
MW		 9751 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9752 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9753 np->vpd.phy_type);
9754 }
a3138df9
DM		 9755}
9756
9757static int __devinit niu_pci_init_one(struct pci_dev *pdev,
9758 const struct pci_device_id *ent)
9759{
a3138df9
DM		 9760 union niu_parent_id parent_id;
9761 struct net_device *dev;
9762 struct niu *np;
9763 int err, pos;
9764 u64 dma_mask;
9765 u16 val16;
9766
9767 niu_driver_version();
9768
9769 err = pci_enable_device(pdev);
9770 if (err) {
f10a1f2e 9771 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
a3138df9
DM		 9772 return err;
9773 }
9774
9775 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
9776 !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
f10a1f2e 9777 dev_err(&pdev->dev, "Cannot find proper PCI device base addresses, aborting\n");
a3138df9
DM		 9778 err = -ENODEV;
9779 goto err_out_disable_pdev;
9780 }
9781
9782 err = pci_request_regions(pdev, DRV_MODULE_NAME);
9783 if (err) {
f10a1f2e 9784 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
a3138df9
DM		 9785 goto err_out_disable_pdev;
9786 }
9787
9788 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
9789 if (pos <= 0) {
f10a1f2e 9790 dev_err(&pdev->dev, "Cannot find PCI Express capability, aborting\n");
a3138df9
DM		 9791 goto err_out_free_res;
9792 }
9793
9794 dev = niu_alloc_and_init(&pdev->dev, pdev, NULL,
9795 &niu_pci_ops, PCI_FUNC(pdev->devfn));
9796 if (!dev) {
9797 err = -ENOMEM;
9798 goto err_out_free_res;
9799 }
9800 np = netdev_priv(dev);
9801
9802 memset(&parent_id, 0, sizeof(parent_id));
9803 parent_id.pci.domain = pci_domain_nr(pdev->bus);
9804 parent_id.pci.bus = pdev->bus->number;
9805 parent_id.pci.device = PCI_SLOT(pdev->devfn);
9806
9807 np->parent = niu_get_parent(np, &parent_id,
9808 PLAT_TYPE_ATLAS);
9809 if (!np->parent) {
9810 err = -ENOMEM;
9811 goto err_out_free_dev;
9812 }
9813
9814 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
9815 val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
9816 val16 |= (PCI_EXP_DEVCTL_CERE |
9817 PCI_EXP_DEVCTL_NFERE |
9818 PCI_EXP_DEVCTL_FERE |
9819 PCI_EXP_DEVCTL_URRE |
9820 PCI_EXP_DEVCTL_RELAX_EN);
9821 pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
9822
8cbd9623 9823 dma_mask = DMA_BIT_MASK(44);
a3138df9
DM		 9824 err = pci_set_dma_mask(pdev, dma_mask);
9825 if (!err) {
9826 dev->features |= NETIF_F_HIGHDMA;
9827 err = pci_set_consistent_dma_mask(pdev, dma_mask);
9828 if (err) {
f10a1f2e 9829 dev_err(&pdev->dev, "Unable to obtain 44 bit DMA for consistent allocations, aborting\n");
a3138df9
DM		 9830 goto err_out_release_parent;
9831 }
9832 }
284901a9
YH		 9833 if (err || dma_mask == DMA_BIT_MASK(32)) {
9834 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
a3138df9 9835 if (err) {
f10a1f2e 9836 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
a3138df9
DM		 9837 goto err_out_release_parent;
9838 }
9839 }
9840
e4fc9d15 9841 dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_GRO);
a3138df9 9842
19ecb6ba 9843 np->regs = pci_ioremap_bar(pdev, 0);
a3138df9 9844 if (!np->regs) {
f10a1f2e 9845 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
a3138df9
DM		 9846 err = -ENOMEM;
9847 goto err_out_release_parent;
9848 }
9849
9850 pci_set_master(pdev);
9851 pci_save_state(pdev);
9852
9853 dev->irq = pdev->irq;
9854
9855 niu_assign_netdev_ops(dev);
9856
9857 err = niu_get_invariants(np);
9858 if (err) {
9859 if (err != -ENODEV)
f10a1f2e 9860 dev_err(&pdev->dev, "Problem fetching invariants of chip, aborting\n");
a3138df9
DM		 9861 goto err_out_iounmap;
9862 }
9863
9864 err = register_netdev(dev);
9865 if (err) {
f10a1f2e 9866 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
a3138df9
DM		 9867 goto err_out_iounmap;
9868 }
9869
9870 pci_set_drvdata(pdev, dev);
9871
9872 niu_device_announce(np);
9873
9874 return 0;
9875
9876err_out_iounmap:
9877 if (np->regs) {
9878 iounmap(np->regs);
9879 np->regs = NULL;
9880 }
9881
9882err_out_release_parent:
9883 niu_put_parent(np);
9884
9885err_out_free_dev:
9886 free_netdev(dev);
9887
9888err_out_free_res:
9889 pci_release_regions(pdev);
9890
9891err_out_disable_pdev:
9892 pci_disable_device(pdev);
9893 pci_set_drvdata(pdev, NULL);
9894
9895 return err;
9896}
9897
9898static void __devexit niu_pci_remove_one(struct pci_dev *pdev)
9899{
9900 struct net_device *dev = pci_get_drvdata(pdev);
9901
9902 if (dev) {
9903 struct niu *np = netdev_priv(dev);
9904
9905 unregister_netdev(dev);
9906 if (np->regs) {
9907 iounmap(np->regs);
9908 np->regs = NULL;
9909 }
9910
9911 niu_ldg_free(np);
9912
9913 niu_put_parent(np);
9914
9915 free_netdev(dev);
9916 pci_release_regions(pdev);
9917 pci_disable_device(pdev);
9918 pci_set_drvdata(pdev, NULL);
9919 }
9920}
9921
9922static int niu_suspend(struct pci_dev *pdev, pm_message_t state)
9923{
9924 struct net_device *dev = pci_get_drvdata(pdev);
9925 struct niu *np = netdev_priv(dev);
9926 unsigned long flags;
9927
9928 if (!netif_running(dev))
9929 return 0;
9930
9931 flush_scheduled_work();
9932 niu_netif_stop(np);
9933
9934 del_timer_sync(&np->timer);
9935
9936 spin_lock_irqsave(&np->lock, flags);
9937 niu_enable_interrupts(np, 0);
9938 spin_unlock_irqrestore(&np->lock, flags);
9939
9940 netif_device_detach(dev);
9941
9942 spin_lock_irqsave(&np->lock, flags);
9943 niu_stop_hw(np);
9944 spin_unlock_irqrestore(&np->lock, flags);
9945
9946 pci_save_state(pdev);
9947
9948 return 0;
9949}
9950
9951static int niu_resume(struct pci_dev *pdev)
9952{
9953 struct net_device *dev = pci_get_drvdata(pdev);
9954 struct niu *np = netdev_priv(dev);
9955 unsigned long flags;
9956 int err;
9957
9958 if (!netif_running(dev))
9959 return 0;
9960
9961 pci_restore_state(pdev);
9962
9963 netif_device_attach(dev);
9964
9965 spin_lock_irqsave(&np->lock, flags);
9966
9967 err = niu_init_hw(np);
9968 if (!err) {
9969 np->timer.expires = jiffies + HZ;
9970 add_timer(&np->timer);
9971 niu_netif_start(np);
9972 }
9973
9974 spin_unlock_irqrestore(&np->lock, flags);
9975
9976 return err;
9977}
9978
9979static struct pci_driver niu_pci_driver = {
9980 .name = DRV_MODULE_NAME,
9981 .id_table = niu_pci_tbl,
9982 .probe = niu_pci_init_one,
9983 .remove = __devexit_p(niu_pci_remove_one),
9984 .suspend = niu_suspend,
9985 .resume = niu_resume,
9986};
9987
9988#ifdef CONFIG_SPARC64
9989static void *niu_phys_alloc_coherent(struct device *dev, size_t size,
9990 u64 *dma_addr, gfp_t flag)
9991{
9992 unsigned long order = get_order(size);
9993 unsigned long page = __get_free_pages(flag, order);
9994
9995 if (page == 0UL)
9996 return NULL;
9997 memset((char *)page, 0, PAGE_SIZE << order);
9998 *dma_addr = __pa(page);
9999
10000 return (void *) page;
10001}
10002
10003static void niu_phys_free_coherent(struct device *dev, size_t size,
10004 void *cpu_addr, u64 handle)
10005{
10006 unsigned long order = get_order(size);
10007
10008 free_pages((unsigned long) cpu_addr, order);
10009}
10010
10011static u64 niu_phys_map_page(struct device *dev, struct page *page,
10012 unsigned long offset, size_t size,
10013 enum dma_data_direction direction)
10014{
10015 return page_to_phys(page) + offset;
10016}
10017
10018static void niu_phys_unmap_page(struct device *dev, u64 dma_address,
10019 size_t size, enum dma_data_direction direction)
10020{
10021 /* Nothing to do. */
10022}
10023
10024static u64 niu_phys_map_single(struct device *dev, void *cpu_addr,
10025 size_t size,
10026 enum dma_data_direction direction)
10027{
10028 return __pa(cpu_addr);
10029}
10030
10031static void niu_phys_unmap_single(struct device *dev, u64 dma_address,
10032 size_t size,
10033 enum dma_data_direction direction)
10034{
10035 /* Nothing to do. */
10036}
10037
10038static const struct niu_ops niu_phys_ops = {
10039 .alloc_coherent = niu_phys_alloc_coherent,
10040 .free_coherent = niu_phys_free_coherent,
10041 .map_page = niu_phys_map_page,
10042 .unmap_page = niu_phys_unmap_page,
10043 .map_single = niu_phys_map_single,
10044 .unmap_single = niu_phys_unmap_single,
10045};
10046
a3138df9
DM		 10047static int __devinit niu_of_probe(struct of_device *op,
10048 const struct of_device_id *match)
10049{
10050 union niu_parent_id parent_id;
10051 struct net_device *dev;
10052 struct niu *np;
10053 const u32 *reg;
10054 int err;
10055
10056 niu_driver_version();
10057
10058 reg = of_get_property(op->node, "reg", NULL);
10059 if (!reg) {
f10a1f2e 10060 dev_err(&op->dev, "%s: No 'reg' property, aborting\n",
a3138df9
DM		 10061 op->node->full_name);
10062 return -ENODEV;
10063 }
10064
10065 dev = niu_alloc_and_init(&op->dev, NULL, op,
10066 &niu_phys_ops, reg[0] & 0x1);
10067 if (!dev) {
10068 err = -ENOMEM;
10069 goto err_out;
10070 }
10071 np = netdev_priv(dev);
10072
10073 memset(&parent_id, 0, sizeof(parent_id));
10074 parent_id.of = of_get_parent(op->node);
10075
10076 np->parent = niu_get_parent(np, &parent_id,
10077 PLAT_TYPE_NIU);
10078 if (!np->parent) {
10079 err = -ENOMEM;
10080 goto err_out_free_dev;
10081 }
10082
10083 dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM);
10084
10085 np->regs = of_ioremap(&op->resource[1], 0,
6f0e0135 10086 resource_size(&op->resource[1]),
a3138df9
DM		 10087 "niu regs");
10088 if (!np->regs) {
f10a1f2e 10089 dev_err(&op->dev, "Cannot map device registers, aborting\n");
a3138df9
DM		 10090 err = -ENOMEM;
10091 goto err_out_release_parent;
10092 }
10093
10094 np->vir_regs_1 = of_ioremap(&op->resource[2], 0,
6f0e0135 10095 resource_size(&op->resource[2]),
a3138df9
DM		 10096 "niu vregs-1");
10097 if (!np->vir_regs_1) {
f10a1f2e 10098 dev_err(&op->dev, "Cannot map device vir registers 1, aborting\n");
a3138df9
DM		 10099 err = -ENOMEM;
10100 goto err_out_iounmap;
10101 }
10102
10103 np->vir_regs_2 = of_ioremap(&op->resource[3], 0,
6f0e0135 10104 resource_size(&op->resource[3]),
a3138df9
DM		 10105 "niu vregs-2");
10106 if (!np->vir_regs_2) {
f10a1f2e 10107 dev_err(&op->dev, "Cannot map device vir registers 2, aborting\n");
a3138df9
DM		 10108 err = -ENOMEM;
10109 goto err_out_iounmap;
10110 }
10111
10112 niu_assign_netdev_ops(dev);
10113
10114 err = niu_get_invariants(np);
10115 if (err) {
10116 if (err != -ENODEV)
f10a1f2e 10117 dev_err(&op->dev, "Problem fetching invariants of chip, aborting\n");
a3138df9
DM		 10118 goto err_out_iounmap;
10119 }
10120
10121 err = register_netdev(dev);
10122 if (err) {
f10a1f2e 10123 dev_err(&op->dev, "Cannot register net device, aborting\n");
a3138df9
DM		 10124 goto err_out_iounmap;
10125 }
10126
10127 dev_set_drvdata(&op->dev, dev);
10128
10129 niu_device_announce(np);
10130
10131 return 0;
10132
10133err_out_iounmap:
10134 if (np->vir_regs_1) {
10135 of_iounmap(&op->resource[2], np->vir_regs_1,
6f0e0135 10136 resource_size(&op->resource[2]));
a3138df9
DM		 10137 np->vir_regs_1 = NULL;
10138 }
10139
10140 if (np->vir_regs_2) {
10141 of_iounmap(&op->resource[3], np->vir_regs_2,
6f0e0135 10142 resource_size(&op->resource[3]));
a3138df9
DM		 10143 np->vir_regs_2 = NULL;
10144 }
10145
10146 if (np->regs) {
10147 of_iounmap(&op->resource[1], np->regs,
6f0e0135 10148 resource_size(&op->resource[1]));
a3138df9
DM		 10149 np->regs = NULL;
10150 }
10151
10152err_out_release_parent:
10153 niu_put_parent(np);
10154
10155err_out_free_dev:
10156 free_netdev(dev);
10157
10158err_out:
10159 return err;
10160}
10161
10162static int __devexit niu_of_remove(struct of_device *op)
10163{
10164 struct net_device *dev = dev_get_drvdata(&op->dev);
10165
10166 if (dev) {
10167 struct niu *np = netdev_priv(dev);
10168
10169 unregister_netdev(dev);
10170
10171 if (np->vir_regs_1) {
10172 of_iounmap(&op->resource[2], np->vir_regs_1,
6f0e0135 10173 resource_size(&op->resource[2]));
a3138df9
DM		 10174 np->vir_regs_1 = NULL;
10175 }
10176
10177 if (np->vir_regs_2) {
10178 of_iounmap(&op->resource[3], np->vir_regs_2,
6f0e0135 10179 resource_size(&op->resource[3]));
a3138df9
DM		 10180 np->vir_regs_2 = NULL;
10181 }
10182
10183 if (np->regs) {
10184 of_iounmap(&op->resource[1], np->regs,
6f0e0135 10185 resource_size(&op->resource[1]));
a3138df9
DM		 10186 np->regs = NULL;
10187 }
10188
10189 niu_ldg_free(np);
10190
10191 niu_put_parent(np);
10192
10193 free_netdev(dev);
10194 dev_set_drvdata(&op->dev, NULL);
10195 }
10196 return 0;
10197}
10198
fd098316 10199static const struct of_device_id niu_match[] = {
a3138df9
DM		 10200 {
10201 .name = "network",
10202 .compatible = "SUNW,niusl",
10203 },
10204 {},
10205};
10206MODULE_DEVICE_TABLE(of, niu_match);
10207
10208static struct of_platform_driver niu_of_driver = {
10209 .name = "niu",
10210 .match_table = niu_match,
10211 .probe = niu_of_probe,
10212 .remove = __devexit_p(niu_of_remove),
10213};
10214
10215#endif /* CONFIG_SPARC64 */
10216
10217static int __init niu_init(void)
10218{
10219 int err = 0;
10220
81429973 10221 BUILD_BUG_ON(PAGE_SIZE < 4 * 1024);
a3138df9
DM		 10222
10223 niu_debug = netif_msg_init(debug, NIU_MSG_DEFAULT);
10224
10225#ifdef CONFIG_SPARC64
10226 err = of_register_driver(&niu_of_driver, &of_bus_type);
10227#endif
10228
10229 if (!err) {
10230 err = pci_register_driver(&niu_pci_driver);
10231#ifdef CONFIG_SPARC64
10232 if (err)
10233 of_unregister_driver(&niu_of_driver);
10234#endif
10235 }
10236
10237 return err;
10238}
10239
10240static void __exit niu_exit(void)
10241{
10242 pci_unregister_driver(&niu_pci_driver);
10243#ifdef CONFIG_SPARC64
10244 of_unregister_driver(&niu_of_driver);
10245#endif
10246}
10247
10248module_init(niu_init);
10249module_exit(niu_exit);
Linux 6.x block layer and io_uring tree(s)