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niu: Determine the # of ports from the card's VPD data
[linux-2.6-block.git] / drivers / net / niu.c
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a3138df9
DM		 1/* niu.c: Neptune ethernet driver.
2 *
3 * Copyright (C) 2007 David S. Miller (davem@davemloft.net)
4 */
5
6#include <linux/module.h>
7#include <linux/init.h>
8#include <linux/pci.h>
9#include <linux/dma-mapping.h>
10#include <linux/netdevice.h>
11#include <linux/ethtool.h>
12#include <linux/etherdevice.h>
13#include <linux/platform_device.h>
14#include <linux/delay.h>
15#include <linux/bitops.h>
16#include <linux/mii.h>
17#include <linux/if_ether.h>
18#include <linux/if_vlan.h>
19#include <linux/ip.h>
20#include <linux/in.h>
21#include <linux/ipv6.h>
22#include <linux/log2.h>
23#include <linux/jiffies.h>
24#include <linux/crc32.h>
25
26#include <linux/io.h>
27
28#ifdef CONFIG_SPARC64
29#include <linux/of_device.h>
30#endif
31
32#include "niu.h"
33
34#define DRV_MODULE_NAME "niu"
35#define PFX DRV_MODULE_NAME ": "
a4425859
DM		 36#define DRV_MODULE_VERSION "0.7"
37#define DRV_MODULE_RELDATE "February 18, 2008"
a3138df9
DM		 38
39static char version[] __devinitdata =
40 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
41
42MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
43MODULE_DESCRIPTION("NIU ethernet driver");
44MODULE_LICENSE("GPL");
45MODULE_VERSION(DRV_MODULE_VERSION);
46
47#ifndef DMA_44BIT_MASK
48#define DMA_44BIT_MASK 0x00000fffffffffffULL
49#endif
50
51#ifndef readq
52static u64 readq(void __iomem *reg)
53{
54 return (((u64)readl(reg + 0x4UL) << 32) |
55 (u64)readl(reg));
56}
57
58static void writeq(u64 val, void __iomem *reg)
59{
60 writel(val & 0xffffffff, reg);
61 writel(val >> 32, reg + 0x4UL);
62}
63#endif
64
65static struct pci_device_id niu_pci_tbl[] = {
66 {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)},
67 {}
68};
69
70MODULE_DEVICE_TABLE(pci, niu_pci_tbl);
71
72#define NIU_TX_TIMEOUT (5 * HZ)
73
74#define nr64(reg) readq(np->regs + (reg))
75#define nw64(reg, val) writeq((val), np->regs + (reg))
76
77#define nr64_mac(reg) readq(np->mac_regs + (reg))
78#define nw64_mac(reg, val) writeq((val), np->mac_regs + (reg))
79
80#define nr64_ipp(reg) readq(np->regs + np->ipp_off + (reg))
81#define nw64_ipp(reg, val) writeq((val), np->regs + np->ipp_off + (reg))
82
83#define nr64_pcs(reg) readq(np->regs + np->pcs_off + (reg))
84#define nw64_pcs(reg, val) writeq((val), np->regs + np->pcs_off + (reg))
85
86#define nr64_xpcs(reg) readq(np->regs + np->xpcs_off + (reg))
87#define nw64_xpcs(reg, val) writeq((val), np->regs + np->xpcs_off + (reg))
88
89#define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
90
91static int niu_debug;
92static int debug = -1;
93module_param(debug, int, 0);
94MODULE_PARM_DESC(debug, "NIU debug level");
95
96#define niudbg(TYPE, f, a...) \
97do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \
98 printk(KERN_DEBUG PFX f, ## a); \
99} while (0)
100
101#define niuinfo(TYPE, f, a...) \
102do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \
103 printk(KERN_INFO PFX f, ## a); \
104} while (0)
105
106#define niuwarn(TYPE, f, a...) \
107do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \
108 printk(KERN_WARNING PFX f, ## a); \
109} while (0)
110
111#define niu_lock_parent(np, flags) \
112 spin_lock_irqsave(&np->parent->lock, flags)
113#define niu_unlock_parent(np, flags) \
114 spin_unlock_irqrestore(&np->parent->lock, flags)
115
5fbd7e24
MW		 116static int serdes_init_10g_serdes(struct niu *np);
117
a3138df9
DM		 118static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg,
119 u64 bits, int limit, int delay)
120{
121 while (--limit >= 0) {
122 u64 val = nr64_mac(reg);
123
124 if (!(val & bits))
125 break;
126 udelay(delay);
127 }
128 if (limit < 0)
129 return -ENODEV;
130 return 0;
131}
132
133static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg,
134 u64 bits, int limit, int delay,
135 const char *reg_name)
136{
137 int err;
138
139 nw64_mac(reg, bits);
140 err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay);
141 if (err)
142 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
143 "would not clear, val[%llx]\n",
144 np->dev->name, (unsigned long long) bits, reg_name,
145 (unsigned long long) nr64_mac(reg));
146 return err;
147}
148
149#define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
150({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
151 __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
152})
153
154static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg,
155 u64 bits, int limit, int delay)
156{
157 while (--limit >= 0) {
158 u64 val = nr64_ipp(reg);
159
160 if (!(val & bits))
161 break;
162 udelay(delay);
163 }
164 if (limit < 0)
165 return -ENODEV;
166 return 0;
167}
168
169static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg,
170 u64 bits, int limit, int delay,
171 const char *reg_name)
172{
173 int err;
174 u64 val;
175
176 val = nr64_ipp(reg);
177 val |= bits;
178 nw64_ipp(reg, val);
179
180 err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay);
181 if (err)
182 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
183 "would not clear, val[%llx]\n",
184 np->dev->name, (unsigned long long) bits, reg_name,
185 (unsigned long long) nr64_ipp(reg));
186 return err;
187}
188
189#define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
190({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
191 __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
192})
193
194static int __niu_wait_bits_clear(struct niu *np, unsigned long reg,
195 u64 bits, int limit, int delay)
196{
197 while (--limit >= 0) {
198 u64 val = nr64(reg);
199
200 if (!(val & bits))
201 break;
202 udelay(delay);
203 }
204 if (limit < 0)
205 return -ENODEV;
206 return 0;
207}
208
209#define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
210({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
211 __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
212})
213
214static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg,
215 u64 bits, int limit, int delay,
216 const char *reg_name)
217{
218 int err;
219
220 nw64(reg, bits);
221 err = __niu_wait_bits_clear(np, reg, bits, limit, delay);
222 if (err)
223 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
224 "would not clear, val[%llx]\n",
225 np->dev->name, (unsigned long long) bits, reg_name,
226 (unsigned long long) nr64(reg));
227 return err;
228}
229
230#define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
231({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
232 __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
233})
234
235static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on)
236{
237 u64 val = (u64) lp->timer;
238
239 if (on)
240 val |= LDG_IMGMT_ARM;
241
242 nw64(LDG_IMGMT(lp->ldg_num), val);
243}
244
245static int niu_ldn_irq_enable(struct niu *np, int ldn, int on)
246{
247 unsigned long mask_reg, bits;
248 u64 val;
249
250 if (ldn < 0 || ldn > LDN_MAX)
251 return -EINVAL;
252
253 if (ldn < 64) {
254 mask_reg = LD_IM0(ldn);
255 bits = LD_IM0_MASK;
256 } else {
257 mask_reg = LD_IM1(ldn - 64);
258 bits = LD_IM1_MASK;
259 }
260
261 val = nr64(mask_reg);
262 if (on)
263 val &= ~bits;
264 else
265 val |= bits;
266 nw64(mask_reg, val);
267
268 return 0;
269}
270
271static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on)
272{
273 struct niu_parent *parent = np->parent;
274 int i;
275
276 for (i = 0; i <= LDN_MAX; i++) {
277 int err;
278
279 if (parent->ldg_map[i] != lp->ldg_num)
280 continue;
281
282 err = niu_ldn_irq_enable(np, i, on);
283 if (err)
284 return err;
285 }
286 return 0;
287}
288
289static int niu_enable_interrupts(struct niu *np, int on)
290{
291 int i;
292
293 for (i = 0; i < np->num_ldg; i++) {
294 struct niu_ldg *lp = &np->ldg[i];
295 int err;
296
297 err = niu_enable_ldn_in_ldg(np, lp, on);
298 if (err)
299 return err;
300 }
301 for (i = 0; i < np->num_ldg; i++)
302 niu_ldg_rearm(np, &np->ldg[i], on);
303
304 return 0;
305}
306
307static u32 phy_encode(u32 type, int port)
308{
309 return (type << (port * 2));
310}
311
312static u32 phy_decode(u32 val, int port)
313{
314 return (val >> (port * 2)) & PORT_TYPE_MASK;
315}
316
317static int mdio_wait(struct niu *np)
318{
319 int limit = 1000;
320 u64 val;
321
322 while (--limit > 0) {
323 val = nr64(MIF_FRAME_OUTPUT);
324 if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1)
325 return val & MIF_FRAME_OUTPUT_DATA;
326
327 udelay(10);
328 }
329
330 return -ENODEV;
331}
332
333static int mdio_read(struct niu *np, int port, int dev, int reg)
334{
335 int err;
336
337 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
338 err = mdio_wait(np);
339 if (err < 0)
340 return err;
341
342 nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev));
343 return mdio_wait(np);
344}
345
346static int mdio_write(struct niu *np, int port, int dev, int reg, int data)
347{
348 int err;
349
350 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
351 err = mdio_wait(np);
352 if (err < 0)
353 return err;
354
355 nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data));
356 err = mdio_wait(np);
357 if (err < 0)
358 return err;
359
360 return 0;
361}
362
363static int mii_read(struct niu *np, int port, int reg)
364{
365 nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg));
366 return mdio_wait(np);
367}
368
369static int mii_write(struct niu *np, int port, int reg, int data)
370{
371 int err;
372
373 nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data));
374 err = mdio_wait(np);
375 if (err < 0)
376 return err;
377
378 return 0;
379}
380
381static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val)
382{
383 int err;
384
385 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
386 ESR2_TI_PLL_TX_CFG_L(channel),
387 val & 0xffff);
388 if (!err)
389 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
390 ESR2_TI_PLL_TX_CFG_H(channel),
391 val >> 16);
392 return err;
393}
394
395static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val)
396{
397 int err;
398
399 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
400 ESR2_TI_PLL_RX_CFG_L(channel),
401 val & 0xffff);
402 if (!err)
403 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
404 ESR2_TI_PLL_RX_CFG_H(channel),
405 val >> 16);
406 return err;
407}
408
409/* Mode is always 10G fiber. */
410static int serdes_init_niu(struct niu *np)
411{
412 struct niu_link_config *lp = &np->link_config;
413 u32 tx_cfg, rx_cfg;
414 unsigned long i;
415
416 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
417 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
418 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
419 PLL_RX_CFG_EQ_LP_ADAPTIVE);
420
421 if (lp->loopback_mode == LOOPBACK_PHY) {
422 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
423
424 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
425 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
426
427 tx_cfg |= PLL_TX_CFG_ENTEST;
428 rx_cfg |= PLL_RX_CFG_ENTEST;
429 }
430
431 /* Initialize all 4 lanes of the SERDES. */
432 for (i = 0; i < 4; i++) {
433 int err = esr2_set_tx_cfg(np, i, tx_cfg);
434 if (err)
435 return err;
436 }
437
438 for (i = 0; i < 4; i++) {
439 int err = esr2_set_rx_cfg(np, i, rx_cfg);
440 if (err)
441 return err;
442 }
443
444 return 0;
445}
446
447static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val)
448{
449 int err;
450
451 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan));
452 if (err >= 0) {
453 *val = (err & 0xffff);
454 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
455 ESR_RXTX_CTRL_H(chan));
456 if (err >= 0)
457 *val |= ((err & 0xffff) << 16);
458 err = 0;
459 }
460 return err;
461}
462
463static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val)
464{
465 int err;
466
467 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
468 ESR_GLUE_CTRL0_L(chan));
469 if (err >= 0) {
470 *val = (err & 0xffff);
471 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
472 ESR_GLUE_CTRL0_H(chan));
473 if (err >= 0) {
474 *val |= ((err & 0xffff) << 16);
475 err = 0;
476 }
477 }
478 return err;
479}
480
481static int esr_read_reset(struct niu *np, u32 *val)
482{
483 int err;
484
485 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
486 ESR_RXTX_RESET_CTRL_L);
487 if (err >= 0) {
488 *val = (err & 0xffff);
489 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
490 ESR_RXTX_RESET_CTRL_H);
491 if (err >= 0) {
492 *val |= ((err & 0xffff) << 16);
493 err = 0;
494 }
495 }
496 return err;
497}
498
499static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val)
500{
501 int err;
502
503 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
504 ESR_RXTX_CTRL_L(chan), val & 0xffff);
505 if (!err)
506 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
507 ESR_RXTX_CTRL_H(chan), (val >> 16));
508 return err;
509}
510
511static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val)
512{
513 int err;
514
515 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
516 ESR_GLUE_CTRL0_L(chan), val & 0xffff);
517 if (!err)
518 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
519 ESR_GLUE_CTRL0_H(chan), (val >> 16));
520 return err;
521}
522
523static int esr_reset(struct niu *np)
524{
525 u32 reset;
526 int err;
527
528 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
529 ESR_RXTX_RESET_CTRL_L, 0x0000);
530 if (err)
531 return err;
532 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
533 ESR_RXTX_RESET_CTRL_H, 0xffff);
534 if (err)
535 return err;
536 udelay(200);
537
538 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
539 ESR_RXTX_RESET_CTRL_L, 0xffff);
540 if (err)
541 return err;
542 udelay(200);
543
544 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
545 ESR_RXTX_RESET_CTRL_H, 0x0000);
546 if (err)
547 return err;
548 udelay(200);
549
550 err = esr_read_reset(np, &reset);
551 if (err)
552 return err;
553 if (reset != 0) {
554 dev_err(np->device, PFX "Port %u ESR_RESET "
555 "did not clear [%08x]\n",
556 np->port, reset);
557 return -ENODEV;
558 }
559
560 return 0;
561}
562
563static int serdes_init_10g(struct niu *np)
564{
565 struct niu_link_config *lp = &np->link_config;
566 unsigned long ctrl_reg, test_cfg_reg, i;
567 u64 ctrl_val, test_cfg_val, sig, mask, val;
568 int err;
569
570 switch (np->port) {
571 case 0:
572 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
573 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
574 break;
575 case 1:
576 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
577 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
578 break;
579
580 default:
581 return -EINVAL;
582 }
583 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
584 ENET_SERDES_CTRL_SDET_1 |
585 ENET_SERDES_CTRL_SDET_2 |
586 ENET_SERDES_CTRL_SDET_3 |
587 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
588 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
589 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
590 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
591 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
592 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
593 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
594 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
595 test_cfg_val = 0;
596
597 if (lp->loopback_mode == LOOPBACK_PHY) {
598 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
599 ENET_SERDES_TEST_MD_0_SHIFT) |
600 (ENET_TEST_MD_PAD_LOOPBACK <<
601 ENET_SERDES_TEST_MD_1_SHIFT) |
602 (ENET_TEST_MD_PAD_LOOPBACK <<
603 ENET_SERDES_TEST_MD_2_SHIFT) |
604 (ENET_TEST_MD_PAD_LOOPBACK <<
605 ENET_SERDES_TEST_MD_3_SHIFT));
606 }
607
608 nw64(ctrl_reg, ctrl_val);
609 nw64(test_cfg_reg, test_cfg_val);
610
611 /* Initialize all 4 lanes of the SERDES. */
612 for (i = 0; i < 4; i++) {
613 u32 rxtx_ctrl, glue0;
614
615 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
616 if (err)
617 return err;
618 err = esr_read_glue0(np, i, &glue0);
619 if (err)
620 return err;
621
622 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
623 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
624 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
625
626 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
627 ESR_GLUE_CTRL0_THCNT |
628 ESR_GLUE_CTRL0_BLTIME);
629 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
630 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
631 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
632 (BLTIME_300_CYCLES <<
633 ESR_GLUE_CTRL0_BLTIME_SHIFT));
634
635 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
636 if (err)
637 return err;
638 err = esr_write_glue0(np, i, glue0);
639 if (err)
640 return err;
641 }
642
643 err = esr_reset(np);
644 if (err)
645 return err;
646
647 sig = nr64(ESR_INT_SIGNALS);
648 switch (np->port) {
649 case 0:
650 mask = ESR_INT_SIGNALS_P0_BITS;
651 val = (ESR_INT_SRDY0_P0 |
652 ESR_INT_DET0_P0 |
653 ESR_INT_XSRDY_P0 |
654 ESR_INT_XDP_P0_CH3 |
655 ESR_INT_XDP_P0_CH2 |
656 ESR_INT_XDP_P0_CH1 |
657 ESR_INT_XDP_P0_CH0);
658 break;
659
660 case 1:
661 mask = ESR_INT_SIGNALS_P1_BITS;
662 val = (ESR_INT_SRDY0_P1 |
663 ESR_INT_DET0_P1 |
664 ESR_INT_XSRDY_P1 |
665 ESR_INT_XDP_P1_CH3 |
666 ESR_INT_XDP_P1_CH2 |
667 ESR_INT_XDP_P1_CH1 |
668 ESR_INT_XDP_P1_CH0);
669 break;
670
671 default:
672 return -EINVAL;
673 }
674
675 if ((sig & mask) != val) {
676 dev_err(np->device, PFX "Port %u signal bits [%08x] are not "
677 "[%08x]\n", np->port, (int) (sig & mask), (int) val);
678 return -ENODEV;
679 }
680
681 return 0;
682}
683
684static int serdes_init_1g(struct niu *np)
685{
686 u64 val;
687
688 val = nr64(ENET_SERDES_1_PLL_CFG);
689 val &= ~ENET_SERDES_PLL_FBDIV2;
690 switch (np->port) {
691 case 0:
692 val |= ENET_SERDES_PLL_HRATE0;
693 break;
694 case 1:
695 val |= ENET_SERDES_PLL_HRATE1;
696 break;
697 case 2:
698 val |= ENET_SERDES_PLL_HRATE2;
699 break;
700 case 3:
701 val |= ENET_SERDES_PLL_HRATE3;
702 break;
703 default:
704 return -EINVAL;
705 }
706 nw64(ENET_SERDES_1_PLL_CFG, val);
707
708 return 0;
709}
710
5fbd7e24
MW		 711static int serdes_init_1g_serdes(struct niu *np)
712{
713 struct niu_link_config *lp = &np->link_config;
714 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
715 u64 ctrl_val, test_cfg_val, sig, mask, val;
716 int err;
717 u64 reset_val, val_rd;
718
719 val = ENET_SERDES_PLL_HRATE0 | ENET_SERDES_PLL_HRATE1 |
720 ENET_SERDES_PLL_HRATE2 | ENET_SERDES_PLL_HRATE3 |
721 ENET_SERDES_PLL_FBDIV0;
722 switch (np->port) {
723 case 0:
724 reset_val = ENET_SERDES_RESET_0;
725 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
726 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
727 pll_cfg = ENET_SERDES_0_PLL_CFG;
728 break;
729 case 1:
730 reset_val = ENET_SERDES_RESET_1;
731 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
732 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
733 pll_cfg = ENET_SERDES_1_PLL_CFG;
734 break;
735
736 default:
737 return -EINVAL;
738 }
739 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
740 ENET_SERDES_CTRL_SDET_1 |
741 ENET_SERDES_CTRL_SDET_2 |
742 ENET_SERDES_CTRL_SDET_3 |
743 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
744 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
745 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
746 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
747 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
748 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
749 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
750 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
751 test_cfg_val = 0;
752
753 if (lp->loopback_mode == LOOPBACK_PHY) {
754 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
755 ENET_SERDES_TEST_MD_0_SHIFT) |
756 (ENET_TEST_MD_PAD_LOOPBACK <<
757 ENET_SERDES_TEST_MD_1_SHIFT) |
758 (ENET_TEST_MD_PAD_LOOPBACK <<
759 ENET_SERDES_TEST_MD_2_SHIFT) |
760 (ENET_TEST_MD_PAD_LOOPBACK <<
761 ENET_SERDES_TEST_MD_3_SHIFT));
762 }
763
764 nw64(ENET_SERDES_RESET, reset_val);
765 mdelay(20);
766 val_rd = nr64(ENET_SERDES_RESET);
767 val_rd &= ~reset_val;
768 nw64(pll_cfg, val);
769 nw64(ctrl_reg, ctrl_val);
770 nw64(test_cfg_reg, test_cfg_val);
771 nw64(ENET_SERDES_RESET, val_rd);
772 mdelay(2000);
773
774 /* Initialize all 4 lanes of the SERDES. */
775 for (i = 0; i < 4; i++) {
776 u32 rxtx_ctrl, glue0;
777
778 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
779 if (err)
780 return err;
781 err = esr_read_glue0(np, i, &glue0);
782 if (err)
783 return err;
784
785 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
786 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
787 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
788
789 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
790 ESR_GLUE_CTRL0_THCNT |
791 ESR_GLUE_CTRL0_BLTIME);
792 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
793 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
794 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
795 (BLTIME_300_CYCLES <<
796 ESR_GLUE_CTRL0_BLTIME_SHIFT));
797
798 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
799 if (err)
800 return err;
801 err = esr_write_glue0(np, i, glue0);
802 if (err)
803 return err;
804 }
805
806
807 sig = nr64(ESR_INT_SIGNALS);
808 switch (np->port) {
809 case 0:
810 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
811 mask = val;
812 break;
813
814 case 1:
815 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
816 mask = val;
817 break;
818
819 default:
820 return -EINVAL;
821 }
822
823 if ((sig & mask) != val) {
824 dev_err(np->device, PFX "Port %u signal bits [%08x] are not "
825 "[%08x]\n", np->port, (int) (sig & mask), (int) val);
826 return -ENODEV;
827 }
828
829 return 0;
830}
831
832static int link_status_1g_serdes(struct niu *np, int *link_up_p)
833{
834 struct niu_link_config *lp = &np->link_config;
835 int link_up;
836 u64 val;
837 u16 current_speed;
838 unsigned long flags;
839 u8 current_duplex;
840
841 link_up = 0;
842 current_speed = SPEED_INVALID;
843 current_duplex = DUPLEX_INVALID;
844
845 spin_lock_irqsave(&np->lock, flags);
846
847 val = nr64_pcs(PCS_MII_STAT);
848
849 if (val & PCS_MII_STAT_LINK_STATUS) {
850 link_up = 1;
851 current_speed = SPEED_1000;
852 current_duplex = DUPLEX_FULL;
853 }
854
855 lp->active_speed = current_speed;
856 lp->active_duplex = current_duplex;
857 spin_unlock_irqrestore(&np->lock, flags);
858
859 *link_up_p = link_up;
860 return 0;
861}
862
863
864static int link_status_10g_serdes(struct niu *np, int *link_up_p)
865{
866 unsigned long flags;
867 struct niu_link_config *lp = &np->link_config;
868 int link_up = 0;
869 int link_ok = 1;
870 u64 val, val2;
871 u16 current_speed;
872 u8 current_duplex;
873
874 if (!(np->flags & NIU_FLAGS_10G))
875 return link_status_1g_serdes(np, link_up_p);
876
877 current_speed = SPEED_INVALID;
878 current_duplex = DUPLEX_INVALID;
879 spin_lock_irqsave(&np->lock, flags);
880
881 val = nr64_xpcs(XPCS_STATUS(0));
882 val2 = nr64_mac(XMAC_INTER2);
883 if (val2 & 0x01000000)
884 link_ok = 0;
885
886 if ((val & 0x1000ULL) && link_ok) {
887 link_up = 1;
888 current_speed = SPEED_10000;
889 current_duplex = DUPLEX_FULL;
890 }
891 lp->active_speed = current_speed;
892 lp->active_duplex = current_duplex;
893 spin_unlock_irqrestore(&np->lock, flags);
894 *link_up_p = link_up;
895 return 0;
896}
897
898
899static int link_status_1g_rgmii(struct niu *np, int *link_up_p)
900{
901 struct niu_link_config *lp = &np->link_config;
902 u16 current_speed, bmsr;
903 unsigned long flags;
904 u8 current_duplex;
905 int err, link_up;
906
907 link_up = 0;
908 current_speed = SPEED_INVALID;
909 current_duplex = DUPLEX_INVALID;
910
911 spin_lock_irqsave(&np->lock, flags);
912
913 err = -EINVAL;
914
915 err = mii_read(np, np->phy_addr, MII_BMSR);
916 if (err < 0)
917 goto out;
918
919 bmsr = err;
920 if (bmsr & BMSR_LSTATUS) {
921 u16 adv, lpa, common, estat;
922
923 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
924 if (err < 0)
925 goto out;
926 adv = err;
927
928 err = mii_read(np, np->phy_addr, MII_LPA);
929 if (err < 0)
930 goto out;
931 lpa = err;
932
933 common = adv & lpa;
934
935 err = mii_read(np, np->phy_addr, MII_ESTATUS);
936 if (err < 0)
937 goto out;
938 estat = err;
939 link_up = 1;
940 current_speed = SPEED_1000;
941 current_duplex = DUPLEX_FULL;
942
943 }
944 lp->active_speed = current_speed;
945 lp->active_duplex = current_duplex;
946 err = 0;
947
948out:
949 spin_unlock_irqrestore(&np->lock, flags);
950
951 *link_up_p = link_up;
952 return err;
953}
954
955
a3138df9
DM		 956static int bcm8704_reset(struct niu *np)
957{
958 int err, limit;
959
960 err = mdio_read(np, np->phy_addr,
961 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
962 if (err < 0)
963 return err;
964 err |= BMCR_RESET;
965 err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
966 MII_BMCR, err);
967 if (err)
968 return err;
969
970 limit = 1000;
971 while (--limit >= 0) {
972 err = mdio_read(np, np->phy_addr,
973 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
974 if (err < 0)
975 return err;
976 if (!(err & BMCR_RESET))
977 break;
978 }
979 if (limit < 0) {
980 dev_err(np->device, PFX "Port %u PHY will not reset "
981 "(bmcr=%04x)\n", np->port, (err & 0xffff));
982 return -ENODEV;
983 }
984 return 0;
985}
986
987/* When written, certain PHY registers need to be read back twice
988 * in order for the bits to settle properly.
989 */
990static int bcm8704_user_dev3_readback(struct niu *np, int reg)
991{
992 int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
993 if (err < 0)
994 return err;
995 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
996 if (err < 0)
997 return err;
998 return 0;
999}
1000
1001static int bcm8704_init_user_dev3(struct niu *np)
1002{
1003 int err;
1004
1005 err = mdio_write(np, np->phy_addr,
1006 BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL,
1007 (USER_CONTROL_OPTXRST_LVL |
1008 USER_CONTROL_OPBIASFLT_LVL |
1009 USER_CONTROL_OBTMPFLT_LVL |
1010 USER_CONTROL_OPPRFLT_LVL |
1011 USER_CONTROL_OPTXFLT_LVL |
1012 USER_CONTROL_OPRXLOS_LVL |
1013 USER_CONTROL_OPRXFLT_LVL |
1014 USER_CONTROL_OPTXON_LVL |
1015 (0x3f << USER_CONTROL_RES1_SHIFT)));
1016 if (err)
1017 return err;
1018
1019 err = mdio_write(np, np->phy_addr,
1020 BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL,
1021 (USER_PMD_TX_CTL_XFP_CLKEN |
1022 (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) |
1023 (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) |
1024 USER_PMD_TX_CTL_TSCK_LPWREN));
1025 if (err)
1026 return err;
1027
1028 err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL);
1029 if (err)
1030 return err;
1031 err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL);
1032 if (err)
1033 return err;
1034
1035 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1036 BCM8704_USER_OPT_DIGITAL_CTRL);
1037 if (err < 0)
1038 return err;
1039 err &= ~USER_ODIG_CTRL_GPIOS;
1040 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1041 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1042 BCM8704_USER_OPT_DIGITAL_CTRL, err);
1043 if (err)
1044 return err;
1045
1046 mdelay(1000);
1047
1048 return 0;
1049}
1050
b0de8e40
ML		 1051static int mrvl88x2011_act_led(struct niu *np, int val)
1052{
1053 int err;
1054
1055 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1056 MRVL88X2011_LED_8_TO_11_CTL);
1057 if (err < 0)
1058 return err;
1059
1060 err &= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT,MRVL88X2011_LED_CTL_MASK);
1061 err |= MRVL88X2011_LED(MRVL88X2011_LED_ACT,val);
1062
1063 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1064 MRVL88X2011_LED_8_TO_11_CTL, err);
1065}
1066
1067static int mrvl88x2011_led_blink_rate(struct niu *np, int rate)
1068{
1069 int err;
1070
1071 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1072 MRVL88X2011_LED_BLINK_CTL);
1073 if (err >= 0) {
1074 err &= ~MRVL88X2011_LED_BLKRATE_MASK;
1075 err |= (rate << 4);
1076
1077 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1078 MRVL88X2011_LED_BLINK_CTL, err);
1079 }
1080
1081 return err;
1082}
1083
1084static int xcvr_init_10g_mrvl88x2011(struct niu *np)
1085{
1086 int err;
1087
1088 /* Set LED functions */
1089 err = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS);
1090 if (err)
1091 return err;
1092
1093 /* led activity */
1094 err = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF);
1095 if (err)
1096 return err;
1097
1098 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1099 MRVL88X2011_GENERAL_CTL);
1100 if (err < 0)
1101 return err;
1102
1103 err |= MRVL88X2011_ENA_XFPREFCLK;
1104
1105 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1106 MRVL88X2011_GENERAL_CTL, err);
1107 if (err < 0)
1108 return err;
1109
1110 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1111 MRVL88X2011_PMA_PMD_CTL_1);
1112 if (err < 0)
1113 return err;
1114
1115 if (np->link_config.loopback_mode == LOOPBACK_MAC)
1116 err |= MRVL88X2011_LOOPBACK;
1117 else
1118 err &= ~MRVL88X2011_LOOPBACK;
1119
1120 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1121 MRVL88X2011_PMA_PMD_CTL_1, err);
1122 if (err < 0)
1123 return err;
1124
1125 /* Enable PMD */
1126 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1127 MRVL88X2011_10G_PMD_TX_DIS, MRVL88X2011_ENA_PMDTX);
1128}
1129
1130static int xcvr_init_10g_bcm8704(struct niu *np)
a3138df9
DM		 1131{
1132 struct niu_link_config *lp = &np->link_config;
1133 u16 analog_stat0, tx_alarm_status;
1134 int err;
a3138df9
DM		 1135
1136 err = bcm8704_reset(np);
1137 if (err)
1138 return err;
1139
1140 err = bcm8704_init_user_dev3(np);
1141 if (err)
1142 return err;
1143
1144 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1145 MII_BMCR);
1146 if (err < 0)
1147 return err;
1148 err &= ~BMCR_LOOPBACK;
1149
1150 if (lp->loopback_mode == LOOPBACK_MAC)
1151 err |= BMCR_LOOPBACK;
1152
1153 err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1154 MII_BMCR, err);
1155 if (err)
1156 return err;
1157
1158#if 1
1159 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1160 MII_STAT1000);
1161 if (err < 0)
1162 return err;
1163 pr_info(PFX "Port %u PMA_PMD(MII_STAT1000) [%04x]\n",
1164 np->port, err);
1165
1166 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20);
1167 if (err < 0)
1168 return err;
1169 pr_info(PFX "Port %u USER_DEV3(0x20) [%04x]\n",
1170 np->port, err);
1171
1172 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1173 MII_NWAYTEST);
1174 if (err < 0)
1175 return err;
1176 pr_info(PFX "Port %u PHYXS(MII_NWAYTEST) [%04x]\n",
1177 np->port, err);
1178#endif
1179
1180 /* XXX dig this out it might not be so useful XXX */
1181 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1182 BCM8704_USER_ANALOG_STATUS0);
1183 if (err < 0)
1184 return err;
1185 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1186 BCM8704_USER_ANALOG_STATUS0);
1187 if (err < 0)
1188 return err;
1189 analog_stat0 = err;
1190
1191 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1192 BCM8704_USER_TX_ALARM_STATUS);
1193 if (err < 0)
1194 return err;
1195 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1196 BCM8704_USER_TX_ALARM_STATUS);
1197 if (err < 0)
1198 return err;
1199 tx_alarm_status = err;
1200
1201 if (analog_stat0 != 0x03fc) {
1202 if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) {
1203 pr_info(PFX "Port %u cable not connected "
1204 "or bad cable.\n", np->port);
1205 } else if (analog_stat0 == 0x639c) {
1206 pr_info(PFX "Port %u optical module is bad "
1207 "or missing.\n", np->port);
1208 }
1209 }
1210
1211 return 0;
1212}
1213
b0de8e40
ML		 1214static int xcvr_init_10g(struct niu *np)
1215{
1216 int phy_id, err;
1217 u64 val;
1218
1219 val = nr64_mac(XMAC_CONFIG);
1220 val &= ~XMAC_CONFIG_LED_POLARITY;
1221 val |= XMAC_CONFIG_FORCE_LED_ON;
1222 nw64_mac(XMAC_CONFIG, val);
1223
1224 /* XXX shared resource, lock parent XXX */
1225 val = nr64(MIF_CONFIG);
1226 val |= MIF_CONFIG_INDIRECT_MODE;
1227 nw64(MIF_CONFIG, val);
1228
1229 phy_id = phy_decode(np->parent->port_phy, np->port);
1230 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
1231
1232 /* handle different phy types */
1233 switch (phy_id & NIU_PHY_ID_MASK) {
1234 case NIU_PHY_ID_MRVL88X2011:
1235 err = xcvr_init_10g_mrvl88x2011(np);
1236 break;
1237
1238 default: /* bcom 8704 */
1239 err = xcvr_init_10g_bcm8704(np);
1240 break;
1241 }
1242
1243 return 0;
1244}
1245
a3138df9
DM		 1246static int mii_reset(struct niu *np)
1247{
1248 int limit, err;
1249
1250 err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET);
1251 if (err)
1252 return err;
1253
1254 limit = 1000;
1255 while (--limit >= 0) {
1256 udelay(500);
1257 err = mii_read(np, np->phy_addr, MII_BMCR);
1258 if (err < 0)
1259 return err;
1260 if (!(err & BMCR_RESET))
1261 break;
1262 }
1263 if (limit < 0) {
1264 dev_err(np->device, PFX "Port %u MII would not reset, "
1265 "bmcr[%04x]\n", np->port, err);
1266 return -ENODEV;
1267 }
1268
1269 return 0;
1270}
1271
5fbd7e24
MW		 1272
1273
1274static int xcvr_init_1g_rgmii(struct niu *np)
1275{
1276 int err;
1277 u64 val;
1278 u16 bmcr, bmsr, estat;
1279
1280 val = nr64(MIF_CONFIG);
1281 val &= ~MIF_CONFIG_INDIRECT_MODE;
1282 nw64(MIF_CONFIG, val);
1283
1284 err = mii_reset(np);
1285 if (err)
1286 return err;
1287
1288 err = mii_read(np, np->phy_addr, MII_BMSR);
1289 if (err < 0)
1290 return err;
1291 bmsr = err;
1292
1293 estat = 0;
1294 if (bmsr & BMSR_ESTATEN) {
1295 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1296 if (err < 0)
1297 return err;
1298 estat = err;
1299 }
1300
1301 bmcr = 0;
1302 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1303 if (err)
1304 return err;
1305
1306 if (bmsr & BMSR_ESTATEN) {
1307 u16 ctrl1000 = 0;
1308
1309 if (estat & ESTATUS_1000_TFULL)
1310 ctrl1000 |= ADVERTISE_1000FULL;
1311 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
1312 if (err)
1313 return err;
1314 }
1315
1316 bmcr = (BMCR_SPEED1000 | BMCR_FULLDPLX);
1317
1318 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1319 if (err)
1320 return err;
1321
1322 err = mii_read(np, np->phy_addr, MII_BMCR);
1323 if (err < 0)
1324 return err;
1325 bmcr = mii_read(np, np->phy_addr, MII_BMCR);
1326
1327 err = mii_read(np, np->phy_addr, MII_BMSR);
1328 if (err < 0)
1329 return err;
1330
1331 return 0;
1332}
1333
1334
a3138df9
DM		 1335static int mii_init_common(struct niu *np)
1336{
1337 struct niu_link_config *lp = &np->link_config;
1338 u16 bmcr, bmsr, adv, estat;
1339 int err;
1340
1341 err = mii_reset(np);
1342 if (err)
1343 return err;
1344
1345 err = mii_read(np, np->phy_addr, MII_BMSR);
1346 if (err < 0)
1347 return err;
1348 bmsr = err;
1349
1350 estat = 0;
1351 if (bmsr & BMSR_ESTATEN) {
1352 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1353 if (err < 0)
1354 return err;
1355 estat = err;
1356 }
1357
1358 bmcr = 0;
1359 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1360 if (err)
1361 return err;
1362
1363 if (lp->loopback_mode == LOOPBACK_MAC) {
1364 bmcr |= BMCR_LOOPBACK;
1365 if (lp->active_speed == SPEED_1000)
1366 bmcr |= BMCR_SPEED1000;
1367 if (lp->active_duplex == DUPLEX_FULL)
1368 bmcr |= BMCR_FULLDPLX;
1369 }
1370
1371 if (lp->loopback_mode == LOOPBACK_PHY) {
1372 u16 aux;
1373
1374 aux = (BCM5464R_AUX_CTL_EXT_LB |
1375 BCM5464R_AUX_CTL_WRITE_1);
1376 err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux);
1377 if (err)
1378 return err;
1379 }
1380
1381 /* XXX configurable XXX */
1382 /* XXX for now don't advertise half-duplex or asym pause... XXX */
1383 adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1384 if (bmsr & BMSR_10FULL)
1385 adv |= ADVERTISE_10FULL;
1386 if (bmsr & BMSR_100FULL)
1387 adv |= ADVERTISE_100FULL;
1388 err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv);
1389 if (err)
1390 return err;
1391
1392 if (bmsr & BMSR_ESTATEN) {
1393 u16 ctrl1000 = 0;
1394
1395 if (estat & ESTATUS_1000_TFULL)
1396 ctrl1000 |= ADVERTISE_1000FULL;
1397 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
1398 if (err)
1399 return err;
1400 }
1401 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1402
1403 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1404 if (err)
1405 return err;
1406
1407 err = mii_read(np, np->phy_addr, MII_BMCR);
1408 if (err < 0)
1409 return err;
1410 err = mii_read(np, np->phy_addr, MII_BMSR);
1411 if (err < 0)
1412 return err;
1413#if 0
1414 pr_info(PFX "Port %u after MII init bmcr[%04x] bmsr[%04x]\n",
1415 np->port, bmcr, bmsr);
1416#endif
1417
1418 return 0;
1419}
1420
1421static int xcvr_init_1g(struct niu *np)
1422{
1423 u64 val;
1424
1425 /* XXX shared resource, lock parent XXX */
1426 val = nr64(MIF_CONFIG);
1427 val &= ~MIF_CONFIG_INDIRECT_MODE;
1428 nw64(MIF_CONFIG, val);
1429
1430 return mii_init_common(np);
1431}
1432
1433static int niu_xcvr_init(struct niu *np)
1434{
1435 const struct niu_phy_ops *ops = np->phy_ops;
1436 int err;
1437
1438 err = 0;
1439 if (ops->xcvr_init)
1440 err = ops->xcvr_init(np);
1441
1442 return err;
1443}
1444
1445static int niu_serdes_init(struct niu *np)
1446{
1447 const struct niu_phy_ops *ops = np->phy_ops;
1448 int err;
1449
1450 err = 0;
1451 if (ops->serdes_init)
1452 err = ops->serdes_init(np);
1453
1454 return err;
1455}
1456
1457static void niu_init_xif(struct niu *);
0c3b091b 1458static void niu_handle_led(struct niu *, int status);
a3138df9
DM		 1459
1460static int niu_link_status_common(struct niu *np, int link_up)
1461{
1462 struct niu_link_config *lp = &np->link_config;
1463 struct net_device *dev = np->dev;
1464 unsigned long flags;
1465
1466 if (!netif_carrier_ok(dev) && link_up) {
1467 niuinfo(LINK, "%s: Link is up at %s, %s duplex\n",
1468 dev->name,
1469 (lp->active_speed == SPEED_10000 ?
1470 "10Gb/sec" :
1471 (lp->active_speed == SPEED_1000 ?
1472 "1Gb/sec" :
1473 (lp->active_speed == SPEED_100 ?
1474 "100Mbit/sec" : "10Mbit/sec"))),
1475 (lp->active_duplex == DUPLEX_FULL ?
1476 "full" : "half"));
1477
1478 spin_lock_irqsave(&np->lock, flags);
1479 niu_init_xif(np);
0c3b091b 1480 niu_handle_led(np, 1);
a3138df9
DM		 1481 spin_unlock_irqrestore(&np->lock, flags);
1482
1483 netif_carrier_on(dev);
1484 } else if (netif_carrier_ok(dev) && !link_up) {
1485 niuwarn(LINK, "%s: Link is down\n", dev->name);
0c3b091b
ML		 1486 spin_lock_irqsave(&np->lock, flags);
1487 niu_handle_led(np, 0);
1488 spin_unlock_irqrestore(&np->lock, flags);
a3138df9
DM		 1489 netif_carrier_off(dev);
1490 }
1491
1492 return 0;
1493}
1494
b0de8e40 1495static int link_status_10g_mrvl(struct niu *np, int *link_up_p)
a3138df9 1496{
b0de8e40 1497 int err, link_up, pma_status, pcs_status;
a3138df9
DM		 1498
1499 link_up = 0;
1500
b0de8e40
ML		 1501 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1502 MRVL88X2011_10G_PMD_STATUS_2);
1503 if (err < 0)
1504 goto out;
a3138df9 1505
b0de8e40
ML		 1506 /* Check PMA/PMD Register: 1.0001.2 == 1 */
1507 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1508 MRVL88X2011_PMA_PMD_STATUS_1);
1509 if (err < 0)
1510 goto out;
1511
1512 pma_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1513
1514 /* Check PMC Register : 3.0001.2 == 1: read twice */
1515 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1516 MRVL88X2011_PMA_PMD_STATUS_1);
1517 if (err < 0)
1518 goto out;
1519
1520 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1521 MRVL88X2011_PMA_PMD_STATUS_1);
1522 if (err < 0)
1523 goto out;
1524
1525 pcs_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1526
1527 /* Check XGXS Register : 4.0018.[0-3,12] */
1528 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV4_ADDR,
1529 MRVL88X2011_10G_XGXS_LANE_STAT);
1530 if (err < 0)
a3138df9
DM		 1531 goto out;
1532
b0de8e40
ML		 1533 if (err == (PHYXS_XGXS_LANE_STAT_ALINGED | PHYXS_XGXS_LANE_STAT_LANE3 |
1534 PHYXS_XGXS_LANE_STAT_LANE2 | PHYXS_XGXS_LANE_STAT_LANE1 |
1535 PHYXS_XGXS_LANE_STAT_LANE0 | PHYXS_XGXS_LANE_STAT_MAGIC |
1536 0x800))
1537 link_up = (pma_status && pcs_status) ? 1 : 0;
1538
1539 np->link_config.active_speed = SPEED_10000;
1540 np->link_config.active_duplex = DUPLEX_FULL;
1541 err = 0;
1542out:
1543 mrvl88x2011_act_led(np, (link_up ?
1544 MRVL88X2011_LED_CTL_PCS_ACT :
1545 MRVL88X2011_LED_CTL_OFF));
1546
1547 *link_up_p = link_up;
1548 return err;
1549}
1550
1551static int link_status_10g_bcom(struct niu *np, int *link_up_p)
1552{
1553 int err, link_up;
1554
1555 link_up = 0;
1556
a3138df9
DM		 1557 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1558 BCM8704_PMD_RCV_SIGDET);
1559 if (err < 0)
1560 goto out;
1561 if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
1562 err = 0;
1563 goto out;
1564 }
1565
1566 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1567 BCM8704_PCS_10G_R_STATUS);
1568 if (err < 0)
1569 goto out;
1570 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
1571 err = 0;
1572 goto out;
1573 }
1574
1575 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1576 BCM8704_PHYXS_XGXS_LANE_STAT);
1577 if (err < 0)
1578 goto out;
1579
1580 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
1581 PHYXS_XGXS_LANE_STAT_MAGIC |
1582 PHYXS_XGXS_LANE_STAT_LANE3 |
1583 PHYXS_XGXS_LANE_STAT_LANE2 |
1584 PHYXS_XGXS_LANE_STAT_LANE1 |
1585 PHYXS_XGXS_LANE_STAT_LANE0)) {
1586 err = 0;
1587 goto out;
1588 }
1589
1590 link_up = 1;
1591 np->link_config.active_speed = SPEED_10000;
1592 np->link_config.active_duplex = DUPLEX_FULL;
1593 err = 0;
1594
1595out:
b0de8e40
ML		 1596 *link_up_p = link_up;
1597 return err;
1598}
1599
1600static int link_status_10g(struct niu *np, int *link_up_p)
1601{
1602 unsigned long flags;
1603 int err = -EINVAL;
1604
1605 spin_lock_irqsave(&np->lock, flags);
1606
1607 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
1608 int phy_id;
1609
1610 phy_id = phy_decode(np->parent->port_phy, np->port);
1611 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
1612
1613 /* handle different phy types */
1614 switch (phy_id & NIU_PHY_ID_MASK) {
1615 case NIU_PHY_ID_MRVL88X2011:
1616 err = link_status_10g_mrvl(np, link_up_p);
1617 break;
1618
1619 default: /* bcom 8704 */
1620 err = link_status_10g_bcom(np, link_up_p);
1621 break;
1622 }
1623 }
1624
a3138df9
DM		 1625 spin_unlock_irqrestore(&np->lock, flags);
1626
a3138df9
DM		 1627 return err;
1628}
1629
1630static int link_status_1g(struct niu *np, int *link_up_p)
1631{
e415e6ea 1632 struct niu_link_config *lp = &np->link_config;
a3138df9
DM		 1633 u16 current_speed, bmsr;
1634 unsigned long flags;
1635 u8 current_duplex;
1636 int err, link_up;
1637
1638 link_up = 0;
1639 current_speed = SPEED_INVALID;
1640 current_duplex = DUPLEX_INVALID;
1641
1642 spin_lock_irqsave(&np->lock, flags);
1643
1644 err = -EINVAL;
1645 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
1646 goto out;
1647
1648 err = mii_read(np, np->phy_addr, MII_BMSR);
1649 if (err < 0)
1650 goto out;
1651
1652 bmsr = err;
1653 if (bmsr & BMSR_LSTATUS) {
1654 u16 adv, lpa, common, estat;
1655
1656 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1657 if (err < 0)
1658 goto out;
1659 adv = err;
1660
1661 err = mii_read(np, np->phy_addr, MII_LPA);
1662 if (err < 0)
1663 goto out;
1664 lpa = err;
1665
1666 common = adv & lpa;
1667
1668 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1669 if (err < 0)
1670 goto out;
1671 estat = err;
1672
1673 link_up = 1;
1674 if (estat & (ESTATUS_1000_TFULL | ESTATUS_1000_THALF)) {
1675 current_speed = SPEED_1000;
1676 if (estat & ESTATUS_1000_TFULL)
1677 current_duplex = DUPLEX_FULL;
1678 else
1679 current_duplex = DUPLEX_HALF;
1680 } else {
1681 if (common & ADVERTISE_100BASE4) {
1682 current_speed = SPEED_100;
1683 current_duplex = DUPLEX_HALF;
1684 } else if (common & ADVERTISE_100FULL) {
1685 current_speed = SPEED_100;
1686 current_duplex = DUPLEX_FULL;
1687 } else if (common & ADVERTISE_100HALF) {
1688 current_speed = SPEED_100;
1689 current_duplex = DUPLEX_HALF;
1690 } else if (common & ADVERTISE_10FULL) {
1691 current_speed = SPEED_10;
1692 current_duplex = DUPLEX_FULL;
1693 } else if (common & ADVERTISE_10HALF) {
1694 current_speed = SPEED_10;
1695 current_duplex = DUPLEX_HALF;
1696 } else
1697 link_up = 0;
1698 }
1699 }
e415e6ea
DM		 1700 lp->active_speed = current_speed;
1701 lp->active_duplex = current_duplex;
a3138df9
DM		 1702 err = 0;
1703
1704out:
1705 spin_unlock_irqrestore(&np->lock, flags);
1706
1707 *link_up_p = link_up;
1708 return err;
1709}
1710
1711static int niu_link_status(struct niu *np, int *link_up_p)
1712{
1713 const struct niu_phy_ops *ops = np->phy_ops;
1714 int err;
1715
1716 err = 0;
1717 if (ops->link_status)
1718 err = ops->link_status(np, link_up_p);
1719
1720 return err;
1721}
1722
1723static void niu_timer(unsigned long __opaque)
1724{
1725 struct niu *np = (struct niu *) __opaque;
1726 unsigned long off;
1727 int err, link_up;
1728
1729 err = niu_link_status(np, &link_up);
1730 if (!err)
1731 niu_link_status_common(np, link_up);
1732
1733 if (netif_carrier_ok(np->dev))
1734 off = 5 * HZ;
1735 else
1736 off = 1 * HZ;
1737 np->timer.expires = jiffies + off;
1738
1739 add_timer(&np->timer);
1740}
1741
5fbd7e24
MW		 1742static const struct niu_phy_ops phy_ops_10g_serdes = {
1743 .serdes_init = serdes_init_10g_serdes,
1744 .link_status = link_status_10g_serdes,
1745};
1746
1747static const struct niu_phy_ops phy_ops_1g_rgmii = {
1748 .xcvr_init = xcvr_init_1g_rgmii,
1749 .link_status = link_status_1g_rgmii,
1750};
1751
a3138df9
DM		 1752static const struct niu_phy_ops phy_ops_10g_fiber_niu = {
1753 .serdes_init = serdes_init_niu,
1754 .xcvr_init = xcvr_init_10g,
1755 .link_status = link_status_10g,
1756};
1757
1758static const struct niu_phy_ops phy_ops_10g_fiber = {
1759 .serdes_init = serdes_init_10g,
1760 .xcvr_init = xcvr_init_10g,
1761 .link_status = link_status_10g,
1762};
1763
1764static const struct niu_phy_ops phy_ops_10g_copper = {
1765 .serdes_init = serdes_init_10g,
1766 .link_status = link_status_10g, /* XXX */
1767};
1768
1769static const struct niu_phy_ops phy_ops_1g_fiber = {
1770 .serdes_init = serdes_init_1g,
1771 .xcvr_init = xcvr_init_1g,
1772 .link_status = link_status_1g,
1773};
1774
1775static const struct niu_phy_ops phy_ops_1g_copper = {
1776 .xcvr_init = xcvr_init_1g,
1777 .link_status = link_status_1g,
1778};
1779
1780struct niu_phy_template {
1781 const struct niu_phy_ops *ops;
1782 u32 phy_addr_base;
1783};
1784
1785static const struct niu_phy_template phy_template_niu = {
1786 .ops = &phy_ops_10g_fiber_niu,
1787 .phy_addr_base = 16,
1788};
1789
1790static const struct niu_phy_template phy_template_10g_fiber = {
1791 .ops = &phy_ops_10g_fiber,
1792 .phy_addr_base = 8,
1793};
1794
1795static const struct niu_phy_template phy_template_10g_copper = {
1796 .ops = &phy_ops_10g_copper,
1797 .phy_addr_base = 10,
1798};
1799
1800static const struct niu_phy_template phy_template_1g_fiber = {
1801 .ops = &phy_ops_1g_fiber,
1802 .phy_addr_base = 0,
1803};
1804
1805static const struct niu_phy_template phy_template_1g_copper = {
1806 .ops = &phy_ops_1g_copper,
1807 .phy_addr_base = 0,
1808};
1809
5fbd7e24
MW		 1810static const struct niu_phy_template phy_template_1g_rgmii = {
1811 .ops = &phy_ops_1g_rgmii,
1812 .phy_addr_base = 0,
1813};
1814
1815static const struct niu_phy_template phy_template_10g_serdes = {
1816 .ops = &phy_ops_10g_serdes,
1817 .phy_addr_base = 0,
1818};
1819
1820static int niu_atca_port_num[4] = {
1821 0, 0, 11, 10
1822};
1823
1824static int serdes_init_10g_serdes(struct niu *np)
1825{
1826 struct niu_link_config *lp = &np->link_config;
1827 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
1828 u64 ctrl_val, test_cfg_val, sig, mask, val;
1829 int err;
1830 u64 reset_val;
1831
1832 switch (np->port) {
1833 case 0:
1834 reset_val = ENET_SERDES_RESET_0;
1835 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
1836 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
1837 pll_cfg = ENET_SERDES_0_PLL_CFG;
1838 break;
1839 case 1:
1840 reset_val = ENET_SERDES_RESET_1;
1841 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
1842 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
1843 pll_cfg = ENET_SERDES_1_PLL_CFG;
1844 break;
1845
1846 default:
1847 return -EINVAL;
1848 }
1849 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
1850 ENET_SERDES_CTRL_SDET_1 |
1851 ENET_SERDES_CTRL_SDET_2 |
1852 ENET_SERDES_CTRL_SDET_3 |
1853 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
1854 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
1855 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
1856 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
1857 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
1858 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
1859 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
1860 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
1861 test_cfg_val = 0;
1862
1863 if (lp->loopback_mode == LOOPBACK_PHY) {
1864 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
1865 ENET_SERDES_TEST_MD_0_SHIFT) |
1866 (ENET_TEST_MD_PAD_LOOPBACK <<
1867 ENET_SERDES_TEST_MD_1_SHIFT) |
1868 (ENET_TEST_MD_PAD_LOOPBACK <<
1869 ENET_SERDES_TEST_MD_2_SHIFT) |
1870 (ENET_TEST_MD_PAD_LOOPBACK <<
1871 ENET_SERDES_TEST_MD_3_SHIFT));
1872 }
1873
1874 esr_reset(np);
1875 nw64(pll_cfg, ENET_SERDES_PLL_FBDIV2);
1876 nw64(ctrl_reg, ctrl_val);
1877 nw64(test_cfg_reg, test_cfg_val);
1878
1879 /* Initialize all 4 lanes of the SERDES. */
1880 for (i = 0; i < 4; i++) {
1881 u32 rxtx_ctrl, glue0;
1882
1883 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
1884 if (err)
1885 return err;
1886 err = esr_read_glue0(np, i, &glue0);
1887 if (err)
1888 return err;
1889
1890 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
1891 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
1892 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
1893
1894 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
1895 ESR_GLUE_CTRL0_THCNT |
1896 ESR_GLUE_CTRL0_BLTIME);
1897 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
1898 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
1899 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
1900 (BLTIME_300_CYCLES <<
1901 ESR_GLUE_CTRL0_BLTIME_SHIFT));
1902
1903 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
1904 if (err)
1905 return err;
1906 err = esr_write_glue0(np, i, glue0);
1907 if (err)
1908 return err;
1909 }
1910
1911
1912 sig = nr64(ESR_INT_SIGNALS);
1913 switch (np->port) {
1914 case 0:
1915 mask = ESR_INT_SIGNALS_P0_BITS;
1916 val = (ESR_INT_SRDY0_P0 |
1917 ESR_INT_DET0_P0 |
1918 ESR_INT_XSRDY_P0 |
1919 ESR_INT_XDP_P0_CH3 |
1920 ESR_INT_XDP_P0_CH2 |
1921 ESR_INT_XDP_P0_CH1 |
1922 ESR_INT_XDP_P0_CH0);
1923 break;
1924
1925 case 1:
1926 mask = ESR_INT_SIGNALS_P1_BITS;
1927 val = (ESR_INT_SRDY0_P1 |
1928 ESR_INT_DET0_P1 |
1929 ESR_INT_XSRDY_P1 |
1930 ESR_INT_XDP_P1_CH3 |
1931 ESR_INT_XDP_P1_CH2 |
1932 ESR_INT_XDP_P1_CH1 |
1933 ESR_INT_XDP_P1_CH0);
1934 break;
1935
1936 default:
1937 return -EINVAL;
1938 }
1939
1940 if ((sig & mask) != val) {
1941 int err;
1942 err = serdes_init_1g_serdes(np);
1943 if (!err) {
1944 np->flags &= ~NIU_FLAGS_10G;
1945 np->mac_xcvr = MAC_XCVR_PCS;
1946 } else {
1947 dev_err(np->device, PFX "Port %u 10G/1G SERDES Link Failed \n",
1948 np->port);
1949 return -ENODEV;
1950 }
1951 }
1952
1953 return 0;
1954}
1955
a3138df9
DM		 1956static int niu_determine_phy_disposition(struct niu *np)
1957{
1958 struct niu_parent *parent = np->parent;
1959 u8 plat_type = parent->plat_type;
1960 const struct niu_phy_template *tp;
1961 u32 phy_addr_off = 0;
1962
1963 if (plat_type == PLAT_TYPE_NIU) {
1964 tp = &phy_template_niu;
1965 phy_addr_off += np->port;
1966 } else {
5fbd7e24
MW		 1967 switch (np->flags &
1968 (NIU_FLAGS_10G |
1969 NIU_FLAGS_FIBER |
1970 NIU_FLAGS_XCVR_SERDES)) {
a3138df9
DM		 1971 case 0:
1972 /* 1G copper */
1973 tp = &phy_template_1g_copper;
1974 if (plat_type == PLAT_TYPE_VF_P0)
1975 phy_addr_off = 10;
1976 else if (plat_type == PLAT_TYPE_VF_P1)
1977 phy_addr_off = 26;
1978
1979 phy_addr_off += (np->port ^ 0x3);
1980 break;
1981
1982 case NIU_FLAGS_10G:
1983 /* 10G copper */
1984 tp = &phy_template_1g_copper;
1985 break;
1986
1987 case NIU_FLAGS_FIBER:
1988 /* 1G fiber */
1989 tp = &phy_template_1g_fiber;
1990 break;
1991
1992 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
1993 /* 10G fiber */
1994 tp = &phy_template_10g_fiber;
1995 if (plat_type == PLAT_TYPE_VF_P0 ||
1996 plat_type == PLAT_TYPE_VF_P1)
1997 phy_addr_off = 8;
1998 phy_addr_off += np->port;
1999 break;
2000
5fbd7e24
MW		 2001 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2002 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
2003 case NIU_FLAGS_XCVR_SERDES:
2004 switch(np->port) {
2005 case 0:
2006 case 1:
2007 tp = &phy_template_10g_serdes;
2008 break;
2009 case 2:
2010 case 3:
2011 tp = &phy_template_1g_rgmii;
2012 break;
2013 default:
2014 return -EINVAL;
2015 break;
2016 }
2017 phy_addr_off = niu_atca_port_num[np->port];
2018 break;
2019
a3138df9
DM		 2020 default:
2021 return -EINVAL;
2022 }
2023 }
2024
2025 np->phy_ops = tp->ops;
2026 np->phy_addr = tp->phy_addr_base + phy_addr_off;
2027
2028 return 0;
2029}
2030
2031static int niu_init_link(struct niu *np)
2032{
2033 struct niu_parent *parent = np->parent;
2034 int err, ignore;
2035
2036 if (parent->plat_type == PLAT_TYPE_NIU) {
2037 err = niu_xcvr_init(np);
2038 if (err)
2039 return err;
2040 msleep(200);
2041 }
2042 err = niu_serdes_init(np);
2043 if (err)
2044 return err;
2045 msleep(200);
2046 err = niu_xcvr_init(np);
2047 if (!err)
2048 niu_link_status(np, &ignore);
2049 return 0;
2050}
2051
2052static void niu_set_primary_mac(struct niu *np, unsigned char *addr)
2053{
2054 u16 reg0 = addr[4] << 8 | addr[5];
2055 u16 reg1 = addr[2] << 8 | addr[3];
2056 u16 reg2 = addr[0] << 8 | addr[1];
2057
2058 if (np->flags & NIU_FLAGS_XMAC) {
2059 nw64_mac(XMAC_ADDR0, reg0);
2060 nw64_mac(XMAC_ADDR1, reg1);
2061 nw64_mac(XMAC_ADDR2, reg2);
2062 } else {
2063 nw64_mac(BMAC_ADDR0, reg0);
2064 nw64_mac(BMAC_ADDR1, reg1);
2065 nw64_mac(BMAC_ADDR2, reg2);
2066 }
2067}
2068
2069static int niu_num_alt_addr(struct niu *np)
2070{
2071 if (np->flags & NIU_FLAGS_XMAC)
2072 return XMAC_NUM_ALT_ADDR;
2073 else
2074 return BMAC_NUM_ALT_ADDR;
2075}
2076
2077static int niu_set_alt_mac(struct niu *np, int index, unsigned char *addr)
2078{
2079 u16 reg0 = addr[4] << 8 | addr[5];
2080 u16 reg1 = addr[2] << 8 | addr[3];
2081 u16 reg2 = addr[0] << 8 | addr[1];
2082
2083 if (index >= niu_num_alt_addr(np))
2084 return -EINVAL;
2085
2086 if (np->flags & NIU_FLAGS_XMAC) {
2087 nw64_mac(XMAC_ALT_ADDR0(index), reg0);
2088 nw64_mac(XMAC_ALT_ADDR1(index), reg1);
2089 nw64_mac(XMAC_ALT_ADDR2(index), reg2);
2090 } else {
2091 nw64_mac(BMAC_ALT_ADDR0(index), reg0);
2092 nw64_mac(BMAC_ALT_ADDR1(index), reg1);
2093 nw64_mac(BMAC_ALT_ADDR2(index), reg2);
2094 }
2095
2096 return 0;
2097}
2098
2099static int niu_enable_alt_mac(struct niu *np, int index, int on)
2100{
2101 unsigned long reg;
2102 u64 val, mask;
2103
2104 if (index >= niu_num_alt_addr(np))
2105 return -EINVAL;
2106
fa907895 2107 if (np->flags & NIU_FLAGS_XMAC) {
a3138df9 2108 reg = XMAC_ADDR_CMPEN;
fa907895
MW		 2109 mask = 1 << index;
2110 } else {
a3138df9 2111 reg = BMAC_ADDR_CMPEN;
fa907895
MW		 2112 mask = 1 << (index + 1);
2113 }
a3138df9
DM		 2114
2115 val = nr64_mac(reg);
2116 if (on)
2117 val |= mask;
2118 else
2119 val &= ~mask;
2120 nw64_mac(reg, val);
2121
2122 return 0;
2123}
2124
2125static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg,
2126 int num, int mac_pref)
2127{
2128 u64 val = nr64_mac(reg);
2129 val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR);
2130 val |= num;
2131 if (mac_pref)
2132 val |= HOST_INFO_MPR;
2133 nw64_mac(reg, val);
2134}
2135
2136static int __set_rdc_table_num(struct niu *np,
2137 int xmac_index, int bmac_index,
2138 int rdc_table_num, int mac_pref)
2139{
2140 unsigned long reg;
2141
2142 if (rdc_table_num & ~HOST_INFO_MACRDCTBLN)
2143 return -EINVAL;
2144 if (np->flags & NIU_FLAGS_XMAC)
2145 reg = XMAC_HOST_INFO(xmac_index);
2146 else
2147 reg = BMAC_HOST_INFO(bmac_index);
2148 __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref);
2149 return 0;
2150}
2151
2152static int niu_set_primary_mac_rdc_table(struct niu *np, int table_num,
2153 int mac_pref)
2154{
2155 return __set_rdc_table_num(np, 17, 0, table_num, mac_pref);
2156}
2157
2158static int niu_set_multicast_mac_rdc_table(struct niu *np, int table_num,
2159 int mac_pref)
2160{
2161 return __set_rdc_table_num(np, 16, 8, table_num, mac_pref);
2162}
2163
2164static int niu_set_alt_mac_rdc_table(struct niu *np, int idx,
2165 int table_num, int mac_pref)
2166{
2167 if (idx >= niu_num_alt_addr(np))
2168 return -EINVAL;
2169 return __set_rdc_table_num(np, idx, idx + 1, table_num, mac_pref);
2170}
2171
2172static u64 vlan_entry_set_parity(u64 reg_val)
2173{
2174 u64 port01_mask;
2175 u64 port23_mask;
2176
2177 port01_mask = 0x00ff;
2178 port23_mask = 0xff00;
2179
2180 if (hweight64(reg_val & port01_mask) & 1)
2181 reg_val |= ENET_VLAN_TBL_PARITY0;
2182 else
2183 reg_val &= ~ENET_VLAN_TBL_PARITY0;
2184
2185 if (hweight64(reg_val & port23_mask) & 1)
2186 reg_val |= ENET_VLAN_TBL_PARITY1;
2187 else
2188 reg_val &= ~ENET_VLAN_TBL_PARITY1;
2189
2190 return reg_val;
2191}
2192
2193static void vlan_tbl_write(struct niu *np, unsigned long index,
2194 int port, int vpr, int rdc_table)
2195{
2196 u64 reg_val = nr64(ENET_VLAN_TBL(index));
2197
2198 reg_val &= ~((ENET_VLAN_TBL_VPR |
2199 ENET_VLAN_TBL_VLANRDCTBLN) <<
2200 ENET_VLAN_TBL_SHIFT(port));
2201 if (vpr)
2202 reg_val |= (ENET_VLAN_TBL_VPR <<
2203 ENET_VLAN_TBL_SHIFT(port));
2204 reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port));
2205
2206 reg_val = vlan_entry_set_parity(reg_val);
2207
2208 nw64(ENET_VLAN_TBL(index), reg_val);
2209}
2210
2211static void vlan_tbl_clear(struct niu *np)
2212{
2213 int i;
2214
2215 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++)
2216 nw64(ENET_VLAN_TBL(i), 0);
2217}
2218
2219static int tcam_wait_bit(struct niu *np, u64 bit)
2220{
2221 int limit = 1000;
2222
2223 while (--limit > 0) {
2224 if (nr64(TCAM_CTL) & bit)
2225 break;
2226 udelay(1);
2227 }
2228 if (limit < 0)
2229 return -ENODEV;
2230
2231 return 0;
2232}
2233
2234static int tcam_flush(struct niu *np, int index)
2235{
2236 nw64(TCAM_KEY_0, 0x00);
2237 nw64(TCAM_KEY_MASK_0, 0xff);
2238 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2239
2240 return tcam_wait_bit(np, TCAM_CTL_STAT);
2241}
2242
2243#if 0
2244static int tcam_read(struct niu *np, int index,
2245 u64 *key, u64 *mask)
2246{
2247 int err;
2248
2249 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index));
2250 err = tcam_wait_bit(np, TCAM_CTL_STAT);
2251 if (!err) {
2252 key[0] = nr64(TCAM_KEY_0);
2253 key[1] = nr64(TCAM_KEY_1);
2254 key[2] = nr64(TCAM_KEY_2);
2255 key[3] = nr64(TCAM_KEY_3);
2256 mask[0] = nr64(TCAM_KEY_MASK_0);
2257 mask[1] = nr64(TCAM_KEY_MASK_1);
2258 mask[2] = nr64(TCAM_KEY_MASK_2);
2259 mask[3] = nr64(TCAM_KEY_MASK_3);
2260 }
2261 return err;
2262}
2263#endif
2264
2265static int tcam_write(struct niu *np, int index,
2266 u64 *key, u64 *mask)
2267{
2268 nw64(TCAM_KEY_0, key[0]);
2269 nw64(TCAM_KEY_1, key[1]);
2270 nw64(TCAM_KEY_2, key[2]);
2271 nw64(TCAM_KEY_3, key[3]);
2272 nw64(TCAM_KEY_MASK_0, mask[0]);
2273 nw64(TCAM_KEY_MASK_1, mask[1]);
2274 nw64(TCAM_KEY_MASK_2, mask[2]);
2275 nw64(TCAM_KEY_MASK_3, mask[3]);
2276 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2277
2278 return tcam_wait_bit(np, TCAM_CTL_STAT);
2279}
2280
2281#if 0
2282static int tcam_assoc_read(struct niu *np, int index, u64 *data)
2283{
2284 int err;
2285
2286 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index));
2287 err = tcam_wait_bit(np, TCAM_CTL_STAT);
2288 if (!err)
2289 *data = nr64(TCAM_KEY_1);
2290
2291 return err;
2292}
2293#endif
2294
2295static int tcam_assoc_write(struct niu *np, int index, u64 assoc_data)
2296{
2297 nw64(TCAM_KEY_1, assoc_data);
2298 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index));
2299
2300 return tcam_wait_bit(np, TCAM_CTL_STAT);
2301}
2302
2303static void tcam_enable(struct niu *np, int on)
2304{
2305 u64 val = nr64(FFLP_CFG_1);
2306
2307 if (on)
2308 val &= ~FFLP_CFG_1_TCAM_DIS;
2309 else
2310 val |= FFLP_CFG_1_TCAM_DIS;
2311 nw64(FFLP_CFG_1, val);
2312}
2313
2314static void tcam_set_lat_and_ratio(struct niu *np, u64 latency, u64 ratio)
2315{
2316 u64 val = nr64(FFLP_CFG_1);
2317
2318 val &= ~(FFLP_CFG_1_FFLPINITDONE |
2319 FFLP_CFG_1_CAMLAT |
2320 FFLP_CFG_1_CAMRATIO);
2321 val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT);
2322 val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT);
2323 nw64(FFLP_CFG_1, val);
2324
2325 val = nr64(FFLP_CFG_1);
2326 val |= FFLP_CFG_1_FFLPINITDONE;
2327 nw64(FFLP_CFG_1, val);
2328}
2329
2330static int tcam_user_eth_class_enable(struct niu *np, unsigned long class,
2331 int on)
2332{
2333 unsigned long reg;
2334 u64 val;
2335
2336 if (class < CLASS_CODE_ETHERTYPE1 ||
2337 class > CLASS_CODE_ETHERTYPE2)
2338 return -EINVAL;
2339
2340 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2341 val = nr64(reg);
2342 if (on)
2343 val |= L2_CLS_VLD;
2344 else
2345 val &= ~L2_CLS_VLD;
2346 nw64(reg, val);
2347
2348 return 0;
2349}
2350
2351#if 0
2352static int tcam_user_eth_class_set(struct niu *np, unsigned long class,
2353 u64 ether_type)
2354{
2355 unsigned long reg;
2356 u64 val;
2357
2358 if (class < CLASS_CODE_ETHERTYPE1 ||
2359 class > CLASS_CODE_ETHERTYPE2 ||
2360 (ether_type & ~(u64)0xffff) != 0)
2361 return -EINVAL;
2362
2363 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2364 val = nr64(reg);
2365 val &= ~L2_CLS_ETYPE;
2366 val |= (ether_type << L2_CLS_ETYPE_SHIFT);
2367 nw64(reg, val);
2368
2369 return 0;
2370}
2371#endif
2372
2373static int tcam_user_ip_class_enable(struct niu *np, unsigned long class,
2374 int on)
2375{
2376 unsigned long reg;
2377 u64 val;
2378
2379 if (class < CLASS_CODE_USER_PROG1 ||
2380 class > CLASS_CODE_USER_PROG4)
2381 return -EINVAL;
2382
2383 reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2384 val = nr64(reg);
2385 if (on)
2386 val |= L3_CLS_VALID;
2387 else
2388 val &= ~L3_CLS_VALID;
2389 nw64(reg, val);
2390
2391 return 0;
2392}
2393
2394#if 0
2395static int tcam_user_ip_class_set(struct niu *np, unsigned long class,
2396 int ipv6, u64 protocol_id,
2397 u64 tos_mask, u64 tos_val)
2398{
2399 unsigned long reg;
2400 u64 val;
2401
2402 if (class < CLASS_CODE_USER_PROG1 ||
2403 class > CLASS_CODE_USER_PROG4 ||
2404 (protocol_id & ~(u64)0xff) != 0 ||
2405 (tos_mask & ~(u64)0xff) != 0 ||
2406 (tos_val & ~(u64)0xff) != 0)
2407 return -EINVAL;
2408
2409 reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2410 val = nr64(reg);
2411 val &= ~(L3_CLS_IPVER | L3_CLS_PID |
2412 L3_CLS_TOSMASK | L3_CLS_TOS);
2413 if (ipv6)
2414 val |= L3_CLS_IPVER;
2415 val |= (protocol_id << L3_CLS_PID_SHIFT);
2416 val |= (tos_mask << L3_CLS_TOSMASK_SHIFT);
2417 val |= (tos_val << L3_CLS_TOS_SHIFT);
2418 nw64(reg, val);
2419
2420 return 0;
2421}
2422#endif
2423
2424static int tcam_early_init(struct niu *np)
2425{
2426 unsigned long i;
2427 int err;
2428
2429 tcam_enable(np, 0);
2430 tcam_set_lat_and_ratio(np,
2431 DEFAULT_TCAM_LATENCY,
2432 DEFAULT_TCAM_ACCESS_RATIO);
2433 for (i = CLASS_CODE_ETHERTYPE1; i <= CLASS_CODE_ETHERTYPE2; i++) {
2434 err = tcam_user_eth_class_enable(np, i, 0);
2435 if (err)
2436 return err;
2437 }
2438 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_USER_PROG4; i++) {
2439 err = tcam_user_ip_class_enable(np, i, 0);
2440 if (err)
2441 return err;
2442 }
2443
2444 return 0;
2445}
2446
2447static int tcam_flush_all(struct niu *np)
2448{
2449 unsigned long i;
2450
2451 for (i = 0; i < np->parent->tcam_num_entries; i++) {
2452 int err = tcam_flush(np, i);
2453 if (err)
2454 return err;
2455 }
2456 return 0;
2457}
2458
2459static u64 hash_addr_regval(unsigned long index, unsigned long num_entries)
2460{
2461 return ((u64)index | (num_entries == 1 ?
2462 HASH_TBL_ADDR_AUTOINC : 0));
2463}
2464
2465#if 0
2466static int hash_read(struct niu *np, unsigned long partition,
2467 unsigned long index, unsigned long num_entries,
2468 u64 *data)
2469{
2470 u64 val = hash_addr_regval(index, num_entries);
2471 unsigned long i;
2472
2473 if (partition >= FCRAM_NUM_PARTITIONS ||
2474 index + num_entries > FCRAM_SIZE)
2475 return -EINVAL;
2476
2477 nw64(HASH_TBL_ADDR(partition), val);
2478 for (i = 0; i < num_entries; i++)
2479 data[i] = nr64(HASH_TBL_DATA(partition));
2480
2481 return 0;
2482}
2483#endif
2484
2485static int hash_write(struct niu *np, unsigned long partition,
2486 unsigned long index, unsigned long num_entries,
2487 u64 *data)
2488{
2489 u64 val = hash_addr_regval(index, num_entries);
2490 unsigned long i;
2491
2492 if (partition >= FCRAM_NUM_PARTITIONS ||
2493 index + (num_entries * 8) > FCRAM_SIZE)
2494 return -EINVAL;
2495
2496 nw64(HASH_TBL_ADDR(partition), val);
2497 for (i = 0; i < num_entries; i++)
2498 nw64(HASH_TBL_DATA(partition), data[i]);
2499
2500 return 0;
2501}
2502
2503static void fflp_reset(struct niu *np)
2504{
2505 u64 val;
2506
2507 nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST);
2508 udelay(10);
2509 nw64(FFLP_CFG_1, 0);
2510
2511 val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE;
2512 nw64(FFLP_CFG_1, val);
2513}
2514
2515static void fflp_set_timings(struct niu *np)
2516{
2517 u64 val = nr64(FFLP_CFG_1);
2518
2519 val &= ~FFLP_CFG_1_FFLPINITDONE;
2520 val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT);
2521 nw64(FFLP_CFG_1, val);
2522
2523 val = nr64(FFLP_CFG_1);
2524 val |= FFLP_CFG_1_FFLPINITDONE;
2525 nw64(FFLP_CFG_1, val);
2526
2527 val = nr64(FCRAM_REF_TMR);
2528 val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN);
2529 val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT);
2530 val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT);
2531 nw64(FCRAM_REF_TMR, val);
2532}
2533
2534static int fflp_set_partition(struct niu *np, u64 partition,
2535 u64 mask, u64 base, int enable)
2536{
2537 unsigned long reg;
2538 u64 val;
2539
2540 if (partition >= FCRAM_NUM_PARTITIONS ||
2541 (mask & ~(u64)0x1f) != 0 ||
2542 (base & ~(u64)0x1f) != 0)
2543 return -EINVAL;
2544
2545 reg = FLW_PRT_SEL(partition);
2546
2547 val = nr64(reg);
2548 val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE);
2549 val |= (mask << FLW_PRT_SEL_MASK_SHIFT);
2550 val |= (base << FLW_PRT_SEL_BASE_SHIFT);
2551 if (enable)
2552 val |= FLW_PRT_SEL_EXT;
2553 nw64(reg, val);
2554
2555 return 0;
2556}
2557
2558static int fflp_disable_all_partitions(struct niu *np)
2559{
2560 unsigned long i;
2561
2562 for (i = 0; i < FCRAM_NUM_PARTITIONS; i++) {
2563 int err = fflp_set_partition(np, 0, 0, 0, 0);
2564 if (err)
2565 return err;
2566 }
2567 return 0;
2568}
2569
2570static void fflp_llcsnap_enable(struct niu *np, int on)
2571{
2572 u64 val = nr64(FFLP_CFG_1);
2573
2574 if (on)
2575 val |= FFLP_CFG_1_LLCSNAP;
2576 else
2577 val &= ~FFLP_CFG_1_LLCSNAP;
2578 nw64(FFLP_CFG_1, val);
2579}
2580
2581static void fflp_errors_enable(struct niu *np, int on)
2582{
2583 u64 val = nr64(FFLP_CFG_1);
2584
2585 if (on)
2586 val &= ~FFLP_CFG_1_ERRORDIS;
2587 else
2588 val |= FFLP_CFG_1_ERRORDIS;
2589 nw64(FFLP_CFG_1, val);
2590}
2591
2592static int fflp_hash_clear(struct niu *np)
2593{
2594 struct fcram_hash_ipv4 ent;
2595 unsigned long i;
2596
2597 /* IPV4 hash entry with valid bit clear, rest is don't care. */
2598 memset(&ent, 0, sizeof(ent));
2599 ent.header = HASH_HEADER_EXT;
2600
2601 for (i = 0; i < FCRAM_SIZE; i += sizeof(ent)) {
2602 int err = hash_write(np, 0, i, 1, (u64 *) &ent);
2603 if (err)
2604 return err;
2605 }
2606 return 0;
2607}
2608
2609static int fflp_early_init(struct niu *np)
2610{
2611 struct niu_parent *parent;
2612 unsigned long flags;
2613 int err;
2614
2615 niu_lock_parent(np, flags);
2616
2617 parent = np->parent;
2618 err = 0;
2619 if (!(parent->flags & PARENT_FLGS_CLS_HWINIT)) {
2620 niudbg(PROBE, "fflp_early_init: Initting hw on port %u\n",
2621 np->port);
2622 if (np->parent->plat_type != PLAT_TYPE_NIU) {
2623 fflp_reset(np);
2624 fflp_set_timings(np);
2625 err = fflp_disable_all_partitions(np);
2626 if (err) {
2627 niudbg(PROBE, "fflp_disable_all_partitions "
2628 "failed, err=%d\n", err);
2629 goto out;
2630 }
2631 }
2632
2633 err = tcam_early_init(np);
2634 if (err) {
2635 niudbg(PROBE, "tcam_early_init failed, err=%d\n",
2636 err);
2637 goto out;
2638 }
2639 fflp_llcsnap_enable(np, 1);
2640 fflp_errors_enable(np, 0);
2641 nw64(H1POLY, 0);
2642 nw64(H2POLY, 0);
2643
2644 err = tcam_flush_all(np);
2645 if (err) {
2646 niudbg(PROBE, "tcam_flush_all failed, err=%d\n",
2647 err);
2648 goto out;
2649 }
2650 if (np->parent->plat_type != PLAT_TYPE_NIU) {
2651 err = fflp_hash_clear(np);
2652 if (err) {
2653 niudbg(PROBE, "fflp_hash_clear failed, "
2654 "err=%d\n", err);
2655 goto out;
2656 }
2657 }
2658
2659 vlan_tbl_clear(np);
2660
2661 niudbg(PROBE, "fflp_early_init: Success\n");
2662 parent->flags |= PARENT_FLGS_CLS_HWINIT;
2663 }
2664out:
2665 niu_unlock_parent(np, flags);
2666 return err;
2667}
2668
2669static int niu_set_flow_key(struct niu *np, unsigned long class_code, u64 key)
2670{
2671 if (class_code < CLASS_CODE_USER_PROG1 ||
2672 class_code > CLASS_CODE_SCTP_IPV6)
2673 return -EINVAL;
2674
2675 nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key);
2676 return 0;
2677}
2678
2679static int niu_set_tcam_key(struct niu *np, unsigned long class_code, u64 key)
2680{
2681 if (class_code < CLASS_CODE_USER_PROG1 ||
2682 class_code > CLASS_CODE_SCTP_IPV6)
2683 return -EINVAL;
2684
2685 nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key);
2686 return 0;
2687}
2688
2689static void niu_rx_skb_append(struct sk_buff *skb, struct page *page,
2690 u32 offset, u32 size)
2691{
2692 int i = skb_shinfo(skb)->nr_frags;
2693 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2694
2695 frag->page = page;
2696 frag->page_offset = offset;
2697 frag->size = size;
2698
2699 skb->len += size;
2700 skb->data_len += size;
2701 skb->truesize += size;
2702
2703 skb_shinfo(skb)->nr_frags = i + 1;
2704}
2705
2706static unsigned int niu_hash_rxaddr(struct rx_ring_info *rp, u64 a)
2707{
2708 a >>= PAGE_SHIFT;
2709 a ^= (a >> ilog2(MAX_RBR_RING_SIZE));
2710
2711 return (a & (MAX_RBR_RING_SIZE - 1));
2712}
2713
2714static struct page *niu_find_rxpage(struct rx_ring_info *rp, u64 addr,
2715 struct page ***link)
2716{
2717 unsigned int h = niu_hash_rxaddr(rp, addr);
2718 struct page *p, **pp;
2719
2720 addr &= PAGE_MASK;
2721 pp = &rp->rxhash[h];
2722 for (; (p = *pp) != NULL; pp = (struct page **) &p->mapping) {
2723 if (p->index == addr) {
2724 *link = pp;
2725 break;
2726 }
2727 }
2728
2729 return p;
2730}
2731
2732static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base)
2733{
2734 unsigned int h = niu_hash_rxaddr(rp, base);
2735
2736 page->index = base;
2737 page->mapping = (struct address_space *) rp->rxhash[h];
2738 rp->rxhash[h] = page;
2739}
2740
2741static int niu_rbr_add_page(struct niu *np, struct rx_ring_info *rp,
2742 gfp_t mask, int start_index)
2743{
2744 struct page *page;
2745 u64 addr;
2746 int i;
2747
2748 page = alloc_page(mask);
2749 if (!page)
2750 return -ENOMEM;
2751
2752 addr = np->ops->map_page(np->device, page, 0,
2753 PAGE_SIZE, DMA_FROM_DEVICE);
2754
2755 niu_hash_page(rp, page, addr);
2756 if (rp->rbr_blocks_per_page > 1)
2757 atomic_add(rp->rbr_blocks_per_page - 1,
2758 &compound_head(page)->_count);
2759
2760 for (i = 0; i < rp->rbr_blocks_per_page; i++) {
2761 __le32 *rbr = &rp->rbr[start_index + i];
2762
2763 *rbr = cpu_to_le32(addr >> RBR_DESCR_ADDR_SHIFT);
2764 addr += rp->rbr_block_size;
2765 }
2766
2767 return 0;
2768}
2769
2770static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
2771{
2772 int index = rp->rbr_index;
2773
2774 rp->rbr_pending++;
2775 if ((rp->rbr_pending % rp->rbr_blocks_per_page) == 0) {
2776 int err = niu_rbr_add_page(np, rp, mask, index);
2777
2778 if (unlikely(err)) {
2779 rp->rbr_pending--;
2780 return;
2781 }
2782
2783 rp->rbr_index += rp->rbr_blocks_per_page;
2784 BUG_ON(rp->rbr_index > rp->rbr_table_size);
2785 if (rp->rbr_index == rp->rbr_table_size)
2786 rp->rbr_index = 0;
2787
2788 if (rp->rbr_pending >= rp->rbr_kick_thresh) {
2789 nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending);
2790 rp->rbr_pending = 0;
2791 }
2792 }
2793}
2794
2795static int niu_rx_pkt_ignore(struct niu *np, struct rx_ring_info *rp)
2796{
2797 unsigned int index = rp->rcr_index;
2798 int num_rcr = 0;
2799
2800 rp->rx_dropped++;
2801 while (1) {
2802 struct page *page, **link;
2803 u64 addr, val;
2804 u32 rcr_size;
2805
2806 num_rcr++;
2807
2808 val = le64_to_cpup(&rp->rcr[index]);
2809 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
2810 RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
2811 page = niu_find_rxpage(rp, addr, &link);
2812
2813 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
2814 RCR_ENTRY_PKTBUFSZ_SHIFT];
2815 if ((page->index + PAGE_SIZE) - rcr_size == addr) {
2816 *link = (struct page *) page->mapping;
2817 np->ops->unmap_page(np->device, page->index,
2818 PAGE_SIZE, DMA_FROM_DEVICE);
2819 page->index = 0;
2820 page->mapping = NULL;
2821 __free_page(page);
2822 rp->rbr_refill_pending++;
2823 }
2824
2825 index = NEXT_RCR(rp, index);
2826 if (!(val & RCR_ENTRY_MULTI))
2827 break;
2828
2829 }
2830 rp->rcr_index = index;
2831
2832 return num_rcr;
2833}
2834
2835static int niu_process_rx_pkt(struct niu *np, struct rx_ring_info *rp)
2836{
2837 unsigned int index = rp->rcr_index;
2838 struct sk_buff *skb;
2839 int len, num_rcr;
2840
2841 skb = netdev_alloc_skb(np->dev, RX_SKB_ALLOC_SIZE);
2842 if (unlikely(!skb))
2843 return niu_rx_pkt_ignore(np, rp);
2844
2845 num_rcr = 0;
2846 while (1) {
2847 struct page *page, **link;
2848 u32 rcr_size, append_size;
2849 u64 addr, val, off;
2850
2851 num_rcr++;
2852
2853 val = le64_to_cpup(&rp->rcr[index]);
2854
2855 len = (val & RCR_ENTRY_L2_LEN) >>
2856 RCR_ENTRY_L2_LEN_SHIFT;
2857 len -= ETH_FCS_LEN;
2858
2859 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
2860 RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
2861 page = niu_find_rxpage(rp, addr, &link);
2862
2863 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
2864 RCR_ENTRY_PKTBUFSZ_SHIFT];
2865
2866 off = addr & ~PAGE_MASK;
2867 append_size = rcr_size;
2868 if (num_rcr == 1) {
2869 int ptype;
2870
2871 off += 2;
2872 append_size -= 2;
2873
2874 ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT);
2875 if ((ptype == RCR_PKT_TYPE_TCP ||
2876 ptype == RCR_PKT_TYPE_UDP) &&
2877 !(val & (RCR_ENTRY_NOPORT |
2878 RCR_ENTRY_ERROR)))
2879 skb->ip_summed = CHECKSUM_UNNECESSARY;
2880 else
2881 skb->ip_summed = CHECKSUM_NONE;
2882 }
2883 if (!(val & RCR_ENTRY_MULTI))
2884 append_size = len - skb->len;
2885
2886 niu_rx_skb_append(skb, page, off, append_size);
2887 if ((page->index + rp->rbr_block_size) - rcr_size == addr) {
2888 *link = (struct page *) page->mapping;
2889 np->ops->unmap_page(np->device, page->index,
2890 PAGE_SIZE, DMA_FROM_DEVICE);
2891 page->index = 0;
2892 page->mapping = NULL;
2893 rp->rbr_refill_pending++;
2894 } else
2895 get_page(page);
2896
2897 index = NEXT_RCR(rp, index);
2898 if (!(val & RCR_ENTRY_MULTI))
2899 break;
2900
2901 }
2902 rp->rcr_index = index;
2903
2904 skb_reserve(skb, NET_IP_ALIGN);
2905 __pskb_pull_tail(skb, min(len, NIU_RXPULL_MAX));
2906
2907 rp->rx_packets++;
2908 rp->rx_bytes += skb->len;
2909
2910 skb->protocol = eth_type_trans(skb, np->dev);
2911 netif_receive_skb(skb);
2912
792dd90f
DM		 2913 np->dev->last_rx = jiffies;
2914
a3138df9
DM		 2915 return num_rcr;
2916}
2917
2918static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
2919{
2920 int blocks_per_page = rp->rbr_blocks_per_page;
2921 int err, index = rp->rbr_index;
2922
2923 err = 0;
2924 while (index < (rp->rbr_table_size - blocks_per_page)) {
2925 err = niu_rbr_add_page(np, rp, mask, index);
2926 if (err)
2927 break;
2928
2929 index += blocks_per_page;
2930 }
2931
2932 rp->rbr_index = index;
2933 return err;
2934}
2935
2936static void niu_rbr_free(struct niu *np, struct rx_ring_info *rp)
2937{
2938 int i;
2939
2940 for (i = 0; i < MAX_RBR_RING_SIZE; i++) {
2941 struct page *page;
2942
2943 page = rp->rxhash[i];
2944 while (page) {
2945 struct page *next = (struct page *) page->mapping;
2946 u64 base = page->index;
2947
2948 np->ops->unmap_page(np->device, base, PAGE_SIZE,
2949 DMA_FROM_DEVICE);
2950 page->index = 0;
2951 page->mapping = NULL;
2952
2953 __free_page(page);
2954
2955 page = next;
2956 }
2957 }
2958
2959 for (i = 0; i < rp->rbr_table_size; i++)
2960 rp->rbr[i] = cpu_to_le32(0);
2961 rp->rbr_index = 0;
2962}
2963
2964static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx)
2965{
2966 struct tx_buff_info *tb = &rp->tx_buffs[idx];
2967 struct sk_buff *skb = tb->skb;
2968 struct tx_pkt_hdr *tp;
2969 u64 tx_flags;
2970 int i, len;
2971
2972 tp = (struct tx_pkt_hdr *) skb->data;
2973 tx_flags = le64_to_cpup(&tp->flags);
2974
2975 rp->tx_packets++;
2976 rp->tx_bytes += (((tx_flags & TXHDR_LEN) >> TXHDR_LEN_SHIFT) -
2977 ((tx_flags & TXHDR_PAD) / 2));
2978
2979 len = skb_headlen(skb);
2980 np->ops->unmap_single(np->device, tb->mapping,
2981 len, DMA_TO_DEVICE);
2982
2983 if (le64_to_cpu(rp->descr[idx]) & TX_DESC_MARK)
2984 rp->mark_pending--;
2985
2986 tb->skb = NULL;
2987 do {
2988 idx = NEXT_TX(rp, idx);
2989 len -= MAX_TX_DESC_LEN;
2990 } while (len > 0);
2991
2992 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2993 tb = &rp->tx_buffs[idx];
2994 BUG_ON(tb->skb != NULL);
2995 np->ops->unmap_page(np->device, tb->mapping,
2996 skb_shinfo(skb)->frags[i].size,
2997 DMA_TO_DEVICE);
2998 idx = NEXT_TX(rp, idx);
2999 }
3000
3001 dev_kfree_skb(skb);
3002
3003 return idx;
3004}
3005
3006#define NIU_TX_WAKEUP_THRESH(rp) ((rp)->pending / 4)
3007
3008static void niu_tx_work(struct niu *np, struct tx_ring_info *rp)
3009{
3010 u16 pkt_cnt, tmp;
3011 int cons;
3012 u64 cs;
3013
3014 cs = rp->tx_cs;
3015 if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK))))
3016 goto out;
3017
3018 tmp = pkt_cnt = (cs & TX_CS_PKT_CNT) >> TX_CS_PKT_CNT_SHIFT;
3019 pkt_cnt = (pkt_cnt - rp->last_pkt_cnt) &
3020 (TX_CS_PKT_CNT >> TX_CS_PKT_CNT_SHIFT);
3021
3022 rp->last_pkt_cnt = tmp;
3023
3024 cons = rp->cons;
3025
3026 niudbg(TX_DONE, "%s: niu_tx_work() pkt_cnt[%u] cons[%d]\n",
3027 np->dev->name, pkt_cnt, cons);
3028
3029 while (pkt_cnt--)
3030 cons = release_tx_packet(np, rp, cons);
3031
3032 rp->cons = cons;
3033 smp_mb();
3034
3035out:
3036 if (unlikely(netif_queue_stopped(np->dev) &&
3037 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) {
3038 netif_tx_lock(np->dev);
3039 if (netif_queue_stopped(np->dev) &&
3040 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))
3041 netif_wake_queue(np->dev);
3042 netif_tx_unlock(np->dev);
3043 }
3044}
3045
3046static int niu_rx_work(struct niu *np, struct rx_ring_info *rp, int budget)
3047{
3048 int qlen, rcr_done = 0, work_done = 0;
3049 struct rxdma_mailbox *mbox = rp->mbox;
3050 u64 stat;
3051
3052#if 1
3053 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3054 qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN;
3055#else
3056 stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
3057 qlen = (le64_to_cpup(&mbox->rcrstat_a) & RCRSTAT_A_QLEN);
3058#endif
3059 mbox->rx_dma_ctl_stat = 0;
3060 mbox->rcrstat_a = 0;
3061
3062 niudbg(RX_STATUS, "%s: niu_rx_work(chan[%d]), stat[%llx] qlen=%d\n",
3063 np->dev->name, rp->rx_channel, (unsigned long long) stat, qlen);
3064
3065 rcr_done = work_done = 0;
3066 qlen = min(qlen, budget);
3067 while (work_done < qlen) {
3068 rcr_done += niu_process_rx_pkt(np, rp);
3069 work_done++;
3070 }
3071
3072 if (rp->rbr_refill_pending >= rp->rbr_kick_thresh) {
3073 unsigned int i;
3074
3075 for (i = 0; i < rp->rbr_refill_pending; i++)
3076 niu_rbr_refill(np, rp, GFP_ATOMIC);
3077 rp->rbr_refill_pending = 0;
3078 }
3079
3080 stat = (RX_DMA_CTL_STAT_MEX |
3081 ((u64)work_done << RX_DMA_CTL_STAT_PKTREAD_SHIFT) |
3082 ((u64)rcr_done << RX_DMA_CTL_STAT_PTRREAD_SHIFT));
3083
3084 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat);
3085
3086 return work_done;
3087}
3088
3089static int niu_poll_core(struct niu *np, struct niu_ldg *lp, int budget)
3090{
3091 u64 v0 = lp->v0;
3092 u32 tx_vec = (v0 >> 32);
3093 u32 rx_vec = (v0 & 0xffffffff);
3094 int i, work_done = 0;
3095
3096 niudbg(INTR, "%s: niu_poll_core() v0[%016llx]\n",
3097 np->dev->name, (unsigned long long) v0);
3098
3099 for (i = 0; i < np->num_tx_rings; i++) {
3100 struct tx_ring_info *rp = &np->tx_rings[i];
3101 if (tx_vec & (1 << rp->tx_channel))
3102 niu_tx_work(np, rp);
3103 nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0);
3104 }
3105
3106 for (i = 0; i < np->num_rx_rings; i++) {
3107 struct rx_ring_info *rp = &np->rx_rings[i];
3108
3109 if (rx_vec & (1 << rp->rx_channel)) {
3110 int this_work_done;
3111
3112 this_work_done = niu_rx_work(np, rp,
3113 budget);
3114
3115 budget -= this_work_done;
3116 work_done += this_work_done;
3117 }
3118 nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0);
3119 }
3120
3121 return work_done;
3122}
3123
3124static int niu_poll(struct napi_struct *napi, int budget)
3125{
3126 struct niu_ldg *lp = container_of(napi, struct niu_ldg, napi);
3127 struct niu *np = lp->np;
3128 int work_done;
3129
3130 work_done = niu_poll_core(np, lp, budget);
3131
3132 if (work_done < budget) {
3133 netif_rx_complete(np->dev, napi);
3134 niu_ldg_rearm(np, lp, 1);
3135 }
3136 return work_done;
3137}
3138
3139static void niu_log_rxchan_errors(struct niu *np, struct rx_ring_info *rp,
3140 u64 stat)
3141{
3142 dev_err(np->device, PFX "%s: RX channel %u errors ( ",
3143 np->dev->name, rp->rx_channel);
3144
3145 if (stat & RX_DMA_CTL_STAT_RBR_TMOUT)
3146 printk("RBR_TMOUT ");
3147 if (stat & RX_DMA_CTL_STAT_RSP_CNT_ERR)
3148 printk("RSP_CNT ");
3149 if (stat & RX_DMA_CTL_STAT_BYTE_EN_BUS)
3150 printk("BYTE_EN_BUS ");
3151 if (stat & RX_DMA_CTL_STAT_RSP_DAT_ERR)
3152 printk("RSP_DAT ");
3153 if (stat & RX_DMA_CTL_STAT_RCR_ACK_ERR)
3154 printk("RCR_ACK ");
3155 if (stat & RX_DMA_CTL_STAT_RCR_SHA_PAR)
3156 printk("RCR_SHA_PAR ");
3157 if (stat & RX_DMA_CTL_STAT_RBR_PRE_PAR)
3158 printk("RBR_PRE_PAR ");
3159 if (stat & RX_DMA_CTL_STAT_CONFIG_ERR)
3160 printk("CONFIG ");
3161 if (stat & RX_DMA_CTL_STAT_RCRINCON)
3162 printk("RCRINCON ");
3163 if (stat & RX_DMA_CTL_STAT_RCRFULL)
3164 printk("RCRFULL ");
3165 if (stat & RX_DMA_CTL_STAT_RBRFULL)
3166 printk("RBRFULL ");
3167 if (stat & RX_DMA_CTL_STAT_RBRLOGPAGE)
3168 printk("RBRLOGPAGE ");
3169 if (stat & RX_DMA_CTL_STAT_CFIGLOGPAGE)
3170 printk("CFIGLOGPAGE ");
3171 if (stat & RX_DMA_CTL_STAT_DC_FIFO_ERR)
3172 printk("DC_FIDO ");
3173
3174 printk(")\n");
3175}
3176
3177static int niu_rx_error(struct niu *np, struct rx_ring_info *rp)
3178{
3179 u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3180 int err = 0;
3181
a3138df9
DM		 3182
3183 if (stat & (RX_DMA_CTL_STAT_CHAN_FATAL |
3184 RX_DMA_CTL_STAT_PORT_FATAL))
3185 err = -EINVAL;
3186
406f353c
MW		 3187 if (err) {
3188 dev_err(np->device, PFX "%s: RX channel %u error, stat[%llx]\n",
3189 np->dev->name, rp->rx_channel,
3190 (unsigned long long) stat);
3191
3192 niu_log_rxchan_errors(np, rp, stat);
3193 }
3194
a3138df9
DM		 3195 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
3196 stat & RX_DMA_CTL_WRITE_CLEAR_ERRS);
3197
3198 return err;
3199}
3200
3201static void niu_log_txchan_errors(struct niu *np, struct tx_ring_info *rp,
3202 u64 cs)
3203{
3204 dev_err(np->device, PFX "%s: TX channel %u errors ( ",
3205 np->dev->name, rp->tx_channel);
3206
3207 if (cs & TX_CS_MBOX_ERR)
3208 printk("MBOX ");
3209 if (cs & TX_CS_PKT_SIZE_ERR)
3210 printk("PKT_SIZE ");
3211 if (cs & TX_CS_TX_RING_OFLOW)
3212 printk("TX_RING_OFLOW ");
3213 if (cs & TX_CS_PREF_BUF_PAR_ERR)
3214 printk("PREF_BUF_PAR ");
3215 if (cs & TX_CS_NACK_PREF)
3216 printk("NACK_PREF ");
3217 if (cs & TX_CS_NACK_PKT_RD)
3218 printk("NACK_PKT_RD ");
3219 if (cs & TX_CS_CONF_PART_ERR)
3220 printk("CONF_PART ");
3221 if (cs & TX_CS_PKT_PRT_ERR)
3222 printk("PKT_PTR ");
3223
3224 printk(")\n");
3225}
3226
3227static int niu_tx_error(struct niu *np, struct tx_ring_info *rp)
3228{
3229 u64 cs, logh, logl;
3230
3231 cs = nr64(TX_CS(rp->tx_channel));
3232 logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel));
3233 logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel));
3234
3235 dev_err(np->device, PFX "%s: TX channel %u error, "
3236 "cs[%llx] logh[%llx] logl[%llx]\n",
3237 np->dev->name, rp->tx_channel,
3238 (unsigned long long) cs,
3239 (unsigned long long) logh,
3240 (unsigned long long) logl);
3241
3242 niu_log_txchan_errors(np, rp, cs);
3243
3244 return -ENODEV;
3245}
3246
3247static int niu_mif_interrupt(struct niu *np)
3248{
3249 u64 mif_status = nr64(MIF_STATUS);
3250 int phy_mdint = 0;
3251
3252 if (np->flags & NIU_FLAGS_XMAC) {
3253 u64 xrxmac_stat = nr64_mac(XRXMAC_STATUS);
3254
3255 if (xrxmac_stat & XRXMAC_STATUS_PHY_MDINT)
3256 phy_mdint = 1;
3257 }
3258
3259 dev_err(np->device, PFX "%s: MIF interrupt, "
3260 "stat[%llx] phy_mdint(%d)\n",
3261 np->dev->name, (unsigned long long) mif_status, phy_mdint);
3262
3263 return -ENODEV;
3264}
3265
3266static void niu_xmac_interrupt(struct niu *np)
3267{
3268 struct niu_xmac_stats *mp = &np->mac_stats.xmac;
3269 u64 val;
3270
3271 val = nr64_mac(XTXMAC_STATUS);
3272 if (val & XTXMAC_STATUS_FRAME_CNT_EXP)
3273 mp->tx_frames += TXMAC_FRM_CNT_COUNT;
3274 if (val & XTXMAC_STATUS_BYTE_CNT_EXP)
3275 mp->tx_bytes += TXMAC_BYTE_CNT_COUNT;
3276 if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR)
3277 mp->tx_fifo_errors++;
3278 if (val & XTXMAC_STATUS_TXMAC_OFLOW)
3279 mp->tx_overflow_errors++;
3280 if (val & XTXMAC_STATUS_MAX_PSIZE_ERR)
3281 mp->tx_max_pkt_size_errors++;
3282 if (val & XTXMAC_STATUS_TXMAC_UFLOW)
3283 mp->tx_underflow_errors++;
3284
3285 val = nr64_mac(XRXMAC_STATUS);
3286 if (val & XRXMAC_STATUS_LCL_FLT_STATUS)
3287 mp->rx_local_faults++;
3288 if (val & XRXMAC_STATUS_RFLT_DET)
3289 mp->rx_remote_faults++;
3290 if (val & XRXMAC_STATUS_LFLT_CNT_EXP)
3291 mp->rx_link_faults += LINK_FAULT_CNT_COUNT;
3292 if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP)
3293 mp->rx_align_errors += RXMAC_ALIGN_ERR_CNT_COUNT;
3294 if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP)
3295 mp->rx_frags += RXMAC_FRAG_CNT_COUNT;
3296 if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP)
3297 mp->rx_mcasts += RXMAC_MC_FRM_CNT_COUNT;
3298 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3299 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3300 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3301 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3302 if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP)
3303 mp->rx_hist_cnt1 += RXMAC_HIST_CNT1_COUNT;
3304 if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP)
3305 mp->rx_hist_cnt2 += RXMAC_HIST_CNT2_COUNT;
3306 if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP)
3307 mp->rx_hist_cnt3 += RXMAC_HIST_CNT3_COUNT;
3308 if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP)
3309 mp->rx_hist_cnt4 += RXMAC_HIST_CNT4_COUNT;
3310 if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP)
3311 mp->rx_hist_cnt5 += RXMAC_HIST_CNT5_COUNT;
3312 if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP)
3313 mp->rx_hist_cnt6 += RXMAC_HIST_CNT6_COUNT;
3314 if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP)
3315 mp->rx_hist_cnt7 += RXMAC_HIST_CNT7_COUNT;
3316 if (val & XRXMAC_STAT_MSK_RXOCTET_CNT_EXP)
3317 mp->rx_octets += RXMAC_BT_CNT_COUNT;
3318 if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP)
3319 mp->rx_code_violations += RXMAC_CD_VIO_CNT_COUNT;
3320 if (val & XRXMAC_STATUS_LENERR_CNT_EXP)
3321 mp->rx_len_errors += RXMAC_MPSZER_CNT_COUNT;
3322 if (val & XRXMAC_STATUS_CRCERR_CNT_EXP)
3323 mp->rx_crc_errors += RXMAC_CRC_ER_CNT_COUNT;
3324 if (val & XRXMAC_STATUS_RXUFLOW)
3325 mp->rx_underflows++;
3326 if (val & XRXMAC_STATUS_RXOFLOW)
3327 mp->rx_overflows++;
3328
3329 val = nr64_mac(XMAC_FC_STAT);
3330 if (val & XMAC_FC_STAT_TX_MAC_NPAUSE)
3331 mp->pause_off_state++;
3332 if (val & XMAC_FC_STAT_TX_MAC_PAUSE)
3333 mp->pause_on_state++;
3334 if (val & XMAC_FC_STAT_RX_MAC_RPAUSE)
3335 mp->pause_received++;
3336}
3337
3338static void niu_bmac_interrupt(struct niu *np)
3339{
3340 struct niu_bmac_stats *mp = &np->mac_stats.bmac;
3341 u64 val;
3342
3343 val = nr64_mac(BTXMAC_STATUS);
3344 if (val & BTXMAC_STATUS_UNDERRUN)
3345 mp->tx_underflow_errors++;
3346 if (val & BTXMAC_STATUS_MAX_PKT_ERR)
3347 mp->tx_max_pkt_size_errors++;
3348 if (val & BTXMAC_STATUS_BYTE_CNT_EXP)
3349 mp->tx_bytes += BTXMAC_BYTE_CNT_COUNT;
3350 if (val & BTXMAC_STATUS_FRAME_CNT_EXP)
3351 mp->tx_frames += BTXMAC_FRM_CNT_COUNT;
3352
3353 val = nr64_mac(BRXMAC_STATUS);
3354 if (val & BRXMAC_STATUS_OVERFLOW)
3355 mp->rx_overflows++;
3356 if (val & BRXMAC_STATUS_FRAME_CNT_EXP)
3357 mp->rx_frames += BRXMAC_FRAME_CNT_COUNT;
3358 if (val & BRXMAC_STATUS_ALIGN_ERR_EXP)
3359 mp->rx_align_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
3360 if (val & BRXMAC_STATUS_CRC_ERR_EXP)
3361 mp->rx_crc_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
3362 if (val & BRXMAC_STATUS_LEN_ERR_EXP)
3363 mp->rx_len_errors += BRXMAC_CODE_VIOL_ERR_CNT_COUNT;
3364
3365 val = nr64_mac(BMAC_CTRL_STATUS);
3366 if (val & BMAC_CTRL_STATUS_NOPAUSE)
3367 mp->pause_off_state++;
3368 if (val & BMAC_CTRL_STATUS_PAUSE)
3369 mp->pause_on_state++;
3370 if (val & BMAC_CTRL_STATUS_PAUSE_RECV)
3371 mp->pause_received++;
3372}
3373
3374static int niu_mac_interrupt(struct niu *np)
3375{
3376 if (np->flags & NIU_FLAGS_XMAC)
3377 niu_xmac_interrupt(np);
3378 else
3379 niu_bmac_interrupt(np);
3380
3381 return 0;
3382}
3383
3384static void niu_log_device_error(struct niu *np, u64 stat)
3385{
3386 dev_err(np->device, PFX "%s: Core device errors ( ",
3387 np->dev->name);
3388
3389 if (stat & SYS_ERR_MASK_META2)
3390 printk("META2 ");
3391 if (stat & SYS_ERR_MASK_META1)
3392 printk("META1 ");
3393 if (stat & SYS_ERR_MASK_PEU)
3394 printk("PEU ");
3395 if (stat & SYS_ERR_MASK_TXC)
3396 printk("TXC ");
3397 if (stat & SYS_ERR_MASK_RDMC)
3398 printk("RDMC ");
3399 if (stat & SYS_ERR_MASK_TDMC)
3400 printk("TDMC ");
3401 if (stat & SYS_ERR_MASK_ZCP)
3402 printk("ZCP ");
3403 if (stat & SYS_ERR_MASK_FFLP)
3404 printk("FFLP ");
3405 if (stat & SYS_ERR_MASK_IPP)
3406 printk("IPP ");
3407 if (stat & SYS_ERR_MASK_MAC)
3408 printk("MAC ");
3409 if (stat & SYS_ERR_MASK_SMX)
3410 printk("SMX ");
3411
3412 printk(")\n");
3413}
3414
3415static int niu_device_error(struct niu *np)
3416{
3417 u64 stat = nr64(SYS_ERR_STAT);
3418
3419 dev_err(np->device, PFX "%s: Core device error, stat[%llx]\n",
3420 np->dev->name, (unsigned long long) stat);
3421
3422 niu_log_device_error(np, stat);
3423
3424 return -ENODEV;
3425}
3426
406f353c
MW		 3427static int niu_slowpath_interrupt(struct niu *np, struct niu_ldg *lp,
3428 u64 v0, u64 v1, u64 v2)
a3138df9 3429{
406f353c 3430
a3138df9
DM		 3431 int i, err = 0;
3432
406f353c
MW		 3433 lp->v0 = v0;
3434 lp->v1 = v1;
3435 lp->v2 = v2;
3436
a3138df9
DM		 3437 if (v1 & 0x00000000ffffffffULL) {
3438 u32 rx_vec = (v1 & 0xffffffff);
3439
3440 for (i = 0; i < np->num_rx_rings; i++) {
3441 struct rx_ring_info *rp = &np->rx_rings[i];
3442
3443 if (rx_vec & (1 << rp->rx_channel)) {
3444 int r = niu_rx_error(np, rp);
406f353c 3445 if (r) {
a3138df9 3446 err = r;
406f353c
MW		 3447 } else {
3448 if (!v0)
3449 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
3450 RX_DMA_CTL_STAT_MEX);
3451 }
a3138df9
DM		 3452 }
3453 }
3454 }
3455 if (v1 & 0x7fffffff00000000ULL) {
3456 u32 tx_vec = (v1 >> 32) & 0x7fffffff;
3457
3458 for (i = 0; i < np->num_tx_rings; i++) {
3459 struct tx_ring_info *rp = &np->tx_rings[i];
3460
3461 if (tx_vec & (1 << rp->tx_channel)) {
3462 int r = niu_tx_error(np, rp);
3463 if (r)
3464 err = r;
3465 }
3466 }
3467 }
3468 if ((v0 | v1) & 0x8000000000000000ULL) {
3469 int r = niu_mif_interrupt(np);
3470 if (r)
3471 err = r;
3472 }
3473 if (v2) {
3474 if (v2 & 0x01ef) {
3475 int r = niu_mac_interrupt(np);
3476 if (r)
3477 err = r;
3478 }
3479 if (v2 & 0x0210) {
3480 int r = niu_device_error(np);
3481 if (r)
3482 err = r;
3483 }
3484 }
3485
3486 if (err)
3487 niu_enable_interrupts(np, 0);
3488
406f353c 3489 return err;
a3138df9
DM		 3490}
3491
3492static void niu_rxchan_intr(struct niu *np, struct rx_ring_info *rp,
3493 int ldn)
3494{
3495 struct rxdma_mailbox *mbox = rp->mbox;
3496 u64 stat_write, stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
3497
3498 stat_write = (RX_DMA_CTL_STAT_RCRTHRES |
3499 RX_DMA_CTL_STAT_RCRTO);
3500 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write);
3501
3502 niudbg(INTR, "%s: rxchan_intr stat[%llx]\n",
3503 np->dev->name, (unsigned long long) stat);
3504}
3505
3506static void niu_txchan_intr(struct niu *np, struct tx_ring_info *rp,
3507 int ldn)
3508{
3509 rp->tx_cs = nr64(TX_CS(rp->tx_channel));
3510
3511 niudbg(INTR, "%s: txchan_intr cs[%llx]\n",
3512 np->dev->name, (unsigned long long) rp->tx_cs);
3513}
3514
3515static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0)
3516{
3517 struct niu_parent *parent = np->parent;
3518 u32 rx_vec, tx_vec;
3519 int i;
3520
3521 tx_vec = (v0 >> 32);
3522 rx_vec = (v0 & 0xffffffff);
3523
3524 for (i = 0; i < np->num_rx_rings; i++) {
3525 struct rx_ring_info *rp = &np->rx_rings[i];
3526 int ldn = LDN_RXDMA(rp->rx_channel);
3527
3528 if (parent->ldg_map[ldn] != ldg)
3529 continue;
3530
3531 nw64(LD_IM0(ldn), LD_IM0_MASK);
3532 if (rx_vec & (1 << rp->rx_channel))
3533 niu_rxchan_intr(np, rp, ldn);
3534 }
3535
3536 for (i = 0; i < np->num_tx_rings; i++) {
3537 struct tx_ring_info *rp = &np->tx_rings[i];
3538 int ldn = LDN_TXDMA(rp->tx_channel);
3539
3540 if (parent->ldg_map[ldn] != ldg)
3541 continue;
3542
3543 nw64(LD_IM0(ldn), LD_IM0_MASK);
3544 if (tx_vec & (1 << rp->tx_channel))
3545 niu_txchan_intr(np, rp, ldn);
3546 }
3547}
3548
3549static void niu_schedule_napi(struct niu *np, struct niu_ldg *lp,
3550 u64 v0, u64 v1, u64 v2)
3551{
3552 if (likely(netif_rx_schedule_prep(np->dev, &lp->napi))) {
3553 lp->v0 = v0;
3554 lp->v1 = v1;
3555 lp->v2 = v2;
3556 __niu_fastpath_interrupt(np, lp->ldg_num, v0);
3557 __netif_rx_schedule(np->dev, &lp->napi);
3558 }
3559}
3560
3561static irqreturn_t niu_interrupt(int irq, void *dev_id)
3562{
3563 struct niu_ldg *lp = dev_id;
3564 struct niu *np = lp->np;
3565 int ldg = lp->ldg_num;
3566 unsigned long flags;
3567 u64 v0, v1, v2;
3568
3569 if (netif_msg_intr(np))
3570 printk(KERN_DEBUG PFX "niu_interrupt() ldg[%p](%d) ",
3571 lp, ldg);
3572
3573 spin_lock_irqsave(&np->lock, flags);
3574
3575 v0 = nr64(LDSV0(ldg));
3576 v1 = nr64(LDSV1(ldg));
3577 v2 = nr64(LDSV2(ldg));
3578
3579 if (netif_msg_intr(np))
3580 printk("v0[%llx] v1[%llx] v2[%llx]\n",
3581 (unsigned long long) v0,
3582 (unsigned long long) v1,
3583 (unsigned long long) v2);
3584
3585 if (unlikely(!v0 && !v1 && !v2)) {
3586 spin_unlock_irqrestore(&np->lock, flags);
3587 return IRQ_NONE;
3588 }
3589
3590 if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) {
406f353c 3591 int err = niu_slowpath_interrupt(np, lp, v0, v1, v2);
a3138df9
DM		 3592 if (err)
3593 goto out;
3594 }
3595 if (likely(v0 & ~((u64)1 << LDN_MIF)))
3596 niu_schedule_napi(np, lp, v0, v1, v2);
3597 else
3598 niu_ldg_rearm(np, lp, 1);
3599out:
3600 spin_unlock_irqrestore(&np->lock, flags);
3601
3602 return IRQ_HANDLED;
3603}
3604
3605static void niu_free_rx_ring_info(struct niu *np, struct rx_ring_info *rp)
3606{
3607 if (rp->mbox) {
3608 np->ops->free_coherent(np->device,
3609 sizeof(struct rxdma_mailbox),
3610 rp->mbox, rp->mbox_dma);
3611 rp->mbox = NULL;
3612 }
3613 if (rp->rcr) {
3614 np->ops->free_coherent(np->device,
3615 MAX_RCR_RING_SIZE * sizeof(__le64),
3616 rp->rcr, rp->rcr_dma);
3617 rp->rcr = NULL;
3618 rp->rcr_table_size = 0;
3619 rp->rcr_index = 0;
3620 }
3621 if (rp->rbr) {
3622 niu_rbr_free(np, rp);
3623
3624 np->ops->free_coherent(np->device,
3625 MAX_RBR_RING_SIZE * sizeof(__le32),
3626 rp->rbr, rp->rbr_dma);
3627 rp->rbr = NULL;
3628 rp->rbr_table_size = 0;
3629 rp->rbr_index = 0;
3630 }
3631 kfree(rp->rxhash);
3632 rp->rxhash = NULL;
3633}
3634
3635static void niu_free_tx_ring_info(struct niu *np, struct tx_ring_info *rp)
3636{
3637 if (rp->mbox) {
3638 np->ops->free_coherent(np->device,
3639 sizeof(struct txdma_mailbox),
3640 rp->mbox, rp->mbox_dma);
3641 rp->mbox = NULL;
3642 }
3643 if (rp->descr) {
3644 int i;
3645
3646 for (i = 0; i < MAX_TX_RING_SIZE; i++) {
3647 if (rp->tx_buffs[i].skb)
3648 (void) release_tx_packet(np, rp, i);
3649 }
3650
3651 np->ops->free_coherent(np->device,
3652 MAX_TX_RING_SIZE * sizeof(__le64),
3653 rp->descr, rp->descr_dma);
3654 rp->descr = NULL;
3655 rp->pending = 0;
3656 rp->prod = 0;
3657 rp->cons = 0;
3658 rp->wrap_bit = 0;
3659 }
3660}
3661
3662static void niu_free_channels(struct niu *np)
3663{
3664 int i;
3665
3666 if (np->rx_rings) {
3667 for (i = 0; i < np->num_rx_rings; i++) {
3668 struct rx_ring_info *rp = &np->rx_rings[i];
3669
3670 niu_free_rx_ring_info(np, rp);
3671 }
3672 kfree(np->rx_rings);
3673 np->rx_rings = NULL;
3674 np->num_rx_rings = 0;
3675 }
3676
3677 if (np->tx_rings) {
3678 for (i = 0; i < np->num_tx_rings; i++) {
3679 struct tx_ring_info *rp = &np->tx_rings[i];
3680
3681 niu_free_tx_ring_info(np, rp);
3682 }
3683 kfree(np->tx_rings);
3684 np->tx_rings = NULL;
3685 np->num_tx_rings = 0;
3686 }
3687}
3688
3689static int niu_alloc_rx_ring_info(struct niu *np,
3690 struct rx_ring_info *rp)
3691{
3692 BUILD_BUG_ON(sizeof(struct rxdma_mailbox) != 64);
3693
3694 rp->rxhash = kzalloc(MAX_RBR_RING_SIZE * sizeof(struct page *),
3695 GFP_KERNEL);
3696 if (!rp->rxhash)
3697 return -ENOMEM;
3698
3699 rp->mbox = np->ops->alloc_coherent(np->device,
3700 sizeof(struct rxdma_mailbox),
3701 &rp->mbox_dma, GFP_KERNEL);
3702 if (!rp->mbox)
3703 return -ENOMEM;
3704 if ((unsigned long)rp->mbox & (64UL - 1)) {
3705 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
3706 "RXDMA mailbox %p\n", np->dev->name, rp->mbox);
3707 return -EINVAL;
3708 }
3709
3710 rp->rcr = np->ops->alloc_coherent(np->device,
3711 MAX_RCR_RING_SIZE * sizeof(__le64),
3712 &rp->rcr_dma, GFP_KERNEL);
3713 if (!rp->rcr)
3714 return -ENOMEM;
3715 if ((unsigned long)rp->rcr & (64UL - 1)) {
3716 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
3717 "RXDMA RCR table %p\n", np->dev->name, rp->rcr);
3718 return -EINVAL;
3719 }
3720 rp->rcr_table_size = MAX_RCR_RING_SIZE;
3721 rp->rcr_index = 0;
3722
3723 rp->rbr = np->ops->alloc_coherent(np->device,
3724 MAX_RBR_RING_SIZE * sizeof(__le32),
3725 &rp->rbr_dma, GFP_KERNEL);
3726 if (!rp->rbr)
3727 return -ENOMEM;
3728 if ((unsigned long)rp->rbr & (64UL - 1)) {
3729 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
3730 "RXDMA RBR table %p\n", np->dev->name, rp->rbr);
3731 return -EINVAL;
3732 }
3733 rp->rbr_table_size = MAX_RBR_RING_SIZE;
3734 rp->rbr_index = 0;
3735 rp->rbr_pending = 0;
3736
3737 return 0;
3738}
3739
3740static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp)
3741{
3742 int mtu = np->dev->mtu;
3743
3744 /* These values are recommended by the HW designers for fair
3745 * utilization of DRR amongst the rings.
3746 */
3747 rp->max_burst = mtu + 32;
3748 if (rp->max_burst > 4096)
3749 rp->max_burst = 4096;
3750}
3751
3752static int niu_alloc_tx_ring_info(struct niu *np,
3753 struct tx_ring_info *rp)
3754{
3755 BUILD_BUG_ON(sizeof(struct txdma_mailbox) != 64);
3756
3757 rp->mbox = np->ops->alloc_coherent(np->device,
3758 sizeof(struct txdma_mailbox),
3759 &rp->mbox_dma, GFP_KERNEL);
3760 if (!rp->mbox)
3761 return -ENOMEM;
3762 if ((unsigned long)rp->mbox & (64UL - 1)) {
3763 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
3764 "TXDMA mailbox %p\n", np->dev->name, rp->mbox);
3765 return -EINVAL;
3766 }
3767
3768 rp->descr = np->ops->alloc_coherent(np->device,
3769 MAX_TX_RING_SIZE * sizeof(__le64),
3770 &rp->descr_dma, GFP_KERNEL);
3771 if (!rp->descr)
3772 return -ENOMEM;
3773 if ((unsigned long)rp->descr & (64UL - 1)) {
3774 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
3775 "TXDMA descr table %p\n", np->dev->name, rp->descr);
3776 return -EINVAL;
3777 }
3778
3779 rp->pending = MAX_TX_RING_SIZE;
3780 rp->prod = 0;
3781 rp->cons = 0;
3782 rp->wrap_bit = 0;
3783
3784 /* XXX make these configurable... XXX */
3785 rp->mark_freq = rp->pending / 4;
3786
3787 niu_set_max_burst(np, rp);
3788
3789 return 0;
3790}
3791
3792static void niu_size_rbr(struct niu *np, struct rx_ring_info *rp)
3793{
81429973 3794 u16 bss;
a3138df9 3795
81429973 3796 bss = min(PAGE_SHIFT, 15);
a3138df9 3797
81429973
OJ		 3798 rp->rbr_block_size = 1 << bss;
3799 rp->rbr_blocks_per_page = 1 << (PAGE_SHIFT-bss);
a3138df9
DM		 3800
3801 rp->rbr_sizes[0] = 256;
3802 rp->rbr_sizes[1] = 1024;
3803 if (np->dev->mtu > ETH_DATA_LEN) {
3804 switch (PAGE_SIZE) {
3805 case 4 * 1024:
3806 rp->rbr_sizes[2] = 4096;
3807 break;
3808
3809 default:
3810 rp->rbr_sizes[2] = 8192;
3811 break;
3812 }
3813 } else {
3814 rp->rbr_sizes[2] = 2048;
3815 }
3816 rp->rbr_sizes[3] = rp->rbr_block_size;
3817}
3818
3819static int niu_alloc_channels(struct niu *np)
3820{
3821 struct niu_parent *parent = np->parent;
3822 int first_rx_channel, first_tx_channel;
3823 int i, port, err;
3824
3825 port = np->port;
3826 first_rx_channel = first_tx_channel = 0;
3827 for (i = 0; i < port; i++) {
3828 first_rx_channel += parent->rxchan_per_port[i];
3829 first_tx_channel += parent->txchan_per_port[i];
3830 }
3831
3832 np->num_rx_rings = parent->rxchan_per_port[port];
3833 np->num_tx_rings = parent->txchan_per_port[port];
3834
3835 np->rx_rings = kzalloc(np->num_rx_rings * sizeof(struct rx_ring_info),
3836 GFP_KERNEL);
3837 err = -ENOMEM;
3838 if (!np->rx_rings)
3839 goto out_err;
3840
3841 for (i = 0; i < np->num_rx_rings; i++) {
3842 struct rx_ring_info *rp = &np->rx_rings[i];
3843
3844 rp->np = np;
3845 rp->rx_channel = first_rx_channel + i;
3846
3847 err = niu_alloc_rx_ring_info(np, rp);
3848 if (err)
3849 goto out_err;
3850
3851 niu_size_rbr(np, rp);
3852
3853 /* XXX better defaults, configurable, etc... XXX */
3854 rp->nonsyn_window = 64;
3855 rp->nonsyn_threshold = rp->rcr_table_size - 64;
3856 rp->syn_window = 64;
3857 rp->syn_threshold = rp->rcr_table_size - 64;
3858 rp->rcr_pkt_threshold = 16;
3859 rp->rcr_timeout = 8;
3860 rp->rbr_kick_thresh = RBR_REFILL_MIN;
3861 if (rp->rbr_kick_thresh < rp->rbr_blocks_per_page)
3862 rp->rbr_kick_thresh = rp->rbr_blocks_per_page;
3863
3864 err = niu_rbr_fill(np, rp, GFP_KERNEL);
3865 if (err)
3866 return err;
3867 }
3868
3869 np->tx_rings = kzalloc(np->num_tx_rings * sizeof(struct tx_ring_info),
3870 GFP_KERNEL);
3871 err = -ENOMEM;
3872 if (!np->tx_rings)
3873 goto out_err;
3874
3875 for (i = 0; i < np->num_tx_rings; i++) {
3876 struct tx_ring_info *rp = &np->tx_rings[i];
3877
3878 rp->np = np;
3879 rp->tx_channel = first_tx_channel + i;
3880
3881 err = niu_alloc_tx_ring_info(np, rp);
3882 if (err)
3883 goto out_err;
3884 }
3885
3886 return 0;
3887
3888out_err:
3889 niu_free_channels(np);
3890 return err;
3891}
3892
3893static int niu_tx_cs_sng_poll(struct niu *np, int channel)
3894{
3895 int limit = 1000;
3896
3897 while (--limit > 0) {
3898 u64 val = nr64(TX_CS(channel));
3899 if (val & TX_CS_SNG_STATE)
3900 return 0;
3901 }
3902 return -ENODEV;
3903}
3904
3905static int niu_tx_channel_stop(struct niu *np, int channel)
3906{
3907 u64 val = nr64(TX_CS(channel));
3908
3909 val |= TX_CS_STOP_N_GO;
3910 nw64(TX_CS(channel), val);
3911
3912 return niu_tx_cs_sng_poll(np, channel);
3913}
3914
3915static int niu_tx_cs_reset_poll(struct niu *np, int channel)
3916{
3917 int limit = 1000;
3918
3919 while (--limit > 0) {
3920 u64 val = nr64(TX_CS(channel));
3921 if (!(val & TX_CS_RST))
3922 return 0;
3923 }
3924 return -ENODEV;
3925}
3926
3927static int niu_tx_channel_reset(struct niu *np, int channel)
3928{
3929 u64 val = nr64(TX_CS(channel));
3930 int err;
3931
3932 val |= TX_CS_RST;
3933 nw64(TX_CS(channel), val);
3934
3935 err = niu_tx_cs_reset_poll(np, channel);
3936 if (!err)
3937 nw64(TX_RING_KICK(channel), 0);
3938
3939 return err;
3940}
3941
3942static int niu_tx_channel_lpage_init(struct niu *np, int channel)
3943{
3944 u64 val;
3945
3946 nw64(TX_LOG_MASK1(channel), 0);
3947 nw64(TX_LOG_VAL1(channel), 0);
3948 nw64(TX_LOG_MASK2(channel), 0);
3949 nw64(TX_LOG_VAL2(channel), 0);
3950 nw64(TX_LOG_PAGE_RELO1(channel), 0);
3951 nw64(TX_LOG_PAGE_RELO2(channel), 0);
3952 nw64(TX_LOG_PAGE_HDL(channel), 0);
3953
3954 val = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT;
3955 val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1);
3956 nw64(TX_LOG_PAGE_VLD(channel), val);
3957
3958 /* XXX TXDMA 32bit mode? XXX */
3959
3960 return 0;
3961}
3962
3963static void niu_txc_enable_port(struct niu *np, int on)
3964{
3965 unsigned long flags;
3966 u64 val, mask;
3967
3968 niu_lock_parent(np, flags);
3969 val = nr64(TXC_CONTROL);
3970 mask = (u64)1 << np->port;
3971 if (on) {
3972 val |= TXC_CONTROL_ENABLE | mask;
3973 } else {
3974 val &= ~mask;
3975 if ((val & ~TXC_CONTROL_ENABLE) == 0)
3976 val &= ~TXC_CONTROL_ENABLE;
3977 }
3978 nw64(TXC_CONTROL, val);
3979 niu_unlock_parent(np, flags);
3980}
3981
3982static void niu_txc_set_imask(struct niu *np, u64 imask)
3983{
3984 unsigned long flags;
3985 u64 val;
3986
3987 niu_lock_parent(np, flags);
3988 val = nr64(TXC_INT_MASK);
3989 val &= ~TXC_INT_MASK_VAL(np->port);
3990 val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port));
3991 niu_unlock_parent(np, flags);
3992}
3993
3994static void niu_txc_port_dma_enable(struct niu *np, int on)
3995{
3996 u64 val = 0;
3997
3998 if (on) {
3999 int i;
4000
4001 for (i = 0; i < np->num_tx_rings; i++)
4002 val |= (1 << np->tx_rings[i].tx_channel);
4003 }
4004 nw64(TXC_PORT_DMA(np->port), val);
4005}
4006
4007static int niu_init_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
4008{
4009 int err, channel = rp->tx_channel;
4010 u64 val, ring_len;
4011
4012 err = niu_tx_channel_stop(np, channel);
4013 if (err)
4014 return err;
4015
4016 err = niu_tx_channel_reset(np, channel);
4017 if (err)
4018 return err;
4019
4020 err = niu_tx_channel_lpage_init(np, channel);
4021 if (err)
4022 return err;
4023
4024 nw64(TXC_DMA_MAX(channel), rp->max_burst);
4025 nw64(TX_ENT_MSK(channel), 0);
4026
4027 if (rp->descr_dma & ~(TX_RNG_CFIG_STADDR_BASE |
4028 TX_RNG_CFIG_STADDR)) {
4029 dev_err(np->device, PFX "%s: TX ring channel %d "
4030 "DMA addr (%llx) is not aligned.\n",
4031 np->dev->name, channel,
4032 (unsigned long long) rp->descr_dma);
4033 return -EINVAL;
4034 }
4035
4036 /* The length field in TX_RNG_CFIG is measured in 64-byte
4037 * blocks. rp->pending is the number of TX descriptors in
4038 * our ring, 8 bytes each, thus we divide by 8 bytes more
4039 * to get the proper value the chip wants.
4040 */
4041 ring_len = (rp->pending / 8);
4042
4043 val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) |
4044 rp->descr_dma);
4045 nw64(TX_RNG_CFIG(channel), val);
4046
4047 if (((rp->mbox_dma >> 32) & ~TXDMA_MBH_MBADDR) ||
4048 ((u32)rp->mbox_dma & ~TXDMA_MBL_MBADDR)) {
4049 dev_err(np->device, PFX "%s: TX ring channel %d "
4050 "MBOX addr (%llx) is has illegal bits.\n",
4051 np->dev->name, channel,
4052 (unsigned long long) rp->mbox_dma);
4053 return -EINVAL;
4054 }
4055 nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32);
4056 nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR);
4057
4058 nw64(TX_CS(channel), 0);
4059
4060 rp->last_pkt_cnt = 0;
4061
4062 return 0;
4063}
4064
4065static void niu_init_rdc_groups(struct niu *np)
4066{
4067 struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port];
4068 int i, first_table_num = tp->first_table_num;
4069
4070 for (i = 0; i < tp->num_tables; i++) {
4071 struct rdc_table *tbl = &tp->tables[i];
4072 int this_table = first_table_num + i;
4073 int slot;
4074
4075 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++)
4076 nw64(RDC_TBL(this_table, slot),
4077 tbl->rxdma_channel[slot]);
4078 }
4079
4080 nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]);
4081}
4082
4083static void niu_init_drr_weight(struct niu *np)
4084{
4085 int type = phy_decode(np->parent->port_phy, np->port);
4086 u64 val;
4087
4088 switch (type) {
4089 case PORT_TYPE_10G:
4090 val = PT_DRR_WEIGHT_DEFAULT_10G;
4091 break;
4092
4093 case PORT_TYPE_1G:
4094 default:
4095 val = PT_DRR_WEIGHT_DEFAULT_1G;
4096 break;
4097 }
4098 nw64(PT_DRR_WT(np->port), val);
4099}
4100
4101static int niu_init_hostinfo(struct niu *np)
4102{
4103 struct niu_parent *parent = np->parent;
4104 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
4105 int i, err, num_alt = niu_num_alt_addr(np);
4106 int first_rdc_table = tp->first_table_num;
4107
4108 err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
4109 if (err)
4110 return err;
4111
4112 err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
4113 if (err)
4114 return err;
4115
4116 for (i = 0; i < num_alt; i++) {
4117 err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1);
4118 if (err)
4119 return err;
4120 }
4121
4122 return 0;
4123}
4124
4125static int niu_rx_channel_reset(struct niu *np, int channel)
4126{
4127 return niu_set_and_wait_clear(np, RXDMA_CFIG1(channel),
4128 RXDMA_CFIG1_RST, 1000, 10,
4129 "RXDMA_CFIG1");
4130}
4131
4132static int niu_rx_channel_lpage_init(struct niu *np, int channel)
4133{
4134 u64 val;
4135
4136 nw64(RX_LOG_MASK1(channel), 0);
4137 nw64(RX_LOG_VAL1(channel), 0);
4138 nw64(RX_LOG_MASK2(channel), 0);
4139 nw64(RX_LOG_VAL2(channel), 0);
4140 nw64(RX_LOG_PAGE_RELO1(channel), 0);
4141 nw64(RX_LOG_PAGE_RELO2(channel), 0);
4142 nw64(RX_LOG_PAGE_HDL(channel), 0);
4143
4144 val = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT;
4145 val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1);
4146 nw64(RX_LOG_PAGE_VLD(channel), val);
4147
4148 return 0;
4149}
4150
4151static void niu_rx_channel_wred_init(struct niu *np, struct rx_ring_info *rp)
4152{
4153 u64 val;
4154
4155 val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) |
4156 ((u64)rp->nonsyn_threshold << RDC_RED_PARA_THRE_SHIFT) |
4157 ((u64)rp->syn_window << RDC_RED_PARA_WIN_SYN_SHIFT) |
4158 ((u64)rp->syn_threshold << RDC_RED_PARA_THRE_SYN_SHIFT));
4159 nw64(RDC_RED_PARA(rp->rx_channel), val);
4160}
4161
4162static int niu_compute_rbr_cfig_b(struct rx_ring_info *rp, u64 *ret)
4163{
4164 u64 val = 0;
4165
4166 switch (rp->rbr_block_size) {
4167 case 4 * 1024:
4168 val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT);
4169 break;
4170 case 8 * 1024:
4171 val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT);
4172 break;
4173 case 16 * 1024:
4174 val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT);
4175 break;
4176 case 32 * 1024:
4177 val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT);
4178 break;
4179 default:
4180 return -EINVAL;
4181 }
4182 val |= RBR_CFIG_B_VLD2;
4183 switch (rp->rbr_sizes[2]) {
4184 case 2 * 1024:
4185 val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT);
4186 break;
4187 case 4 * 1024:
4188 val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT);
4189 break;
4190 case 8 * 1024:
4191 val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT);
4192 break;
4193 case 16 * 1024:
4194 val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT);
4195 break;
4196
4197 default:
4198 return -EINVAL;
4199 }
4200 val |= RBR_CFIG_B_VLD1;
4201 switch (rp->rbr_sizes[1]) {
4202 case 1 * 1024:
4203 val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT);
4204 break;
4205 case 2 * 1024:
4206 val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT);
4207 break;
4208 case 4 * 1024:
4209 val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT);
4210 break;
4211 case 8 * 1024:
4212 val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT);
4213 break;
4214
4215 default:
4216 return -EINVAL;
4217 }
4218 val |= RBR_CFIG_B_VLD0;
4219 switch (rp->rbr_sizes[0]) {
4220 case 256:
4221 val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT);
4222 break;
4223 case 512:
4224 val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT);
4225 break;
4226 case 1 * 1024:
4227 val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT);
4228 break;
4229 case 2 * 1024:
4230 val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT);
4231 break;
4232
4233 default:
4234 return -EINVAL;
4235 }
4236
4237 *ret = val;
4238 return 0;
4239}
4240
4241static int niu_enable_rx_channel(struct niu *np, int channel, int on)
4242{
4243 u64 val = nr64(RXDMA_CFIG1(channel));
4244 int limit;
4245
4246 if (on)
4247 val |= RXDMA_CFIG1_EN;
4248 else
4249 val &= ~RXDMA_CFIG1_EN;
4250 nw64(RXDMA_CFIG1(channel), val);
4251
4252 limit = 1000;
4253 while (--limit > 0) {
4254 if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST)
4255 break;
4256 udelay(10);
4257 }
4258 if (limit <= 0)
4259 return -ENODEV;
4260 return 0;
4261}
4262
4263static int niu_init_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
4264{
4265 int err, channel = rp->rx_channel;
4266 u64 val;
4267
4268 err = niu_rx_channel_reset(np, channel);
4269 if (err)
4270 return err;
4271
4272 err = niu_rx_channel_lpage_init(np, channel);
4273 if (err)
4274 return err;
4275
4276 niu_rx_channel_wred_init(np, rp);
4277
4278 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY);
4279 nw64(RX_DMA_CTL_STAT(channel),
4280 (RX_DMA_CTL_STAT_MEX |
4281 RX_DMA_CTL_STAT_RCRTHRES |
4282 RX_DMA_CTL_STAT_RCRTO |
4283 RX_DMA_CTL_STAT_RBR_EMPTY));
4284 nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32);
4285 nw64(RXDMA_CFIG2(channel), (rp->mbox_dma & 0x00000000ffffffc0));
4286 nw64(RBR_CFIG_A(channel),
4287 ((u64)rp->rbr_table_size << RBR_CFIG_A_LEN_SHIFT) |
4288 (rp->rbr_dma & (RBR_CFIG_A_STADDR_BASE | RBR_CFIG_A_STADDR)));
4289 err = niu_compute_rbr_cfig_b(rp, &val);
4290 if (err)
4291 return err;
4292 nw64(RBR_CFIG_B(channel), val);
4293 nw64(RCRCFIG_A(channel),
4294 ((u64)rp->rcr_table_size << RCRCFIG_A_LEN_SHIFT) |
4295 (rp->rcr_dma & (RCRCFIG_A_STADDR_BASE | RCRCFIG_A_STADDR)));
4296 nw64(RCRCFIG_B(channel),
4297 ((u64)rp->rcr_pkt_threshold << RCRCFIG_B_PTHRES_SHIFT) |
4298 RCRCFIG_B_ENTOUT |
4299 ((u64)rp->rcr_timeout << RCRCFIG_B_TIMEOUT_SHIFT));
4300
4301 err = niu_enable_rx_channel(np, channel, 1);
4302 if (err)
4303 return err;
4304
4305 nw64(RBR_KICK(channel), rp->rbr_index);
4306
4307 val = nr64(RX_DMA_CTL_STAT(channel));
4308 val |= RX_DMA_CTL_STAT_RBR_EMPTY;
4309 nw64(RX_DMA_CTL_STAT(channel), val);
4310
4311 return 0;
4312}
4313
4314static int niu_init_rx_channels(struct niu *np)
4315{
4316 unsigned long flags;
4317 u64 seed = jiffies_64;
4318 int err, i;
4319
4320 niu_lock_parent(np, flags);
4321 nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider);
4322 nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL));
4323 niu_unlock_parent(np, flags);
4324
4325 /* XXX RXDMA 32bit mode? XXX */
4326
4327 niu_init_rdc_groups(np);
4328 niu_init_drr_weight(np);
4329
4330 err = niu_init_hostinfo(np);
4331 if (err)
4332 return err;
4333
4334 for (i = 0; i < np->num_rx_rings; i++) {
4335 struct rx_ring_info *rp = &np->rx_rings[i];
4336
4337 err = niu_init_one_rx_channel(np, rp);
4338 if (err)
4339 return err;
4340 }
4341
4342 return 0;
4343}
4344
4345static int niu_set_ip_frag_rule(struct niu *np)
4346{
4347 struct niu_parent *parent = np->parent;
4348 struct niu_classifier *cp = &np->clas;
4349 struct niu_tcam_entry *tp;
4350 int index, err;
4351
4352 /* XXX fix this allocation scheme XXX */
4353 index = cp->tcam_index;
4354 tp = &parent->tcam[index];
4355
4356 /* Note that the noport bit is the same in both ipv4 and
4357 * ipv6 format TCAM entries.
4358 */
4359 memset(tp, 0, sizeof(*tp));
4360 tp->key[1] = TCAM_V4KEY1_NOPORT;
4361 tp->key_mask[1] = TCAM_V4KEY1_NOPORT;
4362 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
4363 ((u64)0 << TCAM_ASSOCDATA_OFFSET_SHIFT));
4364 err = tcam_write(np, index, tp->key, tp->key_mask);
4365 if (err)
4366 return err;
4367 err = tcam_assoc_write(np, index, tp->assoc_data);
4368 if (err)
4369 return err;
4370
4371 return 0;
4372}
4373
4374static int niu_init_classifier_hw(struct niu *np)
4375{
4376 struct niu_parent *parent = np->parent;
4377 struct niu_classifier *cp = &np->clas;
4378 int i, err;
4379
4380 nw64(H1POLY, cp->h1_init);
4381 nw64(H2POLY, cp->h2_init);
4382
4383 err = niu_init_hostinfo(np);
4384 if (err)
4385 return err;
4386
4387 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) {
4388 struct niu_vlan_rdc *vp = &cp->vlan_mappings[i];
4389
4390 vlan_tbl_write(np, i, np->port,
4391 vp->vlan_pref, vp->rdc_num);
4392 }
4393
4394 for (i = 0; i < cp->num_alt_mac_mappings; i++) {
4395 struct niu_altmac_rdc *ap = &cp->alt_mac_mappings[i];
4396
4397 err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num,
4398 ap->rdc_num, ap->mac_pref);
4399 if (err)
4400 return err;
4401 }
4402
4403 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
4404 int index = i - CLASS_CODE_USER_PROG1;
4405
4406 err = niu_set_tcam_key(np, i, parent->tcam_key[index]);
4407 if (err)
4408 return err;
4409 err = niu_set_flow_key(np, i, parent->flow_key[index]);
4410 if (err)
4411 return err;
4412 }
4413
4414 err = niu_set_ip_frag_rule(np);
4415 if (err)
4416 return err;
4417
4418 tcam_enable(np, 1);
4419
4420 return 0;
4421}
4422
4423static int niu_zcp_write(struct niu *np, int index, u64 *data)
4424{
4425 nw64(ZCP_RAM_DATA0, data[0]);
4426 nw64(ZCP_RAM_DATA1, data[1]);
4427 nw64(ZCP_RAM_DATA2, data[2]);
4428 nw64(ZCP_RAM_DATA3, data[3]);
4429 nw64(ZCP_RAM_DATA4, data[4]);
4430 nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL);
4431 nw64(ZCP_RAM_ACC,
4432 (ZCP_RAM_ACC_WRITE |
4433 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
4434 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
4435
4436 return niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
4437 1000, 100);
4438}
4439
4440static int niu_zcp_read(struct niu *np, int index, u64 *data)
4441{
4442 int err;
4443
4444 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
4445 1000, 100);
4446 if (err) {
4447 dev_err(np->device, PFX "%s: ZCP read busy won't clear, "
4448 "ZCP_RAM_ACC[%llx]\n", np->dev->name,
4449 (unsigned long long) nr64(ZCP_RAM_ACC));
4450 return err;
4451 }
4452
4453 nw64(ZCP_RAM_ACC,
4454 (ZCP_RAM_ACC_READ |
4455 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
4456 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
4457
4458 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
4459 1000, 100);
4460 if (err) {
4461 dev_err(np->device, PFX "%s: ZCP read busy2 won't clear, "
4462 "ZCP_RAM_ACC[%llx]\n", np->dev->name,
4463 (unsigned long long) nr64(ZCP_RAM_ACC));
4464 return err;
4465 }
4466
4467 data[0] = nr64(ZCP_RAM_DATA0);
4468 data[1] = nr64(ZCP_RAM_DATA1);
4469 data[2] = nr64(ZCP_RAM_DATA2);
4470 data[3] = nr64(ZCP_RAM_DATA3);
4471 data[4] = nr64(ZCP_RAM_DATA4);
4472
4473 return 0;
4474}
4475
4476static void niu_zcp_cfifo_reset(struct niu *np)
4477{
4478 u64 val = nr64(RESET_CFIFO);
4479
4480 val |= RESET_CFIFO_RST(np->port);
4481 nw64(RESET_CFIFO, val);
4482 udelay(10);
4483
4484 val &= ~RESET_CFIFO_RST(np->port);
4485 nw64(RESET_CFIFO, val);
4486}
4487
4488static int niu_init_zcp(struct niu *np)
4489{
4490 u64 data[5], rbuf[5];
4491 int i, max, err;
4492
4493 if (np->parent->plat_type != PLAT_TYPE_NIU) {
4494 if (np->port == 0 || np->port == 1)
4495 max = ATLAS_P0_P1_CFIFO_ENTRIES;
4496 else
4497 max = ATLAS_P2_P3_CFIFO_ENTRIES;
4498 } else
4499 max = NIU_CFIFO_ENTRIES;
4500
4501 data[0] = 0;
4502 data[1] = 0;
4503 data[2] = 0;
4504 data[3] = 0;
4505 data[4] = 0;
4506
4507 for (i = 0; i < max; i++) {
4508 err = niu_zcp_write(np, i, data);
4509 if (err)
4510 return err;
4511 err = niu_zcp_read(np, i, rbuf);
4512 if (err)
4513 return err;
4514 }
4515
4516 niu_zcp_cfifo_reset(np);
4517 nw64(CFIFO_ECC(np->port), 0);
4518 nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL);
4519 (void) nr64(ZCP_INT_STAT);
4520 nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL);
4521
4522 return 0;
4523}
4524
4525static void niu_ipp_write(struct niu *np, int index, u64 *data)
4526{
4527 u64 val = nr64_ipp(IPP_CFIG);
4528
4529 nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W);
4530 nw64_ipp(IPP_DFIFO_WR_PTR, index);
4531 nw64_ipp(IPP_DFIFO_WR0, data[0]);
4532 nw64_ipp(IPP_DFIFO_WR1, data[1]);
4533 nw64_ipp(IPP_DFIFO_WR2, data[2]);
4534 nw64_ipp(IPP_DFIFO_WR3, data[3]);
4535 nw64_ipp(IPP_DFIFO_WR4, data[4]);
4536 nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W);
4537}
4538
4539static void niu_ipp_read(struct niu *np, int index, u64 *data)
4540{
4541 nw64_ipp(IPP_DFIFO_RD_PTR, index);
4542 data[0] = nr64_ipp(IPP_DFIFO_RD0);
4543 data[1] = nr64_ipp(IPP_DFIFO_RD1);
4544 data[2] = nr64_ipp(IPP_DFIFO_RD2);
4545 data[3] = nr64_ipp(IPP_DFIFO_RD3);
4546 data[4] = nr64_ipp(IPP_DFIFO_RD4);
4547}
4548
4549static int niu_ipp_reset(struct niu *np)
4550{
4551 return niu_set_and_wait_clear_ipp(np, IPP_CFIG, IPP_CFIG_SOFT_RST,
4552 1000, 100, "IPP_CFIG");
4553}
4554
4555static int niu_init_ipp(struct niu *np)
4556{
4557 u64 data[5], rbuf[5], val;
4558 int i, max, err;
4559
4560 if (np->parent->plat_type != PLAT_TYPE_NIU) {
4561 if (np->port == 0 || np->port == 1)
4562 max = ATLAS_P0_P1_DFIFO_ENTRIES;
4563 else
4564 max = ATLAS_P2_P3_DFIFO_ENTRIES;
4565 } else
4566 max = NIU_DFIFO_ENTRIES;
4567
4568 data[0] = 0;
4569 data[1] = 0;
4570 data[2] = 0;
4571 data[3] = 0;
4572 data[4] = 0;
4573
4574 for (i = 0; i < max; i++) {
4575 niu_ipp_write(np, i, data);
4576 niu_ipp_read(np, i, rbuf);
4577 }
4578
4579 (void) nr64_ipp(IPP_INT_STAT);
4580 (void) nr64_ipp(IPP_INT_STAT);
4581
4582 err = niu_ipp_reset(np);
4583 if (err)
4584 return err;
4585
4586 (void) nr64_ipp(IPP_PKT_DIS);
4587 (void) nr64_ipp(IPP_BAD_CS_CNT);
4588 (void) nr64_ipp(IPP_ECC);
4589
4590 (void) nr64_ipp(IPP_INT_STAT);
4591
4592 nw64_ipp(IPP_MSK, ~IPP_MSK_ALL);
4593
4594 val = nr64_ipp(IPP_CFIG);
4595 val &= ~IPP_CFIG_IP_MAX_PKT;
4596 val |= (IPP_CFIG_IPP_ENABLE |
4597 IPP_CFIG_DFIFO_ECC_EN |
4598 IPP_CFIG_DROP_BAD_CRC |
4599 IPP_CFIG_CKSUM_EN |
4600 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT));
4601 nw64_ipp(IPP_CFIG, val);
4602
4603 return 0;
4604}
4605
0c3b091b 4606static void niu_handle_led(struct niu *np, int status)
a3138df9 4607{
a3138df9 4608 u64 val;
a3138df9
DM		 4609 val = nr64_mac(XMAC_CONFIG);
4610
4611 if ((np->flags & NIU_FLAGS_10G) != 0 &&
4612 (np->flags & NIU_FLAGS_FIBER) != 0) {
0c3b091b 4613 if (status) {
a3138df9
DM		 4614 val |= XMAC_CONFIG_LED_POLARITY;
4615 val &= ~XMAC_CONFIG_FORCE_LED_ON;
4616 } else {
4617 val |= XMAC_CONFIG_FORCE_LED_ON;
4618 val &= ~XMAC_CONFIG_LED_POLARITY;
4619 }
4620 }
4621
0c3b091b
ML		 4622 nw64_mac(XMAC_CONFIG, val);
4623}
4624
4625static void niu_init_xif_xmac(struct niu *np)
4626{
4627 struct niu_link_config *lp = &np->link_config;
4628 u64 val;
4629
5fbd7e24
MW		 4630 if (np->flags & NIU_FLAGS_XCVR_SERDES) {
4631 val = nr64(MIF_CONFIG);
4632 val |= MIF_CONFIG_ATCA_GE;
4633 nw64(MIF_CONFIG, val);
4634 }
4635
0c3b091b 4636 val = nr64_mac(XMAC_CONFIG);
a3138df9
DM		 4637 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
4638
4639 val |= XMAC_CONFIG_TX_OUTPUT_EN;
4640
4641 if (lp->loopback_mode == LOOPBACK_MAC) {
4642 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
4643 val |= XMAC_CONFIG_LOOPBACK;
4644 } else {
4645 val &= ~XMAC_CONFIG_LOOPBACK;
4646 }
4647
4648 if (np->flags & NIU_FLAGS_10G) {
4649 val &= ~XMAC_CONFIG_LFS_DISABLE;
4650 } else {
4651 val |= XMAC_CONFIG_LFS_DISABLE;
5fbd7e24
MW		 4652 if (!(np->flags & NIU_FLAGS_FIBER) &&
4653 !(np->flags & NIU_FLAGS_XCVR_SERDES))
a3138df9
DM		 4654 val |= XMAC_CONFIG_1G_PCS_BYPASS;
4655 else
4656 val &= ~XMAC_CONFIG_1G_PCS_BYPASS;
4657 }
4658
4659 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
4660
4661 if (lp->active_speed == SPEED_100)
4662 val |= XMAC_CONFIG_SEL_CLK_25MHZ;
4663 else
4664 val &= ~XMAC_CONFIG_SEL_CLK_25MHZ;
4665
4666 nw64_mac(XMAC_CONFIG, val);
4667
4668 val = nr64_mac(XMAC_CONFIG);
4669 val &= ~XMAC_CONFIG_MODE_MASK;
4670 if (np->flags & NIU_FLAGS_10G) {
4671 val |= XMAC_CONFIG_MODE_XGMII;
4672 } else {
4673 if (lp->active_speed == SPEED_100)
4674 val |= XMAC_CONFIG_MODE_MII;
4675 else
4676 val |= XMAC_CONFIG_MODE_GMII;
4677 }
4678
4679 nw64_mac(XMAC_CONFIG, val);
4680}
4681
4682static void niu_init_xif_bmac(struct niu *np)
4683{
4684 struct niu_link_config *lp = &np->link_config;
4685 u64 val;
4686
4687 val = BMAC_XIF_CONFIG_TX_OUTPUT_EN;
4688
4689 if (lp->loopback_mode == LOOPBACK_MAC)
4690 val |= BMAC_XIF_CONFIG_MII_LOOPBACK;
4691 else
4692 val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK;
4693
4694 if (lp->active_speed == SPEED_1000)
4695 val |= BMAC_XIF_CONFIG_GMII_MODE;
4696 else
4697 val &= ~BMAC_XIF_CONFIG_GMII_MODE;
4698
4699 val &= ~(BMAC_XIF_CONFIG_LINK_LED |
4700 BMAC_XIF_CONFIG_LED_POLARITY);
4701
4702 if (!(np->flags & NIU_FLAGS_10G) &&
4703 !(np->flags & NIU_FLAGS_FIBER) &&
4704 lp->active_speed == SPEED_100)
4705 val |= BMAC_XIF_CONFIG_25MHZ_CLOCK;
4706 else
4707 val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK;
4708
4709 nw64_mac(BMAC_XIF_CONFIG, val);
4710}
4711
4712static void niu_init_xif(struct niu *np)
4713{
4714 if (np->flags & NIU_FLAGS_XMAC)
4715 niu_init_xif_xmac(np);
4716 else
4717 niu_init_xif_bmac(np);
4718}
4719
4720static void niu_pcs_mii_reset(struct niu *np)
4721{
5fbd7e24 4722 int limit = 1000;
a3138df9
DM		 4723 u64 val = nr64_pcs(PCS_MII_CTL);
4724 val |= PCS_MII_CTL_RST;
4725 nw64_pcs(PCS_MII_CTL, val);
5fbd7e24
MW		 4726 while ((--limit >= 0) && (val & PCS_MII_CTL_RST)) {
4727 udelay(100);
4728 val = nr64_pcs(PCS_MII_CTL);
4729 }
a3138df9
DM		 4730}
4731
4732static void niu_xpcs_reset(struct niu *np)
4733{
5fbd7e24 4734 int limit = 1000;
a3138df9
DM		 4735 u64 val = nr64_xpcs(XPCS_CONTROL1);
4736 val |= XPCS_CONTROL1_RESET;
4737 nw64_xpcs(XPCS_CONTROL1, val);
5fbd7e24
MW		 4738 while ((--limit >= 0) && (val & XPCS_CONTROL1_RESET)) {
4739 udelay(100);
4740 val = nr64_xpcs(XPCS_CONTROL1);
4741 }
a3138df9
DM		 4742}
4743
4744static int niu_init_pcs(struct niu *np)
4745{
4746 struct niu_link_config *lp = &np->link_config;
4747 u64 val;
4748
5fbd7e24
MW		 4749 switch (np->flags & (NIU_FLAGS_10G |
4750 NIU_FLAGS_FIBER |
4751 NIU_FLAGS_XCVR_SERDES)) {
a3138df9
DM		 4752 case NIU_FLAGS_FIBER:
4753 /* 1G fiber */
4754 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
4755 nw64_pcs(PCS_DPATH_MODE, 0);
4756 niu_pcs_mii_reset(np);
4757 break;
4758
4759 case NIU_FLAGS_10G:
4760 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
5fbd7e24
MW		 4761 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
4762 /* 10G SERDES */
a3138df9
DM		 4763 if (!(np->flags & NIU_FLAGS_XMAC))
4764 return -EINVAL;
4765
4766 /* 10G copper or fiber */
4767 val = nr64_mac(XMAC_CONFIG);
4768 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
4769 nw64_mac(XMAC_CONFIG, val);
4770
4771 niu_xpcs_reset(np);
4772
4773 val = nr64_xpcs(XPCS_CONTROL1);
4774 if (lp->loopback_mode == LOOPBACK_PHY)
4775 val |= XPCS_CONTROL1_LOOPBACK;
4776 else
4777 val &= ~XPCS_CONTROL1_LOOPBACK;
4778 nw64_xpcs(XPCS_CONTROL1, val);
4779
4780 nw64_xpcs(XPCS_DESKEW_ERR_CNT, 0);
4781 (void) nr64_xpcs(XPCS_SYMERR_CNT01);
4782 (void) nr64_xpcs(XPCS_SYMERR_CNT23);
4783 break;
4784
5fbd7e24
MW		 4785
4786 case NIU_FLAGS_XCVR_SERDES:
4787 /* 1G SERDES */
4788 niu_pcs_mii_reset(np);
4789 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
4790 nw64_pcs(PCS_DPATH_MODE, 0);
4791 break;
4792
a3138df9
DM		 4793 case 0:
4794 /* 1G copper */
5fbd7e24
MW		 4795 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
4796 /* 1G RGMII FIBER */
a3138df9
DM		 4797 nw64_pcs(PCS_DPATH_MODE, PCS_DPATH_MODE_MII);
4798 niu_pcs_mii_reset(np);
4799 break;
4800
4801 default:
4802 return -EINVAL;
4803 }
4804
4805 return 0;
4806}
4807
4808static int niu_reset_tx_xmac(struct niu *np)
4809{
4810 return niu_set_and_wait_clear_mac(np, XTXMAC_SW_RST,
4811 (XTXMAC_SW_RST_REG_RS |
4812 XTXMAC_SW_RST_SOFT_RST),
4813 1000, 100, "XTXMAC_SW_RST");
4814}
4815
4816static int niu_reset_tx_bmac(struct niu *np)
4817{
4818 int limit;
4819
4820 nw64_mac(BTXMAC_SW_RST, BTXMAC_SW_RST_RESET);
4821 limit = 1000;
4822 while (--limit >= 0) {
4823 if (!(nr64_mac(BTXMAC_SW_RST) & BTXMAC_SW_RST_RESET))
4824 break;
4825 udelay(100);
4826 }
4827 if (limit < 0) {
4828 dev_err(np->device, PFX "Port %u TX BMAC would not reset, "
4829 "BTXMAC_SW_RST[%llx]\n",
4830 np->port,
4831 (unsigned long long) nr64_mac(BTXMAC_SW_RST));
4832 return -ENODEV;
4833 }
4834
4835 return 0;
4836}
4837
4838static int niu_reset_tx_mac(struct niu *np)
4839{
4840 if (np->flags & NIU_FLAGS_XMAC)
4841 return niu_reset_tx_xmac(np);
4842 else
4843 return niu_reset_tx_bmac(np);
4844}
4845
4846static void niu_init_tx_xmac(struct niu *np, u64 min, u64 max)
4847{
4848 u64 val;
4849
4850 val = nr64_mac(XMAC_MIN);
4851 val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE |
4852 XMAC_MIN_RX_MIN_PKT_SIZE);
4853 val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT);
4854 val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT);
4855 nw64_mac(XMAC_MIN, val);
4856
4857 nw64_mac(XMAC_MAX, max);
4858
4859 nw64_mac(XTXMAC_STAT_MSK, ~(u64)0);
4860
4861 val = nr64_mac(XMAC_IPG);
4862 if (np->flags & NIU_FLAGS_10G) {
4863 val &= ~XMAC_IPG_IPG_XGMII;
4864 val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT);
4865 } else {
4866 val &= ~XMAC_IPG_IPG_MII_GMII;
4867 val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT);
4868 }
4869 nw64_mac(XMAC_IPG, val);
4870
4871 val = nr64_mac(XMAC_CONFIG);
4872 val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC |
4873 XMAC_CONFIG_STRETCH_MODE |
4874 XMAC_CONFIG_VAR_MIN_IPG_EN |
4875 XMAC_CONFIG_TX_ENABLE);
4876 nw64_mac(XMAC_CONFIG, val);
4877
4878 nw64_mac(TXMAC_FRM_CNT, 0);
4879 nw64_mac(TXMAC_BYTE_CNT, 0);
4880}
4881
4882static void niu_init_tx_bmac(struct niu *np, u64 min, u64 max)
4883{
4884 u64 val;
4885
4886 nw64_mac(BMAC_MIN_FRAME, min);
4887 nw64_mac(BMAC_MAX_FRAME, max);
4888
4889 nw64_mac(BTXMAC_STATUS_MASK, ~(u64)0);
4890 nw64_mac(BMAC_CTRL_TYPE, 0x8808);
4891 nw64_mac(BMAC_PREAMBLE_SIZE, 7);
4892
4893 val = nr64_mac(BTXMAC_CONFIG);
4894 val &= ~(BTXMAC_CONFIG_FCS_DISABLE |
4895 BTXMAC_CONFIG_ENABLE);
4896 nw64_mac(BTXMAC_CONFIG, val);
4897}
4898
4899static void niu_init_tx_mac(struct niu *np)
4900{
4901 u64 min, max;
4902
4903 min = 64;
4904 if (np->dev->mtu > ETH_DATA_LEN)
4905 max = 9216;
4906 else
4907 max = 1522;
4908
4909 /* The XMAC_MIN register only accepts values for TX min which
4910 * have the low 3 bits cleared.
4911 */
4912 BUILD_BUG_ON(min & 0x7);
4913
4914 if (np->flags & NIU_FLAGS_XMAC)
4915 niu_init_tx_xmac(np, min, max);
4916 else
4917 niu_init_tx_bmac(np, min, max);
4918}
4919
4920static int niu_reset_rx_xmac(struct niu *np)
4921{
4922 int limit;
4923
4924 nw64_mac(XRXMAC_SW_RST,
4925 XRXMAC_SW_RST_REG_RS | XRXMAC_SW_RST_SOFT_RST);
4926 limit = 1000;
4927 while (--limit >= 0) {
4928 if (!(nr64_mac(XRXMAC_SW_RST) & (XRXMAC_SW_RST_REG_RS |
4929 XRXMAC_SW_RST_SOFT_RST)))
4930 break;
4931 udelay(100);
4932 }
4933 if (limit < 0) {
4934 dev_err(np->device, PFX "Port %u RX XMAC would not reset, "
4935 "XRXMAC_SW_RST[%llx]\n",
4936 np->port,
4937 (unsigned long long) nr64_mac(XRXMAC_SW_RST));
4938 return -ENODEV;
4939 }
4940
4941 return 0;
4942}
4943
4944static int niu_reset_rx_bmac(struct niu *np)
4945{
4946 int limit;
4947
4948 nw64_mac(BRXMAC_SW_RST, BRXMAC_SW_RST_RESET);
4949 limit = 1000;
4950 while (--limit >= 0) {
4951 if (!(nr64_mac(BRXMAC_SW_RST) & BRXMAC_SW_RST_RESET))
4952 break;
4953 udelay(100);
4954 }
4955 if (limit < 0) {
4956 dev_err(np->device, PFX "Port %u RX BMAC would not reset, "
4957 "BRXMAC_SW_RST[%llx]\n",
4958 np->port,
4959 (unsigned long long) nr64_mac(BRXMAC_SW_RST));
4960 return -ENODEV;
4961 }
4962
4963 return 0;
4964}
4965
4966static int niu_reset_rx_mac(struct niu *np)
4967{
4968 if (np->flags & NIU_FLAGS_XMAC)
4969 return niu_reset_rx_xmac(np);
4970 else
4971 return niu_reset_rx_bmac(np);
4972}
4973
4974static void niu_init_rx_xmac(struct niu *np)
4975{
4976 struct niu_parent *parent = np->parent;
4977 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
4978 int first_rdc_table = tp->first_table_num;
4979 unsigned long i;
4980 u64 val;
4981
4982 nw64_mac(XMAC_ADD_FILT0, 0);
4983 nw64_mac(XMAC_ADD_FILT1, 0);
4984 nw64_mac(XMAC_ADD_FILT2, 0);
4985 nw64_mac(XMAC_ADD_FILT12_MASK, 0);
4986 nw64_mac(XMAC_ADD_FILT00_MASK, 0);
4987 for (i = 0; i < MAC_NUM_HASH; i++)
4988 nw64_mac(XMAC_HASH_TBL(i), 0);
4989 nw64_mac(XRXMAC_STAT_MSK, ~(u64)0);
4990 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
4991 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
4992
4993 val = nr64_mac(XMAC_CONFIG);
4994 val &= ~(XMAC_CONFIG_RX_MAC_ENABLE |
4995 XMAC_CONFIG_PROMISCUOUS |
4996 XMAC_CONFIG_PROMISC_GROUP |
4997 XMAC_CONFIG_ERR_CHK_DIS |
4998 XMAC_CONFIG_RX_CRC_CHK_DIS |
4999 XMAC_CONFIG_RESERVED_MULTICAST |
5000 XMAC_CONFIG_RX_CODEV_CHK_DIS |
5001 XMAC_CONFIG_ADDR_FILTER_EN |
5002 XMAC_CONFIG_RCV_PAUSE_ENABLE |
5003 XMAC_CONFIG_STRIP_CRC |
5004 XMAC_CONFIG_PASS_FLOW_CTRL |
5005 XMAC_CONFIG_MAC2IPP_PKT_CNT_EN);
5006 val |= (XMAC_CONFIG_HASH_FILTER_EN);
5007 nw64_mac(XMAC_CONFIG, val);
5008
5009 nw64_mac(RXMAC_BT_CNT, 0);
5010 nw64_mac(RXMAC_BC_FRM_CNT, 0);
5011 nw64_mac(RXMAC_MC_FRM_CNT, 0);
5012 nw64_mac(RXMAC_FRAG_CNT, 0);
5013 nw64_mac(RXMAC_HIST_CNT1, 0);
5014 nw64_mac(RXMAC_HIST_CNT2, 0);
5015 nw64_mac(RXMAC_HIST_CNT3, 0);
5016 nw64_mac(RXMAC_HIST_CNT4, 0);
5017 nw64_mac(RXMAC_HIST_CNT5, 0);
5018 nw64_mac(RXMAC_HIST_CNT6, 0);
5019 nw64_mac(RXMAC_HIST_CNT7, 0);
5020 nw64_mac(RXMAC_MPSZER_CNT, 0);
5021 nw64_mac(RXMAC_CRC_ER_CNT, 0);
5022 nw64_mac(RXMAC_CD_VIO_CNT, 0);
5023 nw64_mac(LINK_FAULT_CNT, 0);
5024}
5025
5026static void niu_init_rx_bmac(struct niu *np)
5027{
5028 struct niu_parent *parent = np->parent;
5029 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5030 int first_rdc_table = tp->first_table_num;
5031 unsigned long i;
5032 u64 val;
5033
5034 nw64_mac(BMAC_ADD_FILT0, 0);
5035 nw64_mac(BMAC_ADD_FILT1, 0);
5036 nw64_mac(BMAC_ADD_FILT2, 0);
5037 nw64_mac(BMAC_ADD_FILT12_MASK, 0);
5038 nw64_mac(BMAC_ADD_FILT00_MASK, 0);
5039 for (i = 0; i < MAC_NUM_HASH; i++)
5040 nw64_mac(BMAC_HASH_TBL(i), 0);
5041 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5042 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5043 nw64_mac(BRXMAC_STATUS_MASK, ~(u64)0);
5044
5045 val = nr64_mac(BRXMAC_CONFIG);
5046 val &= ~(BRXMAC_CONFIG_ENABLE |
5047 BRXMAC_CONFIG_STRIP_PAD |
5048 BRXMAC_CONFIG_STRIP_FCS |
5049 BRXMAC_CONFIG_PROMISC |
5050 BRXMAC_CONFIG_PROMISC_GRP |
5051 BRXMAC_CONFIG_ADDR_FILT_EN |
5052 BRXMAC_CONFIG_DISCARD_DIS);
5053 val |= (BRXMAC_CONFIG_HASH_FILT_EN);
5054 nw64_mac(BRXMAC_CONFIG, val);
5055
5056 val = nr64_mac(BMAC_ADDR_CMPEN);
5057 val |= BMAC_ADDR_CMPEN_EN0;
5058 nw64_mac(BMAC_ADDR_CMPEN, val);
5059}
5060
5061static void niu_init_rx_mac(struct niu *np)
5062{
5063 niu_set_primary_mac(np, np->dev->dev_addr);
5064
5065 if (np->flags & NIU_FLAGS_XMAC)
5066 niu_init_rx_xmac(np);
5067 else
5068 niu_init_rx_bmac(np);
5069}
5070
5071static void niu_enable_tx_xmac(struct niu *np, int on)
5072{
5073 u64 val = nr64_mac(XMAC_CONFIG);
5074
5075 if (on)
5076 val |= XMAC_CONFIG_TX_ENABLE;
5077 else
5078 val &= ~XMAC_CONFIG_TX_ENABLE;
5079 nw64_mac(XMAC_CONFIG, val);
5080}
5081
5082static void niu_enable_tx_bmac(struct niu *np, int on)
5083{
5084 u64 val = nr64_mac(BTXMAC_CONFIG);
5085
5086 if (on)
5087 val |= BTXMAC_CONFIG_ENABLE;
5088 else
5089 val &= ~BTXMAC_CONFIG_ENABLE;
5090 nw64_mac(BTXMAC_CONFIG, val);
5091}
5092
5093static void niu_enable_tx_mac(struct niu *np, int on)
5094{
5095 if (np->flags & NIU_FLAGS_XMAC)
5096 niu_enable_tx_xmac(np, on);
5097 else
5098 niu_enable_tx_bmac(np, on);
5099}
5100
5101static void niu_enable_rx_xmac(struct niu *np, int on)
5102{
5103 u64 val = nr64_mac(XMAC_CONFIG);
5104
5105 val &= ~(XMAC_CONFIG_HASH_FILTER_EN |
5106 XMAC_CONFIG_PROMISCUOUS);
5107
5108 if (np->flags & NIU_FLAGS_MCAST)
5109 val |= XMAC_CONFIG_HASH_FILTER_EN;
5110 if (np->flags & NIU_FLAGS_PROMISC)
5111 val |= XMAC_CONFIG_PROMISCUOUS;
5112
5113 if (on)
5114 val |= XMAC_CONFIG_RX_MAC_ENABLE;
5115 else
5116 val &= ~XMAC_CONFIG_RX_MAC_ENABLE;
5117 nw64_mac(XMAC_CONFIG, val);
5118}
5119
5120static void niu_enable_rx_bmac(struct niu *np, int on)
5121{
5122 u64 val = nr64_mac(BRXMAC_CONFIG);
5123
5124 val &= ~(BRXMAC_CONFIG_HASH_FILT_EN |
5125 BRXMAC_CONFIG_PROMISC);
5126
5127 if (np->flags & NIU_FLAGS_MCAST)
5128 val |= BRXMAC_CONFIG_HASH_FILT_EN;
5129 if (np->flags & NIU_FLAGS_PROMISC)
5130 val |= BRXMAC_CONFIG_PROMISC;
5131
5132 if (on)
5133 val |= BRXMAC_CONFIG_ENABLE;
5134 else
5135 val &= ~BRXMAC_CONFIG_ENABLE;
5136 nw64_mac(BRXMAC_CONFIG, val);
5137}
5138
5139static void niu_enable_rx_mac(struct niu *np, int on)
5140{
5141 if (np->flags & NIU_FLAGS_XMAC)
5142 niu_enable_rx_xmac(np, on);
5143 else
5144 niu_enable_rx_bmac(np, on);
5145}
5146
5147static int niu_init_mac(struct niu *np)
5148{
5149 int err;
5150
5151 niu_init_xif(np);
5152 err = niu_init_pcs(np);
5153 if (err)
5154 return err;
5155
5156 err = niu_reset_tx_mac(np);
5157 if (err)
5158 return err;
5159 niu_init_tx_mac(np);
5160 err = niu_reset_rx_mac(np);
5161 if (err)
5162 return err;
5163 niu_init_rx_mac(np);
5164
5165 /* This looks hookey but the RX MAC reset we just did will
5166 * undo some of the state we setup in niu_init_tx_mac() so we
5167 * have to call it again. In particular, the RX MAC reset will
5168 * set the XMAC_MAX register back to it's default value.
5169 */
5170 niu_init_tx_mac(np);
5171 niu_enable_tx_mac(np, 1);
5172
5173 niu_enable_rx_mac(np, 1);
5174
5175 return 0;
5176}
5177
5178static void niu_stop_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5179{
5180 (void) niu_tx_channel_stop(np, rp->tx_channel);
5181}
5182
5183static void niu_stop_tx_channels(struct niu *np)
5184{
5185 int i;
5186
5187 for (i = 0; i < np->num_tx_rings; i++) {
5188 struct tx_ring_info *rp = &np->tx_rings[i];
5189
5190 niu_stop_one_tx_channel(np, rp);
5191 }
5192}
5193
5194static void niu_reset_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5195{
5196 (void) niu_tx_channel_reset(np, rp->tx_channel);
5197}
5198
5199static void niu_reset_tx_channels(struct niu *np)
5200{
5201 int i;
5202
5203 for (i = 0; i < np->num_tx_rings; i++) {
5204 struct tx_ring_info *rp = &np->tx_rings[i];
5205
5206 niu_reset_one_tx_channel(np, rp);
5207 }
5208}
5209
5210static void niu_stop_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5211{
5212 (void) niu_enable_rx_channel(np, rp->rx_channel, 0);
5213}
5214
5215static void niu_stop_rx_channels(struct niu *np)
5216{
5217 int i;
5218
5219 for (i = 0; i < np->num_rx_rings; i++) {
5220 struct rx_ring_info *rp = &np->rx_rings[i];
5221
5222 niu_stop_one_rx_channel(np, rp);
5223 }
5224}
5225
5226static void niu_reset_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5227{
5228 int channel = rp->rx_channel;
5229
5230 (void) niu_rx_channel_reset(np, channel);
5231 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL);
5232 nw64(RX_DMA_CTL_STAT(channel), 0);
5233 (void) niu_enable_rx_channel(np, channel, 0);
5234}
5235
5236static void niu_reset_rx_channels(struct niu *np)
5237{
5238 int i;
5239
5240 for (i = 0; i < np->num_rx_rings; i++) {
5241 struct rx_ring_info *rp = &np->rx_rings[i];
5242
5243 niu_reset_one_rx_channel(np, rp);
5244 }
5245}
5246
5247static void niu_disable_ipp(struct niu *np)
5248{
5249 u64 rd, wr, val;
5250 int limit;
5251
5252 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5253 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5254 limit = 100;
5255 while (--limit >= 0 && (rd != wr)) {
5256 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5257 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5258 }
5259 if (limit < 0 &&
5260 (rd != 0 && wr != 1)) {
5261 dev_err(np->device, PFX "%s: IPP would not quiesce, "
5262 "rd_ptr[%llx] wr_ptr[%llx]\n",
5263 np->dev->name,
5264 (unsigned long long) nr64_ipp(IPP_DFIFO_RD_PTR),
5265 (unsigned long long) nr64_ipp(IPP_DFIFO_WR_PTR));
5266 }
5267
5268 val = nr64_ipp(IPP_CFIG);
5269 val &= ~(IPP_CFIG_IPP_ENABLE |
5270 IPP_CFIG_DFIFO_ECC_EN |
5271 IPP_CFIG_DROP_BAD_CRC |
5272 IPP_CFIG_CKSUM_EN);
5273 nw64_ipp(IPP_CFIG, val);
5274
5275 (void) niu_ipp_reset(np);
5276}
5277
5278static int niu_init_hw(struct niu *np)
5279{
5280 int i, err;
5281
5282 niudbg(IFUP, "%s: Initialize TXC\n", np->dev->name);
5283 niu_txc_enable_port(np, 1);
5284 niu_txc_port_dma_enable(np, 1);
5285 niu_txc_set_imask(np, 0);
5286
5287 niudbg(IFUP, "%s: Initialize TX channels\n", np->dev->name);
5288 for (i = 0; i < np->num_tx_rings; i++) {
5289 struct tx_ring_info *rp = &np->tx_rings[i];
5290
5291 err = niu_init_one_tx_channel(np, rp);
5292 if (err)
5293 return err;
5294 }
5295
5296 niudbg(IFUP, "%s: Initialize RX channels\n", np->dev->name);
5297 err = niu_init_rx_channels(np);
5298 if (err)
5299 goto out_uninit_tx_channels;
5300
5301 niudbg(IFUP, "%s: Initialize classifier\n", np->dev->name);
5302 err = niu_init_classifier_hw(np);
5303 if (err)
5304 goto out_uninit_rx_channels;
5305
5306 niudbg(IFUP, "%s: Initialize ZCP\n", np->dev->name);
5307 err = niu_init_zcp(np);
5308 if (err)
5309 goto out_uninit_rx_channels;
5310
5311 niudbg(IFUP, "%s: Initialize IPP\n", np->dev->name);
5312 err = niu_init_ipp(np);
5313 if (err)
5314 goto out_uninit_rx_channels;
5315
5316 niudbg(IFUP, "%s: Initialize MAC\n", np->dev->name);
5317 err = niu_init_mac(np);
5318 if (err)
5319 goto out_uninit_ipp;
5320
5321 return 0;
5322
5323out_uninit_ipp:
5324 niudbg(IFUP, "%s: Uninit IPP\n", np->dev->name);
5325 niu_disable_ipp(np);
5326
5327out_uninit_rx_channels:
5328 niudbg(IFUP, "%s: Uninit RX channels\n", np->dev->name);
5329 niu_stop_rx_channels(np);
5330 niu_reset_rx_channels(np);
5331
5332out_uninit_tx_channels:
5333 niudbg(IFUP, "%s: Uninit TX channels\n", np->dev->name);
5334 niu_stop_tx_channels(np);
5335 niu_reset_tx_channels(np);
5336
5337 return err;
5338}
5339
5340static void niu_stop_hw(struct niu *np)
5341{
5342 niudbg(IFDOWN, "%s: Disable interrupts\n", np->dev->name);
5343 niu_enable_interrupts(np, 0);
5344
5345 niudbg(IFDOWN, "%s: Disable RX MAC\n", np->dev->name);
5346 niu_enable_rx_mac(np, 0);
5347
5348 niudbg(IFDOWN, "%s: Disable IPP\n", np->dev->name);
5349 niu_disable_ipp(np);
5350
5351 niudbg(IFDOWN, "%s: Stop TX channels\n", np->dev->name);
5352 niu_stop_tx_channels(np);
5353
5354 niudbg(IFDOWN, "%s: Stop RX channels\n", np->dev->name);
5355 niu_stop_rx_channels(np);
5356
5357 niudbg(IFDOWN, "%s: Reset TX channels\n", np->dev->name);
5358 niu_reset_tx_channels(np);
5359
5360 niudbg(IFDOWN, "%s: Reset RX channels\n", np->dev->name);
5361 niu_reset_rx_channels(np);
5362}
5363
5364static int niu_request_irq(struct niu *np)
5365{
5366 int i, j, err;
5367
5368 err = 0;
5369 for (i = 0; i < np->num_ldg; i++) {
5370 struct niu_ldg *lp = &np->ldg[i];
5371
5372 err = request_irq(lp->irq, niu_interrupt,
5373 IRQF_SHARED | IRQF_SAMPLE_RANDOM,
5374 np->dev->name, lp);
5375 if (err)
5376 goto out_free_irqs;
5377
5378 }
5379
5380 return 0;
5381
5382out_free_irqs:
5383 for (j = 0; j < i; j++) {
5384 struct niu_ldg *lp = &np->ldg[j];
5385
5386 free_irq(lp->irq, lp);
5387 }
5388 return err;
5389}
5390
5391static void niu_free_irq(struct niu *np)
5392{
5393 int i;
5394
5395 for (i = 0; i < np->num_ldg; i++) {
5396 struct niu_ldg *lp = &np->ldg[i];
5397
5398 free_irq(lp->irq, lp);
5399 }
5400}
5401
5402static void niu_enable_napi(struct niu *np)
5403{
5404 int i;
5405
5406 for (i = 0; i < np->num_ldg; i++)
5407 napi_enable(&np->ldg[i].napi);
5408}
5409
5410static void niu_disable_napi(struct niu *np)
5411{
5412 int i;
5413
5414 for (i = 0; i < np->num_ldg; i++)
5415 napi_disable(&np->ldg[i].napi);
5416}
5417
5418static int niu_open(struct net_device *dev)
5419{
5420 struct niu *np = netdev_priv(dev);
5421 int err;
5422
5423 netif_carrier_off(dev);
5424
5425 err = niu_alloc_channels(np);
5426 if (err)
5427 goto out_err;
5428
5429 err = niu_enable_interrupts(np, 0);
5430 if (err)
5431 goto out_free_channels;
5432
5433 err = niu_request_irq(np);
5434 if (err)
5435 goto out_free_channels;
5436
5437 niu_enable_napi(np);
5438
5439 spin_lock_irq(&np->lock);
5440
5441 err = niu_init_hw(np);
5442 if (!err) {
5443 init_timer(&np->timer);
5444 np->timer.expires = jiffies + HZ;
5445 np->timer.data = (unsigned long) np;
5446 np->timer.function = niu_timer;
5447
5448 err = niu_enable_interrupts(np, 1);
5449 if (err)
5450 niu_stop_hw(np);
5451 }
5452
5453 spin_unlock_irq(&np->lock);
5454
5455 if (err) {
5456 niu_disable_napi(np);
5457 goto out_free_irq;
5458 }
5459
5460 netif_start_queue(dev);
5461
5462 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
5463 netif_carrier_on(dev);
5464
5465 add_timer(&np->timer);
5466
5467 return 0;
5468
5469out_free_irq:
5470 niu_free_irq(np);
5471
5472out_free_channels:
5473 niu_free_channels(np);
5474
5475out_err:
5476 return err;
5477}
5478
5479static void niu_full_shutdown(struct niu *np, struct net_device *dev)
5480{
5481 cancel_work_sync(&np->reset_task);
5482
5483 niu_disable_napi(np);
5484 netif_stop_queue(dev);
5485
5486 del_timer_sync(&np->timer);
5487
5488 spin_lock_irq(&np->lock);
5489
5490 niu_stop_hw(np);
5491
5492 spin_unlock_irq(&np->lock);
5493}
5494
5495static int niu_close(struct net_device *dev)
5496{
5497 struct niu *np = netdev_priv(dev);
5498
5499 niu_full_shutdown(np, dev);
5500
5501 niu_free_irq(np);
5502
5503 niu_free_channels(np);
5504
0c3b091b
ML		 5505 niu_handle_led(np, 0);
5506
a3138df9
DM		 5507 return 0;
5508}
5509
5510static void niu_sync_xmac_stats(struct niu *np)
5511{
5512 struct niu_xmac_stats *mp = &np->mac_stats.xmac;
5513
5514 mp->tx_frames += nr64_mac(TXMAC_FRM_CNT);
5515 mp->tx_bytes += nr64_mac(TXMAC_BYTE_CNT);
5516
5517 mp->rx_link_faults += nr64_mac(LINK_FAULT_CNT);
5518 mp->rx_align_errors += nr64_mac(RXMAC_ALIGN_ERR_CNT);
5519 mp->rx_frags += nr64_mac(RXMAC_FRAG_CNT);
5520 mp->rx_mcasts += nr64_mac(RXMAC_MC_FRM_CNT);
5521 mp->rx_bcasts += nr64_mac(RXMAC_BC_FRM_CNT);
5522 mp->rx_hist_cnt1 += nr64_mac(RXMAC_HIST_CNT1);
5523 mp->rx_hist_cnt2 += nr64_mac(RXMAC_HIST_CNT2);
5524 mp->rx_hist_cnt3 += nr64_mac(RXMAC_HIST_CNT3);
5525 mp->rx_hist_cnt4 += nr64_mac(RXMAC_HIST_CNT4);
5526 mp->rx_hist_cnt5 += nr64_mac(RXMAC_HIST_CNT5);
5527 mp->rx_hist_cnt6 += nr64_mac(RXMAC_HIST_CNT6);
5528 mp->rx_hist_cnt7 += nr64_mac(RXMAC_HIST_CNT7);
5529 mp->rx_octets += nr64_mac(RXMAC_BT_CNT);
5530 mp->rx_code_violations += nr64_mac(RXMAC_CD_VIO_CNT);
5531 mp->rx_len_errors += nr64_mac(RXMAC_MPSZER_CNT);
5532 mp->rx_crc_errors += nr64_mac(RXMAC_CRC_ER_CNT);
5533}
5534
5535static void niu_sync_bmac_stats(struct niu *np)
5536{
5537 struct niu_bmac_stats *mp = &np->mac_stats.bmac;
5538
5539 mp->tx_bytes += nr64_mac(BTXMAC_BYTE_CNT);
5540 mp->tx_frames += nr64_mac(BTXMAC_FRM_CNT);
5541
5542 mp->rx_frames += nr64_mac(BRXMAC_FRAME_CNT);
5543 mp->rx_align_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
5544 mp->rx_crc_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
5545 mp->rx_len_errors += nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT);
5546}
5547
5548static void niu_sync_mac_stats(struct niu *np)
5549{
5550 if (np->flags & NIU_FLAGS_XMAC)
5551 niu_sync_xmac_stats(np);
5552 else
5553 niu_sync_bmac_stats(np);
5554}
5555
5556static void niu_get_rx_stats(struct niu *np)
5557{
5558 unsigned long pkts, dropped, errors, bytes;
5559 int i;
5560
5561 pkts = dropped = errors = bytes = 0;
5562 for (i = 0; i < np->num_rx_rings; i++) {
5563 struct rx_ring_info *rp = &np->rx_rings[i];
5564
5565 pkts += rp->rx_packets;
5566 bytes += rp->rx_bytes;
5567 dropped += rp->rx_dropped;
5568 errors += rp->rx_errors;
5569 }
5570 np->net_stats.rx_packets = pkts;
5571 np->net_stats.rx_bytes = bytes;
5572 np->net_stats.rx_dropped = dropped;
5573 np->net_stats.rx_errors = errors;
5574}
5575
5576static void niu_get_tx_stats(struct niu *np)
5577{
5578 unsigned long pkts, errors, bytes;
5579 int i;
5580
5581 pkts = errors = bytes = 0;
5582 for (i = 0; i < np->num_tx_rings; i++) {
5583 struct tx_ring_info *rp = &np->tx_rings[i];
5584
5585 pkts += rp->tx_packets;
5586 bytes += rp->tx_bytes;
5587 errors += rp->tx_errors;
5588 }
5589 np->net_stats.tx_packets = pkts;
5590 np->net_stats.tx_bytes = bytes;
5591 np->net_stats.tx_errors = errors;
5592}
5593
5594static struct net_device_stats *niu_get_stats(struct net_device *dev)
5595{
5596 struct niu *np = netdev_priv(dev);
5597
5598 niu_get_rx_stats(np);
5599 niu_get_tx_stats(np);
5600
5601 return &np->net_stats;
5602}
5603
5604static void niu_load_hash_xmac(struct niu *np, u16 *hash)
5605{
5606 int i;
5607
5608 for (i = 0; i < 16; i++)
5609 nw64_mac(XMAC_HASH_TBL(i), hash[i]);
5610}
5611
5612static void niu_load_hash_bmac(struct niu *np, u16 *hash)
5613{
5614 int i;
5615
5616 for (i = 0; i < 16; i++)
5617 nw64_mac(BMAC_HASH_TBL(i), hash[i]);
5618}
5619
5620static void niu_load_hash(struct niu *np, u16 *hash)
5621{
5622 if (np->flags & NIU_FLAGS_XMAC)
5623 niu_load_hash_xmac(np, hash);
5624 else
5625 niu_load_hash_bmac(np, hash);
5626}
5627
5628static void niu_set_rx_mode(struct net_device *dev)
5629{
5630 struct niu *np = netdev_priv(dev);
5631 int i, alt_cnt, err;
5632 struct dev_addr_list *addr;
5633 unsigned long flags;
5634 u16 hash[16] = { 0, };
5635
5636 spin_lock_irqsave(&np->lock, flags);
5637 niu_enable_rx_mac(np, 0);
5638
5639 np->flags &= ~(NIU_FLAGS_MCAST | NIU_FLAGS_PROMISC);
5640 if (dev->flags & IFF_PROMISC)
5641 np->flags |= NIU_FLAGS_PROMISC;
5642 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 0))
5643 np->flags |= NIU_FLAGS_MCAST;
5644
5645 alt_cnt = dev->uc_count;
5646 if (alt_cnt > niu_num_alt_addr(np)) {
5647 alt_cnt = 0;
5648 np->flags |= NIU_FLAGS_PROMISC;
5649 }
5650
5651 if (alt_cnt) {
5652 int index = 0;
5653
5654 for (addr = dev->uc_list; addr; addr = addr->next) {
5655 err = niu_set_alt_mac(np, index,
5656 addr->da_addr);
5657 if (err)
5658 printk(KERN_WARNING PFX "%s: Error %d "
5659 "adding alt mac %d\n",
5660 dev->name, err, index);
5661 err = niu_enable_alt_mac(np, index, 1);
5662 if (err)
5663 printk(KERN_WARNING PFX "%s: Error %d "
5664 "enabling alt mac %d\n",
5665 dev->name, err, index);
5666
5667 index++;
5668 }
5669 } else {
3b5bcede
MW		 5670 int alt_start;
5671 if (np->flags & NIU_FLAGS_XMAC)
5672 alt_start = 0;
5673 else
5674 alt_start = 1;
5675 for (i = alt_start; i < niu_num_alt_addr(np); i++) {
a3138df9
DM		 5676 err = niu_enable_alt_mac(np, i, 0);
5677 if (err)
5678 printk(KERN_WARNING PFX "%s: Error %d "
5679 "disabling alt mac %d\n",
5680 dev->name, err, i);
5681 }
5682 }
5683 if (dev->flags & IFF_ALLMULTI) {
5684 for (i = 0; i < 16; i++)
5685 hash[i] = 0xffff;
5686 } else if (dev->mc_count > 0) {
5687 for (addr = dev->mc_list; addr; addr = addr->next) {
5688 u32 crc = ether_crc_le(ETH_ALEN, addr->da_addr);
5689
5690 crc >>= 24;
5691 hash[crc >> 4] |= (1 << (15 - (crc & 0xf)));
5692 }
5693 }
5694
5695 if (np->flags & NIU_FLAGS_MCAST)
5696 niu_load_hash(np, hash);
5697
5698 niu_enable_rx_mac(np, 1);
5699 spin_unlock_irqrestore(&np->lock, flags);
5700}
5701
5702static int niu_set_mac_addr(struct net_device *dev, void *p)
5703{
5704 struct niu *np = netdev_priv(dev);
5705 struct sockaddr *addr = p;
5706 unsigned long flags;
5707
5708 if (!is_valid_ether_addr(addr->sa_data))
5709 return -EINVAL;
5710
5711 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
5712
5713 if (!netif_running(dev))
5714 return 0;
5715
5716 spin_lock_irqsave(&np->lock, flags);
5717 niu_enable_rx_mac(np, 0);
5718 niu_set_primary_mac(np, dev->dev_addr);
5719 niu_enable_rx_mac(np, 1);
5720 spin_unlock_irqrestore(&np->lock, flags);
5721
5722 return 0;
5723}
5724
5725static int niu_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5726{
5727 return -EOPNOTSUPP;
5728}
5729
5730static void niu_netif_stop(struct niu *np)
5731{
5732 np->dev->trans_start = jiffies; /* prevent tx timeout */
5733
5734 niu_disable_napi(np);
5735
5736 netif_tx_disable(np->dev);
5737}
5738
5739static void niu_netif_start(struct niu *np)
5740{
5741 /* NOTE: unconditional netif_wake_queue is only appropriate
5742 * so long as all callers are assured to have free tx slots
5743 * (such as after niu_init_hw).
5744 */
5745 netif_wake_queue(np->dev);
5746
5747 niu_enable_napi(np);
5748
5749 niu_enable_interrupts(np, 1);
5750}
5751
5752static void niu_reset_task(struct work_struct *work)
5753{
5754 struct niu *np = container_of(work, struct niu, reset_task);
5755 unsigned long flags;
5756 int err;
5757
5758 spin_lock_irqsave(&np->lock, flags);
5759 if (!netif_running(np->dev)) {
5760 spin_unlock_irqrestore(&np->lock, flags);
5761 return;
5762 }
5763
5764 spin_unlock_irqrestore(&np->lock, flags);
5765
5766 del_timer_sync(&np->timer);
5767
5768 niu_netif_stop(np);
5769
5770 spin_lock_irqsave(&np->lock, flags);
5771
5772 niu_stop_hw(np);
5773
5774 err = niu_init_hw(np);
5775 if (!err) {
5776 np->timer.expires = jiffies + HZ;
5777 add_timer(&np->timer);
5778 niu_netif_start(np);
5779 }
5780
5781 spin_unlock_irqrestore(&np->lock, flags);
5782}
5783
5784static void niu_tx_timeout(struct net_device *dev)
5785{
5786 struct niu *np = netdev_priv(dev);
5787
5788 dev_err(np->device, PFX "%s: Transmit timed out, resetting\n",
5789 dev->name);
5790
5791 schedule_work(&np->reset_task);
5792}
5793
5794static void niu_set_txd(struct tx_ring_info *rp, int index,
5795 u64 mapping, u64 len, u64 mark,
5796 u64 n_frags)
5797{
5798 __le64 *desc = &rp->descr[index];
5799
5800 *desc = cpu_to_le64(mark |
5801 (n_frags << TX_DESC_NUM_PTR_SHIFT) |
5802 (len << TX_DESC_TR_LEN_SHIFT) |
5803 (mapping & TX_DESC_SAD));
5804}
5805
5806static u64 niu_compute_tx_flags(struct sk_buff *skb, struct ethhdr *ehdr,
5807 u64 pad_bytes, u64 len)
5808{
5809 u16 eth_proto, eth_proto_inner;
5810 u64 csum_bits, l3off, ihl, ret;
5811 u8 ip_proto;
5812 int ipv6;
5813
5814 eth_proto = be16_to_cpu(ehdr->h_proto);
5815 eth_proto_inner = eth_proto;
5816 if (eth_proto == ETH_P_8021Q) {
5817 struct vlan_ethhdr *vp = (struct vlan_ethhdr *) ehdr;
5818 __be16 val = vp->h_vlan_encapsulated_proto;
5819
5820 eth_proto_inner = be16_to_cpu(val);
5821 }
5822
5823 ipv6 = ihl = 0;
5824 switch (skb->protocol) {
5825 case __constant_htons(ETH_P_IP):
5826 ip_proto = ip_hdr(skb)->protocol;
5827 ihl = ip_hdr(skb)->ihl;
5828 break;
5829 case __constant_htons(ETH_P_IPV6):
5830 ip_proto = ipv6_hdr(skb)->nexthdr;
5831 ihl = (40 >> 2);
5832 ipv6 = 1;
5833 break;
5834 default:
5835 ip_proto = ihl = 0;
5836 break;
5837 }
5838
5839 csum_bits = TXHDR_CSUM_NONE;
5840 if (skb->ip_summed == CHECKSUM_PARTIAL) {
5841 u64 start, stuff;
5842
5843 csum_bits = (ip_proto == IPPROTO_TCP ?
5844 TXHDR_CSUM_TCP :
5845 (ip_proto == IPPROTO_UDP ?
5846 TXHDR_CSUM_UDP : TXHDR_CSUM_SCTP));
5847
5848 start = skb_transport_offset(skb) -
5849 (pad_bytes + sizeof(struct tx_pkt_hdr));
5850 stuff = start + skb->csum_offset;
5851
5852 csum_bits |= (start / 2) << TXHDR_L4START_SHIFT;
5853 csum_bits |= (stuff / 2) << TXHDR_L4STUFF_SHIFT;
5854 }
5855
5856 l3off = skb_network_offset(skb) -
5857 (pad_bytes + sizeof(struct tx_pkt_hdr));
5858
5859 ret = (((pad_bytes / 2) << TXHDR_PAD_SHIFT) |
5860 (len << TXHDR_LEN_SHIFT) |
5861 ((l3off / 2) << TXHDR_L3START_SHIFT) |
5862 (ihl << TXHDR_IHL_SHIFT) |
5863 ((eth_proto_inner < 1536) ? TXHDR_LLC : 0) |
5864 ((eth_proto == ETH_P_8021Q) ? TXHDR_VLAN : 0) |
5865 (ipv6 ? TXHDR_IP_VER : 0) |
5866 csum_bits);
5867
5868 return ret;
5869}
5870
5871static struct tx_ring_info *tx_ring_select(struct niu *np, struct sk_buff *skb)
5872{
5873 return &np->tx_rings[0];
5874}
5875
5876static int niu_start_xmit(struct sk_buff *skb, struct net_device *dev)
5877{
5878 struct niu *np = netdev_priv(dev);
5879 unsigned long align, headroom;
5880 struct tx_ring_info *rp;
5881 struct tx_pkt_hdr *tp;
5882 unsigned int len, nfg;
5883 struct ethhdr *ehdr;
5884 int prod, i, tlen;
5885 u64 mapping, mrk;
5886
5887 rp = tx_ring_select(np, skb);
5888
5889 if (niu_tx_avail(rp) <= (skb_shinfo(skb)->nr_frags + 1)) {
5890 netif_stop_queue(dev);
5891 dev_err(np->device, PFX "%s: BUG! Tx ring full when "
5892 "queue awake!\n", dev->name);
5893 rp->tx_errors++;
5894 return NETDEV_TX_BUSY;
5895 }
5896
5897 if (skb->len < ETH_ZLEN) {
5898 unsigned int pad_bytes = ETH_ZLEN - skb->len;
5899
5900 if (skb_pad(skb, pad_bytes))
5901 goto out;
5902 skb_put(skb, pad_bytes);
5903 }
5904
5905 len = sizeof(struct tx_pkt_hdr) + 15;
5906 if (skb_headroom(skb) < len) {
5907 struct sk_buff *skb_new;
5908
5909 skb_new = skb_realloc_headroom(skb, len);
5910 if (!skb_new) {
5911 rp->tx_errors++;
5912 goto out_drop;
5913 }
5914 kfree_skb(skb);
5915 skb = skb_new;
3ebebccf
DM		 5916 } else
5917 skb_orphan(skb);
a3138df9
DM		 5918
5919 align = ((unsigned long) skb->data & (16 - 1));
5920 headroom = align + sizeof(struct tx_pkt_hdr);
5921
5922 ehdr = (struct ethhdr *) skb->data;
5923 tp = (struct tx_pkt_hdr *) skb_push(skb, headroom);
5924
5925 len = skb->len - sizeof(struct tx_pkt_hdr);
5926 tp->flags = cpu_to_le64(niu_compute_tx_flags(skb, ehdr, align, len));
5927 tp->resv = 0;
5928
5929 len = skb_headlen(skb);
5930 mapping = np->ops->map_single(np->device, skb->data,
5931 len, DMA_TO_DEVICE);
5932
5933 prod = rp->prod;
5934
5935 rp->tx_buffs[prod].skb = skb;
5936 rp->tx_buffs[prod].mapping = mapping;
5937
5938 mrk = TX_DESC_SOP;
5939 if (++rp->mark_counter == rp->mark_freq) {
5940 rp->mark_counter = 0;
5941 mrk |= TX_DESC_MARK;
5942 rp->mark_pending++;
5943 }
5944
5945 tlen = len;
5946 nfg = skb_shinfo(skb)->nr_frags;
5947 while (tlen > 0) {
5948 tlen -= MAX_TX_DESC_LEN;
5949 nfg++;
5950 }
5951
5952 while (len > 0) {
5953 unsigned int this_len = len;
5954
5955 if (this_len > MAX_TX_DESC_LEN)
5956 this_len = MAX_TX_DESC_LEN;
5957
5958 niu_set_txd(rp, prod, mapping, this_len, mrk, nfg);
5959 mrk = nfg = 0;
5960
5961 prod = NEXT_TX(rp, prod);
5962 mapping += this_len;
5963 len -= this_len;
5964 }
5965
5966 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
5967 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5968
5969 len = frag->size;
5970 mapping = np->ops->map_page(np->device, frag->page,
5971 frag->page_offset, len,
5972 DMA_TO_DEVICE);
5973
5974 rp->tx_buffs[prod].skb = NULL;
5975 rp->tx_buffs[prod].mapping = mapping;
5976
5977 niu_set_txd(rp, prod, mapping, len, 0, 0);
5978
5979 prod = NEXT_TX(rp, prod);
5980 }
5981
5982 if (prod < rp->prod)
5983 rp->wrap_bit ^= TX_RING_KICK_WRAP;
5984 rp->prod = prod;
5985
5986 nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3));
5987
5988 if (unlikely(niu_tx_avail(rp) <= (MAX_SKB_FRAGS + 1))) {
5989 netif_stop_queue(dev);
5990 if (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp))
5991 netif_wake_queue(dev);
5992 }
5993
5994 dev->trans_start = jiffies;
5995
5996out:
5997 return NETDEV_TX_OK;
5998
5999out_drop:
6000 rp->tx_errors++;
6001 kfree_skb(skb);
6002 goto out;
6003}
6004
6005static int niu_change_mtu(struct net_device *dev, int new_mtu)
6006{
6007 struct niu *np = netdev_priv(dev);
6008 int err, orig_jumbo, new_jumbo;
6009
6010 if (new_mtu < 68 || new_mtu > NIU_MAX_MTU)
6011 return -EINVAL;
6012
6013 orig_jumbo = (dev->mtu > ETH_DATA_LEN);
6014 new_jumbo = (new_mtu > ETH_DATA_LEN);
6015
6016 dev->mtu = new_mtu;
6017
6018 if (!netif_running(dev) ||
6019 (orig_jumbo == new_jumbo))
6020 return 0;
6021
6022 niu_full_shutdown(np, dev);
6023
6024 niu_free_channels(np);
6025
6026 niu_enable_napi(np);
6027
6028 err = niu_alloc_channels(np);
6029 if (err)
6030 return err;
6031
6032 spin_lock_irq(&np->lock);
6033
6034 err = niu_init_hw(np);
6035 if (!err) {
6036 init_timer(&np->timer);
6037 np->timer.expires = jiffies + HZ;
6038 np->timer.data = (unsigned long) np;
6039 np->timer.function = niu_timer;
6040
6041 err = niu_enable_interrupts(np, 1);
6042 if (err)
6043 niu_stop_hw(np);
6044 }
6045
6046 spin_unlock_irq(&np->lock);
6047
6048 if (!err) {
6049 netif_start_queue(dev);
6050 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6051 netif_carrier_on(dev);
6052
6053 add_timer(&np->timer);
6054 }
6055
6056 return err;
6057}
6058
6059static void niu_get_drvinfo(struct net_device *dev,
6060 struct ethtool_drvinfo *info)
6061{
6062 struct niu *np = netdev_priv(dev);
6063 struct niu_vpd *vpd = &np->vpd;
6064
6065 strcpy(info->driver, DRV_MODULE_NAME);
6066 strcpy(info->version, DRV_MODULE_VERSION);
6067 sprintf(info->fw_version, "%d.%d",
6068 vpd->fcode_major, vpd->fcode_minor);
6069 if (np->parent->plat_type != PLAT_TYPE_NIU)
6070 strcpy(info->bus_info, pci_name(np->pdev));
6071}
6072
6073static int niu_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6074{
6075 struct niu *np = netdev_priv(dev);
6076 struct niu_link_config *lp;
6077
6078 lp = &np->link_config;
6079
6080 memset(cmd, 0, sizeof(*cmd));
6081 cmd->phy_address = np->phy_addr;
6082 cmd->supported = lp->supported;
6083 cmd->advertising = lp->advertising;
6084 cmd->autoneg = lp->autoneg;
6085 cmd->speed = lp->active_speed;
6086 cmd->duplex = lp->active_duplex;
6087
6088 return 0;
6089}
6090
6091static int niu_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6092{
6093 return -EINVAL;
6094}
6095
6096static u32 niu_get_msglevel(struct net_device *dev)
6097{
6098 struct niu *np = netdev_priv(dev);
6099 return np->msg_enable;
6100}
6101
6102static void niu_set_msglevel(struct net_device *dev, u32 value)
6103{
6104 struct niu *np = netdev_priv(dev);
6105 np->msg_enable = value;
6106}
6107
6108static int niu_get_eeprom_len(struct net_device *dev)
6109{
6110 struct niu *np = netdev_priv(dev);
6111
6112 return np->eeprom_len;
6113}
6114
6115static int niu_get_eeprom(struct net_device *dev,
6116 struct ethtool_eeprom *eeprom, u8 *data)
6117{
6118 struct niu *np = netdev_priv(dev);
6119 u32 offset, len, val;
6120
6121 offset = eeprom->offset;
6122 len = eeprom->len;
6123
6124 if (offset + len < offset)
6125 return -EINVAL;
6126 if (offset >= np->eeprom_len)
6127 return -EINVAL;
6128 if (offset + len > np->eeprom_len)
6129 len = eeprom->len = np->eeprom_len - offset;
6130
6131 if (offset & 3) {
6132 u32 b_offset, b_count;
6133
6134 b_offset = offset & 3;
6135 b_count = 4 - b_offset;
6136 if (b_count > len)
6137 b_count = len;
6138
6139 val = nr64(ESPC_NCR((offset - b_offset) / 4));
6140 memcpy(data, ((char *)&val) + b_offset, b_count);
6141 data += b_count;
6142 len -= b_count;
6143 offset += b_count;
6144 }
6145 while (len >= 4) {
6146 val = nr64(ESPC_NCR(offset / 4));
6147 memcpy(data, &val, 4);
6148 data += 4;
6149 len -= 4;
6150 offset += 4;
6151 }
6152 if (len) {
6153 val = nr64(ESPC_NCR(offset / 4));
6154 memcpy(data, &val, len);
6155 }
6156 return 0;
6157}
6158
6159static const struct {
6160 const char string[ETH_GSTRING_LEN];
6161} niu_xmac_stat_keys[] = {
6162 { "tx_frames" },
6163 { "tx_bytes" },
6164 { "tx_fifo_errors" },
6165 { "tx_overflow_errors" },
6166 { "tx_max_pkt_size_errors" },
6167 { "tx_underflow_errors" },
6168 { "rx_local_faults" },
6169 { "rx_remote_faults" },
6170 { "rx_link_faults" },
6171 { "rx_align_errors" },
6172 { "rx_frags" },
6173 { "rx_mcasts" },
6174 { "rx_bcasts" },
6175 { "rx_hist_cnt1" },
6176 { "rx_hist_cnt2" },
6177 { "rx_hist_cnt3" },
6178 { "rx_hist_cnt4" },
6179 { "rx_hist_cnt5" },
6180 { "rx_hist_cnt6" },
6181 { "rx_hist_cnt7" },
6182 { "rx_octets" },
6183 { "rx_code_violations" },
6184 { "rx_len_errors" },
6185 { "rx_crc_errors" },
6186 { "rx_underflows" },
6187 { "rx_overflows" },
6188 { "pause_off_state" },
6189 { "pause_on_state" },
6190 { "pause_received" },
6191};
6192
6193#define NUM_XMAC_STAT_KEYS ARRAY_SIZE(niu_xmac_stat_keys)
6194
6195static const struct {
6196 const char string[ETH_GSTRING_LEN];
6197} niu_bmac_stat_keys[] = {
6198 { "tx_underflow_errors" },
6199 { "tx_max_pkt_size_errors" },
6200 { "tx_bytes" },
6201 { "tx_frames" },
6202 { "rx_overflows" },
6203 { "rx_frames" },
6204 { "rx_align_errors" },
6205 { "rx_crc_errors" },
6206 { "rx_len_errors" },
6207 { "pause_off_state" },
6208 { "pause_on_state" },
6209 { "pause_received" },
6210};
6211
6212#define NUM_BMAC_STAT_KEYS ARRAY_SIZE(niu_bmac_stat_keys)
6213
6214static const struct {
6215 const char string[ETH_GSTRING_LEN];
6216} niu_rxchan_stat_keys[] = {
6217 { "rx_channel" },
6218 { "rx_packets" },
6219 { "rx_bytes" },
6220 { "rx_dropped" },
6221 { "rx_errors" },
6222};
6223
6224#define NUM_RXCHAN_STAT_KEYS ARRAY_SIZE(niu_rxchan_stat_keys)
6225
6226static const struct {
6227 const char string[ETH_GSTRING_LEN];
6228} niu_txchan_stat_keys[] = {
6229 { "tx_channel" },
6230 { "tx_packets" },
6231 { "tx_bytes" },
6232 { "tx_errors" },
6233};
6234
6235#define NUM_TXCHAN_STAT_KEYS ARRAY_SIZE(niu_txchan_stat_keys)
6236
6237static void niu_get_strings(struct net_device *dev, u32 stringset, u8 *data)
6238{
6239 struct niu *np = netdev_priv(dev);
6240 int i;
6241
6242 if (stringset != ETH_SS_STATS)
6243 return;
6244
6245 if (np->flags & NIU_FLAGS_XMAC) {
6246 memcpy(data, niu_xmac_stat_keys,
6247 sizeof(niu_xmac_stat_keys));
6248 data += sizeof(niu_xmac_stat_keys);
6249 } else {
6250 memcpy(data, niu_bmac_stat_keys,
6251 sizeof(niu_bmac_stat_keys));
6252 data += sizeof(niu_bmac_stat_keys);
6253 }
6254 for (i = 0; i < np->num_rx_rings; i++) {
6255 memcpy(data, niu_rxchan_stat_keys,
6256 sizeof(niu_rxchan_stat_keys));
6257 data += sizeof(niu_rxchan_stat_keys);
6258 }
6259 for (i = 0; i < np->num_tx_rings; i++) {
6260 memcpy(data, niu_txchan_stat_keys,
6261 sizeof(niu_txchan_stat_keys));
6262 data += sizeof(niu_txchan_stat_keys);
6263 }
6264}
6265
6266static int niu_get_stats_count(struct net_device *dev)
6267{
6268 struct niu *np = netdev_priv(dev);
6269
6270 return ((np->flags & NIU_FLAGS_XMAC ?
6271 NUM_XMAC_STAT_KEYS :
6272 NUM_BMAC_STAT_KEYS) +
6273 (np->num_rx_rings * NUM_RXCHAN_STAT_KEYS) +
6274 (np->num_tx_rings * NUM_TXCHAN_STAT_KEYS));
6275}
6276
6277static void niu_get_ethtool_stats(struct net_device *dev,
6278 struct ethtool_stats *stats, u64 *data)
6279{
6280 struct niu *np = netdev_priv(dev);
6281 int i;
6282
6283 niu_sync_mac_stats(np);
6284 if (np->flags & NIU_FLAGS_XMAC) {
6285 memcpy(data, &np->mac_stats.xmac,
6286 sizeof(struct niu_xmac_stats));
6287 data += (sizeof(struct niu_xmac_stats) / sizeof(u64));
6288 } else {
6289 memcpy(data, &np->mac_stats.bmac,
6290 sizeof(struct niu_bmac_stats));
6291 data += (sizeof(struct niu_bmac_stats) / sizeof(u64));
6292 }
6293 for (i = 0; i < np->num_rx_rings; i++) {
6294 struct rx_ring_info *rp = &np->rx_rings[i];
6295
6296 data[0] = rp->rx_channel;
6297 data[1] = rp->rx_packets;
6298 data[2] = rp->rx_bytes;
6299 data[3] = rp->rx_dropped;
6300 data[4] = rp->rx_errors;
6301 data += 5;
6302 }
6303 for (i = 0; i < np->num_tx_rings; i++) {
6304 struct tx_ring_info *rp = &np->tx_rings[i];
6305
6306 data[0] = rp->tx_channel;
6307 data[1] = rp->tx_packets;
6308 data[2] = rp->tx_bytes;
6309 data[3] = rp->tx_errors;
6310 data += 4;
6311 }
6312}
6313
6314static u64 niu_led_state_save(struct niu *np)
6315{
6316 if (np->flags & NIU_FLAGS_XMAC)
6317 return nr64_mac(XMAC_CONFIG);
6318 else
6319 return nr64_mac(BMAC_XIF_CONFIG);
6320}
6321
6322static void niu_led_state_restore(struct niu *np, u64 val)
6323{
6324 if (np->flags & NIU_FLAGS_XMAC)
6325 nw64_mac(XMAC_CONFIG, val);
6326 else
6327 nw64_mac(BMAC_XIF_CONFIG, val);
6328}
6329
6330static void niu_force_led(struct niu *np, int on)
6331{
6332 u64 val, reg, bit;
6333
6334 if (np->flags & NIU_FLAGS_XMAC) {
6335 reg = XMAC_CONFIG;
6336 bit = XMAC_CONFIG_FORCE_LED_ON;
6337 } else {
6338 reg = BMAC_XIF_CONFIG;
6339 bit = BMAC_XIF_CONFIG_LINK_LED;
6340 }
6341
6342 val = nr64_mac(reg);
6343 if (on)
6344 val |= bit;
6345 else
6346 val &= ~bit;
6347 nw64_mac(reg, val);
6348}
6349
6350static int niu_phys_id(struct net_device *dev, u32 data)
6351{
6352 struct niu *np = netdev_priv(dev);
6353 u64 orig_led_state;
6354 int i;
6355
6356 if (!netif_running(dev))
6357 return -EAGAIN;
6358
6359 if (data == 0)
6360 data = 2;
6361
6362 orig_led_state = niu_led_state_save(np);
6363 for (i = 0; i < (data * 2); i++) {
6364 int on = ((i % 2) == 0);
6365
6366 niu_force_led(np, on);
6367
6368 if (msleep_interruptible(500))
6369 break;
6370 }
6371 niu_led_state_restore(np, orig_led_state);
6372
6373 return 0;
6374}
6375
6376static const struct ethtool_ops niu_ethtool_ops = {
6377 .get_drvinfo = niu_get_drvinfo,
6378 .get_link = ethtool_op_get_link,
6379 .get_msglevel = niu_get_msglevel,
6380 .set_msglevel = niu_set_msglevel,
6381 .get_eeprom_len = niu_get_eeprom_len,
6382 .get_eeprom = niu_get_eeprom,
6383 .get_settings = niu_get_settings,
6384 .set_settings = niu_set_settings,
6385 .get_strings = niu_get_strings,
6386 .get_stats_count = niu_get_stats_count,
6387 .get_ethtool_stats = niu_get_ethtool_stats,
6388 .phys_id = niu_phys_id,
6389};
6390
6391static int niu_ldg_assign_ldn(struct niu *np, struct niu_parent *parent,
6392 int ldg, int ldn)
6393{
6394 if (ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX)
6395 return -EINVAL;
6396 if (ldn < 0 || ldn > LDN_MAX)
6397 return -EINVAL;
6398
6399 parent->ldg_map[ldn] = ldg;
6400
6401 if (np->parent->plat_type == PLAT_TYPE_NIU) {
6402 /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by
6403 * the firmware, and we're not supposed to change them.
6404 * Validate the mapping, because if it's wrong we probably
6405 * won't get any interrupts and that's painful to debug.
6406 */
6407 if (nr64(LDG_NUM(ldn)) != ldg) {
6408 dev_err(np->device, PFX "Port %u, mis-matched "
6409 "LDG assignment "
6410 "for ldn %d, should be %d is %llu\n",
6411 np->port, ldn, ldg,
6412 (unsigned long long) nr64(LDG_NUM(ldn)));
6413 return -EINVAL;
6414 }
6415 } else
6416 nw64(LDG_NUM(ldn), ldg);
6417
6418 return 0;
6419}
6420
6421static int niu_set_ldg_timer_res(struct niu *np, int res)
6422{
6423 if (res < 0 || res > LDG_TIMER_RES_VAL)
6424 return -EINVAL;
6425
6426
6427 nw64(LDG_TIMER_RES, res);
6428
6429 return 0;
6430}
6431
6432static int niu_set_ldg_sid(struct niu *np, int ldg, int func, int vector)
6433{
6434 if ((ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) ||
6435 (func < 0 || func > 3) ||
6436 (vector < 0 || vector > 0x1f))
6437 return -EINVAL;
6438
6439 nw64(SID(ldg), (func << SID_FUNC_SHIFT) | vector);
6440
6441 return 0;
6442}
6443
6444static int __devinit niu_pci_eeprom_read(struct niu *np, u32 addr)
6445{
6446 u64 frame, frame_base = (ESPC_PIO_STAT_READ_START |
6447 (addr << ESPC_PIO_STAT_ADDR_SHIFT));
6448 int limit;
6449
6450 if (addr > (ESPC_PIO_STAT_ADDR >> ESPC_PIO_STAT_ADDR_SHIFT))
6451 return -EINVAL;
6452
6453 frame = frame_base;
6454 nw64(ESPC_PIO_STAT, frame);
6455 limit = 64;
6456 do {
6457 udelay(5);
6458 frame = nr64(ESPC_PIO_STAT);
6459 if (frame & ESPC_PIO_STAT_READ_END)
6460 break;
6461 } while (limit--);
6462 if (!(frame & ESPC_PIO_STAT_READ_END)) {
6463 dev_err(np->device, PFX "EEPROM read timeout frame[%llx]\n",
6464 (unsigned long long) frame);
6465 return -ENODEV;
6466 }
6467
6468 frame = frame_base;
6469 nw64(ESPC_PIO_STAT, frame);
6470 limit = 64;
6471 do {
6472 udelay(5);
6473 frame = nr64(ESPC_PIO_STAT);
6474 if (frame & ESPC_PIO_STAT_READ_END)
6475 break;
6476 } while (limit--);
6477 if (!(frame & ESPC_PIO_STAT_READ_END)) {
6478 dev_err(np->device, PFX "EEPROM read timeout frame[%llx]\n",
6479 (unsigned long long) frame);
6480 return -ENODEV;
6481 }
6482
6483 frame = nr64(ESPC_PIO_STAT);
6484 return (frame & ESPC_PIO_STAT_DATA) >> ESPC_PIO_STAT_DATA_SHIFT;
6485}
6486
6487static int __devinit niu_pci_eeprom_read16(struct niu *np, u32 off)
6488{
6489 int err = niu_pci_eeprom_read(np, off);
6490 u16 val;
6491
6492 if (err < 0)
6493 return err;
6494 val = (err << 8);
6495 err = niu_pci_eeprom_read(np, off + 1);
6496 if (err < 0)
6497 return err;
6498 val |= (err & 0xff);
6499
6500 return val;
6501}
6502
6503static int __devinit niu_pci_eeprom_read16_swp(struct niu *np, u32 off)
6504{
6505 int err = niu_pci_eeprom_read(np, off);
6506 u16 val;
6507
6508 if (err < 0)
6509 return err;
6510
6511 val = (err & 0xff);
6512 err = niu_pci_eeprom_read(np, off + 1);
6513 if (err < 0)
6514 return err;
6515
6516 val |= (err & 0xff) << 8;
6517
6518 return val;
6519}
6520
6521static int __devinit niu_pci_vpd_get_propname(struct niu *np,
6522 u32 off,
6523 char *namebuf,
6524 int namebuf_len)
6525{
6526 int i;
6527
6528 for (i = 0; i < namebuf_len; i++) {
6529 int err = niu_pci_eeprom_read(np, off + i);
6530 if (err < 0)
6531 return err;
6532 *namebuf++ = err;
6533 if (!err)
6534 break;
6535 }
6536 if (i >= namebuf_len)
6537 return -EINVAL;
6538
6539 return i + 1;
6540}
6541
6542static void __devinit niu_vpd_parse_version(struct niu *np)
6543{
6544 struct niu_vpd *vpd = &np->vpd;
6545 int len = strlen(vpd->version) + 1;
6546 const char *s = vpd->version;
6547 int i;
6548
6549 for (i = 0; i < len - 5; i++) {
6550 if (!strncmp(s + i, "FCode ", 5))
6551 break;
6552 }
6553 if (i >= len - 5)
6554 return;
6555
6556 s += i + 5;
6557 sscanf(s, "%d.%d", &vpd->fcode_major, &vpd->fcode_minor);
6558
6559 niudbg(PROBE, "VPD_SCAN: FCODE major(%d) minor(%d)\n",
6560 vpd->fcode_major, vpd->fcode_minor);
6561 if (vpd->fcode_major > NIU_VPD_MIN_MAJOR ||
6562 (vpd->fcode_major == NIU_VPD_MIN_MAJOR &&
6563 vpd->fcode_minor >= NIU_VPD_MIN_MINOR))
6564 np->flags |= NIU_FLAGS_VPD_VALID;
6565}
6566
6567/* ESPC_PIO_EN_ENABLE must be set */
6568static int __devinit niu_pci_vpd_scan_props(struct niu *np,
6569 u32 start, u32 end)
6570{
6571 unsigned int found_mask = 0;
6572#define FOUND_MASK_MODEL 0x00000001
6573#define FOUND_MASK_BMODEL 0x00000002
6574#define FOUND_MASK_VERS 0x00000004
6575#define FOUND_MASK_MAC 0x00000008
6576#define FOUND_MASK_NMAC 0x00000010
6577#define FOUND_MASK_PHY 0x00000020
6578#define FOUND_MASK_ALL 0x0000003f
6579
6580 niudbg(PROBE, "VPD_SCAN: start[%x] end[%x]\n",
6581 start, end);
6582 while (start < end) {
6583 int len, err, instance, type, prop_len;
6584 char namebuf[64];
6585 u8 *prop_buf;
6586 int max_len;
6587
6588 if (found_mask == FOUND_MASK_ALL) {
6589 niu_vpd_parse_version(np);
6590 return 1;
6591 }
6592
6593 err = niu_pci_eeprom_read(np, start + 2);
6594 if (err < 0)
6595 return err;
6596 len = err;
6597 start += 3;
6598
6599 instance = niu_pci_eeprom_read(np, start);
6600 type = niu_pci_eeprom_read(np, start + 3);
6601 prop_len = niu_pci_eeprom_read(np, start + 4);
6602 err = niu_pci_vpd_get_propname(np, start + 5, namebuf, 64);
6603 if (err < 0)
6604 return err;
6605
6606 prop_buf = NULL;
6607 max_len = 0;
6608 if (!strcmp(namebuf, "model")) {
6609 prop_buf = np->vpd.model;
6610 max_len = NIU_VPD_MODEL_MAX;
6611 found_mask |= FOUND_MASK_MODEL;
6612 } else if (!strcmp(namebuf, "board-model")) {
6613 prop_buf = np->vpd.board_model;
6614 max_len = NIU_VPD_BD_MODEL_MAX;
6615 found_mask |= FOUND_MASK_BMODEL;
6616 } else if (!strcmp(namebuf, "version")) {
6617 prop_buf = np->vpd.version;
6618 max_len = NIU_VPD_VERSION_MAX;
6619 found_mask |= FOUND_MASK_VERS;
6620 } else if (!strcmp(namebuf, "local-mac-address")) {
6621 prop_buf = np->vpd.local_mac;
6622 max_len = ETH_ALEN;
6623 found_mask |= FOUND_MASK_MAC;
6624 } else if (!strcmp(namebuf, "num-mac-addresses")) {
6625 prop_buf = &np->vpd.mac_num;
6626 max_len = 1;
6627 found_mask |= FOUND_MASK_NMAC;
6628 } else if (!strcmp(namebuf, "phy-type")) {
6629 prop_buf = np->vpd.phy_type;
6630 max_len = NIU_VPD_PHY_TYPE_MAX;
6631 found_mask |= FOUND_MASK_PHY;
6632 }
6633
6634 if (max_len && prop_len > max_len) {
6635 dev_err(np->device, PFX "Property '%s' length (%d) is "
6636 "too long.\n", namebuf, prop_len);
6637 return -EINVAL;
6638 }
6639
6640 if (prop_buf) {
6641 u32 off = start + 5 + err;
6642 int i;
6643
6644 niudbg(PROBE, "VPD_SCAN: Reading in property [%s] "
6645 "len[%d]\n", namebuf, prop_len);
6646 for (i = 0; i < prop_len; i++)
6647 *prop_buf++ = niu_pci_eeprom_read(np, off + i);
6648 }
6649
6650 start += len;
6651 }
6652
6653 return 0;
6654}
6655
6656/* ESPC_PIO_EN_ENABLE must be set */
6657static void __devinit niu_pci_vpd_fetch(struct niu *np, u32 start)
6658{
6659 u32 offset;
6660 int err;
6661
6662 err = niu_pci_eeprom_read16_swp(np, start + 1);
6663 if (err < 0)
6664 return;
6665
6666 offset = err + 3;
6667
6668 while (start + offset < ESPC_EEPROM_SIZE) {
6669 u32 here = start + offset;
6670 u32 end;
6671
6672 err = niu_pci_eeprom_read(np, here);
6673 if (err != 0x90)
6674 return;
6675
6676 err = niu_pci_eeprom_read16_swp(np, here + 1);
6677 if (err < 0)
6678 return;
6679
6680 here = start + offset + 3;
6681 end = start + offset + err;
6682
6683 offset += err;
6684
6685 err = niu_pci_vpd_scan_props(np, here, end);
6686 if (err < 0 || err == 1)
6687 return;
6688 }
6689}
6690
6691/* ESPC_PIO_EN_ENABLE must be set */
6692static u32 __devinit niu_pci_vpd_offset(struct niu *np)
6693{
6694 u32 start = 0, end = ESPC_EEPROM_SIZE, ret;
6695 int err;
6696
6697 while (start < end) {
6698 ret = start;
6699
6700 /* ROM header signature? */
6701 err = niu_pci_eeprom_read16(np, start + 0);
6702 if (err != 0x55aa)
6703 return 0;
6704
6705 /* Apply offset to PCI data structure. */
6706 err = niu_pci_eeprom_read16(np, start + 23);
6707 if (err < 0)
6708 return 0;
6709 start += err;
6710
6711 /* Check for "PCIR" signature. */
6712 err = niu_pci_eeprom_read16(np, start + 0);
6713 if (err != 0x5043)
6714 return 0;
6715 err = niu_pci_eeprom_read16(np, start + 2);
6716 if (err != 0x4952)
6717 return 0;
6718
6719 /* Check for OBP image type. */
6720 err = niu_pci_eeprom_read(np, start + 20);
6721 if (err < 0)
6722 return 0;
6723 if (err != 0x01) {
6724 err = niu_pci_eeprom_read(np, ret + 2);
6725 if (err < 0)
6726 return 0;
6727
6728 start = ret + (err * 512);
6729 continue;
6730 }
6731
6732 err = niu_pci_eeprom_read16_swp(np, start + 8);
6733 if (err < 0)
6734 return err;
6735 ret += err;
6736
6737 err = niu_pci_eeprom_read(np, ret + 0);
6738 if (err != 0x82)
6739 return 0;
6740
6741 return ret;
6742 }
6743
6744 return 0;
6745}
6746
6747static int __devinit niu_phy_type_prop_decode(struct niu *np,
6748 const char *phy_prop)
6749{
6750 if (!strcmp(phy_prop, "mif")) {
6751 /* 1G copper, MII */
6752 np->flags &= ~(NIU_FLAGS_FIBER |
6753 NIU_FLAGS_10G);
6754 np->mac_xcvr = MAC_XCVR_MII;
6755 } else if (!strcmp(phy_prop, "xgf")) {
6756 /* 10G fiber, XPCS */
6757 np->flags |= (NIU_FLAGS_10G |
6758 NIU_FLAGS_FIBER);
6759 np->mac_xcvr = MAC_XCVR_XPCS;
6760 } else if (!strcmp(phy_prop, "pcs")) {
6761 /* 1G fiber, PCS */
6762 np->flags &= ~NIU_FLAGS_10G;
6763 np->flags |= NIU_FLAGS_FIBER;
6764 np->mac_xcvr = MAC_XCVR_PCS;
6765 } else if (!strcmp(phy_prop, "xgc")) {
6766 /* 10G copper, XPCS */
6767 np->flags |= NIU_FLAGS_10G;
6768 np->flags &= ~NIU_FLAGS_FIBER;
6769 np->mac_xcvr = MAC_XCVR_XPCS;
6770 } else {
6771 return -EINVAL;
6772 }
6773 return 0;
6774}
6775
7f7c4072
MW		 6776/* niu board models have a trailing dash version incremented
6777 * with HW rev change. Need to ingnore the dash version while
6778 * checking for match
6779 *
6780 * for example, for the 10G card the current vpd.board_model
6781 * is 501-5283-04, of which -04 is the dash version and have
6782 * to be ignored
6783 */
6784static int niu_board_model_match(struct niu *np, const char *model)
6785{
6786 return !strncmp(np->vpd.board_model, model, strlen(model));
6787}
6788
6789static int niu_pci_vpd_get_nports(struct niu *np)
6790{
6791 int ports = 0;
6792
6793 if ((niu_board_model_match(np, NIU_QGC_LP_BM_STR)) ||
6794 (niu_board_model_match(np, NIU_QGC_PEM_BM_STR)) ||
6795 (niu_board_model_match(np, NIU_ALONSO_BM_STR))) {
6796 ports = 4;
6797 } else if ((niu_board_model_match(np, NIU_2XGF_LP_BM_STR)) ||
6798 (niu_board_model_match(np, NIU_2XGF_PEM_BM_STR)) ||
6799 (niu_board_model_match(np, NIU_FOXXY_BM_STR)) ||
6800 (niu_board_model_match(np, NIU_2XGF_MRVL_BM_STR))) {
6801 ports = 2;
6802 }
6803
6804 return ports;
6805}
6806
a3138df9
DM		 6807static void __devinit niu_pci_vpd_validate(struct niu *np)
6808{
6809 struct net_device *dev = np->dev;
6810 struct niu_vpd *vpd = &np->vpd;
6811 u8 val8;
6812
6813 if (!is_valid_ether_addr(&vpd->local_mac[0])) {
6814 dev_err(np->device, PFX "VPD MAC invalid, "
6815 "falling back to SPROM.\n");
6816
6817 np->flags &= ~NIU_FLAGS_VPD_VALID;
6818 return;
6819 }
6820
5fbd7e24
MW		 6821 if (!strcmp(np->vpd.model, "SUNW,CP3220") ||
6822 !strcmp(np->vpd.model, "SUNW,CP3260")) {
6823 np->flags |= NIU_FLAGS_10G;
6824 np->flags &= ~NIU_FLAGS_FIBER;
6825 np->flags |= NIU_FLAGS_XCVR_SERDES;
6826 np->mac_xcvr = MAC_XCVR_PCS;
6827 if (np->port > 1) {
6828 np->flags |= NIU_FLAGS_FIBER;
6829 np->flags &= ~NIU_FLAGS_10G;
6830 }
6831 if (np->flags & NIU_FLAGS_10G)
6832 np->mac_xcvr = MAC_XCVR_XPCS;
6833 } else if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
a3138df9
DM		 6834 dev_err(np->device, PFX "Illegal phy string [%s].\n",
6835 np->vpd.phy_type);
6836 dev_err(np->device, PFX "Falling back to SPROM.\n");
6837 np->flags &= ~NIU_FLAGS_VPD_VALID;
6838 return;
6839 }
6840
6841 memcpy(dev->perm_addr, vpd->local_mac, ETH_ALEN);
6842
6843 val8 = dev->perm_addr[5];
6844 dev->perm_addr[5] += np->port;
6845 if (dev->perm_addr[5] < val8)
6846 dev->perm_addr[4]++;
6847
6848 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
6849}
6850
6851static int __devinit niu_pci_probe_sprom(struct niu *np)
6852{
6853 struct net_device *dev = np->dev;
6854 int len, i;
6855 u64 val, sum;
6856 u8 val8;
6857
6858 val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ);
6859 val >>= ESPC_VER_IMGSZ_IMGSZ_SHIFT;
6860 len = val / 4;
6861
6862 np->eeprom_len = len;
6863
6864 niudbg(PROBE, "SPROM: Image size %llu\n", (unsigned long long) val);
6865
6866 sum = 0;
6867 for (i = 0; i < len; i++) {
6868 val = nr64(ESPC_NCR(i));
6869 sum += (val >> 0) & 0xff;
6870 sum += (val >> 8) & 0xff;
6871 sum += (val >> 16) & 0xff;
6872 sum += (val >> 24) & 0xff;
6873 }
6874 niudbg(PROBE, "SPROM: Checksum %x\n", (int)(sum & 0xff));
6875 if ((sum & 0xff) != 0xab) {
6876 dev_err(np->device, PFX "Bad SPROM checksum "
6877 "(%x, should be 0xab)\n", (int) (sum & 0xff));
6878 return -EINVAL;
6879 }
6880
6881 val = nr64(ESPC_PHY_TYPE);
6882 switch (np->port) {
6883 case 0:
a9d41192 6884 val8 = (val & ESPC_PHY_TYPE_PORT0) >>
a3138df9
DM		 6885 ESPC_PHY_TYPE_PORT0_SHIFT;
6886 break;
6887 case 1:
a9d41192 6888 val8 = (val & ESPC_PHY_TYPE_PORT1) >>
a3138df9
DM		 6889 ESPC_PHY_TYPE_PORT1_SHIFT;
6890 break;
6891 case 2:
a9d41192 6892 val8 = (val & ESPC_PHY_TYPE_PORT2) >>
a3138df9
DM		 6893 ESPC_PHY_TYPE_PORT2_SHIFT;
6894 break;
6895 case 3:
a9d41192 6896 val8 = (val & ESPC_PHY_TYPE_PORT3) >>
a3138df9
DM		 6897 ESPC_PHY_TYPE_PORT3_SHIFT;
6898 break;
6899 default:
6900 dev_err(np->device, PFX "Bogus port number %u\n",
6901 np->port);
6902 return -EINVAL;
6903 }
a9d41192 6904 niudbg(PROBE, "SPROM: PHY type %x\n", val8);
a3138df9 6905
a9d41192 6906 switch (val8) {
a3138df9
DM		 6907 case ESPC_PHY_TYPE_1G_COPPER:
6908 /* 1G copper, MII */
6909 np->flags &= ~(NIU_FLAGS_FIBER |
6910 NIU_FLAGS_10G);
6911 np->mac_xcvr = MAC_XCVR_MII;
6912 break;
6913
6914 case ESPC_PHY_TYPE_1G_FIBER:
6915 /* 1G fiber, PCS */
6916 np->flags &= ~NIU_FLAGS_10G;
6917 np->flags |= NIU_FLAGS_FIBER;
6918 np->mac_xcvr = MAC_XCVR_PCS;
6919 break;
6920
6921 case ESPC_PHY_TYPE_10G_COPPER:
6922 /* 10G copper, XPCS */
6923 np->flags |= NIU_FLAGS_10G;
6924 np->flags &= ~NIU_FLAGS_FIBER;
6925 np->mac_xcvr = MAC_XCVR_XPCS;
6926 break;
6927
6928 case ESPC_PHY_TYPE_10G_FIBER:
6929 /* 10G fiber, XPCS */
6930 np->flags |= (NIU_FLAGS_10G |
6931 NIU_FLAGS_FIBER);
6932 np->mac_xcvr = MAC_XCVR_XPCS;
6933 break;
6934
6935 default:
a9d41192 6936 dev_err(np->device, PFX "Bogus SPROM phy type %u\n", val8);
a3138df9
DM		 6937 return -EINVAL;
6938 }
6939
6940 val = nr64(ESPC_MAC_ADDR0);
6941 niudbg(PROBE, "SPROM: MAC_ADDR0[%08llx]\n",
6942 (unsigned long long) val);
6943 dev->perm_addr[0] = (val >> 0) & 0xff;
6944 dev->perm_addr[1] = (val >> 8) & 0xff;
6945 dev->perm_addr[2] = (val >> 16) & 0xff;
6946 dev->perm_addr[3] = (val >> 24) & 0xff;
6947
6948 val = nr64(ESPC_MAC_ADDR1);
6949 niudbg(PROBE, "SPROM: MAC_ADDR1[%08llx]\n",
6950 (unsigned long long) val);
6951 dev->perm_addr[4] = (val >> 0) & 0xff;
6952 dev->perm_addr[5] = (val >> 8) & 0xff;
6953
6954 if (!is_valid_ether_addr(&dev->perm_addr[0])) {
6955 dev_err(np->device, PFX "SPROM MAC address invalid\n");
6956 dev_err(np->device, PFX "[ \n");
6957 for (i = 0; i < 6; i++)
6958 printk("%02x ", dev->perm_addr[i]);
6959 printk("]\n");
6960 return -EINVAL;
6961 }
6962
6963 val8 = dev->perm_addr[5];
6964 dev->perm_addr[5] += np->port;
6965 if (dev->perm_addr[5] < val8)
6966 dev->perm_addr[4]++;
6967
6968 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
6969
6970 val = nr64(ESPC_MOD_STR_LEN);
6971 niudbg(PROBE, "SPROM: MOD_STR_LEN[%llu]\n",
6972 (unsigned long long) val);
e6a5fdf5 6973 if (val >= 8 * 4)
a3138df9
DM		 6974 return -EINVAL;
6975
6976 for (i = 0; i < val; i += 4) {
6977 u64 tmp = nr64(ESPC_NCR(5 + (i / 4)));
6978
6979 np->vpd.model[i + 3] = (tmp >> 0) & 0xff;
6980 np->vpd.model[i + 2] = (tmp >> 8) & 0xff;
6981 np->vpd.model[i + 1] = (tmp >> 16) & 0xff;
6982 np->vpd.model[i + 0] = (tmp >> 24) & 0xff;
6983 }
6984 np->vpd.model[val] = '\0';
6985
6986 val = nr64(ESPC_BD_MOD_STR_LEN);
6987 niudbg(PROBE, "SPROM: BD_MOD_STR_LEN[%llu]\n",
6988 (unsigned long long) val);
e6a5fdf5 6989 if (val >= 4 * 4)
a3138df9
DM		 6990 return -EINVAL;
6991
6992 for (i = 0; i < val; i += 4) {
6993 u64 tmp = nr64(ESPC_NCR(14 + (i / 4)));
6994
6995 np->vpd.board_model[i + 3] = (tmp >> 0) & 0xff;
6996 np->vpd.board_model[i + 2] = (tmp >> 8) & 0xff;
6997 np->vpd.board_model[i + 1] = (tmp >> 16) & 0xff;
6998 np->vpd.board_model[i + 0] = (tmp >> 24) & 0xff;
6999 }
7000 np->vpd.board_model[val] = '\0';
7001
7002 np->vpd.mac_num =
7003 nr64(ESPC_NUM_PORTS_MACS) & ESPC_NUM_PORTS_MACS_VAL;
7004 niudbg(PROBE, "SPROM: NUM_PORTS_MACS[%d]\n",
7005 np->vpd.mac_num);
7006
7007 return 0;
7008}
7009
7010static int __devinit niu_get_and_validate_port(struct niu *np)
7011{
7012 struct niu_parent *parent = np->parent;
7013
7014 if (np->port <= 1)
7015 np->flags |= NIU_FLAGS_XMAC;
7016
7017 if (!parent->num_ports) {
7018 if (parent->plat_type == PLAT_TYPE_NIU) {
7019 parent->num_ports = 2;
7020 } else {
7f7c4072
MW		 7021 parent->num_ports = niu_pci_vpd_get_nports(np);
7022 if (!parent->num_ports) {
7023 /* Fall back to SPROM as last resort.
7024 * This will fail on most cards.
7025 */
7026 parent->num_ports = nr64(ESPC_NUM_PORTS_MACS) &
7027 ESPC_NUM_PORTS_MACS_VAL;
7028
7029 if (!parent->num_ports)
7030 return -ENODEV;
7031 }
a3138df9
DM		 7032 }
7033 }
7034
7035 niudbg(PROBE, "niu_get_and_validate_port: port[%d] num_ports[%d]\n",
7036 np->port, parent->num_ports);
7037 if (np->port >= parent->num_ports)
7038 return -ENODEV;
7039
7040 return 0;
7041}
7042
7043static int __devinit phy_record(struct niu_parent *parent,
7044 struct phy_probe_info *p,
7045 int dev_id_1, int dev_id_2, u8 phy_port,
7046 int type)
7047{
7048 u32 id = (dev_id_1 << 16) | dev_id_2;
7049 u8 idx;
7050
7051 if (dev_id_1 < 0 || dev_id_2 < 0)
7052 return 0;
7053 if (type == PHY_TYPE_PMA_PMD || type == PHY_TYPE_PCS) {
b0de8e40
ML		 7054 if (((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8704) &&
7055 ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_MRVL88X2011))
a3138df9
DM		 7056 return 0;
7057 } else {
7058 if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM5464R)
7059 return 0;
7060 }
7061
7062 pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n",
7063 parent->index, id,
7064 (type == PHY_TYPE_PMA_PMD ?
7065 "PMA/PMD" :
7066 (type == PHY_TYPE_PCS ?
7067 "PCS" : "MII")),
7068 phy_port);
7069
7070 if (p->cur[type] >= NIU_MAX_PORTS) {
7071 printk(KERN_ERR PFX "Too many PHY ports.\n");
7072 return -EINVAL;
7073 }
7074 idx = p->cur[type];
7075 p->phy_id[type][idx] = id;
7076 p->phy_port[type][idx] = phy_port;
7077 p->cur[type] = idx + 1;
7078 return 0;
7079}
7080
7081static int __devinit port_has_10g(struct phy_probe_info *p, int port)
7082{
7083 int i;
7084
7085 for (i = 0; i < p->cur[PHY_TYPE_PMA_PMD]; i++) {
7086 if (p->phy_port[PHY_TYPE_PMA_PMD][i] == port)
7087 return 1;
7088 }
7089 for (i = 0; i < p->cur[PHY_TYPE_PCS]; i++) {
7090 if (p->phy_port[PHY_TYPE_PCS][i] == port)
7091 return 1;
7092 }
7093
7094 return 0;
7095}
7096
7097static int __devinit count_10g_ports(struct phy_probe_info *p, int *lowest)
7098{
7099 int port, cnt;
7100
7101 cnt = 0;
7102 *lowest = 32;
7103 for (port = 8; port < 32; port++) {
7104 if (port_has_10g(p, port)) {
7105 if (!cnt)
7106 *lowest = port;
7107 cnt++;
7108 }
7109 }
7110
7111 return cnt;
7112}
7113
7114static int __devinit count_1g_ports(struct phy_probe_info *p, int *lowest)
7115{
7116 *lowest = 32;
7117 if (p->cur[PHY_TYPE_MII])
7118 *lowest = p->phy_port[PHY_TYPE_MII][0];
7119
7120 return p->cur[PHY_TYPE_MII];
7121}
7122
7123static void __devinit niu_n2_divide_channels(struct niu_parent *parent)
7124{
7125 int num_ports = parent->num_ports;
7126 int i;
7127
7128 for (i = 0; i < num_ports; i++) {
7129 parent->rxchan_per_port[i] = (16 / num_ports);
7130 parent->txchan_per_port[i] = (16 / num_ports);
7131
7132 pr_info(PFX "niu%d: Port %u [%u RX chans] "
7133 "[%u TX chans]\n",
7134 parent->index, i,
7135 parent->rxchan_per_port[i],
7136 parent->txchan_per_port[i]);
7137 }
7138}
7139
7140static void __devinit niu_divide_channels(struct niu_parent *parent,
7141 int num_10g, int num_1g)
7142{
7143 int num_ports = parent->num_ports;
7144 int rx_chans_per_10g, rx_chans_per_1g;
7145 int tx_chans_per_10g, tx_chans_per_1g;
7146 int i, tot_rx, tot_tx;
7147
7148 if (!num_10g || !num_1g) {
7149 rx_chans_per_10g = rx_chans_per_1g =
7150 (NIU_NUM_RXCHAN / num_ports);
7151 tx_chans_per_10g = tx_chans_per_1g =
7152 (NIU_NUM_TXCHAN / num_ports);
7153 } else {
7154 rx_chans_per_1g = NIU_NUM_RXCHAN / 8;
7155 rx_chans_per_10g = (NIU_NUM_RXCHAN -
7156 (rx_chans_per_1g * num_1g)) /
7157 num_10g;
7158
7159 tx_chans_per_1g = NIU_NUM_TXCHAN / 6;
7160 tx_chans_per_10g = (NIU_NUM_TXCHAN -
7161 (tx_chans_per_1g * num_1g)) /
7162 num_10g;
7163 }
7164
7165 tot_rx = tot_tx = 0;
7166 for (i = 0; i < num_ports; i++) {
7167 int type = phy_decode(parent->port_phy, i);
7168
7169 if (type == PORT_TYPE_10G) {
7170 parent->rxchan_per_port[i] = rx_chans_per_10g;
7171 parent->txchan_per_port[i] = tx_chans_per_10g;
7172 } else {
7173 parent->rxchan_per_port[i] = rx_chans_per_1g;
7174 parent->txchan_per_port[i] = tx_chans_per_1g;
7175 }
7176 pr_info(PFX "niu%d: Port %u [%u RX chans] "
7177 "[%u TX chans]\n",
7178 parent->index, i,
7179 parent->rxchan_per_port[i],
7180 parent->txchan_per_port[i]);
7181 tot_rx += parent->rxchan_per_port[i];
7182 tot_tx += parent->txchan_per_port[i];
7183 }
7184
7185 if (tot_rx > NIU_NUM_RXCHAN) {
7186 printk(KERN_ERR PFX "niu%d: Too many RX channels (%d), "
7187 "resetting to one per port.\n",
7188 parent->index, tot_rx);
7189 for (i = 0; i < num_ports; i++)
7190 parent->rxchan_per_port[i] = 1;
7191 }
7192 if (tot_tx > NIU_NUM_TXCHAN) {
7193 printk(KERN_ERR PFX "niu%d: Too many TX channels (%d), "
7194 "resetting to one per port.\n",
7195 parent->index, tot_tx);
7196 for (i = 0; i < num_ports; i++)
7197 parent->txchan_per_port[i] = 1;
7198 }
7199 if (tot_rx < NIU_NUM_RXCHAN || tot_tx < NIU_NUM_TXCHAN) {
7200 printk(KERN_WARNING PFX "niu%d: Driver bug, wasted channels, "
7201 "RX[%d] TX[%d]\n",
7202 parent->index, tot_rx, tot_tx);
7203 }
7204}
7205
7206static void __devinit niu_divide_rdc_groups(struct niu_parent *parent,
7207 int num_10g, int num_1g)
7208{
7209 int i, num_ports = parent->num_ports;
7210 int rdc_group, rdc_groups_per_port;
7211 int rdc_channel_base;
7212
7213 rdc_group = 0;
7214 rdc_groups_per_port = NIU_NUM_RDC_TABLES / num_ports;
7215
7216 rdc_channel_base = 0;
7217
7218 for (i = 0; i < num_ports; i++) {
7219 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[i];
7220 int grp, num_channels = parent->rxchan_per_port[i];
7221 int this_channel_offset;
7222
7223 tp->first_table_num = rdc_group;
7224 tp->num_tables = rdc_groups_per_port;
7225 this_channel_offset = 0;
7226 for (grp = 0; grp < tp->num_tables; grp++) {
7227 struct rdc_table *rt = &tp->tables[grp];
7228 int slot;
7229
7230 pr_info(PFX "niu%d: Port %d RDC tbl(%d) [ ",
7231 parent->index, i, tp->first_table_num + grp);
7232 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) {
7233 rt->rxdma_channel[slot] =
7234 rdc_channel_base + this_channel_offset;
7235
7236 printk("%d ", rt->rxdma_channel[slot]);
7237
7238 if (++this_channel_offset == num_channels)
7239 this_channel_offset = 0;
7240 }
7241 printk("]\n");
7242 }
7243
7244 parent->rdc_default[i] = rdc_channel_base;
7245
7246 rdc_channel_base += num_channels;
7247 rdc_group += rdc_groups_per_port;
7248 }
7249}
7250
7251static int __devinit fill_phy_probe_info(struct niu *np,
7252 struct niu_parent *parent,
7253 struct phy_probe_info *info)
7254{
7255 unsigned long flags;
7256 int port, err;
7257
7258 memset(info, 0, sizeof(*info));
7259
7260 /* Port 0 to 7 are reserved for onboard Serdes, probe the rest. */
7261 niu_lock_parent(np, flags);
7262 err = 0;
7263 for (port = 8; port < 32; port++) {
7264 int dev_id_1, dev_id_2;
7265
7266 dev_id_1 = mdio_read(np, port,
7267 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID1);
7268 dev_id_2 = mdio_read(np, port,
7269 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID2);
7270 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
7271 PHY_TYPE_PMA_PMD);
7272 if (err)
7273 break;
7274 dev_id_1 = mdio_read(np, port,
7275 NIU_PCS_DEV_ADDR, MII_PHYSID1);
7276 dev_id_2 = mdio_read(np, port,
7277 NIU_PCS_DEV_ADDR, MII_PHYSID2);
7278 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
7279 PHY_TYPE_PCS);
7280 if (err)
7281 break;
7282 dev_id_1 = mii_read(np, port, MII_PHYSID1);
7283 dev_id_2 = mii_read(np, port, MII_PHYSID2);
7284 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
7285 PHY_TYPE_MII);
7286 if (err)
7287 break;
7288 }
7289 niu_unlock_parent(np, flags);
7290
7291 return err;
7292}
7293
7294static int __devinit walk_phys(struct niu *np, struct niu_parent *parent)
7295{
7296 struct phy_probe_info *info = &parent->phy_probe_info;
7297 int lowest_10g, lowest_1g;
7298 int num_10g, num_1g;
7299 u32 val;
7300 int err;
7301
a3138df9 7302
5fbd7e24
MW		 7303 if (!strcmp(np->vpd.model, "SUNW,CP3220") ||
7304 !strcmp(np->vpd.model, "SUNW,CP3260")) {
7305 num_10g = 0;
7306 num_1g = 2;
7307 parent->plat_type = PLAT_TYPE_ATCA_CP3220;
7308 parent->num_ports = 4;
7309 val = (phy_encode(PORT_TYPE_1G, 0) |
7310 phy_encode(PORT_TYPE_1G, 1) |
a3138df9
DM		 7311 phy_encode(PORT_TYPE_1G, 2) |
7312 phy_encode(PORT_TYPE_1G, 3));
5fbd7e24
MW		 7313 } else {
7314 err = fill_phy_probe_info(np, parent, info);
7315 if (err)
7316 return err;
a3138df9 7317
5fbd7e24
MW		 7318 num_10g = count_10g_ports(info, &lowest_10g);
7319 num_1g = count_1g_ports(info, &lowest_1g);
a3138df9 7320
5fbd7e24
MW		 7321 switch ((num_10g << 4) | num_1g) {
7322 case 0x24:
7323 if (lowest_1g == 10)
7324 parent->plat_type = PLAT_TYPE_VF_P0;
7325 else if (lowest_1g == 26)
7326 parent->plat_type = PLAT_TYPE_VF_P1;
7327 else
7328 goto unknown_vg_1g_port;
a3138df9 7329
5fbd7e24
MW		 7330 /* fallthru */
7331 case 0x22:
a3138df9 7332 val = (phy_encode(PORT_TYPE_10G, 0) |
a3138df9
DM		 7333 phy_encode(PORT_TYPE_10G, 1) |
7334 phy_encode(PORT_TYPE_1G, 2) |
7335 phy_encode(PORT_TYPE_1G, 3));
5fbd7e24 7336 break;
a3138df9 7337
5fbd7e24
MW		 7338 case 0x20:
7339 val = (phy_encode(PORT_TYPE_10G, 0) |
7340 phy_encode(PORT_TYPE_10G, 1));
7341 break;
a3138df9 7342
5fbd7e24
MW		 7343 case 0x10:
7344 val = phy_encode(PORT_TYPE_10G, np->port);
7345 break;
a3138df9 7346
5fbd7e24
MW		 7347 case 0x14:
7348 if (lowest_1g == 10)
7349 parent->plat_type = PLAT_TYPE_VF_P0;
7350 else if (lowest_1g == 26)
7351 parent->plat_type = PLAT_TYPE_VF_P1;
7352 else
7353 goto unknown_vg_1g_port;
7354
7355 /* fallthru */
7356 case 0x13:
7357 if ((lowest_10g & 0x7) == 0)
7358 val = (phy_encode(PORT_TYPE_10G, 0) |
7359 phy_encode(PORT_TYPE_1G, 1) |
7360 phy_encode(PORT_TYPE_1G, 2) |
7361 phy_encode(PORT_TYPE_1G, 3));
7362 else
7363 val = (phy_encode(PORT_TYPE_1G, 0) |
7364 phy_encode(PORT_TYPE_10G, 1) |
7365 phy_encode(PORT_TYPE_1G, 2) |
7366 phy_encode(PORT_TYPE_1G, 3));
7367 break;
7368
7369 case 0x04:
7370 if (lowest_1g == 10)
7371 parent->plat_type = PLAT_TYPE_VF_P0;
7372 else if (lowest_1g == 26)
7373 parent->plat_type = PLAT_TYPE_VF_P1;
7374 else
7375 goto unknown_vg_1g_port;
7376
7377 val = (phy_encode(PORT_TYPE_1G, 0) |
7378 phy_encode(PORT_TYPE_1G, 1) |
7379 phy_encode(PORT_TYPE_1G, 2) |
7380 phy_encode(PORT_TYPE_1G, 3));
7381 break;
7382
7383 default:
7384 printk(KERN_ERR PFX "Unsupported port config "
7385 "10G[%d] 1G[%d]\n",
7386 num_10g, num_1g);
7387 return -EINVAL;
7388 }
a3138df9
DM		 7389 }
7390
7391 parent->port_phy = val;
7392
7393 if (parent->plat_type == PLAT_TYPE_NIU)
7394 niu_n2_divide_channels(parent);
7395 else
7396 niu_divide_channels(parent, num_10g, num_1g);
7397
7398 niu_divide_rdc_groups(parent, num_10g, num_1g);
7399
7400 return 0;
7401
7402unknown_vg_1g_port:
7403 printk(KERN_ERR PFX "Cannot identify platform type, 1gport=%d\n",
7404 lowest_1g);
7405 return -EINVAL;
7406}
7407
7408static int __devinit niu_probe_ports(struct niu *np)
7409{
7410 struct niu_parent *parent = np->parent;
7411 int err, i;
7412
7413 niudbg(PROBE, "niu_probe_ports(): port_phy[%08x]\n",
7414 parent->port_phy);
7415
7416 if (parent->port_phy == PORT_PHY_UNKNOWN) {
7417 err = walk_phys(np, parent);
7418 if (err)
7419 return err;
7420
7421 niu_set_ldg_timer_res(np, 2);
7422 for (i = 0; i <= LDN_MAX; i++)
7423 niu_ldn_irq_enable(np, i, 0);
7424 }
7425
7426 if (parent->port_phy == PORT_PHY_INVALID)
7427 return -EINVAL;
7428
7429 return 0;
7430}
7431
7432static int __devinit niu_classifier_swstate_init(struct niu *np)
7433{
7434 struct niu_classifier *cp = &np->clas;
7435
7436 niudbg(PROBE, "niu_classifier_swstate_init: num_tcam(%d)\n",
7437 np->parent->tcam_num_entries);
7438
7439 cp->tcam_index = (u16) np->port;
7440 cp->h1_init = 0xffffffff;
7441 cp->h2_init = 0xffff;
7442
7443 return fflp_early_init(np);
7444}
7445
7446static void __devinit niu_link_config_init(struct niu *np)
7447{
7448 struct niu_link_config *lp = &np->link_config;
7449
7450 lp->advertising = (ADVERTISED_10baseT_Half |
7451 ADVERTISED_10baseT_Full |
7452 ADVERTISED_100baseT_Half |
7453 ADVERTISED_100baseT_Full |
7454 ADVERTISED_1000baseT_Half |
7455 ADVERTISED_1000baseT_Full |
7456 ADVERTISED_10000baseT_Full |
7457 ADVERTISED_Autoneg);
7458 lp->speed = lp->active_speed = SPEED_INVALID;
7459 lp->duplex = lp->active_duplex = DUPLEX_INVALID;
7460#if 0
7461 lp->loopback_mode = LOOPBACK_MAC;
7462 lp->active_speed = SPEED_10000;
7463 lp->active_duplex = DUPLEX_FULL;
7464#else
7465 lp->loopback_mode = LOOPBACK_DISABLED;
7466#endif
7467}
7468
7469static int __devinit niu_init_mac_ipp_pcs_base(struct niu *np)
7470{
7471 switch (np->port) {
7472 case 0:
7473 np->mac_regs = np->regs + XMAC_PORT0_OFF;
7474 np->ipp_off = 0x00000;
7475 np->pcs_off = 0x04000;
7476 np->xpcs_off = 0x02000;
7477 break;
7478
7479 case 1:
7480 np->mac_regs = np->regs + XMAC_PORT1_OFF;
7481 np->ipp_off = 0x08000;
7482 np->pcs_off = 0x0a000;
7483 np->xpcs_off = 0x08000;
7484 break;
7485
7486 case 2:
7487 np->mac_regs = np->regs + BMAC_PORT2_OFF;
7488 np->ipp_off = 0x04000;
7489 np->pcs_off = 0x0e000;
7490 np->xpcs_off = ~0UL;
7491 break;
7492
7493 case 3:
7494 np->mac_regs = np->regs + BMAC_PORT3_OFF;
7495 np->ipp_off = 0x0c000;
7496 np->pcs_off = 0x12000;
7497 np->xpcs_off = ~0UL;
7498 break;
7499
7500 default:
7501 dev_err(np->device, PFX "Port %u is invalid, cannot "
7502 "compute MAC block offset.\n", np->port);
7503 return -EINVAL;
7504 }
7505
7506 return 0;
7507}
7508
7509static void __devinit niu_try_msix(struct niu *np, u8 *ldg_num_map)
7510{
7511 struct msix_entry msi_vec[NIU_NUM_LDG];
7512 struct niu_parent *parent = np->parent;
7513 struct pci_dev *pdev = np->pdev;
7514 int i, num_irqs, err;
7515 u8 first_ldg;
7516
7517 first_ldg = (NIU_NUM_LDG / parent->num_ports) * np->port;
7518 for (i = 0; i < (NIU_NUM_LDG / parent->num_ports); i++)
7519 ldg_num_map[i] = first_ldg + i;
7520
7521 num_irqs = (parent->rxchan_per_port[np->port] +
7522 parent->txchan_per_port[np->port] +
7523 (np->port == 0 ? 3 : 1));
7524 BUG_ON(num_irqs > (NIU_NUM_LDG / parent->num_ports));
7525
7526retry:
7527 for (i = 0; i < num_irqs; i++) {
7528 msi_vec[i].vector = 0;
7529 msi_vec[i].entry = i;
7530 }
7531
7532 err = pci_enable_msix(pdev, msi_vec, num_irqs);
7533 if (err < 0) {
7534 np->flags &= ~NIU_FLAGS_MSIX;
7535 return;
7536 }
7537 if (err > 0) {
7538 num_irqs = err;
7539 goto retry;
7540 }
7541
7542 np->flags |= NIU_FLAGS_MSIX;
7543 for (i = 0; i < num_irqs; i++)
7544 np->ldg[i].irq = msi_vec[i].vector;
7545 np->num_ldg = num_irqs;
7546}
7547
7548static int __devinit niu_n2_irq_init(struct niu *np, u8 *ldg_num_map)
7549{
7550#ifdef CONFIG_SPARC64
7551 struct of_device *op = np->op;
7552 const u32 *int_prop;
7553 int i;
7554
7555 int_prop = of_get_property(op->node, "interrupts", NULL);
7556 if (!int_prop)
7557 return -ENODEV;
7558
7559 for (i = 0; i < op->num_irqs; i++) {
7560 ldg_num_map[i] = int_prop[i];
7561 np->ldg[i].irq = op->irqs[i];
7562 }
7563
7564 np->num_ldg = op->num_irqs;
7565
7566 return 0;
7567#else
7568 return -EINVAL;
7569#endif
7570}
7571
7572static int __devinit niu_ldg_init(struct niu *np)
7573{
7574 struct niu_parent *parent = np->parent;
7575 u8 ldg_num_map[NIU_NUM_LDG];
7576 int first_chan, num_chan;
7577 int i, err, ldg_rotor;
7578 u8 port;
7579
7580 np->num_ldg = 1;
7581 np->ldg[0].irq = np->dev->irq;
7582 if (parent->plat_type == PLAT_TYPE_NIU) {
7583 err = niu_n2_irq_init(np, ldg_num_map);
7584 if (err)
7585 return err;
7586 } else
7587 niu_try_msix(np, ldg_num_map);
7588
7589 port = np->port;
7590 for (i = 0; i < np->num_ldg; i++) {
7591 struct niu_ldg *lp = &np->ldg[i];
7592
7593 netif_napi_add(np->dev, &lp->napi, niu_poll, 64);
7594
7595 lp->np = np;
7596 lp->ldg_num = ldg_num_map[i];
7597 lp->timer = 2; /* XXX */
7598
7599 /* On N2 NIU the firmware has setup the SID mappings so they go
7600 * to the correct values that will route the LDG to the proper
7601 * interrupt in the NCU interrupt table.
7602 */
7603 if (np->parent->plat_type != PLAT_TYPE_NIU) {
7604 err = niu_set_ldg_sid(np, lp->ldg_num, port, i);
7605 if (err)
7606 return err;
7607 }
7608 }
7609
7610 /* We adopt the LDG assignment ordering used by the N2 NIU
7611 * 'interrupt' properties because that simplifies a lot of
7612 * things. This ordering is:
7613 *
7614 * MAC
7615 * MIF (if port zero)
7616 * SYSERR (if port zero)
7617 * RX channels
7618 * TX channels
7619 */
7620
7621 ldg_rotor = 0;
7622
7623 err = niu_ldg_assign_ldn(np, parent, ldg_num_map[ldg_rotor],
7624 LDN_MAC(port));
7625 if (err)
7626 return err;
7627
7628 ldg_rotor++;
7629 if (ldg_rotor == np->num_ldg)
7630 ldg_rotor = 0;
7631
7632 if (port == 0) {
7633 err = niu_ldg_assign_ldn(np, parent,
7634 ldg_num_map[ldg_rotor],
7635 LDN_MIF);
7636 if (err)
7637 return err;
7638
7639 ldg_rotor++;
7640 if (ldg_rotor == np->num_ldg)
7641 ldg_rotor = 0;
7642
7643 err = niu_ldg_assign_ldn(np, parent,
7644 ldg_num_map[ldg_rotor],
7645 LDN_DEVICE_ERROR);
7646 if (err)
7647 return err;
7648
7649 ldg_rotor++;
7650 if (ldg_rotor == np->num_ldg)
7651 ldg_rotor = 0;
7652
7653 }
7654
7655 first_chan = 0;
7656 for (i = 0; i < port; i++)
7657 first_chan += parent->rxchan_per_port[port];
7658 num_chan = parent->rxchan_per_port[port];
7659
7660 for (i = first_chan; i < (first_chan + num_chan); i++) {
7661 err = niu_ldg_assign_ldn(np, parent,
7662 ldg_num_map[ldg_rotor],
7663 LDN_RXDMA(i));
7664 if (err)
7665 return err;
7666 ldg_rotor++;
7667 if (ldg_rotor == np->num_ldg)
7668 ldg_rotor = 0;
7669 }
7670
7671 first_chan = 0;
7672 for (i = 0; i < port; i++)
7673 first_chan += parent->txchan_per_port[port];
7674 num_chan = parent->txchan_per_port[port];
7675 for (i = first_chan; i < (first_chan + num_chan); i++) {
7676 err = niu_ldg_assign_ldn(np, parent,
7677 ldg_num_map[ldg_rotor],
7678 LDN_TXDMA(i));
7679 if (err)
7680 return err;
7681 ldg_rotor++;
7682 if (ldg_rotor == np->num_ldg)
7683 ldg_rotor = 0;
7684 }
7685
7686 return 0;
7687}
7688
7689static void __devexit niu_ldg_free(struct niu *np)
7690{
7691 if (np->flags & NIU_FLAGS_MSIX)
7692 pci_disable_msix(np->pdev);
7693}
7694
7695static int __devinit niu_get_of_props(struct niu *np)
7696{
7697#ifdef CONFIG_SPARC64
7698 struct net_device *dev = np->dev;
7699 struct device_node *dp;
7700 const char *phy_type;
7701 const u8 *mac_addr;
7702 int prop_len;
7703
7704 if (np->parent->plat_type == PLAT_TYPE_NIU)
7705 dp = np->op->node;
7706 else
7707 dp = pci_device_to_OF_node(np->pdev);
7708
7709 phy_type = of_get_property(dp, "phy-type", &prop_len);
7710 if (!phy_type) {
7711 dev_err(np->device, PFX "%s: OF node lacks "
7712 "phy-type property\n",
7713 dp->full_name);
7714 return -EINVAL;
7715 }
7716
7717 if (!strcmp(phy_type, "none"))
7718 return -ENODEV;
7719
7720 strcpy(np->vpd.phy_type, phy_type);
7721
7722 if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
7723 dev_err(np->device, PFX "%s: Illegal phy string [%s].\n",
7724 dp->full_name, np->vpd.phy_type);
7725 return -EINVAL;
7726 }
7727
7728 mac_addr = of_get_property(dp, "local-mac-address", &prop_len);
7729 if (!mac_addr) {
7730 dev_err(np->device, PFX "%s: OF node lacks "
7731 "local-mac-address property\n",
7732 dp->full_name);
7733 return -EINVAL;
7734 }
7735 if (prop_len != dev->addr_len) {
7736 dev_err(np->device, PFX "%s: OF MAC address prop len (%d) "
7737 "is wrong.\n",
7738 dp->full_name, prop_len);
7739 }
7740 memcpy(dev->perm_addr, mac_addr, dev->addr_len);
7741 if (!is_valid_ether_addr(&dev->perm_addr[0])) {
7742 int i;
7743
7744 dev_err(np->device, PFX "%s: OF MAC address is invalid\n",
7745 dp->full_name);
7746 dev_err(np->device, PFX "%s: [ \n",
7747 dp->full_name);
7748 for (i = 0; i < 6; i++)
7749 printk("%02x ", dev->perm_addr[i]);
7750 printk("]\n");
7751 return -EINVAL;
7752 }
7753
7754 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
7755
7756 return 0;
7757#else
7758 return -EINVAL;
7759#endif
7760}
7761
7762static int __devinit niu_get_invariants(struct niu *np)
7763{
7764 int err, have_props;
7765 u32 offset;
7766
7767 err = niu_get_of_props(np);
7768 if (err == -ENODEV)
7769 return err;
7770
7771 have_props = !err;
7772
a3138df9
DM		 7773 err = niu_init_mac_ipp_pcs_base(np);
7774 if (err)
7775 return err;
7776
7f7c4072
MW		 7777 if (have_props) {
7778 err = niu_get_and_validate_port(np);
7779 if (err)
7780 return err;
7781
7782 } else {
a3138df9
DM		 7783 if (np->parent->plat_type == PLAT_TYPE_NIU)
7784 return -EINVAL;
7785
7786 nw64(ESPC_PIO_EN, ESPC_PIO_EN_ENABLE);
7787 offset = niu_pci_vpd_offset(np);
7788 niudbg(PROBE, "niu_get_invariants: VPD offset [%08x]\n",
7789 offset);
7790 if (offset)
7791 niu_pci_vpd_fetch(np, offset);
7792 nw64(ESPC_PIO_EN, 0);
7793
7f7c4072 7794 if (np->flags & NIU_FLAGS_VPD_VALID) {
a3138df9 7795 niu_pci_vpd_validate(np);
7f7c4072
MW		 7796 err = niu_get_and_validate_port(np);
7797 if (err)
7798 return err;
7799 }
a3138df9
DM		 7800
7801 if (!(np->flags & NIU_FLAGS_VPD_VALID)) {
7f7c4072
MW		 7802 err = niu_get_and_validate_port(np);
7803 if (err)
7804 return err;
a3138df9
DM		 7805 err = niu_pci_probe_sprom(np);
7806 if (err)
7807 return err;
7808 }
7809 }
7810
7811 err = niu_probe_ports(np);
7812 if (err)
7813 return err;
7814
7815 niu_ldg_init(np);
7816
7817 niu_classifier_swstate_init(np);
7818 niu_link_config_init(np);
7819
7820 err = niu_determine_phy_disposition(np);
7821 if (!err)
7822 err = niu_init_link(np);
7823
7824 return err;
7825}
7826
7827static LIST_HEAD(niu_parent_list);
7828static DEFINE_MUTEX(niu_parent_lock);
7829static int niu_parent_index;
7830
7831static ssize_t show_port_phy(struct device *dev,
7832 struct device_attribute *attr, char *buf)
7833{
7834 struct platform_device *plat_dev = to_platform_device(dev);
7835 struct niu_parent *p = plat_dev->dev.platform_data;
7836 u32 port_phy = p->port_phy;
7837 char *orig_buf = buf;
7838 int i;
7839
7840 if (port_phy == PORT_PHY_UNKNOWN ||
7841 port_phy == PORT_PHY_INVALID)
7842 return 0;
7843
7844 for (i = 0; i < p->num_ports; i++) {
7845 const char *type_str;
7846 int type;
7847
7848 type = phy_decode(port_phy, i);
7849 if (type == PORT_TYPE_10G)
7850 type_str = "10G";
7851 else
7852 type_str = "1G";
7853 buf += sprintf(buf,
7854 (i == 0) ? "%s" : " %s",
7855 type_str);
7856 }
7857 buf += sprintf(buf, "\n");
7858 return buf - orig_buf;
7859}
7860
7861static ssize_t show_plat_type(struct device *dev,
7862 struct device_attribute *attr, char *buf)
7863{
7864 struct platform_device *plat_dev = to_platform_device(dev);
7865 struct niu_parent *p = plat_dev->dev.platform_data;
7866 const char *type_str;
7867
7868 switch (p->plat_type) {
7869 case PLAT_TYPE_ATLAS:
7870 type_str = "atlas";
7871 break;
7872 case PLAT_TYPE_NIU:
7873 type_str = "niu";
7874 break;
7875 case PLAT_TYPE_VF_P0:
7876 type_str = "vf_p0";
7877 break;
7878 case PLAT_TYPE_VF_P1:
7879 type_str = "vf_p1";
7880 break;
7881 default:
7882 type_str = "unknown";
7883 break;
7884 }
7885
7886 return sprintf(buf, "%s\n", type_str);
7887}
7888
7889static ssize_t __show_chan_per_port(struct device *dev,
7890 struct device_attribute *attr, char *buf,
7891 int rx)
7892{
7893 struct platform_device *plat_dev = to_platform_device(dev);
7894 struct niu_parent *p = plat_dev->dev.platform_data;
7895 char *orig_buf = buf;
7896 u8 *arr;
7897 int i;
7898
7899 arr = (rx ? p->rxchan_per_port : p->txchan_per_port);
7900
7901 for (i = 0; i < p->num_ports; i++) {
7902 buf += sprintf(buf,
7903 (i == 0) ? "%d" : " %d",
7904 arr[i]);
7905 }
7906 buf += sprintf(buf, "\n");
7907
7908 return buf - orig_buf;
7909}
7910
7911static ssize_t show_rxchan_per_port(struct device *dev,
7912 struct device_attribute *attr, char *buf)
7913{
7914 return __show_chan_per_port(dev, attr, buf, 1);
7915}
7916
7917static ssize_t show_txchan_per_port(struct device *dev,
7918 struct device_attribute *attr, char *buf)
7919{
7920 return __show_chan_per_port(dev, attr, buf, 1);
7921}
7922
7923static ssize_t show_num_ports(struct device *dev,
7924 struct device_attribute *attr, char *buf)
7925{
7926 struct platform_device *plat_dev = to_platform_device(dev);
7927 struct niu_parent *p = plat_dev->dev.platform_data;
7928
7929 return sprintf(buf, "%d\n", p->num_ports);
7930}
7931
7932static struct device_attribute niu_parent_attributes[] = {
7933 __ATTR(port_phy, S_IRUGO, show_port_phy, NULL),
7934 __ATTR(plat_type, S_IRUGO, show_plat_type, NULL),
7935 __ATTR(rxchan_per_port, S_IRUGO, show_rxchan_per_port, NULL),
7936 __ATTR(txchan_per_port, S_IRUGO, show_txchan_per_port, NULL),
7937 __ATTR(num_ports, S_IRUGO, show_num_ports, NULL),
7938 {}
7939};
7940
7941static struct niu_parent * __devinit niu_new_parent(struct niu *np,
7942 union niu_parent_id *id,
7943 u8 ptype)
7944{
7945 struct platform_device *plat_dev;
7946 struct niu_parent *p;
7947 int i;
7948
7949 niudbg(PROBE, "niu_new_parent: Creating new parent.\n");
7950
7951 plat_dev = platform_device_register_simple("niu", niu_parent_index,
7952 NULL, 0);
7953 if (!plat_dev)
7954 return NULL;
7955
7956 for (i = 0; attr_name(niu_parent_attributes[i]); i++) {
7957 int err = device_create_file(&plat_dev->dev,
7958 &niu_parent_attributes[i]);
7959 if (err)
7960 goto fail_unregister;
7961 }
7962
7963 p = kzalloc(sizeof(*p), GFP_KERNEL);
7964 if (!p)
7965 goto fail_unregister;
7966
7967 p->index = niu_parent_index++;
7968
7969 plat_dev->dev.platform_data = p;
7970 p->plat_dev = plat_dev;
7971
7972 memcpy(&p->id, id, sizeof(*id));
7973 p->plat_type = ptype;
7974 INIT_LIST_HEAD(&p->list);
7975 atomic_set(&p->refcnt, 0);
7976 list_add(&p->list, &niu_parent_list);
7977 spin_lock_init(&p->lock);
7978
7979 p->rxdma_clock_divider = 7500;
7980
7981 p->tcam_num_entries = NIU_PCI_TCAM_ENTRIES;
7982 if (p->plat_type == PLAT_TYPE_NIU)
7983 p->tcam_num_entries = NIU_NONPCI_TCAM_ENTRIES;
7984
7985 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
7986 int index = i - CLASS_CODE_USER_PROG1;
7987
7988 p->tcam_key[index] = TCAM_KEY_TSEL;
7989 p->flow_key[index] = (FLOW_KEY_IPSA |
7990 FLOW_KEY_IPDA |
7991 FLOW_KEY_PROTO |
7992 (FLOW_KEY_L4_BYTE12 <<
7993 FLOW_KEY_L4_0_SHIFT) |
7994 (FLOW_KEY_L4_BYTE12 <<
7995 FLOW_KEY_L4_1_SHIFT));
7996 }
7997
7998 for (i = 0; i < LDN_MAX + 1; i++)
7999 p->ldg_map[i] = LDG_INVALID;
8000
8001 return p;
8002
8003fail_unregister:
8004 platform_device_unregister(plat_dev);
8005 return NULL;
8006}
8007
8008static struct niu_parent * __devinit niu_get_parent(struct niu *np,
8009 union niu_parent_id *id,
8010 u8 ptype)
8011{
8012 struct niu_parent *p, *tmp;
8013 int port = np->port;
8014
8015 niudbg(PROBE, "niu_get_parent: platform_type[%u] port[%u]\n",
8016 ptype, port);
8017
8018 mutex_lock(&niu_parent_lock);
8019 p = NULL;
8020 list_for_each_entry(tmp, &niu_parent_list, list) {
8021 if (!memcmp(id, &tmp->id, sizeof(*id))) {
8022 p = tmp;
8023 break;
8024 }
8025 }
8026 if (!p)
8027 p = niu_new_parent(np, id, ptype);
8028
8029 if (p) {
8030 char port_name[6];
8031 int err;
8032
8033 sprintf(port_name, "port%d", port);
8034 err = sysfs_create_link(&p->plat_dev->dev.kobj,
8035 &np->device->kobj,
8036 port_name);
8037 if (!err) {
8038 p->ports[port] = np;
8039 atomic_inc(&p->refcnt);
8040 }
8041 }
8042 mutex_unlock(&niu_parent_lock);
8043
8044 return p;
8045}
8046
8047static void niu_put_parent(struct niu *np)
8048{
8049 struct niu_parent *p = np->parent;
8050 u8 port = np->port;
8051 char port_name[6];
8052
8053 BUG_ON(!p || p->ports[port] != np);
8054
8055 niudbg(PROBE, "niu_put_parent: port[%u]\n", port);
8056
8057 sprintf(port_name, "port%d", port);
8058
8059 mutex_lock(&niu_parent_lock);
8060
8061 sysfs_remove_link(&p->plat_dev->dev.kobj, port_name);
8062
8063 p->ports[port] = NULL;
8064 np->parent = NULL;
8065
8066 if (atomic_dec_and_test(&p->refcnt)) {
8067 list_del(&p->list);
8068 platform_device_unregister(p->plat_dev);
8069 }
8070
8071 mutex_unlock(&niu_parent_lock);
8072}
8073
8074static void *niu_pci_alloc_coherent(struct device *dev, size_t size,
8075 u64 *handle, gfp_t flag)
8076{
8077 dma_addr_t dh;
8078 void *ret;
8079
8080 ret = dma_alloc_coherent(dev, size, &dh, flag);
8081 if (ret)
8082 *handle = dh;
8083 return ret;
8084}
8085
8086static void niu_pci_free_coherent(struct device *dev, size_t size,
8087 void *cpu_addr, u64 handle)
8088{
8089 dma_free_coherent(dev, size, cpu_addr, handle);
8090}
8091
8092static u64 niu_pci_map_page(struct device *dev, struct page *page,
8093 unsigned long offset, size_t size,
8094 enum dma_data_direction direction)
8095{
8096 return dma_map_page(dev, page, offset, size, direction);
8097}
8098
8099static void niu_pci_unmap_page(struct device *dev, u64 dma_address,
8100 size_t size, enum dma_data_direction direction)
8101{
8102 return dma_unmap_page(dev, dma_address, size, direction);
8103}
8104
8105static u64 niu_pci_map_single(struct device *dev, void *cpu_addr,
8106 size_t size,
8107 enum dma_data_direction direction)
8108{
8109 return dma_map_single(dev, cpu_addr, size, direction);
8110}
8111
8112static void niu_pci_unmap_single(struct device *dev, u64 dma_address,
8113 size_t size,
8114 enum dma_data_direction direction)
8115{
8116 dma_unmap_single(dev, dma_address, size, direction);
8117}
8118
8119static const struct niu_ops niu_pci_ops = {
8120 .alloc_coherent = niu_pci_alloc_coherent,
8121 .free_coherent = niu_pci_free_coherent,
8122 .map_page = niu_pci_map_page,
8123 .unmap_page = niu_pci_unmap_page,
8124 .map_single = niu_pci_map_single,
8125 .unmap_single = niu_pci_unmap_single,
8126};
8127
8128static void __devinit niu_driver_version(void)
8129{
8130 static int niu_version_printed;
8131
8132 if (niu_version_printed++ == 0)
8133 pr_info("%s", version);
8134}
8135
8136static struct net_device * __devinit niu_alloc_and_init(
8137 struct device *gen_dev, struct pci_dev *pdev,
8138 struct of_device *op, const struct niu_ops *ops,
8139 u8 port)
8140{
8141 struct net_device *dev = alloc_etherdev(sizeof(struct niu));
8142 struct niu *np;
8143
8144 if (!dev) {
8145 dev_err(gen_dev, PFX "Etherdev alloc failed, aborting.\n");
8146 return NULL;
8147 }
8148
8149 SET_NETDEV_DEV(dev, gen_dev);
8150
8151 np = netdev_priv(dev);
8152 np->dev = dev;
8153 np->pdev = pdev;
8154 np->op = op;
8155 np->device = gen_dev;
8156 np->ops = ops;
8157
8158 np->msg_enable = niu_debug;
8159
8160 spin_lock_init(&np->lock);
8161 INIT_WORK(&np->reset_task, niu_reset_task);
8162
8163 np->port = port;
8164
8165 return dev;
8166}
8167
8168static void __devinit niu_assign_netdev_ops(struct net_device *dev)
8169{
8170 dev->open = niu_open;
8171 dev->stop = niu_close;
8172 dev->get_stats = niu_get_stats;
8173 dev->set_multicast_list = niu_set_rx_mode;
8174 dev->set_mac_address = niu_set_mac_addr;
8175 dev->do_ioctl = niu_ioctl;
8176 dev->tx_timeout = niu_tx_timeout;
8177 dev->hard_start_xmit = niu_start_xmit;
8178 dev->ethtool_ops = &niu_ethtool_ops;
8179 dev->watchdog_timeo = NIU_TX_TIMEOUT;
8180 dev->change_mtu = niu_change_mtu;
8181}
8182
8183static void __devinit niu_device_announce(struct niu *np)
8184{
8185 struct net_device *dev = np->dev;
2caf62f6 8186 DECLARE_MAC_BUF(mac);
a3138df9 8187
2caf62f6
JP		 8188 pr_info("%s: NIU Ethernet %s\n",
8189 dev->name, print_mac(mac, dev->dev_addr));
a3138df9 8190
5fbd7e24
MW		 8191 if (np->parent->plat_type == PLAT_TYPE_ATCA_CP3220) {
8192 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
8193 dev->name,
8194 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
8195 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
8196 (np->flags & NIU_FLAGS_FIBER ? "RGMII FIBER" : "SERDES"),
8197 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
8198 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
8199 np->vpd.phy_type);
8200 } else {
8201 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
8202 dev->name,
8203 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
8204 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
8205 (np->flags & NIU_FLAGS_FIBER ? "FIBER" : "COPPER"),
8206 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
8207 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
8208 np->vpd.phy_type);
8209 }
a3138df9
DM		 8210}
8211
8212static int __devinit niu_pci_init_one(struct pci_dev *pdev,
8213 const struct pci_device_id *ent)
8214{
8215 unsigned long niureg_base, niureg_len;
8216 union niu_parent_id parent_id;
8217 struct net_device *dev;
8218 struct niu *np;
8219 int err, pos;
8220 u64 dma_mask;
8221 u16 val16;
8222
8223 niu_driver_version();
8224
8225 err = pci_enable_device(pdev);
8226 if (err) {
8227 dev_err(&pdev->dev, PFX "Cannot enable PCI device, "
8228 "aborting.\n");
8229 return err;
8230 }
8231
8232 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
8233 !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
8234 dev_err(&pdev->dev, PFX "Cannot find proper PCI device "
8235 "base addresses, aborting.\n");
8236 err = -ENODEV;
8237 goto err_out_disable_pdev;
8238 }
8239
8240 err = pci_request_regions(pdev, DRV_MODULE_NAME);
8241 if (err) {
8242 dev_err(&pdev->dev, PFX "Cannot obtain PCI resources, "
8243 "aborting.\n");
8244 goto err_out_disable_pdev;
8245 }
8246
8247 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
8248 if (pos <= 0) {
8249 dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, "
8250 "aborting.\n");
8251 goto err_out_free_res;
8252 }
8253
8254 dev = niu_alloc_and_init(&pdev->dev, pdev, NULL,
8255 &niu_pci_ops, PCI_FUNC(pdev->devfn));
8256 if (!dev) {
8257 err = -ENOMEM;
8258 goto err_out_free_res;
8259 }
8260 np = netdev_priv(dev);
8261
8262 memset(&parent_id, 0, sizeof(parent_id));
8263 parent_id.pci.domain = pci_domain_nr(pdev->bus);
8264 parent_id.pci.bus = pdev->bus->number;
8265 parent_id.pci.device = PCI_SLOT(pdev->devfn);
8266
8267 np->parent = niu_get_parent(np, &parent_id,
8268 PLAT_TYPE_ATLAS);
8269 if (!np->parent) {
8270 err = -ENOMEM;
8271 goto err_out_free_dev;
8272 }
8273
8274 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
8275 val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
8276 val16 |= (PCI_EXP_DEVCTL_CERE |
8277 PCI_EXP_DEVCTL_NFERE |
8278 PCI_EXP_DEVCTL_FERE |
8279 PCI_EXP_DEVCTL_URRE |
8280 PCI_EXP_DEVCTL_RELAX_EN);
8281 pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
8282
8283 dma_mask = DMA_44BIT_MASK;
8284 err = pci_set_dma_mask(pdev, dma_mask);
8285 if (!err) {
8286 dev->features |= NETIF_F_HIGHDMA;
8287 err = pci_set_consistent_dma_mask(pdev, dma_mask);
8288 if (err) {
8289 dev_err(&pdev->dev, PFX "Unable to obtain 44 bit "
8290 "DMA for consistent allocations, "
8291 "aborting.\n");
8292 goto err_out_release_parent;
8293 }
8294 }
8295 if (err || dma_mask == DMA_32BIT_MASK) {
8296 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
8297 if (err) {
8298 dev_err(&pdev->dev, PFX "No usable DMA configuration, "
8299 "aborting.\n");
8300 goto err_out_release_parent;
8301 }
8302 }
8303
8304 dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM);
8305
8306 niureg_base = pci_resource_start(pdev, 0);
8307 niureg_len = pci_resource_len(pdev, 0);
8308
8309 np->regs = ioremap_nocache(niureg_base, niureg_len);
8310 if (!np->regs) {
8311 dev_err(&pdev->dev, PFX "Cannot map device registers, "
8312 "aborting.\n");
8313 err = -ENOMEM;
8314 goto err_out_release_parent;
8315 }
8316
8317 pci_set_master(pdev);
8318 pci_save_state(pdev);
8319
8320 dev->irq = pdev->irq;
8321
8322 niu_assign_netdev_ops(dev);
8323
8324 err = niu_get_invariants(np);
8325 if (err) {
8326 if (err != -ENODEV)
8327 dev_err(&pdev->dev, PFX "Problem fetching invariants "
8328 "of chip, aborting.\n");
8329 goto err_out_iounmap;
8330 }
8331
8332 err = register_netdev(dev);
8333 if (err) {
8334 dev_err(&pdev->dev, PFX "Cannot register net device, "
8335 "aborting.\n");
8336 goto err_out_iounmap;
8337 }
8338
8339 pci_set_drvdata(pdev, dev);
8340
8341 niu_device_announce(np);
8342
8343 return 0;
8344
8345err_out_iounmap:
8346 if (np->regs) {
8347 iounmap(np->regs);
8348 np->regs = NULL;
8349 }
8350
8351err_out_release_parent:
8352 niu_put_parent(np);
8353
8354err_out_free_dev:
8355 free_netdev(dev);
8356
8357err_out_free_res:
8358 pci_release_regions(pdev);
8359
8360err_out_disable_pdev:
8361 pci_disable_device(pdev);
8362 pci_set_drvdata(pdev, NULL);
8363
8364 return err;
8365}
8366
8367static void __devexit niu_pci_remove_one(struct pci_dev *pdev)
8368{
8369 struct net_device *dev = pci_get_drvdata(pdev);
8370
8371 if (dev) {
8372 struct niu *np = netdev_priv(dev);
8373
8374 unregister_netdev(dev);
8375 if (np->regs) {
8376 iounmap(np->regs);
8377 np->regs = NULL;
8378 }
8379
8380 niu_ldg_free(np);
8381
8382 niu_put_parent(np);
8383
8384 free_netdev(dev);
8385 pci_release_regions(pdev);
8386 pci_disable_device(pdev);
8387 pci_set_drvdata(pdev, NULL);
8388 }
8389}
8390
8391static int niu_suspend(struct pci_dev *pdev, pm_message_t state)
8392{
8393 struct net_device *dev = pci_get_drvdata(pdev);
8394 struct niu *np = netdev_priv(dev);
8395 unsigned long flags;
8396
8397 if (!netif_running(dev))
8398 return 0;
8399
8400 flush_scheduled_work();
8401 niu_netif_stop(np);
8402
8403 del_timer_sync(&np->timer);
8404
8405 spin_lock_irqsave(&np->lock, flags);
8406 niu_enable_interrupts(np, 0);
8407 spin_unlock_irqrestore(&np->lock, flags);
8408
8409 netif_device_detach(dev);
8410
8411 spin_lock_irqsave(&np->lock, flags);
8412 niu_stop_hw(np);
8413 spin_unlock_irqrestore(&np->lock, flags);
8414
8415 pci_save_state(pdev);
8416
8417 return 0;
8418}
8419
8420static int niu_resume(struct pci_dev *pdev)
8421{
8422 struct net_device *dev = pci_get_drvdata(pdev);
8423 struct niu *np = netdev_priv(dev);
8424 unsigned long flags;
8425 int err;
8426
8427 if (!netif_running(dev))
8428 return 0;
8429
8430 pci_restore_state(pdev);
8431
8432 netif_device_attach(dev);
8433
8434 spin_lock_irqsave(&np->lock, flags);
8435
8436 err = niu_init_hw(np);
8437 if (!err) {
8438 np->timer.expires = jiffies + HZ;
8439 add_timer(&np->timer);
8440 niu_netif_start(np);
8441 }
8442
8443 spin_unlock_irqrestore(&np->lock, flags);
8444
8445 return err;
8446}
8447
8448static struct pci_driver niu_pci_driver = {
8449 .name = DRV_MODULE_NAME,
8450 .id_table = niu_pci_tbl,
8451 .probe = niu_pci_init_one,
8452 .remove = __devexit_p(niu_pci_remove_one),
8453 .suspend = niu_suspend,
8454 .resume = niu_resume,
8455};
8456
8457#ifdef CONFIG_SPARC64
8458static void *niu_phys_alloc_coherent(struct device *dev, size_t size,
8459 u64 *dma_addr, gfp_t flag)
8460{
8461 unsigned long order = get_order(size);
8462 unsigned long page = __get_free_pages(flag, order);
8463
8464 if (page == 0UL)
8465 return NULL;
8466 memset((char *)page, 0, PAGE_SIZE << order);
8467 *dma_addr = __pa(page);
8468
8469 return (void *) page;
8470}
8471
8472static void niu_phys_free_coherent(struct device *dev, size_t size,
8473 void *cpu_addr, u64 handle)
8474{
8475 unsigned long order = get_order(size);
8476
8477 free_pages((unsigned long) cpu_addr, order);
8478}
8479
8480static u64 niu_phys_map_page(struct device *dev, struct page *page,
8481 unsigned long offset, size_t size,
8482 enum dma_data_direction direction)
8483{
8484 return page_to_phys(page) + offset;
8485}
8486
8487static void niu_phys_unmap_page(struct device *dev, u64 dma_address,
8488 size_t size, enum dma_data_direction direction)
8489{
8490 /* Nothing to do. */
8491}
8492
8493static u64 niu_phys_map_single(struct device *dev, void *cpu_addr,
8494 size_t size,
8495 enum dma_data_direction direction)
8496{
8497 return __pa(cpu_addr);
8498}
8499
8500static void niu_phys_unmap_single(struct device *dev, u64 dma_address,
8501 size_t size,
8502 enum dma_data_direction direction)
8503{
8504 /* Nothing to do. */
8505}
8506
8507static const struct niu_ops niu_phys_ops = {
8508 .alloc_coherent = niu_phys_alloc_coherent,
8509 .free_coherent = niu_phys_free_coherent,
8510 .map_page = niu_phys_map_page,
8511 .unmap_page = niu_phys_unmap_page,
8512 .map_single = niu_phys_map_single,
8513 .unmap_single = niu_phys_unmap_single,
8514};
8515
8516static unsigned long res_size(struct resource *r)
8517{
8518 return r->end - r->start + 1UL;
8519}
8520
8521static int __devinit niu_of_probe(struct of_device *op,
8522 const struct of_device_id *match)
8523{
8524 union niu_parent_id parent_id;
8525 struct net_device *dev;
8526 struct niu *np;
8527 const u32 *reg;
8528 int err;
8529
8530 niu_driver_version();
8531
8532 reg = of_get_property(op->node, "reg", NULL);
8533 if (!reg) {
8534 dev_err(&op->dev, PFX "%s: No 'reg' property, aborting.\n",
8535 op->node->full_name);
8536 return -ENODEV;
8537 }
8538
8539 dev = niu_alloc_and_init(&op->dev, NULL, op,
8540 &niu_phys_ops, reg[0] & 0x1);
8541 if (!dev) {
8542 err = -ENOMEM;
8543 goto err_out;
8544 }
8545 np = netdev_priv(dev);
8546
8547 memset(&parent_id, 0, sizeof(parent_id));
8548 parent_id.of = of_get_parent(op->node);
8549
8550 np->parent = niu_get_parent(np, &parent_id,
8551 PLAT_TYPE_NIU);
8552 if (!np->parent) {
8553 err = -ENOMEM;
8554 goto err_out_free_dev;
8555 }
8556
8557 dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM);
8558
8559 np->regs = of_ioremap(&op->resource[1], 0,
8560 res_size(&op->resource[1]),
8561 "niu regs");
8562 if (!np->regs) {
8563 dev_err(&op->dev, PFX "Cannot map device registers, "
8564 "aborting.\n");
8565 err = -ENOMEM;
8566 goto err_out_release_parent;
8567 }
8568
8569 np->vir_regs_1 = of_ioremap(&op->resource[2], 0,
8570 res_size(&op->resource[2]),
8571 "niu vregs-1");
8572 if (!np->vir_regs_1) {
8573 dev_err(&op->dev, PFX "Cannot map device vir registers 1, "
8574 "aborting.\n");
8575 err = -ENOMEM;
8576 goto err_out_iounmap;
8577 }
8578
8579 np->vir_regs_2 = of_ioremap(&op->resource[3], 0,
8580 res_size(&op->resource[3]),
8581 "niu vregs-2");
8582 if (!np->vir_regs_2) {
8583 dev_err(&op->dev, PFX "Cannot map device vir registers 2, "
8584 "aborting.\n");
8585 err = -ENOMEM;
8586 goto err_out_iounmap;
8587 }
8588
8589 niu_assign_netdev_ops(dev);
8590
8591 err = niu_get_invariants(np);
8592 if (err) {
8593 if (err != -ENODEV)
8594 dev_err(&op->dev, PFX "Problem fetching invariants "
8595 "of chip, aborting.\n");
8596 goto err_out_iounmap;
8597 }
8598
8599 err = register_netdev(dev);
8600 if (err) {
8601 dev_err(&op->dev, PFX "Cannot register net device, "
8602 "aborting.\n");
8603 goto err_out_iounmap;
8604 }
8605
8606 dev_set_drvdata(&op->dev, dev);
8607
8608 niu_device_announce(np);
8609
8610 return 0;
8611
8612err_out_iounmap:
8613 if (np->vir_regs_1) {
8614 of_iounmap(&op->resource[2], np->vir_regs_1,
8615 res_size(&op->resource[2]));
8616 np->vir_regs_1 = NULL;
8617 }
8618
8619 if (np->vir_regs_2) {
8620 of_iounmap(&op->resource[3], np->vir_regs_2,
8621 res_size(&op->resource[3]));
8622 np->vir_regs_2 = NULL;
8623 }
8624
8625 if (np->regs) {
8626 of_iounmap(&op->resource[1], np->regs,
8627 res_size(&op->resource[1]));
8628 np->regs = NULL;
8629 }
8630
8631err_out_release_parent:
8632 niu_put_parent(np);
8633
8634err_out_free_dev:
8635 free_netdev(dev);
8636
8637err_out:
8638 return err;
8639}
8640
8641static int __devexit niu_of_remove(struct of_device *op)
8642{
8643 struct net_device *dev = dev_get_drvdata(&op->dev);
8644
8645 if (dev) {
8646 struct niu *np = netdev_priv(dev);
8647
8648 unregister_netdev(dev);
8649
8650 if (np->vir_regs_1) {
8651 of_iounmap(&op->resource[2], np->vir_regs_1,
8652 res_size(&op->resource[2]));
8653 np->vir_regs_1 = NULL;
8654 }
8655
8656 if (np->vir_regs_2) {
8657 of_iounmap(&op->resource[3], np->vir_regs_2,
8658 res_size(&op->resource[3]));
8659 np->vir_regs_2 = NULL;
8660 }
8661
8662 if (np->regs) {
8663 of_iounmap(&op->resource[1], np->regs,
8664 res_size(&op->resource[1]));
8665 np->regs = NULL;
8666 }
8667
8668 niu_ldg_free(np);
8669
8670 niu_put_parent(np);
8671
8672 free_netdev(dev);
8673 dev_set_drvdata(&op->dev, NULL);
8674 }
8675 return 0;
8676}
8677
8678static struct of_device_id niu_match[] = {
8679 {
8680 .name = "network",
8681 .compatible = "SUNW,niusl",
8682 },
8683 {},
8684};
8685MODULE_DEVICE_TABLE(of, niu_match);
8686
8687static struct of_platform_driver niu_of_driver = {
8688 .name = "niu",
8689 .match_table = niu_match,
8690 .probe = niu_of_probe,
8691 .remove = __devexit_p(niu_of_remove),
8692};
8693
8694#endif /* CONFIG_SPARC64 */
8695
8696static int __init niu_init(void)
8697{
8698 int err = 0;
8699
81429973 8700 BUILD_BUG_ON(PAGE_SIZE < 4 * 1024);
a3138df9
DM		 8701
8702 niu_debug = netif_msg_init(debug, NIU_MSG_DEFAULT);
8703
8704#ifdef CONFIG_SPARC64
8705 err = of_register_driver(&niu_of_driver, &of_bus_type);
8706#endif
8707
8708 if (!err) {
8709 err = pci_register_driver(&niu_pci_driver);
8710#ifdef CONFIG_SPARC64
8711 if (err)
8712 of_unregister_driver(&niu_of_driver);
8713#endif
8714 }
8715
8716 return err;
8717}
8718
8719static void __exit niu_exit(void)
8720{
8721 pci_unregister_driver(&niu_pci_driver);
8722#ifdef CONFIG_SPARC64
8723 of_unregister_driver(&niu_of_driver);
8724#endif
8725}
8726
8727module_init(niu_init);
8728module_exit(niu_exit);
Linux 6.x block layer and io_uring tree(s)