Commit | Line | Data |
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3d396eb1 AK |
1 | /* |
2 | * Copyright (C) 2003 - 2006 NetXen, Inc. | |
3 | * All rights reserved. | |
80922fbc | 4 | * |
3d396eb1 AK |
5 | * This program is free software; you can redistribute it and/or |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
80922fbc | 9 | * |
3d396eb1 AK |
10 | * This program is distributed in the hope that it will be useful, but |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
80922fbc | 14 | * |
3d396eb1 AK |
15 | * You should have received a copy of the GNU General Public License |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, | |
18 | * MA 02111-1307, USA. | |
80922fbc | 19 | * |
3d396eb1 AK |
20 | * The full GNU General Public License is included in this distribution |
21 | * in the file called LICENSE. | |
80922fbc | 22 | * |
3d396eb1 AK |
23 | * Contact Information: |
24 | * info@netxen.com | |
25 | * NetXen, | |
26 | * 3965 Freedom Circle, Fourth floor, | |
27 | * Santa Clara, CA 95054 | |
28 | * | |
29 | * | |
30 | * Source file for NIC routines to initialize the Phantom Hardware | |
31 | * | |
32 | */ | |
33 | ||
34 | #include <linux/netdevice.h> | |
35 | #include <linux/delay.h> | |
36 | #include "netxen_nic.h" | |
37 | #include "netxen_nic_hw.h" | |
3d396eb1 AK |
38 | #include "netxen_nic_phan_reg.h" |
39 | ||
40 | struct crb_addr_pair { | |
e0e20a1a LCMT |
41 | u32 addr; |
42 | u32 data; | |
3d396eb1 AK |
43 | }; |
44 | ||
b58ecad8 LCMT |
45 | unsigned long last_schedule_time; |
46 | ||
3d396eb1 AK |
47 | #define NETXEN_MAX_CRB_XFORM 60 |
48 | static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM]; | |
e0e20a1a | 49 | #define NETXEN_ADDR_ERROR (0xffffffff) |
3d396eb1 AK |
50 | |
51 | #define crb_addr_transform(name) \ | |
52 | crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \ | |
53 | NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20 | |
54 | ||
cb8011ad AK |
55 | #define NETXEN_NIC_XDMA_RESET 0x8000ff |
56 | ||
3d396eb1 AK |
57 | static inline void |
58 | netxen_nic_locked_write_reg(struct netxen_adapter *adapter, | |
59 | unsigned long off, int *data) | |
60 | { | |
cb8011ad | 61 | void __iomem *addr = pci_base_offset(adapter, off); |
3d396eb1 AK |
62 | writel(*data, addr); |
63 | } | |
64 | ||
65 | static void crb_addr_transform_setup(void) | |
66 | { | |
67 | crb_addr_transform(XDMA); | |
68 | crb_addr_transform(TIMR); | |
69 | crb_addr_transform(SRE); | |
70 | crb_addr_transform(SQN3); | |
71 | crb_addr_transform(SQN2); | |
72 | crb_addr_transform(SQN1); | |
73 | crb_addr_transform(SQN0); | |
74 | crb_addr_transform(SQS3); | |
75 | crb_addr_transform(SQS2); | |
76 | crb_addr_transform(SQS1); | |
77 | crb_addr_transform(SQS0); | |
78 | crb_addr_transform(RPMX7); | |
79 | crb_addr_transform(RPMX6); | |
80 | crb_addr_transform(RPMX5); | |
81 | crb_addr_transform(RPMX4); | |
82 | crb_addr_transform(RPMX3); | |
83 | crb_addr_transform(RPMX2); | |
84 | crb_addr_transform(RPMX1); | |
85 | crb_addr_transform(RPMX0); | |
86 | crb_addr_transform(ROMUSB); | |
87 | crb_addr_transform(SN); | |
88 | crb_addr_transform(QMN); | |
89 | crb_addr_transform(QMS); | |
90 | crb_addr_transform(PGNI); | |
91 | crb_addr_transform(PGND); | |
92 | crb_addr_transform(PGN3); | |
93 | crb_addr_transform(PGN2); | |
94 | crb_addr_transform(PGN1); | |
95 | crb_addr_transform(PGN0); | |
96 | crb_addr_transform(PGSI); | |
97 | crb_addr_transform(PGSD); | |
98 | crb_addr_transform(PGS3); | |
99 | crb_addr_transform(PGS2); | |
100 | crb_addr_transform(PGS1); | |
101 | crb_addr_transform(PGS0); | |
102 | crb_addr_transform(PS); | |
103 | crb_addr_transform(PH); | |
104 | crb_addr_transform(NIU); | |
105 | crb_addr_transform(I2Q); | |
106 | crb_addr_transform(EG); | |
107 | crb_addr_transform(MN); | |
108 | crb_addr_transform(MS); | |
109 | crb_addr_transform(CAS2); | |
110 | crb_addr_transform(CAS1); | |
111 | crb_addr_transform(CAS0); | |
112 | crb_addr_transform(CAM); | |
113 | crb_addr_transform(C2C1); | |
114 | crb_addr_transform(C2C0); | |
1fcca1a5 | 115 | crb_addr_transform(SMB); |
3d396eb1 AK |
116 | } |
117 | ||
118 | int netxen_init_firmware(struct netxen_adapter *adapter) | |
119 | { | |
120 | u32 state = 0, loops = 0, err = 0; | |
121 | ||
122 | /* Window 1 call */ | |
123 | state = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE)); | |
124 | ||
125 | if (state == PHAN_INITIALIZE_ACK) | |
126 | return 0; | |
127 | ||
128 | while (state != PHAN_INITIALIZE_COMPLETE && loops < 2000) { | |
129 | udelay(100); | |
130 | /* Window 1 call */ | |
131 | state = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE)); | |
132 | ||
133 | loops++; | |
134 | } | |
135 | if (loops >= 2000) { | |
136 | printk(KERN_ERR "Cmd Peg initialization not complete:%x.\n", | |
137 | state); | |
138 | err = -EIO; | |
139 | return err; | |
140 | } | |
141 | /* Window 1 call */ | |
2d1a3bbd | 142 | writel(INTR_SCHEME_PERPORT, |
143 | NETXEN_CRB_NORMALIZE(adapter, CRB_NIC_CAPABILITIES_HOST)); | |
3176ff3e | 144 | writel(MPORT_MULTI_FUNCTION_MODE, |
ed25ffa1 | 145 | NETXEN_CRB_NORMALIZE(adapter, CRB_MPORT_MODE)); |
3d396eb1 AK |
146 | writel(PHAN_INITIALIZE_ACK, |
147 | NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE)); | |
148 | ||
149 | return err; | |
150 | } | |
151 | ||
cb8011ad AK |
152 | #define NETXEN_ADDR_LIMIT 0xffffffffULL |
153 | ||
154 | void *netxen_alloc(struct pci_dev *pdev, size_t sz, dma_addr_t * ptr, | |
155 | struct pci_dev **used_dev) | |
156 | { | |
157 | void *addr; | |
158 | ||
159 | addr = pci_alloc_consistent(pdev, sz, ptr); | |
160 | if ((unsigned long long)(*ptr) < NETXEN_ADDR_LIMIT) { | |
161 | *used_dev = pdev; | |
162 | return addr; | |
163 | } | |
164 | pci_free_consistent(pdev, sz, addr, *ptr); | |
165 | addr = pci_alloc_consistent(NULL, sz, ptr); | |
166 | *used_dev = NULL; | |
167 | return addr; | |
168 | } | |
169 | ||
3d396eb1 AK |
170 | void netxen_initialize_adapter_sw(struct netxen_adapter *adapter) |
171 | { | |
172 | int ctxid, ring; | |
173 | u32 i; | |
174 | u32 num_rx_bufs = 0; | |
175 | struct netxen_rcv_desc_ctx *rcv_desc; | |
176 | ||
177 | DPRINTK(INFO, "initializing some queues: %p\n", adapter); | |
178 | for (ctxid = 0; ctxid < MAX_RCV_CTX; ++ctxid) { | |
179 | for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) { | |
180 | struct netxen_rx_buffer *rx_buf; | |
181 | rcv_desc = &adapter->recv_ctx[ctxid].rcv_desc[ring]; | |
182 | rcv_desc->rcv_free = rcv_desc->max_rx_desc_count; | |
183 | rcv_desc->begin_alloc = 0; | |
184 | rx_buf = rcv_desc->rx_buf_arr; | |
185 | num_rx_bufs = rcv_desc->max_rx_desc_count; | |
186 | /* | |
187 | * Now go through all of them, set reference handles | |
188 | * and put them in the queues. | |
189 | */ | |
190 | for (i = 0; i < num_rx_bufs; i++) { | |
191 | rx_buf->ref_handle = i; | |
192 | rx_buf->state = NETXEN_BUFFER_FREE; | |
3d396eb1 AK |
193 | DPRINTK(INFO, "Rx buf:ctx%d i(%d) rx_buf:" |
194 | "%p\n", ctxid, i, rx_buf); | |
195 | rx_buf++; | |
196 | } | |
197 | } | |
198 | } | |
3d396eb1 AK |
199 | } |
200 | ||
201 | void netxen_initialize_adapter_hw(struct netxen_adapter *adapter) | |
202 | { | |
cb8011ad AK |
203 | int ports = 0; |
204 | struct netxen_board_info *board_info = &(adapter->ahw.boardcfg); | |
205 | ||
3d396eb1 AK |
206 | if (netxen_nic_get_board_info(adapter) != 0) |
207 | printk("%s: Error getting board config info.\n", | |
208 | netxen_nic_driver_name); | |
cb8011ad AK |
209 | get_brd_port_by_type(board_info->board_type, &ports); |
210 | if (ports == 0) | |
3d396eb1 AK |
211 | printk(KERN_ERR "%s: Unknown board type\n", |
212 | netxen_nic_driver_name); | |
cb8011ad | 213 | adapter->ahw.max_ports = ports; |
3d396eb1 AK |
214 | } |
215 | ||
216 | void netxen_initialize_adapter_ops(struct netxen_adapter *adapter) | |
217 | { | |
3d396eb1 AK |
218 | switch (adapter->ahw.board_type) { |
219 | case NETXEN_NIC_GBE: | |
80922fbc | 220 | adapter->enable_phy_interrupts = |
3d396eb1 | 221 | netxen_niu_gbe_enable_phy_interrupts; |
80922fbc | 222 | adapter->disable_phy_interrupts = |
3d396eb1 | 223 | netxen_niu_gbe_disable_phy_interrupts; |
80922fbc AK |
224 | adapter->handle_phy_intr = netxen_nic_gbe_handle_phy_intr; |
225 | adapter->macaddr_set = netxen_niu_macaddr_set; | |
226 | adapter->set_mtu = netxen_nic_set_mtu_gb; | |
227 | adapter->set_promisc = netxen_niu_set_promiscuous_mode; | |
228 | adapter->unset_promisc = netxen_niu_set_promiscuous_mode; | |
229 | adapter->phy_read = netxen_niu_gbe_phy_read; | |
230 | adapter->phy_write = netxen_niu_gbe_phy_write; | |
80922fbc AK |
231 | adapter->init_niu = netxen_nic_init_niu_gb; |
232 | adapter->stop_port = netxen_niu_disable_gbe_port; | |
3d396eb1 AK |
233 | break; |
234 | ||
235 | case NETXEN_NIC_XGBE: | |
80922fbc | 236 | adapter->enable_phy_interrupts = |
3d396eb1 | 237 | netxen_niu_xgbe_enable_phy_interrupts; |
80922fbc | 238 | adapter->disable_phy_interrupts = |
3d396eb1 | 239 | netxen_niu_xgbe_disable_phy_interrupts; |
80922fbc AK |
240 | adapter->handle_phy_intr = netxen_nic_xgbe_handle_phy_intr; |
241 | adapter->macaddr_set = netxen_niu_xg_macaddr_set; | |
242 | adapter->set_mtu = netxen_nic_set_mtu_xgb; | |
243 | adapter->init_port = netxen_niu_xg_init_port; | |
244 | adapter->set_promisc = netxen_niu_xg_set_promiscuous_mode; | |
245 | adapter->unset_promisc = netxen_niu_xg_set_promiscuous_mode; | |
246 | adapter->stop_port = netxen_niu_disable_xg_port; | |
3d396eb1 AK |
247 | break; |
248 | ||
249 | default: | |
250 | break; | |
251 | } | |
252 | } | |
253 | ||
254 | /* | |
255 | * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB | |
256 | * address to external PCI CRB address. | |
257 | */ | |
e0e20a1a | 258 | u32 netxen_decode_crb_addr(u32 addr) |
3d396eb1 AK |
259 | { |
260 | int i; | |
e0e20a1a | 261 | u32 base_addr, offset, pci_base; |
3d396eb1 AK |
262 | |
263 | crb_addr_transform_setup(); | |
264 | ||
265 | pci_base = NETXEN_ADDR_ERROR; | |
266 | base_addr = addr & 0xfff00000; | |
267 | offset = addr & 0x000fffff; | |
268 | ||
269 | for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) { | |
270 | if (crb_addr_xform[i] == base_addr) { | |
271 | pci_base = i << 20; | |
272 | break; | |
273 | } | |
274 | } | |
275 | if (pci_base == NETXEN_ADDR_ERROR) | |
276 | return pci_base; | |
277 | else | |
278 | return (pci_base + offset); | |
279 | } | |
280 | ||
13ba9c77 MT |
281 | static long rom_max_timeout = 100; |
282 | static long rom_lock_timeout = 10000; | |
27d2ab54 | 283 | static long rom_write_timeout = 700; |
3d396eb1 AK |
284 | |
285 | static inline int rom_lock(struct netxen_adapter *adapter) | |
286 | { | |
287 | int iter; | |
288 | u32 done = 0; | |
289 | int timeout = 0; | |
290 | ||
291 | while (!done) { | |
292 | /* acquire semaphore2 from PCI HW block */ | |
293 | netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_LOCK), | |
294 | &done); | |
295 | if (done == 1) | |
296 | break; | |
297 | if (timeout >= rom_lock_timeout) | |
298 | return -EIO; | |
299 | ||
300 | timeout++; | |
301 | /* | |
302 | * Yield CPU | |
303 | */ | |
304 | if (!in_atomic()) | |
305 | schedule(); | |
306 | else { | |
307 | for (iter = 0; iter < 20; iter++) | |
308 | cpu_relax(); /*This a nop instr on i386 */ | |
309 | } | |
310 | } | |
311 | netxen_nic_reg_write(adapter, NETXEN_ROM_LOCK_ID, ROM_LOCK_DRIVER); | |
312 | return 0; | |
313 | } | |
314 | ||
3d396eb1 AK |
315 | int netxen_wait_rom_done(struct netxen_adapter *adapter) |
316 | { | |
317 | long timeout = 0; | |
318 | long done = 0; | |
319 | ||
320 | while (done == 0) { | |
321 | done = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_GLB_STATUS); | |
322 | done &= 2; | |
323 | timeout++; | |
324 | if (timeout >= rom_max_timeout) { | |
325 | printk("Timeout reached waiting for rom done"); | |
326 | return -EIO; | |
327 | } | |
328 | } | |
329 | return 0; | |
330 | } | |
331 | ||
cb8011ad AK |
332 | static inline int netxen_rom_wren(struct netxen_adapter *adapter) |
333 | { | |
334 | /* Set write enable latch in ROM status register */ | |
335 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0); | |
336 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, | |
337 | M25P_INSTR_WREN); | |
338 | if (netxen_wait_rom_done(adapter)) { | |
339 | return -1; | |
340 | } | |
341 | return 0; | |
342 | } | |
343 | ||
344 | static inline unsigned int netxen_rdcrbreg(struct netxen_adapter *adapter, | |
345 | unsigned int addr) | |
346 | { | |
347 | unsigned int data = 0xdeaddead; | |
348 | data = netxen_nic_reg_read(adapter, addr); | |
349 | return data; | |
350 | } | |
351 | ||
352 | static inline int netxen_do_rom_rdsr(struct netxen_adapter *adapter) | |
353 | { | |
354 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, | |
355 | M25P_INSTR_RDSR); | |
356 | if (netxen_wait_rom_done(adapter)) { | |
357 | return -1; | |
358 | } | |
359 | return netxen_rdcrbreg(adapter, NETXEN_ROMUSB_ROM_RDATA); | |
360 | } | |
361 | ||
362 | static inline void netxen_rom_unlock(struct netxen_adapter *adapter) | |
363 | { | |
364 | u32 val; | |
365 | ||
366 | /* release semaphore2 */ | |
367 | netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_UNLOCK), &val); | |
368 | ||
369 | } | |
370 | ||
371 | int netxen_rom_wip_poll(struct netxen_adapter *adapter) | |
372 | { | |
373 | long timeout = 0; | |
374 | long wip = 1; | |
375 | int val; | |
376 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0); | |
377 | while (wip != 0) { | |
378 | val = netxen_do_rom_rdsr(adapter); | |
379 | wip = val & 1; | |
380 | timeout++; | |
381 | if (timeout > rom_max_timeout) { | |
382 | return -1; | |
383 | } | |
384 | } | |
385 | return 0; | |
386 | } | |
387 | ||
80922fbc AK |
388 | static inline int do_rom_fast_write(struct netxen_adapter *adapter, int addr, |
389 | int data) | |
cb8011ad AK |
390 | { |
391 | if (netxen_rom_wren(adapter)) { | |
392 | return -1; | |
393 | } | |
394 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_WDATA, data); | |
395 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr); | |
396 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3); | |
397 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, | |
398 | M25P_INSTR_PP); | |
399 | if (netxen_wait_rom_done(adapter)) { | |
400 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0); | |
401 | return -1; | |
402 | } | |
403 | ||
404 | return netxen_rom_wip_poll(adapter); | |
405 | } | |
406 | ||
3d396eb1 AK |
407 | static inline int |
408 | do_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp) | |
409 | { | |
96acb6eb | 410 | cond_resched(); |
b58ecad8 | 411 | |
3d396eb1 AK |
412 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr); |
413 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3); | |
b58ecad8 | 414 | udelay(100); /* prevent bursting on CRB */ |
3d396eb1 AK |
415 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); |
416 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb); | |
417 | if (netxen_wait_rom_done(adapter)) { | |
418 | printk("Error waiting for rom done\n"); | |
419 | return -EIO; | |
420 | } | |
421 | /* reset abyte_cnt and dummy_byte_cnt */ | |
422 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0); | |
b58ecad8 | 423 | udelay(100); /* prevent bursting on CRB */ |
3d396eb1 AK |
424 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); |
425 | ||
426 | *valp = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_ROM_RDATA); | |
427 | return 0; | |
428 | } | |
429 | ||
27d2ab54 AK |
430 | static inline int |
431 | do_rom_fast_read_words(struct netxen_adapter *adapter, int addr, | |
432 | u8 *bytes, size_t size) | |
433 | { | |
434 | int addridx; | |
435 | int ret = 0; | |
436 | ||
437 | for (addridx = addr; addridx < (addr + size); addridx += 4) { | |
438 | ret = do_rom_fast_read(adapter, addridx, (int *)bytes); | |
439 | if (ret != 0) | |
440 | break; | |
6d1495f2 | 441 | *(int *)bytes = cpu_to_le32(*(int *)bytes); |
27d2ab54 AK |
442 | bytes += 4; |
443 | } | |
444 | ||
445 | return ret; | |
446 | } | |
447 | ||
448 | int | |
449 | netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr, | |
450 | u8 *bytes, size_t size) | |
451 | { | |
452 | int ret; | |
453 | ||
454 | ret = rom_lock(adapter); | |
455 | if (ret < 0) | |
456 | return ret; | |
457 | ||
458 | ret = do_rom_fast_read_words(adapter, addr, bytes, size); | |
459 | ||
460 | netxen_rom_unlock(adapter); | |
461 | return ret; | |
462 | } | |
463 | ||
3d396eb1 AK |
464 | int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp) |
465 | { | |
466 | int ret; | |
467 | ||
468 | if (rom_lock(adapter) != 0) | |
469 | return -EIO; | |
470 | ||
471 | ret = do_rom_fast_read(adapter, addr, valp); | |
cb8011ad AK |
472 | netxen_rom_unlock(adapter); |
473 | return ret; | |
474 | } | |
475 | ||
476 | int netxen_rom_fast_write(struct netxen_adapter *adapter, int addr, int data) | |
477 | { | |
478 | int ret = 0; | |
479 | ||
480 | if (rom_lock(adapter) != 0) { | |
481 | return -1; | |
482 | } | |
483 | ret = do_rom_fast_write(adapter, addr, data); | |
484 | netxen_rom_unlock(adapter); | |
485 | return ret; | |
486 | } | |
27d2ab54 AK |
487 | |
488 | static inline int do_rom_fast_write_words(struct netxen_adapter *adapter, | |
489 | int addr, u8 *bytes, size_t size) | |
490 | { | |
491 | int addridx = addr; | |
492 | int ret = 0; | |
493 | ||
494 | while (addridx < (addr + size)) { | |
495 | int last_attempt = 0; | |
496 | int timeout = 0; | |
497 | int data; | |
498 | ||
6d1495f2 | 499 | data = le32_to_cpu((*(u32*)bytes)); |
27d2ab54 AK |
500 | ret = do_rom_fast_write(adapter, addridx, data); |
501 | if (ret < 0) | |
502 | return ret; | |
503 | ||
504 | while(1) { | |
505 | int data1; | |
506 | ||
f8dfdd5c SH |
507 | ret = do_rom_fast_read(adapter, addridx, &data1); |
508 | if (ret < 0) | |
509 | return ret; | |
510 | ||
27d2ab54 AK |
511 | if (data1 == data) |
512 | break; | |
513 | ||
514 | if (timeout++ >= rom_write_timeout) { | |
515 | if (last_attempt++ < 4) { | |
516 | ret = do_rom_fast_write(adapter, | |
517 | addridx, data); | |
518 | if (ret < 0) | |
519 | return ret; | |
520 | } | |
521 | else { | |
522 | printk(KERN_INFO "Data write did not " | |
523 | "succeed at address 0x%x\n", addridx); | |
524 | break; | |
525 | } | |
526 | } | |
527 | } | |
528 | ||
529 | bytes += 4; | |
530 | addridx += 4; | |
531 | } | |
532 | ||
533 | return ret; | |
534 | } | |
535 | ||
536 | int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr, | |
537 | u8 *bytes, size_t size) | |
538 | { | |
539 | int ret = 0; | |
540 | ||
541 | ret = rom_lock(adapter); | |
542 | if (ret < 0) | |
543 | return ret; | |
544 | ||
545 | ret = do_rom_fast_write_words(adapter, addr, bytes, size); | |
546 | netxen_rom_unlock(adapter); | |
547 | ||
548 | return ret; | |
549 | } | |
550 | ||
551 | int netxen_rom_wrsr(struct netxen_adapter *adapter, int data) | |
552 | { | |
553 | int ret; | |
554 | ||
555 | ret = netxen_rom_wren(adapter); | |
556 | if (ret < 0) | |
557 | return ret; | |
558 | ||
559 | netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_ROM_WDATA, data); | |
560 | netxen_crb_writelit_adapter(adapter, | |
561 | NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0x1); | |
562 | ||
563 | ret = netxen_wait_rom_done(adapter); | |
564 | if (ret < 0) | |
565 | return ret; | |
566 | ||
567 | return netxen_rom_wip_poll(adapter); | |
568 | } | |
569 | ||
570 | int netxen_rom_rdsr(struct netxen_adapter *adapter) | |
571 | { | |
572 | int ret; | |
573 | ||
574 | ret = rom_lock(adapter); | |
575 | if (ret < 0) | |
576 | return ret; | |
577 | ||
578 | ret = netxen_do_rom_rdsr(adapter); | |
579 | netxen_rom_unlock(adapter); | |
580 | return ret; | |
581 | } | |
582 | ||
583 | int netxen_backup_crbinit(struct netxen_adapter *adapter) | |
584 | { | |
585 | int ret = FLASH_SUCCESS; | |
586 | int val; | |
0d04761d | 587 | char *buffer = kmalloc(NETXEN_FLASH_SECTOR_SIZE, GFP_KERNEL); |
27d2ab54 AK |
588 | |
589 | if (!buffer) | |
590 | return -ENOMEM; | |
591 | /* unlock sector 63 */ | |
592 | val = netxen_rom_rdsr(adapter); | |
593 | val = val & 0xe3; | |
594 | ret = netxen_rom_wrsr(adapter, val); | |
595 | if (ret != FLASH_SUCCESS) | |
596 | goto out_kfree; | |
597 | ||
598 | ret = netxen_rom_wip_poll(adapter); | |
599 | if (ret != FLASH_SUCCESS) | |
600 | goto out_kfree; | |
601 | ||
602 | /* copy sector 0 to sector 63 */ | |
0d04761d MT |
603 | ret = netxen_rom_fast_read_words(adapter, NETXEN_CRBINIT_START, |
604 | buffer, NETXEN_FLASH_SECTOR_SIZE); | |
27d2ab54 AK |
605 | if (ret != FLASH_SUCCESS) |
606 | goto out_kfree; | |
607 | ||
0d04761d MT |
608 | ret = netxen_rom_fast_write_words(adapter, NETXEN_FIXED_START, |
609 | buffer, NETXEN_FLASH_SECTOR_SIZE); | |
27d2ab54 AK |
610 | if (ret != FLASH_SUCCESS) |
611 | goto out_kfree; | |
612 | ||
613 | /* lock sector 63 */ | |
614 | val = netxen_rom_rdsr(adapter); | |
615 | if (!(val & 0x8)) { | |
616 | val |= (0x1 << 2); | |
617 | /* lock sector 63 */ | |
618 | if (netxen_rom_wrsr(adapter, val) == 0) { | |
619 | ret = netxen_rom_wip_poll(adapter); | |
620 | if (ret != FLASH_SUCCESS) | |
621 | goto out_kfree; | |
622 | ||
623 | /* lock SR writes */ | |
624 | ret = netxen_rom_wip_poll(adapter); | |
625 | if (ret != FLASH_SUCCESS) | |
626 | goto out_kfree; | |
627 | } | |
628 | } | |
629 | ||
630 | out_kfree: | |
631 | kfree(buffer); | |
632 | return ret; | |
633 | } | |
634 | ||
cb8011ad AK |
635 | int netxen_do_rom_se(struct netxen_adapter *adapter, int addr) |
636 | { | |
637 | netxen_rom_wren(adapter); | |
638 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr); | |
639 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3); | |
640 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, | |
641 | M25P_INSTR_SE); | |
642 | if (netxen_wait_rom_done(adapter)) { | |
643 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0); | |
644 | return -1; | |
645 | } | |
646 | return netxen_rom_wip_poll(adapter); | |
647 | } | |
648 | ||
27d2ab54 AK |
649 | void check_erased_flash(struct netxen_adapter *adapter, int addr) |
650 | { | |
651 | int i; | |
652 | int val; | |
653 | int count = 0, erased_errors = 0; | |
654 | int range; | |
655 | ||
0d04761d MT |
656 | range = (addr == NETXEN_USER_START) ? |
657 | NETXEN_FIXED_START : addr + NETXEN_FLASH_SECTOR_SIZE; | |
27d2ab54 AK |
658 | |
659 | for (i = addr; i < range; i += 4) { | |
660 | netxen_rom_fast_read(adapter, i, &val); | |
661 | if (val != 0xffffffff) | |
662 | erased_errors++; | |
663 | count++; | |
664 | } | |
665 | ||
666 | if (erased_errors) | |
667 | printk(KERN_INFO "0x%x out of 0x%x words fail to be erased " | |
668 | "for sector address: %x\n", erased_errors, count, addr); | |
669 | } | |
670 | ||
cb8011ad AK |
671 | int netxen_rom_se(struct netxen_adapter *adapter, int addr) |
672 | { | |
673 | int ret = 0; | |
674 | if (rom_lock(adapter) != 0) { | |
675 | return -1; | |
676 | } | |
677 | ret = netxen_do_rom_se(adapter, addr); | |
678 | netxen_rom_unlock(adapter); | |
27d2ab54 AK |
679 | msleep(30); |
680 | check_erased_flash(adapter, addr); | |
681 | ||
682 | return ret; | |
683 | } | |
684 | ||
685 | int | |
686 | netxen_flash_erase_sections(struct netxen_adapter *adapter, int start, int end) | |
687 | { | |
688 | int ret = FLASH_SUCCESS; | |
689 | int i; | |
690 | ||
691 | for (i = start; i < end; i++) { | |
0d04761d | 692 | ret = netxen_rom_se(adapter, i * NETXEN_FLASH_SECTOR_SIZE); |
27d2ab54 AK |
693 | if (ret) |
694 | break; | |
695 | ret = netxen_rom_wip_poll(adapter); | |
696 | if (ret < 0) | |
697 | return ret; | |
698 | } | |
699 | ||
700 | return ret; | |
701 | } | |
702 | ||
703 | int | |
704 | netxen_flash_erase_secondary(struct netxen_adapter *adapter) | |
705 | { | |
706 | int ret = FLASH_SUCCESS; | |
707 | int start, end; | |
708 | ||
0d04761d MT |
709 | start = NETXEN_SECONDARY_START / NETXEN_FLASH_SECTOR_SIZE; |
710 | end = NETXEN_USER_START / NETXEN_FLASH_SECTOR_SIZE; | |
27d2ab54 AK |
711 | ret = netxen_flash_erase_sections(adapter, start, end); |
712 | ||
713 | return ret; | |
714 | } | |
715 | ||
716 | int | |
717 | netxen_flash_erase_primary(struct netxen_adapter *adapter) | |
718 | { | |
719 | int ret = FLASH_SUCCESS; | |
720 | int start, end; | |
721 | ||
0d04761d MT |
722 | start = NETXEN_PRIMARY_START / NETXEN_FLASH_SECTOR_SIZE; |
723 | end = NETXEN_SECONDARY_START / NETXEN_FLASH_SECTOR_SIZE; | |
27d2ab54 AK |
724 | ret = netxen_flash_erase_sections(adapter, start, end); |
725 | ||
726 | return ret; | |
727 | } | |
728 | ||
e45d9ab4 AK |
729 | void netxen_halt_pegs(struct netxen_adapter *adapter) |
730 | { | |
731 | netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0x3c, 1); | |
732 | netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0x3c, 1); | |
733 | netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0x3c, 1); | |
734 | netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0x3c, 1); | |
735 | } | |
736 | ||
27d2ab54 AK |
737 | int netxen_flash_unlock(struct netxen_adapter *adapter) |
738 | { | |
739 | int ret = 0; | |
740 | ||
741 | ret = netxen_rom_wrsr(adapter, 0); | |
742 | if (ret < 0) | |
743 | return ret; | |
744 | ||
745 | ret = netxen_rom_wren(adapter); | |
746 | if (ret < 0) | |
747 | return ret; | |
748 | ||
3d396eb1 AK |
749 | return ret; |
750 | } | |
751 | ||
752 | #define NETXEN_BOARDTYPE 0x4008 | |
753 | #define NETXEN_BOARDNUM 0x400c | |
754 | #define NETXEN_CHIPNUM 0x4010 | |
755 | #define NETXEN_ROMBUS_RESET 0xFFFFFFFF | |
756 | #define NETXEN_ROM_FIRST_BARRIER 0x800000000ULL | |
757 | #define NETXEN_ROM_FOUND_INIT 0x400 | |
758 | ||
759 | int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose) | |
760 | { | |
761 | int addr, val, status; | |
762 | int n, i; | |
763 | int init_delay = 0; | |
764 | struct crb_addr_pair *buf; | |
e0e20a1a | 765 | u32 off; |
3d396eb1 AK |
766 | |
767 | /* resetall */ | |
768 | status = netxen_nic_get_board_info(adapter); | |
769 | if (status) | |
cb8011ad | 770 | printk("%s: netxen_pinit_from_rom: Error getting board info\n", |
3d396eb1 AK |
771 | netxen_nic_driver_name); |
772 | ||
773 | netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_GLB_SW_RESET, | |
774 | NETXEN_ROMBUS_RESET); | |
775 | ||
776 | if (verbose) { | |
777 | int val; | |
778 | if (netxen_rom_fast_read(adapter, NETXEN_BOARDTYPE, &val) == 0) | |
779 | printk("P2 ROM board type: 0x%08x\n", val); | |
780 | else | |
781 | printk("Could not read board type\n"); | |
782 | if (netxen_rom_fast_read(adapter, NETXEN_BOARDNUM, &val) == 0) | |
783 | printk("P2 ROM board num: 0x%08x\n", val); | |
784 | else | |
785 | printk("Could not read board number\n"); | |
786 | if (netxen_rom_fast_read(adapter, NETXEN_CHIPNUM, &val) == 0) | |
787 | printk("P2 ROM chip num: 0x%08x\n", val); | |
788 | else | |
789 | printk("Could not read chip number\n"); | |
790 | } | |
791 | ||
792 | if (netxen_rom_fast_read(adapter, 0, &n) == 0 | |
793 | && (n & NETXEN_ROM_FIRST_BARRIER)) { | |
794 | n &= ~NETXEN_ROM_ROUNDUP; | |
795 | if (n < NETXEN_ROM_FOUND_INIT) { | |
796 | if (verbose) | |
797 | printk("%s: %d CRB init values found" | |
798 | " in ROM.\n", netxen_nic_driver_name, n); | |
799 | } else { | |
800 | printk("%s:n=0x%x Error! NetXen card flash not" | |
801 | " initialized.\n", __FUNCTION__, n); | |
802 | return -EIO; | |
803 | } | |
804 | buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL); | |
805 | if (buf == NULL) { | |
cb8011ad AK |
806 | printk("%s: netxen_pinit_from_rom: Unable to calloc " |
807 | "memory.\n", netxen_nic_driver_name); | |
3d396eb1 AK |
808 | return -ENOMEM; |
809 | } | |
810 | for (i = 0; i < n; i++) { | |
811 | if (netxen_rom_fast_read(adapter, 8 * i + 4, &val) != 0 | |
812 | || netxen_rom_fast_read(adapter, 8 * i + 8, | |
813 | &addr) != 0) | |
814 | return -EIO; | |
815 | ||
816 | buf[i].addr = addr; | |
817 | buf[i].data = val; | |
818 | ||
819 | if (verbose) | |
820 | printk("%s: PCI: 0x%08x == 0x%08x\n", | |
821 | netxen_nic_driver_name, (unsigned int) | |
e0e20a1a | 822 | netxen_decode_crb_addr(addr), val); |
3d396eb1 AK |
823 | } |
824 | for (i = 0; i < n; i++) { | |
825 | ||
e0e20a1a | 826 | off = netxen_decode_crb_addr(buf[i].addr); |
1fcca1a5 | 827 | if (off == NETXEN_ADDR_ERROR) { |
e0e20a1a | 828 | printk(KERN_ERR"CRB init value out of range %x\n", |
1fcca1a5 AK |
829 | buf[i].addr); |
830 | continue; | |
831 | } | |
832 | off += NETXEN_PCI_CRBSPACE; | |
3d396eb1 AK |
833 | /* skipping cold reboot MAGIC */ |
834 | if (off == NETXEN_CAM_RAM(0x1fc)) | |
835 | continue; | |
836 | ||
837 | /* After writing this register, HW needs time for CRB */ | |
838 | /* to quiet down (else crb_window returns 0xffffffff) */ | |
839 | if (off == NETXEN_ROMUSB_GLB_SW_RESET) { | |
840 | init_delay = 1; | |
841 | /* hold xdma in reset also */ | |
cb8011ad | 842 | buf[i].data = NETXEN_NIC_XDMA_RESET; |
3d396eb1 AK |
843 | } |
844 | ||
845 | if (ADDR_IN_WINDOW1(off)) { | |
846 | writel(buf[i].data, | |
847 | NETXEN_CRB_NORMALIZE(adapter, off)); | |
848 | } else { | |
849 | netxen_nic_pci_change_crbwindow(adapter, 0); | |
850 | writel(buf[i].data, | |
cb8011ad | 851 | pci_base_offset(adapter, off)); |
3d396eb1 AK |
852 | |
853 | netxen_nic_pci_change_crbwindow(adapter, 1); | |
854 | } | |
855 | if (init_delay == 1) { | |
96acb6eb | 856 | msleep(2000); |
3d396eb1 AK |
857 | init_delay = 0; |
858 | } | |
96acb6eb | 859 | msleep(20); |
3d396eb1 AK |
860 | } |
861 | kfree(buf); | |
862 | ||
863 | /* disable_peg_cache_all */ | |
864 | ||
865 | /* unreset_net_cache */ | |
866 | netxen_nic_hw_read_wx(adapter, NETXEN_ROMUSB_GLB_SW_RESET, &val, | |
867 | 4); | |
868 | netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_GLB_SW_RESET, | |
869 | (val & 0xffffff0f)); | |
870 | /* p2dn replyCount */ | |
871 | netxen_crb_writelit_adapter(adapter, | |
872 | NETXEN_CRB_PEG_NET_D + 0xec, 0x1e); | |
873 | /* disable_peg_cache 0 */ | |
874 | netxen_crb_writelit_adapter(adapter, | |
875 | NETXEN_CRB_PEG_NET_D + 0x4c, 8); | |
876 | /* disable_peg_cache 1 */ | |
877 | netxen_crb_writelit_adapter(adapter, | |
878 | NETXEN_CRB_PEG_NET_I + 0x4c, 8); | |
879 | ||
880 | /* peg_clr_all */ | |
881 | ||
882 | /* peg_clr 0 */ | |
883 | netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, | |
884 | 0); | |
885 | netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, | |
886 | 0); | |
887 | /* peg_clr 1 */ | |
888 | netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, | |
889 | 0); | |
890 | netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, | |
891 | 0); | |
892 | /* peg_clr 2 */ | |
893 | netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, | |
894 | 0); | |
895 | netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, | |
896 | 0); | |
897 | /* peg_clr 3 */ | |
898 | netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, | |
899 | 0); | |
900 | netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, | |
901 | 0); | |
902 | } | |
903 | return 0; | |
904 | } | |
905 | ||
ed25ffa1 AK |
906 | int netxen_initialize_adapter_offload(struct netxen_adapter *adapter) |
907 | { | |
908 | uint64_t addr; | |
909 | uint32_t hi; | |
910 | uint32_t lo; | |
911 | ||
912 | adapter->dummy_dma.addr = | |
913 | pci_alloc_consistent(adapter->ahw.pdev, | |
914 | NETXEN_HOST_DUMMY_DMA_SIZE, | |
915 | &adapter->dummy_dma.phys_addr); | |
916 | if (adapter->dummy_dma.addr == NULL) { | |
917 | printk("%s: ERROR: Could not allocate dummy DMA memory\n", | |
918 | __FUNCTION__); | |
919 | return -ENOMEM; | |
920 | } | |
921 | ||
922 | addr = (uint64_t) adapter->dummy_dma.phys_addr; | |
923 | hi = (addr >> 32) & 0xffffffff; | |
924 | lo = addr & 0xffffffff; | |
925 | ||
926 | writel(hi, NETXEN_CRB_NORMALIZE(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI)); | |
927 | writel(lo, NETXEN_CRB_NORMALIZE(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO)); | |
928 | ||
929 | return 0; | |
930 | } | |
931 | ||
932 | void netxen_free_adapter_offload(struct netxen_adapter *adapter) | |
933 | { | |
934 | if (adapter->dummy_dma.addr) { | |
935 | pci_free_consistent(adapter->ahw.pdev, | |
936 | NETXEN_HOST_DUMMY_DMA_SIZE, | |
937 | adapter->dummy_dma.addr, | |
938 | adapter->dummy_dma.phys_addr); | |
939 | adapter->dummy_dma.addr = NULL; | |
940 | } | |
941 | } | |
942 | ||
96acb6eb | 943 | int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val) |
3d396eb1 AK |
944 | { |
945 | u32 val = 0; | |
96acb6eb | 946 | int retries = 30; |
3d396eb1 | 947 | |
cb8011ad | 948 | if (!pegtune_val) { |
96acb6eb DP |
949 | do { |
950 | val = readl(NETXEN_CRB_NORMALIZE | |
3d396eb1 | 951 | (adapter, CRB_CMDPEG_STATE)); |
96acb6eb DP |
952 | pegtune_val = readl(NETXEN_CRB_NORMALIZE |
953 | (adapter, NETXEN_ROMUSB_GLB_PEGTUNE_DONE)); | |
954 | ||
955 | if (val == PHAN_INITIALIZE_COMPLETE || | |
956 | val == PHAN_INITIALIZE_ACK) | |
957 | return 0; | |
958 | ||
959 | msleep(1000); | |
960 | } while (--retries); | |
961 | if (!retries) { | |
962 | printk(KERN_WARNING "netxen_phantom_init: init failed, " | |
963 | "pegtune_val=%x\n", pegtune_val); | |
964 | return -1; | |
3d396eb1 | 965 | } |
3d396eb1 | 966 | } |
96acb6eb DP |
967 | |
968 | return 0; | |
3d396eb1 AK |
969 | } |
970 | ||
971 | int netxen_nic_rx_has_work(struct netxen_adapter *adapter) | |
972 | { | |
973 | int ctx; | |
974 | ||
975 | for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) { | |
976 | struct netxen_recv_context *recv_ctx = | |
977 | &(adapter->recv_ctx[ctx]); | |
978 | u32 consumer; | |
979 | struct status_desc *desc_head; | |
cb8011ad | 980 | struct status_desc *desc; |
3d396eb1 AK |
981 | |
982 | consumer = recv_ctx->status_rx_consumer; | |
983 | desc_head = recv_ctx->rcv_status_desc_head; | |
984 | desc = &desc_head[consumer]; | |
985 | ||
a608ab9c | 986 | if (netxen_get_sts_owner(desc) & STATUS_OWNER_HOST) |
3d396eb1 AK |
987 | return 1; |
988 | } | |
989 | ||
990 | return 0; | |
991 | } | |
992 | ||
cb8011ad AK |
993 | static inline int netxen_nic_check_temp(struct netxen_adapter *adapter) |
994 | { | |
3176ff3e | 995 | struct net_device *netdev = adapter->netdev; |
cb8011ad AK |
996 | uint32_t temp, temp_state, temp_val; |
997 | int rv = 0; | |
998 | ||
999 | temp = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_TEMP_STATE)); | |
1000 | ||
1001 | temp_state = nx_get_temp_state(temp); | |
1002 | temp_val = nx_get_temp_val(temp); | |
1003 | ||
1004 | if (temp_state == NX_TEMP_PANIC) { | |
1005 | printk(KERN_ALERT | |
1006 | "%s: Device temperature %d degrees C exceeds" | |
1007 | " maximum allowed. Hardware has been shut down.\n", | |
1008 | netxen_nic_driver_name, temp_val); | |
cb8011ad | 1009 | |
3176ff3e MT |
1010 | netif_carrier_off(netdev); |
1011 | netif_stop_queue(netdev); | |
cb8011ad AK |
1012 | rv = 1; |
1013 | } else if (temp_state == NX_TEMP_WARN) { | |
1014 | if (adapter->temp == NX_TEMP_NORMAL) { | |
1015 | printk(KERN_ALERT | |
1016 | "%s: Device temperature %d degrees C " | |
1017 | "exceeds operating range." | |
1018 | " Immediate action needed.\n", | |
1019 | netxen_nic_driver_name, temp_val); | |
1020 | } | |
1021 | } else { | |
1022 | if (adapter->temp == NX_TEMP_WARN) { | |
1023 | printk(KERN_INFO | |
1024 | "%s: Device temperature is now %d degrees C" | |
1025 | " in normal range.\n", netxen_nic_driver_name, | |
1026 | temp_val); | |
1027 | } | |
1028 | } | |
1029 | adapter->temp = temp_state; | |
1030 | return rv; | |
1031 | } | |
1032 | ||
6d5aefb8 | 1033 | void netxen_watchdog_task(struct work_struct *work) |
3d396eb1 | 1034 | { |
3d396eb1 | 1035 | struct net_device *netdev; |
6d5aefb8 DH |
1036 | struct netxen_adapter *adapter = |
1037 | container_of(work, struct netxen_adapter, watchdog_task); | |
3d396eb1 | 1038 | |
6c80b18d | 1039 | if ((adapter->portnum == 0) && netxen_nic_check_temp(adapter)) |
cb8011ad AK |
1040 | return; |
1041 | ||
c27e6721 MT |
1042 | if (adapter->handle_phy_intr) |
1043 | adapter->handle_phy_intr(adapter); | |
1044 | ||
3176ff3e | 1045 | netdev = adapter->netdev; |
c27e6721 MT |
1046 | if ((netif_running(netdev)) && !netif_carrier_ok(netdev) && |
1047 | netxen_nic_link_ok(adapter) ) { | |
1048 | printk(KERN_INFO "%s %s (port %d), Link is up\n", | |
1049 | netxen_nic_driver_name, netdev->name, adapter->portnum); | |
3176ff3e | 1050 | netif_carrier_on(netdev); |
3176ff3e | 1051 | netif_wake_queue(netdev); |
c27e6721 MT |
1052 | } else if(!(netif_running(netdev)) && netif_carrier_ok(netdev)) { |
1053 | printk(KERN_ERR "%s %s Link is Down\n", | |
1054 | netxen_nic_driver_name, netdev->name); | |
1055 | netif_carrier_off(netdev); | |
1056 | netif_stop_queue(netdev); | |
1057 | } | |
3176ff3e | 1058 | |
3d396eb1 AK |
1059 | mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ); |
1060 | } | |
1061 | ||
1062 | /* | |
1063 | * netxen_process_rcv() send the received packet to the protocol stack. | |
1064 | * and if the number of receives exceeds RX_BUFFERS_REFILL, then we | |
1065 | * invoke the routine to send more rx buffers to the Phantom... | |
1066 | */ | |
1067 | void | |
1068 | netxen_process_rcv(struct netxen_adapter *adapter, int ctxid, | |
1069 | struct status_desc *desc) | |
1070 | { | |
3176ff3e MT |
1071 | struct pci_dev *pdev = adapter->pdev; |
1072 | struct net_device *netdev = adapter->netdev; | |
a608ab9c | 1073 | int index = netxen_get_sts_refhandle(desc); |
3d396eb1 AK |
1074 | struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctxid]); |
1075 | struct netxen_rx_buffer *buffer; | |
1076 | struct sk_buff *skb; | |
a608ab9c | 1077 | u32 length = netxen_get_sts_totallength(desc); |
3d396eb1 AK |
1078 | u32 desc_ctx; |
1079 | struct netxen_rcv_desc_ctx *rcv_desc; | |
1080 | int ret; | |
1081 | ||
ed25ffa1 | 1082 | desc_ctx = netxen_get_sts_type(desc); |
3d396eb1 AK |
1083 | if (unlikely(desc_ctx >= NUM_RCV_DESC_RINGS)) { |
1084 | printk("%s: %s Bad Rcv descriptor ring\n", | |
1085 | netxen_nic_driver_name, netdev->name); | |
1086 | return; | |
1087 | } | |
1088 | ||
1089 | rcv_desc = &recv_ctx->rcv_desc[desc_ctx]; | |
ed25ffa1 AK |
1090 | if (unlikely(index > rcv_desc->max_rx_desc_count)) { |
1091 | DPRINTK(ERR, "Got a buffer index:%x Max is %x\n", | |
1092 | index, rcv_desc->max_rx_desc_count); | |
1093 | return; | |
1094 | } | |
3d396eb1 | 1095 | buffer = &rcv_desc->rx_buf_arr[index]; |
ed25ffa1 AK |
1096 | if (desc_ctx == RCV_DESC_LRO_CTXID) { |
1097 | buffer->lro_current_frags++; | |
1098 | if (netxen_get_sts_desc_lro_last_frag(desc)) { | |
1099 | buffer->lro_expected_frags = | |
1100 | netxen_get_sts_desc_lro_cnt(desc); | |
1101 | buffer->lro_length = length; | |
1102 | } | |
1103 | if (buffer->lro_current_frags != buffer->lro_expected_frags) { | |
1104 | if (buffer->lro_expected_frags != 0) { | |
1105 | printk("LRO: (refhandle:%x) recv frag." | |
1106 | "wait for last. flags: %x expected:%d" | |
1107 | "have:%d\n", index, | |
1108 | netxen_get_sts_desc_lro_last_frag(desc), | |
1109 | buffer->lro_expected_frags, | |
1110 | buffer->lro_current_frags); | |
1111 | } | |
1112 | return; | |
1113 | } | |
1114 | } | |
3d396eb1 AK |
1115 | |
1116 | pci_unmap_single(pdev, buffer->dma, rcv_desc->dma_size, | |
1117 | PCI_DMA_FROMDEVICE); | |
1118 | ||
1119 | skb = (struct sk_buff *)buffer->skb; | |
1120 | ||
200eef20 DP |
1121 | if (likely(adapter->rx_csum && |
1122 | netxen_get_sts_status(desc) == STATUS_CKSUM_OK)) { | |
3176ff3e | 1123 | adapter->stats.csummed++; |
3d396eb1 | 1124 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
200eef20 DP |
1125 | } else |
1126 | skb->ip_summed = CHECKSUM_NONE; | |
1127 | ||
96acb6eb | 1128 | skb->dev = netdev; |
ed25ffa1 AK |
1129 | if (desc_ctx == RCV_DESC_LRO_CTXID) { |
1130 | /* True length was only available on the last pkt */ | |
1131 | skb_put(skb, buffer->lro_length); | |
1132 | } else { | |
1133 | skb_put(skb, length); | |
1134 | } | |
1135 | ||
3d396eb1 AK |
1136 | skb->protocol = eth_type_trans(skb, netdev); |
1137 | ||
1138 | ret = netif_receive_skb(skb); | |
1139 | ||
1140 | /* | |
1141 | * RH: Do we need these stats on a regular basis. Can we get it from | |
1142 | * Linux stats. | |
1143 | */ | |
1144 | switch (ret) { | |
1145 | case NET_RX_SUCCESS: | |
3176ff3e | 1146 | adapter->stats.uphappy++; |
3d396eb1 AK |
1147 | break; |
1148 | ||
1149 | case NET_RX_CN_LOW: | |
3176ff3e | 1150 | adapter->stats.uplcong++; |
3d396eb1 AK |
1151 | break; |
1152 | ||
1153 | case NET_RX_CN_MOD: | |
3176ff3e | 1154 | adapter->stats.upmcong++; |
3d396eb1 AK |
1155 | break; |
1156 | ||
1157 | case NET_RX_CN_HIGH: | |
3176ff3e | 1158 | adapter->stats.uphcong++; |
3d396eb1 AK |
1159 | break; |
1160 | ||
1161 | case NET_RX_DROP: | |
3176ff3e | 1162 | adapter->stats.updropped++; |
3d396eb1 AK |
1163 | break; |
1164 | ||
1165 | default: | |
3176ff3e | 1166 | adapter->stats.updunno++; |
3d396eb1 AK |
1167 | break; |
1168 | } | |
1169 | ||
1170 | netdev->last_rx = jiffies; | |
1171 | ||
1172 | rcv_desc->rcv_free++; | |
1173 | rcv_desc->rcv_pending--; | |
1174 | ||
1175 | /* | |
1176 | * We just consumed one buffer so post a buffer. | |
1177 | */ | |
3d396eb1 AK |
1178 | buffer->skb = NULL; |
1179 | buffer->state = NETXEN_BUFFER_FREE; | |
ed25ffa1 AK |
1180 | buffer->lro_current_frags = 0; |
1181 | buffer->lro_expected_frags = 0; | |
3d396eb1 | 1182 | |
3176ff3e MT |
1183 | adapter->stats.no_rcv++; |
1184 | adapter->stats.rxbytes += length; | |
3d396eb1 AK |
1185 | } |
1186 | ||
1187 | /* Process Receive status ring */ | |
1188 | u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctxid, int max) | |
1189 | { | |
1190 | struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctxid]); | |
1191 | struct status_desc *desc_head = recv_ctx->rcv_status_desc_head; | |
1192 | struct status_desc *desc; /* used to read status desc here */ | |
1193 | u32 consumer = recv_ctx->status_rx_consumer; | |
ed25ffa1 | 1194 | u32 producer = 0; |
3d396eb1 AK |
1195 | int count = 0, ring; |
1196 | ||
1197 | DPRINTK(INFO, "procesing receive\n"); | |
1198 | /* | |
1199 | * we assume in this case that there is only one port and that is | |
1200 | * port #1...changes need to be done in firmware to indicate port | |
1201 | * number as part of the descriptor. This way we will be able to get | |
1202 | * the netdev which is associated with that device. | |
1203 | */ | |
1204 | while (count < max) { | |
1205 | desc = &desc_head[consumer]; | |
a608ab9c | 1206 | if (!(netxen_get_sts_owner(desc) & STATUS_OWNER_HOST)) { |
ed25ffa1 AK |
1207 | DPRINTK(ERR, "desc %p ownedby %x\n", desc, |
1208 | netxen_get_sts_owner(desc)); | |
3d396eb1 AK |
1209 | break; |
1210 | } | |
1211 | netxen_process_rcv(adapter, ctxid, desc); | |
ed25ffa1 | 1212 | netxen_clear_sts_owner(desc); |
a608ab9c | 1213 | netxen_set_sts_owner(desc, STATUS_OWNER_PHANTOM); |
3d396eb1 AK |
1214 | consumer = (consumer + 1) & (adapter->max_rx_desc_count - 1); |
1215 | count++; | |
1216 | } | |
1217 | if (count) { | |
1218 | for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) { | |
ed25ffa1 | 1219 | netxen_post_rx_buffers_nodb(adapter, ctxid, ring); |
3d396eb1 AK |
1220 | } |
1221 | } | |
1222 | ||
1223 | /* update the consumer index in phantom */ | |
1224 | if (count) { | |
3d396eb1 | 1225 | recv_ctx->status_rx_consumer = consumer; |
ed25ffa1 | 1226 | recv_ctx->status_rx_producer = producer; |
3d396eb1 AK |
1227 | |
1228 | /* Window = 1 */ | |
1229 | writel(consumer, | |
1230 | NETXEN_CRB_NORMALIZE(adapter, | |
4a79a04e | 1231 | recv_crb_registers[adapter->portnum]. |
3d396eb1 | 1232 | crb_rcv_status_consumer)); |
96acb6eb | 1233 | wmb(); |
3d396eb1 AK |
1234 | } |
1235 | ||
1236 | return count; | |
1237 | } | |
1238 | ||
1239 | /* Process Command status ring */ | |
ed25ffa1 | 1240 | int netxen_process_cmd_ring(unsigned long data) |
3d396eb1 AK |
1241 | { |
1242 | u32 last_consumer; | |
1243 | u32 consumer; | |
1244 | struct netxen_adapter *adapter = (struct netxen_adapter *)data; | |
ed25ffa1 AK |
1245 | int count1 = 0; |
1246 | int count2 = 0; | |
3d396eb1 | 1247 | struct netxen_cmd_buffer *buffer; |
3d396eb1 AK |
1248 | struct pci_dev *pdev; |
1249 | struct netxen_skb_frag *frag; | |
1250 | u32 i; | |
1251 | struct sk_buff *skb = NULL; | |
ed25ffa1 | 1252 | int done; |
3d396eb1 AK |
1253 | |
1254 | spin_lock(&adapter->tx_lock); | |
1255 | last_consumer = adapter->last_cmd_consumer; | |
1256 | DPRINTK(INFO, "procesing xmit complete\n"); | |
1257 | /* we assume in this case that there is only one port and that is | |
1258 | * port #1...changes need to be done in firmware to indicate port | |
1259 | * number as part of the descriptor. This way we will be able to get | |
1260 | * the netdev which is associated with that device. | |
1261 | */ | |
3d396eb1 | 1262 | |
9b410117 | 1263 | consumer = le32_to_cpu(*(adapter->cmd_consumer)); |
3d396eb1 AK |
1264 | if (last_consumer == consumer) { /* Ring is empty */ |
1265 | DPRINTK(INFO, "last_consumer %d == consumer %d\n", | |
1266 | last_consumer, consumer); | |
1267 | spin_unlock(&adapter->tx_lock); | |
ed25ffa1 | 1268 | return 1; |
3d396eb1 AK |
1269 | } |
1270 | ||
1271 | adapter->proc_cmd_buf_counter++; | |
3d396eb1 AK |
1272 | /* |
1273 | * Not needed - does not seem to be used anywhere. | |
1274 | * adapter->cmd_consumer = consumer; | |
1275 | */ | |
1276 | spin_unlock(&adapter->tx_lock); | |
1277 | ||
ed25ffa1 | 1278 | while ((last_consumer != consumer) && (count1 < MAX_STATUS_HANDLE)) { |
3d396eb1 | 1279 | buffer = &adapter->cmd_buf_arr[last_consumer]; |
3176ff3e | 1280 | pdev = adapter->pdev; |
3d396eb1 AK |
1281 | frag = &buffer->frag_array[0]; |
1282 | skb = buffer->skb; | |
1283 | if (skb && (cmpxchg(&buffer->skb, skb, 0) == skb)) { | |
1284 | pci_unmap_single(pdev, frag->dma, frag->length, | |
1285 | PCI_DMA_TODEVICE); | |
96acb6eb | 1286 | frag->dma = 0ULL; |
3d396eb1 AK |
1287 | for (i = 1; i < buffer->frag_count; i++) { |
1288 | DPRINTK(INFO, "getting fragment no %d\n", i); | |
1289 | frag++; /* Get the next frag */ | |
1290 | pci_unmap_page(pdev, frag->dma, frag->length, | |
1291 | PCI_DMA_TODEVICE); | |
96acb6eb | 1292 | frag->dma = 0ULL; |
3d396eb1 AK |
1293 | } |
1294 | ||
3176ff3e | 1295 | adapter->stats.skbfreed++; |
3d396eb1 AK |
1296 | dev_kfree_skb_any(skb); |
1297 | skb = NULL; | |
1298 | } else if (adapter->proc_cmd_buf_counter == 1) { | |
3176ff3e | 1299 | adapter->stats.txnullskb++; |
3d396eb1 | 1300 | } |
3176ff3e MT |
1301 | if (unlikely(netif_queue_stopped(adapter->netdev) |
1302 | && netif_carrier_ok(adapter->netdev)) | |
1303 | && ((jiffies - adapter->netdev->trans_start) > | |
1304 | adapter->netdev->watchdog_timeo)) { | |
1305 | SCHEDULE_WORK(&adapter->tx_timeout_task); | |
3d396eb1 AK |
1306 | } |
1307 | ||
1308 | last_consumer = get_next_index(last_consumer, | |
1309 | adapter->max_tx_desc_count); | |
ed25ffa1 | 1310 | count1++; |
3d396eb1 | 1311 | } |
3d396eb1 | 1312 | |
ed25ffa1 | 1313 | count2 = 0; |
3d396eb1 AK |
1314 | spin_lock(&adapter->tx_lock); |
1315 | if ((--adapter->proc_cmd_buf_counter) == 0) { | |
1316 | adapter->last_cmd_consumer = last_consumer; | |
1317 | while ((adapter->last_cmd_consumer != consumer) | |
ed25ffa1 | 1318 | && (count2 < MAX_STATUS_HANDLE)) { |
3d396eb1 AK |
1319 | buffer = |
1320 | &adapter->cmd_buf_arr[adapter->last_cmd_consumer]; | |
ed25ffa1 | 1321 | count2++; |
3d396eb1 AK |
1322 | if (buffer->skb) |
1323 | break; | |
1324 | else | |
1325 | adapter->last_cmd_consumer = | |
1326 | get_next_index(adapter->last_cmd_consumer, | |
1327 | adapter->max_tx_desc_count); | |
1328 | } | |
1329 | } | |
ed25ffa1 | 1330 | if (count1 || count2) { |
3176ff3e MT |
1331 | if (netif_queue_stopped(adapter->netdev) |
1332 | && (adapter->flags & NETXEN_NETDEV_STATUS)) { | |
1333 | netif_wake_queue(adapter->netdev); | |
1334 | adapter->flags &= ~NETXEN_NETDEV_STATUS; | |
3d396eb1 AK |
1335 | } |
1336 | } | |
ed25ffa1 AK |
1337 | /* |
1338 | * If everything is freed up to consumer then check if the ring is full | |
1339 | * If the ring is full then check if more needs to be freed and | |
1340 | * schedule the call back again. | |
1341 | * | |
1342 | * This happens when there are 2 CPUs. One could be freeing and the | |
1343 | * other filling it. If the ring is full when we get out of here and | |
1344 | * the card has already interrupted the host then the host can miss the | |
1345 | * interrupt. | |
1346 | * | |
1347 | * There is still a possible race condition and the host could miss an | |
1348 | * interrupt. The card has to take care of this. | |
1349 | */ | |
1350 | if (adapter->last_cmd_consumer == consumer && | |
1351 | (((adapter->cmd_producer + 1) % | |
1352 | adapter->max_tx_desc_count) == adapter->last_cmd_consumer)) { | |
9b410117 | 1353 | consumer = le32_to_cpu(*(adapter->cmd_consumer)); |
ed25ffa1 AK |
1354 | } |
1355 | done = (adapter->last_cmd_consumer == consumer); | |
3d396eb1 AK |
1356 | |
1357 | spin_unlock(&adapter->tx_lock); | |
1358 | DPRINTK(INFO, "last consumer is %d in %s\n", last_consumer, | |
1359 | __FUNCTION__); | |
ed25ffa1 | 1360 | return (done); |
3d396eb1 AK |
1361 | } |
1362 | ||
1363 | /* | |
1364 | * netxen_post_rx_buffers puts buffer in the Phantom memory | |
1365 | */ | |
1366 | void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx, u32 ringid) | |
1367 | { | |
1368 | struct pci_dev *pdev = adapter->ahw.pdev; | |
1369 | struct sk_buff *skb; | |
1370 | struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctx]); | |
1371 | struct netxen_rcv_desc_ctx *rcv_desc = NULL; | |
ed25ffa1 | 1372 | uint producer; |
3d396eb1 AK |
1373 | struct rcv_desc *pdesc; |
1374 | struct netxen_rx_buffer *buffer; | |
1375 | int count = 0; | |
1376 | int index = 0; | |
ed25ffa1 AK |
1377 | netxen_ctx_msg msg = 0; |
1378 | dma_addr_t dma; | |
3d396eb1 | 1379 | |
3d396eb1 | 1380 | rcv_desc = &recv_ctx->rcv_desc[ringid]; |
3d396eb1 AK |
1381 | |
1382 | producer = rcv_desc->producer; | |
1383 | index = rcv_desc->begin_alloc; | |
1384 | buffer = &rcv_desc->rx_buf_arr[index]; | |
1385 | /* We can start writing rx descriptors into the phantom memory. */ | |
1386 | while (buffer->state == NETXEN_BUFFER_FREE) { | |
1387 | skb = dev_alloc_skb(rcv_desc->skb_size); | |
1388 | if (unlikely(!skb)) { | |
1389 | /* | |
ed25ffa1 | 1390 | * TODO |
3d396eb1 AK |
1391 | * We need to schedule the posting of buffers to the pegs. |
1392 | */ | |
1393 | rcv_desc->begin_alloc = index; | |
cb8011ad | 1394 | DPRINTK(ERR, "netxen_post_rx_buffers: " |
3d396eb1 AK |
1395 | " allocated only %d buffers\n", count); |
1396 | break; | |
1397 | } | |
ed25ffa1 AK |
1398 | |
1399 | count++; /* now there should be no failure */ | |
1400 | pdesc = &rcv_desc->desc_head[producer]; | |
1401 | ||
1402 | #if defined(XGB_DEBUG) | |
1403 | *(unsigned long *)(skb->head) = 0xc0debabe; | |
1404 | if (skb_is_nonlinear(skb)) { | |
1405 | printk("Allocated SKB @%p is nonlinear\n"); | |
1406 | } | |
1407 | #endif | |
1408 | skb_reserve(skb, 2); | |
1409 | /* This will be setup when we receive the | |
1410 | * buffer after it has been filled FSL TBD TBD | |
1411 | * skb->dev = netdev; | |
1412 | */ | |
1413 | dma = pci_map_single(pdev, skb->data, rcv_desc->dma_size, | |
1414 | PCI_DMA_FROMDEVICE); | |
ed33ebe4 | 1415 | pdesc->addr_buffer = cpu_to_le64(dma); |
ed25ffa1 AK |
1416 | buffer->skb = skb; |
1417 | buffer->state = NETXEN_BUFFER_BUSY; | |
1418 | buffer->dma = dma; | |
1419 | /* make a rcv descriptor */ | |
ed33ebe4 AK |
1420 | pdesc->reference_handle = cpu_to_le16(buffer->ref_handle); |
1421 | pdesc->buffer_length = cpu_to_le32(rcv_desc->dma_size); | |
ed25ffa1 AK |
1422 | DPRINTK(INFO, "done writing descripter\n"); |
1423 | producer = | |
1424 | get_next_index(producer, rcv_desc->max_rx_desc_count); | |
1425 | index = get_next_index(index, rcv_desc->max_rx_desc_count); | |
1426 | buffer = &rcv_desc->rx_buf_arr[index]; | |
1427 | } | |
1428 | /* if we did allocate buffers, then write the count to Phantom */ | |
1429 | if (count) { | |
1430 | rcv_desc->begin_alloc = index; | |
1431 | rcv_desc->rcv_pending += count; | |
ed25ffa1 AK |
1432 | rcv_desc->producer = producer; |
1433 | if (rcv_desc->rcv_free >= 32) { | |
1434 | rcv_desc->rcv_free = 0; | |
1435 | /* Window = 1 */ | |
1436 | writel((producer - 1) & | |
1437 | (rcv_desc->max_rx_desc_count - 1), | |
1438 | NETXEN_CRB_NORMALIZE(adapter, | |
3176ff3e MT |
1439 | recv_crb_registers[ |
1440 | adapter->portnum]. | |
ed25ffa1 AK |
1441 | rcv_desc_crb[ringid]. |
1442 | crb_rcv_producer_offset)); | |
1443 | /* | |
1444 | * Write a doorbell msg to tell phanmon of change in | |
1445 | * receive ring producer | |
1446 | */ | |
1447 | netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID); | |
1448 | netxen_set_msg_privid(msg); | |
1449 | netxen_set_msg_count(msg, | |
1450 | ((producer - | |
1451 | 1) & (rcv_desc-> | |
1452 | max_rx_desc_count - 1))); | |
3176ff3e | 1453 | netxen_set_msg_ctxid(msg, adapter->portnum); |
ed25ffa1 AK |
1454 | netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid)); |
1455 | writel(msg, | |
1456 | DB_NORMALIZE(adapter, | |
1457 | NETXEN_RCV_PRODUCER_OFFSET)); | |
96acb6eb | 1458 | wmb(); |
ed25ffa1 AK |
1459 | } |
1460 | } | |
1461 | } | |
1462 | ||
1463 | void netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter, uint32_t ctx, | |
1464 | uint32_t ringid) | |
1465 | { | |
1466 | struct pci_dev *pdev = adapter->ahw.pdev; | |
1467 | struct sk_buff *skb; | |
1468 | struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctx]); | |
1469 | struct netxen_rcv_desc_ctx *rcv_desc = NULL; | |
1470 | u32 producer; | |
1471 | struct rcv_desc *pdesc; | |
1472 | struct netxen_rx_buffer *buffer; | |
1473 | int count = 0; | |
1474 | int index = 0; | |
1475 | ||
ed25ffa1 AK |
1476 | rcv_desc = &recv_ctx->rcv_desc[ringid]; |
1477 | ||
1478 | producer = rcv_desc->producer; | |
1479 | index = rcv_desc->begin_alloc; | |
1480 | buffer = &rcv_desc->rx_buf_arr[index]; | |
1481 | /* We can start writing rx descriptors into the phantom memory. */ | |
1482 | while (buffer->state == NETXEN_BUFFER_FREE) { | |
1483 | skb = dev_alloc_skb(rcv_desc->skb_size); | |
1484 | if (unlikely(!skb)) { | |
1485 | /* | |
1486 | * We need to schedule the posting of buffers to the pegs. | |
1487 | */ | |
1488 | rcv_desc->begin_alloc = index; | |
1489 | DPRINTK(ERR, "netxen_post_rx_buffers_nodb: " | |
1490 | " allocated only %d buffers\n", count); | |
1491 | break; | |
1492 | } | |
3d396eb1 AK |
1493 | count++; /* now there should be no failure */ |
1494 | pdesc = &rcv_desc->desc_head[producer]; | |
ed25ffa1 | 1495 | skb_reserve(skb, 2); |
3d396eb1 AK |
1496 | /* |
1497 | * This will be setup when we receive the | |
1498 | * buffer after it has been filled | |
1499 | * skb->dev = netdev; | |
1500 | */ | |
1501 | buffer->skb = skb; | |
1502 | buffer->state = NETXEN_BUFFER_BUSY; | |
1503 | buffer->dma = pci_map_single(pdev, skb->data, | |
1504 | rcv_desc->dma_size, | |
1505 | PCI_DMA_FROMDEVICE); | |
ed25ffa1 | 1506 | |
3d396eb1 | 1507 | /* make a rcv descriptor */ |
ed33ebe4 | 1508 | pdesc->reference_handle = cpu_to_le16(buffer->ref_handle); |
a608ab9c | 1509 | pdesc->buffer_length = cpu_to_le32(rcv_desc->dma_size); |
3d396eb1 AK |
1510 | pdesc->addr_buffer = cpu_to_le64(buffer->dma); |
1511 | DPRINTK(INFO, "done writing descripter\n"); | |
1512 | producer = | |
1513 | get_next_index(producer, rcv_desc->max_rx_desc_count); | |
1514 | index = get_next_index(index, rcv_desc->max_rx_desc_count); | |
1515 | buffer = &rcv_desc->rx_buf_arr[index]; | |
1516 | } | |
1517 | ||
1518 | /* if we did allocate buffers, then write the count to Phantom */ | |
1519 | if (count) { | |
1520 | rcv_desc->begin_alloc = index; | |
1521 | rcv_desc->rcv_pending += count; | |
3d396eb1 AK |
1522 | rcv_desc->producer = producer; |
1523 | if (rcv_desc->rcv_free >= 32) { | |
1524 | rcv_desc->rcv_free = 0; | |
1525 | /* Window = 1 */ | |
1526 | writel((producer - 1) & | |
1527 | (rcv_desc->max_rx_desc_count - 1), | |
1528 | NETXEN_CRB_NORMALIZE(adapter, | |
3176ff3e MT |
1529 | recv_crb_registers[ |
1530 | adapter->portnum]. | |
ed25ffa1 | 1531 | rcv_desc_crb[ringid]. |
3d396eb1 AK |
1532 | crb_rcv_producer_offset)); |
1533 | wmb(); | |
1534 | } | |
1535 | } | |
1536 | } | |
1537 | ||
1538 | int netxen_nic_tx_has_work(struct netxen_adapter *adapter) | |
1539 | { | |
1540 | if (find_diff_among(adapter->last_cmd_consumer, | |
1541 | adapter->cmd_producer, | |
1542 | adapter->max_tx_desc_count) > 0) | |
1543 | return 1; | |
1544 | ||
1545 | return 0; | |
1546 | } | |
1547 | ||
3d396eb1 AK |
1548 | |
1549 | void netxen_nic_clear_stats(struct netxen_adapter *adapter) | |
1550 | { | |
3d396eb1 | 1551 | memset(&adapter->stats, 0, sizeof(adapter->stats)); |
3176ff3e | 1552 | return; |
3d396eb1 AK |
1553 | } |
1554 |