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netxen: validate unified romimage
[linux-2.6-block.git] / drivers / net / netxen / netxen_nic_init.c
CommitLineData
3d396eb1 1/*
5d242f1c 2 * Copyright (C) 2003 - 2009 NetXen, Inc.
13af7a6e 3 * Copyright (C) 2009 - QLogic Corporation.
3d396eb1 4 * All rights reserved.
80922fbc 5 *
3d396eb1
AK		 6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
80922fbc 10 *
3d396eb1
AK		 11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
80922fbc 15 *
3d396eb1
AK		 16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
19 * MA 02111-1307, USA.
80922fbc 20 *
3d396eb1 21 * The full GNU General Public License is included in this distribution
4d21fef4 22 * in the file called "COPYING".
80922fbc 23 *
3d396eb1
AK		 24 */
25
26#include <linux/netdevice.h>
27#include <linux/delay.h>
28#include "netxen_nic.h"
29#include "netxen_nic_hw.h"
3d396eb1
AK		 30
31struct crb_addr_pair {
e0e20a1a
LCMT		 32 u32 addr;
33 u32 data;
3d396eb1
AK		 34};
35
36#define NETXEN_MAX_CRB_XFORM 60
37static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
e0e20a1a 38#define NETXEN_ADDR_ERROR (0xffffffff)
3d396eb1
AK		 39
40#define crb_addr_transform(name) \
41 crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
42 NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
43
cb8011ad
AK		 44#define NETXEN_NIC_XDMA_RESET 0x8000ff
45
becf46a0 46static void
d8b100c5
DP		 47netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
48 struct nx_host_rds_ring *rds_ring);
f50330f9 49static int netxen_p3_has_mn(struct netxen_adapter *adapter);
993fb90c 50
3d396eb1
AK		 51static void crb_addr_transform_setup(void)
52{
53 crb_addr_transform(XDMA);
54 crb_addr_transform(TIMR);
55 crb_addr_transform(SRE);
56 crb_addr_transform(SQN3);
57 crb_addr_transform(SQN2);
58 crb_addr_transform(SQN1);
59 crb_addr_transform(SQN0);
60 crb_addr_transform(SQS3);
61 crb_addr_transform(SQS2);
62 crb_addr_transform(SQS1);
63 crb_addr_transform(SQS0);
64 crb_addr_transform(RPMX7);
65 crb_addr_transform(RPMX6);
66 crb_addr_transform(RPMX5);
67 crb_addr_transform(RPMX4);
68 crb_addr_transform(RPMX3);
69 crb_addr_transform(RPMX2);
70 crb_addr_transform(RPMX1);
71 crb_addr_transform(RPMX0);
72 crb_addr_transform(ROMUSB);
73 crb_addr_transform(SN);
74 crb_addr_transform(QMN);
75 crb_addr_transform(QMS);
76 crb_addr_transform(PGNI);
77 crb_addr_transform(PGND);
78 crb_addr_transform(PGN3);
79 crb_addr_transform(PGN2);
80 crb_addr_transform(PGN1);
81 crb_addr_transform(PGN0);
82 crb_addr_transform(PGSI);
83 crb_addr_transform(PGSD);
84 crb_addr_transform(PGS3);
85 crb_addr_transform(PGS2);
86 crb_addr_transform(PGS1);
87 crb_addr_transform(PGS0);
88 crb_addr_transform(PS);
89 crb_addr_transform(PH);
90 crb_addr_transform(NIU);
91 crb_addr_transform(I2Q);
92 crb_addr_transform(EG);
93 crb_addr_transform(MN);
94 crb_addr_transform(MS);
95 crb_addr_transform(CAS2);
96 crb_addr_transform(CAS1);
97 crb_addr_transform(CAS0);
98 crb_addr_transform(CAM);
99 crb_addr_transform(C2C1);
100 crb_addr_transform(C2C0);
1fcca1a5 101 crb_addr_transform(SMB);
e4c93c81
DP		 102 crb_addr_transform(OCM0);
103 crb_addr_transform(I2C0);
3d396eb1
AK		 104}
105
2956640d 106void netxen_release_rx_buffers(struct netxen_adapter *adapter)
3d396eb1 107{
2956640d 108 struct netxen_recv_context *recv_ctx;
48bfd1e0 109 struct nx_host_rds_ring *rds_ring;
2956640d 110 struct netxen_rx_buffer *rx_buf;
becf46a0
DP		 111 int i, ring;
112
113 recv_ctx = &adapter->recv_ctx;
114 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
115 rds_ring = &recv_ctx->rds_rings[ring];
438627c7 116 for (i = 0; i < rds_ring->num_desc; ++i) {
becf46a0
DP		 117 rx_buf = &(rds_ring->rx_buf_arr[i]);
118 if (rx_buf->state == NETXEN_BUFFER_FREE)
119 continue;
120 pci_unmap_single(adapter->pdev,
121 rx_buf->dma,
122 rds_ring->dma_size,
123 PCI_DMA_FROMDEVICE);
124 if (rx_buf->skb != NULL)
125 dev_kfree_skb_any(rx_buf->skb);
2956640d
DP		 126 }
127 }
128}
129
130void netxen_release_tx_buffers(struct netxen_adapter *adapter)
131{
132 struct netxen_cmd_buffer *cmd_buf;
133 struct netxen_skb_frag *buffrag;
134 int i, j;
4ea528a1 135 struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
2956640d 136
d877f1e3
DP		 137 cmd_buf = tx_ring->cmd_buf_arr;
138 for (i = 0; i < tx_ring->num_desc; i++) {
2956640d
DP		 139 buffrag = cmd_buf->frag_array;
140 if (buffrag->dma) {
141 pci_unmap_single(adapter->pdev, buffrag->dma,
142 buffrag->length, PCI_DMA_TODEVICE);
143 buffrag->dma = 0ULL;
144 }
145 for (j = 0; j < cmd_buf->frag_count; j++) {
146 buffrag++;
147 if (buffrag->dma) {
148 pci_unmap_page(adapter->pdev, buffrag->dma,
149 buffrag->length,
150 PCI_DMA_TODEVICE);
151 buffrag->dma = 0ULL;
152 }
153 }
2956640d
DP		 154 if (cmd_buf->skb) {
155 dev_kfree_skb_any(cmd_buf->skb);
156 cmd_buf->skb = NULL;
157 }
158 cmd_buf++;
159 }
160}
161
162void netxen_free_sw_resources(struct netxen_adapter *adapter)
163{
164 struct netxen_recv_context *recv_ctx;
48bfd1e0 165 struct nx_host_rds_ring *rds_ring;
d877f1e3 166 struct nx_host_tx_ring *tx_ring;
becf46a0
DP		 167 int ring;
168
169 recv_ctx = &adapter->recv_ctx;
4ea528a1
DP		 170
171 if (recv_ctx->rds_rings == NULL)
172 goto skip_rds;
173
becf46a0
DP		 174 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
175 rds_ring = &recv_ctx->rds_rings[ring];
f2333a01
F		 176 vfree(rds_ring->rx_buf_arr);
177 rds_ring->rx_buf_arr = NULL;
2956640d 178 }
4ea528a1
DP		 179 kfree(recv_ctx->rds_rings);
180
181skip_rds:
182 if (adapter->tx_ring == NULL)
183 return;
becf46a0 184
4ea528a1 185 tx_ring = adapter->tx_ring;
f2333a01 186 vfree(tx_ring->cmd_buf_arr);
011f4ea0
AKS		 187 kfree(tx_ring);
188 adapter->tx_ring = NULL;
2956640d
DP		 189}
190
191int netxen_alloc_sw_resources(struct netxen_adapter *adapter)
192{
193 struct netxen_recv_context *recv_ctx;
48bfd1e0 194 struct nx_host_rds_ring *rds_ring;
d8b100c5 195 struct nx_host_sds_ring *sds_ring;
4ea528a1 196 struct nx_host_tx_ring *tx_ring;
2956640d 197 struct netxen_rx_buffer *rx_buf;
4ea528a1 198 int ring, i, size;
2956640d
DP		 199
200 struct netxen_cmd_buffer *cmd_buf_arr;
201 struct net_device *netdev = adapter->netdev;
d877f1e3 202 struct pci_dev *pdev = adapter->pdev;
2956640d 203
4ea528a1
DP		 204 size = sizeof(struct nx_host_tx_ring);
205 tx_ring = kzalloc(size, GFP_KERNEL);
206 if (tx_ring == NULL) {
207 dev_err(&pdev->dev, "%s: failed to allocate tx ring struct\n",
208 netdev->name);
209 return -ENOMEM;
210 }
211 adapter->tx_ring = tx_ring;
212
d877f1e3 213 tx_ring->num_desc = adapter->num_txd;
b2af9cb0 214 tx_ring->txq = netdev_get_tx_queue(netdev, 0);
4ea528a1
DP		 215
216 cmd_buf_arr = vmalloc(TX_BUFF_RINGSIZE(tx_ring));
2956640d 217 if (cmd_buf_arr == NULL) {
d877f1e3 218 dev_err(&pdev->dev, "%s: failed to allocate cmd buffer ring\n",
2956640d
DP		 219 netdev->name);
220 return -ENOMEM;
221 }
d877f1e3
DP		 222 memset(cmd_buf_arr, 0, TX_BUFF_RINGSIZE(tx_ring));
223 tx_ring->cmd_buf_arr = cmd_buf_arr;
2956640d 224
becf46a0 225 recv_ctx = &adapter->recv_ctx;
4ea528a1
DP		 226
227 size = adapter->max_rds_rings * sizeof (struct nx_host_rds_ring);
228 rds_ring = kzalloc(size, GFP_KERNEL);
229 if (rds_ring == NULL) {
230 dev_err(&pdev->dev, "%s: failed to allocate rds ring struct\n",
231 netdev->name);
232 return -ENOMEM;
233 }
234 recv_ctx->rds_rings = rds_ring;
235
becf46a0
DP		 236 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
237 rds_ring = &recv_ctx->rds_rings[ring];
438627c7
DP		 238 switch (ring) {
239 case RCV_RING_NORMAL:
240 rds_ring->num_desc = adapter->num_rxd;
becf46a0
DP		 241 if (adapter->ahw.cut_through) {
242 rds_ring->dma_size =
243 NX_CT_DEFAULT_RX_BUF_LEN;
48bfd1e0 244 rds_ring->skb_size =
becf46a0
DP		 245 NX_CT_DEFAULT_RX_BUF_LEN;
246 } else {
9b08beba
DP		 247 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
248 rds_ring->dma_size =
249 NX_P3_RX_BUF_MAX_LEN;
250 else
251 rds_ring->dma_size =
252 NX_P2_RX_BUF_MAX_LEN;
becf46a0 253 rds_ring->skb_size =
9b08beba 254 rds_ring->dma_size + NET_IP_ALIGN;
becf46a0
DP		 255 }
256 break;
2956640d 257
438627c7
DP		 258 case RCV_RING_JUMBO:
259 rds_ring->num_desc = adapter->num_jumbo_rxd;
becf46a0
DP		 260 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
261 rds_ring->dma_size =
262 NX_P3_RX_JUMBO_BUF_MAX_LEN;
263 else
264 rds_ring->dma_size =
265 NX_P2_RX_JUMBO_BUF_MAX_LEN;
bc75e5bf
DP		 266
267 if (adapter->capabilities & NX_CAP0_HW_LRO)
268 rds_ring->dma_size += NX_LRO_BUFFER_EXTRA;
269
becf46a0
DP		 270 rds_ring->skb_size =
271 rds_ring->dma_size + NET_IP_ALIGN;
272 break;
2956640d 273
becf46a0 274 case RCV_RING_LRO:
438627c7 275 rds_ring->num_desc = adapter->num_lro_rxd;
9b08beba
DP		 276 rds_ring->dma_size = NX_RX_LRO_BUFFER_LENGTH;
277 rds_ring->skb_size = rds_ring->dma_size + NET_IP_ALIGN;
becf46a0
DP		 278 break;
279
280 }
281 rds_ring->rx_buf_arr = (struct netxen_rx_buffer *)
d8b100c5 282 vmalloc(RCV_BUFF_RINGSIZE(rds_ring));
becf46a0
DP		 283 if (rds_ring->rx_buf_arr == NULL) {
284 printk(KERN_ERR "%s: Failed to allocate "
285 "rx buffer ring %d\n",
286 netdev->name, ring);
287 /* free whatever was already allocated */
288 goto err_out;
289 }
d8b100c5 290 memset(rds_ring->rx_buf_arr, 0, RCV_BUFF_RINGSIZE(rds_ring));
becf46a0
DP		 291 INIT_LIST_HEAD(&rds_ring->free_list);
292 /*
293 * Now go through all of them, set reference handles
294 * and put them in the queues.
295 */
becf46a0 296 rx_buf = rds_ring->rx_buf_arr;
4ea528a1 297 for (i = 0; i < rds_ring->num_desc; i++) {
becf46a0
DP		 298 list_add_tail(&rx_buf->list,
299 &rds_ring->free_list);
300 rx_buf->ref_handle = i;
301 rx_buf->state = NETXEN_BUFFER_FREE;
302 rx_buf++;
3d396eb1 303 }
d8b100c5
DP		 304 spin_lock_init(&rds_ring->lock);
305 }
306
307 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
308 sds_ring = &recv_ctx->sds_rings[ring];
309 sds_ring->irq = adapter->msix_entries[ring].vector;
d8b100c5
DP		 310 sds_ring->adapter = adapter;
311 sds_ring->num_desc = adapter->num_rxd;
312
313 for (i = 0; i < NUM_RCV_DESC_RINGS; i++)
314 INIT_LIST_HEAD(&sds_ring->free_list[i]);
3d396eb1 315 }
2956640d
DP		 316
317 return 0;
318
319err_out:
320 netxen_free_sw_resources(adapter);
321 return -ENOMEM;
3d396eb1
AK		 322}
323
3d396eb1
AK		 324/*
325 * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
326 * address to external PCI CRB address.
327 */
993fb90c 328static u32 netxen_decode_crb_addr(u32 addr)
3d396eb1
AK		 329{
330 int i;
e0e20a1a 331 u32 base_addr, offset, pci_base;
3d396eb1
AK		 332
333 crb_addr_transform_setup();
334
335 pci_base = NETXEN_ADDR_ERROR;
336 base_addr = addr & 0xfff00000;
337 offset = addr & 0x000fffff;
338
339 for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
340 if (crb_addr_xform[i] == base_addr) {
341 pci_base = i << 20;
342 break;
343 }
344 }
345 if (pci_base == NETXEN_ADDR_ERROR)
346 return pci_base;
347 else
348 return (pci_base + offset);
349}
350
c9517e58 351#define NETXEN_MAX_ROM_WAIT_USEC 100
3d396eb1 352
993fb90c 353static int netxen_wait_rom_done(struct netxen_adapter *adapter)
3d396eb1
AK		 354{
355 long timeout = 0;
356 long done = 0;
357
27c915a4
DP		 358 cond_resched();
359
3d396eb1 360 while (done == 0) {
f98a9f69 361 done = NXRD32(adapter, NETXEN_ROMUSB_GLB_STATUS);
3d396eb1 362 done &= 2;
c9517e58
DP		 363 if (++timeout >= NETXEN_MAX_ROM_WAIT_USEC) {
364 dev_err(&adapter->pdev->dev,
365 "Timeout reached waiting for rom done");
3d396eb1
AK		 366 return -EIO;
367 }
c9517e58 368 udelay(1);
3d396eb1
AK		 369 }
370 return 0;
371}
372
993fb90c
AB		 373static int do_rom_fast_read(struct netxen_adapter *adapter,
374 int addr, int *valp)
3d396eb1 375{
f98a9f69
DP		 376 NXWR32(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
377 NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
378 NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
379 NXWR32(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
3d396eb1
AK		 380 if (netxen_wait_rom_done(adapter)) {
381 printk("Error waiting for rom done\n");
382 return -EIO;
383 }
384 /* reset abyte_cnt and dummy_byte_cnt */
f98a9f69 385 NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
27c915a4 386 udelay(10);
f98a9f69 387 NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
3d396eb1 388
f98a9f69 389 *valp = NXRD32(adapter, NETXEN_ROMUSB_ROM_RDATA);
3d396eb1
AK		 390 return 0;
391}
392
993fb90c
AB		 393static int do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
394 u8 *bytes, size_t size)
27d2ab54
AK		 395{
396 int addridx;
397 int ret = 0;
398
399 for (addridx = addr; addridx < (addr + size); addridx += 4) {
f305f789
AV		 400 int v;
401 ret = do_rom_fast_read(adapter, addridx, &v);
27d2ab54
AK		 402 if (ret != 0)
403 break;
f305f789 404 *(__le32 *)bytes = cpu_to_le32(v);
27d2ab54
AK		 405 bytes += 4;
406 }
407
408 return ret;
409}
410
411int
4790654c 412netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
27d2ab54
AK		 413 u8 *bytes, size_t size)
414{
415 int ret;
416
c9517e58 417 ret = netxen_rom_lock(adapter);
27d2ab54
AK		 418 if (ret < 0)
419 return ret;
420
421 ret = do_rom_fast_read_words(adapter, addr, bytes, size);
422
423 netxen_rom_unlock(adapter);
424 return ret;
425}
426
3d396eb1
AK		 427int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
428{
429 int ret;
430
c9517e58 431 if (netxen_rom_lock(adapter) != 0)
3d396eb1
AK		 432 return -EIO;
433
434 ret = do_rom_fast_read(adapter, addr, valp);
cb8011ad
AK		 435 netxen_rom_unlock(adapter);
436 return ret;
437}
438
3d396eb1
AK		 439#define NETXEN_BOARDTYPE 0x4008
440#define NETXEN_BOARDNUM 0x400c
441#define NETXEN_CHIPNUM 0x4010
3d396eb1 442
0be367bd 443int netxen_pinit_from_rom(struct netxen_adapter *adapter)
3d396eb1 444{
dcd56fdb 445 int addr, val;
27c915a4 446 int i, n, init_delay = 0;
3d396eb1 447 struct crb_addr_pair *buf;
27c915a4 448 unsigned offset;
e0e20a1a 449 u32 off;
3d396eb1
AK		 450
451 /* resetall */
c9517e58 452 netxen_rom_lock(adapter);
f98a9f69 453 NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0xffffffff);
27c915a4 454 netxen_rom_unlock(adapter);
3d396eb1 455
2956640d
DP		 456 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
457 if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
27c915a4 458 (n != 0xcafecafe) ||
2956640d
DP		 459 netxen_rom_fast_read(adapter, 4, &n) != 0) {
460 printk(KERN_ERR "%s: ERROR Reading crb_init area: "
461 "n: %08x\n", netxen_nic_driver_name, n);
3d396eb1
AK		 462 return -EIO;
463 }
2956640d
DP		 464 offset = n & 0xffffU;
465 n = (n >> 16) & 0xffffU;
466 } else {
467 if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
468 !(n & 0x80000000)) {
469 printk(KERN_ERR "%s: ERROR Reading crb_init area: "
470 "n: %08x\n", netxen_nic_driver_name, n);
471 return -EIO;
3d396eb1 472 }
2956640d
DP		 473 offset = 1;
474 n &= ~0x80000000;
475 }
476
0be367bd 477 if (n >= 1024) {
2956640d
DP		 478 printk(KERN_ERR "%s:n=0x%x Error! NetXen card flash not"
479 " initialized.\n", __func__, n);
480 return -EIO;
481 }
3d396eb1 482
2956640d
DP		 483 buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
484 if (buf == NULL) {
485 printk("%s: netxen_pinit_from_rom: Unable to calloc memory.\n",
486 netxen_nic_driver_name);
487 return -ENOMEM;
488 }
0be367bd 489
2956640d
DP		 490 for (i = 0; i < n; i++) {
491 if (netxen_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 ||
584dbe94
DM		 492 netxen_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0) {
493 kfree(buf);
2956640d 494 return -EIO;
584dbe94 495 }
2956640d
DP		 496
497 buf[i].addr = addr;
498 buf[i].data = val;
499
2956640d 500 }
0be367bd 501
2956640d
DP		 502 for (i = 0; i < n; i++) {
503
504 off = netxen_decode_crb_addr(buf[i].addr);
505 if (off == NETXEN_ADDR_ERROR) {
506 printk(KERN_ERR"CRB init value out of range %x\n",
1fcca1a5 507 buf[i].addr);
2956640d
DP		 508 continue;
509 }
510 off += NETXEN_PCI_CRBSPACE;
0be367bd
AKS		 511
512 if (off & 1)
513 continue;
514
2956640d
DP		 515 /* skipping cold reboot MAGIC */
516 if (off == NETXEN_CAM_RAM(0x1fc))
517 continue;
518
519 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
8bee0a91
DP		 520 if (off == (NETXEN_CRB_I2C0 + 0x1c))
521 continue;
2956640d
DP		 522 /* do not reset PCI */
523 if (off == (ROMUSB_GLB + 0xbc))
1fcca1a5 524 continue;
27c915a4
DP		 525 if (off == (ROMUSB_GLB + 0xa8))
526 continue;
527 if (off == (ROMUSB_GLB + 0xc8)) /* core clock */
528 continue;
529 if (off == (ROMUSB_GLB + 0x24)) /* MN clock */
530 continue;
531 if (off == (ROMUSB_GLB + 0x1c)) /* MS clock */
532 continue;
e7473f12
AKS		 533 if ((off & 0x0ff00000) == NETXEN_CRB_DDR_NET)
534 continue;
0be367bd
AKS		 535 if (off == (NETXEN_CRB_PEG_NET_1 + 0x18) &&
536 !NX_IS_REVISION_P3P(adapter->ahw.revision_id))
2956640d
DP		 537 buf[i].data = 0x1020;
538 /* skip the function enable register */
539 if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION))
3d396eb1 540 continue;
2956640d
DP		 541 if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION2))
542 continue;
543 if ((off & 0x0ff00000) == NETXEN_CRB_SMB)
544 continue;
545 }
3d396eb1 546
27c915a4 547 init_delay = 1;
2956640d
DP		 548 /* After writing this register, HW needs time for CRB */
549 /* to quiet down (else crb_window returns 0xffffffff) */
550 if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
27c915a4 551 init_delay = 1000;
2956640d 552 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
3d396eb1 553 /* hold xdma in reset also */
cb8011ad 554 buf[i].data = NETXEN_NIC_XDMA_RESET;
27c915a4 555 buf[i].data = 0x8000ff;
3d396eb1 556 }
2956640d 557 }
3d396eb1 558
f98a9f69 559 NXWR32(adapter, off, buf[i].data);
3d396eb1 560
27c915a4 561 msleep(init_delay);
2956640d
DP		 562 }
563 kfree(buf);
3d396eb1 564
2956640d 565 /* disable_peg_cache_all */
3d396eb1 566
2956640d
DP		 567 /* unreset_net_cache */
568 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
f98a9f69
DP		 569 val = NXRD32(adapter, NETXEN_ROMUSB_GLB_SW_RESET);
570 NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f));
3d396eb1 571 }
2956640d
DP		 572
573 /* p2dn replyCount */
f98a9f69 574 NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
2956640d 575 /* disable_peg_cache 0 */
f98a9f69 576 NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8);
2956640d 577 /* disable_peg_cache 1 */
f98a9f69 578 NXWR32(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8);
2956640d
DP		 579
580 /* peg_clr_all */
581
582 /* peg_clr 0 */
f98a9f69
DP		 583 NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0);
584 NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0);
2956640d 585 /* peg_clr 1 */
f98a9f69
DP		 586 NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0);
587 NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0);
2956640d 588 /* peg_clr 2 */
f98a9f69
DP		 589 NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0);
590 NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0);
2956640d 591 /* peg_clr 3 */
f98a9f69
DP		 592 NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0);
593 NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0);
3d396eb1
AK		 594 return 0;
595}
596
f50330f9
AKS		 597static struct uni_table_desc *nx_get_table_desc(const u8 *unirom, int section)
598{
599 uint32_t i;
600 struct uni_table_desc *directory = (struct uni_table_desc *) &unirom[0];
601 __le32 entries = cpu_to_le32(directory->num_entries);
602
603 for (i = 0; i < entries; i++) {
604
605 __le32 offs = cpu_to_le32(directory->findex) +
606 (i * cpu_to_le32(directory->entry_size));
607 __le32 tab_type = cpu_to_le32(*((u32 *)&unirom[offs] + 8));
608
609 if (tab_type == section)
610 return (struct uni_table_desc *) &unirom[offs];
611 }
612
613 return NULL;
614}
615
10c0f2a8
RB		 616#define QLCNIC_FILEHEADER_SIZE (14 * 4)
617
f50330f9 618static int
10c0f2a8
RB		 619netxen_nic_validate_header(struct netxen_adapter *adapter)
620 {
f50330f9 621 const u8 *unirom = adapter->fw->data;
10c0f2a8
RB		 622 struct uni_table_desc *directory = (struct uni_table_desc *) &unirom[0];
623 u32 fw_file_size = adapter->fw->size;
624 u32 tab_size;
f50330f9 625 __le32 entries;
10c0f2a8
RB		 626 __le32 entry_size;
627
628 if (fw_file_size < QLCNIC_FILEHEADER_SIZE)
629 return -EINVAL;
630
631 entries = cpu_to_le32(directory->num_entries);
632 entry_size = cpu_to_le32(directory->entry_size);
633 tab_size = cpu_to_le32(directory->findex) + (entries * entry_size);
634
635 if (fw_file_size < tab_size)
636 return -EINVAL;
637
638 return 0;
639}
640
641static int
642netxen_nic_validate_bootld(struct netxen_adapter *adapter)
643{
644 struct uni_table_desc *tab_desc;
645 struct uni_data_desc *descr;
646 const u8 *unirom = adapter->fw->data;
647 __le32 idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
648 NX_UNI_BOOTLD_IDX_OFF));
649 u32 offs;
650 u32 tab_size;
651 u32 data_size;
652
653 tab_desc = nx_get_table_desc(unirom, NX_UNI_DIR_SECT_BOOTLD);
654
655 if (!tab_desc)
656 return -EINVAL;
657
658 tab_size = cpu_to_le32(tab_desc->findex) +
659 (cpu_to_le32(tab_desc->entry_size) * (idx + 1));
660
661 if (adapter->fw->size < tab_size)
662 return -EINVAL;
663
664 offs = cpu_to_le32(tab_desc->findex) +
665 (cpu_to_le32(tab_desc->entry_size) * (idx));
666 descr = (struct uni_data_desc *)&unirom[offs];
667
668 data_size = cpu_to_le32(descr->findex) + cpu_to_le32(descr->size);
669
670 if (adapter->fw->size < data_size)
671 return -EINVAL;
672
673 return 0;
674}
675
676static int
677netxen_nic_validate_fw(struct netxen_adapter *adapter)
678{
679 struct uni_table_desc *tab_desc;
680 struct uni_data_desc *descr;
681 const u8 *unirom = adapter->fw->data;
682 __le32 idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
683 NX_UNI_FIRMWARE_IDX_OFF));
684 u32 offs;
685 u32 tab_size;
686 u32 data_size;
687
688 tab_desc = nx_get_table_desc(unirom, NX_UNI_DIR_SECT_FW);
689
690 if (!tab_desc)
691 return -EINVAL;
f50330f9 692
10c0f2a8
RB		 693 tab_size = cpu_to_le32(tab_desc->findex) +
694 (cpu_to_le32(tab_desc->entry_size) * (idx + 1));
695
696 if (adapter->fw->size < tab_size)
697 return -EINVAL;
698
699 offs = cpu_to_le32(tab_desc->findex) +
700 (cpu_to_le32(tab_desc->entry_size) * (idx));
701 descr = (struct uni_data_desc *)&unirom[offs];
702 data_size = cpu_to_le32(descr->findex) + cpu_to_le32(descr->size);
703
704 if (adapter->fw->size < data_size)
705 return -EINVAL;
706
707 return 0;
708}
709
710
711static int
712netxen_nic_validate_product_offs(struct netxen_adapter *adapter)
713{
714 struct uni_table_desc *ptab_descr;
715 const u8 *unirom = adapter->fw->data;
634d7df8
DP		 716 int mn_present = (NX_IS_REVISION_P2(adapter->ahw.revision_id)) ?
717 1 : netxen_p3_has_mn(adapter);
10c0f2a8
RB		 718 __le32 entries;
719 __le32 entry_size;
720 u32 tab_size;
721 u32 i;
634d7df8 722
f50330f9
AKS		 723 ptab_descr = nx_get_table_desc(unirom, NX_UNI_DIR_SECT_PRODUCT_TBL);
724 if (ptab_descr == NULL)
10c0f2a8 725 return -EINVAL;
f50330f9
AKS		 726
727 entries = cpu_to_le32(ptab_descr->num_entries);
10c0f2a8
RB		 728 entry_size = cpu_to_le32(ptab_descr->entry_size);
729 tab_size = cpu_to_le32(ptab_descr->findex) + (entries * entry_size);
730
731 if (adapter->fw->size < tab_size)
732 return -EINVAL;
f50330f9 733
634d7df8 734nomn:
f50330f9
AKS		 735 for (i = 0; i < entries; i++) {
736
737 __le32 flags, file_chiprev, offs;
738 u8 chiprev = adapter->ahw.revision_id;
f50330f9
AKS		 739 uint32_t flagbit;
740
741 offs = cpu_to_le32(ptab_descr->findex) +
742 (i * cpu_to_le32(ptab_descr->entry_size));
743 flags = cpu_to_le32(*((int *)&unirom[offs] + NX_UNI_FLAGS_OFF));
744 file_chiprev = cpu_to_le32(*((int *)&unirom[offs] +
745 NX_UNI_CHIP_REV_OFF));
746
747 flagbit = mn_present ? 1 : 2;
748
749 if ((chiprev == file_chiprev) &&
750 ((1ULL << flagbit) & flags)) {
751 adapter->file_prd_off = offs;
752 return 0;
753 }
754 }
755
634d7df8
DP		 756 if (mn_present && NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
757 mn_present = 0;
758 goto nomn;
759 }
760
10c0f2a8 761 return -EINVAL;
f50330f9
AKS		 762}
763
10c0f2a8
RB		 764static int
765netxen_nic_validate_unified_romimage(struct netxen_adapter *adapter)
766{
767 if (netxen_nic_validate_header(adapter)) {
768 dev_err(&adapter->pdev->dev,
769 "unified image: header validation failed\n");
770 return -EINVAL;
771 }
772
773 if (netxen_nic_validate_product_offs(adapter)) {
774 dev_err(&adapter->pdev->dev,
775 "unified image: product validation failed\n");
776 return -EINVAL;
777 }
778
779 if (netxen_nic_validate_bootld(adapter)) {
780 dev_err(&adapter->pdev->dev,
781 "unified image: bootld validation failed\n");
782 return -EINVAL;
783 }
784
785 if (netxen_nic_validate_fw(adapter)) {
786 dev_err(&adapter->pdev->dev,
787 "unified image: firmware validation failed\n");
788 return -EINVAL;
789 }
790
791 return 0;
792}
f50330f9
AKS		 793
794static struct uni_data_desc *nx_get_data_desc(struct netxen_adapter *adapter,
795 u32 section, u32 idx_offset)
796{
797 const u8 *unirom = adapter->fw->data;
798 int idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
799 idx_offset));
800 struct uni_table_desc *tab_desc;
801 __le32 offs;
802
803 tab_desc = nx_get_table_desc(unirom, section);
804
805 if (tab_desc == NULL)
806 return NULL;
807
808 offs = cpu_to_le32(tab_desc->findex) +
809 (cpu_to_le32(tab_desc->entry_size) * idx);
810
811 return (struct uni_data_desc *)&unirom[offs];
812}
813
814static u8 *
815nx_get_bootld_offs(struct netxen_adapter *adapter)
816{
817 u32 offs = NETXEN_BOOTLD_START;
818
819 if (adapter->fw_type == NX_UNIFIED_ROMIMAGE)
820 offs = cpu_to_le32((nx_get_data_desc(adapter,
821 NX_UNI_DIR_SECT_BOOTLD,
822 NX_UNI_BOOTLD_IDX_OFF))->findex);
823
824 return (u8 *)&adapter->fw->data[offs];
825}
826
827static u8 *
828nx_get_fw_offs(struct netxen_adapter *adapter)
829{
830 u32 offs = NETXEN_IMAGE_START;
831
832 if (adapter->fw_type == NX_UNIFIED_ROMIMAGE)
833 offs = cpu_to_le32((nx_get_data_desc(adapter,
834 NX_UNI_DIR_SECT_FW,
835 NX_UNI_FIRMWARE_IDX_OFF))->findex);
836
837 return (u8 *)&adapter->fw->data[offs];
838}
839
840static __le32
841nx_get_fw_size(struct netxen_adapter *adapter)
842{
843 if (adapter->fw_type == NX_UNIFIED_ROMIMAGE)
844 return cpu_to_le32((nx_get_data_desc(adapter,
845 NX_UNI_DIR_SECT_FW,
846 NX_UNI_FIRMWARE_IDX_OFF))->size);
847 else
848 return cpu_to_le32(
849 *(u32 *)&adapter->fw->data[NX_FW_SIZE_OFFSET]);
850}
851
852static __le32
853nx_get_fw_version(struct netxen_adapter *adapter)
854{
855 struct uni_data_desc *fw_data_desc;
856 const struct firmware *fw = adapter->fw;
857 __le32 major, minor, sub;
858 const u8 *ver_str;
859 int i, ret = 0;
860
861 if (adapter->fw_type == NX_UNIFIED_ROMIMAGE) {
862
863 fw_data_desc = nx_get_data_desc(adapter,
864 NX_UNI_DIR_SECT_FW, NX_UNI_FIRMWARE_IDX_OFF);
865 ver_str = fw->data + cpu_to_le32(fw_data_desc->findex) +
866 cpu_to_le32(fw_data_desc->size) - 17;
867
868 for (i = 0; i < 12; i++) {
869 if (!strncmp(&ver_str[i], "REV=", 4)) {
870 ret = sscanf(&ver_str[i+4], "%u.%u.%u ",
871 &major, &minor, &sub);
872 break;
873 }
874 }
875
876 if (ret != 3)
877 return 0;
878
879 return major + (minor << 8) + (sub << 16);
880
881 } else
882 return cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]);
883}
884
885static __le32
886nx_get_bios_version(struct netxen_adapter *adapter)
887{
888 const struct firmware *fw = adapter->fw;
889 __le32 bios_ver, prd_off = adapter->file_prd_off;
890
891 if (adapter->fw_type == NX_UNIFIED_ROMIMAGE) {
892 bios_ver = cpu_to_le32(*((u32 *) (&fw->data[prd_off])
893 + NX_UNI_BIOS_VERSION_OFF));
894 return (bios_ver << 24) + ((bios_ver >> 8) & 0xff00) +
895 (bios_ver >> 24);
896 } else
897 return cpu_to_le32(*(u32 *)&fw->data[NX_BIOS_VERSION_OFFSET]);
898
899}
900
67c38fc6
DP		 901int
902netxen_need_fw_reset(struct netxen_adapter *adapter)
903{
904 u32 count, old_count;
905 u32 val, version, major, minor, build;
906 int i, timeout;
907 u8 fw_type;
908
909 /* NX2031 firmware doesn't support heartbit */
910 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
911 return 1;
912
6a808c6c
AKS		 913 if (adapter->need_fw_reset)
914 return 1;
915
67c38fc6
DP		 916 /* last attempt had failed */
917 if (NXRD32(adapter, CRB_CMDPEG_STATE) == PHAN_INITIALIZE_FAILED)
918 return 1;
919
581e8ae4 920 old_count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
67c38fc6
DP		 921
922 for (i = 0; i < 10; i++) {
923
924 timeout = msleep_interruptible(200);
925 if (timeout) {
926 NXWR32(adapter, CRB_CMDPEG_STATE,
927 PHAN_INITIALIZE_FAILED);
928 return -EINTR;
929 }
930
931 count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
932 if (count != old_count)
933 break;
934 }
935
936 /* firmware is dead */
937 if (count == old_count)
938 return 1;
939
940 /* check if we have got newer or different file firmware */
941 if (adapter->fw) {
942
f50330f9 943 val = nx_get_fw_version(adapter);
67c38fc6 944
67c38fc6
DP		 945 version = NETXEN_DECODE_VERSION(val);
946
947 major = NXRD32(adapter, NETXEN_FW_VERSION_MAJOR);
948 minor = NXRD32(adapter, NETXEN_FW_VERSION_MINOR);
949 build = NXRD32(adapter, NETXEN_FW_VERSION_SUB);
950
951 if (version > NETXEN_VERSION_CODE(major, minor, build))
952 return 1;
953
f50330f9
AKS		 954 if (version == NETXEN_VERSION_CODE(major, minor, build) &&
955 adapter->fw_type != NX_UNIFIED_ROMIMAGE) {
67c38fc6
DP		 956
957 val = NXRD32(adapter, NETXEN_MIU_MN_CONTROL);
958 fw_type = (val & 0x4) ?
959 NX_P3_CT_ROMIMAGE : NX_P3_MN_ROMIMAGE;
960
961 if (adapter->fw_type != fw_type)
962 return 1;
963 }
964 }
965
966 return 0;
967}
968
969static char *fw_name[] = {
7e8e5d97
DP		 970 NX_P2_MN_ROMIMAGE_NAME,
971 NX_P3_CT_ROMIMAGE_NAME,
972 NX_P3_MN_ROMIMAGE_NAME,
973 NX_UNIFIED_ROMIMAGE_NAME,
974 NX_FLASH_ROMIMAGE_NAME,
67c38fc6
DP		 975};
976
f7185c71
DP		 977int
978netxen_load_firmware(struct netxen_adapter *adapter)
979{
980 u64 *ptr64;
981 u32 i, flashaddr, size;
982 const struct firmware *fw = adapter->fw;
67c38fc6
DP		 983 struct pci_dev *pdev = adapter->pdev;
984
985 dev_info(&pdev->dev, "loading firmware from %s\n",
986 fw_name[adapter->fw_type]);
f7185c71
DP		 987
988 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
989 NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 1);
990
991 if (fw) {
992 __le64 data;
993
994 size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
995
f50330f9 996 ptr64 = (u64 *)nx_get_bootld_offs(adapter);
f7185c71
DP		 997 flashaddr = NETXEN_BOOTLD_START;
998
999 for (i = 0; i < size; i++) {
1000 data = cpu_to_le64(ptr64[i]);
f50330f9
AKS		 1001
1002 if (adapter->pci_mem_write(adapter, flashaddr, data))
1f5e055d
AKS		 1003 return -EIO;
1004
f7185c71
DP		 1005 flashaddr += 8;
1006 }
1007
f50330f9 1008 size = (__force u32)nx_get_fw_size(adapter) / 8;
f7185c71 1009
f50330f9 1010 ptr64 = (u64 *)nx_get_fw_offs(adapter);
f7185c71
DP		 1011 flashaddr = NETXEN_IMAGE_START;
1012
1013 for (i = 0; i < size; i++) {
1014 data = cpu_to_le64(ptr64[i]);
1015
1016 if (adapter->pci_mem_write(adapter,
1f5e055d 1017 flashaddr, data))
f7185c71
DP		 1018 return -EIO;
1019
1020 flashaddr += 8;
1021 }
1022 } else {
f78c0850
AKS		 1023 u64 data;
1024 u32 hi, lo;
f7185c71 1025
f78c0850 1026 size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
f7185c71
DP		 1027 flashaddr = NETXEN_BOOTLD_START;
1028
1029 for (i = 0; i < size; i++) {
1030 if (netxen_rom_fast_read(adapter,
1f5e055d 1031 flashaddr, (int *)&lo) != 0)
f78c0850
AKS		 1032 return -EIO;
1033 if (netxen_rom_fast_read(adapter,
1f5e055d 1034 flashaddr + 4, (int *)&hi) != 0)
f7185c71
DP		 1035 return -EIO;
1036
f78c0850
AKS		 1037 /* hi, lo are already in host endian byteorder */
1038 data = (((u64)hi << 32) | lo);
1039
f7185c71 1040 if (adapter->pci_mem_write(adapter,
1f5e055d 1041 flashaddr, data))
f7185c71
DP		 1042 return -EIO;
1043
f78c0850 1044 flashaddr += 8;
f7185c71
DP		 1045 }
1046 }
1047 msleep(1);
1048
0be367bd
AKS		 1049 if (NX_IS_REVISION_P3P(adapter->ahw.revision_id)) {
1050 NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x18, 0x1020);
1051 NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001e);
1052 } else if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
f7185c71
DP		 1053 NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d);
1054 else {
1055 NXWR32(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff);
1056 NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 0);
1057 }
1058
1059 return 0;
1060}
1061
1062static int
f50330f9 1063netxen_validate_firmware(struct netxen_adapter *adapter)
f7185c71
DP		 1064{
1065 __le32 val;
10c0f2a8 1066 u32 ver, min_ver, bios;
f7185c71
DP		 1067 struct pci_dev *pdev = adapter->pdev;
1068 const struct firmware *fw = adapter->fw;
f50330f9 1069 u8 fw_type = adapter->fw_type;
f7185c71 1070
f50330f9 1071 if (fw_type == NX_UNIFIED_ROMIMAGE) {
10c0f2a8 1072 if (netxen_nic_validate_unified_romimage(adapter))
f50330f9 1073 return -EINVAL;
f50330f9
AKS		 1074 } else {
1075 val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_MAGIC_OFFSET]);
1076 if ((__force u32)val != NETXEN_BDINFO_MAGIC)
1077 return -EINVAL;
f7185c71 1078
10c0f2a8
RB		 1079 if (fw->size < NX_FW_MIN_SIZE)
1080 return -EINVAL;
f50330f9
AKS		 1081 }
1082
f50330f9 1083 val = nx_get_fw_version(adapter);
f7185c71
DP		 1084
1085 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
1086 min_ver = NETXEN_VERSION_CODE(4, 0, 216);
1087 else
1088 min_ver = NETXEN_VERSION_CODE(3, 4, 216);
1089
98e31bb0 1090 ver = NETXEN_DECODE_VERSION(val);
f7185c71 1091
98e31bb0 1092 if ((_major(ver) > _NETXEN_NIC_LINUX_MAJOR) || (ver < min_ver)) {
f7185c71
DP		 1093 dev_err(&pdev->dev,
1094 "%s: firmware version %d.%d.%d unsupported\n",
f50330f9 1095 fw_name[fw_type], _major(ver), _minor(ver), _build(ver));
f7185c71
DP		 1096 return -EINVAL;
1097 }
1098
f50330f9 1099 val = nx_get_bios_version(adapter);
f7185c71
DP		 1100 netxen_rom_fast_read(adapter, NX_BIOS_VERSION_OFFSET, (int *)&bios);
1101 if ((__force u32)val != bios) {
1102 dev_err(&pdev->dev, "%s: firmware bios is incompatible\n",
f50330f9 1103 fw_name[fw_type]);
f7185c71
DP		 1104 return -EINVAL;
1105 }
1106
1107 /* check if flashed firmware is newer */
1108 if (netxen_rom_fast_read(adapter,
1109 NX_FW_VERSION_OFFSET, (int *)&val))
1110 return -EIO;
98e31bb0
DP		 1111 val = NETXEN_DECODE_VERSION(val);
1112 if (val > ver) {
1113 dev_info(&pdev->dev, "%s: firmware is older than flash\n",
f50330f9 1114 fw_name[fw_type]);
f7185c71 1115 return -EINVAL;
98e31bb0 1116 }
f7185c71
DP		 1117
1118 NXWR32(adapter, NETXEN_CAM_RAM(0x1fc), NETXEN_BDINFO_MAGIC);
1119 return 0;
1120}
1121
f50330f9
AKS		 1122static void
1123nx_get_next_fwtype(struct netxen_adapter *adapter)
1124{
1125 u8 fw_type;
1126
1127 switch (adapter->fw_type) {
1128 case NX_UNKNOWN_ROMIMAGE:
1129 fw_type = NX_UNIFIED_ROMIMAGE;
1130 break;
1131
1132 case NX_UNIFIED_ROMIMAGE:
1133 if (NX_IS_REVISION_P3P(adapter->ahw.revision_id))
1134 fw_type = NX_FLASH_ROMIMAGE;
1135 else if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1136 fw_type = NX_P2_MN_ROMIMAGE;
1137 else if (netxen_p3_has_mn(adapter))
1138 fw_type = NX_P3_MN_ROMIMAGE;
1139 else
1140 fw_type = NX_P3_CT_ROMIMAGE;
1141 break;
1142
1143 case NX_P3_MN_ROMIMAGE:
1144 fw_type = NX_P3_CT_ROMIMAGE;
1145 break;
1146
1147 case NX_P2_MN_ROMIMAGE:
1148 case NX_P3_CT_ROMIMAGE:
1149 default:
1150 fw_type = NX_FLASH_ROMIMAGE;
1151 break;
1152 }
1153
1154 adapter->fw_type = fw_type;
1155}
1156
6598b169
DP		 1157static int
1158netxen_p3_has_mn(struct netxen_adapter *adapter)
f7185c71
DP		 1159{
1160 u32 capability, flashed_ver;
f7185c71
DP		 1161 capability = 0;
1162
634d7df8
DP		 1163 /* NX2031 always had MN */
1164 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1165 return 1;
1166
f7185c71
DP		 1167 netxen_rom_fast_read(adapter,
1168 NX_FW_VERSION_OFFSET, (int *)&flashed_ver);
98e31bb0
DP		 1169 flashed_ver = NETXEN_DECODE_VERSION(flashed_ver);
1170
f7185c71 1171 if (flashed_ver >= NETXEN_VERSION_CODE(4, 0, 220)) {
6598b169 1172
f7185c71 1173 capability = NXRD32(adapter, NX_PEG_TUNE_CAPABILITY);
6598b169
DP		 1174 if (capability & NX_PEG_TUNE_MN_PRESENT)
1175 return 1;
1176 }
1177 return 0;
1178}
1179
1180void netxen_request_firmware(struct netxen_adapter *adapter)
1181{
6598b169
DP		 1182 struct pci_dev *pdev = adapter->pdev;
1183 int rc = 0;
1184
f50330f9 1185 adapter->fw_type = NX_UNKNOWN_ROMIMAGE;
f7185c71 1186
f50330f9
AKS		 1187next:
1188 nx_get_next_fwtype(adapter);
f7185c71 1189
f50330f9 1190 if (adapter->fw_type == NX_FLASH_ROMIMAGE) {
f7185c71 1191 adapter->fw = NULL;
f50330f9
AKS		 1192 } else {
1193 rc = request_firmware(&adapter->fw,
1194 fw_name[adapter->fw_type], &pdev->dev);
1195 if (rc != 0)
1196 goto next;
1197
1198 rc = netxen_validate_firmware(adapter);
1199 if (rc != 0) {
1200 release_firmware(adapter->fw);
f7185c71 1201 msleep(1);
f50330f9 1202 goto next;
f7185c71 1203 }
f7185c71 1204 }
f7185c71
DP		 1205}
1206
1207
1208void
1209netxen_release_firmware(struct netxen_adapter *adapter)
1210{
1211 if (adapter->fw)
1212 release_firmware(adapter->fw);
db4cfd8a 1213 adapter->fw = NULL;
f7185c71
DP		 1214}
1215
83ac51fa 1216int netxen_init_dummy_dma(struct netxen_adapter *adapter)
ed25ffa1 1217{
83ac51fa
DP		 1218 u64 addr;
1219 u32 hi, lo;
ed25ffa1 1220
83ac51fa
DP		 1221 if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
1222 return 0;
1223
1224 adapter->dummy_dma.addr = pci_alloc_consistent(adapter->pdev,
ed25ffa1
AK		 1225 NETXEN_HOST_DUMMY_DMA_SIZE,
1226 &adapter->dummy_dma.phys_addr);
1227 if (adapter->dummy_dma.addr == NULL) {
83ac51fa
DP		 1228 dev_err(&adapter->pdev->dev,
1229 "ERROR: Could not allocate dummy DMA memory\n");
ed25ffa1
AK		 1230 return -ENOMEM;
1231 }
1232
1233 addr = (uint64_t) adapter->dummy_dma.phys_addr;
1234 hi = (addr >> 32) & 0xffffffff;
1235 lo = addr & 0xffffffff;
1236
f98a9f69
DP		 1237 NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi);
1238 NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo);
ed25ffa1
AK		 1239
1240 return 0;
1241}
1242
83ac51fa
DP		 1243/*
1244 * NetXen DMA watchdog control:
1245 *
1246 * Bit 0 : enabled => R/O: 1 watchdog active, 0 inactive
1247 * Bit 1 : disable_request => 1 req disable dma watchdog
1248 * Bit 2 : enable_request => 1 req enable dma watchdog
1249 * Bit 3-31 : unused
1250 */
1251void netxen_free_dummy_dma(struct netxen_adapter *adapter)
ed25ffa1 1252{
15eef1e1 1253 int i = 100;
83ac51fa
DP		 1254 u32 ctrl;
1255
1256 if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
1257 return;
15eef1e1
DP		 1258
1259 if (!adapter->dummy_dma.addr)
1260 return;
439b454e 1261
83ac51fa
DP		 1262 ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
1263 if ((ctrl & 0x1) != 0) {
1264 NXWR32(adapter, NETXEN_DMA_WATCHDOG_CTRL, (ctrl | 0x2));
1265
1266 while ((ctrl & 0x1) != 0) {
1267
439b454e 1268 msleep(50);
83ac51fa
DP		 1269
1270 ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
1271
1272 if (--i == 0)
439b454e 1273 break;
83ac51fa 1274 };
15eef1e1 1275 }
439b454e 1276
15eef1e1
DP		 1277 if (i) {
1278 pci_free_consistent(adapter->pdev,
1279 NETXEN_HOST_DUMMY_DMA_SIZE,
1280 adapter->dummy_dma.addr,
1281 adapter->dummy_dma.phys_addr);
1282 adapter->dummy_dma.addr = NULL;
83ac51fa
DP		 1283 } else
1284 dev_err(&adapter->pdev->dev, "dma_watchdog_shutdown failed\n");
ed25ffa1
AK		 1285}
1286
96acb6eb 1287int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
3d396eb1
AK		 1288{
1289 u32 val = 0;
2956640d 1290 int retries = 60;
3d396eb1 1291
96f2ebd2
DP		 1292 if (pegtune_val)
1293 return 0;
1294
1295 do {
1296 val = NXRD32(adapter, CRB_CMDPEG_STATE);
96acb6eb 1297
96f2ebd2
DP		 1298 switch (val) {
1299 case PHAN_INITIALIZE_COMPLETE:
1300 case PHAN_INITIALIZE_ACK:
1301 return 0;
1302 case PHAN_INITIALIZE_FAILED:
1303 goto out_err;
1304 default:
1305 break;
1306 }
96acb6eb 1307
96f2ebd2 1308 msleep(500);
2956640d 1309
96f2ebd2 1310 } while (--retries);
2956640d 1311
96f2ebd2 1312 NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);
96acb6eb 1313
96f2ebd2
DP		 1314out_err:
1315 dev_warn(&adapter->pdev->dev, "firmware init failed\n");
1316 return -EIO;
3d396eb1
AK		 1317}
1318
56a00787
DP		 1319static int
1320netxen_receive_peg_ready(struct netxen_adapter *adapter)
2956640d
DP		 1321{
1322 u32 val = 0;
1323 int retries = 2000;
1324
1325 do {
f98a9f69 1326 val = NXRD32(adapter, CRB_RCVPEG_STATE);
2956640d
DP		 1327
1328 if (val == PHAN_PEG_RCV_INITIALIZED)
1329 return 0;
1330
1331 msleep(10);
1332
1333 } while (--retries);
1334
1335 if (!retries) {
1336 printk(KERN_ERR "Receive Peg initialization not "
1337 "complete, state: 0x%x.\n", val);
1338 return -EIO;
1339 }
1340
1341 return 0;
1342}
1343
56a00787
DP		 1344int netxen_init_firmware(struct netxen_adapter *adapter)
1345{
1346 int err;
1347
1348 err = netxen_receive_peg_ready(adapter);
1349 if (err)
1350 return err;
1351
f98a9f69
DP		 1352 NXWR32(adapter, CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT);
1353 NXWR32(adapter, CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC);
1354 NXWR32(adapter, CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE);
1355 NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
56a00787
DP		 1356
1357 return err;
1358}
1359
3bf26ce3
DP		 1360static void
1361netxen_handle_linkevent(struct netxen_adapter *adapter, nx_fw_msg_t *msg)
1362{
1363 u32 cable_OUI;
1364 u16 cable_len;
1365 u16 link_speed;
1366 u8 link_status, module, duplex, autoneg;
1367 struct net_device *netdev = adapter->netdev;
1368
1369 adapter->has_link_events = 1;
1370
1371 cable_OUI = msg->body[1] & 0xffffffff;
1372 cable_len = (msg->body[1] >> 32) & 0xffff;
1373 link_speed = (msg->body[1] >> 48) & 0xffff;
1374
1375 link_status = msg->body[2] & 0xff;
1376 duplex = (msg->body[2] >> 16) & 0xff;
1377 autoneg = (msg->body[2] >> 24) & 0xff;
1378
1379 module = (msg->body[2] >> 8) & 0xff;
1380 if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE) {
1381 printk(KERN_INFO "%s: unsupported cable: OUI 0x%x, length %d\n",
1382 netdev->name, cable_OUI, cable_len);
1383 } else if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN) {
1384 printk(KERN_INFO "%s: unsupported cable length %d\n",
1385 netdev->name, cable_len);
1386 }
1387
1388 netxen_advert_link_change(adapter, link_status);
1389
1390 /* update link parameters */
1391 if (duplex == LINKEVENT_FULL_DUPLEX)
1392 adapter->link_duplex = DUPLEX_FULL;
1393 else
1394 adapter->link_duplex = DUPLEX_HALF;
1395 adapter->module_type = module;
1396 adapter->link_autoneg = autoneg;
1397 adapter->link_speed = link_speed;
1398}
1399
1400static void
1401netxen_handle_fw_message(int desc_cnt, int index,
1402 struct nx_host_sds_ring *sds_ring)
1403{
1404 nx_fw_msg_t msg;
1405 struct status_desc *desc;
1406 int i = 0, opcode;
1407
1408 while (desc_cnt > 0 && i < 8) {
1409 desc = &sds_ring->desc_head[index];
1410 msg.words[i++] = le64_to_cpu(desc->status_desc_data[0]);
1411 msg.words[i++] = le64_to_cpu(desc->status_desc_data[1]);
1412
1413 index = get_next_index(index, sds_ring->num_desc);
1414 desc_cnt--;
1415 }
1416
1417 opcode = netxen_get_nic_msg_opcode(msg.body[0]);
1418 switch (opcode) {
1419 case NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE:
1420 netxen_handle_linkevent(sds_ring->adapter, &msg);
1421 break;
1422 default:
1423 break;
1424 }
1425}
1426
d8b100c5
DP		 1427static int
1428netxen_alloc_rx_skb(struct netxen_adapter *adapter,
1429 struct nx_host_rds_ring *rds_ring,
1430 struct netxen_rx_buffer *buffer)
1431{
1432 struct sk_buff *skb;
1433 dma_addr_t dma;
1434 struct pci_dev *pdev = adapter->pdev;
1435
1436 buffer->skb = dev_alloc_skb(rds_ring->skb_size);
1437 if (!buffer->skb)
1438 return 1;
1439
1440 skb = buffer->skb;
1441
1442 if (!adapter->ahw.cut_through)
1443 skb_reserve(skb, 2);
1444
1445 dma = pci_map_single(pdev, skb->data,
1446 rds_ring->dma_size, PCI_DMA_FROMDEVICE);
1447
1448 if (pci_dma_mapping_error(pdev, dma)) {
1449 dev_kfree_skb_any(skb);
1450 buffer->skb = NULL;
1451 return 1;
1452 }
1453
1454 buffer->skb = skb;
1455 buffer->dma = dma;
1456 buffer->state = NETXEN_BUFFER_BUSY;
1457
1458 return 0;
1459}
1460
d9e651bc
DP		 1461static struct sk_buff *netxen_process_rxbuf(struct netxen_adapter *adapter,
1462 struct nx_host_rds_ring *rds_ring, u16 index, u16 cksum)
1463{
1464 struct netxen_rx_buffer *buffer;
1465 struct sk_buff *skb;
1466
1467 buffer = &rds_ring->rx_buf_arr[index];
1468
1469 pci_unmap_single(adapter->pdev, buffer->dma, rds_ring->dma_size,
1470 PCI_DMA_FROMDEVICE);
1471
1472 skb = buffer->skb;
1473 if (!skb)
1474 goto no_skb;
1475
1476 if (likely(adapter->rx_csum && cksum == STATUS_CKSUM_OK)) {
1477 adapter->stats.csummed++;
1478 skb->ip_summed = CHECKSUM_UNNECESSARY;
1479 } else
1480 skb->ip_summed = CHECKSUM_NONE;
1481
1482 skb->dev = adapter->netdev;
1483
1484 buffer->skb = NULL;
d9e651bc
DP		 1485no_skb:
1486 buffer->state = NETXEN_BUFFER_FREE;
d9e651bc
DP		 1487 return skb;
1488}
1489
d8b100c5 1490static struct netxen_rx_buffer *
9b3ef55c 1491netxen_process_rcv(struct netxen_adapter *adapter,
c1c00ab8
DP		 1492 struct nx_host_sds_ring *sds_ring,
1493 int ring, u64 sts_data0)
3d396eb1 1494{
3176ff3e 1495 struct net_device *netdev = adapter->netdev;
becf46a0 1496 struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
3d396eb1
AK		 1497 struct netxen_rx_buffer *buffer;
1498 struct sk_buff *skb;
c1c00ab8
DP		 1499 struct nx_host_rds_ring *rds_ring;
1500 int index, length, cksum, pkt_offset;
3d396eb1 1501
c1c00ab8
DP		 1502 if (unlikely(ring >= adapter->max_rds_rings))
1503 return NULL;
1504
1505 rds_ring = &recv_ctx->rds_rings[ring];
1506
1507 index = netxen_get_sts_refhandle(sts_data0);
1508 if (unlikely(index >= rds_ring->num_desc))
d8b100c5 1509 return NULL;
438627c7 1510
48bfd1e0 1511 buffer = &rds_ring->rx_buf_arr[index];
3d396eb1 1512
c1c00ab8
DP		 1513 length = netxen_get_sts_totallength(sts_data0);
1514 cksum = netxen_get_sts_status(sts_data0);
1515 pkt_offset = netxen_get_sts_pkt_offset(sts_data0);
1516
d9e651bc
DP		 1517 skb = netxen_process_rxbuf(adapter, rds_ring, index, cksum);
1518 if (!skb)
d8b100c5 1519 return buffer;
200eef20 1520
9b3ef55c
DP		 1521 if (length > rds_ring->skb_size)
1522 skb_put(skb, rds_ring->skb_size);
1523 else
1524 skb_put(skb, length);
d9e651bc 1525
9b3ef55c
DP		 1526
1527 if (pkt_offset)
1528 skb_pull(skb, pkt_offset);
ed25ffa1 1529
bc75e5bf 1530 skb->truesize = skb->len + sizeof(struct sk_buff);
3d396eb1
AK		 1531 skb->protocol = eth_type_trans(skb, netdev);
1532
a92e9e65 1533 napi_gro_receive(&sds_ring->napi, skb);
d9e651bc 1534
1bb482f8 1535 adapter->stats.rx_pkts++;
0ddc110c 1536 adapter->stats.rxbytes += length;
d8b100c5
DP		 1537
1538 return buffer;
3d396eb1
AK		 1539}
1540
c1c00ab8
DP		 1541#define TCP_HDR_SIZE 20
1542#define TCP_TS_OPTION_SIZE 12
1543#define TCP_TS_HDR_SIZE (TCP_HDR_SIZE + TCP_TS_OPTION_SIZE)
1544
1545static struct netxen_rx_buffer *
1546netxen_process_lro(struct netxen_adapter *adapter,
1547 struct nx_host_sds_ring *sds_ring,
1548 int ring, u64 sts_data0, u64 sts_data1)
1549{
1550 struct net_device *netdev = adapter->netdev;
1551 struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
1552 struct netxen_rx_buffer *buffer;
1553 struct sk_buff *skb;
1554 struct nx_host_rds_ring *rds_ring;
1555 struct iphdr *iph;
1556 struct tcphdr *th;
1557 bool push, timestamp;
1558 int l2_hdr_offset, l4_hdr_offset;
1559 int index;
1560 u16 lro_length, length, data_offset;
1561 u32 seq_number;
1562
1563 if (unlikely(ring > adapter->max_rds_rings))
1564 return NULL;
1565
1566 rds_ring = &recv_ctx->rds_rings[ring];
1567
1568 index = netxen_get_lro_sts_refhandle(sts_data0);
1569 if (unlikely(index > rds_ring->num_desc))
1570 return NULL;
1571
1572 buffer = &rds_ring->rx_buf_arr[index];
1573
1574 timestamp = netxen_get_lro_sts_timestamp(sts_data0);
1575 lro_length = netxen_get_lro_sts_length(sts_data0);
1576 l2_hdr_offset = netxen_get_lro_sts_l2_hdr_offset(sts_data0);
1577 l4_hdr_offset = netxen_get_lro_sts_l4_hdr_offset(sts_data0);
1578 push = netxen_get_lro_sts_push_flag(sts_data0);
1579 seq_number = netxen_get_lro_sts_seq_number(sts_data1);
1580
1581 skb = netxen_process_rxbuf(adapter, rds_ring, index, STATUS_CKSUM_OK);
1582 if (!skb)
1583 return buffer;
1584
1585 if (timestamp)
1586 data_offset = l4_hdr_offset + TCP_TS_HDR_SIZE;
1587 else
1588 data_offset = l4_hdr_offset + TCP_HDR_SIZE;
1589
1590 skb_put(skb, lro_length + data_offset);
1591
bc75e5bf 1592 skb->truesize = skb->len + sizeof(struct sk_buff) + skb_headroom(skb);
c1c00ab8
DP		 1593
1594 skb_pull(skb, l2_hdr_offset);
1595 skb->protocol = eth_type_trans(skb, netdev);
1596
1597 iph = (struct iphdr *)skb->data;
1598 th = (struct tcphdr *)(skb->data + (iph->ihl << 2));
1599
1600 length = (iph->ihl << 2) + (th->doff << 2) + lro_length;
1601 iph->tot_len = htons(length);
1602 iph->check = 0;
1603 iph->check = ip_fast_csum((unsigned char *)iph, iph->ihl);
1604 th->psh = push;
1605 th->seq = htonl(seq_number);
1606
1bb482f8
NK		 1607 length = skb->len;
1608
c1c00ab8
DP		 1609 netif_receive_skb(skb);
1610
1bb482f8
NK		 1611 adapter->stats.lro_pkts++;
1612 adapter->stats.rxbytes += length;
1613
c1c00ab8
DP		 1614 return buffer;
1615}
1616
d8b100c5
DP		 1617#define netxen_merge_rx_buffers(list, head) \
1618 do { list_splice_tail_init(list, head); } while (0);
1619
becf46a0 1620int
d8b100c5 1621netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max)
3d396eb1 1622{
d8b100c5
DP		 1623 struct netxen_adapter *adapter = sds_ring->adapter;
1624
1625 struct list_head *cur;
1626
0ddc110c 1627 struct status_desc *desc;
d8b100c5
DP		 1628 struct netxen_rx_buffer *rxbuf;
1629
1630 u32 consumer = sds_ring->consumer;
1631
9b3ef55c 1632 int count = 0;
c1c00ab8
DP		 1633 u64 sts_data0, sts_data1;
1634 int opcode, ring = 0, desc_cnt;
3d396eb1 1635
3d396eb1 1636 while (count < max) {
d8b100c5 1637 desc = &sds_ring->desc_head[consumer];
c1c00ab8 1638 sts_data0 = le64_to_cpu(desc->status_desc_data[0]);
0ddc110c 1639
c1c00ab8 1640 if (!(sts_data0 & STATUS_OWNER_HOST))
3d396eb1 1641 break;
d9e651bc 1642
c1c00ab8 1643 desc_cnt = netxen_get_sts_desc_cnt(sts_data0);
3bf26ce3 1644
c1c00ab8 1645 opcode = netxen_get_sts_opcode(sts_data0);
d9e651bc 1646
3bf26ce3
DP		 1647 switch (opcode) {
1648 case NETXEN_NIC_RXPKT_DESC:
1649 case NETXEN_OLD_RXPKT_DESC:
6598b169 1650 case NETXEN_NIC_SYN_OFFLOAD:
c1c00ab8
DP		 1651 ring = netxen_get_sts_type(sts_data0);
1652 rxbuf = netxen_process_rcv(adapter, sds_ring,
1653 ring, sts_data0);
1654 break;
1655 case NETXEN_NIC_LRO_DESC:
1656 ring = netxen_get_lro_sts_type(sts_data0);
1657 sts_data1 = le64_to_cpu(desc->status_desc_data[1]);
1658 rxbuf = netxen_process_lro(adapter, sds_ring,
1659 ring, sts_data0, sts_data1);
3bf26ce3
DP		 1660 break;
1661 case NETXEN_NIC_RESPONSE_DESC:
1662 netxen_handle_fw_message(desc_cnt, consumer, sds_ring);
1663 default:
1664 goto skip;
1665 }
1666
1667 WARN_ON(desc_cnt > 1);
1668
d8b100c5
DP		 1669 if (rxbuf)
1670 list_add_tail(&rxbuf->list, &sds_ring->free_list[ring]);
1671
3bf26ce3
DP		 1672skip:
1673 for (; desc_cnt > 0; desc_cnt--) {
1674 desc = &sds_ring->desc_head[consumer];
1675 desc->status_desc_data[0] =
1676 cpu_to_le64(STATUS_OWNER_PHANTOM);
1677 consumer = get_next_index(consumer, sds_ring->num_desc);
1678 }
3d396eb1
AK		 1679 count++;
1680 }
0ddc110c 1681
d8b100c5
DP		 1682 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
1683 struct nx_host_rds_ring *rds_ring =
1684 &adapter->recv_ctx.rds_rings[ring];
1685
1686 if (!list_empty(&sds_ring->free_list[ring])) {
1687 list_for_each(cur, &sds_ring->free_list[ring]) {
1688 rxbuf = list_entry(cur,
1689 struct netxen_rx_buffer, list);
1690 netxen_alloc_rx_skb(adapter, rds_ring, rxbuf);
1691 }
1692 spin_lock(&rds_ring->lock);
1693 netxen_merge_rx_buffers(&sds_ring->free_list[ring],
1694 &rds_ring->free_list);
1695 spin_unlock(&rds_ring->lock);
1696 }
1697
1698 netxen_post_rx_buffers_nodb(adapter, rds_ring);
1699 }
3d396eb1 1700
3d396eb1 1701 if (count) {
d8b100c5 1702 sds_ring->consumer = consumer;
195c5f98 1703 NXWRIO(adapter, sds_ring->crb_sts_consumer, consumer);
3d396eb1
AK		 1704 }
1705
1706 return count;
1707}
1708
1709/* Process Command status ring */
05aaa02d 1710int netxen_process_cmd_ring(struct netxen_adapter *adapter)
3d396eb1 1711{
d877f1e3 1712 u32 sw_consumer, hw_consumer;
ba53e6b4 1713 int count = 0, i;
3d396eb1 1714 struct netxen_cmd_buffer *buffer;
ba53e6b4
DP		 1715 struct pci_dev *pdev = adapter->pdev;
1716 struct net_device *netdev = adapter->netdev;
3d396eb1 1717 struct netxen_skb_frag *frag;
ba53e6b4 1718 int done = 0;
4ea528a1 1719 struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
3d396eb1 1720
d8b100c5
DP		 1721 if (!spin_trylock(&adapter->tx_clean_lock))
1722 return 1;
1723
d877f1e3 1724 sw_consumer = tx_ring->sw_consumer;
d877f1e3 1725 hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
3d396eb1 1726
d877f1e3
DP		 1727 while (sw_consumer != hw_consumer) {
1728 buffer = &tx_ring->cmd_buf_arr[sw_consumer];
53a01e00 1729 if (buffer->skb) {
1730 frag = &buffer->frag_array[0];
3d396eb1
AK		 1731 pci_unmap_single(pdev, frag->dma, frag->length,
1732 PCI_DMA_TODEVICE);
96acb6eb 1733 frag->dma = 0ULL;
3d396eb1 1734 for (i = 1; i < buffer->frag_count; i++) {
3d396eb1
AK		 1735 frag++; /* Get the next frag */
1736 pci_unmap_page(pdev, frag->dma, frag->length,
1737 PCI_DMA_TODEVICE);
96acb6eb 1738 frag->dma = 0ULL;
3d396eb1
AK		 1739 }
1740
ba53e6b4 1741 adapter->stats.xmitfinished++;
53a01e00 1742 dev_kfree_skb_any(buffer->skb);
1743 buffer->skb = NULL;
3d396eb1
AK		 1744 }
1745
d877f1e3 1746 sw_consumer = get_next_index(sw_consumer, tx_ring->num_desc);
ba53e6b4
DP		 1747 if (++count >= MAX_STATUS_HANDLE)
1748 break;
3d396eb1 1749 }
3d396eb1 1750
22527864 1751 if (count && netif_running(netdev)) {
cb2107be
DP		 1752 tx_ring->sw_consumer = sw_consumer;
1753
ba53e6b4 1754 smp_mb();
cb2107be 1755
22527864 1756 if (netif_queue_stopped(netdev) && netif_carrier_ok(netdev)) {
b2af9cb0 1757 __netif_tx_lock(tx_ring->txq, smp_processor_id());
74c520da 1758 if (netxen_tx_avail(tx_ring) > TX_STOP_THRESH) {
cb2107be 1759 netif_wake_queue(netdev);
74c520da
AKS		 1760 adapter->tx_timeo_cnt = 0;
1761 }
b2af9cb0 1762 __netif_tx_unlock(tx_ring->txq);
3d396eb1
AK		 1763 }
1764 }
ed25ffa1
AK		 1765 /*
1766 * If everything is freed up to consumer then check if the ring is full
1767 * If the ring is full then check if more needs to be freed and
1768 * schedule the call back again.
1769 *
1770 * This happens when there are 2 CPUs. One could be freeing and the
1771 * other filling it. If the ring is full when we get out of here and
1772 * the card has already interrupted the host then the host can miss the
1773 * interrupt.
1774 *
1775 * There is still a possible race condition and the host could miss an
1776 * interrupt. The card has to take care of this.
1777 */
d877f1e3
DP		 1778 hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
1779 done = (sw_consumer == hw_consumer);
d8b100c5 1780 spin_unlock(&adapter->tx_clean_lock);
3d396eb1 1781
ed25ffa1 1782 return (done);
3d396eb1
AK		 1783}
1784
becf46a0 1785void
d8b100c5
DP		 1786netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
1787 struct nx_host_rds_ring *rds_ring)
3d396eb1 1788{
3d396eb1
AK		 1789 struct rcv_desc *pdesc;
1790 struct netxen_rx_buffer *buffer;
d8b100c5 1791 int producer, count = 0;
ed25ffa1 1792 netxen_ctx_msg msg = 0;
d9e651bc 1793 struct list_head *head;
3d396eb1 1794
48bfd1e0 1795 producer = rds_ring->producer;
d9e651bc 1796
d8b100c5
DP		 1797 spin_lock(&rds_ring->lock);
1798 head = &rds_ring->free_list;
d9e651bc
DP		 1799 while (!list_empty(head)) {
1800
d8b100c5 1801 buffer = list_entry(head->next, struct netxen_rx_buffer, list);
6f703406 1802
d8b100c5
DP		 1803 if (!buffer->skb) {
1804 if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
1805 break;
6f703406
DP		 1806 }
1807
1808 count++;
d9e651bc
DP		 1809 list_del(&buffer->list);
1810
ed25ffa1 1811 /* make a rcv descriptor */
6f703406 1812 pdesc = &rds_ring->desc_head[producer];
d8b100c5 1813 pdesc->addr_buffer = cpu_to_le64(buffer->dma);
ed33ebe4 1814 pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
48bfd1e0 1815 pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
6f703406 1816
438627c7 1817 producer = get_next_index(producer, rds_ring->num_desc);
ed25ffa1 1818 }
d8b100c5 1819 spin_unlock(&rds_ring->lock);
9b3ef55c 1820
ed25ffa1 1821 if (count) {
48bfd1e0 1822 rds_ring->producer = producer;
195c5f98 1823 NXWRIO(adapter, rds_ring->crb_rcv_producer,
438627c7 1824 (producer-1) & (rds_ring->num_desc-1));
48bfd1e0 1825
4f96b988 1826 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
ed25ffa1
AK		 1827 /*
1828 * Write a doorbell msg to tell phanmon of change in
1829 * receive ring producer
48bfd1e0 1830 * Only for firmware version < 4.0.0
ed25ffa1
AK		 1831 */
1832 netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
1833 netxen_set_msg_privid(msg);
1834 netxen_set_msg_count(msg,
438627c7
DP		 1835 ((producer - 1) &
1836 (rds_ring->num_desc - 1)));
3176ff3e 1837 netxen_set_msg_ctxid(msg, adapter->portnum);
ed25ffa1 1838 netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
f03b0ebd
DP		 1839 NXWRIO(adapter, DB_NORMALIZE(adapter,
1840 NETXEN_RCV_PRODUCER_OFFSET), msg);
48bfd1e0 1841 }
ed25ffa1
AK		 1842 }
1843}
1844
becf46a0 1845static void
d8b100c5
DP		 1846netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
1847 struct nx_host_rds_ring *rds_ring)
ed25ffa1 1848{
ed25ffa1
AK		 1849 struct rcv_desc *pdesc;
1850 struct netxen_rx_buffer *buffer;
d8b100c5 1851 int producer, count = 0;
d9e651bc 1852 struct list_head *head;
ed25ffa1 1853
48bfd1e0 1854 producer = rds_ring->producer;
d8b100c5
DP		 1855 if (!spin_trylock(&rds_ring->lock))
1856 return;
1857
d9e651bc 1858 head = &rds_ring->free_list;
d9e651bc
DP		 1859 while (!list_empty(head)) {
1860
d8b100c5 1861 buffer = list_entry(head->next, struct netxen_rx_buffer, list);
6f703406 1862
d8b100c5
DP		 1863 if (!buffer->skb) {
1864 if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
1865 break;
6f703406
DP		 1866 }
1867
1868 count++;
d9e651bc
DP		 1869 list_del(&buffer->list);
1870
3d396eb1 1871 /* make a rcv descriptor */
6f703406 1872 pdesc = &rds_ring->desc_head[producer];
ed33ebe4 1873 pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
48bfd1e0 1874 pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
3d396eb1 1875 pdesc->addr_buffer = cpu_to_le64(buffer->dma);
6f703406 1876
438627c7 1877 producer = get_next_index(producer, rds_ring->num_desc);
3d396eb1
AK		 1878 }
1879
3d396eb1 1880 if (count) {
48bfd1e0 1881 rds_ring->producer = producer;
195c5f98 1882 NXWRIO(adapter, rds_ring->crb_rcv_producer,
438627c7 1883 (producer - 1) & (rds_ring->num_desc - 1));
3d396eb1 1884 }
d8b100c5 1885 spin_unlock(&rds_ring->lock);
3d396eb1
AK		 1886}
1887
3d396eb1
AK		 1888void netxen_nic_clear_stats(struct netxen_adapter *adapter)
1889{
3d396eb1 1890 memset(&adapter->stats, 0, sizeof(adapter->stats));
3176ff3e 1891 return;
3d396eb1
AK		 1892}
1893
Linux 6.x block layer and io_uring tree(s)