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jmr3927: do not call tc35815_killall().
[linux-2.6-block.git] / drivers / net / myri10ge / myri10ge.c
CommitLineData
0da34b6d
BG		 1/*************************************************************************
2 * myri10ge.c: Myricom Myri-10G Ethernet driver.
3 *
4 * Copyright (C) 2005, 2006 Myricom, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of Myricom, Inc. nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 *
32 * If the eeprom on your board is not recent enough, you will need to get a
33 * newer firmware image at:
34 * http://www.myri.com/scs/download-Myri10GE.html
35 *
36 * Contact Information:
37 * <help@myri.com>
38 * Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
39 *************************************************************************/
40
41#include <linux/tcp.h>
42#include <linux/netdevice.h>
43#include <linux/skbuff.h>
44#include <linux/string.h>
45#include <linux/module.h>
46#include <linux/pci.h>
b10c0668 47#include <linux/dma-mapping.h>
0da34b6d
BG		 48#include <linux/etherdevice.h>
49#include <linux/if_ether.h>
50#include <linux/if_vlan.h>
51#include <linux/ip.h>
52#include <linux/inet.h>
53#include <linux/in.h>
54#include <linux/ethtool.h>
55#include <linux/firmware.h>
56#include <linux/delay.h>
57#include <linux/version.h>
58#include <linux/timer.h>
59#include <linux/vmalloc.h>
60#include <linux/crc32.h>
61#include <linux/moduleparam.h>
62#include <linux/io.h>
63#include <net/checksum.h>
64#include <asm/byteorder.h>
65#include <asm/io.h>
0da34b6d
BG		 66#include <asm/processor.h>
67#ifdef CONFIG_MTRR
68#include <asm/mtrr.h>
69#endif
70
71#include "myri10ge_mcp.h"
72#include "myri10ge_mcp_gen_header.h"
73
b2db8dd4 74#define MYRI10GE_VERSION_STR "1.2.0"
0da34b6d
BG		 75
76MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
77MODULE_AUTHOR("Maintainer: help@myri.com");
78MODULE_VERSION(MYRI10GE_VERSION_STR);
79MODULE_LICENSE("Dual BSD/GPL");
80
81#define MYRI10GE_MAX_ETHER_MTU 9014
82
83#define MYRI10GE_ETH_STOPPED 0
84#define MYRI10GE_ETH_STOPPING 1
85#define MYRI10GE_ETH_STARTING 2
86#define MYRI10GE_ETH_RUNNING 3
87#define MYRI10GE_ETH_OPEN_FAILED 4
88
89#define MYRI10GE_EEPROM_STRINGS_SIZE 256
90#define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
91
40f6cff5 92#define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
0da34b6d
BG		 93#define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
94
dd50f336
BG		 95#define MYRI10GE_ALLOC_ORDER 0
96#define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE)
97#define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1)
98
0da34b6d 99struct myri10ge_rx_buffer_state {
dd50f336
BG		 100 struct page *page;
101 int page_offset;
0da34b6d
BG		 102 DECLARE_PCI_UNMAP_ADDR(bus)
103 DECLARE_PCI_UNMAP_LEN(len)
104};
105
106struct myri10ge_tx_buffer_state {
107 struct sk_buff *skb;
108 int last;
109 DECLARE_PCI_UNMAP_ADDR(bus)
110 DECLARE_PCI_UNMAP_LEN(len)
111};
112
113struct myri10ge_cmd {
114 u32 data0;
115 u32 data1;
116 u32 data2;
117};
118
119struct myri10ge_rx_buf {
120 struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */
121 u8 __iomem *wc_fifo; /* w/c rx dma addr fifo address */
122 struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */
123 struct myri10ge_rx_buffer_state *info;
dd50f336
BG		 124 struct page *page;
125 dma_addr_t bus;
126 int page_offset;
0da34b6d 127 int cnt;
dd50f336 128 int fill_cnt;
0da34b6d
BG		 129 int alloc_fail;
130 int mask; /* number of rx slots -1 */
dd50f336 131 int watchdog_needed;
0da34b6d
BG		 132};
133
134struct myri10ge_tx_buf {
135 struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */
136 u8 __iomem *wc_fifo; /* w/c send fifo address */
137 struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */
138 char *req_bytes;
139 struct myri10ge_tx_buffer_state *info;
140 int mask; /* number of transmit slots -1 */
141 int boundary; /* boundary transmits cannot cross */
142 int req ____cacheline_aligned; /* transmit slots submitted */
143 int pkt_start; /* packets started */
144 int done ____cacheline_aligned; /* transmit slots completed */
145 int pkt_done; /* packets completed */
146};
147
148struct myri10ge_rx_done {
149 struct mcp_slot *entry;
150 dma_addr_t bus;
151 int cnt;
152 int idx;
153};
154
155struct myri10ge_priv {
156 int running; /* running? */
157 int csum_flag; /* rx_csums? */
158 struct myri10ge_tx_buf tx; /* transmit ring */
159 struct myri10ge_rx_buf rx_small;
160 struct myri10ge_rx_buf rx_big;
161 struct myri10ge_rx_done rx_done;
162 int small_bytes;
dd50f336 163 int big_bytes;
0da34b6d
BG		 164 struct net_device *dev;
165 struct net_device_stats stats;
166 u8 __iomem *sram;
167 int sram_size;
168 unsigned long board_span;
169 unsigned long iomem_base;
40f6cff5
AV		 170 __be32 __iomem *irq_claim;
171 __be32 __iomem *irq_deassert;
0da34b6d
BG		 172 char *mac_addr_string;
173 struct mcp_cmd_response *cmd;
174 dma_addr_t cmd_bus;
175 struct mcp_irq_data *fw_stats;
176 dma_addr_t fw_stats_bus;
177 struct pci_dev *pdev;
178 int msi_enabled;
40f6cff5 179 __be32 link_state;
0da34b6d
BG		 180 unsigned int rdma_tags_available;
181 int intr_coal_delay;
40f6cff5 182 __be32 __iomem *intr_coal_delay_ptr;
0da34b6d
BG		 183 int mtrr;
184 int wake_queue;
185 int stop_queue;
186 int down_cnt;
187 wait_queue_head_t down_wq;
188 struct work_struct watchdog_work;
189 struct timer_list watchdog_timer;
190 int watchdog_tx_done;
c54772e7 191 int watchdog_tx_req;
0da34b6d
BG		 192 int watchdog_resets;
193 int tx_linearized;
194 int pause;
195 char *fw_name;
196 char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
197 char fw_version[128];
9dc6f0e7
BG		 198 int fw_ver_major;
199 int fw_ver_minor;
200 int fw_ver_tiny;
201 int adopted_rx_filter_bug;
0da34b6d
BG		 202 u8 mac_addr[6]; /* eeprom mac address */
203 unsigned long serial_number;
204 int vendor_specific_offset;
85a7ea1b 205 int fw_multicast_support;
0da34b6d
BG		 206 u32 read_dma;
207 u32 write_dma;
208 u32 read_write_dma;
c58ac5ca
BG		 209 u32 link_changes;
210 u32 msg_enable;
0da34b6d
BG		 211};
212
213static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
214static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
215
216static char *myri10ge_fw_name = NULL;
217module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
218MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name\n");
219
220static int myri10ge_ecrc_enable = 1;
221module_param(myri10ge_ecrc_enable, int, S_IRUGO);
222MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E\n");
223
224static int myri10ge_max_intr_slots = 1024;
225module_param(myri10ge_max_intr_slots, int, S_IRUGO);
226MODULE_PARM_DESC(myri10ge_max_intr_slots, "Interrupt queue slots\n");
227
228static int myri10ge_small_bytes = -1; /* -1 == auto */
229module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
230MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets\n");
231
232static int myri10ge_msi = 1; /* enable msi by default */
3621cec5 233module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR);
0da34b6d
BG		 234MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts\n");
235
236static int myri10ge_intr_coal_delay = 25;
237module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
238MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay\n");
239
240static int myri10ge_flow_control = 1;
241module_param(myri10ge_flow_control, int, S_IRUGO);
242MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter\n");
243
244static int myri10ge_deassert_wait = 1;
245module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
246MODULE_PARM_DESC(myri10ge_deassert_wait,
247 "Wait when deasserting legacy interrupts\n");
248
249static int myri10ge_force_firmware = 0;
250module_param(myri10ge_force_firmware, int, S_IRUGO);
251MODULE_PARM_DESC(myri10ge_force_firmware,
252 "Force firmware to assume aligned completions\n");
253
0da34b6d
BG		 254static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
255module_param(myri10ge_initial_mtu, int, S_IRUGO);
256MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU\n");
257
258static int myri10ge_napi_weight = 64;
259module_param(myri10ge_napi_weight, int, S_IRUGO);
260MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight\n");
261
262static int myri10ge_watchdog_timeout = 1;
263module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
264MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout\n");
265
266static int myri10ge_max_irq_loops = 1048576;
267module_param(myri10ge_max_irq_loops, int, S_IRUGO);
268MODULE_PARM_DESC(myri10ge_max_irq_loops,
269 "Set stuck legacy IRQ detection threshold\n");
270
c58ac5ca
BG		 271#define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
272
273static int myri10ge_debug = -1; /* defaults above */
274module_param(myri10ge_debug, int, 0);
275MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
276
dd50f336
BG		 277static int myri10ge_fill_thresh = 256;
278module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
279MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed\n");
280
6ebc087a
BG		 281static int myri10ge_wcfifo = 1;
282module_param(myri10ge_wcfifo, int, S_IRUGO);
283MODULE_PARM_DESC(myri10ge_wcfifo, "Enable WC Fifo when WC is enabled\n");
284
0da34b6d
BG		 285#define MYRI10GE_FW_OFFSET 1024*1024
286#define MYRI10GE_HIGHPART_TO_U32(X) \
287(sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
288#define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
289
290#define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
291
6250223e 292static inline void put_be32(__be32 val, __be32 __iomem * p)
40f6cff5 293{
6250223e 294 __raw_writel((__force __u32) val, (__force void __iomem *)p);
40f6cff5
AV		 295}
296
0da34b6d
BG		 297static int
298myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
299 struct myri10ge_cmd *data, int atomic)
300{
301 struct mcp_cmd *buf;
302 char buf_bytes[sizeof(*buf) + 8];
303 struct mcp_cmd_response *response = mgp->cmd;
e700f9f4 304 char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
0da34b6d
BG		 305 u32 dma_low, dma_high, result, value;
306 int sleep_total = 0;
307
308 /* ensure buf is aligned to 8 bytes */
309 buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
310
311 buf->data0 = htonl(data->data0);
312 buf->data1 = htonl(data->data1);
313 buf->data2 = htonl(data->data2);
314 buf->cmd = htonl(cmd);
315 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
316 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
317
318 buf->response_addr.low = htonl(dma_low);
319 buf->response_addr.high = htonl(dma_high);
40f6cff5 320 response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 321 mb();
322 myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
323
324 /* wait up to 15ms. Longest command is the DMA benchmark,
325 * which is capped at 5ms, but runs from a timeout handler
326 * that runs every 7.8ms. So a 15ms timeout leaves us with
327 * a 2.2ms margin
328 */
329 if (atomic) {
330 /* if atomic is set, do not sleep,
331 * and try to get the completion quickly
332 * (1ms will be enough for those commands) */
333 for (sleep_total = 0;
334 sleep_total < 1000
40f6cff5 335 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 336 sleep_total += 10)
337 udelay(10);
338 } else {
339 /* use msleep for most command */
340 for (sleep_total = 0;
341 sleep_total < 15
40f6cff5 342 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 343 sleep_total++)
344 msleep(1);
345 }
346
347 result = ntohl(response->result);
348 value = ntohl(response->data);
349 if (result != MYRI10GE_NO_RESPONSE_RESULT) {
350 if (result == 0) {
351 data->data0 = value;
352 return 0;
85a7ea1b
BG		 353 } else if (result == MXGEFW_CMD_UNKNOWN) {
354 return -ENOSYS;
0da34b6d
BG		 355 } else {
356 dev_err(&mgp->pdev->dev,
357 "command %d failed, result = %d\n",
358 cmd, result);
359 return -ENXIO;
360 }
361 }
362
363 dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
364 cmd, result);
365 return -EAGAIN;
366}
367
368/*
369 * The eeprom strings on the lanaiX have the format
370 * SN=x\0
371 * MAC=x:x:x:x:x:x\0
372 * PT:ddd mmm xx xx:xx:xx xx\0
373 * PV:ddd mmm xx xx:xx:xx xx\0
374 */
375static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
376{
377 char *ptr, *limit;
378 int i;
379
380 ptr = mgp->eeprom_strings;
381 limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
382
383 while (*ptr != '\0' && ptr < limit) {
384 if (memcmp(ptr, "MAC=", 4) == 0) {
385 ptr += 4;
386 mgp->mac_addr_string = ptr;
387 for (i = 0; i < 6; i++) {
388 if ((ptr + 2) > limit)
389 goto abort;
390 mgp->mac_addr[i] =
391 simple_strtoul(ptr, &ptr, 16);
392 ptr += 1;
393 }
394 }
395 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
396 ptr += 3;
397 mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
398 }
399 while (ptr < limit && *ptr++) ;
400 }
401
402 return 0;
403
404abort:
405 dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
406 return -ENXIO;
407}
408
409/*
410 * Enable or disable periodic RDMAs from the host to make certain
411 * chipsets resend dropped PCIe messages
412 */
413
414static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
415{
416 char __iomem *submit;
40f6cff5 417 __be32 buf[16];
0da34b6d
BG		 418 u32 dma_low, dma_high;
419 int i;
420
421 /* clear confirmation addr */
422 mgp->cmd->data = 0;
423 mb();
424
425 /* send a rdma command to the PCIe engine, and wait for the
426 * response in the confirmation address. The firmware should
427 * write a -1 there to indicate it is alive and well
428 */
429 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
430 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
431
432 buf[0] = htonl(dma_high); /* confirm addr MSW */
433 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 434 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 435 buf[3] = htonl(dma_high); /* dummy addr MSW */
436 buf[4] = htonl(dma_low); /* dummy addr LSW */
437 buf[5] = htonl(enable); /* enable? */
438
e700f9f4 439 submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
0da34b6d
BG		 440
441 myri10ge_pio_copy(submit, &buf, sizeof(buf));
442 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
443 msleep(1);
444 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
445 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
446 (enable ? "enable" : "disable"));
447}
448
449static int
450myri10ge_validate_firmware(struct myri10ge_priv *mgp,
451 struct mcp_gen_header *hdr)
452{
453 struct device *dev = &mgp->pdev->dev;
0da34b6d
BG		 454
455 /* check firmware type */
456 if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
457 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
458 return -EINVAL;
459 }
460
461 /* save firmware version for ethtool */
462 strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
463
9dc6f0e7
BG		 464 sscanf(mgp->fw_version, "%d.%d.%d", &mgp->fw_ver_major,
465 &mgp->fw_ver_minor, &mgp->fw_ver_tiny);
0da34b6d 466
9dc6f0e7
BG		 467 if (!(mgp->fw_ver_major == MXGEFW_VERSION_MAJOR
468 && mgp->fw_ver_minor == MXGEFW_VERSION_MINOR)) {
0da34b6d
BG		 469 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
470 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
471 MXGEFW_VERSION_MINOR);
472 return -EINVAL;
473 }
474 return 0;
475}
476
477static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
478{
479 unsigned crc, reread_crc;
480 const struct firmware *fw;
481 struct device *dev = &mgp->pdev->dev;
482 struct mcp_gen_header *hdr;
483 size_t hdr_offset;
484 int status;
e454358a 485 unsigned i;
0da34b6d
BG		 486
487 if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
488 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
489 mgp->fw_name);
490 status = -EINVAL;
491 goto abort_with_nothing;
492 }
493
494 /* check size */
495
496 if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
497 fw->size < MCP_HEADER_PTR_OFFSET + 4) {
498 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
499 status = -EINVAL;
500 goto abort_with_fw;
501 }
502
503 /* check id */
40f6cff5 504 hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
0da34b6d
BG		 505 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
506 dev_err(dev, "Bad firmware file\n");
507 status = -EINVAL;
508 goto abort_with_fw;
509 }
510 hdr = (void *)(fw->data + hdr_offset);
511
512 status = myri10ge_validate_firmware(mgp, hdr);
513 if (status != 0)
514 goto abort_with_fw;
515
516 crc = crc32(~0, fw->data, fw->size);
e454358a
BG		 517 for (i = 0; i < fw->size; i += 256) {
518 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
519 fw->data + i,
520 min(256U, (unsigned)(fw->size - i)));
521 mb();
522 readb(mgp->sram);
b10c0668 523 }
0da34b6d
BG		 524 /* corruption checking is good for parity recovery and buggy chipset */
525 memcpy_fromio(fw->data, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
526 reread_crc = crc32(~0, fw->data, fw->size);
527 if (crc != reread_crc) {
528 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
529 (unsigned)fw->size, reread_crc, crc);
530 status = -EIO;
531 goto abort_with_fw;
532 }
533 *size = (u32) fw->size;
534
535abort_with_fw:
536 release_firmware(fw);
537
538abort_with_nothing:
539 return status;
540}
541
542static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
543{
544 struct mcp_gen_header *hdr;
545 struct device *dev = &mgp->pdev->dev;
546 const size_t bytes = sizeof(struct mcp_gen_header);
547 size_t hdr_offset;
548 int status;
549
550 /* find running firmware header */
551 hdr_offset = ntohl(__raw_readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
552
553 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
554 dev_err(dev, "Running firmware has bad header offset (%d)\n",
555 (int)hdr_offset);
556 return -EIO;
557 }
558
559 /* copy header of running firmware from SRAM to host memory to
560 * validate firmware */
561 hdr = kmalloc(bytes, GFP_KERNEL);
562 if (hdr == NULL) {
563 dev_err(dev, "could not malloc firmware hdr\n");
564 return -ENOMEM;
565 }
566 memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
567 status = myri10ge_validate_firmware(mgp, hdr);
568 kfree(hdr);
9dc6f0e7
BG		 569
570 /* check to see if adopted firmware has bug where adopting
571 * it will cause broadcasts to be filtered unless the NIC
572 * is kept in ALLMULTI mode */
573 if (mgp->fw_ver_major == 1 && mgp->fw_ver_minor == 4 &&
574 mgp->fw_ver_tiny >= 4 && mgp->fw_ver_tiny <= 11) {
575 mgp->adopted_rx_filter_bug = 1;
576 dev_warn(dev, "Adopting fw %d.%d.%d: "
577 "working around rx filter bug\n",
578 mgp->fw_ver_major, mgp->fw_ver_minor,
579 mgp->fw_ver_tiny);
580 }
0da34b6d
BG		 581 return status;
582}
583
584static int myri10ge_load_firmware(struct myri10ge_priv *mgp)
585{
586 char __iomem *submit;
40f6cff5 587 __be32 buf[16];
0da34b6d
BG		 588 u32 dma_low, dma_high, size;
589 int status, i;
590
b10c0668 591 size = 0;
0da34b6d
BG		 592 status = myri10ge_load_hotplug_firmware(mgp, &size);
593 if (status) {
594 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
595
596 /* Do not attempt to adopt firmware if there
597 * was a bad crc */
598 if (status == -EIO)
599 return status;
600
601 status = myri10ge_adopt_running_firmware(mgp);
602 if (status != 0) {
603 dev_err(&mgp->pdev->dev,
604 "failed to adopt running firmware\n");
605 return status;
606 }
607 dev_info(&mgp->pdev->dev,
608 "Successfully adopted running firmware\n");
609 if (mgp->tx.boundary == 4096) {
610 dev_warn(&mgp->pdev->dev,
611 "Using firmware currently running on NIC"
612 ". For optimal\n");
613 dev_warn(&mgp->pdev->dev,
614 "performance consider loading optimized "
615 "firmware\n");
616 dev_warn(&mgp->pdev->dev, "via hotplug\n");
617 }
618
619 mgp->fw_name = "adopted";
620 mgp->tx.boundary = 2048;
621 return status;
622 }
623
624 /* clear confirmation addr */
625 mgp->cmd->data = 0;
626 mb();
627
628 /* send a reload command to the bootstrap MCP, and wait for the
629 * response in the confirmation address. The firmware should
630 * write a -1 there to indicate it is alive and well
631 */
632 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
633 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
634
635 buf[0] = htonl(dma_high); /* confirm addr MSW */
636 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 637 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 638
639 /* FIX: All newest firmware should un-protect the bottom of
640 * the sram before handoff. However, the very first interfaces
641 * do not. Therefore the handoff copy must skip the first 8 bytes
642 */
643 buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
644 buf[4] = htonl(size - 8); /* length of code */
645 buf[5] = htonl(8); /* where to copy to */
646 buf[6] = htonl(0); /* where to jump to */
647
e700f9f4 648 submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
0da34b6d
BG		 649
650 myri10ge_pio_copy(submit, &buf, sizeof(buf));
651 mb();
652 msleep(1);
653 mb();
654 i = 0;
655 while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20) {
656 msleep(1);
657 i++;
658 }
659 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
660 dev_err(&mgp->pdev->dev, "handoff failed\n");
661 return -ENXIO;
662 }
663 dev_info(&mgp->pdev->dev, "handoff confirmed\n");
9a71db72 664 myri10ge_dummy_rdma(mgp, 1);
0da34b6d
BG		 665
666 return 0;
667}
668
669static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
670{
671 struct myri10ge_cmd cmd;
672 int status;
673
674 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
675 | (addr[2] << 8) | addr[3]);
676
677 cmd.data1 = ((addr[4] << 8) | (addr[5]));
678
679 status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
680 return status;
681}
682
683static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
684{
685 struct myri10ge_cmd cmd;
686 int status, ctl;
687
688 ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
689 status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
690
691 if (status) {
692 printk(KERN_ERR
693 "myri10ge: %s: Failed to set flow control mode\n",
694 mgp->dev->name);
695 return status;
696 }
697 mgp->pause = pause;
698 return 0;
699}
700
701static void
702myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
703{
704 struct myri10ge_cmd cmd;
705 int status, ctl;
706
707 ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
708 status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
709 if (status)
710 printk(KERN_ERR "myri10ge: %s: Failed to set promisc mode\n",
711 mgp->dev->name);
712}
713
714static int myri10ge_reset(struct myri10ge_priv *mgp)
715{
716 struct myri10ge_cmd cmd;
717 int status;
718 size_t bytes;
719 u32 len;
720
721 /* try to send a reset command to the card to see if it
722 * is alive */
723 memset(&cmd, 0, sizeof(cmd));
724 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
725 if (status != 0) {
726 dev_err(&mgp->pdev->dev, "failed reset\n");
727 return -ENXIO;
728 }
729
730 /* Now exchange information about interrupts */
731
732 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
733 memset(mgp->rx_done.entry, 0, bytes);
734 cmd.data0 = (u32) bytes;
735 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
736 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
737 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
738 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA, &cmd, 0);
739
740 status |=
741 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
40f6cff5 742 mgp->irq_claim = (__iomem __be32 *) (mgp->sram + cmd.data0);
df30a740
BG		 743 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
744 &cmd, 0);
745 mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d 746
0da34b6d
BG		 747 status |= myri10ge_send_cmd
748 (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
40f6cff5 749 mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d
BG		 750 if (status != 0) {
751 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
752 return status;
753 }
40f6cff5 754 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d
BG		 755
756 /* Run a small DMA test.
757 * The magic multipliers to the length tell the firmware
758 * to do DMA read, write, or read+write tests. The
759 * results are returned in cmd.data0. The upper 16
760 * bits or the return is the number of transfers completed.
761 * The lower 16 bits is the time in 0.5us ticks that the
762 * transfers took to complete.
763 */
764
765 len = mgp->tx.boundary;
766
767 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
768 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
769 cmd.data2 = len * 0x10000;
770 status = myri10ge_send_cmd(mgp, MXGEFW_DMA_TEST, &cmd, 0);
771 if (status == 0)
772 mgp->read_dma = ((cmd.data0 >> 16) * len * 2) /
773 (cmd.data0 & 0xffff);
774 else
775 dev_warn(&mgp->pdev->dev, "DMA read benchmark failed: %d\n",
776 status);
777 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
778 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
779 cmd.data2 = len * 0x1;
780 status = myri10ge_send_cmd(mgp, MXGEFW_DMA_TEST, &cmd, 0);
781 if (status == 0)
782 mgp->write_dma = ((cmd.data0 >> 16) * len * 2) /
783 (cmd.data0 & 0xffff);
784 else
785 dev_warn(&mgp->pdev->dev, "DMA write benchmark failed: %d\n",
786 status);
787
788 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
789 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
790 cmd.data2 = len * 0x10001;
791 status = myri10ge_send_cmd(mgp, MXGEFW_DMA_TEST, &cmd, 0);
792 if (status == 0)
793 mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
794 (cmd.data0 & 0xffff);
795 else
796 dev_warn(&mgp->pdev->dev,
797 "DMA read/write benchmark failed: %d\n", status);
798
799 memset(mgp->rx_done.entry, 0, bytes);
800
801 /* reset mcp/driver shared state back to 0 */
802 mgp->tx.req = 0;
803 mgp->tx.done = 0;
804 mgp->tx.pkt_start = 0;
805 mgp->tx.pkt_done = 0;
806 mgp->rx_big.cnt = 0;
807 mgp->rx_small.cnt = 0;
808 mgp->rx_done.idx = 0;
809 mgp->rx_done.cnt = 0;
c58ac5ca 810 mgp->link_changes = 0;
0da34b6d
BG		 811 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
812 myri10ge_change_promisc(mgp, 0, 0);
813 myri10ge_change_pause(mgp, mgp->pause);
9dc6f0e7
BG		 814 if (mgp->adopted_rx_filter_bug)
815 (void)myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
0da34b6d
BG		 816 return status;
817}
818
819static inline void
820myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
821 struct mcp_kreq_ether_recv *src)
822{
40f6cff5 823 __be32 low;
0da34b6d
BG		 824
825 low = src->addr_low;
40f6cff5 826 src->addr_low = htonl(DMA_32BIT_MASK);
e67bda55
BG		 827 myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
828 mb();
829 myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
0da34b6d
BG		 830 mb();
831 src->addr_low = low;
40f6cff5 832 put_be32(low, &dst->addr_low);
0da34b6d
BG		 833 mb();
834}
835
40f6cff5 836static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
0da34b6d
BG		 837{
838 struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
839
40f6cff5 840 if ((skb->protocol == htons(ETH_P_8021Q)) &&
0da34b6d
BG		 841 (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
842 vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
843 skb->csum = hw_csum;
84fa7933 844 skb->ip_summed = CHECKSUM_COMPLETE;
0da34b6d
BG		 845 }
846}
847
dd50f336
BG		 848static inline void
849myri10ge_rx_skb_build(struct sk_buff *skb, u8 * va,
850 struct skb_frag_struct *rx_frags, int len, int hlen)
851{
852 struct skb_frag_struct *skb_frags;
853
854 skb->len = skb->data_len = len;
855 skb->truesize = len + sizeof(struct sk_buff);
856 /* attach the page(s) */
857
858 skb_frags = skb_shinfo(skb)->frags;
859 while (len > 0) {
860 memcpy(skb_frags, rx_frags, sizeof(*skb_frags));
861 len -= rx_frags->size;
862 skb_frags++;
863 rx_frags++;
864 skb_shinfo(skb)->nr_frags++;
865 }
866
867 /* pskb_may_pull is not available in irq context, but
868 * skb_pull() (for ether_pad and eth_type_trans()) requires
869 * the beginning of the packet in skb_headlen(), move it
870 * manually */
871 memcpy(skb->data, va, hlen);
872 skb_shinfo(skb)->frags[0].page_offset += hlen;
873 skb_shinfo(skb)->frags[0].size -= hlen;
874 skb->data_len -= hlen;
875 skb->tail += hlen;
876 skb_pull(skb, MXGEFW_PAD);
877}
878
879static void
880myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
881 int bytes, int watchdog)
882{
883 struct page *page;
884 int idx;
885
886 if (unlikely(rx->watchdog_needed && !watchdog))
887 return;
888
889 /* try to refill entire ring */
890 while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) {
891 idx = rx->fill_cnt & rx->mask;
892
893 if ((bytes < MYRI10GE_ALLOC_SIZE / 2) &&
894 (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE)) {
895 /* we can use part of previous page */
896 get_page(rx->page);
897 } else {
898 /* we need a new page */
899 page =
900 alloc_pages(GFP_ATOMIC | __GFP_COMP,
901 MYRI10GE_ALLOC_ORDER);
902 if (unlikely(page == NULL)) {
903 if (rx->fill_cnt - rx->cnt < 16)
904 rx->watchdog_needed = 1;
905 return;
906 }
907 rx->page = page;
908 rx->page_offset = 0;
909 rx->bus = pci_map_page(mgp->pdev, page, 0,
910 MYRI10GE_ALLOC_SIZE,
911 PCI_DMA_FROMDEVICE);
912 }
913 rx->info[idx].page = rx->page;
914 rx->info[idx].page_offset = rx->page_offset;
915 /* note that this is the address of the start of the
916 * page */
917 pci_unmap_addr_set(&rx->info[idx], bus, rx->bus);
918 rx->shadow[idx].addr_low =
919 htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset);
920 rx->shadow[idx].addr_high =
921 htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus));
922
923 /* start next packet on a cacheline boundary */
924 rx->page_offset += SKB_DATA_ALIGN(bytes);
925 rx->fill_cnt++;
926
927 /* copy 8 descriptors to the firmware at a time */
928 if ((idx & 7) == 7) {
929 if (rx->wc_fifo == NULL)
930 myri10ge_submit_8rx(&rx->lanai[idx - 7],
931 &rx->shadow[idx - 7]);
932 else {
933 mb();
934 myri10ge_pio_copy(rx->wc_fifo,
935 &rx->shadow[idx - 7], 64);
936 }
937 }
938 }
939}
940
941static inline void
942myri10ge_unmap_rx_page(struct pci_dev *pdev,
943 struct myri10ge_rx_buffer_state *info, int bytes)
944{
945 /* unmap the recvd page if we're the only or last user of it */
946 if (bytes >= MYRI10GE_ALLOC_SIZE / 2 ||
947 (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) {
948 pci_unmap_page(pdev, (pci_unmap_addr(info, bus)
949 & ~(MYRI10GE_ALLOC_SIZE - 1)),
950 MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
951 }
952}
953
954#define MYRI10GE_HLEN 64 /* The number of bytes to copy from a
955 * page into an skb */
956
957static inline int
52ea6fb3
BG		 958myri10ge_rx_done(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
959 int bytes, int len, __wsum csum)
dd50f336
BG		 960{
961 struct sk_buff *skb;
962 struct skb_frag_struct rx_frags[MYRI10GE_MAX_FRAGS_PER_FRAME];
963 int i, idx, hlen, remainder;
964 struct pci_dev *pdev = mgp->pdev;
965 struct net_device *dev = mgp->dev;
966 u8 *va;
967
968 len += MXGEFW_PAD;
969 idx = rx->cnt & rx->mask;
970 va = page_address(rx->info[idx].page) + rx->info[idx].page_offset;
971 prefetch(va);
972 /* Fill skb_frag_struct(s) with data from our receive */
973 for (i = 0, remainder = len; remainder > 0; i++) {
974 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
975 rx_frags[i].page = rx->info[idx].page;
976 rx_frags[i].page_offset = rx->info[idx].page_offset;
977 if (remainder < MYRI10GE_ALLOC_SIZE)
978 rx_frags[i].size = remainder;
979 else
980 rx_frags[i].size = MYRI10GE_ALLOC_SIZE;
981 rx->cnt++;
982 idx = rx->cnt & rx->mask;
983 remainder -= MYRI10GE_ALLOC_SIZE;
984 }
985
986 hlen = MYRI10GE_HLEN > len ? len : MYRI10GE_HLEN;
987
988 /* allocate an skb to attach the page(s) to. */
989
990 skb = netdev_alloc_skb(dev, MYRI10GE_HLEN + 16);
991 if (unlikely(skb == NULL)) {
992 mgp->stats.rx_dropped++;
993 do {
994 i--;
995 put_page(rx_frags[i].page);
996 } while (i != 0);
997 return 0;
998 }
999
1000 /* Attach the pages to the skb, and trim off any padding */
1001 myri10ge_rx_skb_build(skb, va, rx_frags, len, hlen);
1002 if (skb_shinfo(skb)->frags[0].size <= 0) {
1003 put_page(skb_shinfo(skb)->frags[0].page);
1004 skb_shinfo(skb)->nr_frags = 0;
1005 }
1006 skb->protocol = eth_type_trans(skb, dev);
1007 skb->dev = dev;
1008
1009 if (mgp->csum_flag) {
1010 if ((skb->protocol == htons(ETH_P_IP)) ||
1011 (skb->protocol == htons(ETH_P_IPV6))) {
1012 skb->csum = csum;
1013 skb->ip_summed = CHECKSUM_COMPLETE;
1014 } else
1015 myri10ge_vlan_ip_csum(skb, csum);
1016 }
1017 netif_receive_skb(skb);
1018 dev->last_rx = jiffies;
1019 return 1;
1020}
1021
0da34b6d
BG		 1022static inline void myri10ge_tx_done(struct myri10ge_priv *mgp, int mcp_index)
1023{
1024 struct pci_dev *pdev = mgp->pdev;
1025 struct myri10ge_tx_buf *tx = &mgp->tx;
1026 struct sk_buff *skb;
1027 int idx, len;
1028 int limit = 0;
1029
1030 while (tx->pkt_done != mcp_index) {
1031 idx = tx->done & tx->mask;
1032 skb = tx->info[idx].skb;
1033
1034 /* Mark as free */
1035 tx->info[idx].skb = NULL;
1036 if (tx->info[idx].last) {
1037 tx->pkt_done++;
1038 tx->info[idx].last = 0;
1039 }
1040 tx->done++;
1041 len = pci_unmap_len(&tx->info[idx], len);
1042 pci_unmap_len_set(&tx->info[idx], len, 0);
1043 if (skb) {
1044 mgp->stats.tx_bytes += skb->len;
1045 mgp->stats.tx_packets++;
1046 dev_kfree_skb_irq(skb);
1047 if (len)
1048 pci_unmap_single(pdev,
1049 pci_unmap_addr(&tx->info[idx],
1050 bus), len,
1051 PCI_DMA_TODEVICE);
1052 } else {
1053 if (len)
1054 pci_unmap_page(pdev,
1055 pci_unmap_addr(&tx->info[idx],
1056 bus), len,
1057 PCI_DMA_TODEVICE);
1058 }
1059
1060 /* limit potential for livelock by only handling
1061 * 2 full tx rings per call */
1062 if (unlikely(++limit > 2 * tx->mask))
1063 break;
1064 }
1065 /* start the queue if we've stopped it */
1066 if (netif_queue_stopped(mgp->dev)
1067 && tx->req - tx->done < (tx->mask >> 1)) {
1068 mgp->wake_queue++;
1069 netif_wake_queue(mgp->dev);
1070 }
1071}
1072
1073static inline void myri10ge_clean_rx_done(struct myri10ge_priv *mgp, int *limit)
1074{
1075 struct myri10ge_rx_done *rx_done = &mgp->rx_done;
1076 unsigned long rx_bytes = 0;
1077 unsigned long rx_packets = 0;
1078 unsigned long rx_ok;
1079
1080 int idx = rx_done->idx;
1081 int cnt = rx_done->cnt;
1082 u16 length;
40f6cff5 1083 __wsum checksum;
0da34b6d
BG		 1084
1085 while (rx_done->entry[idx].length != 0 && *limit != 0) {
1086 length = ntohs(rx_done->entry[idx].length);
1087 rx_done->entry[idx].length = 0;
40f6cff5 1088 checksum = csum_unfold(rx_done->entry[idx].checksum);
0da34b6d 1089 if (length <= mgp->small_bytes)
52ea6fb3
BG		 1090 rx_ok = myri10ge_rx_done(mgp, &mgp->rx_small,
1091 mgp->small_bytes,
1092 length, checksum);
0da34b6d 1093 else
52ea6fb3
BG		 1094 rx_ok = myri10ge_rx_done(mgp, &mgp->rx_big,
1095 mgp->big_bytes,
1096 length, checksum);
0da34b6d
BG		 1097 rx_packets += rx_ok;
1098 rx_bytes += rx_ok * (unsigned long)length;
1099 cnt++;
1100 idx = cnt & (myri10ge_max_intr_slots - 1);
1101
1102 /* limit potential for livelock by only handling a
1103 * limited number of frames. */
1104 (*limit)--;
1105 }
1106 rx_done->idx = idx;
1107 rx_done->cnt = cnt;
1108 mgp->stats.rx_packets += rx_packets;
1109 mgp->stats.rx_bytes += rx_bytes;
c7dab99b
BG		 1110
1111 /* restock receive rings if needed */
1112 if (mgp->rx_small.fill_cnt - mgp->rx_small.cnt < myri10ge_fill_thresh)
1113 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
1114 mgp->small_bytes + MXGEFW_PAD, 0);
1115 if (mgp->rx_big.fill_cnt - mgp->rx_big.cnt < myri10ge_fill_thresh)
1116 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 0);
1117
0da34b6d
BG		 1118}
1119
1120static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1121{
1122 struct mcp_irq_data *stats = mgp->fw_stats;
1123
1124 if (unlikely(stats->stats_updated)) {
1125 if (mgp->link_state != stats->link_up) {
1126 mgp->link_state = stats->link_up;
1127 if (mgp->link_state) {
c58ac5ca
BG		 1128 if (netif_msg_link(mgp))
1129 printk(KERN_INFO
1130 "myri10ge: %s: link up\n",
1131 mgp->dev->name);
0da34b6d 1132 netif_carrier_on(mgp->dev);
c58ac5ca 1133 mgp->link_changes++;
0da34b6d 1134 } else {
c58ac5ca
BG		 1135 if (netif_msg_link(mgp))
1136 printk(KERN_INFO
1137 "myri10ge: %s: link down\n",
1138 mgp->dev->name);
0da34b6d 1139 netif_carrier_off(mgp->dev);
c58ac5ca 1140 mgp->link_changes++;
0da34b6d
BG		 1141 }
1142 }
1143 if (mgp->rdma_tags_available !=
1144 ntohl(mgp->fw_stats->rdma_tags_available)) {
1145 mgp->rdma_tags_available =
1146 ntohl(mgp->fw_stats->rdma_tags_available);
1147 printk(KERN_WARNING "myri10ge: %s: RDMA timed out! "
1148 "%d tags left\n", mgp->dev->name,
1149 mgp->rdma_tags_available);
1150 }
1151 mgp->down_cnt += stats->link_down;
1152 if (stats->link_down)
1153 wake_up(&mgp->down_wq);
1154 }
1155}
1156
1157static int myri10ge_poll(struct net_device *netdev, int *budget)
1158{
1159 struct myri10ge_priv *mgp = netdev_priv(netdev);
1160 struct myri10ge_rx_done *rx_done = &mgp->rx_done;
1161 int limit, orig_limit, work_done;
1162
1163 /* process as many rx events as NAPI will allow */
1164 limit = min(*budget, netdev->quota);
1165 orig_limit = limit;
1166 myri10ge_clean_rx_done(mgp, &limit);
1167 work_done = orig_limit - limit;
1168 *budget -= work_done;
1169 netdev->quota -= work_done;
1170
1171 if (rx_done->entry[rx_done->idx].length == 0 || !netif_running(netdev)) {
1172 netif_rx_complete(netdev);
40f6cff5 1173 put_be32(htonl(3), mgp->irq_claim);
0da34b6d
BG		 1174 return 0;
1175 }
1176 return 1;
1177}
1178
7d12e780 1179static irqreturn_t myri10ge_intr(int irq, void *arg)
0da34b6d
BG		 1180{
1181 struct myri10ge_priv *mgp = arg;
1182 struct mcp_irq_data *stats = mgp->fw_stats;
1183 struct myri10ge_tx_buf *tx = &mgp->tx;
1184 u32 send_done_count;
1185 int i;
1186
1187 /* make sure it is our IRQ, and that the DMA has finished */
1188 if (unlikely(!stats->valid))
1189 return (IRQ_NONE);
1190
1191 /* low bit indicates receives are present, so schedule
1192 * napi poll handler */
1193 if (stats->valid & 1)
1194 netif_rx_schedule(mgp->dev);
1195
1196 if (!mgp->msi_enabled) {
40f6cff5 1197 put_be32(0, mgp->irq_deassert);
0da34b6d
BG		 1198 if (!myri10ge_deassert_wait)
1199 stats->valid = 0;
1200 mb();
1201 } else
1202 stats->valid = 0;
1203
1204 /* Wait for IRQ line to go low, if using INTx */
1205 i = 0;
1206 while (1) {
1207 i++;
1208 /* check for transmit completes and receives */
1209 send_done_count = ntohl(stats->send_done_count);
1210 if (send_done_count != tx->pkt_done)
1211 myri10ge_tx_done(mgp, (int)send_done_count);
1212 if (unlikely(i > myri10ge_max_irq_loops)) {
1213 printk(KERN_WARNING "myri10ge: %s: irq stuck?\n",
1214 mgp->dev->name);
1215 stats->valid = 0;
1216 schedule_work(&mgp->watchdog_work);
1217 }
1218 if (likely(stats->valid == 0))
1219 break;
1220 cpu_relax();
1221 barrier();
1222 }
1223
1224 myri10ge_check_statblock(mgp);
1225
40f6cff5 1226 put_be32(htonl(3), mgp->irq_claim + 1);
0da34b6d
BG		 1227 return (IRQ_HANDLED);
1228}
1229
1230static int
1231myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1232{
1233 cmd->autoneg = AUTONEG_DISABLE;
1234 cmd->speed = SPEED_10000;
1235 cmd->duplex = DUPLEX_FULL;
1236 return 0;
1237}
1238
1239static void
1240myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1241{
1242 struct myri10ge_priv *mgp = netdev_priv(netdev);
1243
1244 strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1245 strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1246 strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1247 strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1248}
1249
1250static int
1251myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1252{
1253 struct myri10ge_priv *mgp = netdev_priv(netdev);
1254 coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1255 return 0;
1256}
1257
1258static int
1259myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1260{
1261 struct myri10ge_priv *mgp = netdev_priv(netdev);
1262
1263 mgp->intr_coal_delay = coal->rx_coalesce_usecs;
40f6cff5 1264 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d
BG		 1265 return 0;
1266}
1267
1268static void
1269myri10ge_get_pauseparam(struct net_device *netdev,
1270 struct ethtool_pauseparam *pause)
1271{
1272 struct myri10ge_priv *mgp = netdev_priv(netdev);
1273
1274 pause->autoneg = 0;
1275 pause->rx_pause = mgp->pause;
1276 pause->tx_pause = mgp->pause;
1277}
1278
1279static int
1280myri10ge_set_pauseparam(struct net_device *netdev,
1281 struct ethtool_pauseparam *pause)
1282{
1283 struct myri10ge_priv *mgp = netdev_priv(netdev);
1284
1285 if (pause->tx_pause != mgp->pause)
1286 return myri10ge_change_pause(mgp, pause->tx_pause);
1287 if (pause->rx_pause != mgp->pause)
1288 return myri10ge_change_pause(mgp, pause->tx_pause);
1289 if (pause->autoneg != 0)
1290 return -EINVAL;
1291 return 0;
1292}
1293
1294static void
1295myri10ge_get_ringparam(struct net_device *netdev,
1296 struct ethtool_ringparam *ring)
1297{
1298 struct myri10ge_priv *mgp = netdev_priv(netdev);
1299
1300 ring->rx_mini_max_pending = mgp->rx_small.mask + 1;
1301 ring->rx_max_pending = mgp->rx_big.mask + 1;
1302 ring->rx_jumbo_max_pending = 0;
1303 ring->tx_max_pending = mgp->rx_small.mask + 1;
1304 ring->rx_mini_pending = ring->rx_mini_max_pending;
1305 ring->rx_pending = ring->rx_max_pending;
1306 ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1307 ring->tx_pending = ring->tx_max_pending;
1308}
1309
1310static u32 myri10ge_get_rx_csum(struct net_device *netdev)
1311{
1312 struct myri10ge_priv *mgp = netdev_priv(netdev);
1313 if (mgp->csum_flag)
1314 return 1;
1315 else
1316 return 0;
1317}
1318
1319static int myri10ge_set_rx_csum(struct net_device *netdev, u32 csum_enabled)
1320{
1321 struct myri10ge_priv *mgp = netdev_priv(netdev);
1322 if (csum_enabled)
1323 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
1324 else
1325 mgp->csum_flag = 0;
1326 return 0;
1327}
1328
1329static const char myri10ge_gstrings_stats[][ETH_GSTRING_LEN] = {
1330 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1331 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1332 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1333 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1334 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1335 "tx_heartbeat_errors", "tx_window_errors",
1336 /* device-specific stats */
2c1a1088 1337 "tx_boundary", "WC", "irq", "MSI",
0da34b6d
BG		 1338 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
1339 "serial_number", "tx_pkt_start", "tx_pkt_done",
1340 "tx_req", "tx_done", "rx_small_cnt", "rx_big_cnt",
1341 "wake_queue", "stop_queue", "watchdog_resets", "tx_linearized",
c58ac5ca 1342 "link_changes", "link_up", "dropped_link_overflow",
85a7ea1b 1343 "dropped_link_error_or_filtered", "dropped_multicast_filtered",
0da34b6d
BG		 1344 "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
1345 "dropped_no_big_buffer"
1346};
1347
1348#define MYRI10GE_NET_STATS_LEN 21
1349#define MYRI10GE_STATS_LEN sizeof(myri10ge_gstrings_stats) / ETH_GSTRING_LEN
1350
1351static void
1352myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1353{
1354 switch (stringset) {
1355 case ETH_SS_STATS:
1356 memcpy(data, *myri10ge_gstrings_stats,
1357 sizeof(myri10ge_gstrings_stats));
1358 break;
1359 }
1360}
1361
1362static int myri10ge_get_stats_count(struct net_device *netdev)
1363{
1364 return MYRI10GE_STATS_LEN;
1365}
1366
1367static void
1368myri10ge_get_ethtool_stats(struct net_device *netdev,
1369 struct ethtool_stats *stats, u64 * data)
1370{
1371 struct myri10ge_priv *mgp = netdev_priv(netdev);
1372 int i;
1373
1374 for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
1375 data[i] = ((unsigned long *)&mgp->stats)[i];
1376
2c1a1088
BG		 1377 data[i++] = (unsigned int)mgp->tx.boundary;
1378 data[i++] = (unsigned int)(mgp->mtrr >= 0);
1379 data[i++] = (unsigned int)mgp->pdev->irq;
1380 data[i++] = (unsigned int)mgp->msi_enabled;
0da34b6d
BG		 1381 data[i++] = (unsigned int)mgp->read_dma;
1382 data[i++] = (unsigned int)mgp->write_dma;
1383 data[i++] = (unsigned int)mgp->read_write_dma;
1384 data[i++] = (unsigned int)mgp->serial_number;
1385 data[i++] = (unsigned int)mgp->tx.pkt_start;
1386 data[i++] = (unsigned int)mgp->tx.pkt_done;
1387 data[i++] = (unsigned int)mgp->tx.req;
1388 data[i++] = (unsigned int)mgp->tx.done;
1389 data[i++] = (unsigned int)mgp->rx_small.cnt;
1390 data[i++] = (unsigned int)mgp->rx_big.cnt;
1391 data[i++] = (unsigned int)mgp->wake_queue;
1392 data[i++] = (unsigned int)mgp->stop_queue;
1393 data[i++] = (unsigned int)mgp->watchdog_resets;
1394 data[i++] = (unsigned int)mgp->tx_linearized;
c58ac5ca 1395 data[i++] = (unsigned int)mgp->link_changes;
0da34b6d
BG		 1396 data[i++] = (unsigned int)ntohl(mgp->fw_stats->link_up);
1397 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_link_overflow);
1398 data[i++] =
1399 (unsigned int)ntohl(mgp->fw_stats->dropped_link_error_or_filtered);
85a7ea1b
BG		 1400 data[i++] =
1401 (unsigned int)ntohl(mgp->fw_stats->dropped_multicast_filtered);
0da34b6d
BG		 1402 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_runt);
1403 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_overrun);
1404 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_small_buffer);
1405 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_big_buffer);
1406}
1407
c58ac5ca
BG		 1408static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
1409{
1410 struct myri10ge_priv *mgp = netdev_priv(netdev);
1411 mgp->msg_enable = value;
1412}
1413
1414static u32 myri10ge_get_msglevel(struct net_device *netdev)
1415{
1416 struct myri10ge_priv *mgp = netdev_priv(netdev);
1417 return mgp->msg_enable;
1418}
1419
7282d491 1420static const struct ethtool_ops myri10ge_ethtool_ops = {
0da34b6d
BG		 1421 .get_settings = myri10ge_get_settings,
1422 .get_drvinfo = myri10ge_get_drvinfo,
1423 .get_coalesce = myri10ge_get_coalesce,
1424 .set_coalesce = myri10ge_set_coalesce,
1425 .get_pauseparam = myri10ge_get_pauseparam,
1426 .set_pauseparam = myri10ge_set_pauseparam,
1427 .get_ringparam = myri10ge_get_ringparam,
1428 .get_rx_csum = myri10ge_get_rx_csum,
1429 .set_rx_csum = myri10ge_set_rx_csum,
1430 .get_tx_csum = ethtool_op_get_tx_csum,
b10c0668 1431 .set_tx_csum = ethtool_op_set_tx_hw_csum,
0da34b6d
BG		 1432 .get_sg = ethtool_op_get_sg,
1433 .set_sg = ethtool_op_set_sg,
0da34b6d
BG		 1434 .get_tso = ethtool_op_get_tso,
1435 .set_tso = ethtool_op_set_tso,
0da34b6d
BG		 1436 .get_strings = myri10ge_get_strings,
1437 .get_stats_count = myri10ge_get_stats_count,
c58ac5ca
BG		 1438 .get_ethtool_stats = myri10ge_get_ethtool_stats,
1439 .set_msglevel = myri10ge_set_msglevel,
1440 .get_msglevel = myri10ge_get_msglevel
0da34b6d
BG		 1441};
1442
1443static int myri10ge_allocate_rings(struct net_device *dev)
1444{
1445 struct myri10ge_priv *mgp;
1446 struct myri10ge_cmd cmd;
1447 int tx_ring_size, rx_ring_size;
1448 int tx_ring_entries, rx_ring_entries;
1449 int i, status;
1450 size_t bytes;
1451
1452 mgp = netdev_priv(dev);
1453
1454 /* get ring sizes */
1455
1456 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1457 tx_ring_size = cmd.data0;
1458 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
1459 rx_ring_size = cmd.data0;
1460
1461 tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1462 rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
1463 mgp->tx.mask = tx_ring_entries - 1;
1464 mgp->rx_small.mask = mgp->rx_big.mask = rx_ring_entries - 1;
1465
1466 /* allocate the host shadow rings */
1467
1468 bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
1469 * sizeof(*mgp->tx.req_list);
1470 mgp->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
1471 if (mgp->tx.req_bytes == NULL)
1472 goto abort_with_nothing;
1473
1474 /* ensure req_list entries are aligned to 8 bytes */
1475 mgp->tx.req_list = (struct mcp_kreq_ether_send *)
1476 ALIGN((unsigned long)mgp->tx.req_bytes, 8);
1477
1478 bytes = rx_ring_entries * sizeof(*mgp->rx_small.shadow);
1479 mgp->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
1480 if (mgp->rx_small.shadow == NULL)
1481 goto abort_with_tx_req_bytes;
1482
1483 bytes = rx_ring_entries * sizeof(*mgp->rx_big.shadow);
1484 mgp->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
1485 if (mgp->rx_big.shadow == NULL)
1486 goto abort_with_rx_small_shadow;
1487
1488 /* allocate the host info rings */
1489
1490 bytes = tx_ring_entries * sizeof(*mgp->tx.info);
1491 mgp->tx.info = kzalloc(bytes, GFP_KERNEL);
1492 if (mgp->tx.info == NULL)
1493 goto abort_with_rx_big_shadow;
1494
1495 bytes = rx_ring_entries * sizeof(*mgp->rx_small.info);
1496 mgp->rx_small.info = kzalloc(bytes, GFP_KERNEL);
1497 if (mgp->rx_small.info == NULL)
1498 goto abort_with_tx_info;
1499
1500 bytes = rx_ring_entries * sizeof(*mgp->rx_big.info);
1501 mgp->rx_big.info = kzalloc(bytes, GFP_KERNEL);
1502 if (mgp->rx_big.info == NULL)
1503 goto abort_with_rx_small_info;
1504
1505 /* Fill the receive rings */
c7dab99b
BG		 1506 mgp->rx_big.cnt = 0;
1507 mgp->rx_small.cnt = 0;
1508 mgp->rx_big.fill_cnt = 0;
1509 mgp->rx_small.fill_cnt = 0;
1510 mgp->rx_small.page_offset = MYRI10GE_ALLOC_SIZE;
1511 mgp->rx_big.page_offset = MYRI10GE_ALLOC_SIZE;
1512 mgp->rx_small.watchdog_needed = 0;
1513 mgp->rx_big.watchdog_needed = 0;
1514 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
1515 mgp->small_bytes + MXGEFW_PAD, 0);
0da34b6d 1516
c7dab99b
BG		 1517 if (mgp->rx_small.fill_cnt < mgp->rx_small.mask + 1) {
1518 printk(KERN_ERR "myri10ge: %s: alloced only %d small bufs\n",
1519 dev->name, mgp->rx_small.fill_cnt);
1520 goto abort_with_rx_small_ring;
0da34b6d
BG		 1521 }
1522
c7dab99b
BG		 1523 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 0);
1524 if (mgp->rx_big.fill_cnt < mgp->rx_big.mask + 1) {
1525 printk(KERN_ERR "myri10ge: %s: alloced only %d big bufs\n",
1526 dev->name, mgp->rx_big.fill_cnt);
1527 goto abort_with_rx_big_ring;
0da34b6d
BG		 1528 }
1529
1530 return 0;
1531
1532abort_with_rx_big_ring:
c7dab99b
BG		 1533 for (i = mgp->rx_big.cnt; i < mgp->rx_big.fill_cnt; i++) {
1534 int idx = i & mgp->rx_big.mask;
1535 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_big.info[idx],
1536 mgp->big_bytes);
1537 put_page(mgp->rx_big.info[idx].page);
0da34b6d
BG		 1538 }
1539
1540abort_with_rx_small_ring:
c7dab99b
BG		 1541 for (i = mgp->rx_small.cnt; i < mgp->rx_small.fill_cnt; i++) {
1542 int idx = i & mgp->rx_small.mask;
1543 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_small.info[idx],
1544 mgp->small_bytes + MXGEFW_PAD);
1545 put_page(mgp->rx_small.info[idx].page);
0da34b6d 1546 }
c7dab99b 1547
0da34b6d
BG		 1548 kfree(mgp->rx_big.info);
1549
1550abort_with_rx_small_info:
1551 kfree(mgp->rx_small.info);
1552
1553abort_with_tx_info:
1554 kfree(mgp->tx.info);
1555
1556abort_with_rx_big_shadow:
1557 kfree(mgp->rx_big.shadow);
1558
1559abort_with_rx_small_shadow:
1560 kfree(mgp->rx_small.shadow);
1561
1562abort_with_tx_req_bytes:
1563 kfree(mgp->tx.req_bytes);
1564 mgp->tx.req_bytes = NULL;
1565 mgp->tx.req_list = NULL;
1566
1567abort_with_nothing:
1568 return status;
1569}
1570
1571static void myri10ge_free_rings(struct net_device *dev)
1572{
1573 struct myri10ge_priv *mgp;
1574 struct sk_buff *skb;
1575 struct myri10ge_tx_buf *tx;
1576 int i, len, idx;
1577
1578 mgp = netdev_priv(dev);
1579
c7dab99b
BG		 1580 for (i = mgp->rx_big.cnt; i < mgp->rx_big.fill_cnt; i++) {
1581 idx = i & mgp->rx_big.mask;
1582 if (i == mgp->rx_big.fill_cnt - 1)
1583 mgp->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE;
1584 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_big.info[idx],
1585 mgp->big_bytes);
1586 put_page(mgp->rx_big.info[idx].page);
0da34b6d
BG		 1587 }
1588
c7dab99b
BG		 1589 for (i = mgp->rx_small.cnt; i < mgp->rx_small.fill_cnt; i++) {
1590 idx = i & mgp->rx_small.mask;
1591 if (i == mgp->rx_small.fill_cnt - 1)
1592 mgp->rx_small.info[idx].page_offset =
1593 MYRI10GE_ALLOC_SIZE;
1594 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_small.info[idx],
1595 mgp->small_bytes + MXGEFW_PAD);
1596 put_page(mgp->rx_small.info[idx].page);
1597 }
0da34b6d
BG		 1598 tx = &mgp->tx;
1599 while (tx->done != tx->req) {
1600 idx = tx->done & tx->mask;
1601 skb = tx->info[idx].skb;
1602
1603 /* Mark as free */
1604 tx->info[idx].skb = NULL;
1605 tx->done++;
1606 len = pci_unmap_len(&tx->info[idx], len);
1607 pci_unmap_len_set(&tx->info[idx], len, 0);
1608 if (skb) {
1609 mgp->stats.tx_dropped++;
1610 dev_kfree_skb_any(skb);
1611 if (len)
1612 pci_unmap_single(mgp->pdev,
1613 pci_unmap_addr(&tx->info[idx],
1614 bus), len,
1615 PCI_DMA_TODEVICE);
1616 } else {
1617 if (len)
1618 pci_unmap_page(mgp->pdev,
1619 pci_unmap_addr(&tx->info[idx],
1620 bus), len,
1621 PCI_DMA_TODEVICE);
1622 }
1623 }
1624 kfree(mgp->rx_big.info);
1625
1626 kfree(mgp->rx_small.info);
1627
1628 kfree(mgp->tx.info);
1629
1630 kfree(mgp->rx_big.shadow);
1631
1632 kfree(mgp->rx_small.shadow);
1633
1634 kfree(mgp->tx.req_bytes);
1635 mgp->tx.req_bytes = NULL;
1636 mgp->tx.req_list = NULL;
1637}
1638
df30a740
BG		 1639static int myri10ge_request_irq(struct myri10ge_priv *mgp)
1640{
1641 struct pci_dev *pdev = mgp->pdev;
1642 int status;
1643
1644 if (myri10ge_msi) {
1645 status = pci_enable_msi(pdev);
1646 if (status != 0)
1647 dev_err(&pdev->dev,
1648 "Error %d setting up MSI; falling back to xPIC\n",
1649 status);
1650 else
1651 mgp->msi_enabled = 1;
1652 } else {
1653 mgp->msi_enabled = 0;
1654 }
1655 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
1656 mgp->dev->name, mgp);
1657 if (status != 0) {
1658 dev_err(&pdev->dev, "failed to allocate IRQ\n");
1659 if (mgp->msi_enabled)
1660 pci_disable_msi(pdev);
1661 }
1662 return status;
1663}
1664
1665static void myri10ge_free_irq(struct myri10ge_priv *mgp)
1666{
1667 struct pci_dev *pdev = mgp->pdev;
1668
1669 free_irq(pdev->irq, mgp);
1670 if (mgp->msi_enabled)
1671 pci_disable_msi(pdev);
1672}
1673
0da34b6d
BG		 1674static int myri10ge_open(struct net_device *dev)
1675{
1676 struct myri10ge_priv *mgp;
1677 struct myri10ge_cmd cmd;
1678 int status, big_pow2;
1679
1680 mgp = netdev_priv(dev);
1681
1682 if (mgp->running != MYRI10GE_ETH_STOPPED)
1683 return -EBUSY;
1684
1685 mgp->running = MYRI10GE_ETH_STARTING;
1686 status = myri10ge_reset(mgp);
1687 if (status != 0) {
1688 printk(KERN_ERR "myri10ge: %s: failed reset\n", dev->name);
df30a740 1689 goto abort_with_nothing;
0da34b6d
BG		 1690 }
1691
df30a740
BG		 1692 status = myri10ge_request_irq(mgp);
1693 if (status != 0)
1694 goto abort_with_nothing;
1695
0da34b6d
BG		 1696 /* decide what small buffer size to use. For good TCP rx
1697 * performance, it is important to not receive 1514 byte
1698 * frames into jumbo buffers, as it confuses the socket buffer
1699 * accounting code, leading to drops and erratic performance.
1700 */
1701
1702 if (dev->mtu <= ETH_DATA_LEN)
c7dab99b
BG		 1703 /* enough for a TCP header */
1704 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
1705 ? (128 - MXGEFW_PAD)
1706 : (SMP_CACHE_BYTES - MXGEFW_PAD);
0da34b6d 1707 else
de3c4507
BG		 1708 /* enough for a vlan encapsulated ETH_DATA_LEN frame */
1709 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
0da34b6d
BG		 1710
1711 /* Override the small buffer size? */
1712 if (myri10ge_small_bytes > 0)
1713 mgp->small_bytes = myri10ge_small_bytes;
1714
0da34b6d
BG		 1715 /* get the lanai pointers to the send and receive rings */
1716
1717 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET, &cmd, 0);
1718 mgp->tx.lanai =
1719 (struct mcp_kreq_ether_send __iomem *)(mgp->sram + cmd.data0);
1720
1721 status |=
1722 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET, &cmd, 0);
1723 mgp->rx_small.lanai =
1724 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1725
1726 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
1727 mgp->rx_big.lanai =
1728 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1729
1730 if (status != 0) {
1731 printk(KERN_ERR
1732 "myri10ge: %s: failed to get ring sizes or locations\n",
1733 dev->name);
1734 mgp->running = MYRI10GE_ETH_STOPPED;
df30a740 1735 goto abort_with_irq;
0da34b6d
BG		 1736 }
1737
6ebc087a 1738 if (myri10ge_wcfifo && mgp->mtrr >= 0) {
e700f9f4
BG		 1739 mgp->tx.wc_fifo = (u8 __iomem *) mgp->sram + MXGEFW_ETH_SEND_4;
1740 mgp->rx_small.wc_fifo =
1741 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_SMALL;
1742 mgp->rx_big.wc_fifo =
1743 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_BIG;
0da34b6d
BG		 1744 } else {
1745 mgp->tx.wc_fifo = NULL;
1746 mgp->rx_small.wc_fifo = NULL;
1747 mgp->rx_big.wc_fifo = NULL;
1748 }
1749
0da34b6d
BG		 1750 /* Firmware needs the big buff size as a power of 2. Lie and
1751 * tell him the buffer is larger, because we only use 1
1752 * buffer/pkt, and the mtu will prevent overruns.
1753 */
13348bee 1754 big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b
BG		 1755 if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) {
1756 while ((big_pow2 & (big_pow2 - 1)) != 0)
1757 big_pow2++;
13348bee 1758 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b
BG		 1759 } else {
1760 big_pow2 = MYRI10GE_ALLOC_SIZE;
1761 mgp->big_bytes = big_pow2;
1762 }
1763
1764 status = myri10ge_allocate_rings(dev);
1765 if (status != 0)
df30a740 1766 goto abort_with_irq;
0da34b6d
BG		 1767
1768 /* now give firmware buffers sizes, and MTU */
1769 cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
1770 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
1771 cmd.data0 = mgp->small_bytes;
1772 status |=
1773 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
1774 cmd.data0 = big_pow2;
1775 status |=
1776 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
1777 if (status) {
1778 printk(KERN_ERR "myri10ge: %s: Couldn't set buffer sizes\n",
1779 dev->name);
1780 goto abort_with_rings;
1781 }
1782
1783 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->fw_stats_bus);
1784 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->fw_stats_bus);
85a7ea1b
BG		 1785 cmd.data2 = sizeof(struct mcp_irq_data);
1786 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
1787 if (status == -ENOSYS) {
1788 dma_addr_t bus = mgp->fw_stats_bus;
1789 bus += offsetof(struct mcp_irq_data, send_done_count);
1790 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
1791 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
1792 status = myri10ge_send_cmd(mgp,
1793 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
1794 &cmd, 0);
1795 /* Firmware cannot support multicast without STATS_DMA_V2 */
1796 mgp->fw_multicast_support = 0;
1797 } else {
1798 mgp->fw_multicast_support = 1;
1799 }
0da34b6d
BG		 1800 if (status) {
1801 printk(KERN_ERR "myri10ge: %s: Couldn't set stats DMA\n",
1802 dev->name);
1803 goto abort_with_rings;
1804 }
1805
40f6cff5 1806 mgp->link_state = htonl(~0U);
0da34b6d
BG		 1807 mgp->rdma_tags_available = 15;
1808
1809 netif_poll_enable(mgp->dev); /* must happen prior to any irq */
1810
1811 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
1812 if (status) {
1813 printk(KERN_ERR "myri10ge: %s: Couldn't bring up link\n",
1814 dev->name);
1815 goto abort_with_rings;
1816 }
1817
1818 mgp->wake_queue = 0;
1819 mgp->stop_queue = 0;
1820 mgp->running = MYRI10GE_ETH_RUNNING;
1821 mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
1822 add_timer(&mgp->watchdog_timer);
1823 netif_wake_queue(dev);
1824 return 0;
1825
1826abort_with_rings:
1827 myri10ge_free_rings(dev);
1828
df30a740
BG		 1829abort_with_irq:
1830 myri10ge_free_irq(mgp);
1831
0da34b6d
BG		 1832abort_with_nothing:
1833 mgp->running = MYRI10GE_ETH_STOPPED;
1834 return -ENOMEM;
1835}
1836
1837static int myri10ge_close(struct net_device *dev)
1838{
1839 struct myri10ge_priv *mgp;
1840 struct myri10ge_cmd cmd;
1841 int status, old_down_cnt;
1842
1843 mgp = netdev_priv(dev);
1844
1845 if (mgp->running != MYRI10GE_ETH_RUNNING)
1846 return 0;
1847
1848 if (mgp->tx.req_bytes == NULL)
1849 return 0;
1850
1851 del_timer_sync(&mgp->watchdog_timer);
1852 mgp->running = MYRI10GE_ETH_STOPPING;
1853 netif_poll_disable(mgp->dev);
1854 netif_carrier_off(dev);
1855 netif_stop_queue(dev);
1856 old_down_cnt = mgp->down_cnt;
1857 mb();
1858 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
1859 if (status)
1860 printk(KERN_ERR "myri10ge: %s: Couldn't bring down link\n",
1861 dev->name);
1862
1863 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt, HZ);
1864 if (old_down_cnt == mgp->down_cnt)
1865 printk(KERN_ERR "myri10ge: %s never got down irq\n", dev->name);
1866
1867 netif_tx_disable(dev);
df30a740 1868 myri10ge_free_irq(mgp);
0da34b6d
BG		 1869 myri10ge_free_rings(dev);
1870
1871 mgp->running = MYRI10GE_ETH_STOPPED;
1872 return 0;
1873}
1874
1875/* copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
1876 * backwards one at a time and handle ring wraps */
1877
1878static inline void
1879myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
1880 struct mcp_kreq_ether_send *src, int cnt)
1881{
1882 int idx, starting_slot;
1883 starting_slot = tx->req;
1884 while (cnt > 1) {
1885 cnt--;
1886 idx = (starting_slot + cnt) & tx->mask;
1887 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
1888 mb();
1889 }
1890}
1891
1892/*
1893 * copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
1894 * at most 32 bytes at a time, so as to avoid involving the software
1895 * pio handler in the nic. We re-write the first segment's flags
1896 * to mark them valid only after writing the entire chain.
1897 */
1898
1899static inline void
1900myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
1901 int cnt)
1902{
1903 int idx, i;
1904 struct mcp_kreq_ether_send __iomem *dstp, *dst;
1905 struct mcp_kreq_ether_send *srcp;
1906 u8 last_flags;
1907
1908 idx = tx->req & tx->mask;
1909
1910 last_flags = src->flags;
1911 src->flags = 0;
1912 mb();
1913 dst = dstp = &tx->lanai[idx];
1914 srcp = src;
1915
1916 if ((idx + cnt) < tx->mask) {
1917 for (i = 0; i < (cnt - 1); i += 2) {
1918 myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
1919 mb(); /* force write every 32 bytes */
1920 srcp += 2;
1921 dstp += 2;
1922 }
1923 } else {
1924 /* submit all but the first request, and ensure
1925 * that it is submitted below */
1926 myri10ge_submit_req_backwards(tx, src, cnt);
1927 i = 0;
1928 }
1929 if (i < cnt) {
1930 /* submit the first request */
1931 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
1932 mb(); /* barrier before setting valid flag */
1933 }
1934
1935 /* re-write the last 32-bits with the valid flags */
1936 src->flags = last_flags;
40f6cff5 1937 put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
0da34b6d
BG		 1938 tx->req += cnt;
1939 mb();
1940}
1941
1942static inline void
1943myri10ge_submit_req_wc(struct myri10ge_tx_buf *tx,
1944 struct mcp_kreq_ether_send *src, int cnt)
1945{
1946 tx->req += cnt;
1947 mb();
1948 while (cnt >= 4) {
1949 myri10ge_pio_copy(tx->wc_fifo, src, 64);
1950 mb();
1951 src += 4;
1952 cnt -= 4;
1953 }
1954 if (cnt > 0) {
1955 /* pad it to 64 bytes. The src is 64 bytes bigger than it
1956 * needs to be so that we don't overrun it */
e700f9f4
BG		 1957 myri10ge_pio_copy(tx->wc_fifo + MXGEFW_ETH_SEND_OFFSET(cnt),
1958 src, 64);
0da34b6d
BG		 1959 mb();
1960 }
1961}
1962
1963/*
1964 * Transmit a packet. We need to split the packet so that a single
1965 * segment does not cross myri10ge->tx.boundary, so this makes segment
1966 * counting tricky. So rather than try to count segments up front, we
1967 * just give up if there are too few segments to hold a reasonably
1968 * fragmented packet currently available. If we run
1969 * out of segments while preparing a packet for DMA, we just linearize
1970 * it and try again.
1971 */
1972
1973static int myri10ge_xmit(struct sk_buff *skb, struct net_device *dev)
1974{
1975 struct myri10ge_priv *mgp = netdev_priv(dev);
1976 struct mcp_kreq_ether_send *req;
1977 struct myri10ge_tx_buf *tx = &mgp->tx;
1978 struct skb_frag_struct *frag;
1979 dma_addr_t bus;
40f6cff5
AV		 1980 u32 low;
1981 __be32 high_swapped;
0da34b6d
BG		 1982 unsigned int len;
1983 int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
1984 u16 pseudo_hdr_offset, cksum_offset;
1985 int cum_len, seglen, boundary, rdma_count;
1986 u8 flags, odd_flag;
1987
1988again:
1989 req = tx->req_list;
1990 avail = tx->mask - 1 - (tx->req - tx->done);
1991
1992 mss = 0;
1993 max_segments = MXGEFW_MAX_SEND_DESC;
1994
0da34b6d 1995 if (skb->len > (dev->mtu + ETH_HLEN)) {
7967168c 1996 mss = skb_shinfo(skb)->gso_size;
0da34b6d
BG		 1997 if (mss != 0)
1998 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
1999 }
0da34b6d
BG		 2000
2001 if ((unlikely(avail < max_segments))) {
2002 /* we are out of transmit resources */
2003 mgp->stop_queue++;
2004 netif_stop_queue(dev);
2005 return 1;
2006 }
2007
2008 /* Setup checksum offloading, if needed */
2009 cksum_offset = 0;
2010 pseudo_hdr_offset = 0;
2011 odd_flag = 0;
2012 flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
84fa7933 2013 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
0da34b6d 2014 cksum_offset = (skb->h.raw - skb->data);
ff1dcadb 2015 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
0da34b6d
BG		 2016 /* If the headers are excessively large, then we must
2017 * fall back to a software checksum */
2018 if (unlikely(cksum_offset > 255 || pseudo_hdr_offset > 127)) {
84fa7933 2019 if (skb_checksum_help(skb))
0da34b6d
BG		 2020 goto drop;
2021 cksum_offset = 0;
2022 pseudo_hdr_offset = 0;
2023 } else {
0da34b6d
BG		 2024 odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2025 flags |= MXGEFW_FLAGS_CKSUM;
2026 }
2027 }
2028
2029 cum_len = 0;
2030
0da34b6d
BG		 2031 if (mss) { /* TSO */
2032 /* this removes any CKSUM flag from before */
2033 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
2034
2035 /* negative cum_len signifies to the
2036 * send loop that we are still in the
2037 * header portion of the TSO packet.
2038 * TSO header must be at most 134 bytes long */
2039 cum_len = -((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
2040
2041 /* for TSO, pseudo_hdr_offset holds mss.
2042 * The firmware figures out where to put
2043 * the checksum by parsing the header. */
40f6cff5 2044 pseudo_hdr_offset = mss;
0da34b6d 2045 } else
0da34b6d
BG		 2046 /* Mark small packets, and pad out tiny packets */
2047 if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
2048 flags |= MXGEFW_FLAGS_SMALL;
2049
2050 /* pad frames to at least ETH_ZLEN bytes */
2051 if (unlikely(skb->len < ETH_ZLEN)) {
5b057c6b 2052 if (skb_padto(skb, ETH_ZLEN)) {
0da34b6d
BG		 2053 /* The packet is gone, so we must
2054 * return 0 */
2055 mgp->stats.tx_dropped += 1;
2056 return 0;
2057 }
2058 /* adjust the len to account for the zero pad
2059 * so that the nic can know how long it is */
2060 skb->len = ETH_ZLEN;
2061 }
2062 }
2063
2064 /* map the skb for DMA */
2065 len = skb->len - skb->data_len;
2066 idx = tx->req & tx->mask;
2067 tx->info[idx].skb = skb;
2068 bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
2069 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2070 pci_unmap_len_set(&tx->info[idx], len, len);
2071
2072 frag_cnt = skb_shinfo(skb)->nr_frags;
2073 frag_idx = 0;
2074 count = 0;
2075 rdma_count = 0;
2076
2077 /* "rdma_count" is the number of RDMAs belonging to the
2078 * current packet BEFORE the current send request. For
2079 * non-TSO packets, this is equal to "count".
2080 * For TSO packets, rdma_count needs to be reset
2081 * to 0 after a segment cut.
2082 *
2083 * The rdma_count field of the send request is
2084 * the number of RDMAs of the packet starting at
2085 * that request. For TSO send requests with one ore more cuts
2086 * in the middle, this is the number of RDMAs starting
2087 * after the last cut in the request. All previous
2088 * segments before the last cut implicitly have 1 RDMA.
2089 *
2090 * Since the number of RDMAs is not known beforehand,
2091 * it must be filled-in retroactively - after each
2092 * segmentation cut or at the end of the entire packet.
2093 */
2094
2095 while (1) {
2096 /* Break the SKB or Fragment up into pieces which
2097 * do not cross mgp->tx.boundary */
2098 low = MYRI10GE_LOWPART_TO_U32(bus);
2099 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2100 while (len) {
2101 u8 flags_next;
2102 int cum_len_next;
2103
2104 if (unlikely(count == max_segments))
2105 goto abort_linearize;
2106
2107 boundary = (low + tx->boundary) & ~(tx->boundary - 1);
2108 seglen = boundary - low;
2109 if (seglen > len)
2110 seglen = len;
2111 flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2112 cum_len_next = cum_len + seglen;
0da34b6d
BG		 2113 if (mss) { /* TSO */
2114 (req - rdma_count)->rdma_count = rdma_count + 1;
2115
2116 if (likely(cum_len >= 0)) { /* payload */
2117 int next_is_first, chop;
2118
2119 chop = (cum_len_next > mss);
2120 cum_len_next = cum_len_next % mss;
2121 next_is_first = (cum_len_next == 0);
2122 flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2123 flags_next |= next_is_first *
2124 MXGEFW_FLAGS_FIRST;
2125 rdma_count |= -(chop | next_is_first);
2126 rdma_count += chop & !next_is_first;
2127 } else if (likely(cum_len_next >= 0)) { /* header ends */
2128 int small;
2129
2130 rdma_count = -1;
2131 cum_len_next = 0;
2132 seglen = -cum_len;
2133 small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2134 flags_next = MXGEFW_FLAGS_TSO_PLD |
2135 MXGEFW_FLAGS_FIRST |
2136 (small * MXGEFW_FLAGS_SMALL);
2137 }
2138 }
0da34b6d
BG		 2139 req->addr_high = high_swapped;
2140 req->addr_low = htonl(low);
40f6cff5 2141 req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
0da34b6d
BG		 2142 req->pad = 0; /* complete solid 16-byte block; does this matter? */
2143 req->rdma_count = 1;
2144 req->length = htons(seglen);
2145 req->cksum_offset = cksum_offset;
2146 req->flags = flags | ((cum_len & 1) * odd_flag);
2147
2148 low += seglen;
2149 len -= seglen;
2150 cum_len = cum_len_next;
2151 flags = flags_next;
2152 req++;
2153 count++;
2154 rdma_count++;
2155 if (unlikely(cksum_offset > seglen))
2156 cksum_offset -= seglen;
2157 else
2158 cksum_offset = 0;
2159 }
2160 if (frag_idx == frag_cnt)
2161 break;
2162
2163 /* map next fragment for DMA */
2164 idx = (count + tx->req) & tx->mask;
2165 frag = &skb_shinfo(skb)->frags[frag_idx];
2166 frag_idx++;
2167 len = frag->size;
2168 bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset,
2169 len, PCI_DMA_TODEVICE);
2170 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2171 pci_unmap_len_set(&tx->info[idx], len, len);
2172 }
2173
2174 (req - rdma_count)->rdma_count = rdma_count;
0da34b6d
BG		 2175 if (mss)
2176 do {
2177 req--;
2178 req->flags |= MXGEFW_FLAGS_TSO_LAST;
2179 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2180 MXGEFW_FLAGS_FIRST)));
0da34b6d
BG		 2181 idx = ((count - 1) + tx->req) & tx->mask;
2182 tx->info[idx].last = 1;
2183 if (tx->wc_fifo == NULL)
2184 myri10ge_submit_req(tx, tx->req_list, count);
2185 else
2186 myri10ge_submit_req_wc(tx, tx->req_list, count);
2187 tx->pkt_start++;
2188 if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
2189 mgp->stop_queue++;
2190 netif_stop_queue(dev);
2191 }
2192 dev->trans_start = jiffies;
2193 return 0;
2194
2195abort_linearize:
2196 /* Free any DMA resources we've alloced and clear out the skb
2197 * slot so as to not trip up assertions, and to avoid a
2198 * double-free if linearizing fails */
2199
2200 last_idx = (idx + 1) & tx->mask;
2201 idx = tx->req & tx->mask;
2202 tx->info[idx].skb = NULL;
2203 do {
2204 len = pci_unmap_len(&tx->info[idx], len);
2205 if (len) {
2206 if (tx->info[idx].skb != NULL)
2207 pci_unmap_single(mgp->pdev,
2208 pci_unmap_addr(&tx->info[idx],
2209 bus), len,
2210 PCI_DMA_TODEVICE);
2211 else
2212 pci_unmap_page(mgp->pdev,
2213 pci_unmap_addr(&tx->info[idx],
2214 bus), len,
2215 PCI_DMA_TODEVICE);
2216 pci_unmap_len_set(&tx->info[idx], len, 0);
2217 tx->info[idx].skb = NULL;
2218 }
2219 idx = (idx + 1) & tx->mask;
2220 } while (idx != last_idx);
89114afd 2221 if (skb_is_gso(skb)) {
0da34b6d
BG		 2222 printk(KERN_ERR
2223 "myri10ge: %s: TSO but wanted to linearize?!?!?\n",
2224 mgp->dev->name);
2225 goto drop;
2226 }
2227
bec0e859 2228 if (skb_linearize(skb))
0da34b6d
BG		 2229 goto drop;
2230
2231 mgp->tx_linearized++;
2232 goto again;
2233
2234drop:
2235 dev_kfree_skb_any(skb);
2236 mgp->stats.tx_dropped += 1;
2237 return 0;
2238
2239}
2240
2241static struct net_device_stats *myri10ge_get_stats(struct net_device *dev)
2242{
2243 struct myri10ge_priv *mgp = netdev_priv(dev);
2244 return &mgp->stats;
2245}
2246
2247static void myri10ge_set_multicast_list(struct net_device *dev)
2248{
85a7ea1b
BG		 2249 struct myri10ge_cmd cmd;
2250 struct myri10ge_priv *mgp;
2251 struct dev_mc_list *mc_list;
6250223e 2252 __be32 data[2] = { 0, 0 };
85a7ea1b
BG		 2253 int err;
2254
2255 mgp = netdev_priv(dev);
0da34b6d
BG		 2256 /* can be called from atomic contexts,
2257 * pass 1 to force atomicity in myri10ge_send_cmd() */
85a7ea1b
BG		 2258 myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
2259
2260 /* This firmware is known to not support multicast */
9dc6f0e7 2261 if (!mgp->fw_multicast_support || mgp->adopted_rx_filter_bug)
85a7ea1b
BG		 2262 return;
2263
2264 /* Disable multicast filtering */
2265
2266 err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
2267 if (err != 0) {
2268 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_ENABLE_ALLMULTI,"
2269 " error status: %d\n", dev->name, err);
2270 goto abort;
2271 }
2272
2273 if (dev->flags & IFF_ALLMULTI) {
2274 /* request to disable multicast filtering, so quit here */
2275 return;
2276 }
2277
2278 /* Flush the filters */
2279
2280 err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
2281 &cmd, 1);
2282 if (err != 0) {
2283 printk(KERN_ERR
2284 "myri10ge: %s: Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS"
2285 ", error status: %d\n", dev->name, err);
2286 goto abort;
2287 }
2288
2289 /* Walk the multicast list, and add each address */
2290 for (mc_list = dev->mc_list; mc_list != NULL; mc_list = mc_list->next) {
40f6cff5
AV		 2291 memcpy(data, &mc_list->dmi_addr, 6);
2292 cmd.data0 = ntohl(data[0]);
2293 cmd.data1 = ntohl(data[1]);
85a7ea1b
BG		 2294 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
2295 &cmd, 1);
2296
2297 if (err != 0) {
2298 printk(KERN_ERR "myri10ge: %s: Failed "
2299 "MXGEFW_JOIN_MULTICAST_GROUP, error status:"
2300 "%d\t", dev->name, err);
2301 printk(KERN_ERR "MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
2302 ((unsigned char *)&mc_list->dmi_addr)[0],
2303 ((unsigned char *)&mc_list->dmi_addr)[1],
2304 ((unsigned char *)&mc_list->dmi_addr)[2],
2305 ((unsigned char *)&mc_list->dmi_addr)[3],
2306 ((unsigned char *)&mc_list->dmi_addr)[4],
2307 ((unsigned char *)&mc_list->dmi_addr)[5]
2308 );
2309 goto abort;
2310 }
2311 }
2312 /* Enable multicast filtering */
2313 err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
2314 if (err != 0) {
2315 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_DISABLE_ALLMULTI,"
2316 "error status: %d\n", dev->name, err);
2317 goto abort;
2318 }
2319
2320 return;
2321
2322abort:
2323 return;
0da34b6d
BG		 2324}
2325
2326static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
2327{
2328 struct sockaddr *sa = addr;
2329 struct myri10ge_priv *mgp = netdev_priv(dev);
2330 int status;
2331
2332 if (!is_valid_ether_addr(sa->sa_data))
2333 return -EADDRNOTAVAIL;
2334
2335 status = myri10ge_update_mac_address(mgp, sa->sa_data);
2336 if (status != 0) {
2337 printk(KERN_ERR
2338 "myri10ge: %s: changing mac address failed with %d\n",
2339 dev->name, status);
2340 return status;
2341 }
2342
2343 /* change the dev structure */
2344 memcpy(dev->dev_addr, sa->sa_data, 6);
2345 return 0;
2346}
2347
2348static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
2349{
2350 struct myri10ge_priv *mgp = netdev_priv(dev);
2351 int error = 0;
2352
2353 if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
2354 printk(KERN_ERR "myri10ge: %s: new mtu (%d) is not valid\n",
2355 dev->name, new_mtu);
2356 return -EINVAL;
2357 }
2358 printk(KERN_INFO "%s: changing mtu from %d to %d\n",
2359 dev->name, dev->mtu, new_mtu);
2360 if (mgp->running) {
2361 /* if we change the mtu on an active device, we must
2362 * reset the device so the firmware sees the change */
2363 myri10ge_close(dev);
2364 dev->mtu = new_mtu;
2365 myri10ge_open(dev);
2366 } else
2367 dev->mtu = new_mtu;
2368
2369 return error;
2370}
2371
2372/*
2373 * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
2374 * Only do it if the bridge is a root port since we don't want to disturb
2375 * any other device, except if forced with myri10ge_ecrc_enable > 1.
2376 */
2377
0da34b6d
BG		 2378static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
2379{
2380 struct pci_dev *bridge = mgp->pdev->bus->self;
2381 struct device *dev = &mgp->pdev->dev;
2382 unsigned cap;
2383 unsigned err_cap;
2384 u16 val;
2385 u8 ext_type;
2386 int ret;
2387
2388 if (!myri10ge_ecrc_enable || !bridge)
2389 return;
2390
2391 /* check that the bridge is a root port */
2392 cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
2393 pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
2394 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2395 if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
2396 if (myri10ge_ecrc_enable > 1) {
2397 struct pci_dev *old_bridge = bridge;
2398
2399 /* Walk the hierarchy up to the root port
2400 * where ECRC has to be enabled */
2401 do {
2402 bridge = bridge->bus->self;
2403 if (!bridge) {
2404 dev_err(dev,
2405 "Failed to find root port"
2406 " to force ECRC\n");
2407 return;
2408 }
2409 cap =
2410 pci_find_capability(bridge, PCI_CAP_ID_EXP);
2411 pci_read_config_word(bridge,
2412 cap + PCI_CAP_FLAGS, &val);
2413 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2414 } while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
2415
2416 dev_info(dev,
2417 "Forcing ECRC on non-root port %s"
2418 " (enabling on root port %s)\n",
2419 pci_name(old_bridge), pci_name(bridge));
2420 } else {
2421 dev_err(dev,
2422 "Not enabling ECRC on non-root port %s\n",
2423 pci_name(bridge));
2424 return;
2425 }
2426 }
2427
2428 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
0da34b6d
BG		 2429 if (!cap)
2430 return;
2431
2432 ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
2433 if (ret) {
2434 dev_err(dev, "failed reading ext-conf-space of %s\n",
2435 pci_name(bridge));
2436 dev_err(dev, "\t pci=nommconf in use? "
2437 "or buggy/incomplete/absent ACPI MCFG attr?\n");
2438 return;
2439 }
2440 if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
2441 return;
2442
2443 err_cap |= PCI_ERR_CAP_ECRC_GENE;
2444 pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
2445 dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
2446 mgp->tx.boundary = 4096;
2447 mgp->fw_name = myri10ge_fw_aligned;
2448}
2449
2450/*
2451 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
2452 * when the PCI-E Completion packets are aligned on an 8-byte
2453 * boundary. Some PCI-E chip sets always align Completion packets; on
2454 * the ones that do not, the alignment can be enforced by enabling
2455 * ECRC generation (if supported).
2456 *
2457 * When PCI-E Completion packets are not aligned, it is actually more
2458 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
2459 *
2460 * If the driver can neither enable ECRC nor verify that it has
2461 * already been enabled, then it must use a firmware image which works
2462 * around unaligned completion packets (myri10ge_ethp_z8e.dat), and it
2463 * should also ensure that it never gives the device a Read-DMA which is
2464 * larger than 2KB by setting the tx.boundary to 2KB. If ECRC is
2465 * enabled, then the driver should use the aligned (myri10ge_eth_z8e.dat)
2466 * firmware image, and set tx.boundary to 4KB.
2467 */
2468
ce7f9368
BG		 2469#define PCI_DEVICE_ID_INTEL_E5000_PCIE23 0x25f7
2470#define PCI_DEVICE_ID_INTEL_E5000_PCIE47 0x25fa
0da34b6d
BG		 2471
2472static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
2473{
2474 struct pci_dev *bridge = mgp->pdev->bus->self;
2475
2476 mgp->tx.boundary = 2048;
2477 mgp->fw_name = myri10ge_fw_unaligned;
2478
2479 if (myri10ge_force_firmware == 0) {
ce7f9368
BG		 2480 int link_width, exp_cap;
2481 u16 lnk;
2482
2483 exp_cap = pci_find_capability(mgp->pdev, PCI_CAP_ID_EXP);
2484 pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
2485 link_width = (lnk >> 4) & 0x3f;
2486
0da34b6d
BG		 2487 myri10ge_enable_ecrc(mgp);
2488
ce7f9368
BG		 2489 /* Check to see if Link is less than 8 or if the
2490 * upstream bridge is known to provide aligned
2491 * completions */
2492 if (link_width < 8) {
2493 dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
2494 link_width);
2495 mgp->tx.boundary = 4096;
2496 mgp->fw_name = myri10ge_fw_aligned;
2497 } else if (bridge &&
2498 /* ServerWorks HT2000/HT1000 */
2499 ((bridge->vendor == PCI_VENDOR_ID_SERVERWORKS
2500 && bridge->device ==
2501 PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE)
2502 /* All Intel E5000 PCIE ports */
2503 || (bridge->vendor == PCI_VENDOR_ID_INTEL
2504 && bridge->device >=
2505 PCI_DEVICE_ID_INTEL_E5000_PCIE23
2506 && bridge->device <=
2507 PCI_DEVICE_ID_INTEL_E5000_PCIE47))) {
0da34b6d
BG		 2508 dev_info(&mgp->pdev->dev,
2509 "Assuming aligned completions (0x%x:0x%x)\n",
2510 bridge->vendor, bridge->device);
2511 mgp->tx.boundary = 4096;
2512 mgp->fw_name = myri10ge_fw_aligned;
2513 }
2514 } else {
2515 if (myri10ge_force_firmware == 1) {
2516 dev_info(&mgp->pdev->dev,
2517 "Assuming aligned completions (forced)\n");
2518 mgp->tx.boundary = 4096;
2519 mgp->fw_name = myri10ge_fw_aligned;
2520 } else {
2521 dev_info(&mgp->pdev->dev,
2522 "Assuming unaligned completions (forced)\n");
2523 mgp->tx.boundary = 2048;
2524 mgp->fw_name = myri10ge_fw_unaligned;
2525 }
2526 }
2527 if (myri10ge_fw_name != NULL) {
2528 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
2529 myri10ge_fw_name);
2530 mgp->fw_name = myri10ge_fw_name;
2531 }
2532}
2533
0da34b6d
BG		 2534#ifdef CONFIG_PM
2535
2536static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
2537{
2538 struct myri10ge_priv *mgp;
2539 struct net_device *netdev;
2540
2541 mgp = pci_get_drvdata(pdev);
2542 if (mgp == NULL)
2543 return -EINVAL;
2544 netdev = mgp->dev;
2545
2546 netif_device_detach(netdev);
2547 if (netif_running(netdev)) {
2548 printk(KERN_INFO "myri10ge: closing %s\n", netdev->name);
2549 rtnl_lock();
2550 myri10ge_close(netdev);
2551 rtnl_unlock();
2552 }
2553 myri10ge_dummy_rdma(mgp, 0);
83f6e152 2554 pci_save_state(pdev);
0da34b6d 2555 pci_disable_device(pdev);
1a63e846
BG		 2556
2557 return pci_set_power_state(pdev, pci_choose_state(pdev, state));
0da34b6d
BG		 2558}
2559
2560static int myri10ge_resume(struct pci_dev *pdev)
2561{
2562 struct myri10ge_priv *mgp;
2563 struct net_device *netdev;
2564 int status;
2565 u16 vendor;
2566
2567 mgp = pci_get_drvdata(pdev);
2568 if (mgp == NULL)
2569 return -EINVAL;
2570 netdev = mgp->dev;
2571 pci_set_power_state(pdev, 0); /* zeros conf space as a side effect */
2572 msleep(5); /* give card time to respond */
2573 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2574 if (vendor == 0xffff) {
2575 printk(KERN_ERR "myri10ge: %s: device disappeared!\n",
2576 mgp->dev->name);
2577 return -EIO;
2578 }
83f6e152 2579
1a63e846
BG		 2580 status = pci_restore_state(pdev);
2581 if (status)
2582 return status;
4c2248cc
BG		 2583
2584 status = pci_enable_device(pdev);
1a63e846 2585 if (status) {
4c2248cc 2586 dev_err(&pdev->dev, "failed to enable device\n");
1a63e846 2587 return status;
4c2248cc
BG		 2588 }
2589
0da34b6d
BG		 2590 pci_set_master(pdev);
2591
0da34b6d 2592 myri10ge_reset(mgp);
013b68bf 2593 myri10ge_dummy_rdma(mgp, 1);
0da34b6d
BG		 2594
2595 /* Save configuration space to be restored if the
2596 * nic resets due to a parity error */
83f6e152 2597 pci_save_state(pdev);
0da34b6d
BG		 2598
2599 if (netif_running(netdev)) {
2600 rtnl_lock();
df30a740 2601 status = myri10ge_open(netdev);
0da34b6d 2602 rtnl_unlock();
df30a740
BG		 2603 if (status != 0)
2604 goto abort_with_enabled;
2605
0da34b6d
BG		 2606 }
2607 netif_device_attach(netdev);
2608
2609 return 0;
2610
4c2248cc
BG		 2611abort_with_enabled:
2612 pci_disable_device(pdev);
0da34b6d
BG		 2613 return -EIO;
2614
2615}
2616
2617#endif /* CONFIG_PM */
2618
2619static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
2620{
2621 struct pci_dev *pdev = mgp->pdev;
2622 int vs = mgp->vendor_specific_offset;
2623 u32 reboot;
2624
2625 /*enter read32 mode */
2626 pci_write_config_byte(pdev, vs + 0x10, 0x3);
2627
2628 /*read REBOOT_STATUS (0xfffffff0) */
2629 pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
2630 pci_read_config_dword(pdev, vs + 0x14, &reboot);
2631 return reboot;
2632}
2633
2634/*
2635 * This watchdog is used to check whether the board has suffered
2636 * from a parity error and needs to be recovered.
2637 */
c4028958 2638static void myri10ge_watchdog(struct work_struct *work)
0da34b6d 2639{
c4028958 2640 struct myri10ge_priv *mgp =
6250223e 2641 container_of(work, struct myri10ge_priv, watchdog_work);
0da34b6d
BG		 2642 u32 reboot;
2643 int status;
2644 u16 cmd, vendor;
2645
2646 mgp->watchdog_resets++;
2647 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
2648 if ((cmd & PCI_COMMAND_MASTER) == 0) {
2649 /* Bus master DMA disabled? Check to see
2650 * if the card rebooted due to a parity error
2651 * For now, just report it */
2652 reboot = myri10ge_read_reboot(mgp);
2653 printk(KERN_ERR
2654 "myri10ge: %s: NIC rebooted (0x%x), resetting\n",
2655 mgp->dev->name, reboot);
2656 /*
2657 * A rebooted nic will come back with config space as
2658 * it was after power was applied to PCIe bus.
2659 * Attempt to restore config space which was saved
2660 * when the driver was loaded, or the last time the
2661 * nic was resumed from power saving mode.
2662 */
83f6e152 2663 pci_restore_state(mgp->pdev);
7adda30c
BG		 2664
2665 /* save state again for accounting reasons */
83f6e152 2666 pci_save_state(mgp->pdev);
7adda30c 2667
0da34b6d
BG		 2668 } else {
2669 /* if we get back -1's from our slot, perhaps somebody
2670 * powered off our card. Don't try to reset it in
2671 * this case */
2672 if (cmd == 0xffff) {
2673 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2674 if (vendor == 0xffff) {
2675 printk(KERN_ERR
2676 "myri10ge: %s: device disappeared!\n",
2677 mgp->dev->name);
2678 return;
2679 }
2680 }
2681 /* Perhaps it is a software error. Try to reset */
2682
2683 printk(KERN_ERR "myri10ge: %s: device timeout, resetting\n",
2684 mgp->dev->name);
2685 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
2686 mgp->dev->name, mgp->tx.req, mgp->tx.done,
2687 mgp->tx.pkt_start, mgp->tx.pkt_done,
2688 (int)ntohl(mgp->fw_stats->send_done_count));
2689 msleep(2000);
2690 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
2691 mgp->dev->name, mgp->tx.req, mgp->tx.done,
2692 mgp->tx.pkt_start, mgp->tx.pkt_done,
2693 (int)ntohl(mgp->fw_stats->send_done_count));
2694 }
2695 rtnl_lock();
2696 myri10ge_close(mgp->dev);
2697 status = myri10ge_load_firmware(mgp);
2698 if (status != 0)
2699 printk(KERN_ERR "myri10ge: %s: failed to load firmware\n",
2700 mgp->dev->name);
2701 else
2702 myri10ge_open(mgp->dev);
2703 rtnl_unlock();
2704}
2705
2706/*
2707 * We use our own timer routine rather than relying upon
2708 * netdev->tx_timeout because we have a very large hardware transmit
2709 * queue. Due to the large queue, the netdev->tx_timeout function
2710 * cannot detect a NIC with a parity error in a timely fashion if the
2711 * NIC is lightly loaded.
2712 */
2713static void myri10ge_watchdog_timer(unsigned long arg)
2714{
2715 struct myri10ge_priv *mgp;
2716
2717 mgp = (struct myri10ge_priv *)arg;
c7dab99b
BG		 2718
2719 if (mgp->rx_small.watchdog_needed) {
2720 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
2721 mgp->small_bytes + MXGEFW_PAD, 1);
2722 if (mgp->rx_small.fill_cnt - mgp->rx_small.cnt >=
2723 myri10ge_fill_thresh)
2724 mgp->rx_small.watchdog_needed = 0;
2725 }
2726 if (mgp->rx_big.watchdog_needed) {
2727 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 1);
2728 if (mgp->rx_big.fill_cnt - mgp->rx_big.cnt >=
2729 myri10ge_fill_thresh)
2730 mgp->rx_big.watchdog_needed = 0;
2731 }
2732
0da34b6d 2733 if (mgp->tx.req != mgp->tx.done &&
c54772e7
BG		 2734 mgp->tx.done == mgp->watchdog_tx_done &&
2735 mgp->watchdog_tx_req != mgp->watchdog_tx_done)
0da34b6d
BG		 2736 /* nic seems like it might be stuck.. */
2737 schedule_work(&mgp->watchdog_work);
2738 else
2739 /* rearm timer */
2740 mod_timer(&mgp->watchdog_timer,
2741 jiffies + myri10ge_watchdog_timeout * HZ);
2742
2743 mgp->watchdog_tx_done = mgp->tx.done;
c54772e7 2744 mgp->watchdog_tx_req = mgp->tx.req;
0da34b6d
BG		 2745}
2746
2747static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2748{
2749 struct net_device *netdev;
2750 struct myri10ge_priv *mgp;
2751 struct device *dev = &pdev->dev;
2752 size_t bytes;
2753 int i;
2754 int status = -ENXIO;
2755 int cap;
2756 int dac_enabled;
2757 u16 val;
2758
2759 netdev = alloc_etherdev(sizeof(*mgp));
2760 if (netdev == NULL) {
2761 dev_err(dev, "Could not allocate ethernet device\n");
2762 return -ENOMEM;
2763 }
2764
2765 mgp = netdev_priv(netdev);
2766 memset(mgp, 0, sizeof(*mgp));
2767 mgp->dev = netdev;
2768 mgp->pdev = pdev;
2769 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
2770 mgp->pause = myri10ge_flow_control;
2771 mgp->intr_coal_delay = myri10ge_intr_coal_delay;
c58ac5ca 2772 mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
0da34b6d
BG		 2773 init_waitqueue_head(&mgp->down_wq);
2774
2775 if (pci_enable_device(pdev)) {
2776 dev_err(&pdev->dev, "pci_enable_device call failed\n");
2777 status = -ENODEV;
2778 goto abort_with_netdev;
2779 }
2780 myri10ge_select_firmware(mgp);
2781
2782 /* Find the vendor-specific cap so we can check
2783 * the reboot register later on */
2784 mgp->vendor_specific_offset
2785 = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
2786
2787 /* Set our max read request to 4KB */
2788 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2789 if (cap < 64) {
2790 dev_err(&pdev->dev, "Bad PCI_CAP_ID_EXP location %d\n", cap);
2791 goto abort_with_netdev;
2792 }
2793 status = pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &val);
2794 if (status != 0) {
2795 dev_err(&pdev->dev, "Error %d reading PCI_EXP_DEVCTL\n",
2796 status);
2797 goto abort_with_netdev;
2798 }
2799 val = (val & ~PCI_EXP_DEVCTL_READRQ) | (5 << 12);
2800 status = pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, val);
2801 if (status != 0) {
2802 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
2803 status);
2804 goto abort_with_netdev;
2805 }
2806
2807 pci_set_master(pdev);
2808 dac_enabled = 1;
2809 status = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
2810 if (status != 0) {
2811 dac_enabled = 0;
2812 dev_err(&pdev->dev,
2813 "64-bit pci address mask was refused, trying 32-bit");
2814 status = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2815 }
2816 if (status != 0) {
2817 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
2818 goto abort_with_netdev;
2819 }
b10c0668
BG		 2820 mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
2821 &mgp->cmd_bus, GFP_KERNEL);
0da34b6d
BG		 2822 if (mgp->cmd == NULL)
2823 goto abort_with_netdev;
2824
b10c0668
BG		 2825 mgp->fw_stats = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
2826 &mgp->fw_stats_bus, GFP_KERNEL);
0da34b6d
BG		 2827 if (mgp->fw_stats == NULL)
2828 goto abort_with_cmd;
2829
2830 mgp->board_span = pci_resource_len(pdev, 0);
2831 mgp->iomem_base = pci_resource_start(pdev, 0);
2832 mgp->mtrr = -1;
2833#ifdef CONFIG_MTRR
2834 mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
2835 MTRR_TYPE_WRCOMB, 1);
2836#endif
2837 /* Hack. need to get rid of these magic numbers */
2838 mgp->sram_size =
2839 2 * 1024 * 1024 - (2 * (48 * 1024) + (32 * 1024)) - 0x100;
2840 if (mgp->sram_size > mgp->board_span) {
2841 dev_err(&pdev->dev, "board span %ld bytes too small\n",
2842 mgp->board_span);
2843 goto abort_with_wc;
2844 }
2845 mgp->sram = ioremap(mgp->iomem_base, mgp->board_span);
2846 if (mgp->sram == NULL) {
2847 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
2848 mgp->board_span, mgp->iomem_base);
2849 status = -ENXIO;
2850 goto abort_with_wc;
2851 }
2852 memcpy_fromio(mgp->eeprom_strings,
2853 mgp->sram + mgp->sram_size - MYRI10GE_EEPROM_STRINGS_SIZE,
2854 MYRI10GE_EEPROM_STRINGS_SIZE);
2855 memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
2856 status = myri10ge_read_mac_addr(mgp);
2857 if (status)
2858 goto abort_with_ioremap;
2859
2860 for (i = 0; i < ETH_ALEN; i++)
2861 netdev->dev_addr[i] = mgp->mac_addr[i];
2862
2863 /* allocate rx done ring */
2864 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
b10c0668
BG		 2865 mgp->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
2866 &mgp->rx_done.bus, GFP_KERNEL);
0da34b6d
BG		 2867 if (mgp->rx_done.entry == NULL)
2868 goto abort_with_ioremap;
2869 memset(mgp->rx_done.entry, 0, bytes);
2870
2871 status = myri10ge_load_firmware(mgp);
2872 if (status != 0) {
2873 dev_err(&pdev->dev, "failed to load firmware\n");
2874 goto abort_with_rx_done;
2875 }
2876
2877 status = myri10ge_reset(mgp);
2878 if (status != 0) {
2879 dev_err(&pdev->dev, "failed reset\n");
2880 goto abort_with_firmware;
2881 }
2882
0da34b6d
BG		 2883 pci_set_drvdata(pdev, mgp);
2884 if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
2885 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
2886 if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
2887 myri10ge_initial_mtu = 68;
2888 netdev->mtu = myri10ge_initial_mtu;
2889 netdev->open = myri10ge_open;
2890 netdev->stop = myri10ge_close;
2891 netdev->hard_start_xmit = myri10ge_xmit;
2892 netdev->get_stats = myri10ge_get_stats;
2893 netdev->base_addr = mgp->iomem_base;
0da34b6d
BG		 2894 netdev->change_mtu = myri10ge_change_mtu;
2895 netdev->set_multicast_list = myri10ge_set_multicast_list;
2896 netdev->set_mac_address = myri10ge_set_mac_address;
2897 netdev->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
2898 if (dac_enabled)
2899 netdev->features |= NETIF_F_HIGHDMA;
2900 netdev->poll = myri10ge_poll;
2901 netdev->weight = myri10ge_napi_weight;
2902
21d05db1
BG		 2903 /* make sure we can get an irq, and that MSI can be
2904 * setup (if available). Also ensure netdev->irq
2905 * is set to correct value if MSI is enabled */
2906 status = myri10ge_request_irq(mgp);
2907 if (status != 0)
2908 goto abort_with_firmware;
2909 netdev->irq = pdev->irq;
2910 myri10ge_free_irq(mgp);
2911
0da34b6d
BG		 2912 /* Save configuration space to be restored if the
2913 * nic resets due to a parity error */
83f6e152 2914 pci_save_state(pdev);
0da34b6d
BG		 2915
2916 /* Setup the watchdog timer */
2917 setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
2918 (unsigned long)mgp);
2919
2920 SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
c4028958 2921 INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
0da34b6d
BG		 2922 status = register_netdev(netdev);
2923 if (status != 0) {
2924 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
7adda30c 2925 goto abort_with_state;
0da34b6d 2926 }
21d05db1
BG		 2927 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
2928 (mgp->msi_enabled ? "MSI" : "xPIC"),
2929 netdev->irq, mgp->tx.boundary, mgp->fw_name,
d6020787 2930 (mgp->mtrr >= 0 ? "Enabled" : "Disabled"));
0da34b6d
BG		 2931
2932 return 0;
2933
7adda30c 2934abort_with_state:
83f6e152 2935 pci_restore_state(pdev);
0da34b6d
BG		 2936
2937abort_with_firmware:
2938 myri10ge_dummy_rdma(mgp, 0);
2939
2940abort_with_rx_done:
2941 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
b10c0668
BG		 2942 dma_free_coherent(&pdev->dev, bytes,
2943 mgp->rx_done.entry, mgp->rx_done.bus);
0da34b6d
BG		 2944
2945abort_with_ioremap:
2946 iounmap(mgp->sram);
2947
2948abort_with_wc:
2949#ifdef CONFIG_MTRR
2950 if (mgp->mtrr >= 0)
2951 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
2952#endif
b10c0668
BG		 2953 dma_free_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
2954 mgp->fw_stats, mgp->fw_stats_bus);
0da34b6d
BG		 2955
2956abort_with_cmd:
b10c0668
BG		 2957 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
2958 mgp->cmd, mgp->cmd_bus);
0da34b6d
BG		 2959
2960abort_with_netdev:
2961
2962 free_netdev(netdev);
2963 return status;
2964}
2965
2966/*
2967 * myri10ge_remove
2968 *
2969 * Does what is necessary to shutdown one Myrinet device. Called
2970 * once for each Myrinet card by the kernel when a module is
2971 * unloaded.
2972 */
2973static void myri10ge_remove(struct pci_dev *pdev)
2974{
2975 struct myri10ge_priv *mgp;
2976 struct net_device *netdev;
2977 size_t bytes;
2978
2979 mgp = pci_get_drvdata(pdev);
2980 if (mgp == NULL)
2981 return;
2982
2983 flush_scheduled_work();
2984 netdev = mgp->dev;
2985 unregister_netdev(netdev);
0da34b6d
BG		 2986
2987 myri10ge_dummy_rdma(mgp, 0);
2988
7adda30c 2989 /* avoid a memory leak */
83f6e152 2990 pci_restore_state(pdev);
7adda30c 2991
0da34b6d 2992 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
b10c0668
BG		 2993 dma_free_coherent(&pdev->dev, bytes,
2994 mgp->rx_done.entry, mgp->rx_done.bus);
0da34b6d
BG		 2995
2996 iounmap(mgp->sram);
2997
2998#ifdef CONFIG_MTRR
2999 if (mgp->mtrr >= 0)
3000 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3001#endif
b10c0668
BG		 3002 dma_free_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
3003 mgp->fw_stats, mgp->fw_stats_bus);
0da34b6d 3004
b10c0668
BG		 3005 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3006 mgp->cmd, mgp->cmd_bus);
0da34b6d
BG		 3007
3008 free_netdev(netdev);
3009 pci_set_drvdata(pdev, NULL);
3010}
3011
b10c0668 3012#define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E 0x0008
0da34b6d
BG		 3013
3014static struct pci_device_id myri10ge_pci_tbl[] = {
b10c0668 3015 {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
0da34b6d
BG		 3016 {0},
3017};
3018
3019static struct pci_driver myri10ge_driver = {
3020 .name = "myri10ge",
3021 .probe = myri10ge_probe,
3022 .remove = myri10ge_remove,
3023 .id_table = myri10ge_pci_tbl,
3024#ifdef CONFIG_PM
3025 .suspend = myri10ge_suspend,
3026 .resume = myri10ge_resume,
3027#endif
3028};
3029
3030static __init int myri10ge_init_module(void)
3031{
3032 printk(KERN_INFO "%s: Version %s\n", myri10ge_driver.name,
3033 MYRI10GE_VERSION_STR);
3034 return pci_register_driver(&myri10ge_driver);
3035}
3036
3037module_init(myri10ge_init_module);
3038
3039static __exit void myri10ge_cleanup_module(void)
3040{
3041 pci_unregister_driver(&myri10ge_driver);
3042}
3043
3044module_exit(myri10ge_cleanup_module);
Linux 6.x block layer and io_uring tree(s)