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[linux-2.6-block.git] / drivers / net / myri10ge / myri10ge.c
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0da34b6d
BG		 1/*************************************************************************
2 * myri10ge.c: Myricom Myri-10G Ethernet driver.
3 *
e3fd5534 4 * Copyright (C) 2005 - 2009 Myricom, Inc.
0da34b6d
BG		 5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of Myricom, Inc. nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
4a2e612a
BG		 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0da34b6d 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
4a2e612a
BG		 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
0da34b6d
BG		 30 *
31 *
32 * If the eeprom on your board is not recent enough, you will need to get a
33 * newer firmware image at:
34 * http://www.myri.com/scs/download-Myri10GE.html
35 *
36 * Contact Information:
37 * <help@myri.com>
38 * Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
39 *************************************************************************/
40
41#include <linux/tcp.h>
42#include <linux/netdevice.h>
43#include <linux/skbuff.h>
44#include <linux/string.h>
45#include <linux/module.h>
46#include <linux/pci.h>
b10c0668 47#include <linux/dma-mapping.h>
0da34b6d
BG		 48#include <linux/etherdevice.h>
49#include <linux/if_ether.h>
50#include <linux/if_vlan.h>
1e6e9342 51#include <linux/inet_lro.h>
981813d8 52#include <linux/dca.h>
0da34b6d
BG		 53#include <linux/ip.h>
54#include <linux/inet.h>
55#include <linux/in.h>
56#include <linux/ethtool.h>
57#include <linux/firmware.h>
58#include <linux/delay.h>
0da34b6d
BG		 59#include <linux/timer.h>
60#include <linux/vmalloc.h>
61#include <linux/crc32.h>
62#include <linux/moduleparam.h>
63#include <linux/io.h>
199126a2 64#include <linux/log2.h>
0da34b6d 65#include <net/checksum.h>
1e6e9342
AG		 66#include <net/ip.h>
67#include <net/tcp.h>
0da34b6d
BG		 68#include <asm/byteorder.h>
69#include <asm/io.h>
0da34b6d
BG		 70#include <asm/processor.h>
71#ifdef CONFIG_MTRR
72#include <asm/mtrr.h>
73#endif
74
75#include "myri10ge_mcp.h"
76#include "myri10ge_mcp_gen_header.h"
77
dddc045e 78#define MYRI10GE_VERSION_STR "1.5.0-1.418"
0da34b6d
BG		 79
80MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
81MODULE_AUTHOR("Maintainer: help@myri.com");
82MODULE_VERSION(MYRI10GE_VERSION_STR);
83MODULE_LICENSE("Dual BSD/GPL");
84
85#define MYRI10GE_MAX_ETHER_MTU 9014
86
87#define MYRI10GE_ETH_STOPPED 0
88#define MYRI10GE_ETH_STOPPING 1
89#define MYRI10GE_ETH_STARTING 2
90#define MYRI10GE_ETH_RUNNING 3
91#define MYRI10GE_ETH_OPEN_FAILED 4
92
93#define MYRI10GE_EEPROM_STRINGS_SIZE 256
94#define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
1e6e9342
AG		 95#define MYRI10GE_MAX_LRO_DESCRIPTORS 8
96#define MYRI10GE_LRO_MAX_PKTS 64
0da34b6d 97
40f6cff5 98#define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
0da34b6d
BG		 99#define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
100
dd50f336
BG		 101#define MYRI10GE_ALLOC_ORDER 0
102#define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE)
103#define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1)
104
236bb5e6
BG		 105#define MYRI10GE_MAX_SLICES 32
106
0da34b6d 107struct myri10ge_rx_buffer_state {
dd50f336
BG		 108 struct page *page;
109 int page_offset;
0da34b6d
BG		 110 DECLARE_PCI_UNMAP_ADDR(bus)
111 DECLARE_PCI_UNMAP_LEN(len)
112};
113
114struct myri10ge_tx_buffer_state {
115 struct sk_buff *skb;
116 int last;
117 DECLARE_PCI_UNMAP_ADDR(bus)
118 DECLARE_PCI_UNMAP_LEN(len)
119};
120
121struct myri10ge_cmd {
122 u32 data0;
123 u32 data1;
124 u32 data2;
125};
126
127struct myri10ge_rx_buf {
128 struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */
0da34b6d
BG		 129 struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */
130 struct myri10ge_rx_buffer_state *info;
dd50f336
BG		 131 struct page *page;
132 dma_addr_t bus;
133 int page_offset;
0da34b6d 134 int cnt;
dd50f336 135 int fill_cnt;
0da34b6d
BG		 136 int alloc_fail;
137 int mask; /* number of rx slots -1 */
dd50f336 138 int watchdog_needed;
0da34b6d
BG		 139};
140
141struct myri10ge_tx_buf {
142 struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */
236bb5e6
BG		 143 __be32 __iomem *send_go; /* "go" doorbell ptr */
144 __be32 __iomem *send_stop; /* "stop" doorbell ptr */
0da34b6d
BG		 145 struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */
146 char *req_bytes;
147 struct myri10ge_tx_buffer_state *info;
148 int mask; /* number of transmit slots -1 */
0da34b6d
BG		 149 int req ____cacheline_aligned; /* transmit slots submitted */
150 int pkt_start; /* packets started */
b53bef84
BG		 151 int stop_queue;
152 int linearized;
0da34b6d
BG		 153 int done ____cacheline_aligned; /* transmit slots completed */
154 int pkt_done; /* packets completed */
b53bef84 155 int wake_queue;
236bb5e6 156 int queue_active;
0da34b6d
BG		 157};
158
159struct myri10ge_rx_done {
160 struct mcp_slot *entry;
161 dma_addr_t bus;
162 int cnt;
163 int idx;
1e6e9342
AG		 164 struct net_lro_mgr lro_mgr;
165 struct net_lro_desc lro_desc[MYRI10GE_MAX_LRO_DESCRIPTORS];
0da34b6d
BG		 166};
167
b53bef84
BG		 168struct myri10ge_slice_netstats {
169 unsigned long rx_packets;
170 unsigned long tx_packets;
171 unsigned long rx_bytes;
172 unsigned long tx_bytes;
173 unsigned long rx_dropped;
174 unsigned long tx_dropped;
175};
176
177struct myri10ge_slice_state {
0da34b6d
BG		 178 struct myri10ge_tx_buf tx; /* transmit ring */
179 struct myri10ge_rx_buf rx_small;
180 struct myri10ge_rx_buf rx_big;
181 struct myri10ge_rx_done rx_done;
b53bef84
BG		 182 struct net_device *dev;
183 struct napi_struct napi;
184 struct myri10ge_priv *mgp;
185 struct myri10ge_slice_netstats stats;
186 __be32 __iomem *irq_claim;
187 struct mcp_irq_data *fw_stats;
188 dma_addr_t fw_stats_bus;
189 int watchdog_tx_done;
190 int watchdog_tx_req;
5dd2d332 191#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 192 int cached_dca_tag;
193 int cpu;
194 __be32 __iomem *dca_tag;
195#endif
0dcffac1 196 char irq_desc[32];
b53bef84
BG		 197};
198
199struct myri10ge_priv {
0dcffac1 200 struct myri10ge_slice_state *ss;
b53bef84 201 int tx_boundary; /* boundary transmits cannot cross */
0dcffac1 202 int num_slices;
b53bef84
BG		 203 int running; /* running? */
204 int csum_flag; /* rx_csums? */
0da34b6d 205 int small_bytes;
dd50f336 206 int big_bytes;
fa0a90d9 207 int max_intr_slots;
0da34b6d
BG		 208 struct net_device *dev;
209 struct net_device_stats stats;
b53bef84 210 spinlock_t stats_lock;
0da34b6d
BG		 211 u8 __iomem *sram;
212 int sram_size;
213 unsigned long board_span;
214 unsigned long iomem_base;
40f6cff5 215 __be32 __iomem *irq_deassert;
0da34b6d
BG		 216 char *mac_addr_string;
217 struct mcp_cmd_response *cmd;
218 dma_addr_t cmd_bus;
0da34b6d
BG		 219 struct pci_dev *pdev;
220 int msi_enabled;
0dcffac1
BG		 221 int msix_enabled;
222 struct msix_entry *msix_vectors;
5dd2d332 223#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 224 int dca_enabled;
225#endif
66341fff 226 u32 link_state;
0da34b6d
BG		 227 unsigned int rdma_tags_available;
228 int intr_coal_delay;
40f6cff5 229 __be32 __iomem *intr_coal_delay_ptr;
0da34b6d 230 int mtrr;
276e26c3 231 int wc_enabled;
0da34b6d
BG		 232 int down_cnt;
233 wait_queue_head_t down_wq;
234 struct work_struct watchdog_work;
235 struct timer_list watchdog_timer;
0da34b6d 236 int watchdog_resets;
b53bef84 237 int watchdog_pause;
0da34b6d
BG		 238 int pause;
239 char *fw_name;
240 char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
c0bf8801 241 char *product_code_string;
0da34b6d 242 char fw_version[128];
9dc6f0e7
BG		 243 int fw_ver_major;
244 int fw_ver_minor;
245 int fw_ver_tiny;
246 int adopted_rx_filter_bug;
0da34b6d
BG		 247 u8 mac_addr[6]; /* eeprom mac address */
248 unsigned long serial_number;
249 int vendor_specific_offset;
85a7ea1b 250 int fw_multicast_support;
4f93fde0
BG		 251 unsigned long features;
252 u32 max_tso6;
0da34b6d
BG		 253 u32 read_dma;
254 u32 write_dma;
255 u32 read_write_dma;
c58ac5ca
BG		 256 u32 link_changes;
257 u32 msg_enable;
2d90b0aa 258 unsigned int board_number;
0da34b6d
BG		 259};
260
261static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
262static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
0dcffac1
BG		 263static char *myri10ge_fw_rss_unaligned = "myri10ge_rss_ethp_z8e.dat";
264static char *myri10ge_fw_rss_aligned = "myri10ge_rss_eth_z8e.dat";
0da34b6d
BG		 265
266static char *myri10ge_fw_name = NULL;
267module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
d1ce3a0f 268MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name");
0da34b6d 269
2d90b0aa
BG		 270#define MYRI10GE_MAX_BOARDS 8
271static char *myri10ge_fw_names[MYRI10GE_MAX_BOARDS] =
7fe624f5 272 {[0 ... (MYRI10GE_MAX_BOARDS - 1)] = NULL };
2d90b0aa
BG		 273module_param_array_named(myri10ge_fw_names, myri10ge_fw_names, charp, NULL,
274 0444);
275MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image names per board");
276
0da34b6d
BG		 277static int myri10ge_ecrc_enable = 1;
278module_param(myri10ge_ecrc_enable, int, S_IRUGO);
d1ce3a0f 279MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E");
0da34b6d 280
0da34b6d
BG		 281static int myri10ge_small_bytes = -1; /* -1 == auto */
282module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
d1ce3a0f 283MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets");
0da34b6d
BG		 284
285static int myri10ge_msi = 1; /* enable msi by default */
3621cec5 286module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR);
d1ce3a0f 287MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts");
0da34b6d 288
f761fae1 289static int myri10ge_intr_coal_delay = 75;
0da34b6d 290module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
d1ce3a0f 291MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay");
0da34b6d
BG		 292
293static int myri10ge_flow_control = 1;
294module_param(myri10ge_flow_control, int, S_IRUGO);
d1ce3a0f 295MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter");
0da34b6d
BG		 296
297static int myri10ge_deassert_wait = 1;
298module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
299MODULE_PARM_DESC(myri10ge_deassert_wait,
d1ce3a0f 300 "Wait when deasserting legacy interrupts");
0da34b6d
BG		 301
302static int myri10ge_force_firmware = 0;
303module_param(myri10ge_force_firmware, int, S_IRUGO);
304MODULE_PARM_DESC(myri10ge_force_firmware,
d1ce3a0f 305 "Force firmware to assume aligned completions");
0da34b6d 306
0da34b6d
BG		 307static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
308module_param(myri10ge_initial_mtu, int, S_IRUGO);
d1ce3a0f 309MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU");
0da34b6d
BG		 310
311static int myri10ge_napi_weight = 64;
312module_param(myri10ge_napi_weight, int, S_IRUGO);
d1ce3a0f 313MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight");
0da34b6d
BG		 314
315static int myri10ge_watchdog_timeout = 1;
316module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
d1ce3a0f 317MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout");
0da34b6d
BG		 318
319static int myri10ge_max_irq_loops = 1048576;
320module_param(myri10ge_max_irq_loops, int, S_IRUGO);
321MODULE_PARM_DESC(myri10ge_max_irq_loops,
d1ce3a0f 322 "Set stuck legacy IRQ detection threshold");
0da34b6d 323
c58ac5ca
BG		 324#define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
325
326static int myri10ge_debug = -1; /* defaults above */
327module_param(myri10ge_debug, int, 0);
328MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
329
1e6e9342
AG		 330static int myri10ge_lro_max_pkts = MYRI10GE_LRO_MAX_PKTS;
331module_param(myri10ge_lro_max_pkts, int, S_IRUGO);
d1ce3a0f
BG		 332MODULE_PARM_DESC(myri10ge_lro_max_pkts,
333 "Number of LRO packets to be aggregated");
1e6e9342 334
dd50f336
BG		 335static int myri10ge_fill_thresh = 256;
336module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
d1ce3a0f 337MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed");
dd50f336 338
f181137f
BG		 339static int myri10ge_reset_recover = 1;
340
0dcffac1
BG		 341static int myri10ge_max_slices = 1;
342module_param(myri10ge_max_slices, int, S_IRUGO);
343MODULE_PARM_DESC(myri10ge_max_slices, "Max tx/rx queues");
344
345static int myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_PORT;
346module_param(myri10ge_rss_hash, int, S_IRUGO);
347MODULE_PARM_DESC(myri10ge_rss_hash, "Type of RSS hashing to do");
348
981813d8
BG		 349static int myri10ge_dca = 1;
350module_param(myri10ge_dca, int, S_IRUGO);
351MODULE_PARM_DESC(myri10ge_dca, "Enable DCA if possible");
352
0da34b6d
BG		 353#define MYRI10GE_FW_OFFSET 1024*1024
354#define MYRI10GE_HIGHPART_TO_U32(X) \
355(sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
356#define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
357
358#define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
359
2f76216f 360static void myri10ge_set_multicast_list(struct net_device *dev);
4f93fde0 361static int myri10ge_sw_tso(struct sk_buff *skb, struct net_device *dev);
2f76216f 362
6250223e 363static inline void put_be32(__be32 val, __be32 __iomem * p)
40f6cff5 364{
6250223e 365 __raw_writel((__force __u32) val, (__force void __iomem *)p);
40f6cff5
AV		 366}
367
59081825
BG		 368static struct net_device_stats *myri10ge_get_stats(struct net_device *dev);
369
0da34b6d
BG		 370static int
371myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
372 struct myri10ge_cmd *data, int atomic)
373{
374 struct mcp_cmd *buf;
375 char buf_bytes[sizeof(*buf) + 8];
376 struct mcp_cmd_response *response = mgp->cmd;
e700f9f4 377 char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
0da34b6d
BG		 378 u32 dma_low, dma_high, result, value;
379 int sleep_total = 0;
380
381 /* ensure buf is aligned to 8 bytes */
382 buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
383
384 buf->data0 = htonl(data->data0);
385 buf->data1 = htonl(data->data1);
386 buf->data2 = htonl(data->data2);
387 buf->cmd = htonl(cmd);
388 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
389 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
390
391 buf->response_addr.low = htonl(dma_low);
392 buf->response_addr.high = htonl(dma_high);
40f6cff5 393 response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 394 mb();
395 myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
396
397 /* wait up to 15ms. Longest command is the DMA benchmark,
398 * which is capped at 5ms, but runs from a timeout handler
399 * that runs every 7.8ms. So a 15ms timeout leaves us with
400 * a 2.2ms margin
401 */
402 if (atomic) {
403 /* if atomic is set, do not sleep,
404 * and try to get the completion quickly
405 * (1ms will be enough for those commands) */
406 for (sleep_total = 0;
407 sleep_total < 1000
40f6cff5 408 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
bd2db0cf 409 sleep_total += 10) {
0da34b6d 410 udelay(10);
bd2db0cf
BG		 411 mb();
412 }
0da34b6d
BG		 413 } else {
414 /* use msleep for most command */
415 for (sleep_total = 0;
416 sleep_total < 15
40f6cff5 417 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 418 sleep_total++)
419 msleep(1);
420 }
421
422 result = ntohl(response->result);
423 value = ntohl(response->data);
424 if (result != MYRI10GE_NO_RESPONSE_RESULT) {
425 if (result == 0) {
426 data->data0 = value;
427 return 0;
85a7ea1b
BG		 428 } else if (result == MXGEFW_CMD_UNKNOWN) {
429 return -ENOSYS;
5443e9ea
BG		 430 } else if (result == MXGEFW_CMD_ERROR_UNALIGNED) {
431 return -E2BIG;
236bb5e6
BG		 432 } else if (result == MXGEFW_CMD_ERROR_RANGE &&
433 cmd == MXGEFW_CMD_ENABLE_RSS_QUEUES &&
434 (data->
435 data1 & MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES) !=
436 0) {
437 return -ERANGE;
0da34b6d
BG		 438 } else {
439 dev_err(&mgp->pdev->dev,
440 "command %d failed, result = %d\n",
441 cmd, result);
442 return -ENXIO;
443 }
444 }
445
446 dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
447 cmd, result);
448 return -EAGAIN;
449}
450
451/*
452 * The eeprom strings on the lanaiX have the format
453 * SN=x\0
454 * MAC=x:x:x:x:x:x\0
455 * PT:ddd mmm xx xx:xx:xx xx\0
456 * PV:ddd mmm xx xx:xx:xx xx\0
457 */
458static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
459{
460 char *ptr, *limit;
461 int i;
462
463 ptr = mgp->eeprom_strings;
464 limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
465
466 while (*ptr != '\0' && ptr < limit) {
467 if (memcmp(ptr, "MAC=", 4) == 0) {
468 ptr += 4;
469 mgp->mac_addr_string = ptr;
470 for (i = 0; i < 6; i++) {
471 if ((ptr + 2) > limit)
472 goto abort;
473 mgp->mac_addr[i] =
474 simple_strtoul(ptr, &ptr, 16);
475 ptr += 1;
476 }
477 }
c0bf8801
BG		 478 if (memcmp(ptr, "PC=", 3) == 0) {
479 ptr += 3;
480 mgp->product_code_string = ptr;
481 }
0da34b6d
BG		 482 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
483 ptr += 3;
484 mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
485 }
486 while (ptr < limit && *ptr++) ;
487 }
488
489 return 0;
490
491abort:
492 dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
493 return -ENXIO;
494}
495
496/*
497 * Enable or disable periodic RDMAs from the host to make certain
498 * chipsets resend dropped PCIe messages
499 */
500
501static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
502{
503 char __iomem *submit;
f8fd57c1 504 __be32 buf[16] __attribute__ ((__aligned__(8)));
0da34b6d
BG		 505 u32 dma_low, dma_high;
506 int i;
507
508 /* clear confirmation addr */
509 mgp->cmd->data = 0;
510 mb();
511
512 /* send a rdma command to the PCIe engine, and wait for the
513 * response in the confirmation address. The firmware should
514 * write a -1 there to indicate it is alive and well
515 */
516 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
517 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
518
519 buf[0] = htonl(dma_high); /* confirm addr MSW */
520 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 521 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 522 buf[3] = htonl(dma_high); /* dummy addr MSW */
523 buf[4] = htonl(dma_low); /* dummy addr LSW */
524 buf[5] = htonl(enable); /* enable? */
525
e700f9f4 526 submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
0da34b6d
BG		 527
528 myri10ge_pio_copy(submit, &buf, sizeof(buf));
529 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
530 msleep(1);
531 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
532 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
533 (enable ? "enable" : "disable"));
534}
535
536static int
537myri10ge_validate_firmware(struct myri10ge_priv *mgp,
538 struct mcp_gen_header *hdr)
539{
540 struct device *dev = &mgp->pdev->dev;
0da34b6d
BG		 541
542 /* check firmware type */
543 if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
544 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
545 return -EINVAL;
546 }
547
548 /* save firmware version for ethtool */
549 strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
550
9dc6f0e7
BG		 551 sscanf(mgp->fw_version, "%d.%d.%d", &mgp->fw_ver_major,
552 &mgp->fw_ver_minor, &mgp->fw_ver_tiny);
0da34b6d 553
9dc6f0e7
BG		 554 if (!(mgp->fw_ver_major == MXGEFW_VERSION_MAJOR
555 && mgp->fw_ver_minor == MXGEFW_VERSION_MINOR)) {
0da34b6d
BG		 556 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
557 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
558 MXGEFW_VERSION_MINOR);
559 return -EINVAL;
560 }
561 return 0;
562}
563
564static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
565{
566 unsigned crc, reread_crc;
567 const struct firmware *fw;
568 struct device *dev = &mgp->pdev->dev;
b0d31d6b 569 unsigned char *fw_readback;
0da34b6d
BG		 570 struct mcp_gen_header *hdr;
571 size_t hdr_offset;
572 int status;
e454358a 573 unsigned i;
0da34b6d
BG		 574
575 if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
576 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
577 mgp->fw_name);
578 status = -EINVAL;
579 goto abort_with_nothing;
580 }
581
582 /* check size */
583
584 if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
585 fw->size < MCP_HEADER_PTR_OFFSET + 4) {
586 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
587 status = -EINVAL;
588 goto abort_with_fw;
589 }
590
591 /* check id */
40f6cff5 592 hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
0da34b6d
BG		 593 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
594 dev_err(dev, "Bad firmware file\n");
595 status = -EINVAL;
596 goto abort_with_fw;
597 }
598 hdr = (void *)(fw->data + hdr_offset);
599
600 status = myri10ge_validate_firmware(mgp, hdr);
601 if (status != 0)
602 goto abort_with_fw;
603
604 crc = crc32(~0, fw->data, fw->size);
e454358a
BG		 605 for (i = 0; i < fw->size; i += 256) {
606 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
607 fw->data + i,
608 min(256U, (unsigned)(fw->size - i)));
609 mb();
610 readb(mgp->sram);
b10c0668 611 }
b0d31d6b
DW		 612 fw_readback = vmalloc(fw->size);
613 if (!fw_readback) {
614 status = -ENOMEM;
615 goto abort_with_fw;
616 }
0da34b6d 617 /* corruption checking is good for parity recovery and buggy chipset */
b0d31d6b
DW		 618 memcpy_fromio(fw_readback, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
619 reread_crc = crc32(~0, fw_readback, fw->size);
620 vfree(fw_readback);
0da34b6d
BG		 621 if (crc != reread_crc) {
622 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
623 (unsigned)fw->size, reread_crc, crc);
624 status = -EIO;
625 goto abort_with_fw;
626 }
627 *size = (u32) fw->size;
628
629abort_with_fw:
630 release_firmware(fw);
631
632abort_with_nothing:
633 return status;
634}
635
636static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
637{
638 struct mcp_gen_header *hdr;
639 struct device *dev = &mgp->pdev->dev;
640 const size_t bytes = sizeof(struct mcp_gen_header);
641 size_t hdr_offset;
642 int status;
643
644 /* find running firmware header */
66341fff 645 hdr_offset = swab32(readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
0da34b6d
BG		 646
647 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
648 dev_err(dev, "Running firmware has bad header offset (%d)\n",
649 (int)hdr_offset);
650 return -EIO;
651 }
652
653 /* copy header of running firmware from SRAM to host memory to
654 * validate firmware */
655 hdr = kmalloc(bytes, GFP_KERNEL);
656 if (hdr == NULL) {
657 dev_err(dev, "could not malloc firmware hdr\n");
658 return -ENOMEM;
659 }
660 memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
661 status = myri10ge_validate_firmware(mgp, hdr);
662 kfree(hdr);
9dc6f0e7
BG		 663
664 /* check to see if adopted firmware has bug where adopting
665 * it will cause broadcasts to be filtered unless the NIC
666 * is kept in ALLMULTI mode */
667 if (mgp->fw_ver_major == 1 && mgp->fw_ver_minor == 4 &&
668 mgp->fw_ver_tiny >= 4 && mgp->fw_ver_tiny <= 11) {
669 mgp->adopted_rx_filter_bug = 1;
670 dev_warn(dev, "Adopting fw %d.%d.%d: "
671 "working around rx filter bug\n",
672 mgp->fw_ver_major, mgp->fw_ver_minor,
673 mgp->fw_ver_tiny);
674 }
0da34b6d
BG		 675 return status;
676}
677
0178ec3d 678static int myri10ge_get_firmware_capabilities(struct myri10ge_priv *mgp)
fa0a90d9
BG		 679{
680 struct myri10ge_cmd cmd;
681 int status;
682
683 /* probe for IPv6 TSO support */
684 mgp->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
685 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE,
686 &cmd, 0);
687 if (status == 0) {
688 mgp->max_tso6 = cmd.data0;
689 mgp->features |= NETIF_F_TSO6;
690 }
691
692 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
693 if (status != 0) {
694 dev_err(&mgp->pdev->dev,
695 "failed MXGEFW_CMD_GET_RX_RING_SIZE\n");
696 return -ENXIO;
697 }
698
699 mgp->max_intr_slots = 2 * (cmd.data0 / sizeof(struct mcp_dma_addr));
700
701 return 0;
702}
703
0dcffac1 704static int myri10ge_load_firmware(struct myri10ge_priv *mgp, int adopt)
0da34b6d
BG		 705{
706 char __iomem *submit;
f8fd57c1 707 __be32 buf[16] __attribute__ ((__aligned__(8)));
0da34b6d
BG		 708 u32 dma_low, dma_high, size;
709 int status, i;
710
b10c0668 711 size = 0;
0da34b6d
BG		 712 status = myri10ge_load_hotplug_firmware(mgp, &size);
713 if (status) {
0dcffac1
BG		 714 if (!adopt)
715 return status;
0da34b6d
BG		 716 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
717
718 /* Do not attempt to adopt firmware if there
719 * was a bad crc */
720 if (status == -EIO)
721 return status;
722
723 status = myri10ge_adopt_running_firmware(mgp);
724 if (status != 0) {
725 dev_err(&mgp->pdev->dev,
726 "failed to adopt running firmware\n");
727 return status;
728 }
729 dev_info(&mgp->pdev->dev,
730 "Successfully adopted running firmware\n");
b53bef84 731 if (mgp->tx_boundary == 4096) {
0da34b6d
BG		 732 dev_warn(&mgp->pdev->dev,
733 "Using firmware currently running on NIC"
734 ". For optimal\n");
735 dev_warn(&mgp->pdev->dev,
736 "performance consider loading optimized "
737 "firmware\n");
738 dev_warn(&mgp->pdev->dev, "via hotplug\n");
739 }
740
741 mgp->fw_name = "adopted";
b53bef84 742 mgp->tx_boundary = 2048;
fa0a90d9
BG		 743 myri10ge_dummy_rdma(mgp, 1);
744 status = myri10ge_get_firmware_capabilities(mgp);
0da34b6d
BG		 745 return status;
746 }
747
748 /* clear confirmation addr */
749 mgp->cmd->data = 0;
750 mb();
751
752 /* send a reload command to the bootstrap MCP, and wait for the
753 * response in the confirmation address. The firmware should
754 * write a -1 there to indicate it is alive and well
755 */
756 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
757 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
758
759 buf[0] = htonl(dma_high); /* confirm addr MSW */
760 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 761 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 762
763 /* FIX: All newest firmware should un-protect the bottom of
764 * the sram before handoff. However, the very first interfaces
765 * do not. Therefore the handoff copy must skip the first 8 bytes
766 */
767 buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
768 buf[4] = htonl(size - 8); /* length of code */
769 buf[5] = htonl(8); /* where to copy to */
770 buf[6] = htonl(0); /* where to jump to */
771
e700f9f4 772 submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
0da34b6d
BG		 773
774 myri10ge_pio_copy(submit, &buf, sizeof(buf));
775 mb();
776 msleep(1);
777 mb();
778 i = 0;
d93ca2a4
BG		 779 while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 9) {
780 msleep(1 << i);
0da34b6d
BG		 781 i++;
782 }
783 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
784 dev_err(&mgp->pdev->dev, "handoff failed\n");
785 return -ENXIO;
786 }
9a71db72 787 myri10ge_dummy_rdma(mgp, 1);
fa0a90d9 788 status = myri10ge_get_firmware_capabilities(mgp);
0da34b6d 789
fa0a90d9 790 return status;
0da34b6d
BG		 791}
792
793static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
794{
795 struct myri10ge_cmd cmd;
796 int status;
797
798 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
799 | (addr[2] << 8) | addr[3]);
800
801 cmd.data1 = ((addr[4] << 8) | (addr[5]));
802
803 status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
804 return status;
805}
806
807static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
808{
809 struct myri10ge_cmd cmd;
810 int status, ctl;
811
812 ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
813 status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
814
815 if (status) {
816 printk(KERN_ERR
817 "myri10ge: %s: Failed to set flow control mode\n",
818 mgp->dev->name);
819 return status;
820 }
821 mgp->pause = pause;
822 return 0;
823}
824
825static void
826myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
827{
828 struct myri10ge_cmd cmd;
829 int status, ctl;
830
831 ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
832 status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
833 if (status)
834 printk(KERN_ERR "myri10ge: %s: Failed to set promisc mode\n",
835 mgp->dev->name);
836}
837
0d6ac257 838static int myri10ge_dma_test(struct myri10ge_priv *mgp, int test_type)
0da34b6d
BG		 839{
840 struct myri10ge_cmd cmd;
841 int status;
0da34b6d 842 u32 len;
34fdccea
BG		 843 struct page *dmatest_page;
844 dma_addr_t dmatest_bus;
0d6ac257
BG		 845 char *test = " ";
846
847 dmatest_page = alloc_page(GFP_KERNEL);
848 if (!dmatest_page)
849 return -ENOMEM;
850 dmatest_bus = pci_map_page(mgp->pdev, dmatest_page, 0, PAGE_SIZE,
851 DMA_BIDIRECTIONAL);
852
853 /* Run a small DMA test.
854 * The magic multipliers to the length tell the firmware
855 * to do DMA read, write, or read+write tests. The
856 * results are returned in cmd.data0. The upper 16
857 * bits or the return is the number of transfers completed.
858 * The lower 16 bits is the time in 0.5us ticks that the
859 * transfers took to complete.
860 */
861
b53bef84 862 len = mgp->tx_boundary;
0d6ac257
BG		 863
864 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
865 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
866 cmd.data2 = len * 0x10000;
867 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
868 if (status != 0) {
869 test = "read";
870 goto abort;
871 }
872 mgp->read_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
873 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
874 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
875 cmd.data2 = len * 0x1;
876 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
877 if (status != 0) {
878 test = "write";
879 goto abort;
880 }
881 mgp->write_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
882
883 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
884 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
885 cmd.data2 = len * 0x10001;
886 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
887 if (status != 0) {
888 test = "read/write";
889 goto abort;
890 }
891 mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
892 (cmd.data0 & 0xffff);
893
894abort:
895 pci_unmap_page(mgp->pdev, dmatest_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
896 put_page(dmatest_page);
897
898 if (status != 0 && test_type != MXGEFW_CMD_UNALIGNED_TEST)
899 dev_warn(&mgp->pdev->dev, "DMA %s benchmark failed: %d\n",
900 test, status);
901
902 return status;
903}
904
905static int myri10ge_reset(struct myri10ge_priv *mgp)
906{
907 struct myri10ge_cmd cmd;
0dcffac1
BG		 908 struct myri10ge_slice_state *ss;
909 int i, status;
0d6ac257 910 size_t bytes;
5dd2d332 911#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 912 unsigned long dca_tag_off;
913#endif
0da34b6d
BG		 914
915 /* try to send a reset command to the card to see if it
916 * is alive */
917 memset(&cmd, 0, sizeof(cmd));
918 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
919 if (status != 0) {
920 dev_err(&mgp->pdev->dev, "failed reset\n");
921 return -ENXIO;
922 }
0d6ac257
BG		 923
924 (void)myri10ge_dma_test(mgp, MXGEFW_DMA_TEST);
0dcffac1
BG		 925 /*
926 * Use non-ndis mcp_slot (eg, 4 bytes total,
927 * no toeplitz hash value returned. Older firmware will
928 * not understand this command, but will use the correct
929 * sized mcp_slot, so we ignore error returns
930 */
931 cmd.data0 = MXGEFW_RSS_MCP_SLOT_TYPE_MIN;
932 (void)myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE, &cmd, 0);
0da34b6d
BG		 933
934 /* Now exchange information about interrupts */
935
0dcffac1 936 bytes = mgp->max_intr_slots * sizeof(*mgp->ss[0].rx_done.entry);
0da34b6d
BG		 937 cmd.data0 = (u32) bytes;
938 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
0dcffac1
BG		 939
940 /*
941 * Even though we already know how many slices are supported
942 * via myri10ge_probe_slices() MXGEFW_CMD_GET_MAX_RSS_QUEUES
943 * has magic side effects, and must be called after a reset.
944 * It must be called prior to calling any RSS related cmds,
945 * including assigning an interrupt queue for anything but
946 * slice 0. It must also be called *after*
947 * MXGEFW_CMD_SET_INTRQ_SIZE, since the intrq size is used by
948 * the firmware to compute offsets.
949 */
950
951 if (mgp->num_slices > 1) {
952
953 /* ask the maximum number of slices it supports */
954 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES,
955 &cmd, 0);
956 if (status != 0) {
957 dev_err(&mgp->pdev->dev,
958 "failed to get number of slices\n");
959 }
960
961 /*
962 * MXGEFW_CMD_ENABLE_RSS_QUEUES must be called prior
963 * to setting up the interrupt queue DMA
964 */
965
966 cmd.data0 = mgp->num_slices;
236bb5e6
BG		 967 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
968 if (mgp->dev->real_num_tx_queues > 1)
969 cmd.data1 |= MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES;
0dcffac1
BG		 970 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
971 &cmd, 0);
236bb5e6
BG		 972
973 /* Firmware older than 1.4.32 only supports multiple
974 * RX queues, so if we get an error, first retry using a
975 * single TX queue before giving up */
976 if (status != 0 && mgp->dev->real_num_tx_queues > 1) {
977 mgp->dev->real_num_tx_queues = 1;
978 cmd.data0 = mgp->num_slices;
979 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
980 status = myri10ge_send_cmd(mgp,
981 MXGEFW_CMD_ENABLE_RSS_QUEUES,
982 &cmd, 0);
983 }
984
0dcffac1
BG		 985 if (status != 0) {
986 dev_err(&mgp->pdev->dev,
987 "failed to set number of slices\n");
988
989 return status;
990 }
991 }
992 for (i = 0; i < mgp->num_slices; i++) {
993 ss = &mgp->ss[i];
994 cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->rx_done.bus);
995 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->rx_done.bus);
996 cmd.data2 = i;
997 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA,
998 &cmd, 0);
999 };
0da34b6d
BG		 1000
1001 status |=
1002 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
0dcffac1
BG		 1003 for (i = 0; i < mgp->num_slices; i++) {
1004 ss = &mgp->ss[i];
1005 ss->irq_claim =
1006 (__iomem __be32 *) (mgp->sram + cmd.data0 + 8 * i);
1007 }
df30a740
BG		 1008 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
1009 &cmd, 0);
1010 mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d 1011
0da34b6d
BG		 1012 status |= myri10ge_send_cmd
1013 (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
40f6cff5 1014 mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d
BG		 1015 if (status != 0) {
1016 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
1017 return status;
1018 }
40f6cff5 1019 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d 1020
5dd2d332 1021#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 1022 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_DCA_OFFSET, &cmd, 0);
1023 dca_tag_off = cmd.data0;
1024 for (i = 0; i < mgp->num_slices; i++) {
1025 ss = &mgp->ss[i];
1026 if (status == 0) {
1027 ss->dca_tag = (__iomem __be32 *)
1028 (mgp->sram + dca_tag_off + 4 * i);
1029 } else {
1030 ss->dca_tag = NULL;
1031 }
1032 }
4ee2ac51 1033#endif /* CONFIG_MYRI10GE_DCA */
981813d8 1034
0da34b6d 1035 /* reset mcp/driver shared state back to 0 */
0dcffac1 1036
c58ac5ca 1037 mgp->link_changes = 0;
0dcffac1
BG		 1038 for (i = 0; i < mgp->num_slices; i++) {
1039 ss = &mgp->ss[i];
1040
1041 memset(ss->rx_done.entry, 0, bytes);
1042 ss->tx.req = 0;
1043 ss->tx.done = 0;
1044 ss->tx.pkt_start = 0;
1045 ss->tx.pkt_done = 0;
1046 ss->rx_big.cnt = 0;
1047 ss->rx_small.cnt = 0;
1048 ss->rx_done.idx = 0;
1049 ss->rx_done.cnt = 0;
1050 ss->tx.wake_queue = 0;
1051 ss->tx.stop_queue = 0;
1052 }
1053
0da34b6d 1054 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
0da34b6d 1055 myri10ge_change_pause(mgp, mgp->pause);
2f76216f 1056 myri10ge_set_multicast_list(mgp->dev);
0da34b6d
BG		 1057 return status;
1058}
1059
5dd2d332 1060#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 1061static void
1062myri10ge_write_dca(struct myri10ge_slice_state *ss, int cpu, int tag)
1063{
1064 ss->cpu = cpu;
1065 ss->cached_dca_tag = tag;
1066 put_be32(htonl(tag), ss->dca_tag);
1067}
1068
1069static inline void myri10ge_update_dca(struct myri10ge_slice_state *ss)
1070{
1071 int cpu = get_cpu();
1072 int tag;
1073
1074 if (cpu != ss->cpu) {
1075 tag = dca_get_tag(cpu);
1076 if (ss->cached_dca_tag != tag)
1077 myri10ge_write_dca(ss, cpu, tag);
1078 }
1079 put_cpu();
1080}
1081
1082static void myri10ge_setup_dca(struct myri10ge_priv *mgp)
1083{
1084 int err, i;
1085 struct pci_dev *pdev = mgp->pdev;
1086
1087 if (mgp->ss[0].dca_tag == NULL || mgp->dca_enabled)
1088 return;
1089 if (!myri10ge_dca) {
1090 dev_err(&pdev->dev, "dca disabled by administrator\n");
1091 return;
1092 }
1093 err = dca_add_requester(&pdev->dev);
1094 if (err) {
330554cb
BG		 1095 if (err != -ENODEV)
1096 dev_err(&pdev->dev,
1097 "dca_add_requester() failed, err=%d\n", err);
981813d8
BG		 1098 return;
1099 }
1100 mgp->dca_enabled = 1;
1101 for (i = 0; i < mgp->num_slices; i++)
1102 myri10ge_write_dca(&mgp->ss[i], -1, 0);
1103}
1104
1105static void myri10ge_teardown_dca(struct myri10ge_priv *mgp)
1106{
1107 struct pci_dev *pdev = mgp->pdev;
1108 int err;
1109
1110 if (!mgp->dca_enabled)
1111 return;
1112 mgp->dca_enabled = 0;
1113 err = dca_remove_requester(&pdev->dev);
1114}
1115
1116static int myri10ge_notify_dca_device(struct device *dev, void *data)
1117{
1118 struct myri10ge_priv *mgp;
1119 unsigned long event;
1120
1121 mgp = dev_get_drvdata(dev);
1122 event = *(unsigned long *)data;
1123
1124 if (event == DCA_PROVIDER_ADD)
1125 myri10ge_setup_dca(mgp);
1126 else if (event == DCA_PROVIDER_REMOVE)
1127 myri10ge_teardown_dca(mgp);
1128 return 0;
1129}
4ee2ac51 1130#endif /* CONFIG_MYRI10GE_DCA */
981813d8 1131
0da34b6d
BG		 1132static inline void
1133myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
1134 struct mcp_kreq_ether_recv *src)
1135{
40f6cff5 1136 __be32 low;
0da34b6d
BG		 1137
1138 low = src->addr_low;
284901a9 1139 src->addr_low = htonl(DMA_BIT_MASK(32));
e67bda55
BG		 1140 myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
1141 mb();
1142 myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
0da34b6d
BG		 1143 mb();
1144 src->addr_low = low;
40f6cff5 1145 put_be32(low, &dst->addr_low);
0da34b6d
BG		 1146 mb();
1147}
1148
40f6cff5 1149static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
0da34b6d
BG		 1150{
1151 struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
1152
40f6cff5 1153 if ((skb->protocol == htons(ETH_P_8021Q)) &&
0da34b6d
BG		 1154 (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
1155 vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
1156 skb->csum = hw_csum;
84fa7933 1157 skb->ip_summed = CHECKSUM_COMPLETE;
0da34b6d
BG		 1158 }
1159}
1160
dd50f336
BG		 1161static inline void
1162myri10ge_rx_skb_build(struct sk_buff *skb, u8 * va,
1163 struct skb_frag_struct *rx_frags, int len, int hlen)
1164{
1165 struct skb_frag_struct *skb_frags;
1166
1167 skb->len = skb->data_len = len;
1168 skb->truesize = len + sizeof(struct sk_buff);
1169 /* attach the page(s) */
1170
1171 skb_frags = skb_shinfo(skb)->frags;
1172 while (len > 0) {
1173 memcpy(skb_frags, rx_frags, sizeof(*skb_frags));
1174 len -= rx_frags->size;
1175 skb_frags++;
1176 rx_frags++;
1177 skb_shinfo(skb)->nr_frags++;
1178 }
1179
1180 /* pskb_may_pull is not available in irq context, but
1181 * skb_pull() (for ether_pad and eth_type_trans()) requires
1182 * the beginning of the packet in skb_headlen(), move it
1183 * manually */
27d7ff46 1184 skb_copy_to_linear_data(skb, va, hlen);
dd50f336
BG		 1185 skb_shinfo(skb)->frags[0].page_offset += hlen;
1186 skb_shinfo(skb)->frags[0].size -= hlen;
1187 skb->data_len -= hlen;
1188 skb->tail += hlen;
1189 skb_pull(skb, MXGEFW_PAD);
1190}
1191
1192static void
1193myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
1194 int bytes, int watchdog)
1195{
1196 struct page *page;
1197 int idx;
1198
1199 if (unlikely(rx->watchdog_needed && !watchdog))
1200 return;
1201
1202 /* try to refill entire ring */
1203 while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) {
1204 idx = rx->fill_cnt & rx->mask;
ae8509b1 1205 if (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE) {
dd50f336
BG		 1206 /* we can use part of previous page */
1207 get_page(rx->page);
1208 } else {
1209 /* we need a new page */
1210 page =
1211 alloc_pages(GFP_ATOMIC | __GFP_COMP,
1212 MYRI10GE_ALLOC_ORDER);
1213 if (unlikely(page == NULL)) {
1214 if (rx->fill_cnt - rx->cnt < 16)
1215 rx->watchdog_needed = 1;
1216 return;
1217 }
1218 rx->page = page;
1219 rx->page_offset = 0;
1220 rx->bus = pci_map_page(mgp->pdev, page, 0,
1221 MYRI10GE_ALLOC_SIZE,
1222 PCI_DMA_FROMDEVICE);
1223 }
1224 rx->info[idx].page = rx->page;
1225 rx->info[idx].page_offset = rx->page_offset;
1226 /* note that this is the address of the start of the
1227 * page */
1228 pci_unmap_addr_set(&rx->info[idx], bus, rx->bus);
1229 rx->shadow[idx].addr_low =
1230 htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset);
1231 rx->shadow[idx].addr_high =
1232 htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus));
1233
1234 /* start next packet on a cacheline boundary */
1235 rx->page_offset += SKB_DATA_ALIGN(bytes);
ae8509b1
BG		 1236
1237#if MYRI10GE_ALLOC_SIZE > 4096
1238 /* don't cross a 4KB boundary */
1239 if ((rx->page_offset >> 12) !=
1240 ((rx->page_offset + bytes - 1) >> 12))
1241 rx->page_offset = (rx->page_offset + 4096) & ~4095;
1242#endif
dd50f336
BG		 1243 rx->fill_cnt++;
1244
1245 /* copy 8 descriptors to the firmware at a time */
1246 if ((idx & 7) == 7) {
e454e7e2
BG		 1247 myri10ge_submit_8rx(&rx->lanai[idx - 7],
1248 &rx->shadow[idx - 7]);
dd50f336
BG		 1249 }
1250 }
1251}
1252
1253static inline void
1254myri10ge_unmap_rx_page(struct pci_dev *pdev,
1255 struct myri10ge_rx_buffer_state *info, int bytes)
1256{
1257 /* unmap the recvd page if we're the only or last user of it */
1258 if (bytes >= MYRI10GE_ALLOC_SIZE / 2 ||
1259 (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) {
1260 pci_unmap_page(pdev, (pci_unmap_addr(info, bus)
1261 & ~(MYRI10GE_ALLOC_SIZE - 1)),
1262 MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
1263 }
1264}
1265
1266#define MYRI10GE_HLEN 64 /* The number of bytes to copy from a
1267 * page into an skb */
1268
1269static inline int
b53bef84 1270myri10ge_rx_done(struct myri10ge_slice_state *ss, struct myri10ge_rx_buf *rx,
52ea6fb3 1271 int bytes, int len, __wsum csum)
dd50f336 1272{
b53bef84 1273 struct myri10ge_priv *mgp = ss->mgp;
dd50f336
BG		 1274 struct sk_buff *skb;
1275 struct skb_frag_struct rx_frags[MYRI10GE_MAX_FRAGS_PER_FRAME];
1276 int i, idx, hlen, remainder;
1277 struct pci_dev *pdev = mgp->pdev;
1278 struct net_device *dev = mgp->dev;
1279 u8 *va;
1280
1281 len += MXGEFW_PAD;
1282 idx = rx->cnt & rx->mask;
1283 va = page_address(rx->info[idx].page) + rx->info[idx].page_offset;
1284 prefetch(va);
1285 /* Fill skb_frag_struct(s) with data from our receive */
1286 for (i = 0, remainder = len; remainder > 0; i++) {
1287 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
1288 rx_frags[i].page = rx->info[idx].page;
1289 rx_frags[i].page_offset = rx->info[idx].page_offset;
1290 if (remainder < MYRI10GE_ALLOC_SIZE)
1291 rx_frags[i].size = remainder;
1292 else
1293 rx_frags[i].size = MYRI10GE_ALLOC_SIZE;
1294 rx->cnt++;
1295 idx = rx->cnt & rx->mask;
1296 remainder -= MYRI10GE_ALLOC_SIZE;
1297 }
1298
3a0c7d2d 1299 if (dev->features & NETIF_F_LRO) {
1e6e9342
AG		 1300 rx_frags[0].page_offset += MXGEFW_PAD;
1301 rx_frags[0].size -= MXGEFW_PAD;
1302 len -= MXGEFW_PAD;
b53bef84 1303 lro_receive_frags(&ss->rx_done.lro_mgr, rx_frags,
b53bef84 1304 /* opaque, will come back in get_frag_header */
0dcffac1 1305 len, len,
b53bef84 1306 (void *)(__force unsigned long)csum, csum);
0dcffac1 1307
1e6e9342
AG		 1308 return 1;
1309 }
1310
dd50f336
BG		 1311 hlen = MYRI10GE_HLEN > len ? len : MYRI10GE_HLEN;
1312
e636b2ea
BG		 1313 /* allocate an skb to attach the page(s) to. This is done
1314 * after trying LRO, so as to avoid skb allocation overheads */
dd50f336
BG		 1315
1316 skb = netdev_alloc_skb(dev, MYRI10GE_HLEN + 16);
1317 if (unlikely(skb == NULL)) {
d6279c88 1318 ss->stats.rx_dropped++;
dd50f336
BG		 1319 do {
1320 i--;
1321 put_page(rx_frags[i].page);
1322 } while (i != 0);
1323 return 0;
1324 }
1325
1326 /* Attach the pages to the skb, and trim off any padding */
1327 myri10ge_rx_skb_build(skb, va, rx_frags, len, hlen);
1328 if (skb_shinfo(skb)->frags[0].size <= 0) {
1329 put_page(skb_shinfo(skb)->frags[0].page);
1330 skb_shinfo(skb)->nr_frags = 0;
1331 }
1332 skb->protocol = eth_type_trans(skb, dev);
0c8dfc83 1333 skb_record_rx_queue(skb, ss - &mgp->ss[0]);
dd50f336
BG		 1334
1335 if (mgp->csum_flag) {
1336 if ((skb->protocol == htons(ETH_P_IP)) ||
1337 (skb->protocol == htons(ETH_P_IPV6))) {
1338 skb->csum = csum;
1339 skb->ip_summed = CHECKSUM_COMPLETE;
1340 } else
1341 myri10ge_vlan_ip_csum(skb, csum);
1342 }
1343 netif_receive_skb(skb);
dd50f336
BG		 1344 return 1;
1345}
1346
b53bef84
BG		 1347static inline void
1348myri10ge_tx_done(struct myri10ge_slice_state *ss, int mcp_index)
0da34b6d 1349{
b53bef84
BG		 1350 struct pci_dev *pdev = ss->mgp->pdev;
1351 struct myri10ge_tx_buf *tx = &ss->tx;
236bb5e6 1352 struct netdev_queue *dev_queue;
0da34b6d
BG		 1353 struct sk_buff *skb;
1354 int idx, len;
0da34b6d
BG		 1355
1356 while (tx->pkt_done != mcp_index) {
1357 idx = tx->done & tx->mask;
1358 skb = tx->info[idx].skb;
1359
1360 /* Mark as free */
1361 tx->info[idx].skb = NULL;
1362 if (tx->info[idx].last) {
1363 tx->pkt_done++;
1364 tx->info[idx].last = 0;
1365 }
1366 tx->done++;
1367 len = pci_unmap_len(&tx->info[idx], len);
1368 pci_unmap_len_set(&tx->info[idx], len, 0);
1369 if (skb) {
b53bef84
BG		 1370 ss->stats.tx_bytes += skb->len;
1371 ss->stats.tx_packets++;
0da34b6d
BG		 1372 dev_kfree_skb_irq(skb);
1373 if (len)
1374 pci_unmap_single(pdev,
1375 pci_unmap_addr(&tx->info[idx],
1376 bus), len,
1377 PCI_DMA_TODEVICE);
1378 } else {
1379 if (len)
1380 pci_unmap_page(pdev,
1381 pci_unmap_addr(&tx->info[idx],
1382 bus), len,
1383 PCI_DMA_TODEVICE);
1384 }
0da34b6d 1385 }
236bb5e6
BG		 1386
1387 dev_queue = netdev_get_tx_queue(ss->dev, ss - ss->mgp->ss);
1388 /*
1389 * Make a minimal effort to prevent the NIC from polling an
1390 * idle tx queue. If we can't get the lock we leave the queue
1391 * active. In this case, either a thread was about to start
1392 * using the queue anyway, or we lost a race and the NIC will
1393 * waste some of its resources polling an inactive queue for a
1394 * while.
1395 */
1396
1397 if ((ss->mgp->dev->real_num_tx_queues > 1) &&
1398 __netif_tx_trylock(dev_queue)) {
1399 if (tx->req == tx->done) {
1400 tx->queue_active = 0;
1401 put_be32(htonl(1), tx->send_stop);
8c2f5fa5 1402 mb();
6824a105 1403 mmiowb();
236bb5e6
BG		 1404 }
1405 __netif_tx_unlock(dev_queue);
1406 }
1407
0da34b6d 1408 /* start the queue if we've stopped it */
236bb5e6 1409 if (netif_tx_queue_stopped(dev_queue)
0da34b6d 1410 && tx->req - tx->done < (tx->mask >> 1)) {
b53bef84 1411 tx->wake_queue++;
236bb5e6 1412 netif_tx_wake_queue(dev_queue);
0da34b6d
BG		 1413 }
1414}
1415
b53bef84
BG		 1416static inline int
1417myri10ge_clean_rx_done(struct myri10ge_slice_state *ss, int budget)
0da34b6d 1418{
b53bef84
BG		 1419 struct myri10ge_rx_done *rx_done = &ss->rx_done;
1420 struct myri10ge_priv *mgp = ss->mgp;
18af3e7c 1421 struct net_device *netdev = mgp->dev;
0da34b6d
BG		 1422 unsigned long rx_bytes = 0;
1423 unsigned long rx_packets = 0;
1424 unsigned long rx_ok;
1425
1426 int idx = rx_done->idx;
1427 int cnt = rx_done->cnt;
bea3348e 1428 int work_done = 0;
0da34b6d 1429 u16 length;
40f6cff5 1430 __wsum checksum;
0da34b6d 1431
c956a240 1432 while (rx_done->entry[idx].length != 0 && work_done < budget) {
0da34b6d
BG		 1433 length = ntohs(rx_done->entry[idx].length);
1434 rx_done->entry[idx].length = 0;
40f6cff5 1435 checksum = csum_unfold(rx_done->entry[idx].checksum);
0da34b6d 1436 if (length <= mgp->small_bytes)
b53bef84 1437 rx_ok = myri10ge_rx_done(ss, &ss->rx_small,
52ea6fb3
BG		 1438 mgp->small_bytes,
1439 length, checksum);
0da34b6d 1440 else
b53bef84 1441 rx_ok = myri10ge_rx_done(ss, &ss->rx_big,
52ea6fb3
BG		 1442 mgp->big_bytes,
1443 length, checksum);
0da34b6d
BG		 1444 rx_packets += rx_ok;
1445 rx_bytes += rx_ok * (unsigned long)length;
1446 cnt++;
014377a1 1447 idx = cnt & (mgp->max_intr_slots - 1);
c956a240 1448 work_done++;
0da34b6d
BG		 1449 }
1450 rx_done->idx = idx;
1451 rx_done->cnt = cnt;
b53bef84
BG		 1452 ss->stats.rx_packets += rx_packets;
1453 ss->stats.rx_bytes += rx_bytes;
c7dab99b 1454
18af3e7c 1455 if (netdev->features & NETIF_F_LRO)
1e6e9342
AG		 1456 lro_flush_all(&rx_done->lro_mgr);
1457
c7dab99b 1458 /* restock receive rings if needed */
b53bef84
BG		 1459 if (ss->rx_small.fill_cnt - ss->rx_small.cnt < myri10ge_fill_thresh)
1460 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
c7dab99b 1461 mgp->small_bytes + MXGEFW_PAD, 0);
b53bef84
BG		 1462 if (ss->rx_big.fill_cnt - ss->rx_big.cnt < myri10ge_fill_thresh)
1463 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
c7dab99b 1464
bea3348e 1465 return work_done;
0da34b6d
BG		 1466}
1467
1468static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1469{
0dcffac1 1470 struct mcp_irq_data *stats = mgp->ss[0].fw_stats;
0da34b6d
BG		 1471
1472 if (unlikely(stats->stats_updated)) {
798a95db
BG		 1473 unsigned link_up = ntohl(stats->link_up);
1474 if (mgp->link_state != link_up) {
1475 mgp->link_state = link_up;
1476
1477 if (mgp->link_state == MXGEFW_LINK_UP) {
c58ac5ca
BG		 1478 if (netif_msg_link(mgp))
1479 printk(KERN_INFO
1480 "myri10ge: %s: link up\n",
1481 mgp->dev->name);
0da34b6d 1482 netif_carrier_on(mgp->dev);
c58ac5ca 1483 mgp->link_changes++;
0da34b6d 1484 } else {
c58ac5ca
BG		 1485 if (netif_msg_link(mgp))
1486 printk(KERN_INFO
798a95db
BG		 1487 "myri10ge: %s: link %s\n",
1488 mgp->dev->name,
1489 (link_up == MXGEFW_LINK_MYRINET ?
1490 "mismatch (Myrinet detected)" :
1491 "down"));
0da34b6d 1492 netif_carrier_off(mgp->dev);
c58ac5ca 1493 mgp->link_changes++;
0da34b6d
BG		 1494 }
1495 }
1496 if (mgp->rdma_tags_available !=
b53bef84 1497 ntohl(stats->rdma_tags_available)) {
0da34b6d 1498 mgp->rdma_tags_available =
b53bef84 1499 ntohl(stats->rdma_tags_available);
0da34b6d
BG		 1500 printk(KERN_WARNING "myri10ge: %s: RDMA timed out! "
1501 "%d tags left\n", mgp->dev->name,
1502 mgp->rdma_tags_available);
1503 }
1504 mgp->down_cnt += stats->link_down;
1505 if (stats->link_down)
1506 wake_up(&mgp->down_wq);
1507 }
1508}
1509
bea3348e 1510static int myri10ge_poll(struct napi_struct *napi, int budget)
0da34b6d 1511{
b53bef84
BG		 1512 struct myri10ge_slice_state *ss =
1513 container_of(napi, struct myri10ge_slice_state, napi);
bea3348e 1514 int work_done;
0da34b6d 1515
5dd2d332 1516#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 1517 if (ss->mgp->dca_enabled)
1518 myri10ge_update_dca(ss);
1519#endif
1520
0da34b6d 1521 /* process as many rx events as NAPI will allow */
b53bef84 1522 work_done = myri10ge_clean_rx_done(ss, budget);
0da34b6d 1523
4ec24119 1524 if (work_done < budget) {
288379f0 1525 napi_complete(napi);
b53bef84 1526 put_be32(htonl(3), ss->irq_claim);
0da34b6d 1527 }
bea3348e 1528 return work_done;
0da34b6d
BG		 1529}
1530
7d12e780 1531static irqreturn_t myri10ge_intr(int irq, void *arg)
0da34b6d 1532{
b53bef84
BG		 1533 struct myri10ge_slice_state *ss = arg;
1534 struct myri10ge_priv *mgp = ss->mgp;
1535 struct mcp_irq_data *stats = ss->fw_stats;
1536 struct myri10ge_tx_buf *tx = &ss->tx;
0da34b6d
BG		 1537 u32 send_done_count;
1538 int i;
1539
236bb5e6
BG		 1540 /* an interrupt on a non-zero receive-only slice is implicitly
1541 * valid since MSI-X irqs are not shared */
1542 if ((mgp->dev->real_num_tx_queues == 1) && (ss != mgp->ss)) {
288379f0 1543 napi_schedule(&ss->napi);
0dcffac1
BG		 1544 return (IRQ_HANDLED);
1545 }
1546
0da34b6d
BG		 1547 /* make sure it is our IRQ, and that the DMA has finished */
1548 if (unlikely(!stats->valid))
1549 return (IRQ_NONE);
1550
1551 /* low bit indicates receives are present, so schedule
1552 * napi poll handler */
1553 if (stats->valid & 1)
288379f0 1554 napi_schedule(&ss->napi);
0da34b6d 1555
0dcffac1 1556 if (!mgp->msi_enabled && !mgp->msix_enabled) {
40f6cff5 1557 put_be32(0, mgp->irq_deassert);
0da34b6d
BG		 1558 if (!myri10ge_deassert_wait)
1559 stats->valid = 0;
1560 mb();
1561 } else
1562 stats->valid = 0;
1563
1564 /* Wait for IRQ line to go low, if using INTx */
1565 i = 0;
1566 while (1) {
1567 i++;
1568 /* check for transmit completes and receives */
1569 send_done_count = ntohl(stats->send_done_count);
1570 if (send_done_count != tx->pkt_done)
b53bef84 1571 myri10ge_tx_done(ss, (int)send_done_count);
0da34b6d
BG		 1572 if (unlikely(i > myri10ge_max_irq_loops)) {
1573 printk(KERN_WARNING "myri10ge: %s: irq stuck?\n",
1574 mgp->dev->name);
1575 stats->valid = 0;
1576 schedule_work(&mgp->watchdog_work);
1577 }
1578 if (likely(stats->valid == 0))
1579 break;
1580 cpu_relax();
1581 barrier();
1582 }
1583
236bb5e6
BG		 1584 /* Only slice 0 updates stats */
1585 if (ss == mgp->ss)
1586 myri10ge_check_statblock(mgp);
0da34b6d 1587
b53bef84 1588 put_be32(htonl(3), ss->irq_claim + 1);
0da34b6d
BG		 1589 return (IRQ_HANDLED);
1590}
1591
1592static int
1593myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1594{
c0bf8801
BG		 1595 struct myri10ge_priv *mgp = netdev_priv(netdev);
1596 char *ptr;
1597 int i;
1598
0da34b6d
BG		 1599 cmd->autoneg = AUTONEG_DISABLE;
1600 cmd->speed = SPEED_10000;
1601 cmd->duplex = DUPLEX_FULL;
c0bf8801
BG		 1602
1603 /*
1604 * parse the product code to deterimine the interface type
1605 * (CX4, XFP, Quad Ribbon Fiber) by looking at the character
1606 * after the 3rd dash in the driver's cached copy of the
1607 * EEPROM's product code string.
1608 */
1609 ptr = mgp->product_code_string;
1610 if (ptr == NULL) {
1611 printk(KERN_ERR "myri10ge: %s: Missing product code\n",
99f5f87e 1612 netdev->name);
c0bf8801
BG		 1613 return 0;
1614 }
1615 for (i = 0; i < 3; i++, ptr++) {
1616 ptr = strchr(ptr, '-');
1617 if (ptr == NULL) {
1618 printk(KERN_ERR "myri10ge: %s: Invalid product "
1619 "code %s\n", netdev->name,
1620 mgp->product_code_string);
1621 return 0;
1622 }
1623 }
1624 if (*ptr == 'R' || *ptr == 'Q') {
1625 /* We've found either an XFP or quad ribbon fiber */
1626 cmd->port = PORT_FIBRE;
1627 }
0da34b6d
BG		 1628 return 0;
1629}
1630
1631static void
1632myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1633{
1634 struct myri10ge_priv *mgp = netdev_priv(netdev);
1635
1636 strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1637 strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1638 strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1639 strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1640}
1641
1642static int
1643myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1644{
1645 struct myri10ge_priv *mgp = netdev_priv(netdev);
99f5f87e 1646
0da34b6d
BG		 1647 coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1648 return 0;
1649}
1650
1651static int
1652myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1653{
1654 struct myri10ge_priv *mgp = netdev_priv(netdev);
1655
1656 mgp->intr_coal_delay = coal->rx_coalesce_usecs;
40f6cff5 1657 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d
BG		 1658 return 0;
1659}
1660
1661static void
1662myri10ge_get_pauseparam(struct net_device *netdev,
1663 struct ethtool_pauseparam *pause)
1664{
1665 struct myri10ge_priv *mgp = netdev_priv(netdev);
1666
1667 pause->autoneg = 0;
1668 pause->rx_pause = mgp->pause;
1669 pause->tx_pause = mgp->pause;
1670}
1671
1672static int
1673myri10ge_set_pauseparam(struct net_device *netdev,
1674 struct ethtool_pauseparam *pause)
1675{
1676 struct myri10ge_priv *mgp = netdev_priv(netdev);
1677
1678 if (pause->tx_pause != mgp->pause)
1679 return myri10ge_change_pause(mgp, pause->tx_pause);
1680 if (pause->rx_pause != mgp->pause)
1681 return myri10ge_change_pause(mgp, pause->tx_pause);
1682 if (pause->autoneg != 0)
1683 return -EINVAL;
1684 return 0;
1685}
1686
1687static void
1688myri10ge_get_ringparam(struct net_device *netdev,
1689 struct ethtool_ringparam *ring)
1690{
1691 struct myri10ge_priv *mgp = netdev_priv(netdev);
1692
0dcffac1
BG		 1693 ring->rx_mini_max_pending = mgp->ss[0].rx_small.mask + 1;
1694 ring->rx_max_pending = mgp->ss[0].rx_big.mask + 1;
0da34b6d 1695 ring->rx_jumbo_max_pending = 0;
6498be3f 1696 ring->tx_max_pending = mgp->ss[0].tx.mask + 1;
0da34b6d
BG		 1697 ring->rx_mini_pending = ring->rx_mini_max_pending;
1698 ring->rx_pending = ring->rx_max_pending;
1699 ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1700 ring->tx_pending = ring->tx_max_pending;
1701}
1702
1703static u32 myri10ge_get_rx_csum(struct net_device *netdev)
1704{
1705 struct myri10ge_priv *mgp = netdev_priv(netdev);
99f5f87e 1706
0da34b6d
BG		 1707 if (mgp->csum_flag)
1708 return 1;
1709 else
1710 return 0;
1711}
1712
1713static int myri10ge_set_rx_csum(struct net_device *netdev, u32 csum_enabled)
1714{
1715 struct myri10ge_priv *mgp = netdev_priv(netdev);
3a0c7d2d 1716 int err = 0;
99f5f87e 1717
0da34b6d
BG		 1718 if (csum_enabled)
1719 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
3a0c7d2d
BG		 1720 else {
1721 u32 flags = ethtool_op_get_flags(netdev);
1722 err = ethtool_op_set_flags(netdev, (flags & ~ETH_FLAG_LRO));
0da34b6d 1723 mgp->csum_flag = 0;
3a0c7d2d
BG		 1724
1725 }
1726 return err;
0da34b6d
BG		 1727}
1728
4f93fde0
BG		 1729static int myri10ge_set_tso(struct net_device *netdev, u32 tso_enabled)
1730{
1731 struct myri10ge_priv *mgp = netdev_priv(netdev);
1732 unsigned long flags = mgp->features & (NETIF_F_TSO6 | NETIF_F_TSO);
1733
1734 if (tso_enabled)
1735 netdev->features |= flags;
1736 else
1737 netdev->features &= ~flags;
1738 return 0;
1739}
1740
b53bef84 1741static const char myri10ge_gstrings_main_stats[][ETH_GSTRING_LEN] = {
0da34b6d
BG		 1742 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1743 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1744 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1745 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1746 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1747 "tx_heartbeat_errors", "tx_window_errors",
1748 /* device-specific stats */
0dcffac1 1749 "tx_boundary", "WC", "irq", "MSI", "MSIX",
0da34b6d 1750 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
b53bef84 1751 "serial_number", "watchdog_resets",
5dd2d332 1752#ifdef CONFIG_MYRI10GE_DCA
9a6b3b54 1753 "dca_capable_firmware", "dca_device_present",
981813d8 1754#endif
c58ac5ca 1755 "link_changes", "link_up", "dropped_link_overflow",
cee505db
BG		 1756 "dropped_link_error_or_filtered",
1757 "dropped_pause", "dropped_bad_phy", "dropped_bad_crc32",
1758 "dropped_unicast_filtered", "dropped_multicast_filtered",
0da34b6d 1759 "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
b53bef84
BG		 1760 "dropped_no_big_buffer"
1761};
1762
1763static const char myri10ge_gstrings_slice_stats[][ETH_GSTRING_LEN] = {
1764 "----------- slice ---------",
1765 "tx_pkt_start", "tx_pkt_done", "tx_req", "tx_done",
1766 "rx_small_cnt", "rx_big_cnt",
1767 "wake_queue", "stop_queue", "tx_linearized", "LRO aggregated",
1768 "LRO flushed",
1e6e9342 1769 "LRO avg aggr", "LRO no_desc"
0da34b6d
BG		 1770};
1771
1772#define MYRI10GE_NET_STATS_LEN 21
b53bef84
BG		 1773#define MYRI10GE_MAIN_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_main_stats)
1774#define MYRI10GE_SLICE_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_slice_stats)
0da34b6d
BG		 1775
1776static void
1777myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1778{
0dcffac1
BG		 1779 struct myri10ge_priv *mgp = netdev_priv(netdev);
1780 int i;
1781
0da34b6d
BG		 1782 switch (stringset) {
1783 case ETH_SS_STATS:
b53bef84
BG		 1784 memcpy(data, *myri10ge_gstrings_main_stats,
1785 sizeof(myri10ge_gstrings_main_stats));
1786 data += sizeof(myri10ge_gstrings_main_stats);
0dcffac1
BG		 1787 for (i = 0; i < mgp->num_slices; i++) {
1788 memcpy(data, *myri10ge_gstrings_slice_stats,
1789 sizeof(myri10ge_gstrings_slice_stats));
1790 data += sizeof(myri10ge_gstrings_slice_stats);
1791 }
0da34b6d
BG		 1792 break;
1793 }
1794}
1795
b9f2c044 1796static int myri10ge_get_sset_count(struct net_device *netdev, int sset)
0da34b6d 1797{
0dcffac1
BG		 1798 struct myri10ge_priv *mgp = netdev_priv(netdev);
1799
b9f2c044
JG		 1800 switch (sset) {
1801 case ETH_SS_STATS:
0dcffac1
BG		 1802 return MYRI10GE_MAIN_STATS_LEN +
1803 mgp->num_slices * MYRI10GE_SLICE_STATS_LEN;
b9f2c044
JG		 1804 default:
1805 return -EOPNOTSUPP;
1806 }
0da34b6d
BG		 1807}
1808
1809static void
1810myri10ge_get_ethtool_stats(struct net_device *netdev,
1811 struct ethtool_stats *stats, u64 * data)
1812{
1813 struct myri10ge_priv *mgp = netdev_priv(netdev);
b53bef84 1814 struct myri10ge_slice_state *ss;
0dcffac1 1815 int slice;
0da34b6d
BG		 1816 int i;
1817
59081825
BG		 1818 /* force stats update */
1819 (void)myri10ge_get_stats(netdev);
0da34b6d
BG		 1820 for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
1821 data[i] = ((unsigned long *)&mgp->stats)[i];
1822
b53bef84 1823 data[i++] = (unsigned int)mgp->tx_boundary;
276e26c3 1824 data[i++] = (unsigned int)mgp->wc_enabled;
2c1a1088
BG		 1825 data[i++] = (unsigned int)mgp->pdev->irq;
1826 data[i++] = (unsigned int)mgp->msi_enabled;
0dcffac1 1827 data[i++] = (unsigned int)mgp->msix_enabled;
0da34b6d
BG		 1828 data[i++] = (unsigned int)mgp->read_dma;
1829 data[i++] = (unsigned int)mgp->write_dma;
1830 data[i++] = (unsigned int)mgp->read_write_dma;
1831 data[i++] = (unsigned int)mgp->serial_number;
0da34b6d 1832 data[i++] = (unsigned int)mgp->watchdog_resets;
5dd2d332 1833#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 1834 data[i++] = (unsigned int)(mgp->ss[0].dca_tag != NULL);
1835 data[i++] = (unsigned int)(mgp->dca_enabled);
1836#endif
c58ac5ca 1837 data[i++] = (unsigned int)mgp->link_changes;
b53bef84
BG		 1838
1839 /* firmware stats are useful only in the first slice */
0dcffac1 1840 ss = &mgp->ss[0];
b53bef84
BG		 1841 data[i++] = (unsigned int)ntohl(ss->fw_stats->link_up);
1842 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_link_overflow);
cee505db 1843 data[i++] =
b53bef84
BG		 1844 (unsigned int)ntohl(ss->fw_stats->dropped_link_error_or_filtered);
1845 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_pause);
1846 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_phy);
1847 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_crc32);
1848 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_unicast_filtered);
85a7ea1b 1849 data[i++] =
b53bef84
BG		 1850 (unsigned int)ntohl(ss->fw_stats->dropped_multicast_filtered);
1851 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_runt);
1852 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_overrun);
1853 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_small_buffer);
1854 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_big_buffer);
1855
0dcffac1
BG		 1856 for (slice = 0; slice < mgp->num_slices; slice++) {
1857 ss = &mgp->ss[slice];
1858 data[i++] = slice;
1859 data[i++] = (unsigned int)ss->tx.pkt_start;
1860 data[i++] = (unsigned int)ss->tx.pkt_done;
1861 data[i++] = (unsigned int)ss->tx.req;
1862 data[i++] = (unsigned int)ss->tx.done;
1863 data[i++] = (unsigned int)ss->rx_small.cnt;
1864 data[i++] = (unsigned int)ss->rx_big.cnt;
1865 data[i++] = (unsigned int)ss->tx.wake_queue;
1866 data[i++] = (unsigned int)ss->tx.stop_queue;
1867 data[i++] = (unsigned int)ss->tx.linearized;
1868 data[i++] = ss->rx_done.lro_mgr.stats.aggregated;
1869 data[i++] = ss->rx_done.lro_mgr.stats.flushed;
1870 if (ss->rx_done.lro_mgr.stats.flushed)
1871 data[i++] = ss->rx_done.lro_mgr.stats.aggregated /
1872 ss->rx_done.lro_mgr.stats.flushed;
1873 else
1874 data[i++] = 0;
1875 data[i++] = ss->rx_done.lro_mgr.stats.no_desc;
1876 }
0da34b6d
BG		 1877}
1878
c58ac5ca
BG		 1879static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
1880{
1881 struct myri10ge_priv *mgp = netdev_priv(netdev);
1882 mgp->msg_enable = value;
1883}
1884
1885static u32 myri10ge_get_msglevel(struct net_device *netdev)
1886{
1887 struct myri10ge_priv *mgp = netdev_priv(netdev);
1888 return mgp->msg_enable;
1889}
1890
7282d491 1891static const struct ethtool_ops myri10ge_ethtool_ops = {
0da34b6d
BG		 1892 .get_settings = myri10ge_get_settings,
1893 .get_drvinfo = myri10ge_get_drvinfo,
1894 .get_coalesce = myri10ge_get_coalesce,
1895 .set_coalesce = myri10ge_set_coalesce,
1896 .get_pauseparam = myri10ge_get_pauseparam,
1897 .set_pauseparam = myri10ge_set_pauseparam,
1898 .get_ringparam = myri10ge_get_ringparam,
1899 .get_rx_csum = myri10ge_get_rx_csum,
1900 .set_rx_csum = myri10ge_set_rx_csum,
b10c0668 1901 .set_tx_csum = ethtool_op_set_tx_hw_csum,
0da34b6d 1902 .set_sg = ethtool_op_set_sg,
4f93fde0 1903 .set_tso = myri10ge_set_tso,
6ffdd071 1904 .get_link = ethtool_op_get_link,
0da34b6d 1905 .get_strings = myri10ge_get_strings,
b9f2c044 1906 .get_sset_count = myri10ge_get_sset_count,
c58ac5ca
BG		 1907 .get_ethtool_stats = myri10ge_get_ethtool_stats,
1908 .set_msglevel = myri10ge_set_msglevel,
3a0c7d2d
BG		 1909 .get_msglevel = myri10ge_get_msglevel,
1910 .get_flags = ethtool_op_get_flags,
1911 .set_flags = ethtool_op_set_flags
0da34b6d
BG		 1912};
1913
b53bef84 1914static int myri10ge_allocate_rings(struct myri10ge_slice_state *ss)
0da34b6d 1915{
b53bef84 1916 struct myri10ge_priv *mgp = ss->mgp;
0da34b6d 1917 struct myri10ge_cmd cmd;
b53bef84 1918 struct net_device *dev = mgp->dev;
0da34b6d
BG		 1919 int tx_ring_size, rx_ring_size;
1920 int tx_ring_entries, rx_ring_entries;
0dcffac1 1921 int i, slice, status;
0da34b6d
BG		 1922 size_t bytes;
1923
0da34b6d 1924 /* get ring sizes */
0dcffac1
BG		 1925 slice = ss - mgp->ss;
1926 cmd.data0 = slice;
0da34b6d
BG		 1927 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1928 tx_ring_size = cmd.data0;
0dcffac1 1929 cmd.data0 = slice;
0da34b6d 1930 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
355c7265
BG		 1931 if (status != 0)
1932 return status;
0da34b6d
BG		 1933 rx_ring_size = cmd.data0;
1934
1935 tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1936 rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
b53bef84
BG		 1937 ss->tx.mask = tx_ring_entries - 1;
1938 ss->rx_small.mask = ss->rx_big.mask = rx_ring_entries - 1;
0da34b6d 1939
355c7265
BG		 1940 status = -ENOMEM;
1941
0da34b6d
BG		 1942 /* allocate the host shadow rings */
1943
1944 bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
b53bef84
BG		 1945 * sizeof(*ss->tx.req_list);
1946 ss->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
1947 if (ss->tx.req_bytes == NULL)
0da34b6d
BG		 1948 goto abort_with_nothing;
1949
1950 /* ensure req_list entries are aligned to 8 bytes */
b53bef84
BG		 1951 ss->tx.req_list = (struct mcp_kreq_ether_send *)
1952 ALIGN((unsigned long)ss->tx.req_bytes, 8);
236bb5e6 1953 ss->tx.queue_active = 0;
0da34b6d 1954
b53bef84
BG		 1955 bytes = rx_ring_entries * sizeof(*ss->rx_small.shadow);
1956 ss->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
1957 if (ss->rx_small.shadow == NULL)
0da34b6d
BG		 1958 goto abort_with_tx_req_bytes;
1959
b53bef84
BG		 1960 bytes = rx_ring_entries * sizeof(*ss->rx_big.shadow);
1961 ss->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
1962 if (ss->rx_big.shadow == NULL)
0da34b6d
BG		 1963 goto abort_with_rx_small_shadow;
1964
1965 /* allocate the host info rings */
1966
b53bef84
BG		 1967 bytes = tx_ring_entries * sizeof(*ss->tx.info);
1968 ss->tx.info = kzalloc(bytes, GFP_KERNEL);
1969 if (ss->tx.info == NULL)
0da34b6d
BG		 1970 goto abort_with_rx_big_shadow;
1971
b53bef84
BG		 1972 bytes = rx_ring_entries * sizeof(*ss->rx_small.info);
1973 ss->rx_small.info = kzalloc(bytes, GFP_KERNEL);
1974 if (ss->rx_small.info == NULL)
0da34b6d
BG		 1975 goto abort_with_tx_info;
1976
b53bef84
BG		 1977 bytes = rx_ring_entries * sizeof(*ss->rx_big.info);
1978 ss->rx_big.info = kzalloc(bytes, GFP_KERNEL);
1979 if (ss->rx_big.info == NULL)
0da34b6d
BG		 1980 goto abort_with_rx_small_info;
1981
1982 /* Fill the receive rings */
b53bef84
BG		 1983 ss->rx_big.cnt = 0;
1984 ss->rx_small.cnt = 0;
1985 ss->rx_big.fill_cnt = 0;
1986 ss->rx_small.fill_cnt = 0;
1987 ss->rx_small.page_offset = MYRI10GE_ALLOC_SIZE;
1988 ss->rx_big.page_offset = MYRI10GE_ALLOC_SIZE;
1989 ss->rx_small.watchdog_needed = 0;
1990 ss->rx_big.watchdog_needed = 0;
1991 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
c7dab99b 1992 mgp->small_bytes + MXGEFW_PAD, 0);
0da34b6d 1993
b53bef84 1994 if (ss->rx_small.fill_cnt < ss->rx_small.mask + 1) {
0dcffac1
BG		 1995 printk(KERN_ERR
1996 "myri10ge: %s:slice-%d: alloced only %d small bufs\n",
1997 dev->name, slice, ss->rx_small.fill_cnt);
c7dab99b 1998 goto abort_with_rx_small_ring;
0da34b6d
BG		 1999 }
2000
b53bef84
BG		 2001 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
2002 if (ss->rx_big.fill_cnt < ss->rx_big.mask + 1) {
0dcffac1
BG		 2003 printk(KERN_ERR
2004 "myri10ge: %s:slice-%d: alloced only %d big bufs\n",
2005 dev->name, slice, ss->rx_big.fill_cnt);
c7dab99b 2006 goto abort_with_rx_big_ring;
0da34b6d
BG		 2007 }
2008
2009 return 0;
2010
2011abort_with_rx_big_ring:
b53bef84
BG		 2012 for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
2013 int idx = i & ss->rx_big.mask;
2014 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
c7dab99b 2015 mgp->big_bytes);
b53bef84 2016 put_page(ss->rx_big.info[idx].page);
0da34b6d
BG		 2017 }
2018
2019abort_with_rx_small_ring:
b53bef84
BG		 2020 for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
2021 int idx = i & ss->rx_small.mask;
2022 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
c7dab99b 2023 mgp->small_bytes + MXGEFW_PAD);
b53bef84 2024 put_page(ss->rx_small.info[idx].page);
0da34b6d 2025 }
c7dab99b 2026
b53bef84 2027 kfree(ss->rx_big.info);
0da34b6d
BG		 2028
2029abort_with_rx_small_info:
b53bef84 2030 kfree(ss->rx_small.info);
0da34b6d
BG		 2031
2032abort_with_tx_info:
b53bef84 2033 kfree(ss->tx.info);
0da34b6d
BG		 2034
2035abort_with_rx_big_shadow:
b53bef84 2036 kfree(ss->rx_big.shadow);
0da34b6d
BG		 2037
2038abort_with_rx_small_shadow:
b53bef84 2039 kfree(ss->rx_small.shadow);
0da34b6d
BG		 2040
2041abort_with_tx_req_bytes:
b53bef84
BG		 2042 kfree(ss->tx.req_bytes);
2043 ss->tx.req_bytes = NULL;
2044 ss->tx.req_list = NULL;
0da34b6d
BG		 2045
2046abort_with_nothing:
2047 return status;
2048}
2049
b53bef84 2050static void myri10ge_free_rings(struct myri10ge_slice_state *ss)
0da34b6d 2051{
b53bef84 2052 struct myri10ge_priv *mgp = ss->mgp;
0da34b6d
BG		 2053 struct sk_buff *skb;
2054 struct myri10ge_tx_buf *tx;
2055 int i, len, idx;
2056
0dcffac1
BG		 2057 /* If not allocated, skip it */
2058 if (ss->tx.req_list == NULL)
2059 return;
2060
b53bef84
BG		 2061 for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
2062 idx = i & ss->rx_big.mask;
2063 if (i == ss->rx_big.fill_cnt - 1)
2064 ss->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE;
2065 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
c7dab99b 2066 mgp->big_bytes);
b53bef84 2067 put_page(ss->rx_big.info[idx].page);
0da34b6d
BG		 2068 }
2069
b53bef84
BG		 2070 for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
2071 idx = i & ss->rx_small.mask;
2072 if (i == ss->rx_small.fill_cnt - 1)
2073 ss->rx_small.info[idx].page_offset =
c7dab99b 2074 MYRI10GE_ALLOC_SIZE;
b53bef84 2075 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
c7dab99b 2076 mgp->small_bytes + MXGEFW_PAD);
b53bef84 2077 put_page(ss->rx_small.info[idx].page);
c7dab99b 2078 }
b53bef84 2079 tx = &ss->tx;
0da34b6d
BG		 2080 while (tx->done != tx->req) {
2081 idx = tx->done & tx->mask;
2082 skb = tx->info[idx].skb;
2083
2084 /* Mark as free */
2085 tx->info[idx].skb = NULL;
2086 tx->done++;
2087 len = pci_unmap_len(&tx->info[idx], len);
2088 pci_unmap_len_set(&tx->info[idx], len, 0);
2089 if (skb) {
b53bef84 2090 ss->stats.tx_dropped++;
0da34b6d
BG		 2091 dev_kfree_skb_any(skb);
2092 if (len)
2093 pci_unmap_single(mgp->pdev,
2094 pci_unmap_addr(&tx->info[idx],
2095 bus), len,
2096 PCI_DMA_TODEVICE);
2097 } else {
2098 if (len)
2099 pci_unmap_page(mgp->pdev,
2100 pci_unmap_addr(&tx->info[idx],
2101 bus), len,
2102 PCI_DMA_TODEVICE);
2103 }
2104 }
b53bef84 2105 kfree(ss->rx_big.info);
0da34b6d 2106
b53bef84 2107 kfree(ss->rx_small.info);
0da34b6d 2108
b53bef84 2109 kfree(ss->tx.info);
0da34b6d 2110
b53bef84 2111 kfree(ss->rx_big.shadow);
0da34b6d 2112
b53bef84 2113 kfree(ss->rx_small.shadow);
0da34b6d 2114
b53bef84
BG		 2115 kfree(ss->tx.req_bytes);
2116 ss->tx.req_bytes = NULL;
2117 ss->tx.req_list = NULL;
0da34b6d
BG		 2118}
2119
df30a740
BG		 2120static int myri10ge_request_irq(struct myri10ge_priv *mgp)
2121{
2122 struct pci_dev *pdev = mgp->pdev;
0dcffac1
BG		 2123 struct myri10ge_slice_state *ss;
2124 struct net_device *netdev = mgp->dev;
2125 int i;
df30a740
BG		 2126 int status;
2127
0dcffac1
BG		 2128 mgp->msi_enabled = 0;
2129 mgp->msix_enabled = 0;
2130 status = 0;
df30a740 2131 if (myri10ge_msi) {
0dcffac1
BG		 2132 if (mgp->num_slices > 1) {
2133 status =
2134 pci_enable_msix(pdev, mgp->msix_vectors,
2135 mgp->num_slices);
2136 if (status == 0) {
2137 mgp->msix_enabled = 1;
2138 } else {
2139 dev_err(&pdev->dev,
2140 "Error %d setting up MSI-X\n", status);
2141 return status;
2142 }
2143 }
2144 if (mgp->msix_enabled == 0) {
2145 status = pci_enable_msi(pdev);
2146 if (status != 0) {
2147 dev_err(&pdev->dev,
2148 "Error %d setting up MSI; falling back to xPIC\n",
2149 status);
2150 } else {
2151 mgp->msi_enabled = 1;
2152 }
2153 }
df30a740 2154 }
0dcffac1
BG		 2155 if (mgp->msix_enabled) {
2156 for (i = 0; i < mgp->num_slices; i++) {
2157 ss = &mgp->ss[i];
2158 snprintf(ss->irq_desc, sizeof(ss->irq_desc),
2159 "%s:slice-%d", netdev->name, i);
2160 status = request_irq(mgp->msix_vectors[i].vector,
2161 myri10ge_intr, 0, ss->irq_desc,
2162 ss);
2163 if (status != 0) {
2164 dev_err(&pdev->dev,
2165 "slice %d failed to allocate IRQ\n", i);
2166 i--;
2167 while (i >= 0) {
2168 free_irq(mgp->msix_vectors[i].vector,
2169 &mgp->ss[i]);
2170 i--;
2171 }
2172 pci_disable_msix(pdev);
2173 return status;
2174 }
2175 }
2176 } else {
2177 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
2178 mgp->dev->name, &mgp->ss[0]);
2179 if (status != 0) {
2180 dev_err(&pdev->dev, "failed to allocate IRQ\n");
2181 if (mgp->msi_enabled)
2182 pci_disable_msi(pdev);
2183 }
df30a740
BG		 2184 }
2185 return status;
2186}
2187
2188static void myri10ge_free_irq(struct myri10ge_priv *mgp)
2189{
2190 struct pci_dev *pdev = mgp->pdev;
0dcffac1 2191 int i;
df30a740 2192
0dcffac1
BG		 2193 if (mgp->msix_enabled) {
2194 for (i = 0; i < mgp->num_slices; i++)
2195 free_irq(mgp->msix_vectors[i].vector, &mgp->ss[i]);
2196 } else {
2197 free_irq(pdev->irq, &mgp->ss[0]);
2198 }
df30a740
BG		 2199 if (mgp->msi_enabled)
2200 pci_disable_msi(pdev);
0dcffac1
BG		 2201 if (mgp->msix_enabled)
2202 pci_disable_msix(pdev);
df30a740
BG		 2203}
2204
1e6e9342
AG		 2205static int
2206myri10ge_get_frag_header(struct skb_frag_struct *frag, void **mac_hdr,
2207 void **ip_hdr, void **tcpudp_hdr,
2208 u64 * hdr_flags, void *priv)
2209{
2210 struct ethhdr *eh;
2211 struct vlan_ethhdr *veh;
2212 struct iphdr *iph;
2213 u8 *va = page_address(frag->page) + frag->page_offset;
2214 unsigned long ll_hlen;
66341fff
AV		 2215 /* passed opaque through lro_receive_frags() */
2216 __wsum csum = (__force __wsum) (unsigned long)priv;
1e6e9342
AG		 2217
2218 /* find the mac header, aborting if not IPv4 */
2219
2220 eh = (struct ethhdr *)va;
2221 *mac_hdr = eh;
2222 ll_hlen = ETH_HLEN;
2223 if (eh->h_proto != htons(ETH_P_IP)) {
2224 if (eh->h_proto == htons(ETH_P_8021Q)) {
2225 veh = (struct vlan_ethhdr *)va;
2226 if (veh->h_vlan_encapsulated_proto != htons(ETH_P_IP))
2227 return -1;
2228
2229 ll_hlen += VLAN_HLEN;
2230
2231 /*
2232 * HW checksum starts ETH_HLEN bytes into
2233 * frame, so we must subtract off the VLAN
2234 * header's checksum before csum can be used
2235 */
2236 csum = csum_sub(csum, csum_partial(va + ETH_HLEN,
2237 VLAN_HLEN, 0));
2238 } else {
2239 return -1;
2240 }
2241 }
2242 *hdr_flags = LRO_IPV4;
2243
2244 iph = (struct iphdr *)(va + ll_hlen);
2245 *ip_hdr = iph;
2246 if (iph->protocol != IPPROTO_TCP)
2247 return -1;
bcb09dc2
BG		 2248 if (iph->frag_off & htons(IP_MF | IP_OFFSET))
2249 return -1;
1e6e9342
AG		 2250 *hdr_flags |= LRO_TCP;
2251 *tcpudp_hdr = (u8 *) (*ip_hdr) + (iph->ihl << 2);
2252
2253 /* verify the IP checksum */
2254 if (unlikely(ip_fast_csum((u8 *) iph, iph->ihl)))
2255 return -1;
2256
2257 /* verify the checksum */
2258 if (unlikely(csum_tcpudp_magic(iph->saddr, iph->daddr,
2259 ntohs(iph->tot_len) - (iph->ihl << 2),
2260 IPPROTO_TCP, csum)))
2261 return -1;
2262
2263 return 0;
2264}
2265
77929732
BG		 2266static int myri10ge_get_txrx(struct myri10ge_priv *mgp, int slice)
2267{
2268 struct myri10ge_cmd cmd;
2269 struct myri10ge_slice_state *ss;
2270 int status;
2271
2272 ss = &mgp->ss[slice];
236bb5e6
BG		 2273 status = 0;
2274 if (slice == 0 || (mgp->dev->real_num_tx_queues > 1)) {
2275 cmd.data0 = slice;
2276 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET,
2277 &cmd, 0);
2278 ss->tx.lanai = (struct mcp_kreq_ether_send __iomem *)
2279 (mgp->sram + cmd.data0);
2280 }
77929732
BG		 2281 cmd.data0 = slice;
2282 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET,
2283 &cmd, 0);
2284 ss->rx_small.lanai = (struct mcp_kreq_ether_recv __iomem *)
2285 (mgp->sram + cmd.data0);
2286
2287 cmd.data0 = slice;
2288 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
2289 ss->rx_big.lanai = (struct mcp_kreq_ether_recv __iomem *)
2290 (mgp->sram + cmd.data0);
2291
236bb5e6
BG		 2292 ss->tx.send_go = (__iomem __be32 *)
2293 (mgp->sram + MXGEFW_ETH_SEND_GO + 64 * slice);
2294 ss->tx.send_stop = (__iomem __be32 *)
2295 (mgp->sram + MXGEFW_ETH_SEND_STOP + 64 * slice);
77929732
BG		 2296 return status;
2297
2298}
2299
2300static int myri10ge_set_stats(struct myri10ge_priv *mgp, int slice)
2301{
2302 struct myri10ge_cmd cmd;
2303 struct myri10ge_slice_state *ss;
2304 int status;
2305
2306 ss = &mgp->ss[slice];
2307 cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->fw_stats_bus);
2308 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->fw_stats_bus);
236bb5e6 2309 cmd.data2 = sizeof(struct mcp_irq_data) | (slice << 16);
77929732
BG		 2310 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
2311 if (status == -ENOSYS) {
2312 dma_addr_t bus = ss->fw_stats_bus;
2313 if (slice != 0)
2314 return -EINVAL;
2315 bus += offsetof(struct mcp_irq_data, send_done_count);
2316 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
2317 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
2318 status = myri10ge_send_cmd(mgp,
2319 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
2320 &cmd, 0);
2321 /* Firmware cannot support multicast without STATS_DMA_V2 */
2322 mgp->fw_multicast_support = 0;
2323 } else {
2324 mgp->fw_multicast_support = 1;
2325 }
2326 return 0;
2327}
77929732 2328
0da34b6d
BG		 2329static int myri10ge_open(struct net_device *dev)
2330{
0dcffac1 2331 struct myri10ge_slice_state *ss;
b53bef84 2332 struct myri10ge_priv *mgp = netdev_priv(dev);
0da34b6d 2333 struct myri10ge_cmd cmd;
0dcffac1
BG		 2334 int i, status, big_pow2, slice;
2335 u8 *itable;
1e6e9342 2336 struct net_lro_mgr *lro_mgr;
0da34b6d 2337
0da34b6d
BG		 2338 if (mgp->running != MYRI10GE_ETH_STOPPED)
2339 return -EBUSY;
2340
2341 mgp->running = MYRI10GE_ETH_STARTING;
2342 status = myri10ge_reset(mgp);
2343 if (status != 0) {
2344 printk(KERN_ERR "myri10ge: %s: failed reset\n", dev->name);
df30a740 2345 goto abort_with_nothing;
0da34b6d
BG		 2346 }
2347
0dcffac1
BG		 2348 if (mgp->num_slices > 1) {
2349 cmd.data0 = mgp->num_slices;
236bb5e6
BG		 2350 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
2351 if (mgp->dev->real_num_tx_queues > 1)
2352 cmd.data1 |= MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES;
0dcffac1
BG		 2353 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
2354 &cmd, 0);
2355 if (status != 0) {
2356 printk(KERN_ERR
2357 "myri10ge: %s: failed to set number of slices\n",
2358 dev->name);
2359 goto abort_with_nothing;
2360 }
2361 /* setup the indirection table */
2362 cmd.data0 = mgp->num_slices;
2363 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_TABLE_SIZE,
2364 &cmd, 0);
2365
2366 status |= myri10ge_send_cmd(mgp,
2367 MXGEFW_CMD_GET_RSS_TABLE_OFFSET,
2368 &cmd, 0);
2369 if (status != 0) {
2370 printk(KERN_ERR
2371 "myri10ge: %s: failed to setup rss tables\n",
2372 dev->name);
236bb5e6 2373 goto abort_with_nothing;
0dcffac1
BG		 2374 }
2375
2376 /* just enable an identity mapping */
2377 itable = mgp->sram + cmd.data0;
2378 for (i = 0; i < mgp->num_slices; i++)
2379 __raw_writeb(i, &itable[i]);
2380
2381 cmd.data0 = 1;
2382 cmd.data1 = myri10ge_rss_hash;
2383 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_ENABLE,
2384 &cmd, 0);
2385 if (status != 0) {
2386 printk(KERN_ERR
2387 "myri10ge: %s: failed to enable slices\n",
2388 dev->name);
2389 goto abort_with_nothing;
2390 }
2391 }
2392
df30a740
BG		 2393 status = myri10ge_request_irq(mgp);
2394 if (status != 0)
2395 goto abort_with_nothing;
2396
0da34b6d
BG		 2397 /* decide what small buffer size to use. For good TCP rx
2398 * performance, it is important to not receive 1514 byte
2399 * frames into jumbo buffers, as it confuses the socket buffer
2400 * accounting code, leading to drops and erratic performance.
2401 */
2402
2403 if (dev->mtu <= ETH_DATA_LEN)
c7dab99b
BG		 2404 /* enough for a TCP header */
2405 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
2406 ? (128 - MXGEFW_PAD)
2407 : (SMP_CACHE_BYTES - MXGEFW_PAD);
0da34b6d 2408 else
de3c4507
BG		 2409 /* enough for a vlan encapsulated ETH_DATA_LEN frame */
2410 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
0da34b6d
BG		 2411
2412 /* Override the small buffer size? */
2413 if (myri10ge_small_bytes > 0)
2414 mgp->small_bytes = myri10ge_small_bytes;
2415
0da34b6d
BG		 2416 /* Firmware needs the big buff size as a power of 2. Lie and
2417 * tell him the buffer is larger, because we only use 1
2418 * buffer/pkt, and the mtu will prevent overruns.
2419 */
13348bee 2420 big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b 2421 if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) {
199126a2 2422 while (!is_power_of_2(big_pow2))
c7dab99b 2423 big_pow2++;
13348bee 2424 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b
BG		 2425 } else {
2426 big_pow2 = MYRI10GE_ALLOC_SIZE;
2427 mgp->big_bytes = big_pow2;
2428 }
2429
0dcffac1
BG		 2430 /* setup the per-slice data structures */
2431 for (slice = 0; slice < mgp->num_slices; slice++) {
2432 ss = &mgp->ss[slice];
2433
2434 status = myri10ge_get_txrx(mgp, slice);
2435 if (status != 0) {
2436 printk(KERN_ERR
2437 "myri10ge: %s: failed to get ring sizes or locations\n",
2438 dev->name);
2439 goto abort_with_rings;
2440 }
2441 status = myri10ge_allocate_rings(ss);
2442 if (status != 0)
2443 goto abort_with_rings;
236bb5e6
BG		 2444
2445 /* only firmware which supports multiple TX queues
2446 * supports setting up the tx stats on non-zero
2447 * slices */
2448 if (slice == 0 || mgp->dev->real_num_tx_queues > 1)
0dcffac1
BG		 2449 status = myri10ge_set_stats(mgp, slice);
2450 if (status) {
2451 printk(KERN_ERR
2452 "myri10ge: %s: Couldn't set stats DMA\n",
2453 dev->name);
2454 goto abort_with_rings;
2455 }
2456
2457 lro_mgr = &ss->rx_done.lro_mgr;
2458 lro_mgr->dev = dev;
2459 lro_mgr->features = LRO_F_NAPI;
2460 lro_mgr->ip_summed = CHECKSUM_COMPLETE;
2461 lro_mgr->ip_summed_aggr = CHECKSUM_UNNECESSARY;
2462 lro_mgr->max_desc = MYRI10GE_MAX_LRO_DESCRIPTORS;
2463 lro_mgr->lro_arr = ss->rx_done.lro_desc;
2464 lro_mgr->get_frag_header = myri10ge_get_frag_header;
2465 lro_mgr->max_aggr = myri10ge_lro_max_pkts;
636d2f68 2466 lro_mgr->frag_align_pad = 2;
0dcffac1
BG		 2467 if (lro_mgr->max_aggr > MAX_SKB_FRAGS)
2468 lro_mgr->max_aggr = MAX_SKB_FRAGS;
2469
2470 /* must happen prior to any irq */
2471 napi_enable(&(ss)->napi);
2472 }
0da34b6d
BG		 2473
2474 /* now give firmware buffers sizes, and MTU */
2475 cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
2476 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
2477 cmd.data0 = mgp->small_bytes;
2478 status |=
2479 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
2480 cmd.data0 = big_pow2;
2481 status |=
2482 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
2483 if (status) {
2484 printk(KERN_ERR "myri10ge: %s: Couldn't set buffer sizes\n",
2485 dev->name);
2486 goto abort_with_rings;
2487 }
2488
0dcffac1
BG		 2489 /*
2490 * Set Linux style TSO mode; this is needed only on newer
2491 * firmware versions. Older versions default to Linux
2492 * style TSO
2493 */
2494 cmd.data0 = 0;
2495 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_TSO_MODE, &cmd, 0);
2496 if (status && status != -ENOSYS) {
2497 printk(KERN_ERR "myri10ge: %s: Couldn't set TSO mode\n",
0da34b6d
BG		 2498 dev->name);
2499 goto abort_with_rings;
2500 }
2501
66341fff 2502 mgp->link_state = ~0U;
0da34b6d
BG		 2503 mgp->rdma_tags_available = 15;
2504
0da34b6d
BG		 2505 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
2506 if (status) {
2507 printk(KERN_ERR "myri10ge: %s: Couldn't bring up link\n",
2508 dev->name);
2509 goto abort_with_rings;
2510 }
2511
0da34b6d
BG		 2512 mgp->running = MYRI10GE_ETH_RUNNING;
2513 mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
2514 add_timer(&mgp->watchdog_timer);
236bb5e6
BG		 2515 netif_tx_wake_all_queues(dev);
2516
0da34b6d
BG		 2517 return 0;
2518
2519abort_with_rings:
051d36f3
BG		 2520 while (slice) {
2521 slice--;
2522 napi_disable(&mgp->ss[slice].napi);
2523 }
0dcffac1
BG		 2524 for (i = 0; i < mgp->num_slices; i++)
2525 myri10ge_free_rings(&mgp->ss[i]);
0da34b6d 2526
df30a740
BG		 2527 myri10ge_free_irq(mgp);
2528
0da34b6d
BG		 2529abort_with_nothing:
2530 mgp->running = MYRI10GE_ETH_STOPPED;
2531 return -ENOMEM;
2532}
2533
2534static int myri10ge_close(struct net_device *dev)
2535{
b53bef84 2536 struct myri10ge_priv *mgp = netdev_priv(dev);
0da34b6d
BG		 2537 struct myri10ge_cmd cmd;
2538 int status, old_down_cnt;
0dcffac1 2539 int i;
0da34b6d 2540
0da34b6d
BG		 2541 if (mgp->running != MYRI10GE_ETH_RUNNING)
2542 return 0;
2543
0dcffac1 2544 if (mgp->ss[0].tx.req_bytes == NULL)
0da34b6d
BG		 2545 return 0;
2546
2547 del_timer_sync(&mgp->watchdog_timer);
2548 mgp->running = MYRI10GE_ETH_STOPPING;
0dcffac1
BG		 2549 for (i = 0; i < mgp->num_slices; i++) {
2550 napi_disable(&mgp->ss[i].napi);
2551 }
0da34b6d 2552 netif_carrier_off(dev);
236bb5e6
BG		 2553
2554 netif_tx_stop_all_queues(dev);
0da34b6d
BG		 2555 old_down_cnt = mgp->down_cnt;
2556 mb();
2557 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
2558 if (status)
2559 printk(KERN_ERR "myri10ge: %s: Couldn't bring down link\n",
2560 dev->name);
2561
2562 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt, HZ);
2563 if (old_down_cnt == mgp->down_cnt)
2564 printk(KERN_ERR "myri10ge: %s never got down irq\n", dev->name);
2565
2566 netif_tx_disable(dev);
df30a740 2567 myri10ge_free_irq(mgp);
0dcffac1
BG		 2568 for (i = 0; i < mgp->num_slices; i++)
2569 myri10ge_free_rings(&mgp->ss[i]);
0da34b6d
BG		 2570
2571 mgp->running = MYRI10GE_ETH_STOPPED;
2572 return 0;
2573}
2574
2575/* copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2576 * backwards one at a time and handle ring wraps */
2577
2578static inline void
2579myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
2580 struct mcp_kreq_ether_send *src, int cnt)
2581{
2582 int idx, starting_slot;
2583 starting_slot = tx->req;
2584 while (cnt > 1) {
2585 cnt--;
2586 idx = (starting_slot + cnt) & tx->mask;
2587 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
2588 mb();
2589 }
2590}
2591
2592/*
2593 * copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2594 * at most 32 bytes at a time, so as to avoid involving the software
2595 * pio handler in the nic. We re-write the first segment's flags
2596 * to mark them valid only after writing the entire chain.
2597 */
2598
2599static inline void
2600myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
2601 int cnt)
2602{
2603 int idx, i;
2604 struct mcp_kreq_ether_send __iomem *dstp, *dst;
2605 struct mcp_kreq_ether_send *srcp;
2606 u8 last_flags;
2607
2608 idx = tx->req & tx->mask;
2609
2610 last_flags = src->flags;
2611 src->flags = 0;
2612 mb();
2613 dst = dstp = &tx->lanai[idx];
2614 srcp = src;
2615
2616 if ((idx + cnt) < tx->mask) {
2617 for (i = 0; i < (cnt - 1); i += 2) {
2618 myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
2619 mb(); /* force write every 32 bytes */
2620 srcp += 2;
2621 dstp += 2;
2622 }
2623 } else {
2624 /* submit all but the first request, and ensure
2625 * that it is submitted below */
2626 myri10ge_submit_req_backwards(tx, src, cnt);
2627 i = 0;
2628 }
2629 if (i < cnt) {
2630 /* submit the first request */
2631 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
2632 mb(); /* barrier before setting valid flag */
2633 }
2634
2635 /* re-write the last 32-bits with the valid flags */
2636 src->flags = last_flags;
40f6cff5 2637 put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
0da34b6d
BG		 2638 tx->req += cnt;
2639 mb();
2640}
2641
0da34b6d
BG		 2642/*
2643 * Transmit a packet. We need to split the packet so that a single
b53bef84 2644 * segment does not cross myri10ge->tx_boundary, so this makes segment
0da34b6d
BG		 2645 * counting tricky. So rather than try to count segments up front, we
2646 * just give up if there are too few segments to hold a reasonably
2647 * fragmented packet currently available. If we run
2648 * out of segments while preparing a packet for DMA, we just linearize
2649 * it and try again.
2650 */
2651
2652static int myri10ge_xmit(struct sk_buff *skb, struct net_device *dev)
2653{
2654 struct myri10ge_priv *mgp = netdev_priv(dev);
b53bef84 2655 struct myri10ge_slice_state *ss;
0da34b6d 2656 struct mcp_kreq_ether_send *req;
b53bef84 2657 struct myri10ge_tx_buf *tx;
0da34b6d 2658 struct skb_frag_struct *frag;
236bb5e6 2659 struct netdev_queue *netdev_queue;
0da34b6d 2660 dma_addr_t bus;
40f6cff5
AV		 2661 u32 low;
2662 __be32 high_swapped;
0da34b6d
BG		 2663 unsigned int len;
2664 int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
236bb5e6 2665 u16 pseudo_hdr_offset, cksum_offset, queue;
0da34b6d
BG		 2666 int cum_len, seglen, boundary, rdma_count;
2667 u8 flags, odd_flag;
2668
236bb5e6 2669 queue = skb_get_queue_mapping(skb);
236bb5e6
BG		 2670 ss = &mgp->ss[queue];
2671 netdev_queue = netdev_get_tx_queue(mgp->dev, queue);
b53bef84 2672 tx = &ss->tx;
236bb5e6 2673
0da34b6d
BG		 2674again:
2675 req = tx->req_list;
2676 avail = tx->mask - 1 - (tx->req - tx->done);
2677
2678 mss = 0;
2679 max_segments = MXGEFW_MAX_SEND_DESC;
2680
917690cd 2681 if (skb_is_gso(skb)) {
7967168c 2682 mss = skb_shinfo(skb)->gso_size;
917690cd 2683 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
0da34b6d 2684 }
0da34b6d
BG		 2685
2686 if ((unlikely(avail < max_segments))) {
2687 /* we are out of transmit resources */
b53bef84 2688 tx->stop_queue++;
236bb5e6 2689 netif_tx_stop_queue(netdev_queue);
5b548140 2690 return NETDEV_TX_BUSY;
0da34b6d
BG		 2691 }
2692
2693 /* Setup checksum offloading, if needed */
2694 cksum_offset = 0;
2695 pseudo_hdr_offset = 0;
2696 odd_flag = 0;
2697 flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
84fa7933 2698 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
ea2ae17d 2699 cksum_offset = skb_transport_offset(skb);
ff1dcadb 2700 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
0da34b6d
BG		 2701 /* If the headers are excessively large, then we must
2702 * fall back to a software checksum */
4f93fde0
BG		 2703 if (unlikely(!mss && (cksum_offset > 255 ||
2704 pseudo_hdr_offset > 127))) {
84fa7933 2705 if (skb_checksum_help(skb))
0da34b6d
BG		 2706 goto drop;
2707 cksum_offset = 0;
2708 pseudo_hdr_offset = 0;
2709 } else {
0da34b6d
BG		 2710 odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2711 flags |= MXGEFW_FLAGS_CKSUM;
2712 }
2713 }
2714
2715 cum_len = 0;
2716
0da34b6d
BG		 2717 if (mss) { /* TSO */
2718 /* this removes any CKSUM flag from before */
2719 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
2720
2721 /* negative cum_len signifies to the
2722 * send loop that we are still in the
2723 * header portion of the TSO packet.
4f93fde0 2724 * TSO header can be at most 1KB long */
ab6a5bb6 2725 cum_len = -(skb_transport_offset(skb) + tcp_hdrlen(skb));
0da34b6d 2726
4f93fde0
BG		 2727 /* for IPv6 TSO, the checksum offset stores the
2728 * TCP header length, to save the firmware from
2729 * the need to parse the headers */
2730 if (skb_is_gso_v6(skb)) {
2731 cksum_offset = tcp_hdrlen(skb);
2732 /* Can only handle headers <= max_tso6 long */
2733 if (unlikely(-cum_len > mgp->max_tso6))
2734 return myri10ge_sw_tso(skb, dev);
2735 }
0da34b6d
BG		 2736 /* for TSO, pseudo_hdr_offset holds mss.
2737 * The firmware figures out where to put
2738 * the checksum by parsing the header. */
40f6cff5 2739 pseudo_hdr_offset = mss;
0da34b6d 2740 } else
0da34b6d
BG		 2741 /* Mark small packets, and pad out tiny packets */
2742 if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
2743 flags |= MXGEFW_FLAGS_SMALL;
2744
2745 /* pad frames to at least ETH_ZLEN bytes */
2746 if (unlikely(skb->len < ETH_ZLEN)) {
5b057c6b 2747 if (skb_padto(skb, ETH_ZLEN)) {
0da34b6d
BG		 2748 /* The packet is gone, so we must
2749 * return 0 */
b53bef84 2750 ss->stats.tx_dropped += 1;
6ed10654 2751 return NETDEV_TX_OK;
0da34b6d
BG		 2752 }
2753 /* adjust the len to account for the zero pad
2754 * so that the nic can know how long it is */
2755 skb->len = ETH_ZLEN;
2756 }
2757 }
2758
2759 /* map the skb for DMA */
2760 len = skb->len - skb->data_len;
2761 idx = tx->req & tx->mask;
2762 tx->info[idx].skb = skb;
2763 bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
2764 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2765 pci_unmap_len_set(&tx->info[idx], len, len);
2766
2767 frag_cnt = skb_shinfo(skb)->nr_frags;
2768 frag_idx = 0;
2769 count = 0;
2770 rdma_count = 0;
2771
2772 /* "rdma_count" is the number of RDMAs belonging to the
2773 * current packet BEFORE the current send request. For
2774 * non-TSO packets, this is equal to "count".
2775 * For TSO packets, rdma_count needs to be reset
2776 * to 0 after a segment cut.
2777 *
2778 * The rdma_count field of the send request is
2779 * the number of RDMAs of the packet starting at
2780 * that request. For TSO send requests with one ore more cuts
2781 * in the middle, this is the number of RDMAs starting
2782 * after the last cut in the request. All previous
2783 * segments before the last cut implicitly have 1 RDMA.
2784 *
2785 * Since the number of RDMAs is not known beforehand,
2786 * it must be filled-in retroactively - after each
2787 * segmentation cut or at the end of the entire packet.
2788 */
2789
2790 while (1) {
2791 /* Break the SKB or Fragment up into pieces which
b53bef84 2792 * do not cross mgp->tx_boundary */
0da34b6d
BG		 2793 low = MYRI10GE_LOWPART_TO_U32(bus);
2794 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2795 while (len) {
2796 u8 flags_next;
2797 int cum_len_next;
2798
2799 if (unlikely(count == max_segments))
2800 goto abort_linearize;
2801
b53bef84
BG		 2802 boundary =
2803 (low + mgp->tx_boundary) & ~(mgp->tx_boundary - 1);
0da34b6d
BG		 2804 seglen = boundary - low;
2805 if (seglen > len)
2806 seglen = len;
2807 flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2808 cum_len_next = cum_len + seglen;
0da34b6d
BG		 2809 if (mss) { /* TSO */
2810 (req - rdma_count)->rdma_count = rdma_count + 1;
2811
2812 if (likely(cum_len >= 0)) { /* payload */
2813 int next_is_first, chop;
2814
2815 chop = (cum_len_next > mss);
2816 cum_len_next = cum_len_next % mss;
2817 next_is_first = (cum_len_next == 0);
2818 flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2819 flags_next |= next_is_first *
2820 MXGEFW_FLAGS_FIRST;
2821 rdma_count |= -(chop | next_is_first);
2822 rdma_count += chop & !next_is_first;
2823 } else if (likely(cum_len_next >= 0)) { /* header ends */
2824 int small;
2825
2826 rdma_count = -1;
2827 cum_len_next = 0;
2828 seglen = -cum_len;
2829 small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2830 flags_next = MXGEFW_FLAGS_TSO_PLD |
2831 MXGEFW_FLAGS_FIRST |
2832 (small * MXGEFW_FLAGS_SMALL);
2833 }
2834 }
0da34b6d
BG		 2835 req->addr_high = high_swapped;
2836 req->addr_low = htonl(low);
40f6cff5 2837 req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
0da34b6d
BG		 2838 req->pad = 0; /* complete solid 16-byte block; does this matter? */
2839 req->rdma_count = 1;
2840 req->length = htons(seglen);
2841 req->cksum_offset = cksum_offset;
2842 req->flags = flags | ((cum_len & 1) * odd_flag);
2843
2844 low += seglen;
2845 len -= seglen;
2846 cum_len = cum_len_next;
2847 flags = flags_next;
2848 req++;
2849 count++;
2850 rdma_count++;
4f93fde0
BG		 2851 if (cksum_offset != 0 && !(mss && skb_is_gso_v6(skb))) {
2852 if (unlikely(cksum_offset > seglen))
2853 cksum_offset -= seglen;
2854 else
2855 cksum_offset = 0;
2856 }
0da34b6d
BG		 2857 }
2858 if (frag_idx == frag_cnt)
2859 break;
2860
2861 /* map next fragment for DMA */
2862 idx = (count + tx->req) & tx->mask;
2863 frag = &skb_shinfo(skb)->frags[frag_idx];
2864 frag_idx++;
2865 len = frag->size;
2866 bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset,
2867 len, PCI_DMA_TODEVICE);
2868 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2869 pci_unmap_len_set(&tx->info[idx], len, len);
2870 }
2871
2872 (req - rdma_count)->rdma_count = rdma_count;
0da34b6d
BG		 2873 if (mss)
2874 do {
2875 req--;
2876 req->flags |= MXGEFW_FLAGS_TSO_LAST;
2877 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2878 MXGEFW_FLAGS_FIRST)));
0da34b6d
BG		 2879 idx = ((count - 1) + tx->req) & tx->mask;
2880 tx->info[idx].last = 1;
e454e7e2 2881 myri10ge_submit_req(tx, tx->req_list, count);
236bb5e6
BG		 2882 /* if using multiple tx queues, make sure NIC polls the
2883 * current slice */
2884 if ((mgp->dev->real_num_tx_queues > 1) && tx->queue_active == 0) {
2885 tx->queue_active = 1;
2886 put_be32(htonl(1), tx->send_go);
8c2f5fa5 2887 mb();
6824a105 2888 mmiowb();
236bb5e6 2889 }
0da34b6d
BG		 2890 tx->pkt_start++;
2891 if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
b53bef84 2892 tx->stop_queue++;
236bb5e6 2893 netif_tx_stop_queue(netdev_queue);
0da34b6d 2894 }
6ed10654 2895 return NETDEV_TX_OK;
0da34b6d
BG		 2896
2897abort_linearize:
2898 /* Free any DMA resources we've alloced and clear out the skb
2899 * slot so as to not trip up assertions, and to avoid a
2900 * double-free if linearizing fails */
2901
2902 last_idx = (idx + 1) & tx->mask;
2903 idx = tx->req & tx->mask;
2904 tx->info[idx].skb = NULL;
2905 do {
2906 len = pci_unmap_len(&tx->info[idx], len);
2907 if (len) {
2908 if (tx->info[idx].skb != NULL)
2909 pci_unmap_single(mgp->pdev,
2910 pci_unmap_addr(&tx->info[idx],
2911 bus), len,
2912 PCI_DMA_TODEVICE);
2913 else
2914 pci_unmap_page(mgp->pdev,
2915 pci_unmap_addr(&tx->info[idx],
2916 bus), len,
2917 PCI_DMA_TODEVICE);
2918 pci_unmap_len_set(&tx->info[idx], len, 0);
2919 tx->info[idx].skb = NULL;
2920 }
2921 idx = (idx + 1) & tx->mask;
2922 } while (idx != last_idx);
89114afd 2923 if (skb_is_gso(skb)) {
0da34b6d
BG		 2924 printk(KERN_ERR
2925 "myri10ge: %s: TSO but wanted to linearize?!?!?\n",
2926 mgp->dev->name);
2927 goto drop;
2928 }
2929
bec0e859 2930 if (skb_linearize(skb))
0da34b6d
BG		 2931 goto drop;
2932
b53bef84 2933 tx->linearized++;
0da34b6d
BG		 2934 goto again;
2935
2936drop:
2937 dev_kfree_skb_any(skb);
b53bef84 2938 ss->stats.tx_dropped += 1;
6ed10654 2939 return NETDEV_TX_OK;
0da34b6d
BG		 2940
2941}
2942
4f93fde0
BG		 2943static int myri10ge_sw_tso(struct sk_buff *skb, struct net_device *dev)
2944{
2945 struct sk_buff *segs, *curr;
b53bef84 2946 struct myri10ge_priv *mgp = netdev_priv(dev);
d6279c88 2947 struct myri10ge_slice_state *ss;
4f93fde0
BG		 2948 int status;
2949
2950 segs = skb_gso_segment(skb, dev->features & ~NETIF_F_TSO6);
801678c5 2951 if (IS_ERR(segs))
4f93fde0
BG		 2952 goto drop;
2953
2954 while (segs) {
2955 curr = segs;
2956 segs = segs->next;
2957 curr->next = NULL;
2958 status = myri10ge_xmit(curr, dev);
2959 if (status != 0) {
2960 dev_kfree_skb_any(curr);
2961 if (segs != NULL) {
2962 curr = segs;
2963 segs = segs->next;
2964 curr->next = NULL;
2965 dev_kfree_skb_any(segs);
2966 }
2967 goto drop;
2968 }
2969 }
2970 dev_kfree_skb_any(skb);
2971 return 0;
2972
2973drop:
d6279c88 2974 ss = &mgp->ss[skb_get_queue_mapping(skb)];
4f93fde0 2975 dev_kfree_skb_any(skb);
d6279c88 2976 ss->stats.tx_dropped += 1;
4f93fde0
BG		 2977 return 0;
2978}
2979
0da34b6d
BG		 2980static struct net_device_stats *myri10ge_get_stats(struct net_device *dev)
2981{
2982 struct myri10ge_priv *mgp = netdev_priv(dev);
0dcffac1
BG		 2983 struct myri10ge_slice_netstats *slice_stats;
2984 struct net_device_stats *stats = &mgp->stats;
2985 int i;
2986
59081825 2987 spin_lock(&mgp->stats_lock);
0dcffac1
BG		 2988 memset(stats, 0, sizeof(*stats));
2989 for (i = 0; i < mgp->num_slices; i++) {
2990 slice_stats = &mgp->ss[i].stats;
2991 stats->rx_packets += slice_stats->rx_packets;
2992 stats->tx_packets += slice_stats->tx_packets;
2993 stats->rx_bytes += slice_stats->rx_bytes;
2994 stats->tx_bytes += slice_stats->tx_bytes;
2995 stats->rx_dropped += slice_stats->rx_dropped;
2996 stats->tx_dropped += slice_stats->tx_dropped;
2997 }
59081825 2998 spin_unlock(&mgp->stats_lock);
0dcffac1 2999 return stats;
0da34b6d
BG		 3000}
3001
3002static void myri10ge_set_multicast_list(struct net_device *dev)
3003{
b53bef84 3004 struct myri10ge_priv *mgp = netdev_priv(dev);
85a7ea1b 3005 struct myri10ge_cmd cmd;
85a7ea1b 3006 struct dev_mc_list *mc_list;
6250223e 3007 __be32 data[2] = { 0, 0 };
85a7ea1b
BG		 3008 int err;
3009
0da34b6d
BG		 3010 /* can be called from atomic contexts,
3011 * pass 1 to force atomicity in myri10ge_send_cmd() */
85a7ea1b
BG		 3012 myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
3013
3014 /* This firmware is known to not support multicast */
2f76216f 3015 if (!mgp->fw_multicast_support)
85a7ea1b
BG		 3016 return;
3017
3018 /* Disable multicast filtering */
3019
3020 err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
3021 if (err != 0) {
3022 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_ENABLE_ALLMULTI,"
3023 " error status: %d\n", dev->name, err);
3024 goto abort;
3025 }
3026
2f76216f 3027 if ((dev->flags & IFF_ALLMULTI) || mgp->adopted_rx_filter_bug) {
85a7ea1b
BG		 3028 /* request to disable multicast filtering, so quit here */
3029 return;
3030 }
3031
3032 /* Flush the filters */
3033
3034 err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
3035 &cmd, 1);
3036 if (err != 0) {
3037 printk(KERN_ERR
3038 "myri10ge: %s: Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS"
3039 ", error status: %d\n", dev->name, err);
3040 goto abort;
3041 }
3042
3043 /* Walk the multicast list, and add each address */
3044 for (mc_list = dev->mc_list; mc_list != NULL; mc_list = mc_list->next) {
40f6cff5
AV		 3045 memcpy(data, &mc_list->dmi_addr, 6);
3046 cmd.data0 = ntohl(data[0]);
3047 cmd.data1 = ntohl(data[1]);
85a7ea1b
BG		 3048 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
3049 &cmd, 1);
3050
3051 if (err != 0) {
3052 printk(KERN_ERR "myri10ge: %s: Failed "
3053 "MXGEFW_JOIN_MULTICAST_GROUP, error status:"
3054 "%d\t", dev->name, err);
e174961c 3055 printk(KERN_ERR "MAC %pM\n", mc_list->dmi_addr);
85a7ea1b
BG		 3056 goto abort;
3057 }
3058 }
3059 /* Enable multicast filtering */
3060 err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
3061 if (err != 0) {
3062 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_DISABLE_ALLMULTI,"
3063 "error status: %d\n", dev->name, err);
3064 goto abort;
3065 }
3066
3067 return;
3068
3069abort:
3070 return;
0da34b6d
BG		 3071}
3072
3073static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
3074{
3075 struct sockaddr *sa = addr;
3076 struct myri10ge_priv *mgp = netdev_priv(dev);
3077 int status;
3078
3079 if (!is_valid_ether_addr(sa->sa_data))
3080 return -EADDRNOTAVAIL;
3081
3082 status = myri10ge_update_mac_address(mgp, sa->sa_data);
3083 if (status != 0) {
3084 printk(KERN_ERR
3085 "myri10ge: %s: changing mac address failed with %d\n",
3086 dev->name, status);
3087 return status;
3088 }
3089
3090 /* change the dev structure */
3091 memcpy(dev->dev_addr, sa->sa_data, 6);
3092 return 0;
3093}
3094
3095static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
3096{
3097 struct myri10ge_priv *mgp = netdev_priv(dev);
3098 int error = 0;
3099
3100 if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
3101 printk(KERN_ERR "myri10ge: %s: new mtu (%d) is not valid\n",
3102 dev->name, new_mtu);
3103 return -EINVAL;
3104 }
3105 printk(KERN_INFO "%s: changing mtu from %d to %d\n",
3106 dev->name, dev->mtu, new_mtu);
3107 if (mgp->running) {
3108 /* if we change the mtu on an active device, we must
3109 * reset the device so the firmware sees the change */
3110 myri10ge_close(dev);
3111 dev->mtu = new_mtu;
3112 myri10ge_open(dev);
3113 } else
3114 dev->mtu = new_mtu;
3115
3116 return error;
3117}
3118
3119/*
3120 * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
3121 * Only do it if the bridge is a root port since we don't want to disturb
3122 * any other device, except if forced with myri10ge_ecrc_enable > 1.
3123 */
3124
0da34b6d
BG		 3125static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
3126{
3127 struct pci_dev *bridge = mgp->pdev->bus->self;
3128 struct device *dev = &mgp->pdev->dev;
3129 unsigned cap;
3130 unsigned err_cap;
3131 u16 val;
3132 u8 ext_type;
3133 int ret;
3134
3135 if (!myri10ge_ecrc_enable || !bridge)
3136 return;
3137
3138 /* check that the bridge is a root port */
3139 cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
3140 pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
3141 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
3142 if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
3143 if (myri10ge_ecrc_enable > 1) {
eca3fd83 3144 struct pci_dev *prev_bridge, *old_bridge = bridge;
0da34b6d
BG		 3145
3146 /* Walk the hierarchy up to the root port
3147 * where ECRC has to be enabled */
3148 do {
eca3fd83 3149 prev_bridge = bridge;
0da34b6d 3150 bridge = bridge->bus->self;
eca3fd83 3151 if (!bridge || prev_bridge == bridge) {
0da34b6d
BG		 3152 dev_err(dev,
3153 "Failed to find root port"
3154 " to force ECRC\n");
3155 return;
3156 }
3157 cap =
3158 pci_find_capability(bridge, PCI_CAP_ID_EXP);
3159 pci_read_config_word(bridge,
3160 cap + PCI_CAP_FLAGS, &val);
3161 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
3162 } while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
3163
3164 dev_info(dev,
3165 "Forcing ECRC on non-root port %s"
3166 " (enabling on root port %s)\n",
3167 pci_name(old_bridge), pci_name(bridge));
3168 } else {
3169 dev_err(dev,
3170 "Not enabling ECRC on non-root port %s\n",
3171 pci_name(bridge));
3172 return;
3173 }
3174 }
3175
3176 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
0da34b6d
BG		 3177 if (!cap)
3178 return;
3179
3180 ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
3181 if (ret) {
3182 dev_err(dev, "failed reading ext-conf-space of %s\n",
3183 pci_name(bridge));
3184 dev_err(dev, "\t pci=nommconf in use? "
3185 "or buggy/incomplete/absent ACPI MCFG attr?\n");
3186 return;
3187 }
3188 if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
3189 return;
3190
3191 err_cap |= PCI_ERR_CAP_ECRC_GENE;
3192 pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
3193 dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
0da34b6d
BG		 3194}
3195
3196/*
3197 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
3198 * when the PCI-E Completion packets are aligned on an 8-byte
3199 * boundary. Some PCI-E chip sets always align Completion packets; on
3200 * the ones that do not, the alignment can be enforced by enabling
3201 * ECRC generation (if supported).
3202 *
3203 * When PCI-E Completion packets are not aligned, it is actually more
3204 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
3205 *
3206 * If the driver can neither enable ECRC nor verify that it has
3207 * already been enabled, then it must use a firmware image which works
0dcffac1 3208 * around unaligned completion packets (myri10ge_rss_ethp_z8e.dat), and it
0da34b6d 3209 * should also ensure that it never gives the device a Read-DMA which is
b53bef84 3210 * larger than 2KB by setting the tx_boundary to 2KB. If ECRC is
0dcffac1 3211 * enabled, then the driver should use the aligned (myri10ge_rss_eth_z8e.dat)
b53bef84 3212 * firmware image, and set tx_boundary to 4KB.
0da34b6d
BG		 3213 */
3214
5443e9ea 3215static void myri10ge_firmware_probe(struct myri10ge_priv *mgp)
0da34b6d 3216{
5443e9ea
BG		 3217 struct pci_dev *pdev = mgp->pdev;
3218 struct device *dev = &pdev->dev;
302d242c 3219 int status;
0da34b6d 3220
b53bef84 3221 mgp->tx_boundary = 4096;
5443e9ea
BG		 3222 /*
3223 * Verify the max read request size was set to 4KB
3224 * before trying the test with 4KB.
3225 */
302d242c
BG		 3226 status = pcie_get_readrq(pdev);
3227 if (status < 0) {
5443e9ea
BG		 3228 dev_err(dev, "Couldn't read max read req size: %d\n", status);
3229 goto abort;
3230 }
302d242c
BG		 3231 if (status != 4096) {
3232 dev_warn(dev, "Max Read Request size != 4096 (%d)\n", status);
b53bef84 3233 mgp->tx_boundary = 2048;
5443e9ea
BG		 3234 }
3235 /*
3236 * load the optimized firmware (which assumes aligned PCIe
3237 * completions) in order to see if it works on this host.
3238 */
3239 mgp->fw_name = myri10ge_fw_aligned;
0dcffac1 3240 status = myri10ge_load_firmware(mgp, 1);
5443e9ea
BG		 3241 if (status != 0) {
3242 goto abort;
3243 }
3244
3245 /*
3246 * Enable ECRC if possible
3247 */
3248 myri10ge_enable_ecrc(mgp);
3249
3250 /*
3251 * Run a DMA test which watches for unaligned completions and
3252 * aborts on the first one seen.
3253 */
3254
3255 status = myri10ge_dma_test(mgp, MXGEFW_CMD_UNALIGNED_TEST);
3256 if (status == 0)
3257 return; /* keep the aligned firmware */
3258
3259 if (status != -E2BIG)
3260 dev_warn(dev, "DMA test failed: %d\n", status);
3261 if (status == -ENOSYS)
3262 dev_warn(dev, "Falling back to ethp! "
3263 "Please install up to date fw\n");
3264abort:
3265 /* fall back to using the unaligned firmware */
b53bef84 3266 mgp->tx_boundary = 2048;
0da34b6d
BG		 3267 mgp->fw_name = myri10ge_fw_unaligned;
3268
5443e9ea
BG		 3269}
3270
3271static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
3272{
2d90b0aa
BG		 3273 int overridden = 0;
3274
0da34b6d 3275 if (myri10ge_force_firmware == 0) {
ce7f9368
BG		 3276 int link_width, exp_cap;
3277 u16 lnk;
3278
3279 exp_cap = pci_find_capability(mgp->pdev, PCI_CAP_ID_EXP);
3280 pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
3281 link_width = (lnk >> 4) & 0x3f;
3282
ce7f9368
BG		 3283 /* Check to see if Link is less than 8 or if the
3284 * upstream bridge is known to provide aligned
3285 * completions */
3286 if (link_width < 8) {
3287 dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
3288 link_width);
b53bef84 3289 mgp->tx_boundary = 4096;
ce7f9368 3290 mgp->fw_name = myri10ge_fw_aligned;
5443e9ea
BG		 3291 } else {
3292 myri10ge_firmware_probe(mgp);
0da34b6d
BG		 3293 }
3294 } else {
3295 if (myri10ge_force_firmware == 1) {
3296 dev_info(&mgp->pdev->dev,
3297 "Assuming aligned completions (forced)\n");
b53bef84 3298 mgp->tx_boundary = 4096;
0da34b6d
BG		 3299 mgp->fw_name = myri10ge_fw_aligned;
3300 } else {
3301 dev_info(&mgp->pdev->dev,
3302 "Assuming unaligned completions (forced)\n");
b53bef84 3303 mgp->tx_boundary = 2048;
0da34b6d
BG		 3304 mgp->fw_name = myri10ge_fw_unaligned;
3305 }
3306 }
3307 if (myri10ge_fw_name != NULL) {
2d90b0aa 3308 overridden = 1;
0da34b6d
BG		 3309 mgp->fw_name = myri10ge_fw_name;
3310 }
2d90b0aa
BG		 3311 if (mgp->board_number < MYRI10GE_MAX_BOARDS &&
3312 myri10ge_fw_names[mgp->board_number] != NULL &&
3313 strlen(myri10ge_fw_names[mgp->board_number])) {
3314 mgp->fw_name = myri10ge_fw_names[mgp->board_number];
3315 overridden = 1;
3316 }
3317 if (overridden)
3318 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
3319 mgp->fw_name);
0da34b6d
BG		 3320}
3321
0da34b6d 3322#ifdef CONFIG_PM
0da34b6d
BG		 3323static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
3324{
3325 struct myri10ge_priv *mgp;
3326 struct net_device *netdev;
3327
3328 mgp = pci_get_drvdata(pdev);
3329 if (mgp == NULL)
3330 return -EINVAL;
3331 netdev = mgp->dev;
3332
3333 netif_device_detach(netdev);
3334 if (netif_running(netdev)) {
3335 printk(KERN_INFO "myri10ge: closing %s\n", netdev->name);
3336 rtnl_lock();
3337 myri10ge_close(netdev);
3338 rtnl_unlock();
3339 }
3340 myri10ge_dummy_rdma(mgp, 0);
83f6e152 3341 pci_save_state(pdev);
0da34b6d 3342 pci_disable_device(pdev);
1a63e846
BG		 3343
3344 return pci_set_power_state(pdev, pci_choose_state(pdev, state));
0da34b6d
BG		 3345}
3346
3347static int myri10ge_resume(struct pci_dev *pdev)
3348{
3349 struct myri10ge_priv *mgp;
3350 struct net_device *netdev;
3351 int status;
3352 u16 vendor;
3353
3354 mgp = pci_get_drvdata(pdev);
3355 if (mgp == NULL)
3356 return -EINVAL;
3357 netdev = mgp->dev;
3358 pci_set_power_state(pdev, 0); /* zeros conf space as a side effect */
3359 msleep(5); /* give card time to respond */
3360 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3361 if (vendor == 0xffff) {
3362 printk(KERN_ERR "myri10ge: %s: device disappeared!\n",
3363 mgp->dev->name);
3364 return -EIO;
3365 }
83f6e152 3366
1a63e846
BG		 3367 status = pci_restore_state(pdev);
3368 if (status)
3369 return status;
4c2248cc
BG		 3370
3371 status = pci_enable_device(pdev);
1a63e846 3372 if (status) {
4c2248cc 3373 dev_err(&pdev->dev, "failed to enable device\n");
1a63e846 3374 return status;
4c2248cc
BG		 3375 }
3376
0da34b6d
BG		 3377 pci_set_master(pdev);
3378
0da34b6d 3379 myri10ge_reset(mgp);
013b68bf 3380 myri10ge_dummy_rdma(mgp, 1);
0da34b6d
BG		 3381
3382 /* Save configuration space to be restored if the
3383 * nic resets due to a parity error */
83f6e152 3384 pci_save_state(pdev);
0da34b6d
BG		 3385
3386 if (netif_running(netdev)) {
3387 rtnl_lock();
df30a740 3388 status = myri10ge_open(netdev);
0da34b6d 3389 rtnl_unlock();
df30a740
BG		 3390 if (status != 0)
3391 goto abort_with_enabled;
3392
0da34b6d
BG		 3393 }
3394 netif_device_attach(netdev);
3395
3396 return 0;
3397
4c2248cc
BG		 3398abort_with_enabled:
3399 pci_disable_device(pdev);
0da34b6d
BG		 3400 return -EIO;
3401
3402}
0da34b6d
BG		 3403#endif /* CONFIG_PM */
3404
3405static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
3406{
3407 struct pci_dev *pdev = mgp->pdev;
3408 int vs = mgp->vendor_specific_offset;
3409 u32 reboot;
3410
3411 /*enter read32 mode */
3412 pci_write_config_byte(pdev, vs + 0x10, 0x3);
3413
3414 /*read REBOOT_STATUS (0xfffffff0) */
3415 pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
3416 pci_read_config_dword(pdev, vs + 0x14, &reboot);
3417 return reboot;
3418}
3419
3420/*
3421 * This watchdog is used to check whether the board has suffered
3422 * from a parity error and needs to be recovered.
3423 */
c4028958 3424static void myri10ge_watchdog(struct work_struct *work)
0da34b6d 3425{
c4028958 3426 struct myri10ge_priv *mgp =
6250223e 3427 container_of(work, struct myri10ge_priv, watchdog_work);
b53bef84 3428 struct myri10ge_tx_buf *tx;
0da34b6d
BG		 3429 u32 reboot;
3430 int status;
0dcffac1 3431 int i;
0da34b6d
BG		 3432 u16 cmd, vendor;
3433
3434 mgp->watchdog_resets++;
3435 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
3436 if ((cmd & PCI_COMMAND_MASTER) == 0) {
3437 /* Bus master DMA disabled? Check to see
3438 * if the card rebooted due to a parity error
3439 * For now, just report it */
3440 reboot = myri10ge_read_reboot(mgp);
3441 printk(KERN_ERR
f181137f
BG		 3442 "myri10ge: %s: NIC rebooted (0x%x),%s resetting\n",
3443 mgp->dev->name, reboot,
3444 myri10ge_reset_recover ? " " : " not");
3445 if (myri10ge_reset_recover == 0)
3446 return;
3447
3448 myri10ge_reset_recover--;
3449
0da34b6d
BG		 3450 /*
3451 * A rebooted nic will come back with config space as
3452 * it was after power was applied to PCIe bus.
3453 * Attempt to restore config space which was saved
3454 * when the driver was loaded, or the last time the
3455 * nic was resumed from power saving mode.
3456 */
83f6e152 3457 pci_restore_state(mgp->pdev);
7adda30c
BG		 3458
3459 /* save state again for accounting reasons */
83f6e152 3460 pci_save_state(mgp->pdev);
7adda30c 3461
0da34b6d
BG		 3462 } else {
3463 /* if we get back -1's from our slot, perhaps somebody
3464 * powered off our card. Don't try to reset it in
3465 * this case */
3466 if (cmd == 0xffff) {
3467 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3468 if (vendor == 0xffff) {
3469 printk(KERN_ERR
3470 "myri10ge: %s: device disappeared!\n",
3471 mgp->dev->name);
3472 return;
3473 }
3474 }
3475 /* Perhaps it is a software error. Try to reset */
3476
3477 printk(KERN_ERR "myri10ge: %s: device timeout, resetting\n",
3478 mgp->dev->name);
0dcffac1
BG		 3479 for (i = 0; i < mgp->num_slices; i++) {
3480 tx = &mgp->ss[i].tx;
3481 printk(KERN_INFO
236bb5e6
BG		 3482 "myri10ge: %s: (%d): %d %d %d %d %d %d\n",
3483 mgp->dev->name, i, tx->queue_active, tx->req,
3484 tx->done, tx->pkt_start, tx->pkt_done,
0dcffac1
BG		 3485 (int)ntohl(mgp->ss[i].fw_stats->
3486 send_done_count));
3487 msleep(2000);
3488 printk(KERN_INFO
236bb5e6
BG		 3489 "myri10ge: %s: (%d): %d %d %d %d %d %d\n",
3490 mgp->dev->name, i, tx->queue_active, tx->req,
3491 tx->done, tx->pkt_start, tx->pkt_done,
0dcffac1
BG		 3492 (int)ntohl(mgp->ss[i].fw_stats->
3493 send_done_count));
3494 }
0da34b6d 3495 }
236bb5e6 3496
0da34b6d
BG		 3497 rtnl_lock();
3498 myri10ge_close(mgp->dev);
0dcffac1 3499 status = myri10ge_load_firmware(mgp, 1);
0da34b6d
BG		 3500 if (status != 0)
3501 printk(KERN_ERR "myri10ge: %s: failed to load firmware\n",
3502 mgp->dev->name);
3503 else
3504 myri10ge_open(mgp->dev);
3505 rtnl_unlock();
3506}
3507
3508/*
3509 * We use our own timer routine rather than relying upon
3510 * netdev->tx_timeout because we have a very large hardware transmit
3511 * queue. Due to the large queue, the netdev->tx_timeout function
3512 * cannot detect a NIC with a parity error in a timely fashion if the
3513 * NIC is lightly loaded.
3514 */
3515static void myri10ge_watchdog_timer(unsigned long arg)
3516{
3517 struct myri10ge_priv *mgp;
b53bef84 3518 struct myri10ge_slice_state *ss;
0dcffac1 3519 int i, reset_needed;
626fda94 3520 u32 rx_pause_cnt;
0da34b6d
BG		 3521
3522 mgp = (struct myri10ge_priv *)arg;
c7dab99b 3523
0dcffac1
BG		 3524 rx_pause_cnt = ntohl(mgp->ss[0].fw_stats->dropped_pause);
3525 for (i = 0, reset_needed = 0;
3526 i < mgp->num_slices && reset_needed == 0; ++i) {
b53bef84 3527
0dcffac1
BG		 3528 ss = &mgp->ss[i];
3529 if (ss->rx_small.watchdog_needed) {
3530 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
3531 mgp->small_bytes + MXGEFW_PAD,
3532 1);
3533 if (ss->rx_small.fill_cnt - ss->rx_small.cnt >=
3534 myri10ge_fill_thresh)
3535 ss->rx_small.watchdog_needed = 0;
3536 }
3537 if (ss->rx_big.watchdog_needed) {
3538 myri10ge_alloc_rx_pages(mgp, &ss->rx_big,
3539 mgp->big_bytes, 1);
3540 if (ss->rx_big.fill_cnt - ss->rx_big.cnt >=
3541 myri10ge_fill_thresh)
3542 ss->rx_big.watchdog_needed = 0;
3543 }
3544
3545 if (ss->tx.req != ss->tx.done &&
3546 ss->tx.done == ss->watchdog_tx_done &&
3547 ss->watchdog_tx_req != ss->watchdog_tx_done) {
3548 /* nic seems like it might be stuck.. */
3549 if (rx_pause_cnt != mgp->watchdog_pause) {
3550 if (net_ratelimit())
236bb5e6
BG		 3551 printk(KERN_WARNING
3552 "myri10ge %s slice %d:"
0dcffac1 3553 "TX paused, check link partner\n",
236bb5e6 3554 mgp->dev->name, i);
0dcffac1 3555 } else {
236bb5e6
BG		 3556 printk(KERN_WARNING
3557 "myri10ge %s slice %d stuck:",
3558 mgp->dev->name, i);
0dcffac1
BG		 3559 reset_needed = 1;
3560 }
626fda94 3561 }
0dcffac1
BG		 3562 ss->watchdog_tx_done = ss->tx.done;
3563 ss->watchdog_tx_req = ss->tx.req;
626fda94 3564 }
626fda94 3565 mgp->watchdog_pause = rx_pause_cnt;
0dcffac1
BG		 3566
3567 if (reset_needed) {
3568 schedule_work(&mgp->watchdog_work);
3569 } else {
3570 /* rearm timer */
3571 mod_timer(&mgp->watchdog_timer,
3572 jiffies + myri10ge_watchdog_timeout * HZ);
3573 }
0da34b6d
BG		 3574}
3575
77929732
BG		 3576static void myri10ge_free_slices(struct myri10ge_priv *mgp)
3577{
3578 struct myri10ge_slice_state *ss;
3579 struct pci_dev *pdev = mgp->pdev;
3580 size_t bytes;
3581 int i;
3582
3583 if (mgp->ss == NULL)
3584 return;
3585
3586 for (i = 0; i < mgp->num_slices; i++) {
3587 ss = &mgp->ss[i];
3588 if (ss->rx_done.entry != NULL) {
3589 bytes = mgp->max_intr_slots *
3590 sizeof(*ss->rx_done.entry);
3591 dma_free_coherent(&pdev->dev, bytes,
3592 ss->rx_done.entry, ss->rx_done.bus);
3593 ss->rx_done.entry = NULL;
3594 }
3595 if (ss->fw_stats != NULL) {
3596 bytes = sizeof(*ss->fw_stats);
3597 dma_free_coherent(&pdev->dev, bytes,
3598 ss->fw_stats, ss->fw_stats_bus);
3599 ss->fw_stats = NULL;
3600 }
3601 }
3602 kfree(mgp->ss);
3603 mgp->ss = NULL;
3604}
3605
3606static int myri10ge_alloc_slices(struct myri10ge_priv *mgp)
3607{
3608 struct myri10ge_slice_state *ss;
3609 struct pci_dev *pdev = mgp->pdev;
3610 size_t bytes;
3611 int i;
3612
3613 bytes = sizeof(*mgp->ss) * mgp->num_slices;
3614 mgp->ss = kzalloc(bytes, GFP_KERNEL);
3615 if (mgp->ss == NULL) {
3616 return -ENOMEM;
3617 }
3618
3619 for (i = 0; i < mgp->num_slices; i++) {
3620 ss = &mgp->ss[i];
3621 bytes = mgp->max_intr_slots * sizeof(*ss->rx_done.entry);
3622 ss->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
3623 &ss->rx_done.bus,
3624 GFP_KERNEL);
3625 if (ss->rx_done.entry == NULL)
3626 goto abort;
3627 memset(ss->rx_done.entry, 0, bytes);
3628 bytes = sizeof(*ss->fw_stats);
3629 ss->fw_stats = dma_alloc_coherent(&pdev->dev, bytes,
3630 &ss->fw_stats_bus,
3631 GFP_KERNEL);
3632 if (ss->fw_stats == NULL)
3633 goto abort;
3634 ss->mgp = mgp;
3635 ss->dev = mgp->dev;
3636 netif_napi_add(ss->dev, &ss->napi, myri10ge_poll,
3637 myri10ge_napi_weight);
3638 }
3639 return 0;
3640abort:
3641 myri10ge_free_slices(mgp);
3642 return -ENOMEM;
3643}
3644
3645/*
3646 * This function determines the number of slices supported.
3647 * The number slices is the minumum of the number of CPUS,
3648 * the number of MSI-X irqs supported, the number of slices
3649 * supported by the firmware
3650 */
3651static void myri10ge_probe_slices(struct myri10ge_priv *mgp)
3652{
3653 struct myri10ge_cmd cmd;
3654 struct pci_dev *pdev = mgp->pdev;
3655 char *old_fw;
3656 int i, status, ncpus, msix_cap;
3657
3658 mgp->num_slices = 1;
3659 msix_cap = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
3660 ncpus = num_online_cpus();
3661
3662 if (myri10ge_max_slices == 1 || msix_cap == 0 ||
3663 (myri10ge_max_slices == -1 && ncpus < 2))
3664 return;
3665
3666 /* try to load the slice aware rss firmware */
3667 old_fw = mgp->fw_name;
13b2738c
BG		 3668 if (myri10ge_fw_name != NULL) {
3669 dev_info(&mgp->pdev->dev, "overriding rss firmware to %s\n",
3670 myri10ge_fw_name);
3671 mgp->fw_name = myri10ge_fw_name;
3672 } else if (old_fw == myri10ge_fw_aligned)
77929732
BG		 3673 mgp->fw_name = myri10ge_fw_rss_aligned;
3674 else
3675 mgp->fw_name = myri10ge_fw_rss_unaligned;
3676 status = myri10ge_load_firmware(mgp, 0);
3677 if (status != 0) {
3678 dev_info(&pdev->dev, "Rss firmware not found\n");
3679 return;
3680 }
3681
3682 /* hit the board with a reset to ensure it is alive */
3683 memset(&cmd, 0, sizeof(cmd));
3684 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
3685 if (status != 0) {
3686 dev_err(&mgp->pdev->dev, "failed reset\n");
3687 goto abort_with_fw;
3688 return;
3689 }
3690
3691 mgp->max_intr_slots = cmd.data0 / sizeof(struct mcp_slot);
3692
3693 /* tell it the size of the interrupt queues */
3694 cmd.data0 = mgp->max_intr_slots * sizeof(struct mcp_slot);
3695 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
3696 if (status != 0) {
3697 dev_err(&mgp->pdev->dev, "failed MXGEFW_CMD_SET_INTRQ_SIZE\n");
3698 goto abort_with_fw;
3699 }
3700
3701 /* ask the maximum number of slices it supports */
3702 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES, &cmd, 0);
3703 if (status != 0)
3704 goto abort_with_fw;
3705 else
3706 mgp->num_slices = cmd.data0;
3707
3708 /* Only allow multiple slices if MSI-X is usable */
3709 if (!myri10ge_msi) {
3710 goto abort_with_fw;
3711 }
3712
3713 /* if the admin did not specify a limit to how many
3714 * slices we should use, cap it automatically to the
3715 * number of CPUs currently online */
3716 if (myri10ge_max_slices == -1)
3717 myri10ge_max_slices = ncpus;
3718
3719 if (mgp->num_slices > myri10ge_max_slices)
3720 mgp->num_slices = myri10ge_max_slices;
3721
3722 /* Now try to allocate as many MSI-X vectors as we have
3723 * slices. We give up on MSI-X if we can only get a single
3724 * vector. */
3725
3726 mgp->msix_vectors = kzalloc(mgp->num_slices *
3727 sizeof(*mgp->msix_vectors), GFP_KERNEL);
3728 if (mgp->msix_vectors == NULL)
3729 goto disable_msix;
3730 for (i = 0; i < mgp->num_slices; i++) {
3731 mgp->msix_vectors[i].entry = i;
3732 }
3733
3734 while (mgp->num_slices > 1) {
3735 /* make sure it is a power of two */
3736 while (!is_power_of_2(mgp->num_slices))
3737 mgp->num_slices--;
3738 if (mgp->num_slices == 1)
3739 goto disable_msix;
3740 status = pci_enable_msix(pdev, mgp->msix_vectors,
3741 mgp->num_slices);
3742 if (status == 0) {
3743 pci_disable_msix(pdev);
3744 return;
3745 }
3746 if (status > 0)
3747 mgp->num_slices = status;
3748 else
3749 goto disable_msix;
3750 }
3751
3752disable_msix:
3753 if (mgp->msix_vectors != NULL) {
3754 kfree(mgp->msix_vectors);
3755 mgp->msix_vectors = NULL;
3756 }
3757
3758abort_with_fw:
3759 mgp->num_slices = 1;
3760 mgp->fw_name = old_fw;
3761 myri10ge_load_firmware(mgp, 0);
3762}
77929732 3763
8126089f
SH		 3764static const struct net_device_ops myri10ge_netdev_ops = {
3765 .ndo_open = myri10ge_open,
3766 .ndo_stop = myri10ge_close,
3767 .ndo_start_xmit = myri10ge_xmit,
3768 .ndo_get_stats = myri10ge_get_stats,
3769 .ndo_validate_addr = eth_validate_addr,
3770 .ndo_change_mtu = myri10ge_change_mtu,
3771 .ndo_set_multicast_list = myri10ge_set_multicast_list,
3772 .ndo_set_mac_address = myri10ge_set_mac_address,
3773};
3774
0da34b6d
BG		 3775static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3776{
3777 struct net_device *netdev;
3778 struct myri10ge_priv *mgp;
3779 struct device *dev = &pdev->dev;
0da34b6d
BG		 3780 int i;
3781 int status = -ENXIO;
0da34b6d 3782 int dac_enabled;
00b5e505 3783 unsigned hdr_offset, ss_offset;
2d90b0aa 3784 static int board_number;
0da34b6d 3785
236bb5e6 3786 netdev = alloc_etherdev_mq(sizeof(*mgp), MYRI10GE_MAX_SLICES);
0da34b6d
BG		 3787 if (netdev == NULL) {
3788 dev_err(dev, "Could not allocate ethernet device\n");
3789 return -ENOMEM;
3790 }
3791
b245fb67
MH		 3792 SET_NETDEV_DEV(netdev, &pdev->dev);
3793
0da34b6d 3794 mgp = netdev_priv(netdev);
0da34b6d
BG		 3795 mgp->dev = netdev;
3796 mgp->pdev = pdev;
3797 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
3798 mgp->pause = myri10ge_flow_control;
3799 mgp->intr_coal_delay = myri10ge_intr_coal_delay;
c58ac5ca 3800 mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
2d90b0aa 3801 mgp->board_number = board_number;
0da34b6d
BG		 3802 init_waitqueue_head(&mgp->down_wq);
3803
3804 if (pci_enable_device(pdev)) {
3805 dev_err(&pdev->dev, "pci_enable_device call failed\n");
3806 status = -ENODEV;
3807 goto abort_with_netdev;
3808 }
0da34b6d
BG		 3809
3810 /* Find the vendor-specific cap so we can check
3811 * the reboot register later on */
3812 mgp->vendor_specific_offset
3813 = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
3814
3815 /* Set our max read request to 4KB */
302d242c 3816 status = pcie_set_readrq(pdev, 4096);
0da34b6d
BG		 3817 if (status != 0) {
3818 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
3819 status);
e3fd5534 3820 goto abort_with_enabled;
0da34b6d
BG		 3821 }
3822
3823 pci_set_master(pdev);
3824 dac_enabled = 1;
6a35528a 3825 status = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
0da34b6d
BG		 3826 if (status != 0) {
3827 dac_enabled = 0;
3828 dev_err(&pdev->dev,
898eb71c
JP		 3829 "64-bit pci address mask was refused, "
3830 "trying 32-bit\n");
284901a9 3831 status = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
0da34b6d
BG		 3832 }
3833 if (status != 0) {
3834 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
e3fd5534 3835 goto abort_with_enabled;
0da34b6d 3836 }
6a35528a 3837 (void)pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
b10c0668
BG		 3838 mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
3839 &mgp->cmd_bus, GFP_KERNEL);
0da34b6d 3840 if (mgp->cmd == NULL)
e3fd5534 3841 goto abort_with_enabled;
0da34b6d 3842
0da34b6d
BG		 3843 mgp->board_span = pci_resource_len(pdev, 0);
3844 mgp->iomem_base = pci_resource_start(pdev, 0);
3845 mgp->mtrr = -1;
276e26c3 3846 mgp->wc_enabled = 0;
0da34b6d
BG		 3847#ifdef CONFIG_MTRR
3848 mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
3849 MTRR_TYPE_WRCOMB, 1);
276e26c3
BG		 3850 if (mgp->mtrr >= 0)
3851 mgp->wc_enabled = 1;
0da34b6d 3852#endif
c7f80993 3853 mgp->sram = ioremap_wc(mgp->iomem_base, mgp->board_span);
0da34b6d
BG		 3854 if (mgp->sram == NULL) {
3855 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
3856 mgp->board_span, mgp->iomem_base);
3857 status = -ENXIO;
c7f80993 3858 goto abort_with_mtrr;
0da34b6d 3859 }
00b5e505
BG		 3860 hdr_offset =
3861 ntohl(__raw_readl(mgp->sram + MCP_HEADER_PTR_OFFSET)) & 0xffffc;
3862 ss_offset = hdr_offset + offsetof(struct mcp_gen_header, string_specs);
3863 mgp->sram_size = ntohl(__raw_readl(mgp->sram + ss_offset));
3864 if (mgp->sram_size > mgp->board_span ||
3865 mgp->sram_size <= MYRI10GE_FW_OFFSET) {
3866 dev_err(&pdev->dev,
3867 "invalid sram_size %dB or board span %ldB\n",
3868 mgp->sram_size, mgp->board_span);
3869 goto abort_with_ioremap;
3870 }
0da34b6d 3871 memcpy_fromio(mgp->eeprom_strings,
00b5e505 3872 mgp->sram + mgp->sram_size, MYRI10GE_EEPROM_STRINGS_SIZE);
0da34b6d
BG		 3873 memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
3874 status = myri10ge_read_mac_addr(mgp);
3875 if (status)
3876 goto abort_with_ioremap;
3877
3878 for (i = 0; i < ETH_ALEN; i++)
3879 netdev->dev_addr[i] = mgp->mac_addr[i];
3880
5443e9ea
BG		 3881 myri10ge_select_firmware(mgp);
3882
0dcffac1 3883 status = myri10ge_load_firmware(mgp, 1);
0da34b6d
BG		 3884 if (status != 0) {
3885 dev_err(&pdev->dev, "failed to load firmware\n");
0dcffac1
BG		 3886 goto abort_with_ioremap;
3887 }
3888 myri10ge_probe_slices(mgp);
3889 status = myri10ge_alloc_slices(mgp);
3890 if (status != 0) {
3891 dev_err(&pdev->dev, "failed to alloc slice state\n");
3892 goto abort_with_firmware;
0da34b6d 3893 }
236bb5e6 3894 netdev->real_num_tx_queues = mgp->num_slices;
0da34b6d
BG		 3895 status = myri10ge_reset(mgp);
3896 if (status != 0) {
3897 dev_err(&pdev->dev, "failed reset\n");
0dcffac1 3898 goto abort_with_slices;
0da34b6d 3899 }
5dd2d332 3900#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 3901 myri10ge_setup_dca(mgp);
3902#endif
0da34b6d
BG		 3903 pci_set_drvdata(pdev, mgp);
3904 if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
3905 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
3906 if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
3907 myri10ge_initial_mtu = 68;
8126089f
SH		 3908
3909 netdev->netdev_ops = &myri10ge_netdev_ops;
0da34b6d 3910 netdev->mtu = myri10ge_initial_mtu;
0da34b6d 3911 netdev->base_addr = mgp->iomem_base;
4f93fde0 3912 netdev->features = mgp->features;
236bb5e6 3913
0da34b6d
BG		 3914 if (dac_enabled)
3915 netdev->features |= NETIF_F_HIGHDMA;
2552c31b 3916 netdev->features |= NETIF_F_LRO;
0da34b6d 3917
dddc045e
BG		 3918 netdev->vlan_features |= mgp->features;
3919 if (mgp->fw_ver_tiny < 37)
3920 netdev->vlan_features &= ~NETIF_F_TSO6;
3921 if (mgp->fw_ver_tiny < 32)
3922 netdev->vlan_features &= ~NETIF_F_TSO;
3923
21d05db1
BG		 3924 /* make sure we can get an irq, and that MSI can be
3925 * setup (if available). Also ensure netdev->irq
3926 * is set to correct value if MSI is enabled */
3927 status = myri10ge_request_irq(mgp);
3928 if (status != 0)
3929 goto abort_with_firmware;
3930 netdev->irq = pdev->irq;
3931 myri10ge_free_irq(mgp);
3932
0da34b6d
BG		 3933 /* Save configuration space to be restored if the
3934 * nic resets due to a parity error */
83f6e152 3935 pci_save_state(pdev);
0da34b6d
BG		 3936
3937 /* Setup the watchdog timer */
3938 setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
3939 (unsigned long)mgp);
3940
59081825 3941 spin_lock_init(&mgp->stats_lock);
0da34b6d 3942 SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
c4028958 3943 INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
0da34b6d
BG		 3944 status = register_netdev(netdev);
3945 if (status != 0) {
3946 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
7adda30c 3947 goto abort_with_state;
0da34b6d 3948 }
0dcffac1
BG		 3949 if (mgp->msix_enabled)
3950 dev_info(dev, "%d MSI-X IRQs, tx bndry %d, fw %s, WC %s\n",
3951 mgp->num_slices, mgp->tx_boundary, mgp->fw_name,
3952 (mgp->wc_enabled ? "Enabled" : "Disabled"));
3953 else
3954 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
3955 mgp->msi_enabled ? "MSI" : "xPIC",
3956 netdev->irq, mgp->tx_boundary, mgp->fw_name,
3957 (mgp->wc_enabled ? "Enabled" : "Disabled"));
0da34b6d 3958
2d90b0aa 3959 board_number++;
0da34b6d
BG		 3960 return 0;
3961
7adda30c 3962abort_with_state:
83f6e152 3963 pci_restore_state(pdev);
0da34b6d 3964
0dcffac1
BG		 3965abort_with_slices:
3966 myri10ge_free_slices(mgp);
3967
0da34b6d
BG		 3968abort_with_firmware:
3969 myri10ge_dummy_rdma(mgp, 0);
3970
0da34b6d 3971abort_with_ioremap:
0f840011
BG		 3972 if (mgp->mac_addr_string != NULL)
3973 dev_err(&pdev->dev,
3974 "myri10ge_probe() failed: MAC=%s, SN=%ld\n",
3975 mgp->mac_addr_string, mgp->serial_number);
0da34b6d
BG		 3976 iounmap(mgp->sram);
3977
c7f80993 3978abort_with_mtrr:
0da34b6d
BG		 3979#ifdef CONFIG_MTRR
3980 if (mgp->mtrr >= 0)
3981 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3982#endif
b10c0668
BG		 3983 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3984 mgp->cmd, mgp->cmd_bus);
0da34b6d 3985
e3fd5534
BG		 3986abort_with_enabled:
3987 pci_disable_device(pdev);
0da34b6d 3988
e3fd5534 3989abort_with_netdev:
0da34b6d
BG		 3990 free_netdev(netdev);
3991 return status;
3992}
3993
3994/*
3995 * myri10ge_remove
3996 *
3997 * Does what is necessary to shutdown one Myrinet device. Called
3998 * once for each Myrinet card by the kernel when a module is
3999 * unloaded.
4000 */
4001static void myri10ge_remove(struct pci_dev *pdev)
4002{
4003 struct myri10ge_priv *mgp;
4004 struct net_device *netdev;
0da34b6d
BG		 4005
4006 mgp = pci_get_drvdata(pdev);
4007 if (mgp == NULL)
4008 return;
4009
4010 flush_scheduled_work();
4011 netdev = mgp->dev;
4012 unregister_netdev(netdev);
0da34b6d 4013
5dd2d332 4014#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 4015 myri10ge_teardown_dca(mgp);
4016#endif
0da34b6d
BG		 4017 myri10ge_dummy_rdma(mgp, 0);
4018
7adda30c 4019 /* avoid a memory leak */
83f6e152 4020 pci_restore_state(pdev);
7adda30c 4021
0da34b6d
BG		 4022 iounmap(mgp->sram);
4023
4024#ifdef CONFIG_MTRR
4025 if (mgp->mtrr >= 0)
4026 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
4027#endif
0dcffac1
BG		 4028 myri10ge_free_slices(mgp);
4029 if (mgp->msix_vectors != NULL)
4030 kfree(mgp->msix_vectors);
b10c0668
BG		 4031 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
4032 mgp->cmd, mgp->cmd_bus);
0da34b6d
BG		 4033
4034 free_netdev(netdev);
e3fd5534 4035 pci_disable_device(pdev);
0da34b6d
BG		 4036 pci_set_drvdata(pdev, NULL);
4037}
4038
b10c0668 4039#define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E 0x0008
a07bc1ff 4040#define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9 0x0009
0da34b6d
BG		 4041
4042static struct pci_device_id myri10ge_pci_tbl[] = {
b10c0668 4043 {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
a07bc1ff
BG		 4044 {PCI_DEVICE
4045 (PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9)},
0da34b6d
BG		 4046 {0},
4047};
4048
97131079
BG		 4049MODULE_DEVICE_TABLE(pci, myri10ge_pci_tbl);
4050
0da34b6d
BG		 4051static struct pci_driver myri10ge_driver = {
4052 .name = "myri10ge",
4053 .probe = myri10ge_probe,
4054 .remove = myri10ge_remove,
4055 .id_table = myri10ge_pci_tbl,
4056#ifdef CONFIG_PM
4057 .suspend = myri10ge_suspend,
4058 .resume = myri10ge_resume,
4059#endif
4060};
4061
5dd2d332 4062#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 4063static int
4064myri10ge_notify_dca(struct notifier_block *nb, unsigned long event, void *p)
4065{
4066 int err = driver_for_each_device(&myri10ge_driver.driver,
4067 NULL, &event,
4068 myri10ge_notify_dca_device);
4069
4070 if (err)
4071 return NOTIFY_BAD;
4072 return NOTIFY_DONE;
4073}
4074
4075static struct notifier_block myri10ge_dca_notifier = {
4076 .notifier_call = myri10ge_notify_dca,
4077 .next = NULL,
4078 .priority = 0,
4079};
4ee2ac51 4080#endif /* CONFIG_MYRI10GE_DCA */
981813d8 4081
0da34b6d
BG		 4082static __init int myri10ge_init_module(void)
4083{
4084 printk(KERN_INFO "%s: Version %s\n", myri10ge_driver.name,
4085 MYRI10GE_VERSION_STR);
0dcffac1 4086
236bb5e6 4087 if (myri10ge_rss_hash > MXGEFW_RSS_HASH_TYPE_MAX) {
0dcffac1
BG		 4088 printk(KERN_ERR
4089 "%s: Illegal rssh hash type %d, defaulting to source port\n",
4090 myri10ge_driver.name, myri10ge_rss_hash);
4091 myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_PORT;
4092 }
5dd2d332 4093#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 4094 dca_register_notify(&myri10ge_dca_notifier);
4095#endif
236bb5e6
BG		 4096 if (myri10ge_max_slices > MYRI10GE_MAX_SLICES)
4097 myri10ge_max_slices = MYRI10GE_MAX_SLICES;
0dcffac1 4098
0da34b6d
BG		 4099 return pci_register_driver(&myri10ge_driver);
4100}
4101
4102module_init(myri10ge_init_module);
4103
4104static __exit void myri10ge_cleanup_module(void)
4105{
5dd2d332 4106#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 4107 dca_unregister_notify(&myri10ge_dca_notifier);
4108#endif
0da34b6d
BG		 4109 pci_unregister_driver(&myri10ge_driver);
4110}
4111
4112module_exit(myri10ge_cleanup_module);
Linux 6.x block layer and io_uring tree(s)