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myri10ge: make wc_fifo usage load-time tunable
[linux-2.6-block.git] / drivers / net / myri10ge / myri10ge.c
CommitLineData
0da34b6d
BG		 1/*************************************************************************
2 * myri10ge.c: Myricom Myri-10G Ethernet driver.
3 *
4 * Copyright (C) 2005, 2006 Myricom, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of Myricom, Inc. nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 *
32 * If the eeprom on your board is not recent enough, you will need to get a
33 * newer firmware image at:
34 * http://www.myri.com/scs/download-Myri10GE.html
35 *
36 * Contact Information:
37 * <help@myri.com>
38 * Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
39 *************************************************************************/
40
41#include <linux/tcp.h>
42#include <linux/netdevice.h>
43#include <linux/skbuff.h>
44#include <linux/string.h>
45#include <linux/module.h>
46#include <linux/pci.h>
b10c0668 47#include <linux/dma-mapping.h>
0da34b6d
BG		 48#include <linux/etherdevice.h>
49#include <linux/if_ether.h>
50#include <linux/if_vlan.h>
51#include <linux/ip.h>
52#include <linux/inet.h>
53#include <linux/in.h>
54#include <linux/ethtool.h>
55#include <linux/firmware.h>
56#include <linux/delay.h>
57#include <linux/version.h>
58#include <linux/timer.h>
59#include <linux/vmalloc.h>
60#include <linux/crc32.h>
61#include <linux/moduleparam.h>
62#include <linux/io.h>
63#include <net/checksum.h>
64#include <asm/byteorder.h>
65#include <asm/io.h>
0da34b6d
BG		 66#include <asm/processor.h>
67#ifdef CONFIG_MTRR
68#include <asm/mtrr.h>
69#endif
70
71#include "myri10ge_mcp.h"
72#include "myri10ge_mcp_gen_header.h"
73
5796df19 74#define MYRI10GE_VERSION_STR "1.1.0"
0da34b6d
BG		 75
76MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
77MODULE_AUTHOR("Maintainer: help@myri.com");
78MODULE_VERSION(MYRI10GE_VERSION_STR);
79MODULE_LICENSE("Dual BSD/GPL");
80
81#define MYRI10GE_MAX_ETHER_MTU 9014
82
83#define MYRI10GE_ETH_STOPPED 0
84#define MYRI10GE_ETH_STOPPING 1
85#define MYRI10GE_ETH_STARTING 2
86#define MYRI10GE_ETH_RUNNING 3
87#define MYRI10GE_ETH_OPEN_FAILED 4
88
89#define MYRI10GE_EEPROM_STRINGS_SIZE 256
90#define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
91
40f6cff5 92#define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
0da34b6d
BG		 93#define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
94
dd50f336
BG		 95#define MYRI10GE_ALLOC_ORDER 0
96#define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE)
97#define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1)
98
0da34b6d 99struct myri10ge_rx_buffer_state {
dd50f336
BG		 100 struct page *page;
101 int page_offset;
0da34b6d
BG		 102 DECLARE_PCI_UNMAP_ADDR(bus)
103 DECLARE_PCI_UNMAP_LEN(len)
104};
105
106struct myri10ge_tx_buffer_state {
107 struct sk_buff *skb;
108 int last;
109 DECLARE_PCI_UNMAP_ADDR(bus)
110 DECLARE_PCI_UNMAP_LEN(len)
111};
112
113struct myri10ge_cmd {
114 u32 data0;
115 u32 data1;
116 u32 data2;
117};
118
119struct myri10ge_rx_buf {
120 struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */
121 u8 __iomem *wc_fifo; /* w/c rx dma addr fifo address */
122 struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */
123 struct myri10ge_rx_buffer_state *info;
dd50f336
BG		 124 struct page *page;
125 dma_addr_t bus;
126 int page_offset;
0da34b6d 127 int cnt;
dd50f336 128 int fill_cnt;
0da34b6d
BG		 129 int alloc_fail;
130 int mask; /* number of rx slots -1 */
dd50f336 131 int watchdog_needed;
0da34b6d
BG		 132};
133
134struct myri10ge_tx_buf {
135 struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */
136 u8 __iomem *wc_fifo; /* w/c send fifo address */
137 struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */
138 char *req_bytes;
139 struct myri10ge_tx_buffer_state *info;
140 int mask; /* number of transmit slots -1 */
141 int boundary; /* boundary transmits cannot cross */
142 int req ____cacheline_aligned; /* transmit slots submitted */
143 int pkt_start; /* packets started */
144 int done ____cacheline_aligned; /* transmit slots completed */
145 int pkt_done; /* packets completed */
146};
147
148struct myri10ge_rx_done {
149 struct mcp_slot *entry;
150 dma_addr_t bus;
151 int cnt;
152 int idx;
153};
154
155struct myri10ge_priv {
156 int running; /* running? */
157 int csum_flag; /* rx_csums? */
158 struct myri10ge_tx_buf tx; /* transmit ring */
159 struct myri10ge_rx_buf rx_small;
160 struct myri10ge_rx_buf rx_big;
161 struct myri10ge_rx_done rx_done;
162 int small_bytes;
dd50f336 163 int big_bytes;
0da34b6d
BG		 164 struct net_device *dev;
165 struct net_device_stats stats;
166 u8 __iomem *sram;
167 int sram_size;
168 unsigned long board_span;
169 unsigned long iomem_base;
40f6cff5
AV		 170 __be32 __iomem *irq_claim;
171 __be32 __iomem *irq_deassert;
0da34b6d
BG		 172 char *mac_addr_string;
173 struct mcp_cmd_response *cmd;
174 dma_addr_t cmd_bus;
175 struct mcp_irq_data *fw_stats;
176 dma_addr_t fw_stats_bus;
177 struct pci_dev *pdev;
178 int msi_enabled;
40f6cff5 179 __be32 link_state;
0da34b6d
BG		 180 unsigned int rdma_tags_available;
181 int intr_coal_delay;
40f6cff5 182 __be32 __iomem *intr_coal_delay_ptr;
0da34b6d
BG		 183 int mtrr;
184 int wake_queue;
185 int stop_queue;
186 int down_cnt;
187 wait_queue_head_t down_wq;
188 struct work_struct watchdog_work;
189 struct timer_list watchdog_timer;
190 int watchdog_tx_done;
c54772e7 191 int watchdog_tx_req;
0da34b6d
BG		 192 int watchdog_resets;
193 int tx_linearized;
194 int pause;
195 char *fw_name;
196 char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
197 char fw_version[128];
198 u8 mac_addr[6]; /* eeprom mac address */
199 unsigned long serial_number;
200 int vendor_specific_offset;
85a7ea1b 201 int fw_multicast_support;
0da34b6d
BG		 202 u32 read_dma;
203 u32 write_dma;
204 u32 read_write_dma;
c58ac5ca
BG		 205 u32 link_changes;
206 u32 msg_enable;
0da34b6d
BG		 207};
208
209static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
210static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
211
212static char *myri10ge_fw_name = NULL;
213module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
214MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name\n");
215
216static int myri10ge_ecrc_enable = 1;
217module_param(myri10ge_ecrc_enable, int, S_IRUGO);
218MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E\n");
219
220static int myri10ge_max_intr_slots = 1024;
221module_param(myri10ge_max_intr_slots, int, S_IRUGO);
222MODULE_PARM_DESC(myri10ge_max_intr_slots, "Interrupt queue slots\n");
223
224static int myri10ge_small_bytes = -1; /* -1 == auto */
225module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
226MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets\n");
227
228static int myri10ge_msi = 1; /* enable msi by default */
3621cec5 229module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR);
0da34b6d
BG		 230MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts\n");
231
232static int myri10ge_intr_coal_delay = 25;
233module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
234MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay\n");
235
236static int myri10ge_flow_control = 1;
237module_param(myri10ge_flow_control, int, S_IRUGO);
238MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter\n");
239
240static int myri10ge_deassert_wait = 1;
241module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
242MODULE_PARM_DESC(myri10ge_deassert_wait,
243 "Wait when deasserting legacy interrupts\n");
244
245static int myri10ge_force_firmware = 0;
246module_param(myri10ge_force_firmware, int, S_IRUGO);
247MODULE_PARM_DESC(myri10ge_force_firmware,
248 "Force firmware to assume aligned completions\n");
249
0da34b6d
BG		 250static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
251module_param(myri10ge_initial_mtu, int, S_IRUGO);
252MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU\n");
253
254static int myri10ge_napi_weight = 64;
255module_param(myri10ge_napi_weight, int, S_IRUGO);
256MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight\n");
257
258static int myri10ge_watchdog_timeout = 1;
259module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
260MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout\n");
261
262static int myri10ge_max_irq_loops = 1048576;
263module_param(myri10ge_max_irq_loops, int, S_IRUGO);
264MODULE_PARM_DESC(myri10ge_max_irq_loops,
265 "Set stuck legacy IRQ detection threshold\n");
266
c58ac5ca
BG		 267#define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
268
269static int myri10ge_debug = -1; /* defaults above */
270module_param(myri10ge_debug, int, 0);
271MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
272
dd50f336
BG		 273static int myri10ge_fill_thresh = 256;
274module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
275MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed\n");
276
6ebc087a
BG		 277static int myri10ge_wcfifo = 1;
278module_param(myri10ge_wcfifo, int, S_IRUGO);
279MODULE_PARM_DESC(myri10ge_wcfifo, "Enable WC Fifo when WC is enabled\n");
280
0da34b6d
BG		 281#define MYRI10GE_FW_OFFSET 1024*1024
282#define MYRI10GE_HIGHPART_TO_U32(X) \
283(sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
284#define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
285
286#define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
287
6250223e 288static inline void put_be32(__be32 val, __be32 __iomem * p)
40f6cff5 289{
6250223e 290 __raw_writel((__force __u32) val, (__force void __iomem *)p);
40f6cff5
AV		 291}
292
0da34b6d
BG		 293static int
294myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
295 struct myri10ge_cmd *data, int atomic)
296{
297 struct mcp_cmd *buf;
298 char buf_bytes[sizeof(*buf) + 8];
299 struct mcp_cmd_response *response = mgp->cmd;
e700f9f4 300 char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
0da34b6d
BG		 301 u32 dma_low, dma_high, result, value;
302 int sleep_total = 0;
303
304 /* ensure buf is aligned to 8 bytes */
305 buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
306
307 buf->data0 = htonl(data->data0);
308 buf->data1 = htonl(data->data1);
309 buf->data2 = htonl(data->data2);
310 buf->cmd = htonl(cmd);
311 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
312 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
313
314 buf->response_addr.low = htonl(dma_low);
315 buf->response_addr.high = htonl(dma_high);
40f6cff5 316 response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 317 mb();
318 myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
319
320 /* wait up to 15ms. Longest command is the DMA benchmark,
321 * which is capped at 5ms, but runs from a timeout handler
322 * that runs every 7.8ms. So a 15ms timeout leaves us with
323 * a 2.2ms margin
324 */
325 if (atomic) {
326 /* if atomic is set, do not sleep,
327 * and try to get the completion quickly
328 * (1ms will be enough for those commands) */
329 for (sleep_total = 0;
330 sleep_total < 1000
40f6cff5 331 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 332 sleep_total += 10)
333 udelay(10);
334 } else {
335 /* use msleep for most command */
336 for (sleep_total = 0;
337 sleep_total < 15
40f6cff5 338 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 339 sleep_total++)
340 msleep(1);
341 }
342
343 result = ntohl(response->result);
344 value = ntohl(response->data);
345 if (result != MYRI10GE_NO_RESPONSE_RESULT) {
346 if (result == 0) {
347 data->data0 = value;
348 return 0;
85a7ea1b
BG		 349 } else if (result == MXGEFW_CMD_UNKNOWN) {
350 return -ENOSYS;
0da34b6d
BG		 351 } else {
352 dev_err(&mgp->pdev->dev,
353 "command %d failed, result = %d\n",
354 cmd, result);
355 return -ENXIO;
356 }
357 }
358
359 dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
360 cmd, result);
361 return -EAGAIN;
362}
363
364/*
365 * The eeprom strings on the lanaiX have the format
366 * SN=x\0
367 * MAC=x:x:x:x:x:x\0
368 * PT:ddd mmm xx xx:xx:xx xx\0
369 * PV:ddd mmm xx xx:xx:xx xx\0
370 */
371static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
372{
373 char *ptr, *limit;
374 int i;
375
376 ptr = mgp->eeprom_strings;
377 limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
378
379 while (*ptr != '\0' && ptr < limit) {
380 if (memcmp(ptr, "MAC=", 4) == 0) {
381 ptr += 4;
382 mgp->mac_addr_string = ptr;
383 for (i = 0; i < 6; i++) {
384 if ((ptr + 2) > limit)
385 goto abort;
386 mgp->mac_addr[i] =
387 simple_strtoul(ptr, &ptr, 16);
388 ptr += 1;
389 }
390 }
391 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
392 ptr += 3;
393 mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
394 }
395 while (ptr < limit && *ptr++) ;
396 }
397
398 return 0;
399
400abort:
401 dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
402 return -ENXIO;
403}
404
405/*
406 * Enable or disable periodic RDMAs from the host to make certain
407 * chipsets resend dropped PCIe messages
408 */
409
410static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
411{
412 char __iomem *submit;
40f6cff5 413 __be32 buf[16];
0da34b6d
BG		 414 u32 dma_low, dma_high;
415 int i;
416
417 /* clear confirmation addr */
418 mgp->cmd->data = 0;
419 mb();
420
421 /* send a rdma command to the PCIe engine, and wait for the
422 * response in the confirmation address. The firmware should
423 * write a -1 there to indicate it is alive and well
424 */
425 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
426 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
427
428 buf[0] = htonl(dma_high); /* confirm addr MSW */
429 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 430 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 431 buf[3] = htonl(dma_high); /* dummy addr MSW */
432 buf[4] = htonl(dma_low); /* dummy addr LSW */
433 buf[5] = htonl(enable); /* enable? */
434
e700f9f4 435 submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
0da34b6d
BG		 436
437 myri10ge_pio_copy(submit, &buf, sizeof(buf));
438 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
439 msleep(1);
440 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
441 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
442 (enable ? "enable" : "disable"));
443}
444
445static int
446myri10ge_validate_firmware(struct myri10ge_priv *mgp,
447 struct mcp_gen_header *hdr)
448{
449 struct device *dev = &mgp->pdev->dev;
450 int major, minor;
451
452 /* check firmware type */
453 if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
454 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
455 return -EINVAL;
456 }
457
458 /* save firmware version for ethtool */
459 strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
460
461 sscanf(mgp->fw_version, "%d.%d", &major, &minor);
462
463 if (!(major == MXGEFW_VERSION_MAJOR && minor == MXGEFW_VERSION_MINOR)) {
464 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
465 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
466 MXGEFW_VERSION_MINOR);
467 return -EINVAL;
468 }
469 return 0;
470}
471
472static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
473{
474 unsigned crc, reread_crc;
475 const struct firmware *fw;
476 struct device *dev = &mgp->pdev->dev;
477 struct mcp_gen_header *hdr;
478 size_t hdr_offset;
479 int status;
e454358a 480 unsigned i;
0da34b6d
BG		 481
482 if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
483 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
484 mgp->fw_name);
485 status = -EINVAL;
486 goto abort_with_nothing;
487 }
488
489 /* check size */
490
491 if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
492 fw->size < MCP_HEADER_PTR_OFFSET + 4) {
493 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
494 status = -EINVAL;
495 goto abort_with_fw;
496 }
497
498 /* check id */
40f6cff5 499 hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
0da34b6d
BG		 500 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
501 dev_err(dev, "Bad firmware file\n");
502 status = -EINVAL;
503 goto abort_with_fw;
504 }
505 hdr = (void *)(fw->data + hdr_offset);
506
507 status = myri10ge_validate_firmware(mgp, hdr);
508 if (status != 0)
509 goto abort_with_fw;
510
511 crc = crc32(~0, fw->data, fw->size);
e454358a
BG		 512 for (i = 0; i < fw->size; i += 256) {
513 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
514 fw->data + i,
515 min(256U, (unsigned)(fw->size - i)));
516 mb();
517 readb(mgp->sram);
b10c0668 518 }
0da34b6d
BG		 519 /* corruption checking is good for parity recovery and buggy chipset */
520 memcpy_fromio(fw->data, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
521 reread_crc = crc32(~0, fw->data, fw->size);
522 if (crc != reread_crc) {
523 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
524 (unsigned)fw->size, reread_crc, crc);
525 status = -EIO;
526 goto abort_with_fw;
527 }
528 *size = (u32) fw->size;
529
530abort_with_fw:
531 release_firmware(fw);
532
533abort_with_nothing:
534 return status;
535}
536
537static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
538{
539 struct mcp_gen_header *hdr;
540 struct device *dev = &mgp->pdev->dev;
541 const size_t bytes = sizeof(struct mcp_gen_header);
542 size_t hdr_offset;
543 int status;
544
545 /* find running firmware header */
546 hdr_offset = ntohl(__raw_readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
547
548 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
549 dev_err(dev, "Running firmware has bad header offset (%d)\n",
550 (int)hdr_offset);
551 return -EIO;
552 }
553
554 /* copy header of running firmware from SRAM to host memory to
555 * validate firmware */
556 hdr = kmalloc(bytes, GFP_KERNEL);
557 if (hdr == NULL) {
558 dev_err(dev, "could not malloc firmware hdr\n");
559 return -ENOMEM;
560 }
561 memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
562 status = myri10ge_validate_firmware(mgp, hdr);
563 kfree(hdr);
564 return status;
565}
566
567static int myri10ge_load_firmware(struct myri10ge_priv *mgp)
568{
569 char __iomem *submit;
40f6cff5 570 __be32 buf[16];
0da34b6d
BG		 571 u32 dma_low, dma_high, size;
572 int status, i;
573
b10c0668 574 size = 0;
0da34b6d
BG		 575 status = myri10ge_load_hotplug_firmware(mgp, &size);
576 if (status) {
577 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
578
579 /* Do not attempt to adopt firmware if there
580 * was a bad crc */
581 if (status == -EIO)
582 return status;
583
584 status = myri10ge_adopt_running_firmware(mgp);
585 if (status != 0) {
586 dev_err(&mgp->pdev->dev,
587 "failed to adopt running firmware\n");
588 return status;
589 }
590 dev_info(&mgp->pdev->dev,
591 "Successfully adopted running firmware\n");
592 if (mgp->tx.boundary == 4096) {
593 dev_warn(&mgp->pdev->dev,
594 "Using firmware currently running on NIC"
595 ". For optimal\n");
596 dev_warn(&mgp->pdev->dev,
597 "performance consider loading optimized "
598 "firmware\n");
599 dev_warn(&mgp->pdev->dev, "via hotplug\n");
600 }
601
602 mgp->fw_name = "adopted";
603 mgp->tx.boundary = 2048;
604 return status;
605 }
606
607 /* clear confirmation addr */
608 mgp->cmd->data = 0;
609 mb();
610
611 /* send a reload command to the bootstrap MCP, and wait for the
612 * response in the confirmation address. The firmware should
613 * write a -1 there to indicate it is alive and well
614 */
615 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
616 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
617
618 buf[0] = htonl(dma_high); /* confirm addr MSW */
619 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 620 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 621
622 /* FIX: All newest firmware should un-protect the bottom of
623 * the sram before handoff. However, the very first interfaces
624 * do not. Therefore the handoff copy must skip the first 8 bytes
625 */
626 buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
627 buf[4] = htonl(size - 8); /* length of code */
628 buf[5] = htonl(8); /* where to copy to */
629 buf[6] = htonl(0); /* where to jump to */
630
e700f9f4 631 submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
0da34b6d
BG		 632
633 myri10ge_pio_copy(submit, &buf, sizeof(buf));
634 mb();
635 msleep(1);
636 mb();
637 i = 0;
638 while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20) {
639 msleep(1);
640 i++;
641 }
642 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
643 dev_err(&mgp->pdev->dev, "handoff failed\n");
644 return -ENXIO;
645 }
646 dev_info(&mgp->pdev->dev, "handoff confirmed\n");
9a71db72 647 myri10ge_dummy_rdma(mgp, 1);
0da34b6d
BG		 648
649 return 0;
650}
651
652static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
653{
654 struct myri10ge_cmd cmd;
655 int status;
656
657 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
658 | (addr[2] << 8) | addr[3]);
659
660 cmd.data1 = ((addr[4] << 8) | (addr[5]));
661
662 status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
663 return status;
664}
665
666static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
667{
668 struct myri10ge_cmd cmd;
669 int status, ctl;
670
671 ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
672 status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
673
674 if (status) {
675 printk(KERN_ERR
676 "myri10ge: %s: Failed to set flow control mode\n",
677 mgp->dev->name);
678 return status;
679 }
680 mgp->pause = pause;
681 return 0;
682}
683
684static void
685myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
686{
687 struct myri10ge_cmd cmd;
688 int status, ctl;
689
690 ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
691 status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
692 if (status)
693 printk(KERN_ERR "myri10ge: %s: Failed to set promisc mode\n",
694 mgp->dev->name);
695}
696
697static int myri10ge_reset(struct myri10ge_priv *mgp)
698{
699 struct myri10ge_cmd cmd;
700 int status;
701 size_t bytes;
702 u32 len;
703
704 /* try to send a reset command to the card to see if it
705 * is alive */
706 memset(&cmd, 0, sizeof(cmd));
707 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
708 if (status != 0) {
709 dev_err(&mgp->pdev->dev, "failed reset\n");
710 return -ENXIO;
711 }
712
713 /* Now exchange information about interrupts */
714
715 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
716 memset(mgp->rx_done.entry, 0, bytes);
717 cmd.data0 = (u32) bytes;
718 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
719 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
720 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
721 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA, &cmd, 0);
722
723 status |=
724 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
40f6cff5 725 mgp->irq_claim = (__iomem __be32 *) (mgp->sram + cmd.data0);
df30a740
BG		 726 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
727 &cmd, 0);
728 mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d 729
0da34b6d
BG		 730 status |= myri10ge_send_cmd
731 (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
40f6cff5 732 mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d
BG		 733 if (status != 0) {
734 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
735 return status;
736 }
40f6cff5 737 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d
BG		 738
739 /* Run a small DMA test.
740 * The magic multipliers to the length tell the firmware
741 * to do DMA read, write, or read+write tests. The
742 * results are returned in cmd.data0. The upper 16
743 * bits or the return is the number of transfers completed.
744 * The lower 16 bits is the time in 0.5us ticks that the
745 * transfers took to complete.
746 */
747
748 len = mgp->tx.boundary;
749
750 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
751 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
752 cmd.data2 = len * 0x10000;
753 status = myri10ge_send_cmd(mgp, MXGEFW_DMA_TEST, &cmd, 0);
754 if (status == 0)
755 mgp->read_dma = ((cmd.data0 >> 16) * len * 2) /
756 (cmd.data0 & 0xffff);
757 else
758 dev_warn(&mgp->pdev->dev, "DMA read benchmark failed: %d\n",
759 status);
760 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
761 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
762 cmd.data2 = len * 0x1;
763 status = myri10ge_send_cmd(mgp, MXGEFW_DMA_TEST, &cmd, 0);
764 if (status == 0)
765 mgp->write_dma = ((cmd.data0 >> 16) * len * 2) /
766 (cmd.data0 & 0xffff);
767 else
768 dev_warn(&mgp->pdev->dev, "DMA write benchmark failed: %d\n",
769 status);
770
771 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
772 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
773 cmd.data2 = len * 0x10001;
774 status = myri10ge_send_cmd(mgp, MXGEFW_DMA_TEST, &cmd, 0);
775 if (status == 0)
776 mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
777 (cmd.data0 & 0xffff);
778 else
779 dev_warn(&mgp->pdev->dev,
780 "DMA read/write benchmark failed: %d\n", status);
781
782 memset(mgp->rx_done.entry, 0, bytes);
783
784 /* reset mcp/driver shared state back to 0 */
785 mgp->tx.req = 0;
786 mgp->tx.done = 0;
787 mgp->tx.pkt_start = 0;
788 mgp->tx.pkt_done = 0;
789 mgp->rx_big.cnt = 0;
790 mgp->rx_small.cnt = 0;
791 mgp->rx_done.idx = 0;
792 mgp->rx_done.cnt = 0;
c58ac5ca 793 mgp->link_changes = 0;
0da34b6d
BG		 794 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
795 myri10ge_change_promisc(mgp, 0, 0);
796 myri10ge_change_pause(mgp, mgp->pause);
797 return status;
798}
799
800static inline void
801myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
802 struct mcp_kreq_ether_recv *src)
803{
40f6cff5 804 __be32 low;
0da34b6d
BG		 805
806 low = src->addr_low;
40f6cff5 807 src->addr_low = htonl(DMA_32BIT_MASK);
e67bda55
BG		 808 myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
809 mb();
810 myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
0da34b6d
BG		 811 mb();
812 src->addr_low = low;
40f6cff5 813 put_be32(low, &dst->addr_low);
0da34b6d
BG		 814 mb();
815}
816
40f6cff5 817static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
0da34b6d
BG		 818{
819 struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
820
40f6cff5 821 if ((skb->protocol == htons(ETH_P_8021Q)) &&
0da34b6d
BG		 822 (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
823 vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
824 skb->csum = hw_csum;
84fa7933 825 skb->ip_summed = CHECKSUM_COMPLETE;
0da34b6d
BG		 826 }
827}
828
dd50f336
BG		 829static inline void
830myri10ge_rx_skb_build(struct sk_buff *skb, u8 * va,
831 struct skb_frag_struct *rx_frags, int len, int hlen)
832{
833 struct skb_frag_struct *skb_frags;
834
835 skb->len = skb->data_len = len;
836 skb->truesize = len + sizeof(struct sk_buff);
837 /* attach the page(s) */
838
839 skb_frags = skb_shinfo(skb)->frags;
840 while (len > 0) {
841 memcpy(skb_frags, rx_frags, sizeof(*skb_frags));
842 len -= rx_frags->size;
843 skb_frags++;
844 rx_frags++;
845 skb_shinfo(skb)->nr_frags++;
846 }
847
848 /* pskb_may_pull is not available in irq context, but
849 * skb_pull() (for ether_pad and eth_type_trans()) requires
850 * the beginning of the packet in skb_headlen(), move it
851 * manually */
852 memcpy(skb->data, va, hlen);
853 skb_shinfo(skb)->frags[0].page_offset += hlen;
854 skb_shinfo(skb)->frags[0].size -= hlen;
855 skb->data_len -= hlen;
856 skb->tail += hlen;
857 skb_pull(skb, MXGEFW_PAD);
858}
859
860static void
861myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
862 int bytes, int watchdog)
863{
864 struct page *page;
865 int idx;
866
867 if (unlikely(rx->watchdog_needed && !watchdog))
868 return;
869
870 /* try to refill entire ring */
871 while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) {
872 idx = rx->fill_cnt & rx->mask;
873
874 if ((bytes < MYRI10GE_ALLOC_SIZE / 2) &&
875 (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE)) {
876 /* we can use part of previous page */
877 get_page(rx->page);
878 } else {
879 /* we need a new page */
880 page =
881 alloc_pages(GFP_ATOMIC | __GFP_COMP,
882 MYRI10GE_ALLOC_ORDER);
883 if (unlikely(page == NULL)) {
884 if (rx->fill_cnt - rx->cnt < 16)
885 rx->watchdog_needed = 1;
886 return;
887 }
888 rx->page = page;
889 rx->page_offset = 0;
890 rx->bus = pci_map_page(mgp->pdev, page, 0,
891 MYRI10GE_ALLOC_SIZE,
892 PCI_DMA_FROMDEVICE);
893 }
894 rx->info[idx].page = rx->page;
895 rx->info[idx].page_offset = rx->page_offset;
896 /* note that this is the address of the start of the
897 * page */
898 pci_unmap_addr_set(&rx->info[idx], bus, rx->bus);
899 rx->shadow[idx].addr_low =
900 htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset);
901 rx->shadow[idx].addr_high =
902 htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus));
903
904 /* start next packet on a cacheline boundary */
905 rx->page_offset += SKB_DATA_ALIGN(bytes);
906 rx->fill_cnt++;
907
908 /* copy 8 descriptors to the firmware at a time */
909 if ((idx & 7) == 7) {
910 if (rx->wc_fifo == NULL)
911 myri10ge_submit_8rx(&rx->lanai[idx - 7],
912 &rx->shadow[idx - 7]);
913 else {
914 mb();
915 myri10ge_pio_copy(rx->wc_fifo,
916 &rx->shadow[idx - 7], 64);
917 }
918 }
919 }
920}
921
922static inline void
923myri10ge_unmap_rx_page(struct pci_dev *pdev,
924 struct myri10ge_rx_buffer_state *info, int bytes)
925{
926 /* unmap the recvd page if we're the only or last user of it */
927 if (bytes >= MYRI10GE_ALLOC_SIZE / 2 ||
928 (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) {
929 pci_unmap_page(pdev, (pci_unmap_addr(info, bus)
930 & ~(MYRI10GE_ALLOC_SIZE - 1)),
931 MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
932 }
933}
934
935#define MYRI10GE_HLEN 64 /* The number of bytes to copy from a
936 * page into an skb */
937
938static inline int
52ea6fb3
BG		 939myri10ge_rx_done(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
940 int bytes, int len, __wsum csum)
dd50f336
BG		 941{
942 struct sk_buff *skb;
943 struct skb_frag_struct rx_frags[MYRI10GE_MAX_FRAGS_PER_FRAME];
944 int i, idx, hlen, remainder;
945 struct pci_dev *pdev = mgp->pdev;
946 struct net_device *dev = mgp->dev;
947 u8 *va;
948
949 len += MXGEFW_PAD;
950 idx = rx->cnt & rx->mask;
951 va = page_address(rx->info[idx].page) + rx->info[idx].page_offset;
952 prefetch(va);
953 /* Fill skb_frag_struct(s) with data from our receive */
954 for (i = 0, remainder = len; remainder > 0; i++) {
955 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
956 rx_frags[i].page = rx->info[idx].page;
957 rx_frags[i].page_offset = rx->info[idx].page_offset;
958 if (remainder < MYRI10GE_ALLOC_SIZE)
959 rx_frags[i].size = remainder;
960 else
961 rx_frags[i].size = MYRI10GE_ALLOC_SIZE;
962 rx->cnt++;
963 idx = rx->cnt & rx->mask;
964 remainder -= MYRI10GE_ALLOC_SIZE;
965 }
966
967 hlen = MYRI10GE_HLEN > len ? len : MYRI10GE_HLEN;
968
969 /* allocate an skb to attach the page(s) to. */
970
971 skb = netdev_alloc_skb(dev, MYRI10GE_HLEN + 16);
972 if (unlikely(skb == NULL)) {
973 mgp->stats.rx_dropped++;
974 do {
975 i--;
976 put_page(rx_frags[i].page);
977 } while (i != 0);
978 return 0;
979 }
980
981 /* Attach the pages to the skb, and trim off any padding */
982 myri10ge_rx_skb_build(skb, va, rx_frags, len, hlen);
983 if (skb_shinfo(skb)->frags[0].size <= 0) {
984 put_page(skb_shinfo(skb)->frags[0].page);
985 skb_shinfo(skb)->nr_frags = 0;
986 }
987 skb->protocol = eth_type_trans(skb, dev);
988 skb->dev = dev;
989
990 if (mgp->csum_flag) {
991 if ((skb->protocol == htons(ETH_P_IP)) ||
992 (skb->protocol == htons(ETH_P_IPV6))) {
993 skb->csum = csum;
994 skb->ip_summed = CHECKSUM_COMPLETE;
995 } else
996 myri10ge_vlan_ip_csum(skb, csum);
997 }
998 netif_receive_skb(skb);
999 dev->last_rx = jiffies;
1000 return 1;
1001}
1002
0da34b6d
BG		 1003static inline void myri10ge_tx_done(struct myri10ge_priv *mgp, int mcp_index)
1004{
1005 struct pci_dev *pdev = mgp->pdev;
1006 struct myri10ge_tx_buf *tx = &mgp->tx;
1007 struct sk_buff *skb;
1008 int idx, len;
1009 int limit = 0;
1010
1011 while (tx->pkt_done != mcp_index) {
1012 idx = tx->done & tx->mask;
1013 skb = tx->info[idx].skb;
1014
1015 /* Mark as free */
1016 tx->info[idx].skb = NULL;
1017 if (tx->info[idx].last) {
1018 tx->pkt_done++;
1019 tx->info[idx].last = 0;
1020 }
1021 tx->done++;
1022 len = pci_unmap_len(&tx->info[idx], len);
1023 pci_unmap_len_set(&tx->info[idx], len, 0);
1024 if (skb) {
1025 mgp->stats.tx_bytes += skb->len;
1026 mgp->stats.tx_packets++;
1027 dev_kfree_skb_irq(skb);
1028 if (len)
1029 pci_unmap_single(pdev,
1030 pci_unmap_addr(&tx->info[idx],
1031 bus), len,
1032 PCI_DMA_TODEVICE);
1033 } else {
1034 if (len)
1035 pci_unmap_page(pdev,
1036 pci_unmap_addr(&tx->info[idx],
1037 bus), len,
1038 PCI_DMA_TODEVICE);
1039 }
1040
1041 /* limit potential for livelock by only handling
1042 * 2 full tx rings per call */
1043 if (unlikely(++limit > 2 * tx->mask))
1044 break;
1045 }
1046 /* start the queue if we've stopped it */
1047 if (netif_queue_stopped(mgp->dev)
1048 && tx->req - tx->done < (tx->mask >> 1)) {
1049 mgp->wake_queue++;
1050 netif_wake_queue(mgp->dev);
1051 }
1052}
1053
1054static inline void myri10ge_clean_rx_done(struct myri10ge_priv *mgp, int *limit)
1055{
1056 struct myri10ge_rx_done *rx_done = &mgp->rx_done;
1057 unsigned long rx_bytes = 0;
1058 unsigned long rx_packets = 0;
1059 unsigned long rx_ok;
1060
1061 int idx = rx_done->idx;
1062 int cnt = rx_done->cnt;
1063 u16 length;
40f6cff5 1064 __wsum checksum;
0da34b6d
BG		 1065
1066 while (rx_done->entry[idx].length != 0 && *limit != 0) {
1067 length = ntohs(rx_done->entry[idx].length);
1068 rx_done->entry[idx].length = 0;
40f6cff5 1069 checksum = csum_unfold(rx_done->entry[idx].checksum);
0da34b6d 1070 if (length <= mgp->small_bytes)
52ea6fb3
BG		 1071 rx_ok = myri10ge_rx_done(mgp, &mgp->rx_small,
1072 mgp->small_bytes,
1073 length, checksum);
0da34b6d 1074 else
52ea6fb3
BG		 1075 rx_ok = myri10ge_rx_done(mgp, &mgp->rx_big,
1076 mgp->big_bytes,
1077 length, checksum);
0da34b6d
BG		 1078 rx_packets += rx_ok;
1079 rx_bytes += rx_ok * (unsigned long)length;
1080 cnt++;
1081 idx = cnt & (myri10ge_max_intr_slots - 1);
1082
1083 /* limit potential for livelock by only handling a
1084 * limited number of frames. */
1085 (*limit)--;
1086 }
1087 rx_done->idx = idx;
1088 rx_done->cnt = cnt;
1089 mgp->stats.rx_packets += rx_packets;
1090 mgp->stats.rx_bytes += rx_bytes;
c7dab99b
BG		 1091
1092 /* restock receive rings if needed */
1093 if (mgp->rx_small.fill_cnt - mgp->rx_small.cnt < myri10ge_fill_thresh)
1094 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
1095 mgp->small_bytes + MXGEFW_PAD, 0);
1096 if (mgp->rx_big.fill_cnt - mgp->rx_big.cnt < myri10ge_fill_thresh)
1097 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 0);
1098
0da34b6d
BG		 1099}
1100
1101static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1102{
1103 struct mcp_irq_data *stats = mgp->fw_stats;
1104
1105 if (unlikely(stats->stats_updated)) {
1106 if (mgp->link_state != stats->link_up) {
1107 mgp->link_state = stats->link_up;
1108 if (mgp->link_state) {
c58ac5ca
BG		 1109 if (netif_msg_link(mgp))
1110 printk(KERN_INFO
1111 "myri10ge: %s: link up\n",
1112 mgp->dev->name);
0da34b6d 1113 netif_carrier_on(mgp->dev);
c58ac5ca 1114 mgp->link_changes++;
0da34b6d 1115 } else {
c58ac5ca
BG		 1116 if (netif_msg_link(mgp))
1117 printk(KERN_INFO
1118 "myri10ge: %s: link down\n",
1119 mgp->dev->name);
0da34b6d 1120 netif_carrier_off(mgp->dev);
c58ac5ca 1121 mgp->link_changes++;
0da34b6d
BG		 1122 }
1123 }
1124 if (mgp->rdma_tags_available !=
1125 ntohl(mgp->fw_stats->rdma_tags_available)) {
1126 mgp->rdma_tags_available =
1127 ntohl(mgp->fw_stats->rdma_tags_available);
1128 printk(KERN_WARNING "myri10ge: %s: RDMA timed out! "
1129 "%d tags left\n", mgp->dev->name,
1130 mgp->rdma_tags_available);
1131 }
1132 mgp->down_cnt += stats->link_down;
1133 if (stats->link_down)
1134 wake_up(&mgp->down_wq);
1135 }
1136}
1137
1138static int myri10ge_poll(struct net_device *netdev, int *budget)
1139{
1140 struct myri10ge_priv *mgp = netdev_priv(netdev);
1141 struct myri10ge_rx_done *rx_done = &mgp->rx_done;
1142 int limit, orig_limit, work_done;
1143
1144 /* process as many rx events as NAPI will allow */
1145 limit = min(*budget, netdev->quota);
1146 orig_limit = limit;
1147 myri10ge_clean_rx_done(mgp, &limit);
1148 work_done = orig_limit - limit;
1149 *budget -= work_done;
1150 netdev->quota -= work_done;
1151
1152 if (rx_done->entry[rx_done->idx].length == 0 || !netif_running(netdev)) {
1153 netif_rx_complete(netdev);
40f6cff5 1154 put_be32(htonl(3), mgp->irq_claim);
0da34b6d
BG		 1155 return 0;
1156 }
1157 return 1;
1158}
1159
7d12e780 1160static irqreturn_t myri10ge_intr(int irq, void *arg)
0da34b6d
BG		 1161{
1162 struct myri10ge_priv *mgp = arg;
1163 struct mcp_irq_data *stats = mgp->fw_stats;
1164 struct myri10ge_tx_buf *tx = &mgp->tx;
1165 u32 send_done_count;
1166 int i;
1167
1168 /* make sure it is our IRQ, and that the DMA has finished */
1169 if (unlikely(!stats->valid))
1170 return (IRQ_NONE);
1171
1172 /* low bit indicates receives are present, so schedule
1173 * napi poll handler */
1174 if (stats->valid & 1)
1175 netif_rx_schedule(mgp->dev);
1176
1177 if (!mgp->msi_enabled) {
40f6cff5 1178 put_be32(0, mgp->irq_deassert);
0da34b6d
BG		 1179 if (!myri10ge_deassert_wait)
1180 stats->valid = 0;
1181 mb();
1182 } else
1183 stats->valid = 0;
1184
1185 /* Wait for IRQ line to go low, if using INTx */
1186 i = 0;
1187 while (1) {
1188 i++;
1189 /* check for transmit completes and receives */
1190 send_done_count = ntohl(stats->send_done_count);
1191 if (send_done_count != tx->pkt_done)
1192 myri10ge_tx_done(mgp, (int)send_done_count);
1193 if (unlikely(i > myri10ge_max_irq_loops)) {
1194 printk(KERN_WARNING "myri10ge: %s: irq stuck?\n",
1195 mgp->dev->name);
1196 stats->valid = 0;
1197 schedule_work(&mgp->watchdog_work);
1198 }
1199 if (likely(stats->valid == 0))
1200 break;
1201 cpu_relax();
1202 barrier();
1203 }
1204
1205 myri10ge_check_statblock(mgp);
1206
40f6cff5 1207 put_be32(htonl(3), mgp->irq_claim + 1);
0da34b6d
BG		 1208 return (IRQ_HANDLED);
1209}
1210
1211static int
1212myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1213{
1214 cmd->autoneg = AUTONEG_DISABLE;
1215 cmd->speed = SPEED_10000;
1216 cmd->duplex = DUPLEX_FULL;
1217 return 0;
1218}
1219
1220static void
1221myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1222{
1223 struct myri10ge_priv *mgp = netdev_priv(netdev);
1224
1225 strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1226 strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1227 strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1228 strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1229}
1230
1231static int
1232myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1233{
1234 struct myri10ge_priv *mgp = netdev_priv(netdev);
1235 coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1236 return 0;
1237}
1238
1239static int
1240myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1241{
1242 struct myri10ge_priv *mgp = netdev_priv(netdev);
1243
1244 mgp->intr_coal_delay = coal->rx_coalesce_usecs;
40f6cff5 1245 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d
BG		 1246 return 0;
1247}
1248
1249static void
1250myri10ge_get_pauseparam(struct net_device *netdev,
1251 struct ethtool_pauseparam *pause)
1252{
1253 struct myri10ge_priv *mgp = netdev_priv(netdev);
1254
1255 pause->autoneg = 0;
1256 pause->rx_pause = mgp->pause;
1257 pause->tx_pause = mgp->pause;
1258}
1259
1260static int
1261myri10ge_set_pauseparam(struct net_device *netdev,
1262 struct ethtool_pauseparam *pause)
1263{
1264 struct myri10ge_priv *mgp = netdev_priv(netdev);
1265
1266 if (pause->tx_pause != mgp->pause)
1267 return myri10ge_change_pause(mgp, pause->tx_pause);
1268 if (pause->rx_pause != mgp->pause)
1269 return myri10ge_change_pause(mgp, pause->tx_pause);
1270 if (pause->autoneg != 0)
1271 return -EINVAL;
1272 return 0;
1273}
1274
1275static void
1276myri10ge_get_ringparam(struct net_device *netdev,
1277 struct ethtool_ringparam *ring)
1278{
1279 struct myri10ge_priv *mgp = netdev_priv(netdev);
1280
1281 ring->rx_mini_max_pending = mgp->rx_small.mask + 1;
1282 ring->rx_max_pending = mgp->rx_big.mask + 1;
1283 ring->rx_jumbo_max_pending = 0;
1284 ring->tx_max_pending = mgp->rx_small.mask + 1;
1285 ring->rx_mini_pending = ring->rx_mini_max_pending;
1286 ring->rx_pending = ring->rx_max_pending;
1287 ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1288 ring->tx_pending = ring->tx_max_pending;
1289}
1290
1291static u32 myri10ge_get_rx_csum(struct net_device *netdev)
1292{
1293 struct myri10ge_priv *mgp = netdev_priv(netdev);
1294 if (mgp->csum_flag)
1295 return 1;
1296 else
1297 return 0;
1298}
1299
1300static int myri10ge_set_rx_csum(struct net_device *netdev, u32 csum_enabled)
1301{
1302 struct myri10ge_priv *mgp = netdev_priv(netdev);
1303 if (csum_enabled)
1304 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
1305 else
1306 mgp->csum_flag = 0;
1307 return 0;
1308}
1309
1310static const char myri10ge_gstrings_stats[][ETH_GSTRING_LEN] = {
1311 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1312 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1313 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1314 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1315 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1316 "tx_heartbeat_errors", "tx_window_errors",
1317 /* device-specific stats */
2c1a1088 1318 "tx_boundary", "WC", "irq", "MSI",
0da34b6d
BG		 1319 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
1320 "serial_number", "tx_pkt_start", "tx_pkt_done",
1321 "tx_req", "tx_done", "rx_small_cnt", "rx_big_cnt",
1322 "wake_queue", "stop_queue", "watchdog_resets", "tx_linearized",
c58ac5ca 1323 "link_changes", "link_up", "dropped_link_overflow",
85a7ea1b 1324 "dropped_link_error_or_filtered", "dropped_multicast_filtered",
0da34b6d
BG		 1325 "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
1326 "dropped_no_big_buffer"
1327};
1328
1329#define MYRI10GE_NET_STATS_LEN 21
1330#define MYRI10GE_STATS_LEN sizeof(myri10ge_gstrings_stats) / ETH_GSTRING_LEN
1331
1332static void
1333myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1334{
1335 switch (stringset) {
1336 case ETH_SS_STATS:
1337 memcpy(data, *myri10ge_gstrings_stats,
1338 sizeof(myri10ge_gstrings_stats));
1339 break;
1340 }
1341}
1342
1343static int myri10ge_get_stats_count(struct net_device *netdev)
1344{
1345 return MYRI10GE_STATS_LEN;
1346}
1347
1348static void
1349myri10ge_get_ethtool_stats(struct net_device *netdev,
1350 struct ethtool_stats *stats, u64 * data)
1351{
1352 struct myri10ge_priv *mgp = netdev_priv(netdev);
1353 int i;
1354
1355 for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
1356 data[i] = ((unsigned long *)&mgp->stats)[i];
1357
2c1a1088
BG		 1358 data[i++] = (unsigned int)mgp->tx.boundary;
1359 data[i++] = (unsigned int)(mgp->mtrr >= 0);
1360 data[i++] = (unsigned int)mgp->pdev->irq;
1361 data[i++] = (unsigned int)mgp->msi_enabled;
0da34b6d
BG		 1362 data[i++] = (unsigned int)mgp->read_dma;
1363 data[i++] = (unsigned int)mgp->write_dma;
1364 data[i++] = (unsigned int)mgp->read_write_dma;
1365 data[i++] = (unsigned int)mgp->serial_number;
1366 data[i++] = (unsigned int)mgp->tx.pkt_start;
1367 data[i++] = (unsigned int)mgp->tx.pkt_done;
1368 data[i++] = (unsigned int)mgp->tx.req;
1369 data[i++] = (unsigned int)mgp->tx.done;
1370 data[i++] = (unsigned int)mgp->rx_small.cnt;
1371 data[i++] = (unsigned int)mgp->rx_big.cnt;
1372 data[i++] = (unsigned int)mgp->wake_queue;
1373 data[i++] = (unsigned int)mgp->stop_queue;
1374 data[i++] = (unsigned int)mgp->watchdog_resets;
1375 data[i++] = (unsigned int)mgp->tx_linearized;
c58ac5ca 1376 data[i++] = (unsigned int)mgp->link_changes;
0da34b6d
BG		 1377 data[i++] = (unsigned int)ntohl(mgp->fw_stats->link_up);
1378 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_link_overflow);
1379 data[i++] =
1380 (unsigned int)ntohl(mgp->fw_stats->dropped_link_error_or_filtered);
85a7ea1b
BG		 1381 data[i++] =
1382 (unsigned int)ntohl(mgp->fw_stats->dropped_multicast_filtered);
0da34b6d
BG		 1383 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_runt);
1384 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_overrun);
1385 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_small_buffer);
1386 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_big_buffer);
1387}
1388
c58ac5ca
BG		 1389static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
1390{
1391 struct myri10ge_priv *mgp = netdev_priv(netdev);
1392 mgp->msg_enable = value;
1393}
1394
1395static u32 myri10ge_get_msglevel(struct net_device *netdev)
1396{
1397 struct myri10ge_priv *mgp = netdev_priv(netdev);
1398 return mgp->msg_enable;
1399}
1400
7282d491 1401static const struct ethtool_ops myri10ge_ethtool_ops = {
0da34b6d
BG		 1402 .get_settings = myri10ge_get_settings,
1403 .get_drvinfo = myri10ge_get_drvinfo,
1404 .get_coalesce = myri10ge_get_coalesce,
1405 .set_coalesce = myri10ge_set_coalesce,
1406 .get_pauseparam = myri10ge_get_pauseparam,
1407 .set_pauseparam = myri10ge_set_pauseparam,
1408 .get_ringparam = myri10ge_get_ringparam,
1409 .get_rx_csum = myri10ge_get_rx_csum,
1410 .set_rx_csum = myri10ge_set_rx_csum,
1411 .get_tx_csum = ethtool_op_get_tx_csum,
b10c0668 1412 .set_tx_csum = ethtool_op_set_tx_hw_csum,
0da34b6d
BG		 1413 .get_sg = ethtool_op_get_sg,
1414 .set_sg = ethtool_op_set_sg,
1415#ifdef NETIF_F_TSO
1416 .get_tso = ethtool_op_get_tso,
1417 .set_tso = ethtool_op_set_tso,
1418#endif
1419 .get_strings = myri10ge_get_strings,
1420 .get_stats_count = myri10ge_get_stats_count,
c58ac5ca
BG		 1421 .get_ethtool_stats = myri10ge_get_ethtool_stats,
1422 .set_msglevel = myri10ge_set_msglevel,
1423 .get_msglevel = myri10ge_get_msglevel
0da34b6d
BG		 1424};
1425
1426static int myri10ge_allocate_rings(struct net_device *dev)
1427{
1428 struct myri10ge_priv *mgp;
1429 struct myri10ge_cmd cmd;
1430 int tx_ring_size, rx_ring_size;
1431 int tx_ring_entries, rx_ring_entries;
1432 int i, status;
1433 size_t bytes;
1434
1435 mgp = netdev_priv(dev);
1436
1437 /* get ring sizes */
1438
1439 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1440 tx_ring_size = cmd.data0;
1441 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
1442 rx_ring_size = cmd.data0;
1443
1444 tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1445 rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
1446 mgp->tx.mask = tx_ring_entries - 1;
1447 mgp->rx_small.mask = mgp->rx_big.mask = rx_ring_entries - 1;
1448
1449 /* allocate the host shadow rings */
1450
1451 bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
1452 * sizeof(*mgp->tx.req_list);
1453 mgp->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
1454 if (mgp->tx.req_bytes == NULL)
1455 goto abort_with_nothing;
1456
1457 /* ensure req_list entries are aligned to 8 bytes */
1458 mgp->tx.req_list = (struct mcp_kreq_ether_send *)
1459 ALIGN((unsigned long)mgp->tx.req_bytes, 8);
1460
1461 bytes = rx_ring_entries * sizeof(*mgp->rx_small.shadow);
1462 mgp->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
1463 if (mgp->rx_small.shadow == NULL)
1464 goto abort_with_tx_req_bytes;
1465
1466 bytes = rx_ring_entries * sizeof(*mgp->rx_big.shadow);
1467 mgp->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
1468 if (mgp->rx_big.shadow == NULL)
1469 goto abort_with_rx_small_shadow;
1470
1471 /* allocate the host info rings */
1472
1473 bytes = tx_ring_entries * sizeof(*mgp->tx.info);
1474 mgp->tx.info = kzalloc(bytes, GFP_KERNEL);
1475 if (mgp->tx.info == NULL)
1476 goto abort_with_rx_big_shadow;
1477
1478 bytes = rx_ring_entries * sizeof(*mgp->rx_small.info);
1479 mgp->rx_small.info = kzalloc(bytes, GFP_KERNEL);
1480 if (mgp->rx_small.info == NULL)
1481 goto abort_with_tx_info;
1482
1483 bytes = rx_ring_entries * sizeof(*mgp->rx_big.info);
1484 mgp->rx_big.info = kzalloc(bytes, GFP_KERNEL);
1485 if (mgp->rx_big.info == NULL)
1486 goto abort_with_rx_small_info;
1487
1488 /* Fill the receive rings */
c7dab99b
BG		 1489 mgp->rx_big.cnt = 0;
1490 mgp->rx_small.cnt = 0;
1491 mgp->rx_big.fill_cnt = 0;
1492 mgp->rx_small.fill_cnt = 0;
1493 mgp->rx_small.page_offset = MYRI10GE_ALLOC_SIZE;
1494 mgp->rx_big.page_offset = MYRI10GE_ALLOC_SIZE;
1495 mgp->rx_small.watchdog_needed = 0;
1496 mgp->rx_big.watchdog_needed = 0;
1497 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
1498 mgp->small_bytes + MXGEFW_PAD, 0);
0da34b6d 1499
c7dab99b
BG		 1500 if (mgp->rx_small.fill_cnt < mgp->rx_small.mask + 1) {
1501 printk(KERN_ERR "myri10ge: %s: alloced only %d small bufs\n",
1502 dev->name, mgp->rx_small.fill_cnt);
1503 goto abort_with_rx_small_ring;
0da34b6d
BG		 1504 }
1505
c7dab99b
BG		 1506 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 0);
1507 if (mgp->rx_big.fill_cnt < mgp->rx_big.mask + 1) {
1508 printk(KERN_ERR "myri10ge: %s: alloced only %d big bufs\n",
1509 dev->name, mgp->rx_big.fill_cnt);
1510 goto abort_with_rx_big_ring;
0da34b6d
BG		 1511 }
1512
1513 return 0;
1514
1515abort_with_rx_big_ring:
c7dab99b
BG		 1516 for (i = mgp->rx_big.cnt; i < mgp->rx_big.fill_cnt; i++) {
1517 int idx = i & mgp->rx_big.mask;
1518 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_big.info[idx],
1519 mgp->big_bytes);
1520 put_page(mgp->rx_big.info[idx].page);
0da34b6d
BG		 1521 }
1522
1523abort_with_rx_small_ring:
c7dab99b
BG		 1524 for (i = mgp->rx_small.cnt; i < mgp->rx_small.fill_cnt; i++) {
1525 int idx = i & mgp->rx_small.mask;
1526 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_small.info[idx],
1527 mgp->small_bytes + MXGEFW_PAD);
1528 put_page(mgp->rx_small.info[idx].page);
0da34b6d 1529 }
c7dab99b 1530
0da34b6d
BG		 1531 kfree(mgp->rx_big.info);
1532
1533abort_with_rx_small_info:
1534 kfree(mgp->rx_small.info);
1535
1536abort_with_tx_info:
1537 kfree(mgp->tx.info);
1538
1539abort_with_rx_big_shadow:
1540 kfree(mgp->rx_big.shadow);
1541
1542abort_with_rx_small_shadow:
1543 kfree(mgp->rx_small.shadow);
1544
1545abort_with_tx_req_bytes:
1546 kfree(mgp->tx.req_bytes);
1547 mgp->tx.req_bytes = NULL;
1548 mgp->tx.req_list = NULL;
1549
1550abort_with_nothing:
1551 return status;
1552}
1553
1554static void myri10ge_free_rings(struct net_device *dev)
1555{
1556 struct myri10ge_priv *mgp;
1557 struct sk_buff *skb;
1558 struct myri10ge_tx_buf *tx;
1559 int i, len, idx;
1560
1561 mgp = netdev_priv(dev);
1562
c7dab99b
BG		 1563 for (i = mgp->rx_big.cnt; i < mgp->rx_big.fill_cnt; i++) {
1564 idx = i & mgp->rx_big.mask;
1565 if (i == mgp->rx_big.fill_cnt - 1)
1566 mgp->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE;
1567 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_big.info[idx],
1568 mgp->big_bytes);
1569 put_page(mgp->rx_big.info[idx].page);
0da34b6d
BG		 1570 }
1571
c7dab99b
BG		 1572 for (i = mgp->rx_small.cnt; i < mgp->rx_small.fill_cnt; i++) {
1573 idx = i & mgp->rx_small.mask;
1574 if (i == mgp->rx_small.fill_cnt - 1)
1575 mgp->rx_small.info[idx].page_offset =
1576 MYRI10GE_ALLOC_SIZE;
1577 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_small.info[idx],
1578 mgp->small_bytes + MXGEFW_PAD);
1579 put_page(mgp->rx_small.info[idx].page);
1580 }
0da34b6d
BG		 1581 tx = &mgp->tx;
1582 while (tx->done != tx->req) {
1583 idx = tx->done & tx->mask;
1584 skb = tx->info[idx].skb;
1585
1586 /* Mark as free */
1587 tx->info[idx].skb = NULL;
1588 tx->done++;
1589 len = pci_unmap_len(&tx->info[idx], len);
1590 pci_unmap_len_set(&tx->info[idx], len, 0);
1591 if (skb) {
1592 mgp->stats.tx_dropped++;
1593 dev_kfree_skb_any(skb);
1594 if (len)
1595 pci_unmap_single(mgp->pdev,
1596 pci_unmap_addr(&tx->info[idx],
1597 bus), len,
1598 PCI_DMA_TODEVICE);
1599 } else {
1600 if (len)
1601 pci_unmap_page(mgp->pdev,
1602 pci_unmap_addr(&tx->info[idx],
1603 bus), len,
1604 PCI_DMA_TODEVICE);
1605 }
1606 }
1607 kfree(mgp->rx_big.info);
1608
1609 kfree(mgp->rx_small.info);
1610
1611 kfree(mgp->tx.info);
1612
1613 kfree(mgp->rx_big.shadow);
1614
1615 kfree(mgp->rx_small.shadow);
1616
1617 kfree(mgp->tx.req_bytes);
1618 mgp->tx.req_bytes = NULL;
1619 mgp->tx.req_list = NULL;
1620}
1621
df30a740
BG		 1622static int myri10ge_request_irq(struct myri10ge_priv *mgp)
1623{
1624 struct pci_dev *pdev = mgp->pdev;
1625 int status;
1626
1627 if (myri10ge_msi) {
1628 status = pci_enable_msi(pdev);
1629 if (status != 0)
1630 dev_err(&pdev->dev,
1631 "Error %d setting up MSI; falling back to xPIC\n",
1632 status);
1633 else
1634 mgp->msi_enabled = 1;
1635 } else {
1636 mgp->msi_enabled = 0;
1637 }
1638 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
1639 mgp->dev->name, mgp);
1640 if (status != 0) {
1641 dev_err(&pdev->dev, "failed to allocate IRQ\n");
1642 if (mgp->msi_enabled)
1643 pci_disable_msi(pdev);
1644 }
1645 return status;
1646}
1647
1648static void myri10ge_free_irq(struct myri10ge_priv *mgp)
1649{
1650 struct pci_dev *pdev = mgp->pdev;
1651
1652 free_irq(pdev->irq, mgp);
1653 if (mgp->msi_enabled)
1654 pci_disable_msi(pdev);
1655}
1656
0da34b6d
BG		 1657static int myri10ge_open(struct net_device *dev)
1658{
1659 struct myri10ge_priv *mgp;
1660 struct myri10ge_cmd cmd;
1661 int status, big_pow2;
1662
1663 mgp = netdev_priv(dev);
1664
1665 if (mgp->running != MYRI10GE_ETH_STOPPED)
1666 return -EBUSY;
1667
1668 mgp->running = MYRI10GE_ETH_STARTING;
1669 status = myri10ge_reset(mgp);
1670 if (status != 0) {
1671 printk(KERN_ERR "myri10ge: %s: failed reset\n", dev->name);
df30a740 1672 goto abort_with_nothing;
0da34b6d
BG		 1673 }
1674
df30a740
BG		 1675 status = myri10ge_request_irq(mgp);
1676 if (status != 0)
1677 goto abort_with_nothing;
1678
0da34b6d
BG		 1679 /* decide what small buffer size to use. For good TCP rx
1680 * performance, it is important to not receive 1514 byte
1681 * frames into jumbo buffers, as it confuses the socket buffer
1682 * accounting code, leading to drops and erratic performance.
1683 */
1684
1685 if (dev->mtu <= ETH_DATA_LEN)
c7dab99b
BG		 1686 /* enough for a TCP header */
1687 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
1688 ? (128 - MXGEFW_PAD)
1689 : (SMP_CACHE_BYTES - MXGEFW_PAD);
0da34b6d 1690 else
de3c4507
BG		 1691 /* enough for a vlan encapsulated ETH_DATA_LEN frame */
1692 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
0da34b6d
BG		 1693
1694 /* Override the small buffer size? */
1695 if (myri10ge_small_bytes > 0)
1696 mgp->small_bytes = myri10ge_small_bytes;
1697
0da34b6d
BG		 1698 /* get the lanai pointers to the send and receive rings */
1699
1700 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET, &cmd, 0);
1701 mgp->tx.lanai =
1702 (struct mcp_kreq_ether_send __iomem *)(mgp->sram + cmd.data0);
1703
1704 status |=
1705 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET, &cmd, 0);
1706 mgp->rx_small.lanai =
1707 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1708
1709 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
1710 mgp->rx_big.lanai =
1711 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1712
1713 if (status != 0) {
1714 printk(KERN_ERR
1715 "myri10ge: %s: failed to get ring sizes or locations\n",
1716 dev->name);
1717 mgp->running = MYRI10GE_ETH_STOPPED;
df30a740 1718 goto abort_with_irq;
0da34b6d
BG		 1719 }
1720
6ebc087a 1721 if (myri10ge_wcfifo && mgp->mtrr >= 0) {
e700f9f4
BG		 1722 mgp->tx.wc_fifo = (u8 __iomem *) mgp->sram + MXGEFW_ETH_SEND_4;
1723 mgp->rx_small.wc_fifo =
1724 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_SMALL;
1725 mgp->rx_big.wc_fifo =
1726 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_BIG;
0da34b6d
BG		 1727 } else {
1728 mgp->tx.wc_fifo = NULL;
1729 mgp->rx_small.wc_fifo = NULL;
1730 mgp->rx_big.wc_fifo = NULL;
1731 }
1732
0da34b6d
BG		 1733 /* Firmware needs the big buff size as a power of 2. Lie and
1734 * tell him the buffer is larger, because we only use 1
1735 * buffer/pkt, and the mtu will prevent overruns.
1736 */
13348bee 1737 big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b
BG		 1738 if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) {
1739 while ((big_pow2 & (big_pow2 - 1)) != 0)
1740 big_pow2++;
13348bee 1741 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b
BG		 1742 } else {
1743 big_pow2 = MYRI10GE_ALLOC_SIZE;
1744 mgp->big_bytes = big_pow2;
1745 }
1746
1747 status = myri10ge_allocate_rings(dev);
1748 if (status != 0)
df30a740 1749 goto abort_with_irq;
0da34b6d
BG		 1750
1751 /* now give firmware buffers sizes, and MTU */
1752 cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
1753 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
1754 cmd.data0 = mgp->small_bytes;
1755 status |=
1756 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
1757 cmd.data0 = big_pow2;
1758 status |=
1759 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
1760 if (status) {
1761 printk(KERN_ERR "myri10ge: %s: Couldn't set buffer sizes\n",
1762 dev->name);
1763 goto abort_with_rings;
1764 }
1765
1766 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->fw_stats_bus);
1767 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->fw_stats_bus);
85a7ea1b
BG		 1768 cmd.data2 = sizeof(struct mcp_irq_data);
1769 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
1770 if (status == -ENOSYS) {
1771 dma_addr_t bus = mgp->fw_stats_bus;
1772 bus += offsetof(struct mcp_irq_data, send_done_count);
1773 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
1774 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
1775 status = myri10ge_send_cmd(mgp,
1776 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
1777 &cmd, 0);
1778 /* Firmware cannot support multicast without STATS_DMA_V2 */
1779 mgp->fw_multicast_support = 0;
1780 } else {
1781 mgp->fw_multicast_support = 1;
1782 }
0da34b6d
BG		 1783 if (status) {
1784 printk(KERN_ERR "myri10ge: %s: Couldn't set stats DMA\n",
1785 dev->name);
1786 goto abort_with_rings;
1787 }
1788
40f6cff5 1789 mgp->link_state = htonl(~0U);
0da34b6d
BG		 1790 mgp->rdma_tags_available = 15;
1791
1792 netif_poll_enable(mgp->dev); /* must happen prior to any irq */
1793
1794 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
1795 if (status) {
1796 printk(KERN_ERR "myri10ge: %s: Couldn't bring up link\n",
1797 dev->name);
1798 goto abort_with_rings;
1799 }
1800
1801 mgp->wake_queue = 0;
1802 mgp->stop_queue = 0;
1803 mgp->running = MYRI10GE_ETH_RUNNING;
1804 mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
1805 add_timer(&mgp->watchdog_timer);
1806 netif_wake_queue(dev);
1807 return 0;
1808
1809abort_with_rings:
1810 myri10ge_free_rings(dev);
1811
df30a740
BG		 1812abort_with_irq:
1813 myri10ge_free_irq(mgp);
1814
0da34b6d
BG		 1815abort_with_nothing:
1816 mgp->running = MYRI10GE_ETH_STOPPED;
1817 return -ENOMEM;
1818}
1819
1820static int myri10ge_close(struct net_device *dev)
1821{
1822 struct myri10ge_priv *mgp;
1823 struct myri10ge_cmd cmd;
1824 int status, old_down_cnt;
1825
1826 mgp = netdev_priv(dev);
1827
1828 if (mgp->running != MYRI10GE_ETH_RUNNING)
1829 return 0;
1830
1831 if (mgp->tx.req_bytes == NULL)
1832 return 0;
1833
1834 del_timer_sync(&mgp->watchdog_timer);
1835 mgp->running = MYRI10GE_ETH_STOPPING;
1836 netif_poll_disable(mgp->dev);
1837 netif_carrier_off(dev);
1838 netif_stop_queue(dev);
1839 old_down_cnt = mgp->down_cnt;
1840 mb();
1841 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
1842 if (status)
1843 printk(KERN_ERR "myri10ge: %s: Couldn't bring down link\n",
1844 dev->name);
1845
1846 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt, HZ);
1847 if (old_down_cnt == mgp->down_cnt)
1848 printk(KERN_ERR "myri10ge: %s never got down irq\n", dev->name);
1849
1850 netif_tx_disable(dev);
df30a740 1851 myri10ge_free_irq(mgp);
0da34b6d
BG		 1852 myri10ge_free_rings(dev);
1853
1854 mgp->running = MYRI10GE_ETH_STOPPED;
1855 return 0;
1856}
1857
1858/* copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
1859 * backwards one at a time and handle ring wraps */
1860
1861static inline void
1862myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
1863 struct mcp_kreq_ether_send *src, int cnt)
1864{
1865 int idx, starting_slot;
1866 starting_slot = tx->req;
1867 while (cnt > 1) {
1868 cnt--;
1869 idx = (starting_slot + cnt) & tx->mask;
1870 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
1871 mb();
1872 }
1873}
1874
1875/*
1876 * copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
1877 * at most 32 bytes at a time, so as to avoid involving the software
1878 * pio handler in the nic. We re-write the first segment's flags
1879 * to mark them valid only after writing the entire chain.
1880 */
1881
1882static inline void
1883myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
1884 int cnt)
1885{
1886 int idx, i;
1887 struct mcp_kreq_ether_send __iomem *dstp, *dst;
1888 struct mcp_kreq_ether_send *srcp;
1889 u8 last_flags;
1890
1891 idx = tx->req & tx->mask;
1892
1893 last_flags = src->flags;
1894 src->flags = 0;
1895 mb();
1896 dst = dstp = &tx->lanai[idx];
1897 srcp = src;
1898
1899 if ((idx + cnt) < tx->mask) {
1900 for (i = 0; i < (cnt - 1); i += 2) {
1901 myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
1902 mb(); /* force write every 32 bytes */
1903 srcp += 2;
1904 dstp += 2;
1905 }
1906 } else {
1907 /* submit all but the first request, and ensure
1908 * that it is submitted below */
1909 myri10ge_submit_req_backwards(tx, src, cnt);
1910 i = 0;
1911 }
1912 if (i < cnt) {
1913 /* submit the first request */
1914 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
1915 mb(); /* barrier before setting valid flag */
1916 }
1917
1918 /* re-write the last 32-bits with the valid flags */
1919 src->flags = last_flags;
40f6cff5 1920 put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
0da34b6d
BG		 1921 tx->req += cnt;
1922 mb();
1923}
1924
1925static inline void
1926myri10ge_submit_req_wc(struct myri10ge_tx_buf *tx,
1927 struct mcp_kreq_ether_send *src, int cnt)
1928{
1929 tx->req += cnt;
1930 mb();
1931 while (cnt >= 4) {
1932 myri10ge_pio_copy(tx->wc_fifo, src, 64);
1933 mb();
1934 src += 4;
1935 cnt -= 4;
1936 }
1937 if (cnt > 0) {
1938 /* pad it to 64 bytes. The src is 64 bytes bigger than it
1939 * needs to be so that we don't overrun it */
e700f9f4
BG		 1940 myri10ge_pio_copy(tx->wc_fifo + MXGEFW_ETH_SEND_OFFSET(cnt),
1941 src, 64);
0da34b6d
BG		 1942 mb();
1943 }
1944}
1945
1946/*
1947 * Transmit a packet. We need to split the packet so that a single
1948 * segment does not cross myri10ge->tx.boundary, so this makes segment
1949 * counting tricky. So rather than try to count segments up front, we
1950 * just give up if there are too few segments to hold a reasonably
1951 * fragmented packet currently available. If we run
1952 * out of segments while preparing a packet for DMA, we just linearize
1953 * it and try again.
1954 */
1955
1956static int myri10ge_xmit(struct sk_buff *skb, struct net_device *dev)
1957{
1958 struct myri10ge_priv *mgp = netdev_priv(dev);
1959 struct mcp_kreq_ether_send *req;
1960 struct myri10ge_tx_buf *tx = &mgp->tx;
1961 struct skb_frag_struct *frag;
1962 dma_addr_t bus;
40f6cff5
AV		 1963 u32 low;
1964 __be32 high_swapped;
0da34b6d
BG		 1965 unsigned int len;
1966 int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
1967 u16 pseudo_hdr_offset, cksum_offset;
1968 int cum_len, seglen, boundary, rdma_count;
1969 u8 flags, odd_flag;
1970
1971again:
1972 req = tx->req_list;
1973 avail = tx->mask - 1 - (tx->req - tx->done);
1974
1975 mss = 0;
1976 max_segments = MXGEFW_MAX_SEND_DESC;
1977
1978#ifdef NETIF_F_TSO
1979 if (skb->len > (dev->mtu + ETH_HLEN)) {
7967168c 1980 mss = skb_shinfo(skb)->gso_size;
0da34b6d
BG		 1981 if (mss != 0)
1982 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
1983 }
1984#endif /*NETIF_F_TSO */
1985
1986 if ((unlikely(avail < max_segments))) {
1987 /* we are out of transmit resources */
1988 mgp->stop_queue++;
1989 netif_stop_queue(dev);
1990 return 1;
1991 }
1992
1993 /* Setup checksum offloading, if needed */
1994 cksum_offset = 0;
1995 pseudo_hdr_offset = 0;
1996 odd_flag = 0;
1997 flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
84fa7933 1998 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
0da34b6d 1999 cksum_offset = (skb->h.raw - skb->data);
ff1dcadb 2000 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
0da34b6d
BG		 2001 /* If the headers are excessively large, then we must
2002 * fall back to a software checksum */
2003 if (unlikely(cksum_offset > 255 || pseudo_hdr_offset > 127)) {
84fa7933 2004 if (skb_checksum_help(skb))
0da34b6d
BG		 2005 goto drop;
2006 cksum_offset = 0;
2007 pseudo_hdr_offset = 0;
2008 } else {
0da34b6d
BG		 2009 odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2010 flags |= MXGEFW_FLAGS_CKSUM;
2011 }
2012 }
2013
2014 cum_len = 0;
2015
2016#ifdef NETIF_F_TSO
2017 if (mss) { /* TSO */
2018 /* this removes any CKSUM flag from before */
2019 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
2020
2021 /* negative cum_len signifies to the
2022 * send loop that we are still in the
2023 * header portion of the TSO packet.
2024 * TSO header must be at most 134 bytes long */
2025 cum_len = -((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
2026
2027 /* for TSO, pseudo_hdr_offset holds mss.
2028 * The firmware figures out where to put
2029 * the checksum by parsing the header. */
40f6cff5 2030 pseudo_hdr_offset = mss;
0da34b6d
BG		 2031 } else
2032#endif /*NETIF_F_TSO */
2033 /* Mark small packets, and pad out tiny packets */
2034 if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
2035 flags |= MXGEFW_FLAGS_SMALL;
2036
2037 /* pad frames to at least ETH_ZLEN bytes */
2038 if (unlikely(skb->len < ETH_ZLEN)) {
5b057c6b 2039 if (skb_padto(skb, ETH_ZLEN)) {
0da34b6d
BG		 2040 /* The packet is gone, so we must
2041 * return 0 */
2042 mgp->stats.tx_dropped += 1;
2043 return 0;
2044 }
2045 /* adjust the len to account for the zero pad
2046 * so that the nic can know how long it is */
2047 skb->len = ETH_ZLEN;
2048 }
2049 }
2050
2051 /* map the skb for DMA */
2052 len = skb->len - skb->data_len;
2053 idx = tx->req & tx->mask;
2054 tx->info[idx].skb = skb;
2055 bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
2056 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2057 pci_unmap_len_set(&tx->info[idx], len, len);
2058
2059 frag_cnt = skb_shinfo(skb)->nr_frags;
2060 frag_idx = 0;
2061 count = 0;
2062 rdma_count = 0;
2063
2064 /* "rdma_count" is the number of RDMAs belonging to the
2065 * current packet BEFORE the current send request. For
2066 * non-TSO packets, this is equal to "count".
2067 * For TSO packets, rdma_count needs to be reset
2068 * to 0 after a segment cut.
2069 *
2070 * The rdma_count field of the send request is
2071 * the number of RDMAs of the packet starting at
2072 * that request. For TSO send requests with one ore more cuts
2073 * in the middle, this is the number of RDMAs starting
2074 * after the last cut in the request. All previous
2075 * segments before the last cut implicitly have 1 RDMA.
2076 *
2077 * Since the number of RDMAs is not known beforehand,
2078 * it must be filled-in retroactively - after each
2079 * segmentation cut or at the end of the entire packet.
2080 */
2081
2082 while (1) {
2083 /* Break the SKB or Fragment up into pieces which
2084 * do not cross mgp->tx.boundary */
2085 low = MYRI10GE_LOWPART_TO_U32(bus);
2086 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2087 while (len) {
2088 u8 flags_next;
2089 int cum_len_next;
2090
2091 if (unlikely(count == max_segments))
2092 goto abort_linearize;
2093
2094 boundary = (low + tx->boundary) & ~(tx->boundary - 1);
2095 seglen = boundary - low;
2096 if (seglen > len)
2097 seglen = len;
2098 flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2099 cum_len_next = cum_len + seglen;
2100#ifdef NETIF_F_TSO
2101 if (mss) { /* TSO */
2102 (req - rdma_count)->rdma_count = rdma_count + 1;
2103
2104 if (likely(cum_len >= 0)) { /* payload */
2105 int next_is_first, chop;
2106
2107 chop = (cum_len_next > mss);
2108 cum_len_next = cum_len_next % mss;
2109 next_is_first = (cum_len_next == 0);
2110 flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2111 flags_next |= next_is_first *
2112 MXGEFW_FLAGS_FIRST;
2113 rdma_count |= -(chop | next_is_first);
2114 rdma_count += chop & !next_is_first;
2115 } else if (likely(cum_len_next >= 0)) { /* header ends */
2116 int small;
2117
2118 rdma_count = -1;
2119 cum_len_next = 0;
2120 seglen = -cum_len;
2121 small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2122 flags_next = MXGEFW_FLAGS_TSO_PLD |
2123 MXGEFW_FLAGS_FIRST |
2124 (small * MXGEFW_FLAGS_SMALL);
2125 }
2126 }
2127#endif /* NETIF_F_TSO */
2128 req->addr_high = high_swapped;
2129 req->addr_low = htonl(low);
40f6cff5 2130 req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
0da34b6d
BG		 2131 req->pad = 0; /* complete solid 16-byte block; does this matter? */
2132 req->rdma_count = 1;
2133 req->length = htons(seglen);
2134 req->cksum_offset = cksum_offset;
2135 req->flags = flags | ((cum_len & 1) * odd_flag);
2136
2137 low += seglen;
2138 len -= seglen;
2139 cum_len = cum_len_next;
2140 flags = flags_next;
2141 req++;
2142 count++;
2143 rdma_count++;
2144 if (unlikely(cksum_offset > seglen))
2145 cksum_offset -= seglen;
2146 else
2147 cksum_offset = 0;
2148 }
2149 if (frag_idx == frag_cnt)
2150 break;
2151
2152 /* map next fragment for DMA */
2153 idx = (count + tx->req) & tx->mask;
2154 frag = &skb_shinfo(skb)->frags[frag_idx];
2155 frag_idx++;
2156 len = frag->size;
2157 bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset,
2158 len, PCI_DMA_TODEVICE);
2159 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2160 pci_unmap_len_set(&tx->info[idx], len, len);
2161 }
2162
2163 (req - rdma_count)->rdma_count = rdma_count;
2164#ifdef NETIF_F_TSO
2165 if (mss)
2166 do {
2167 req--;
2168 req->flags |= MXGEFW_FLAGS_TSO_LAST;
2169 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2170 MXGEFW_FLAGS_FIRST)));
2171#endif
2172 idx = ((count - 1) + tx->req) & tx->mask;
2173 tx->info[idx].last = 1;
2174 if (tx->wc_fifo == NULL)
2175 myri10ge_submit_req(tx, tx->req_list, count);
2176 else
2177 myri10ge_submit_req_wc(tx, tx->req_list, count);
2178 tx->pkt_start++;
2179 if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
2180 mgp->stop_queue++;
2181 netif_stop_queue(dev);
2182 }
2183 dev->trans_start = jiffies;
2184 return 0;
2185
2186abort_linearize:
2187 /* Free any DMA resources we've alloced and clear out the skb
2188 * slot so as to not trip up assertions, and to avoid a
2189 * double-free if linearizing fails */
2190
2191 last_idx = (idx + 1) & tx->mask;
2192 idx = tx->req & tx->mask;
2193 tx->info[idx].skb = NULL;
2194 do {
2195 len = pci_unmap_len(&tx->info[idx], len);
2196 if (len) {
2197 if (tx->info[idx].skb != NULL)
2198 pci_unmap_single(mgp->pdev,
2199 pci_unmap_addr(&tx->info[idx],
2200 bus), len,
2201 PCI_DMA_TODEVICE);
2202 else
2203 pci_unmap_page(mgp->pdev,
2204 pci_unmap_addr(&tx->info[idx],
2205 bus), len,
2206 PCI_DMA_TODEVICE);
2207 pci_unmap_len_set(&tx->info[idx], len, 0);
2208 tx->info[idx].skb = NULL;
2209 }
2210 idx = (idx + 1) & tx->mask;
2211 } while (idx != last_idx);
89114afd 2212 if (skb_is_gso(skb)) {
0da34b6d
BG		 2213 printk(KERN_ERR
2214 "myri10ge: %s: TSO but wanted to linearize?!?!?\n",
2215 mgp->dev->name);
2216 goto drop;
2217 }
2218
bec0e859 2219 if (skb_linearize(skb))
0da34b6d
BG		 2220 goto drop;
2221
2222 mgp->tx_linearized++;
2223 goto again;
2224
2225drop:
2226 dev_kfree_skb_any(skb);
2227 mgp->stats.tx_dropped += 1;
2228 return 0;
2229
2230}
2231
2232static struct net_device_stats *myri10ge_get_stats(struct net_device *dev)
2233{
2234 struct myri10ge_priv *mgp = netdev_priv(dev);
2235 return &mgp->stats;
2236}
2237
2238static void myri10ge_set_multicast_list(struct net_device *dev)
2239{
85a7ea1b
BG		 2240 struct myri10ge_cmd cmd;
2241 struct myri10ge_priv *mgp;
2242 struct dev_mc_list *mc_list;
6250223e 2243 __be32 data[2] = { 0, 0 };
85a7ea1b
BG		 2244 int err;
2245
2246 mgp = netdev_priv(dev);
0da34b6d
BG		 2247 /* can be called from atomic contexts,
2248 * pass 1 to force atomicity in myri10ge_send_cmd() */
85a7ea1b
BG		 2249 myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
2250
2251 /* This firmware is known to not support multicast */
2252 if (!mgp->fw_multicast_support)
2253 return;
2254
2255 /* Disable multicast filtering */
2256
2257 err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
2258 if (err != 0) {
2259 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_ENABLE_ALLMULTI,"
2260 " error status: %d\n", dev->name, err);
2261 goto abort;
2262 }
2263
2264 if (dev->flags & IFF_ALLMULTI) {
2265 /* request to disable multicast filtering, so quit here */
2266 return;
2267 }
2268
2269 /* Flush the filters */
2270
2271 err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
2272 &cmd, 1);
2273 if (err != 0) {
2274 printk(KERN_ERR
2275 "myri10ge: %s: Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS"
2276 ", error status: %d\n", dev->name, err);
2277 goto abort;
2278 }
2279
2280 /* Walk the multicast list, and add each address */
2281 for (mc_list = dev->mc_list; mc_list != NULL; mc_list = mc_list->next) {
40f6cff5
AV		 2282 memcpy(data, &mc_list->dmi_addr, 6);
2283 cmd.data0 = ntohl(data[0]);
2284 cmd.data1 = ntohl(data[1]);
85a7ea1b
BG		 2285 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
2286 &cmd, 1);
2287
2288 if (err != 0) {
2289 printk(KERN_ERR "myri10ge: %s: Failed "
2290 "MXGEFW_JOIN_MULTICAST_GROUP, error status:"
2291 "%d\t", dev->name, err);
2292 printk(KERN_ERR "MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
2293 ((unsigned char *)&mc_list->dmi_addr)[0],
2294 ((unsigned char *)&mc_list->dmi_addr)[1],
2295 ((unsigned char *)&mc_list->dmi_addr)[2],
2296 ((unsigned char *)&mc_list->dmi_addr)[3],
2297 ((unsigned char *)&mc_list->dmi_addr)[4],
2298 ((unsigned char *)&mc_list->dmi_addr)[5]
2299 );
2300 goto abort;
2301 }
2302 }
2303 /* Enable multicast filtering */
2304 err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
2305 if (err != 0) {
2306 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_DISABLE_ALLMULTI,"
2307 "error status: %d\n", dev->name, err);
2308 goto abort;
2309 }
2310
2311 return;
2312
2313abort:
2314 return;
0da34b6d
BG		 2315}
2316
2317static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
2318{
2319 struct sockaddr *sa = addr;
2320 struct myri10ge_priv *mgp = netdev_priv(dev);
2321 int status;
2322
2323 if (!is_valid_ether_addr(sa->sa_data))
2324 return -EADDRNOTAVAIL;
2325
2326 status = myri10ge_update_mac_address(mgp, sa->sa_data);
2327 if (status != 0) {
2328 printk(KERN_ERR
2329 "myri10ge: %s: changing mac address failed with %d\n",
2330 dev->name, status);
2331 return status;
2332 }
2333
2334 /* change the dev structure */
2335 memcpy(dev->dev_addr, sa->sa_data, 6);
2336 return 0;
2337}
2338
2339static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
2340{
2341 struct myri10ge_priv *mgp = netdev_priv(dev);
2342 int error = 0;
2343
2344 if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
2345 printk(KERN_ERR "myri10ge: %s: new mtu (%d) is not valid\n",
2346 dev->name, new_mtu);
2347 return -EINVAL;
2348 }
2349 printk(KERN_INFO "%s: changing mtu from %d to %d\n",
2350 dev->name, dev->mtu, new_mtu);
2351 if (mgp->running) {
2352 /* if we change the mtu on an active device, we must
2353 * reset the device so the firmware sees the change */
2354 myri10ge_close(dev);
2355 dev->mtu = new_mtu;
2356 myri10ge_open(dev);
2357 } else
2358 dev->mtu = new_mtu;
2359
2360 return error;
2361}
2362
2363/*
2364 * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
2365 * Only do it if the bridge is a root port since we don't want to disturb
2366 * any other device, except if forced with myri10ge_ecrc_enable > 1.
2367 */
2368
0da34b6d
BG		 2369static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
2370{
2371 struct pci_dev *bridge = mgp->pdev->bus->self;
2372 struct device *dev = &mgp->pdev->dev;
2373 unsigned cap;
2374 unsigned err_cap;
2375 u16 val;
2376 u8 ext_type;
2377 int ret;
2378
2379 if (!myri10ge_ecrc_enable || !bridge)
2380 return;
2381
2382 /* check that the bridge is a root port */
2383 cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
2384 pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
2385 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2386 if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
2387 if (myri10ge_ecrc_enable > 1) {
2388 struct pci_dev *old_bridge = bridge;
2389
2390 /* Walk the hierarchy up to the root port
2391 * where ECRC has to be enabled */
2392 do {
2393 bridge = bridge->bus->self;
2394 if (!bridge) {
2395 dev_err(dev,
2396 "Failed to find root port"
2397 " to force ECRC\n");
2398 return;
2399 }
2400 cap =
2401 pci_find_capability(bridge, PCI_CAP_ID_EXP);
2402 pci_read_config_word(bridge,
2403 cap + PCI_CAP_FLAGS, &val);
2404 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2405 } while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
2406
2407 dev_info(dev,
2408 "Forcing ECRC on non-root port %s"
2409 " (enabling on root port %s)\n",
2410 pci_name(old_bridge), pci_name(bridge));
2411 } else {
2412 dev_err(dev,
2413 "Not enabling ECRC on non-root port %s\n",
2414 pci_name(bridge));
2415 return;
2416 }
2417 }
2418
2419 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
0da34b6d
BG		 2420 if (!cap)
2421 return;
2422
2423 ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
2424 if (ret) {
2425 dev_err(dev, "failed reading ext-conf-space of %s\n",
2426 pci_name(bridge));
2427 dev_err(dev, "\t pci=nommconf in use? "
2428 "or buggy/incomplete/absent ACPI MCFG attr?\n");
2429 return;
2430 }
2431 if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
2432 return;
2433
2434 err_cap |= PCI_ERR_CAP_ECRC_GENE;
2435 pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
2436 dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
2437 mgp->tx.boundary = 4096;
2438 mgp->fw_name = myri10ge_fw_aligned;
2439}
2440
2441/*
2442 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
2443 * when the PCI-E Completion packets are aligned on an 8-byte
2444 * boundary. Some PCI-E chip sets always align Completion packets; on
2445 * the ones that do not, the alignment can be enforced by enabling
2446 * ECRC generation (if supported).
2447 *
2448 * When PCI-E Completion packets are not aligned, it is actually more
2449 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
2450 *
2451 * If the driver can neither enable ECRC nor verify that it has
2452 * already been enabled, then it must use a firmware image which works
2453 * around unaligned completion packets (myri10ge_ethp_z8e.dat), and it
2454 * should also ensure that it never gives the device a Read-DMA which is
2455 * larger than 2KB by setting the tx.boundary to 2KB. If ECRC is
2456 * enabled, then the driver should use the aligned (myri10ge_eth_z8e.dat)
2457 * firmware image, and set tx.boundary to 4KB.
2458 */
2459
ce7f9368
BG		 2460#define PCI_DEVICE_ID_INTEL_E5000_PCIE23 0x25f7
2461#define PCI_DEVICE_ID_INTEL_E5000_PCIE47 0x25fa
0da34b6d
BG		 2462
2463static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
2464{
2465 struct pci_dev *bridge = mgp->pdev->bus->self;
2466
2467 mgp->tx.boundary = 2048;
2468 mgp->fw_name = myri10ge_fw_unaligned;
2469
2470 if (myri10ge_force_firmware == 0) {
ce7f9368
BG		 2471 int link_width, exp_cap;
2472 u16 lnk;
2473
2474 exp_cap = pci_find_capability(mgp->pdev, PCI_CAP_ID_EXP);
2475 pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
2476 link_width = (lnk >> 4) & 0x3f;
2477
0da34b6d
BG		 2478 myri10ge_enable_ecrc(mgp);
2479
ce7f9368
BG		 2480 /* Check to see if Link is less than 8 or if the
2481 * upstream bridge is known to provide aligned
2482 * completions */
2483 if (link_width < 8) {
2484 dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
2485 link_width);
2486 mgp->tx.boundary = 4096;
2487 mgp->fw_name = myri10ge_fw_aligned;
2488 } else if (bridge &&
2489 /* ServerWorks HT2000/HT1000 */
2490 ((bridge->vendor == PCI_VENDOR_ID_SERVERWORKS
2491 && bridge->device ==
2492 PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE)
2493 /* All Intel E5000 PCIE ports */
2494 || (bridge->vendor == PCI_VENDOR_ID_INTEL
2495 && bridge->device >=
2496 PCI_DEVICE_ID_INTEL_E5000_PCIE23
2497 && bridge->device <=
2498 PCI_DEVICE_ID_INTEL_E5000_PCIE47))) {
0da34b6d
BG		 2499 dev_info(&mgp->pdev->dev,
2500 "Assuming aligned completions (0x%x:0x%x)\n",
2501 bridge->vendor, bridge->device);
2502 mgp->tx.boundary = 4096;
2503 mgp->fw_name = myri10ge_fw_aligned;
2504 }
2505 } else {
2506 if (myri10ge_force_firmware == 1) {
2507 dev_info(&mgp->pdev->dev,
2508 "Assuming aligned completions (forced)\n");
2509 mgp->tx.boundary = 4096;
2510 mgp->fw_name = myri10ge_fw_aligned;
2511 } else {
2512 dev_info(&mgp->pdev->dev,
2513 "Assuming unaligned completions (forced)\n");
2514 mgp->tx.boundary = 2048;
2515 mgp->fw_name = myri10ge_fw_unaligned;
2516 }
2517 }
2518 if (myri10ge_fw_name != NULL) {
2519 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
2520 myri10ge_fw_name);
2521 mgp->fw_name = myri10ge_fw_name;
2522 }
2523}
2524
0da34b6d
BG		 2525#ifdef CONFIG_PM
2526
2527static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
2528{
2529 struct myri10ge_priv *mgp;
2530 struct net_device *netdev;
2531
2532 mgp = pci_get_drvdata(pdev);
2533 if (mgp == NULL)
2534 return -EINVAL;
2535 netdev = mgp->dev;
2536
2537 netif_device_detach(netdev);
2538 if (netif_running(netdev)) {
2539 printk(KERN_INFO "myri10ge: closing %s\n", netdev->name);
2540 rtnl_lock();
2541 myri10ge_close(netdev);
2542 rtnl_unlock();
2543 }
2544 myri10ge_dummy_rdma(mgp, 0);
83f6e152 2545 pci_save_state(pdev);
0da34b6d 2546 pci_disable_device(pdev);
1a63e846
BG		 2547
2548 return pci_set_power_state(pdev, pci_choose_state(pdev, state));
0da34b6d
BG		 2549}
2550
2551static int myri10ge_resume(struct pci_dev *pdev)
2552{
2553 struct myri10ge_priv *mgp;
2554 struct net_device *netdev;
2555 int status;
2556 u16 vendor;
2557
2558 mgp = pci_get_drvdata(pdev);
2559 if (mgp == NULL)
2560 return -EINVAL;
2561 netdev = mgp->dev;
2562 pci_set_power_state(pdev, 0); /* zeros conf space as a side effect */
2563 msleep(5); /* give card time to respond */
2564 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2565 if (vendor == 0xffff) {
2566 printk(KERN_ERR "myri10ge: %s: device disappeared!\n",
2567 mgp->dev->name);
2568 return -EIO;
2569 }
83f6e152 2570
1a63e846
BG		 2571 status = pci_restore_state(pdev);
2572 if (status)
2573 return status;
4c2248cc
BG		 2574
2575 status = pci_enable_device(pdev);
1a63e846 2576 if (status) {
4c2248cc 2577 dev_err(&pdev->dev, "failed to enable device\n");
1a63e846 2578 return status;
4c2248cc
BG		 2579 }
2580
0da34b6d
BG		 2581 pci_set_master(pdev);
2582
0da34b6d 2583 myri10ge_reset(mgp);
013b68bf 2584 myri10ge_dummy_rdma(mgp, 1);
0da34b6d
BG		 2585
2586 /* Save configuration space to be restored if the
2587 * nic resets due to a parity error */
83f6e152 2588 pci_save_state(pdev);
0da34b6d
BG		 2589
2590 if (netif_running(netdev)) {
2591 rtnl_lock();
df30a740 2592 status = myri10ge_open(netdev);
0da34b6d 2593 rtnl_unlock();
df30a740
BG		 2594 if (status != 0)
2595 goto abort_with_enabled;
2596
0da34b6d
BG		 2597 }
2598 netif_device_attach(netdev);
2599
2600 return 0;
2601
4c2248cc
BG		 2602abort_with_enabled:
2603 pci_disable_device(pdev);
0da34b6d
BG		 2604 return -EIO;
2605
2606}
2607
2608#endif /* CONFIG_PM */
2609
2610static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
2611{
2612 struct pci_dev *pdev = mgp->pdev;
2613 int vs = mgp->vendor_specific_offset;
2614 u32 reboot;
2615
2616 /*enter read32 mode */
2617 pci_write_config_byte(pdev, vs + 0x10, 0x3);
2618
2619 /*read REBOOT_STATUS (0xfffffff0) */
2620 pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
2621 pci_read_config_dword(pdev, vs + 0x14, &reboot);
2622 return reboot;
2623}
2624
2625/*
2626 * This watchdog is used to check whether the board has suffered
2627 * from a parity error and needs to be recovered.
2628 */
c4028958 2629static void myri10ge_watchdog(struct work_struct *work)
0da34b6d 2630{
c4028958 2631 struct myri10ge_priv *mgp =
6250223e 2632 container_of(work, struct myri10ge_priv, watchdog_work);
0da34b6d
BG		 2633 u32 reboot;
2634 int status;
2635 u16 cmd, vendor;
2636
2637 mgp->watchdog_resets++;
2638 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
2639 if ((cmd & PCI_COMMAND_MASTER) == 0) {
2640 /* Bus master DMA disabled? Check to see
2641 * if the card rebooted due to a parity error
2642 * For now, just report it */
2643 reboot = myri10ge_read_reboot(mgp);
2644 printk(KERN_ERR
2645 "myri10ge: %s: NIC rebooted (0x%x), resetting\n",
2646 mgp->dev->name, reboot);
2647 /*
2648 * A rebooted nic will come back with config space as
2649 * it was after power was applied to PCIe bus.
2650 * Attempt to restore config space which was saved
2651 * when the driver was loaded, or the last time the
2652 * nic was resumed from power saving mode.
2653 */
83f6e152 2654 pci_restore_state(mgp->pdev);
7adda30c
BG		 2655
2656 /* save state again for accounting reasons */
83f6e152 2657 pci_save_state(mgp->pdev);
7adda30c 2658
0da34b6d
BG		 2659 } else {
2660 /* if we get back -1's from our slot, perhaps somebody
2661 * powered off our card. Don't try to reset it in
2662 * this case */
2663 if (cmd == 0xffff) {
2664 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2665 if (vendor == 0xffff) {
2666 printk(KERN_ERR
2667 "myri10ge: %s: device disappeared!\n",
2668 mgp->dev->name);
2669 return;
2670 }
2671 }
2672 /* Perhaps it is a software error. Try to reset */
2673
2674 printk(KERN_ERR "myri10ge: %s: device timeout, resetting\n",
2675 mgp->dev->name);
2676 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
2677 mgp->dev->name, mgp->tx.req, mgp->tx.done,
2678 mgp->tx.pkt_start, mgp->tx.pkt_done,
2679 (int)ntohl(mgp->fw_stats->send_done_count));
2680 msleep(2000);
2681 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
2682 mgp->dev->name, mgp->tx.req, mgp->tx.done,
2683 mgp->tx.pkt_start, mgp->tx.pkt_done,
2684 (int)ntohl(mgp->fw_stats->send_done_count));
2685 }
2686 rtnl_lock();
2687 myri10ge_close(mgp->dev);
2688 status = myri10ge_load_firmware(mgp);
2689 if (status != 0)
2690 printk(KERN_ERR "myri10ge: %s: failed to load firmware\n",
2691 mgp->dev->name);
2692 else
2693 myri10ge_open(mgp->dev);
2694 rtnl_unlock();
2695}
2696
2697/*
2698 * We use our own timer routine rather than relying upon
2699 * netdev->tx_timeout because we have a very large hardware transmit
2700 * queue. Due to the large queue, the netdev->tx_timeout function
2701 * cannot detect a NIC with a parity error in a timely fashion if the
2702 * NIC is lightly loaded.
2703 */
2704static void myri10ge_watchdog_timer(unsigned long arg)
2705{
2706 struct myri10ge_priv *mgp;
2707
2708 mgp = (struct myri10ge_priv *)arg;
c7dab99b
BG		 2709
2710 if (mgp->rx_small.watchdog_needed) {
2711 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
2712 mgp->small_bytes + MXGEFW_PAD, 1);
2713 if (mgp->rx_small.fill_cnt - mgp->rx_small.cnt >=
2714 myri10ge_fill_thresh)
2715 mgp->rx_small.watchdog_needed = 0;
2716 }
2717 if (mgp->rx_big.watchdog_needed) {
2718 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 1);
2719 if (mgp->rx_big.fill_cnt - mgp->rx_big.cnt >=
2720 myri10ge_fill_thresh)
2721 mgp->rx_big.watchdog_needed = 0;
2722 }
2723
0da34b6d 2724 if (mgp->tx.req != mgp->tx.done &&
c54772e7
BG		 2725 mgp->tx.done == mgp->watchdog_tx_done &&
2726 mgp->watchdog_tx_req != mgp->watchdog_tx_done)
0da34b6d
BG		 2727 /* nic seems like it might be stuck.. */
2728 schedule_work(&mgp->watchdog_work);
2729 else
2730 /* rearm timer */
2731 mod_timer(&mgp->watchdog_timer,
2732 jiffies + myri10ge_watchdog_timeout * HZ);
2733
2734 mgp->watchdog_tx_done = mgp->tx.done;
c54772e7 2735 mgp->watchdog_tx_req = mgp->tx.req;
0da34b6d
BG		 2736}
2737
2738static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2739{
2740 struct net_device *netdev;
2741 struct myri10ge_priv *mgp;
2742 struct device *dev = &pdev->dev;
2743 size_t bytes;
2744 int i;
2745 int status = -ENXIO;
2746 int cap;
2747 int dac_enabled;
2748 u16 val;
2749
2750 netdev = alloc_etherdev(sizeof(*mgp));
2751 if (netdev == NULL) {
2752 dev_err(dev, "Could not allocate ethernet device\n");
2753 return -ENOMEM;
2754 }
2755
2756 mgp = netdev_priv(netdev);
2757 memset(mgp, 0, sizeof(*mgp));
2758 mgp->dev = netdev;
2759 mgp->pdev = pdev;
2760 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
2761 mgp->pause = myri10ge_flow_control;
2762 mgp->intr_coal_delay = myri10ge_intr_coal_delay;
c58ac5ca 2763 mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
0da34b6d
BG		 2764 init_waitqueue_head(&mgp->down_wq);
2765
2766 if (pci_enable_device(pdev)) {
2767 dev_err(&pdev->dev, "pci_enable_device call failed\n");
2768 status = -ENODEV;
2769 goto abort_with_netdev;
2770 }
2771 myri10ge_select_firmware(mgp);
2772
2773 /* Find the vendor-specific cap so we can check
2774 * the reboot register later on */
2775 mgp->vendor_specific_offset
2776 = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
2777
2778 /* Set our max read request to 4KB */
2779 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2780 if (cap < 64) {
2781 dev_err(&pdev->dev, "Bad PCI_CAP_ID_EXP location %d\n", cap);
2782 goto abort_with_netdev;
2783 }
2784 status = pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &val);
2785 if (status != 0) {
2786 dev_err(&pdev->dev, "Error %d reading PCI_EXP_DEVCTL\n",
2787 status);
2788 goto abort_with_netdev;
2789 }
2790 val = (val & ~PCI_EXP_DEVCTL_READRQ) | (5 << 12);
2791 status = pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, val);
2792 if (status != 0) {
2793 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
2794 status);
2795 goto abort_with_netdev;
2796 }
2797
2798 pci_set_master(pdev);
2799 dac_enabled = 1;
2800 status = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
2801 if (status != 0) {
2802 dac_enabled = 0;
2803 dev_err(&pdev->dev,
2804 "64-bit pci address mask was refused, trying 32-bit");
2805 status = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2806 }
2807 if (status != 0) {
2808 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
2809 goto abort_with_netdev;
2810 }
b10c0668
BG		 2811 mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
2812 &mgp->cmd_bus, GFP_KERNEL);
0da34b6d
BG		 2813 if (mgp->cmd == NULL)
2814 goto abort_with_netdev;
2815
b10c0668
BG		 2816 mgp->fw_stats = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
2817 &mgp->fw_stats_bus, GFP_KERNEL);
0da34b6d
BG		 2818 if (mgp->fw_stats == NULL)
2819 goto abort_with_cmd;
2820
2821 mgp->board_span = pci_resource_len(pdev, 0);
2822 mgp->iomem_base = pci_resource_start(pdev, 0);
2823 mgp->mtrr = -1;
2824#ifdef CONFIG_MTRR
2825 mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
2826 MTRR_TYPE_WRCOMB, 1);
2827#endif
2828 /* Hack. need to get rid of these magic numbers */
2829 mgp->sram_size =
2830 2 * 1024 * 1024 - (2 * (48 * 1024) + (32 * 1024)) - 0x100;
2831 if (mgp->sram_size > mgp->board_span) {
2832 dev_err(&pdev->dev, "board span %ld bytes too small\n",
2833 mgp->board_span);
2834 goto abort_with_wc;
2835 }
2836 mgp->sram = ioremap(mgp->iomem_base, mgp->board_span);
2837 if (mgp->sram == NULL) {
2838 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
2839 mgp->board_span, mgp->iomem_base);
2840 status = -ENXIO;
2841 goto abort_with_wc;
2842 }
2843 memcpy_fromio(mgp->eeprom_strings,
2844 mgp->sram + mgp->sram_size - MYRI10GE_EEPROM_STRINGS_SIZE,
2845 MYRI10GE_EEPROM_STRINGS_SIZE);
2846 memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
2847 status = myri10ge_read_mac_addr(mgp);
2848 if (status)
2849 goto abort_with_ioremap;
2850
2851 for (i = 0; i < ETH_ALEN; i++)
2852 netdev->dev_addr[i] = mgp->mac_addr[i];
2853
2854 /* allocate rx done ring */
2855 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
b10c0668
BG		 2856 mgp->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
2857 &mgp->rx_done.bus, GFP_KERNEL);
0da34b6d
BG		 2858 if (mgp->rx_done.entry == NULL)
2859 goto abort_with_ioremap;
2860 memset(mgp->rx_done.entry, 0, bytes);
2861
2862 status = myri10ge_load_firmware(mgp);
2863 if (status != 0) {
2864 dev_err(&pdev->dev, "failed to load firmware\n");
2865 goto abort_with_rx_done;
2866 }
2867
2868 status = myri10ge_reset(mgp);
2869 if (status != 0) {
2870 dev_err(&pdev->dev, "failed reset\n");
2871 goto abort_with_firmware;
2872 }
2873
0da34b6d
BG		 2874 pci_set_drvdata(pdev, mgp);
2875 if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
2876 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
2877 if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
2878 myri10ge_initial_mtu = 68;
2879 netdev->mtu = myri10ge_initial_mtu;
2880 netdev->open = myri10ge_open;
2881 netdev->stop = myri10ge_close;
2882 netdev->hard_start_xmit = myri10ge_xmit;
2883 netdev->get_stats = myri10ge_get_stats;
2884 netdev->base_addr = mgp->iomem_base;
2885 netdev->irq = pdev->irq;
2886 netdev->change_mtu = myri10ge_change_mtu;
2887 netdev->set_multicast_list = myri10ge_set_multicast_list;
2888 netdev->set_mac_address = myri10ge_set_mac_address;
2889 netdev->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
2890 if (dac_enabled)
2891 netdev->features |= NETIF_F_HIGHDMA;
2892 netdev->poll = myri10ge_poll;
2893 netdev->weight = myri10ge_napi_weight;
2894
2895 /* Save configuration space to be restored if the
2896 * nic resets due to a parity error */
83f6e152 2897 pci_save_state(pdev);
0da34b6d
BG		 2898
2899 /* Setup the watchdog timer */
2900 setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
2901 (unsigned long)mgp);
2902
2903 SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
c4028958 2904 INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
0da34b6d
BG		 2905 status = register_netdev(netdev);
2906 if (status != 0) {
2907 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
7adda30c 2908 goto abort_with_state;
0da34b6d 2909 }
df30a740 2910 dev_info(dev, "%d, tx bndry %d, fw %s, WC %s\n",
d6020787
BG		 2911 pdev->irq, mgp->tx.boundary, mgp->fw_name,
2912 (mgp->mtrr >= 0 ? "Enabled" : "Disabled"));
0da34b6d
BG		 2913
2914 return 0;
2915
7adda30c 2916abort_with_state:
83f6e152 2917 pci_restore_state(pdev);
0da34b6d
BG		 2918
2919abort_with_firmware:
2920 myri10ge_dummy_rdma(mgp, 0);
2921
2922abort_with_rx_done:
2923 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
b10c0668
BG		 2924 dma_free_coherent(&pdev->dev, bytes,
2925 mgp->rx_done.entry, mgp->rx_done.bus);
0da34b6d
BG		 2926
2927abort_with_ioremap:
2928 iounmap(mgp->sram);
2929
2930abort_with_wc:
2931#ifdef CONFIG_MTRR
2932 if (mgp->mtrr >= 0)
2933 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
2934#endif
b10c0668
BG		 2935 dma_free_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
2936 mgp->fw_stats, mgp->fw_stats_bus);
0da34b6d
BG		 2937
2938abort_with_cmd:
b10c0668
BG		 2939 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
2940 mgp->cmd, mgp->cmd_bus);
0da34b6d
BG		 2941
2942abort_with_netdev:
2943
2944 free_netdev(netdev);
2945 return status;
2946}
2947
2948/*
2949 * myri10ge_remove
2950 *
2951 * Does what is necessary to shutdown one Myrinet device. Called
2952 * once for each Myrinet card by the kernel when a module is
2953 * unloaded.
2954 */
2955static void myri10ge_remove(struct pci_dev *pdev)
2956{
2957 struct myri10ge_priv *mgp;
2958 struct net_device *netdev;
2959 size_t bytes;
2960
2961 mgp = pci_get_drvdata(pdev);
2962 if (mgp == NULL)
2963 return;
2964
2965 flush_scheduled_work();
2966 netdev = mgp->dev;
2967 unregister_netdev(netdev);
0da34b6d
BG		 2968
2969 myri10ge_dummy_rdma(mgp, 0);
2970
7adda30c 2971 /* avoid a memory leak */
83f6e152 2972 pci_restore_state(pdev);
7adda30c 2973
0da34b6d 2974 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
b10c0668
BG		 2975 dma_free_coherent(&pdev->dev, bytes,
2976 mgp->rx_done.entry, mgp->rx_done.bus);
0da34b6d
BG		 2977
2978 iounmap(mgp->sram);
2979
2980#ifdef CONFIG_MTRR
2981 if (mgp->mtrr >= 0)
2982 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
2983#endif
b10c0668
BG		 2984 dma_free_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
2985 mgp->fw_stats, mgp->fw_stats_bus);
0da34b6d 2986
b10c0668
BG		 2987 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
2988 mgp->cmd, mgp->cmd_bus);
0da34b6d
BG		 2989
2990 free_netdev(netdev);
2991 pci_set_drvdata(pdev, NULL);
2992}
2993
b10c0668 2994#define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E 0x0008
0da34b6d
BG		 2995
2996static struct pci_device_id myri10ge_pci_tbl[] = {
b10c0668 2997 {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
0da34b6d
BG		 2998 {0},
2999};
3000
3001static struct pci_driver myri10ge_driver = {
3002 .name = "myri10ge",
3003 .probe = myri10ge_probe,
3004 .remove = myri10ge_remove,
3005 .id_table = myri10ge_pci_tbl,
3006#ifdef CONFIG_PM
3007 .suspend = myri10ge_suspend,
3008 .resume = myri10ge_resume,
3009#endif
3010};
3011
3012static __init int myri10ge_init_module(void)
3013{
3014 printk(KERN_INFO "%s: Version %s\n", myri10ge_driver.name,
3015 MYRI10GE_VERSION_STR);
3016 return pci_register_driver(&myri10ge_driver);
3017}
3018
3019module_init(myri10ge_init_module);
3020
3021static __exit void myri10ge_cleanup_module(void)
3022{
3023 pci_unregister_driver(&myri10ge_driver);
3024}
3025
3026module_exit(myri10ge_cleanup_module);
Linux 6.x block layer and io_uring tree(s)