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mv643xx_eth: kill ->rx_resource_err
[linux-2.6-block.git] / drivers / net / mv643xx_eth.c
CommitLineData
1da177e4 1/*
9c1bbdfe 2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
1da177e4
LT		 3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
4547fa61
LB		 6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
1da177e4
LT		 8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
3bb8a18a 10 * written by Manish Lachwani
1da177e4
LT		 11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
c8aaea25 14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
1da177e4
LT		 15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
4547fa61
LB		 20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
1da177e4
LT		 23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36 */
a779d38c 37
1da177e4
LT		 38#include <linux/init.h>
39#include <linux/dma-mapping.h>
b6298c22 40#include <linux/in.h>
1da177e4
LT		 41#include <linux/tcp.h>
42#include <linux/udp.h>
43#include <linux/etherdevice.h>
1da177e4
LT		 44#include <linux/delay.h>
45#include <linux/ethtool.h>
d052d1be 46#include <linux/platform_device.h>
fbd6a754
LB		 47#include <linux/module.h>
48#include <linux/kernel.h>
49#include <linux/spinlock.h>
50#include <linux/workqueue.h>
51#include <linux/mii.h>
fbd6a754 52#include <linux/mv643xx_eth.h>
1da177e4
LT		 53#include <asm/io.h>
54#include <asm/types.h>
1da177e4 55#include <asm/system.h>
fbd6a754 56
e5371493
LB		 57static char mv643xx_eth_driver_name[] = "mv643xx_eth";
58static char mv643xx_eth_driver_version[] = "1.0";
c9df406f 59
e5371493
LB		 60#define MV643XX_ETH_CHECKSUM_OFFLOAD_TX
61#define MV643XX_ETH_NAPI
62#define MV643XX_ETH_TX_FAST_REFILL
63#undef MV643XX_ETH_COAL
fbd6a754 64
e5371493
LB		 65#define MV643XX_ETH_TX_COAL 100
66#ifdef MV643XX_ETH_COAL
67#define MV643XX_ETH_RX_COAL 100
fbd6a754
LB		 68#endif
69
e5371493 70#ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
fbd6a754
LB		 71#define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
72#else
73#define MAX_DESCS_PER_SKB 1
74#endif
75
76#define ETH_VLAN_HLEN 4
77#define ETH_FCS_LEN 4
78#define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */
79#define ETH_WRAPPER_LEN (ETH_HW_IP_ALIGN + ETH_HLEN + \
80 ETH_VLAN_HLEN + ETH_FCS_LEN)
81#define ETH_RX_SKB_SIZE (dev->mtu + ETH_WRAPPER_LEN + \
82 dma_get_cache_alignment())
83
84/*
85 * Registers shared between all ports.
86 */
3cb4667c
LB		 87#define PHY_ADDR 0x0000
88#define SMI_REG 0x0004
89#define WINDOW_BASE(w) (0x0200 + ((w) << 3))
90#define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
91#define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
92#define WINDOW_BAR_ENABLE 0x0290
93#define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
fbd6a754
LB		 94
95/*
96 * Per-port registers.
97 */
3cb4667c 98#define PORT_CONFIG(p) (0x0400 + ((p) << 10))
d9a073ea 99#define UNICAST_PROMISCUOUS_MODE 0x00000001
3cb4667c
LB		 100#define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
101#define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
102#define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
103#define SDMA_CONFIG(p) (0x041c + ((p) << 10))
104#define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
105#define PORT_STATUS(p) (0x0444 + ((p) << 10))
a2a41689 106#define TX_FIFO_EMPTY 0x00000400
3cb4667c
LB		 107#define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
108#define TX_BW_MTU(p) (0x0458 + ((p) << 10))
109#define INT_CAUSE(p) (0x0460 + ((p) << 10))
073a345c
LB		 110#define INT_RX 0x00000804
111#define INT_EXT 0x00000002
3cb4667c 112#define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
073a345c
LB		 113#define INT_EXT_LINK 0x00100000
114#define INT_EXT_PHY 0x00010000
115#define INT_EXT_TX_ERROR_0 0x00000100
116#define INT_EXT_TX_0 0x00000001
117#define INT_EXT_TX 0x00000101
3cb4667c
LB		 118#define INT_MASK(p) (0x0468 + ((p) << 10))
119#define INT_MASK_EXT(p) (0x046c + ((p) << 10))
120#define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
121#define RXQ_CURRENT_DESC_PTR(p) (0x060c + ((p) << 10))
122#define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
123#define TXQ_CURRENT_DESC_PTR(p) (0x06c0 + ((p) << 10))
124#define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
125#define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
126#define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
127#define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
fbd6a754 128
2679a550
LB		 129
130/*
131 * SDMA configuration register.
132 */
fbd6a754 133#define RX_BURST_SIZE_4_64BIT (2 << 1)
fbd6a754 134#define BLM_RX_NO_SWAP (1 << 4)
fbd6a754 135#define BLM_TX_NO_SWAP (1 << 5)
fbd6a754 136#define TX_BURST_SIZE_4_64BIT (2 << 22)
fbd6a754
LB		 137
138#if defined(__BIG_ENDIAN)
139#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
140 RX_BURST_SIZE_4_64BIT | \
fbd6a754
LB		 141 TX_BURST_SIZE_4_64BIT
142#elif defined(__LITTLE_ENDIAN)
143#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
144 RX_BURST_SIZE_4_64BIT | \
145 BLM_RX_NO_SWAP | \
146 BLM_TX_NO_SWAP | \
fbd6a754
LB		 147 TX_BURST_SIZE_4_64BIT
148#else
149#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
150#endif
151
2beff77b
LB		 152
153/*
154 * Port serial control register.
155 */
156#define SET_MII_SPEED_TO_100 (1 << 24)
157#define SET_GMII_SPEED_TO_1000 (1 << 23)
158#define SET_FULL_DUPLEX_MODE (1 << 21)
fbd6a754 159#define MAX_RX_PACKET_1522BYTE (1 << 17)
fbd6a754
LB		 160#define MAX_RX_PACKET_9700BYTE (5 << 17)
161#define MAX_RX_PACKET_MASK (7 << 17)
2beff77b
LB		 162#define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
163#define DO_NOT_FORCE_LINK_FAIL (1 << 10)
164#define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
165#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
166#define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
167#define FORCE_LINK_PASS (1 << 1)
168#define SERIAL_PORT_ENABLE (1 << 0)
fbd6a754 169
cc9754b3
LB		 170#define DEFAULT_RX_QUEUE_SIZE 400
171#define DEFAULT_TX_QUEUE_SIZE 800
fbd6a754 172
fbd6a754 173/* SMI reg */
cc9754b3
LB		 174#define SMI_BUSY 0x10000000 /* 0 - Write, 1 - Read */
175#define SMI_READ_VALID 0x08000000 /* 0 - Write, 1 - Read */
176#define SMI_OPCODE_WRITE 0 /* Completion of Read */
177#define SMI_OPCODE_READ 0x04000000 /* Operation is in progress */
fbd6a754 178
fbd6a754
LB		 179/* typedefs */
180
cc9754b3 181typedef enum _func_ret_status {
fbd6a754
LB		 182 ETH_OK, /* Returned as expected. */
183 ETH_ERROR, /* Fundamental error. */
184 ETH_RETRY, /* Could not process request. Try later.*/
185 ETH_END_OF_JOB, /* Ring has nothing to process. */
186 ETH_QUEUE_FULL, /* Ring resource error. */
187 ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */
cc9754b3 188} FUNC_RET_STATUS;
fbd6a754 189
7ca72a3b
LB		 190/*
191 * RX/TX descriptors.
fbd6a754
LB		 192 */
193#if defined(__BIG_ENDIAN)
cc9754b3 194struct rx_desc {
fbd6a754
LB		 195 u16 byte_cnt; /* Descriptor buffer byte count */
196 u16 buf_size; /* Buffer size */
197 u32 cmd_sts; /* Descriptor command status */
198 u32 next_desc_ptr; /* Next descriptor pointer */
199 u32 buf_ptr; /* Descriptor buffer pointer */
200};
201
cc9754b3 202struct tx_desc {
fbd6a754
LB		 203 u16 byte_cnt; /* buffer byte count */
204 u16 l4i_chk; /* CPU provided TCP checksum */
205 u32 cmd_sts; /* Command/status field */
206 u32 next_desc_ptr; /* Pointer to next descriptor */
207 u32 buf_ptr; /* pointer to buffer for this descriptor*/
208};
209#elif defined(__LITTLE_ENDIAN)
cc9754b3 210struct rx_desc {
fbd6a754
LB		 211 u32 cmd_sts; /* Descriptor command status */
212 u16 buf_size; /* Buffer size */
213 u16 byte_cnt; /* Descriptor buffer byte count */
214 u32 buf_ptr; /* Descriptor buffer pointer */
215 u32 next_desc_ptr; /* Next descriptor pointer */
216};
217
cc9754b3 218struct tx_desc {
fbd6a754
LB		 219 u32 cmd_sts; /* Command/status field */
220 u16 l4i_chk; /* CPU provided TCP checksum */
221 u16 byte_cnt; /* buffer byte count */
222 u32 buf_ptr; /* pointer to buffer for this descriptor*/
223 u32 next_desc_ptr; /* Pointer to next descriptor */
224};
225#else
226#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
227#endif
228
7ca72a3b 229/* RX & TX descriptor command */
cc9754b3 230#define BUFFER_OWNED_BY_DMA 0x80000000
7ca72a3b
LB		 231
232/* RX & TX descriptor status */
cc9754b3 233#define ERROR_SUMMARY 0x00000001
7ca72a3b
LB		 234
235/* RX descriptor status */
cc9754b3
LB		 236#define LAYER_4_CHECKSUM_OK 0x40000000
237#define RX_ENABLE_INTERRUPT 0x20000000
238#define RX_FIRST_DESC 0x08000000
239#define RX_LAST_DESC 0x04000000
7ca72a3b
LB		 240
241/* TX descriptor command */
cc9754b3
LB		 242#define TX_ENABLE_INTERRUPT 0x00800000
243#define GEN_CRC 0x00400000
244#define TX_FIRST_DESC 0x00200000
245#define TX_LAST_DESC 0x00100000
246#define ZERO_PADDING 0x00080000
247#define GEN_IP_V4_CHECKSUM 0x00040000
248#define GEN_TCP_UDP_CHECKSUM 0x00020000
249#define UDP_FRAME 0x00010000
7ca72a3b 250
cc9754b3 251#define TX_IHL_SHIFT 11
7ca72a3b
LB		 252
253
fbd6a754
LB		 254/* Unified struct for Rx and Tx operations. The user is not required to */
255/* be familier with neither Tx nor Rx descriptors. */
256struct pkt_info {
257 unsigned short byte_cnt; /* Descriptor buffer byte count */
258 unsigned short l4i_chk; /* Tx CPU provided TCP Checksum */
259 unsigned int cmd_sts; /* Descriptor command status */
260 dma_addr_t buf_ptr; /* Descriptor buffer pointer */
261 struct sk_buff *return_info; /* User resource return information */
262};
263
c9df406f
LB		 264
265/* global *******************************************************************/
e5371493 266struct mv643xx_eth_shared_private {
cc9754b3 267 void __iomem *base;
c9df406f
LB		 268
269 /* used to protect SMI_REG, which is shared across ports */
270 spinlock_t phy_lock;
271
272 u32 win_protect;
273
274 unsigned int t_clk;
275};
276
277
278/* per-port *****************************************************************/
e5371493 279struct mib_counters {
fbd6a754
LB		 280 u64 good_octets_received;
281 u32 bad_octets_received;
282 u32 internal_mac_transmit_err;
283 u32 good_frames_received;
284 u32 bad_frames_received;
285 u32 broadcast_frames_received;
286 u32 multicast_frames_received;
287 u32 frames_64_octets;
288 u32 frames_65_to_127_octets;
289 u32 frames_128_to_255_octets;
290 u32 frames_256_to_511_octets;
291 u32 frames_512_to_1023_octets;
292 u32 frames_1024_to_max_octets;
293 u64 good_octets_sent;
294 u32 good_frames_sent;
295 u32 excessive_collision;
296 u32 multicast_frames_sent;
297 u32 broadcast_frames_sent;
298 u32 unrec_mac_control_received;
299 u32 fc_sent;
300 u32 good_fc_received;
301 u32 bad_fc_received;
302 u32 undersize_received;
303 u32 fragments_received;
304 u32 oversize_received;
305 u32 jabber_received;
306 u32 mac_receive_error;
307 u32 bad_crc_event;
308 u32 collision;
309 u32 late_collision;
310};
311
e5371493
LB		 312struct mv643xx_eth_private {
313 struct mv643xx_eth_shared_private *shared;
fbd6a754
LB		 314 int port_num; /* User Ethernet port number */
315
e5371493 316 struct mv643xx_eth_shared_private *shared_smi;
ce4e2e45 317
fbd6a754
LB		 318 u32 rx_sram_addr; /* Base address of rx sram area */
319 u32 rx_sram_size; /* Size of rx sram area */
320 u32 tx_sram_addr; /* Base address of tx sram area */
321 u32 tx_sram_size; /* Size of tx sram area */
322
fbd6a754
LB		 323 /* Tx/Rx rings managment indexes fields. For driver use */
324
325 /* Next available and first returning Rx resource */
326 int rx_curr_desc_q, rx_used_desc_q;
327
328 /* Next available and first returning Tx resource */
329 int tx_curr_desc_q, tx_used_desc_q;
330
e5371493 331#ifdef MV643XX_ETH_TX_FAST_REFILL
fbd6a754
LB		 332 u32 tx_clean_threshold;
333#endif
334
cc9754b3 335 struct rx_desc *p_rx_desc_area;
fbd6a754
LB		 336 dma_addr_t rx_desc_dma;
337 int rx_desc_area_size;
338 struct sk_buff **rx_skb;
339
cc9754b3 340 struct tx_desc *p_tx_desc_area;
fbd6a754
LB		 341 dma_addr_t tx_desc_dma;
342 int tx_desc_area_size;
343 struct sk_buff **tx_skb;
344
345 struct work_struct tx_timeout_task;
346
347 struct net_device *dev;
348 struct napi_struct napi;
349 struct net_device_stats stats;
e5371493 350 struct mib_counters mib_counters;
fbd6a754
LB		 351 spinlock_t lock;
352 /* Size of Tx Ring per queue */
353 int tx_ring_size;
354 /* Number of tx descriptors in use */
355 int tx_desc_count;
356 /* Size of Rx Ring per queue */
357 int rx_ring_size;
358 /* Number of rx descriptors in use */
359 int rx_desc_count;
360
361 /*
362 * Used in case RX Ring is empty, which can be caused when
363 * system does not have resources (skb's)
364 */
365 struct timer_list timeout;
366
367 u32 rx_int_coal;
368 u32 tx_int_coal;
369 struct mii_if_info mii;
370};
1da177e4 371
fbd6a754 372
c9df406f 373/* port register accessors **************************************************/
e5371493 374static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
c9df406f 375{
cc9754b3 376 return readl(mp->shared->base + offset);
c9df406f 377}
fbd6a754 378
e5371493 379static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
c9df406f 380{
cc9754b3 381 writel(data, mp->shared->base + offset);
c9df406f 382}
fbd6a754 383
fbd6a754 384
c9df406f 385/* rxq/txq helper functions *************************************************/
e5371493 386static void mv643xx_eth_port_enable_rx(struct mv643xx_eth_private *mp,
c9df406f
LB		 387 unsigned int queues)
388{
3cb4667c 389 wrl(mp, RXQ_COMMAND(mp->port_num), queues);
c9df406f 390}
fbd6a754 391
e5371493 392static unsigned int mv643xx_eth_port_disable_rx(struct mv643xx_eth_private *mp)
c9df406f
LB		 393{
394 unsigned int port_num = mp->port_num;
395 u32 queues;
fbd6a754 396
c9df406f 397 /* Stop Rx port activity. Check port Rx activity. */
3cb4667c 398 queues = rdl(mp, RXQ_COMMAND(port_num)) & 0xFF;
c9df406f
LB		 399 if (queues) {
400 /* Issue stop command for active queues only */
3cb4667c 401 wrl(mp, RXQ_COMMAND(port_num), (queues << 8));
1da177e4 402
c9df406f
LB		 403 /* Wait for all Rx activity to terminate. */
404 /* Check port cause register that all Rx queues are stopped */
3cb4667c 405 while (rdl(mp, RXQ_COMMAND(port_num)) & 0xFF)
e1bea50a 406 udelay(10);
c9df406f 407 }
1da177e4 408
c9df406f
LB		 409 return queues;
410}
411
e5371493 412static void mv643xx_eth_port_enable_tx(struct mv643xx_eth_private *mp,
c9df406f 413 unsigned int queues)
1da177e4 414{
3cb4667c 415 wrl(mp, TXQ_COMMAND(mp->port_num), queues);
1da177e4
LT		 416}
417
e5371493 418static unsigned int mv643xx_eth_port_disable_tx(struct mv643xx_eth_private *mp)
1da177e4 419{
c9df406f
LB		 420 unsigned int port_num = mp->port_num;
421 u32 queues;
422
423 /* Stop Tx port activity. Check port Tx activity. */
3cb4667c 424 queues = rdl(mp, TXQ_COMMAND(port_num)) & 0xFF;
c9df406f
LB		 425 if (queues) {
426 /* Issue stop command for active queues only */
3cb4667c 427 wrl(mp, TXQ_COMMAND(port_num), (queues << 8));
c9df406f
LB		 428
429 /* Wait for all Tx activity to terminate. */
430 /* Check port cause register that all Tx queues are stopped */
3cb4667c 431 while (rdl(mp, TXQ_COMMAND(port_num)) & 0xFF)
e1bea50a 432 udelay(10);
c9df406f
LB		 433
434 /* Wait for Tx FIFO to empty */
a2a41689 435 while (rdl(mp, PORT_STATUS(port_num)) & TX_FIFO_EMPTY)
e1bea50a 436 udelay(10);
c9df406f
LB		 437 }
438
439 return queues;
1da177e4
LT		 440}
441
c9df406f
LB		 442
443/* rx ***********************************************************************/
444static void mv643xx_eth_free_completed_tx_descs(struct net_device *dev);
445
e5371493 446static FUNC_RET_STATUS rx_return_buff(struct mv643xx_eth_private *mp,
c9df406f 447 struct pkt_info *p_pkt_info)
1da177e4 448{
c9df406f 449 int used_rx_desc; /* Where to return Rx resource */
cc9754b3 450 volatile struct rx_desc *p_used_rx_desc;
c9df406f 451 unsigned long flags;
1da177e4 452
c9df406f 453 spin_lock_irqsave(&mp->lock, flags);
c0d0f2ca 454
c9df406f
LB		 455 /* Get 'used' Rx descriptor */
456 used_rx_desc = mp->rx_used_desc_q;
457 p_used_rx_desc = &mp->p_rx_desc_area[used_rx_desc];
1da177e4 458
c9df406f
LB		 459 p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
460 p_used_rx_desc->buf_size = p_pkt_info->byte_cnt;
461 mp->rx_skb[used_rx_desc] = p_pkt_info->return_info;
462
463 /* Flush the write pipe */
464
465 /* Return the descriptor to DMA ownership */
466 wmb();
cc9754b3 467 p_used_rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT;
c9df406f
LB		 468 wmb();
469
470 /* Move the used descriptor pointer to the next descriptor */
471 mp->rx_used_desc_q = (used_rx_desc + 1) % mp->rx_ring_size;
472
c9df406f
LB		 473 spin_unlock_irqrestore(&mp->lock, flags);
474
475 return ETH_OK;
1da177e4
LT		 476}
477
f78fb474 478static void mv643xx_eth_rx_refill_descs(struct net_device *dev)
1da177e4 479{
e5371493 480 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4
LT		 481 struct pkt_info pkt_info;
482 struct sk_buff *skb;
b44cd572 483 int unaligned;
1da177e4 484
f78fb474 485 while (mp->rx_desc_count < mp->rx_ring_size) {
908b637f 486 skb = dev_alloc_skb(ETH_RX_SKB_SIZE + dma_get_cache_alignment());
1da177e4
LT		 487 if (!skb)
488 break;
f98e36f1 489 mp->rx_desc_count++;
908b637f 490 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
b44cd572 491 if (unaligned)
908b637f 492 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
cc9754b3 493 pkt_info.cmd_sts = RX_ENABLE_INTERRUPT;
7303fde8
DF		 494 pkt_info.byte_cnt = ETH_RX_SKB_SIZE;
495 pkt_info.buf_ptr = dma_map_single(NULL, skb->data,
496 ETH_RX_SKB_SIZE, DMA_FROM_DEVICE);
1da177e4 497 pkt_info.return_info = skb;
cc9754b3 498 if (rx_return_buff(mp, &pkt_info) != ETH_OK) {
1da177e4
LT		 499 printk(KERN_ERR
500 "%s: Error allocating RX Ring\n", dev->name);
501 break;
502 }
7303fde8 503 skb_reserve(skb, ETH_HW_IP_ALIGN);
1da177e4 504 }
1da177e4
LT		 505 /*
506 * If RX ring is empty of SKB, set a timer to try allocating
f78fb474 507 * again at a later time.
1da177e4 508 */
f78fb474 509 if (mp->rx_desc_count == 0) {
1da177e4 510 printk(KERN_INFO "%s: Rx ring is empty\n", dev->name);
f78fb474 511 mp->timeout.expires = jiffies + (HZ / 10); /* 100 mSec */
1da177e4 512 add_timer(&mp->timeout);
1da177e4 513 }
1da177e4
LT		 514}
515
f78fb474 516static inline void mv643xx_eth_rx_refill_descs_timer_wrapper(unsigned long data)
1da177e4 517{
f78fb474 518 mv643xx_eth_rx_refill_descs((struct net_device *)data);
1da177e4
LT		 519}
520
e5371493 521static FUNC_RET_STATUS port_receive(struct mv643xx_eth_private *mp,
c9df406f 522 struct pkt_info *p_pkt_info)
1da177e4 523{
c9df406f 524 int rx_next_curr_desc, rx_curr_desc, rx_used_desc;
cc9754b3 525 volatile struct rx_desc *p_rx_desc;
c9df406f
LB		 526 unsigned int command_status;
527 unsigned long flags;
1da177e4 528
c9df406f 529 spin_lock_irqsave(&mp->lock, flags);
1da177e4 530
c9df406f
LB		 531 /* Get the Rx Desc ring 'curr and 'used' indexes */
532 rx_curr_desc = mp->rx_curr_desc_q;
533 rx_used_desc = mp->rx_used_desc_q;
1da177e4 534
c9df406f 535 p_rx_desc = &mp->p_rx_desc_area[rx_curr_desc];
1da177e4 536
c9df406f
LB		 537 /* The following parameters are used to save readings from memory */
538 command_status = p_rx_desc->cmd_sts;
539 rmb();
1da177e4 540
c9df406f 541 /* Nothing to receive... */
cc9754b3 542 if (command_status & BUFFER_OWNED_BY_DMA) {
d344bff9 543 spin_unlock_irqrestore(&mp->lock, flags);
c9df406f
LB		 544 return ETH_END_OF_JOB;
545 }
d344bff9 546
0a6cf74d 547 p_pkt_info->byte_cnt = p_rx_desc->byte_cnt - ETH_HW_IP_ALIGN;
c9df406f 548 p_pkt_info->cmd_sts = command_status;
0a6cf74d 549 p_pkt_info->buf_ptr = p_rx_desc->buf_ptr + ETH_HW_IP_ALIGN;
c9df406f
LB		 550 p_pkt_info->return_info = mp->rx_skb[rx_curr_desc];
551 p_pkt_info->l4i_chk = p_rx_desc->buf_size;
ff561eef 552
c9df406f
LB		 553 /*
554 * Clean the return info field to indicate that the
555 * packet has been moved to the upper layers
556 */
557 mp->rx_skb[rx_curr_desc] = NULL;
1da177e4 558
c9df406f
LB		 559 /* Update current index in data structure */
560 rx_next_curr_desc = (rx_curr_desc + 1) % mp->rx_ring_size;
561 mp->rx_curr_desc_q = rx_next_curr_desc;
1da177e4 562
c9df406f 563 spin_unlock_irqrestore(&mp->lock, flags);
ff561eef 564
c9df406f 565 return ETH_OK;
ff561eef
DF		 566}
567
1da177e4 568static int mv643xx_eth_receive_queue(struct net_device *dev, int budget)
1da177e4 569{
e5371493 570 struct mv643xx_eth_private *mp = netdev_priv(dev);
09f75cd7 571 struct net_device_stats *stats = &dev->stats;
1da177e4
LT		 572 unsigned int received_packets = 0;
573 struct sk_buff *skb;
574 struct pkt_info pkt_info;
575
cc9754b3 576 while (budget-- > 0 && port_receive(mp, &pkt_info) == ETH_OK) {
54caf44d 577 dma_unmap_single(NULL, pkt_info.buf_ptr, ETH_RX_SKB_SIZE,
71d28725 578 DMA_FROM_DEVICE);
f98e36f1 579 mp->rx_desc_count--;
1da177e4 580 received_packets++;
b1dd9ca1 581
468d09f8
DF		 582 /*
583 * Update statistics.
584 * Note byte count includes 4 byte CRC count
585 */
1da177e4
LT		 586 stats->rx_packets++;
587 stats->rx_bytes += pkt_info.byte_cnt;
588 skb = pkt_info.return_info;
589 /*
590 * In case received a packet without first / last bits on OR
591 * the error summary bit is on, the packets needs to be dropeed.
592 */
cc9754b3
LB		 593 if (((pkt_info.cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
594 (RX_FIRST_DESC | RX_LAST_DESC))
595 || (pkt_info.cmd_sts & ERROR_SUMMARY)) {
1da177e4 596 stats->rx_dropped++;
cc9754b3
LB		 597 if ((pkt_info.cmd_sts & (RX_FIRST_DESC |
598 RX_LAST_DESC)) !=
599 (RX_FIRST_DESC | RX_LAST_DESC)) {
1da177e4
LT		 600 if (net_ratelimit())
601 printk(KERN_ERR
602 "%s: Received packet spread "
603 "on multiple descriptors\n",
604 dev->name);
605 }
cc9754b3 606 if (pkt_info.cmd_sts & ERROR_SUMMARY)
1da177e4
LT		 607 stats->rx_errors++;
608
609 dev_kfree_skb_irq(skb);
610 } else {
611 /*
612 * The -4 is for the CRC in the trailer of the
613 * received packet
614 */
615 skb_put(skb, pkt_info.byte_cnt - 4);
1da177e4 616
cc9754b3 617 if (pkt_info.cmd_sts & LAYER_4_CHECKSUM_OK) {
1da177e4
LT		 618 skb->ip_summed = CHECKSUM_UNNECESSARY;
619 skb->csum = htons(
620 (pkt_info.cmd_sts & 0x0007fff8) >> 3);
621 }
622 skb->protocol = eth_type_trans(skb, dev);
e5371493 623#ifdef MV643XX_ETH_NAPI
1da177e4
LT		 624 netif_receive_skb(skb);
625#else
626 netif_rx(skb);
627#endif
628 }
12ad74f8 629 dev->last_rx = jiffies;
1da177e4 630 }
f78fb474 631 mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */
1da177e4
LT		 632
633 return received_packets;
634}
635
e5371493 636#ifdef MV643XX_ETH_NAPI
e5371493 637static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
d0412d96 638{
e5371493 639 struct mv643xx_eth_private *mp = container_of(napi, struct mv643xx_eth_private, napi);
c9df406f
LB		 640 struct net_device *dev = mp->dev;
641 unsigned int port_num = mp->port_num;
642 int work_done;
d0412d96 643
e5371493 644#ifdef MV643XX_ETH_TX_FAST_REFILL
c9df406f
LB		 645 if (++mp->tx_clean_threshold > 5) {
646 mv643xx_eth_free_completed_tx_descs(dev);
647 mp->tx_clean_threshold = 0;
d0412d96 648 }
c9df406f 649#endif
d0412d96 650
c9df406f 651 work_done = 0;
3cb4667c 652 if ((rdl(mp, RXQ_CURRENT_DESC_PTR(port_num)))
c9df406f
LB		 653 != (u32) mp->rx_used_desc_q)
654 work_done = mv643xx_eth_receive_queue(dev, budget);
d0412d96 655
c9df406f
LB		 656 if (work_done < budget) {
657 netif_rx_complete(dev, napi);
3cb4667c
LB		 658 wrl(mp, INT_CAUSE(port_num), 0);
659 wrl(mp, INT_CAUSE_EXT(port_num), 0);
073a345c 660 wrl(mp, INT_MASK(port_num), INT_RX | INT_EXT);
d0412d96 661 }
c9df406f
LB		 662
663 return work_done;
d0412d96 664}
c9df406f 665#endif
d0412d96 666
c9df406f
LB		 667
668/* tx ***********************************************************************/
c9df406f 669static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1da177e4 670{
c9df406f
LB		 671 unsigned int frag;
672 skb_frag_t *fragp;
1da177e4 673
c9df406f
LB		 674 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
675 fragp = &skb_shinfo(skb)->frags[frag];
676 if (fragp->size <= 8 && fragp->page_offset & 0x7)
677 return 1;
1da177e4 678 }
c9df406f
LB		 679 return 0;
680}
7303fde8 681
e5371493 682static int alloc_tx_desc_index(struct mv643xx_eth_private *mp)
c9df406f
LB		 683{
684 int tx_desc_curr;
d0412d96 685
c9df406f 686 BUG_ON(mp->tx_desc_count >= mp->tx_ring_size);
1da177e4 687
c9df406f
LB		 688 tx_desc_curr = mp->tx_curr_desc_q;
689 mp->tx_curr_desc_q = (tx_desc_curr + 1) % mp->tx_ring_size;
e4d00fa9 690
c9df406f 691 BUG_ON(mp->tx_curr_desc_q == mp->tx_used_desc_q);
468d09f8 692
c9df406f
LB		 693 return tx_desc_curr;
694}
468d09f8 695
e5371493 696static void tx_fill_frag_descs(struct mv643xx_eth_private *mp,
c9df406f
LB		 697 struct sk_buff *skb)
698{
699 int frag;
700 int tx_index;
cc9754b3 701 struct tx_desc *desc;
1da177e4 702
c9df406f
LB		 703 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
704 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
705
cc9754b3 706 tx_index = alloc_tx_desc_index(mp);
c9df406f
LB		 707 desc = &mp->p_tx_desc_area[tx_index];
708
cc9754b3 709 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
c9df406f
LB		 710 /* Last Frag enables interrupt and frees the skb */
711 if (frag == (skb_shinfo(skb)->nr_frags - 1)) {
cc9754b3
LB		 712 desc->cmd_sts |= ZERO_PADDING |
713 TX_LAST_DESC |
714 TX_ENABLE_INTERRUPT;
c9df406f
LB		 715 mp->tx_skb[tx_index] = skb;
716 } else
717 mp->tx_skb[tx_index] = NULL;
718
719 desc = &mp->p_tx_desc_area[tx_index];
720 desc->l4i_chk = 0;
721 desc->byte_cnt = this_frag->size;
722 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
723 this_frag->page_offset,
724 this_frag->size,
725 DMA_TO_DEVICE);
726 }
1da177e4
LT		 727}
728
c9df406f
LB		 729static inline __be16 sum16_as_be(__sum16 sum)
730{
731 return (__force __be16)sum;
732}
1da177e4 733
e5371493 734static void tx_submit_descs_for_skb(struct mv643xx_eth_private *mp,
c9df406f 735 struct sk_buff *skb)
1da177e4 736{
c9df406f 737 int tx_index;
cc9754b3 738 struct tx_desc *desc;
c9df406f
LB		 739 u32 cmd_sts;
740 int length;
741 int nr_frags = skb_shinfo(skb)->nr_frags;
1da177e4 742
cc9754b3 743 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
1da177e4 744
cc9754b3 745 tx_index = alloc_tx_desc_index(mp);
c9df406f
LB		 746 desc = &mp->p_tx_desc_area[tx_index];
747
748 if (nr_frags) {
cc9754b3 749 tx_fill_frag_descs(mp, skb);
c9df406f
LB		 750
751 length = skb_headlen(skb);
752 mp->tx_skb[tx_index] = NULL;
753 } else {
cc9754b3 754 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
c9df406f
LB		 755 length = skb->len;
756 mp->tx_skb[tx_index] = skb;
757 }
758
759 desc->byte_cnt = length;
760 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
761
762 if (skb->ip_summed == CHECKSUM_PARTIAL) {
763 BUG_ON(skb->protocol != htons(ETH_P_IP));
764
cc9754b3
LB		 765 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
766 GEN_IP_V4_CHECKSUM |
767 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
c9df406f
LB		 768
769 switch (ip_hdr(skb)->protocol) {
770 case IPPROTO_UDP:
cc9754b3 771 cmd_sts |= UDP_FRAME;
c9df406f
LB		 772 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
773 break;
774 case IPPROTO_TCP:
775 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
776 break;
777 default:
778 BUG();
779 }
780 } else {
781 /* Errata BTS #50, IHL must be 5 if no HW checksum */
cc9754b3 782 cmd_sts |= 5 << TX_IHL_SHIFT;
c9df406f
LB		 783 desc->l4i_chk = 0;
784 }
785
786 /* ensure all other descriptors are written before first cmd_sts */
787 wmb();
788 desc->cmd_sts = cmd_sts;
789
790 /* ensure all descriptors are written before poking hardware */
791 wmb();
073a345c 792 mv643xx_eth_port_enable_tx(mp, 1);
c9df406f
LB		 793
794 mp->tx_desc_count += nr_frags + 1;
1da177e4 795}
1da177e4 796
c9df406f 797static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 798{
e5371493 799 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f
LB		 800 struct net_device_stats *stats = &dev->stats;
801 unsigned long flags;
afdb57a2 802
c9df406f 803 BUG_ON(netif_queue_stopped(dev));
afdb57a2 804
c9df406f
LB		 805 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
806 stats->tx_dropped++;
807 printk(KERN_DEBUG "%s: failed to linearize tiny "
808 "unaligned fragment\n", dev->name);
809 return NETDEV_TX_BUSY;
810 }
811
812 spin_lock_irqsave(&mp->lock, flags);
813
814 if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB) {
815 printk(KERN_ERR "%s: transmit with queue full\n", dev->name);
816 netif_stop_queue(dev);
817 spin_unlock_irqrestore(&mp->lock, flags);
818 return NETDEV_TX_BUSY;
819 }
820
cc9754b3 821 tx_submit_descs_for_skb(mp, skb);
c9df406f
LB		 822 stats->tx_bytes += skb->len;
823 stats->tx_packets++;
824 dev->trans_start = jiffies;
825
826 if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB)
827 netif_stop_queue(dev);
828
829 spin_unlock_irqrestore(&mp->lock, flags);
830
831 return NETDEV_TX_OK;
1da177e4
LT		 832}
833
c9df406f
LB		 834
835/* mii management interface *************************************************/
e5371493 836static int phy_addr_get(struct mv643xx_eth_private *mp);
c9df406f 837
e5371493 838static void read_smi_reg(struct mv643xx_eth_private *mp,
c9df406f 839 unsigned int phy_reg, unsigned int *value)
1da177e4 840{
cc9754b3
LB		 841 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
842 int phy_addr = phy_addr_get(mp);
c9df406f 843 unsigned long flags;
1da177e4
LT		 844 int i;
845
c9df406f
LB		 846 /* the SMI register is a shared resource */
847 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
848
849 /* wait for the SMI register to become available */
cc9754b3 850 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
e1bea50a 851 if (i == 1000) {
c9df406f
LB		 852 printk("%s: PHY busy timeout\n", mp->dev->name);
853 goto out;
854 }
e1bea50a 855 udelay(10);
1da177e4
LT		 856 }
857
cc9754b3 858 writel((phy_addr << 16) | (phy_reg << 21) | SMI_OPCODE_READ, smi_reg);
1da177e4 859
c9df406f 860 /* now wait for the data to be valid */
cc9754b3 861 for (i = 0; !(readl(smi_reg) & SMI_READ_VALID); i++) {
e1bea50a 862 if (i == 1000) {
c9df406f
LB		 863 printk("%s: PHY read timeout\n", mp->dev->name);
864 goto out;
865 }
e1bea50a 866 udelay(10);
c9df406f
LB		 867 }
868
869 *value = readl(smi_reg) & 0xffff;
870out:
871 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
1da177e4
LT		 872}
873
e5371493 874static void write_smi_reg(struct mv643xx_eth_private *mp,
c9df406f 875 unsigned int phy_reg, unsigned int value)
1da177e4 876{
cc9754b3
LB		 877 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
878 int phy_addr = phy_addr_get(mp);
c9df406f 879 unsigned long flags;
1da177e4
LT		 880 int i;
881
c9df406f
LB		 882 /* the SMI register is a shared resource */
883 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
884
885 /* wait for the SMI register to become available */
cc9754b3 886 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
e1bea50a 887 if (i == 1000) {
c9df406f
LB		 888 printk("%s: PHY busy timeout\n", mp->dev->name);
889 goto out;
890 }
e1bea50a 891 udelay(10);
1da177e4
LT		 892 }
893
c9df406f 894 writel((phy_addr << 16) | (phy_reg << 21) |
cc9754b3 895 SMI_OPCODE_WRITE | (value & 0xffff), smi_reg);
c9df406f
LB		 896out:
897 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
898}
1da177e4 899
c9df406f
LB		 900
901/* mib counters *************************************************************/
e5371493 902static void clear_mib_counters(struct mv643xx_eth_private *mp)
c9df406f
LB		 903{
904 unsigned int port_num = mp->port_num;
905 int i;
906
907 /* Perform dummy reads from MIB counters */
4b8e3655 908 for (i = 0; i < 0x80; i += 4)
3cb4667c 909 rdl(mp, MIB_COUNTERS(port_num) + i);
1da177e4
LT		 910}
911
e5371493 912static inline u32 read_mib(struct mv643xx_eth_private *mp, int offset)
d0412d96 913{
3cb4667c 914 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
c9df406f 915}
d0412d96 916
e5371493 917static void update_mib_counters(struct mv643xx_eth_private *mp)
c9df406f 918{
e5371493 919 struct mib_counters *p = &mp->mib_counters;
4b8e3655
LB		 920
921 p->good_octets_received += read_mib(mp, 0x00);
922 p->good_octets_received += (u64)read_mib(mp, 0x04) << 32;
923 p->bad_octets_received += read_mib(mp, 0x08);
924 p->internal_mac_transmit_err += read_mib(mp, 0x0c);
925 p->good_frames_received += read_mib(mp, 0x10);
926 p->bad_frames_received += read_mib(mp, 0x14);
927 p->broadcast_frames_received += read_mib(mp, 0x18);
928 p->multicast_frames_received += read_mib(mp, 0x1c);
929 p->frames_64_octets += read_mib(mp, 0x20);
930 p->frames_65_to_127_octets += read_mib(mp, 0x24);
931 p->frames_128_to_255_octets += read_mib(mp, 0x28);
932 p->frames_256_to_511_octets += read_mib(mp, 0x2c);
933 p->frames_512_to_1023_octets += read_mib(mp, 0x30);
934 p->frames_1024_to_max_octets += read_mib(mp, 0x34);
935 p->good_octets_sent += read_mib(mp, 0x38);
936 p->good_octets_sent += (u64)read_mib(mp, 0x3c) << 32;
937 p->good_frames_sent += read_mib(mp, 0x40);
938 p->excessive_collision += read_mib(mp, 0x44);
939 p->multicast_frames_sent += read_mib(mp, 0x48);
940 p->broadcast_frames_sent += read_mib(mp, 0x4c);
941 p->unrec_mac_control_received += read_mib(mp, 0x50);
942 p->fc_sent += read_mib(mp, 0x54);
943 p->good_fc_received += read_mib(mp, 0x58);
944 p->bad_fc_received += read_mib(mp, 0x5c);
945 p->undersize_received += read_mib(mp, 0x60);
946 p->fragments_received += read_mib(mp, 0x64);
947 p->oversize_received += read_mib(mp, 0x68);
948 p->jabber_received += read_mib(mp, 0x6c);
949 p->mac_receive_error += read_mib(mp, 0x70);
950 p->bad_crc_event += read_mib(mp, 0x74);
951 p->collision += read_mib(mp, 0x78);
952 p->late_collision += read_mib(mp, 0x7c);
d0412d96
JC		 953}
954
c9df406f
LB		 955
956/* ethtool ******************************************************************/
e5371493 957struct mv643xx_eth_stats {
c9df406f
LB		 958 char stat_string[ETH_GSTRING_LEN];
959 int sizeof_stat;
960 int stat_offset;
961};
962
e5371493
LB		 963#define MV643XX_ETH_STAT(m) FIELD_SIZEOF(struct mv643xx_eth_private, m), \
964 offsetof(struct mv643xx_eth_private, m)
965
966static const struct mv643xx_eth_stats mv643xx_eth_gstrings_stats[] = {
967 { "rx_packets", MV643XX_ETH_STAT(stats.rx_packets) },
968 { "tx_packets", MV643XX_ETH_STAT(stats.tx_packets) },
969 { "rx_bytes", MV643XX_ETH_STAT(stats.rx_bytes) },
970 { "tx_bytes", MV643XX_ETH_STAT(stats.tx_bytes) },
971 { "rx_errors", MV643XX_ETH_STAT(stats.rx_errors) },
972 { "tx_errors", MV643XX_ETH_STAT(stats.tx_errors) },
973 { "rx_dropped", MV643XX_ETH_STAT(stats.rx_dropped) },
974 { "tx_dropped", MV643XX_ETH_STAT(stats.tx_dropped) },
975 { "good_octets_received", MV643XX_ETH_STAT(mib_counters.good_octets_received) },
976 { "bad_octets_received", MV643XX_ETH_STAT(mib_counters.bad_octets_received) },
977 { "internal_mac_transmit_err", MV643XX_ETH_STAT(mib_counters.internal_mac_transmit_err) },
978 { "good_frames_received", MV643XX_ETH_STAT(mib_counters.good_frames_received) },
979 { "bad_frames_received", MV643XX_ETH_STAT(mib_counters.bad_frames_received) },
980 { "broadcast_frames_received", MV643XX_ETH_STAT(mib_counters.broadcast_frames_received) },
981 { "multicast_frames_received", MV643XX_ETH_STAT(mib_counters.multicast_frames_received) },
982 { "frames_64_octets", MV643XX_ETH_STAT(mib_counters.frames_64_octets) },
983 { "frames_65_to_127_octets", MV643XX_ETH_STAT(mib_counters.frames_65_to_127_octets) },
984 { "frames_128_to_255_octets", MV643XX_ETH_STAT(mib_counters.frames_128_to_255_octets) },
985 { "frames_256_to_511_octets", MV643XX_ETH_STAT(mib_counters.frames_256_to_511_octets) },
986 { "frames_512_to_1023_octets", MV643XX_ETH_STAT(mib_counters.frames_512_to_1023_octets) },
987 { "frames_1024_to_max_octets", MV643XX_ETH_STAT(mib_counters.frames_1024_to_max_octets) },
988 { "good_octets_sent", MV643XX_ETH_STAT(mib_counters.good_octets_sent) },
989 { "good_frames_sent", MV643XX_ETH_STAT(mib_counters.good_frames_sent) },
990 { "excessive_collision", MV643XX_ETH_STAT(mib_counters.excessive_collision) },
991 { "multicast_frames_sent", MV643XX_ETH_STAT(mib_counters.multicast_frames_sent) },
992 { "broadcast_frames_sent", MV643XX_ETH_STAT(mib_counters.broadcast_frames_sent) },
993 { "unrec_mac_control_received", MV643XX_ETH_STAT(mib_counters.unrec_mac_control_received) },
994 { "fc_sent", MV643XX_ETH_STAT(mib_counters.fc_sent) },
995 { "good_fc_received", MV643XX_ETH_STAT(mib_counters.good_fc_received) },
996 { "bad_fc_received", MV643XX_ETH_STAT(mib_counters.bad_fc_received) },
997 { "undersize_received", MV643XX_ETH_STAT(mib_counters.undersize_received) },
998 { "fragments_received", MV643XX_ETH_STAT(mib_counters.fragments_received) },
999 { "oversize_received", MV643XX_ETH_STAT(mib_counters.oversize_received) },
1000 { "jabber_received", MV643XX_ETH_STAT(mib_counters.jabber_received) },
1001 { "mac_receive_error", MV643XX_ETH_STAT(mib_counters.mac_receive_error) },
1002 { "bad_crc_event", MV643XX_ETH_STAT(mib_counters.bad_crc_event) },
1003 { "collision", MV643XX_ETH_STAT(mib_counters.collision) },
1004 { "late_collision", MV643XX_ETH_STAT(mib_counters.late_collision) },
c9df406f
LB		 1005};
1006
e5371493 1007#define MV643XX_ETH_STATS_LEN ARRAY_SIZE(mv643xx_eth_gstrings_stats)
c9df406f 1008
e5371493 1009static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
d0412d96 1010{
e5371493 1011 struct mv643xx_eth_private *mp = netdev_priv(dev);
d0412d96
JC		 1012 int err;
1013
1014 spin_lock_irq(&mp->lock);
1015 err = mii_ethtool_gset(&mp->mii, cmd);
1016 spin_unlock_irq(&mp->lock);
1017
1018 /* The PHY may support 1000baseT_Half, but the mv643xx does not */
1019 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1020 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1021
1022 return err;
1023}
1024
e5371493 1025static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4 1026{
e5371493 1027 struct mv643xx_eth_private *mp = netdev_priv(dev);
ab4384a6
DF		 1028 int err;
1029
c9df406f
LB		 1030 spin_lock_irq(&mp->lock);
1031 err = mii_ethtool_sset(&mp->mii, cmd);
1032 spin_unlock_irq(&mp->lock);
85cf572c 1033
c9df406f
LB		 1034 return err;
1035}
1da177e4 1036
e5371493 1037static void mv643xx_eth_get_drvinfo(struct net_device *netdev,
c9df406f
LB		 1038 struct ethtool_drvinfo *drvinfo)
1039{
e5371493
LB		 1040 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1041 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
c9df406f
LB		 1042 strncpy(drvinfo->fw_version, "N/A", 32);
1043 strncpy(drvinfo->bus_info, "mv643xx", 32);
e5371493 1044 drvinfo->n_stats = MV643XX_ETH_STATS_LEN;
c9df406f 1045}
1da177e4 1046
c9df406f
LB		 1047static int mv643xx_eth_nway_restart(struct net_device *dev)
1048{
e5371493 1049 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1050
c9df406f
LB		 1051 return mii_nway_restart(&mp->mii);
1052}
1da177e4 1053
c9df406f
LB		 1054static u32 mv643xx_eth_get_link(struct net_device *dev)
1055{
e5371493 1056 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1057
c9df406f
LB		 1058 return mii_link_ok(&mp->mii);
1059}
1da177e4 1060
e5371493 1061static void mv643xx_eth_get_strings(struct net_device *netdev, uint32_t stringset,
c9df406f
LB		 1062 uint8_t *data)
1063{
1064 int i;
1da177e4 1065
c9df406f
LB		 1066 switch(stringset) {
1067 case ETH_SS_STATS:
e5371493 1068 for (i=0; i < MV643XX_ETH_STATS_LEN; i++) {
c9df406f 1069 memcpy(data + i * ETH_GSTRING_LEN,
e5371493
LB		 1070 mv643xx_eth_gstrings_stats[i].stat_string,
1071 ETH_GSTRING_LEN);
c9df406f
LB		 1072 }
1073 break;
1074 }
1075}
1da177e4 1076
e5371493 1077static void mv643xx_eth_get_ethtool_stats(struct net_device *netdev,
c9df406f
LB		 1078 struct ethtool_stats *stats, uint64_t *data)
1079{
e5371493 1080 struct mv643xx_eth_private *mp = netdev->priv;
c9df406f 1081 int i;
1da177e4 1082
cc9754b3 1083 update_mib_counters(mp);
1da177e4 1084
e5371493
LB		 1085 for (i = 0; i < MV643XX_ETH_STATS_LEN; i++) {
1086 char *p = (char *)mp+mv643xx_eth_gstrings_stats[i].stat_offset;
1087 data[i] = (mv643xx_eth_gstrings_stats[i].sizeof_stat ==
c9df406f 1088 sizeof(uint64_t)) ? *(uint64_t *)p : *(uint32_t *)p;
1da177e4 1089 }
c9df406f 1090}
1da177e4 1091
e5371493 1092static int mv643xx_eth_get_sset_count(struct net_device *netdev, int sset)
c9df406f
LB		 1093{
1094 switch (sset) {
1095 case ETH_SS_STATS:
e5371493 1096 return MV643XX_ETH_STATS_LEN;
c9df406f
LB		 1097 default:
1098 return -EOPNOTSUPP;
1099 }
1100}
1da177e4 1101
e5371493
LB		 1102static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1103 .get_settings = mv643xx_eth_get_settings,
1104 .set_settings = mv643xx_eth_set_settings,
1105 .get_drvinfo = mv643xx_eth_get_drvinfo,
c9df406f
LB		 1106 .get_link = mv643xx_eth_get_link,
1107 .set_sg = ethtool_op_set_sg,
e5371493
LB		 1108 .get_sset_count = mv643xx_eth_get_sset_count,
1109 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1110 .get_strings = mv643xx_eth_get_strings,
c9df406f
LB		 1111 .nway_reset = mv643xx_eth_nway_restart,
1112};
1da177e4 1113
bea3348e 1114
c9df406f 1115/* address handling *********************************************************/
e5371493 1116static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *p_addr)
c9df406f
LB		 1117{
1118 unsigned int port_num = mp->port_num;
1119 unsigned int mac_h;
1120 unsigned int mac_l;
1da177e4 1121
c9df406f
LB		 1122 mac_h = rdl(mp, MAC_ADDR_HIGH(port_num));
1123 mac_l = rdl(mp, MAC_ADDR_LOW(port_num));
1da177e4 1124
c9df406f
LB		 1125 p_addr[0] = (mac_h >> 24) & 0xff;
1126 p_addr[1] = (mac_h >> 16) & 0xff;
1127 p_addr[2] = (mac_h >> 8) & 0xff;
1128 p_addr[3] = mac_h & 0xff;
1129 p_addr[4] = (mac_l >> 8) & 0xff;
1130 p_addr[5] = mac_l & 0xff;
1131}
1da177e4 1132
e5371493 1133static void init_mac_tables(struct mv643xx_eth_private *mp)
c9df406f
LB		 1134{
1135 unsigned int port_num = mp->port_num;
1136 int table_index;
1da177e4 1137
c9df406f
LB		 1138 /* Clear DA filter unicast table (Ex_dFUT) */
1139 for (table_index = 0; table_index <= 0xC; table_index += 4)
3cb4667c 1140 wrl(mp, UNICAST_TABLE(port_num) + table_index, 0);
1da177e4 1141
c9df406f
LB		 1142 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
1143 /* Clear DA filter special multicast table (Ex_dFSMT) */
3cb4667c 1144 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + table_index, 0);
c9df406f 1145 /* Clear DA filter other multicast table (Ex_dFOMT) */
3cb4667c 1146 wrl(mp, OTHER_MCAST_TABLE(port_num) + table_index, 0);
c9df406f
LB		 1147 }
1148}
d0412d96 1149
e5371493 1150static void set_filter_table_entry(struct mv643xx_eth_private *mp,
c9df406f
LB		 1151 int table, unsigned char entry)
1152{
1153 unsigned int table_reg;
1154 unsigned int tbl_offset;
1155 unsigned int reg_offset;
ab4384a6 1156
c9df406f
LB		 1157 tbl_offset = (entry / 4) * 4; /* Register offset of DA table entry */
1158 reg_offset = entry % 4; /* Entry offset within the register */
ab4384a6 1159
c9df406f
LB		 1160 /* Set "accepts frame bit" at specified table entry */
1161 table_reg = rdl(mp, table + tbl_offset);
1162 table_reg |= 0x01 << (8 * reg_offset);
1163 wrl(mp, table + tbl_offset, table_reg);
1da177e4
LT		 1164}
1165
e5371493 1166static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *p_addr)
1da177e4 1167{
c9df406f
LB		 1168 unsigned int port_num = mp->port_num;
1169 unsigned int mac_h;
1170 unsigned int mac_l;
1171 int table;
1da177e4 1172
c9df406f
LB		 1173 mac_l = (p_addr[4] << 8) | (p_addr[5]);
1174 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
1175 (p_addr[3] << 0);
ff561eef 1176
c9df406f
LB		 1177 wrl(mp, MAC_ADDR_LOW(port_num), mac_l);
1178 wrl(mp, MAC_ADDR_HIGH(port_num), mac_h);
1da177e4 1179
c9df406f 1180 /* Accept frames with this address */
3cb4667c 1181 table = UNICAST_TABLE(port_num);
cc9754b3 1182 set_filter_table_entry(mp, table, p_addr[5] & 0x0f);
1da177e4
LT		 1183}
1184
c9df406f 1185static void mv643xx_eth_update_mac_address(struct net_device *dev)
1da177e4 1186{
e5371493 1187 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1188
cc9754b3
LB		 1189 init_mac_tables(mp);
1190 uc_addr_set(mp, dev->dev_addr);
c9df406f 1191}
1da177e4 1192
c9df406f 1193static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1da177e4 1194{
c9df406f 1195 int i;
1da177e4 1196
c9df406f
LB		 1197 for (i = 0; i < 6; i++)
1198 /* +2 is for the offset of the HW addr type */
1199 dev->dev_addr[i] = ((unsigned char *)addr)[i + 2];
1200 mv643xx_eth_update_mac_address(dev);
1da177e4
LT		 1201 return 0;
1202}
1203
e5371493 1204static void mc_addr(struct mv643xx_eth_private *mp, unsigned char *p_addr)
1da177e4 1205{
1da177e4 1206 unsigned int port_num = mp->port_num;
c9df406f
LB		 1207 unsigned int mac_h;
1208 unsigned int mac_l;
1209 unsigned char crc_result = 0;
1210 int table;
1211 int mac_array[48];
1212 int crc[8];
1213 int i;
1da177e4 1214
c9df406f
LB		 1215 if ((p_addr[0] == 0x01) && (p_addr[1] == 0x00) &&
1216 (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) {
3cb4667c 1217 table = SPECIAL_MCAST_TABLE(port_num);
cc9754b3 1218 set_filter_table_entry(mp, table, p_addr[5]);
c9df406f 1219 return;
1da177e4 1220 }
1da177e4 1221
c9df406f
LB		 1222 /* Calculate CRC-8 out of the given address */
1223 mac_h = (p_addr[0] << 8) | (p_addr[1]);
1224 mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
1225 (p_addr[4] << 8) | (p_addr[5] << 0);
1da177e4 1226
c9df406f
LB		 1227 for (i = 0; i < 32; i++)
1228 mac_array[i] = (mac_l >> i) & 0x1;
1229 for (i = 32; i < 48; i++)
1230 mac_array[i] = (mac_h >> (i - 32)) & 0x1;
1da177e4 1231
c9df406f
LB		 1232 crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ mac_array[39] ^
1233 mac_array[35] ^ mac_array[34] ^ mac_array[31] ^ mac_array[30] ^
1234 mac_array[28] ^ mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
1235 mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ mac_array[12] ^
1236 mac_array[8] ^ mac_array[7] ^ mac_array[6] ^ mac_array[0];
1da177e4 1237
c9df406f
LB		 1238 crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
1239 mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ mac_array[34] ^
1240 mac_array[32] ^ mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
1241 mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ mac_array[21] ^
1242 mac_array[20] ^ mac_array[18] ^ mac_array[17] ^ mac_array[16] ^
1243 mac_array[15] ^ mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
1244 mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ mac_array[0];
f7ea3337 1245
c9df406f
LB		 1246 crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ mac_array[43] ^
1247 mac_array[42] ^ mac_array[39] ^ mac_array[37] ^ mac_array[34] ^
1248 mac_array[33] ^ mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
1249 mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ mac_array[15] ^
1250 mac_array[13] ^ mac_array[12] ^ mac_array[10] ^ mac_array[8] ^
1251 mac_array[6] ^ mac_array[2] ^ mac_array[1] ^ mac_array[0];
f7ea3337 1252
c9df406f
LB		 1253 crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
1254 mac_array[40] ^ mac_array[38] ^ mac_array[35] ^ mac_array[34] ^
1255 mac_array[30] ^ mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
1256 mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
1257 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[7] ^
1258 mac_array[3] ^ mac_array[2] ^ mac_array[1];
f7ea3337 1259
c9df406f
LB		 1260 crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[41] ^
1261 mac_array[39] ^ mac_array[36] ^ mac_array[35] ^ mac_array[31] ^
1262 mac_array[30] ^ mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
1263 mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ mac_array[14] ^
1264 mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ mac_array[4] ^
1265 mac_array[3] ^ mac_array[2];
c8aaea25 1266
c9df406f
LB		 1267 crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ mac_array[42] ^
1268 mac_array[40] ^ mac_array[37] ^ mac_array[36] ^ mac_array[32] ^
1269 mac_array[31] ^ mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
1270 mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ mac_array[15] ^
1271 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[5] ^
1272 mac_array[4] ^ mac_array[3];
c8aaea25 1273
c9df406f
LB		 1274 crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ mac_array[41] ^
1275 mac_array[38] ^ mac_array[37] ^ mac_array[33] ^ mac_array[32] ^
1276 mac_array[29] ^ mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
1277 mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ mac_array[14] ^
1278 mac_array[12] ^ mac_array[10] ^ mac_array[6] ^ mac_array[5] ^
1279 mac_array[4];
c8aaea25 1280
c9df406f
LB		 1281 crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ mac_array[39] ^
1282 mac_array[38] ^ mac_array[34] ^ mac_array[33] ^ mac_array[30] ^
1283 mac_array[29] ^ mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
1284 mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ mac_array[13] ^
1285 mac_array[11] ^ mac_array[7] ^ mac_array[6] ^ mac_array[5];
c8aaea25 1286
c9df406f
LB		 1287 for (i = 0; i < 8; i++)
1288 crc_result = crc_result | (crc[i] << i);
1289
3cb4667c 1290 table = OTHER_MCAST_TABLE(port_num);
cc9754b3 1291 set_filter_table_entry(mp, table, crc_result);
c8aaea25
DF		 1292}
1293
cc9754b3 1294static void set_multicast_list(struct net_device *dev)
1da177e4 1295{
1da177e4 1296
c9df406f
LB		 1297 struct dev_mc_list *mc_list;
1298 int i;
1299 int table_index;
e5371493 1300 struct mv643xx_eth_private *mp = netdev_priv(dev);
cc9754b3 1301 unsigned int port_num = mp->port_num;
c8aaea25 1302
c9df406f
LB		 1303 /* If the device is in promiscuous mode or in all multicast mode,
1304 * we will fully populate both multicast tables with accept.
1305 * This is guaranteed to yield a match on all multicast addresses...
1306 */
1307 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) {
1308 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
1309 /* Set all entries in DA filter special multicast
1310 * table (Ex_dFSMT)
1311 * Set for ETH_Q0 for now
1312 * Bits
1313 * 0 Accept=1, Drop=0
1314 * 3-1 Queue ETH_Q0=0
1315 * 7-4 Reserved = 0;
1316 */
cc9754b3 1317 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + table_index, 0x01010101);
c8aaea25 1318
c9df406f
LB		 1319 /* Set all entries in DA filter other multicast
1320 * table (Ex_dFOMT)
1321 * Set for ETH_Q0 for now
1322 * Bits
1323 * 0 Accept=1, Drop=0
1324 * 3-1 Queue ETH_Q0=0
1325 * 7-4 Reserved = 0;
1326 */
cc9754b3 1327 wrl(mp, OTHER_MCAST_TABLE(port_num) + table_index, 0x01010101);
c9df406f
LB		 1328 }
1329 return;
1330 }
c8aaea25 1331
c9df406f
LB		 1332 /* We will clear out multicast tables every time we get the list.
1333 * Then add the entire new list...
1334 */
1335 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
1336 /* Clear DA filter special multicast table (Ex_dFSMT) */
cc9754b3 1337 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + table_index, 0);
c9df406f
LB		 1338
1339 /* Clear DA filter other multicast table (Ex_dFOMT) */
cc9754b3 1340 wrl(mp, OTHER_MCAST_TABLE(port_num) + table_index, 0);
1da177e4
LT		 1341 }
1342
c9df406f
LB		 1343 /* Get pointer to net_device multicast list and add each one... */
1344 for (i = 0, mc_list = dev->mc_list;
1345 (i < 256) && (mc_list != NULL) && (i < dev->mc_count);
1346 i++, mc_list = mc_list->next)
1347 if (mc_list->dmi_addrlen == 6)
cc9754b3 1348 mc_addr(mp, mc_list->dmi_addr);
324ff2c1
BB		 1349}
1350
c9df406f 1351static void mv643xx_eth_set_rx_mode(struct net_device *dev)
c8aaea25 1352{
e5371493 1353 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 1354 u32 config_reg;
1da177e4 1355
3cb4667c 1356 config_reg = rdl(mp, PORT_CONFIG(mp->port_num));
c9df406f 1357 if (dev->flags & IFF_PROMISC)
d9a073ea 1358 config_reg |= UNICAST_PROMISCUOUS_MODE;
c9df406f 1359 else
d9a073ea 1360 config_reg &= ~UNICAST_PROMISCUOUS_MODE;
3cb4667c 1361 wrl(mp, PORT_CONFIG(mp->port_num), config_reg);
1da177e4 1362
cc9754b3 1363 set_multicast_list(dev);
c9df406f 1364}
c8aaea25 1365
c8aaea25 1366
c9df406f 1367/* rx/tx queue initialisation ***********************************************/
e5371493 1368static void ether_init_rx_desc_ring(struct mv643xx_eth_private *mp)
c9df406f 1369{
cc9754b3 1370 volatile struct rx_desc *p_rx_desc;
c9df406f
LB		 1371 int rx_desc_num = mp->rx_ring_size;
1372 int i;
1373
1374 /* initialize the next_desc_ptr links in the Rx descriptors ring */
cc9754b3 1375 p_rx_desc = (struct rx_desc *)mp->p_rx_desc_area;
c9df406f
LB		 1376 for (i = 0; i < rx_desc_num; i++) {
1377 p_rx_desc[i].next_desc_ptr = mp->rx_desc_dma +
cc9754b3 1378 ((i + 1) % rx_desc_num) * sizeof(struct rx_desc);
f7ea3337
PJ		 1379 }
1380
c9df406f
LB		 1381 /* Save Rx desc pointer to driver struct. */
1382 mp->rx_curr_desc_q = 0;
1383 mp->rx_used_desc_q = 0;
1da177e4 1384
cc9754b3 1385 mp->rx_desc_area_size = rx_desc_num * sizeof(struct rx_desc);
c9df406f 1386}
c8aaea25 1387
c9df406f
LB		 1388static void mv643xx_eth_free_rx_rings(struct net_device *dev)
1389{
e5371493 1390 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 1391 int curr;
c8aaea25 1392
c9df406f
LB		 1393 /* Stop RX Queues */
1394 mv643xx_eth_port_disable_rx(mp);
1395
1396 /* Free preallocated skb's on RX rings */
1397 for (curr = 0; mp->rx_desc_count && curr < mp->rx_ring_size; curr++) {
1398 if (mp->rx_skb[curr]) {
1399 dev_kfree_skb(mp->rx_skb[curr]);
1400 mp->rx_desc_count--;
1da177e4 1401 }
c8aaea25 1402 }
1da177e4 1403
c9df406f
LB		 1404 if (mp->rx_desc_count)
1405 printk(KERN_ERR
1406 "%s: Error in freeing Rx Ring. %d skb's still"
1407 " stuck in RX Ring - ignoring them\n", dev->name,
1408 mp->rx_desc_count);
1409 /* Free RX ring */
1410 if (mp->rx_sram_size)
1411 iounmap(mp->p_rx_desc_area);
1412 else
1413 dma_free_coherent(NULL, mp->rx_desc_area_size,
1414 mp->p_rx_desc_area, mp->rx_desc_dma);
1415}
1da177e4 1416
e5371493 1417static void ether_init_tx_desc_ring(struct mv643xx_eth_private *mp)
c9df406f
LB		 1418{
1419 int tx_desc_num = mp->tx_ring_size;
cc9754b3 1420 struct tx_desc *p_tx_desc;
c9df406f 1421 int i;
1da177e4 1422
c9df406f 1423 /* Initialize the next_desc_ptr links in the Tx descriptors ring */
cc9754b3 1424 p_tx_desc = (struct tx_desc *)mp->p_tx_desc_area;
c9df406f
LB		 1425 for (i = 0; i < tx_desc_num; i++) {
1426 p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma +
cc9754b3 1427 ((i + 1) % tx_desc_num) * sizeof(struct tx_desc);
c9df406f
LB		 1428 }
1429
1430 mp->tx_curr_desc_q = 0;
1431 mp->tx_used_desc_q = 0;
1432
cc9754b3 1433 mp->tx_desc_area_size = tx_desc_num * sizeof(struct tx_desc);
c8aaea25 1434}
1da177e4 1435
c9df406f 1436static int mv643xx_eth_free_tx_descs(struct net_device *dev, int force)
c8aaea25 1437{
e5371493 1438 struct mv643xx_eth_private *mp = netdev_priv(dev);
cc9754b3 1439 struct tx_desc *desc;
c9df406f
LB		 1440 u32 cmd_sts;
1441 struct sk_buff *skb;
c8aaea25 1442 unsigned long flags;
c9df406f
LB		 1443 int tx_index;
1444 dma_addr_t addr;
1445 int count;
1446 int released = 0;
1da177e4 1447
c9df406f
LB		 1448 while (mp->tx_desc_count > 0) {
1449 spin_lock_irqsave(&mp->lock, flags);
94843566 1450
c9df406f
LB		 1451 /* tx_desc_count might have changed before acquiring the lock */
1452 if (mp->tx_desc_count <= 0) {
1453 spin_unlock_irqrestore(&mp->lock, flags);
1454 return released;
1455 }
4d64e718 1456
c9df406f
LB		 1457 tx_index = mp->tx_used_desc_q;
1458 desc = &mp->p_tx_desc_area[tx_index];
1459 cmd_sts = desc->cmd_sts;
4d64e718 1460
cc9754b3 1461 if (!force && (cmd_sts & BUFFER_OWNED_BY_DMA)) {
c9df406f
LB		 1462 spin_unlock_irqrestore(&mp->lock, flags);
1463 return released;
1464 }
1da177e4 1465
c9df406f
LB		 1466 mp->tx_used_desc_q = (tx_index + 1) % mp->tx_ring_size;
1467 mp->tx_desc_count--;
1da177e4 1468
c9df406f
LB		 1469 addr = desc->buf_ptr;
1470 count = desc->byte_cnt;
1471 skb = mp->tx_skb[tx_index];
1472 if (skb)
1473 mp->tx_skb[tx_index] = NULL;
c8aaea25 1474
cc9754b3 1475 if (cmd_sts & ERROR_SUMMARY) {
c9df406f
LB		 1476 printk("%s: Error in TX\n", dev->name);
1477 dev->stats.tx_errors++;
1478 }
1da177e4 1479
c9df406f 1480 spin_unlock_irqrestore(&mp->lock, flags);
1da177e4 1481
cc9754b3 1482 if (cmd_sts & TX_FIRST_DESC)
c9df406f
LB		 1483 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
1484 else
1485 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
c2e5b352 1486
c9df406f
LB		 1487 if (skb)
1488 dev_kfree_skb_irq(skb);
63c9e549 1489
c9df406f
LB		 1490 released = 1;
1491 }
c2e5b352 1492
c9df406f 1493 return released;
63c9e549 1494}
63c9e549 1495
c9df406f 1496static void mv643xx_eth_free_completed_tx_descs(struct net_device *dev)
d0412d96 1497{
e5371493 1498 struct mv643xx_eth_private *mp = netdev_priv(dev);
d0412d96 1499
c9df406f
LB		 1500 if (mv643xx_eth_free_tx_descs(dev, 0) &&
1501 mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB)
1502 netif_wake_queue(dev);
d0412d96
JC		 1503}
1504
c9df406f 1505static void mv643xx_eth_free_all_tx_descs(struct net_device *dev)
1da177e4 1506{
c9df406f
LB		 1507 mv643xx_eth_free_tx_descs(dev, 1);
1508}
1da177e4 1509
c9df406f
LB		 1510static void mv643xx_eth_free_tx_rings(struct net_device *dev)
1511{
e5371493 1512 struct mv643xx_eth_private *mp = netdev_priv(dev);
84dd619e 1513
c9df406f
LB		 1514 /* Stop Tx Queues */
1515 mv643xx_eth_port_disable_tx(mp);
fa3959f4 1516
c9df406f
LB		 1517 /* Free outstanding skb's on TX ring */
1518 mv643xx_eth_free_all_tx_descs(dev);
1da177e4 1519
c9df406f 1520 BUG_ON(mp->tx_used_desc_q != mp->tx_curr_desc_q);
1da177e4 1521
c9df406f
LB		 1522 /* Free TX ring */
1523 if (mp->tx_sram_size)
1524 iounmap(mp->p_tx_desc_area);
1525 else
1526 dma_free_coherent(NULL, mp->tx_desc_area_size,
1527 mp->p_tx_desc_area, mp->tx_desc_dma);
1528}
1da177e4 1529
1da177e4 1530
c9df406f 1531/* netdev ops and related ***************************************************/
e5371493 1532static void port_reset(struct mv643xx_eth_private *mp);
1da177e4 1533
c9df406f
LB		 1534static void mv643xx_eth_update_pscr(struct net_device *dev,
1535 struct ethtool_cmd *ecmd)
1536{
e5371493 1537 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f
LB		 1538 int port_num = mp->port_num;
1539 u32 o_pscr, n_pscr;
1540 unsigned int queues;
1da177e4 1541
3cb4667c 1542 o_pscr = rdl(mp, PORT_SERIAL_CONTROL(port_num));
c9df406f 1543 n_pscr = o_pscr;
63c9e549 1544
c9df406f
LB		 1545 /* clear speed, duplex and rx buffer size fields */
1546 n_pscr &= ~(SET_MII_SPEED_TO_100 |
1547 SET_GMII_SPEED_TO_1000 |
1548 SET_FULL_DUPLEX_MODE |
1549 MAX_RX_PACKET_MASK);
1da177e4 1550
c9df406f
LB		 1551 if (ecmd->duplex == DUPLEX_FULL)
1552 n_pscr |= SET_FULL_DUPLEX_MODE;
1da177e4 1553
c9df406f
LB		 1554 if (ecmd->speed == SPEED_1000)
1555 n_pscr |= SET_GMII_SPEED_TO_1000 |
1556 MAX_RX_PACKET_9700BYTE;
1557 else {
1558 if (ecmd->speed == SPEED_100)
1559 n_pscr |= SET_MII_SPEED_TO_100;
1560 n_pscr |= MAX_RX_PACKET_1522BYTE;
1561 }
1da177e4 1562
c9df406f
LB		 1563 if (n_pscr != o_pscr) {
1564 if ((o_pscr & SERIAL_PORT_ENABLE) == 0)
3cb4667c 1565 wrl(mp, PORT_SERIAL_CONTROL(port_num), n_pscr);
c9df406f
LB		 1566 else {
1567 queues = mv643xx_eth_port_disable_tx(mp);
1da177e4 1568
c9df406f 1569 o_pscr &= ~SERIAL_PORT_ENABLE;
3cb4667c
LB		 1570 wrl(mp, PORT_SERIAL_CONTROL(port_num), o_pscr);
1571 wrl(mp, PORT_SERIAL_CONTROL(port_num), n_pscr);
1572 wrl(mp, PORT_SERIAL_CONTROL(port_num), n_pscr);
c9df406f
LB		 1573 if (queues)
1574 mv643xx_eth_port_enable_tx(mp, queues);
1575 }
1576 }
1577}
84dd619e 1578
c9df406f
LB		 1579static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id)
1580{
1581 struct net_device *dev = (struct net_device *)dev_id;
e5371493 1582 struct mv643xx_eth_private *mp = netdev_priv(dev);
cc9754b3 1583 u32 int_cause, int_cause_ext = 0;
c9df406f 1584 unsigned int port_num = mp->port_num;
ce4e2e45 1585
c9df406f 1586 /* Read interrupt cause registers */
cc9754b3
LB		 1587 int_cause = rdl(mp, INT_CAUSE(port_num)) & (INT_RX | INT_EXT);
1588 if (int_cause & INT_EXT) {
1589 int_cause_ext = rdl(mp, INT_CAUSE_EXT(port_num))
073a345c 1590 & (INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
cc9754b3 1591 wrl(mp, INT_CAUSE_EXT(port_num), ~int_cause_ext);
c9df406f 1592 }
1da177e4 1593
c9df406f 1594 /* PHY status changed */
cc9754b3 1595 if (int_cause_ext & (INT_EXT_LINK | INT_EXT_PHY)) {
c9df406f 1596 struct ethtool_cmd cmd;
1da177e4 1597
c9df406f
LB		 1598 if (mii_link_ok(&mp->mii)) {
1599 mii_ethtool_gset(&mp->mii, &cmd);
1600 mv643xx_eth_update_pscr(dev, &cmd);
073a345c 1601 mv643xx_eth_port_enable_tx(mp, 1);
c9df406f
LB		 1602 if (!netif_carrier_ok(dev)) {
1603 netif_carrier_on(dev);
1604 if (mp->tx_ring_size - mp->tx_desc_count >=
1605 MAX_DESCS_PER_SKB)
1606 netif_wake_queue(dev);
1607 }
1608 } else if (netif_carrier_ok(dev)) {
1609 netif_stop_queue(dev);
1610 netif_carrier_off(dev);
1611 }
1612 }
1da177e4 1613
e5371493 1614#ifdef MV643XX_ETH_NAPI
cc9754b3 1615 if (int_cause & INT_RX) {
c9df406f 1616 /* schedule the NAPI poll routine to maintain port */
073a345c 1617 wrl(mp, INT_MASK(port_num), 0x00000000);
1da177e4 1618
c9df406f 1619 /* wait for previous write to complete */
3cb4667c 1620 rdl(mp, INT_MASK(port_num));
1da177e4 1621
c9df406f 1622 netif_rx_schedule(dev, &mp->napi);
84dd619e 1623 }
c9df406f 1624#else
cc9754b3 1625 if (int_cause & INT_RX)
c9df406f
LB		 1626 mv643xx_eth_receive_queue(dev, INT_MAX);
1627#endif
cc9754b3 1628 if (int_cause_ext & INT_EXT_TX)
c9df406f 1629 mv643xx_eth_free_completed_tx_descs(dev);
1da177e4 1630
f2ce825d 1631 /*
c9df406f
LB		 1632 * If no real interrupt occured, exit.
1633 * This can happen when using gigE interrupt coalescing mechanism.
f2ce825d 1634 */
cc9754b3 1635 if ((int_cause == 0x0) && (int_cause_ext == 0x0))
c9df406f 1636 return IRQ_NONE;
1da177e4 1637
c9df406f 1638 return IRQ_HANDLED;
1da177e4
LT		 1639}
1640
e5371493 1641static void phy_reset(struct mv643xx_eth_private *mp)
1da177e4 1642{
c9df406f 1643 unsigned int phy_reg_data;
1da177e4 1644
c9df406f 1645 /* Reset the PHY */
cc9754b3 1646 read_smi_reg(mp, 0, &phy_reg_data);
c9df406f 1647 phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
cc9754b3 1648 write_smi_reg(mp, 0, phy_reg_data);
1da177e4 1649
c9df406f
LB		 1650 /* wait for PHY to come out of reset */
1651 do {
1652 udelay(1);
cc9754b3 1653 read_smi_reg(mp, 0, &phy_reg_data);
c9df406f 1654 } while (phy_reg_data & 0x8000);
1da177e4
LT		 1655}
1656
cc9754b3 1657static void port_start(struct net_device *dev)
1da177e4 1658{
e5371493 1659 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4
LT		 1660 unsigned int port_num = mp->port_num;
1661 int tx_curr_desc, rx_curr_desc;
d0412d96
JC		 1662 u32 pscr;
1663 struct ethtool_cmd ethtool_cmd;
1da177e4
LT		 1664
1665 /* Assignment of Tx CTRP of given queue */
1666 tx_curr_desc = mp->tx_curr_desc_q;
3cb4667c 1667 wrl(mp, TXQ_CURRENT_DESC_PTR(port_num),
cc9754b3 1668 (u32)((struct tx_desc *)mp->tx_desc_dma + tx_curr_desc));
1da177e4
LT		 1669
1670 /* Assignment of Rx CRDP of given queue */
1671 rx_curr_desc = mp->rx_curr_desc_q;
3cb4667c 1672 wrl(mp, RXQ_CURRENT_DESC_PTR(port_num),
cc9754b3 1673 (u32)((struct rx_desc *)mp->rx_desc_dma + rx_curr_desc));
1da177e4
LT		 1674
1675 /* Add the assigned Ethernet address to the port's address table */
cc9754b3 1676 uc_addr_set(mp, dev->dev_addr);
1da177e4 1677
d9a073ea
LB		 1678 /*
1679 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
1680 * frames to RX queue #0.
1681 */
1682 wrl(mp, PORT_CONFIG(port_num), 0x00000000);
01999873 1683
376489a2
LB		 1684 /*
1685 * Treat BPDUs as normal multicasts, and disable partition mode.
1686 */
1687 wrl(mp, PORT_CONFIG_EXT(port_num), 0x00000000);
1da177e4 1688
3cb4667c 1689 pscr = rdl(mp, PORT_SERIAL_CONTROL(port_num));
01999873 1690
e4d00fa9 1691 pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS);
3cb4667c 1692 wrl(mp, PORT_SERIAL_CONTROL(port_num), pscr);
1da177e4 1693
e4d00fa9
LB		 1694 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1695 DISABLE_AUTO_NEG_SPEED_GMII |
2beff77b 1696 DISABLE_AUTO_NEG_FOR_DUPLEX |
e4d00fa9
LB		 1697 DO_NOT_FORCE_LINK_FAIL |
1698 SERIAL_PORT_CONTROL_RESERVED;
1da177e4 1699
3cb4667c 1700 wrl(mp, PORT_SERIAL_CONTROL(port_num), pscr);
1da177e4 1701
e4d00fa9 1702 pscr |= SERIAL_PORT_ENABLE;
3cb4667c 1703 wrl(mp, PORT_SERIAL_CONTROL(port_num), pscr);
1da177e4
LT		 1704
1705 /* Assign port SDMA configuration */
3cb4667c 1706 wrl(mp, SDMA_CONFIG(port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1da177e4
LT		 1707
1708 /* Enable port Rx. */
073a345c 1709 mv643xx_eth_port_enable_rx(mp, 1);
8f543718
DF		 1710
1711 /* Disable port bandwidth limits by clearing MTU register */
3cb4667c 1712 wrl(mp, TX_BW_MTU(port_num), 0);
d0412d96
JC		 1713
1714 /* save phy settings across reset */
e5371493 1715 mv643xx_eth_get_settings(dev, &ethtool_cmd);
cc9754b3 1716 phy_reset(mp);
e5371493 1717 mv643xx_eth_set_settings(dev, &ethtool_cmd);
1da177e4
LT		 1718}
1719
e5371493 1720#ifdef MV643XX_ETH_COAL
e5371493 1721static unsigned int set_rx_coal(struct mv643xx_eth_private *mp,
c9df406f 1722 unsigned int delay)
1da177e4 1723{
afdb57a2 1724 unsigned int port_num = mp->port_num;
c9df406f 1725 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1da177e4 1726
c9df406f 1727 /* Set RX Coalescing mechanism */
3cb4667c 1728 wrl(mp, SDMA_CONFIG(port_num),
c9df406f 1729 ((coal & 0x3fff) << 8) |
3cb4667c 1730 (rdl(mp, SDMA_CONFIG(port_num))
c9df406f 1731 & 0xffc000ff));
1da177e4 1732
c9df406f 1733 return coal;
1da177e4 1734}
c9df406f 1735#endif
1da177e4 1736
e5371493 1737static unsigned int set_tx_coal(struct mv643xx_eth_private *mp,
c9df406f 1738 unsigned int delay)
1da177e4 1739{
c9df406f 1740 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1da177e4 1741
c9df406f 1742 /* Set TX Coalescing mechanism */
3cb4667c 1743 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), coal << 4);
1da177e4 1744
c9df406f 1745 return coal;
1da177e4
LT		 1746}
1747
e5371493 1748static void port_init(struct mv643xx_eth_private *mp)
16e03018 1749{
cc9754b3 1750 port_reset(mp);
16e03018 1751
cc9754b3 1752 init_mac_tables(mp);
16e03018
DF		 1753}
1754
c9df406f 1755static int mv643xx_eth_open(struct net_device *dev)
16e03018 1756{
e5371493 1757 struct mv643xx_eth_private *mp = netdev_priv(dev);
afdb57a2 1758 unsigned int port_num = mp->port_num;
c9df406f
LB		 1759 unsigned int size;
1760 int err;
16e03018 1761
c9df406f 1762 /* Clear any pending ethernet port interrupts */
3cb4667c
LB		 1763 wrl(mp, INT_CAUSE(port_num), 0);
1764 wrl(mp, INT_CAUSE_EXT(port_num), 0);
c9df406f 1765 /* wait for previous write to complete */
3cb4667c 1766 rdl(mp, INT_CAUSE_EXT(port_num));
c9df406f
LB		 1767
1768 err = request_irq(dev->irq, mv643xx_eth_int_handler,
1769 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
1770 if (err) {
1771 printk(KERN_ERR "%s: Can not assign IRQ\n", dev->name);
1772 return -EAGAIN;
16e03018
DF		 1773 }
1774
cc9754b3 1775 port_init(mp);
16e03018 1776
c9df406f
LB		 1777 memset(&mp->timeout, 0, sizeof(struct timer_list));
1778 mp->timeout.function = mv643xx_eth_rx_refill_descs_timer_wrapper;
1779 mp->timeout.data = (unsigned long)dev;
16e03018 1780
c9df406f
LB		 1781 /* Allocate RX and TX skb rings */
1782 mp->rx_skb = kmalloc(sizeof(*mp->rx_skb) * mp->rx_ring_size,
1783 GFP_KERNEL);
1784 if (!mp->rx_skb) {
1785 printk(KERN_ERR "%s: Cannot allocate Rx skb ring\n", dev->name);
1786 err = -ENOMEM;
1787 goto out_free_irq;
1788 }
1789 mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size,
1790 GFP_KERNEL);
1791 if (!mp->tx_skb) {
1792 printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name);
1793 err = -ENOMEM;
1794 goto out_free_rx_skb;
1795 }
16e03018 1796
c9df406f
LB		 1797 /* Allocate TX ring */
1798 mp->tx_desc_count = 0;
cc9754b3 1799 size = mp->tx_ring_size * sizeof(struct tx_desc);
c9df406f 1800 mp->tx_desc_area_size = size;
16e03018 1801
c9df406f
LB		 1802 if (mp->tx_sram_size) {
1803 mp->p_tx_desc_area = ioremap(mp->tx_sram_addr,
1804 mp->tx_sram_size);
1805 mp->tx_desc_dma = mp->tx_sram_addr;
1806 } else
1807 mp->p_tx_desc_area = dma_alloc_coherent(NULL, size,
1808 &mp->tx_desc_dma,
1809 GFP_KERNEL);
16e03018 1810
c9df406f
LB		 1811 if (!mp->p_tx_desc_area) {
1812 printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n",
1813 dev->name, size);
1814 err = -ENOMEM;
1815 goto out_free_tx_skb;
1816 }
1817 BUG_ON((u32) mp->p_tx_desc_area & 0xf); /* check 16-byte alignment */
1818 memset((void *)mp->p_tx_desc_area, 0, mp->tx_desc_area_size);
16e03018 1819
c9df406f 1820 ether_init_tx_desc_ring(mp);
16e03018 1821
c9df406f
LB		 1822 /* Allocate RX ring */
1823 mp->rx_desc_count = 0;
cc9754b3 1824 size = mp->rx_ring_size * sizeof(struct rx_desc);
c9df406f 1825 mp->rx_desc_area_size = size;
16e03018 1826
c9df406f
LB		 1827 if (mp->rx_sram_size) {
1828 mp->p_rx_desc_area = ioremap(mp->rx_sram_addr,
1829 mp->rx_sram_size);
1830 mp->rx_desc_dma = mp->rx_sram_addr;
1831 } else
1832 mp->p_rx_desc_area = dma_alloc_coherent(NULL, size,
1833 &mp->rx_desc_dma,
1834 GFP_KERNEL);
16e03018 1835
c9df406f
LB		 1836 if (!mp->p_rx_desc_area) {
1837 printk(KERN_ERR "%s: Cannot allocate Rx ring (size %d bytes)\n",
1838 dev->name, size);
1839 printk(KERN_ERR "%s: Freeing previously allocated TX queues...",
1840 dev->name);
1841 if (mp->rx_sram_size)
1842 iounmap(mp->p_tx_desc_area);
1843 else
1844 dma_free_coherent(NULL, mp->tx_desc_area_size,
1845 mp->p_tx_desc_area, mp->tx_desc_dma);
1846 err = -ENOMEM;
1847 goto out_free_tx_skb;
1848 }
1849 memset((void *)mp->p_rx_desc_area, 0, size);
16e03018 1850
c9df406f 1851 ether_init_rx_desc_ring(mp);
16e03018 1852
c9df406f 1853 mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */
16e03018 1854
e5371493 1855#ifdef MV643XX_ETH_NAPI
c9df406f
LB		 1856 napi_enable(&mp->napi);
1857#endif
16e03018 1858
cc9754b3 1859 port_start(dev);
16e03018 1860
c9df406f 1861 /* Interrupt Coalescing */
b4de9051 1862
e5371493
LB		 1863#ifdef MV643XX_ETH_COAL
1864 mp->rx_int_coal = set_rx_coal(mp, MV643XX_ETH_RX_COAL);
c9df406f
LB		 1865#endif
1866
e5371493 1867 mp->tx_int_coal = set_tx_coal(mp, MV643XX_ETH_TX_COAL);
16e03018 1868
c9df406f 1869 /* Unmask phy and link status changes interrupts */
073a345c 1870 wrl(mp, INT_MASK_EXT(port_num), INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
16e03018 1871
c9df406f 1872 /* Unmask RX buffer and TX end interrupt */
073a345c 1873 wrl(mp, INT_MASK(port_num), INT_RX | INT_EXT);
16e03018 1874
c9df406f
LB		 1875 return 0;
1876
1877out_free_tx_skb:
1878 kfree(mp->tx_skb);
1879out_free_rx_skb:
1880 kfree(mp->rx_skb);
1881out_free_irq:
1882 free_irq(dev->irq, dev);
1883
1884 return err;
16e03018
DF		 1885}
1886
e5371493 1887static void port_reset(struct mv643xx_eth_private *mp)
1da177e4 1888{
afdb57a2 1889 unsigned int port_num = mp->port_num;
c9df406f 1890 unsigned int reg_data;
1da177e4 1891
c9df406f
LB		 1892 mv643xx_eth_port_disable_tx(mp);
1893 mv643xx_eth_port_disable_rx(mp);
1da177e4 1894
c9df406f 1895 /* Clear all MIB counters */
cc9754b3 1896 clear_mib_counters(mp);
c9df406f
LB		 1897
1898 /* Reset the Enable bit in the Configuration Register */
3cb4667c 1899 reg_data = rdl(mp, PORT_SERIAL_CONTROL(port_num));
c9df406f
LB		 1900 reg_data &= ~(SERIAL_PORT_ENABLE |
1901 DO_NOT_FORCE_LINK_FAIL |
1902 FORCE_LINK_PASS);
3cb4667c 1903 wrl(mp, PORT_SERIAL_CONTROL(port_num), reg_data);
1da177e4
LT		 1904}
1905
c9df406f 1906static int mv643xx_eth_stop(struct net_device *dev)
1da177e4 1907{
e5371493 1908 struct mv643xx_eth_private *mp = netdev_priv(dev);
afdb57a2 1909 unsigned int port_num = mp->port_num;
1da177e4 1910
c9df406f 1911 /* Mask all interrupts on ethernet port */
073a345c 1912 wrl(mp, INT_MASK(port_num), 0x00000000);
c9df406f 1913 /* wait for previous write to complete */
3cb4667c 1914 rdl(mp, INT_MASK(port_num));
1da177e4 1915
e5371493 1916#ifdef MV643XX_ETH_NAPI
c9df406f
LB		 1917 napi_disable(&mp->napi);
1918#endif
1919 netif_carrier_off(dev);
1920 netif_stop_queue(dev);
1da177e4 1921
cc9754b3 1922 port_reset(mp);
1da177e4 1923
c9df406f
LB		 1924 mv643xx_eth_free_tx_rings(dev);
1925 mv643xx_eth_free_rx_rings(dev);
1da177e4 1926
c9df406f 1927 free_irq(dev->irq, dev);
1da177e4 1928
c9df406f 1929 return 0;
1da177e4
LT		 1930}
1931
c9df406f 1932static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1da177e4 1933{
e5371493 1934 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1935
c9df406f 1936 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
1da177e4
LT		 1937}
1938
c9df406f 1939static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 1940{
c9df406f
LB		 1941 if ((new_mtu > 9500) || (new_mtu < 64))
1942 return -EINVAL;
1da177e4 1943
c9df406f
LB		 1944 dev->mtu = new_mtu;
1945 if (!netif_running(dev))
1946 return 0;
1da177e4 1947
c9df406f
LB		 1948 /*
1949 * Stop and then re-open the interface. This will allocate RX
1950 * skbs of the new MTU.
1951 * There is a possible danger that the open will not succeed,
1952 * due to memory being full, which might fail the open function.
1953 */
1954 mv643xx_eth_stop(dev);
1955 if (mv643xx_eth_open(dev)) {
1956 printk(KERN_ERR "%s: Fatal error on opening device\n",
1957 dev->name);
1958 }
1959
1960 return 0;
1da177e4
LT		 1961}
1962
c9df406f 1963static void mv643xx_eth_tx_timeout_task(struct work_struct *ugly)
1da177e4 1964{
e5371493 1965 struct mv643xx_eth_private *mp = container_of(ugly, struct mv643xx_eth_private,
c9df406f
LB		 1966 tx_timeout_task);
1967 struct net_device *dev = mp->dev;
1da177e4 1968
c9df406f
LB		 1969 if (!netif_running(dev))
1970 return;
1da177e4 1971
c9df406f
LB		 1972 netif_stop_queue(dev);
1973
cc9754b3
LB		 1974 port_reset(mp);
1975 port_start(dev);
c9df406f
LB		 1976
1977 if (mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB)
1978 netif_wake_queue(dev);
1979}
1980
c9df406f 1981static void mv643xx_eth_tx_timeout(struct net_device *dev)
1da177e4 1982{
e5371493 1983 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1984
c9df406f 1985 printk(KERN_INFO "%s: TX timeout ", dev->name);
d0412d96 1986
c9df406f
LB		 1987 /* Do the reset outside of interrupt context */
1988 schedule_work(&mp->tx_timeout_task);
1da177e4
LT		 1989}
1990
c9df406f 1991#ifdef CONFIG_NET_POLL_CONTROLLER
e5371493 1992static void mv643xx_eth_netpoll(struct net_device *netdev)
9f8dd319 1993{
e5371493 1994 struct mv643xx_eth_private *mp = netdev_priv(netdev);
c9df406f
LB		 1995 int port_num = mp->port_num;
1996
073a345c 1997 wrl(mp, INT_MASK(port_num), 0x00000000);
c9df406f 1998 /* wait for previous write to complete */
3cb4667c 1999 rdl(mp, INT_MASK(port_num));
c9df406f
LB		 2000
2001 mv643xx_eth_int_handler(netdev->irq, netdev);
2002
073a345c 2003 wrl(mp, INT_MASK(port_num), INT_RX | INT_CAUSE_EXT);
9f8dd319 2004}
c9df406f 2005#endif
9f8dd319 2006
e5371493 2007static int mv643xx_eth_mdio_read(struct net_device *dev, int phy_id, int location)
9f8dd319 2008{
e5371493 2009 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f
LB		 2010 int val;
2011
cc9754b3 2012 read_smi_reg(mp, location, &val);
c9df406f 2013 return val;
9f8dd319
DF		 2014}
2015
e5371493 2016static void mv643xx_eth_mdio_write(struct net_device *dev, int phy_id, int location, int val)
9f8dd319 2017{
e5371493 2018 struct mv643xx_eth_private *mp = netdev_priv(dev);
cc9754b3 2019 write_smi_reg(mp, location, val);
c9df406f 2020}
9f8dd319 2021
9f8dd319 2022
c9df406f 2023/* platform glue ************************************************************/
e5371493
LB		 2024static void
2025mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2026 struct mbus_dram_target_info *dram)
c9df406f 2027{
cc9754b3 2028 void __iomem *base = msp->base;
c9df406f
LB		 2029 u32 win_enable;
2030 u32 win_protect;
2031 int i;
9f8dd319 2032
c9df406f
LB		 2033 for (i = 0; i < 6; i++) {
2034 writel(0, base + WINDOW_BASE(i));
2035 writel(0, base + WINDOW_SIZE(i));
2036 if (i < 4)
2037 writel(0, base + WINDOW_REMAP_HIGH(i));
9f8dd319
DF		 2038 }
2039
c9df406f
LB		 2040 win_enable = 0x3f;
2041 win_protect = 0;
2042
2043 for (i = 0; i < dram->num_cs; i++) {
2044 struct mbus_dram_window *cs = dram->cs + i;
2045
2046 writel((cs->base & 0xffff0000) |
2047 (cs->mbus_attr << 8) |
2048 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2049 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2050
2051 win_enable &= ~(1 << i);
2052 win_protect |= 3 << (2 * i);
2053 }
2054
2055 writel(win_enable, base + WINDOW_BAR_ENABLE);
2056 msp->win_protect = win_protect;
9f8dd319
DF		 2057}
2058
c9df406f 2059static int mv643xx_eth_shared_probe(struct platform_device *pdev)
9f8dd319 2060{
e5371493 2061 static int mv643xx_eth_version_printed = 0;
c9df406f 2062 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
e5371493 2063 struct mv643xx_eth_shared_private *msp;
c9df406f
LB		 2064 struct resource *res;
2065 int ret;
9f8dd319 2066
e5371493 2067 if (!mv643xx_eth_version_printed++)
c9df406f 2068 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
9f8dd319 2069
c9df406f
LB		 2070 ret = -EINVAL;
2071 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2072 if (res == NULL)
2073 goto out;
9f8dd319 2074
c9df406f
LB		 2075 ret = -ENOMEM;
2076 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2077 if (msp == NULL)
2078 goto out;
2079 memset(msp, 0, sizeof(*msp));
2080
cc9754b3
LB		 2081 msp->base = ioremap(res->start, res->end - res->start + 1);
2082 if (msp->base == NULL)
c9df406f
LB		 2083 goto out_free;
2084
2085 spin_lock_init(&msp->phy_lock);
2086 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
2087
2088 platform_set_drvdata(pdev, msp);
2089
2090 /*
2091 * (Re-)program MBUS remapping windows if we are asked to.
2092 */
2093 if (pd != NULL && pd->dram != NULL)
2094 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2095
2096 return 0;
2097
2098out_free:
2099 kfree(msp);
2100out:
2101 return ret;
2102}
2103
2104static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2105{
e5371493 2106 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
c9df406f 2107
cc9754b3 2108 iounmap(msp->base);
c9df406f
LB		 2109 kfree(msp);
2110
2111 return 0;
9f8dd319
DF		 2112}
2113
c9df406f
LB		 2114static struct platform_driver mv643xx_eth_shared_driver = {
2115 .probe = mv643xx_eth_shared_probe,
2116 .remove = mv643xx_eth_shared_remove,
2117 .driver = {
2118 .name = MV643XX_ETH_SHARED_NAME,
2119 .owner = THIS_MODULE,
2120 },
2121};
2122
e5371493 2123static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
1da177e4 2124{
c9df406f
LB		 2125 u32 reg_data;
2126 int addr_shift = 5 * mp->port_num;
1da177e4 2127
3cb4667c 2128 reg_data = rdl(mp, PHY_ADDR);
c9df406f
LB		 2129 reg_data &= ~(0x1f << addr_shift);
2130 reg_data |= (phy_addr & 0x1f) << addr_shift;
3cb4667c 2131 wrl(mp, PHY_ADDR, reg_data);
1da177e4
LT		 2132}
2133
e5371493 2134static int phy_addr_get(struct mv643xx_eth_private *mp)
1da177e4 2135{
c9df406f 2136 unsigned int reg_data;
1da177e4 2137
3cb4667c 2138 reg_data = rdl(mp, PHY_ADDR);
1da177e4 2139
c9df406f 2140 return ((reg_data >> (5 * mp->port_num)) & 0x1f);
1da177e4
LT		 2141}
2142
e5371493 2143static int phy_detect(struct mv643xx_eth_private *mp)
1da177e4 2144{
c9df406f
LB		 2145 unsigned int phy_reg_data0;
2146 int auto_neg;
1da177e4 2147
cc9754b3 2148 read_smi_reg(mp, 0, &phy_reg_data0);
c9df406f
LB		 2149 auto_neg = phy_reg_data0 & 0x1000;
2150 phy_reg_data0 ^= 0x1000; /* invert auto_neg */
cc9754b3 2151 write_smi_reg(mp, 0, phy_reg_data0);
1da177e4 2152
cc9754b3 2153 read_smi_reg(mp, 0, &phy_reg_data0);
c9df406f
LB		 2154 if ((phy_reg_data0 & 0x1000) == auto_neg)
2155 return -ENODEV; /* change didn't take */
1da177e4 2156
c9df406f 2157 phy_reg_data0 ^= 0x1000;
cc9754b3 2158 write_smi_reg(mp, 0, phy_reg_data0);
c9df406f 2159 return 0;
1da177e4
LT		 2160}
2161
c9df406f
LB		 2162static void mv643xx_init_ethtool_cmd(struct net_device *dev, int phy_address,
2163 int speed, int duplex,
2164 struct ethtool_cmd *cmd)
c28a4f89 2165{
e5371493 2166 struct mv643xx_eth_private *mp = netdev_priv(dev);
c28a4f89 2167
c9df406f 2168 memset(cmd, 0, sizeof(*cmd));
c28a4f89 2169
c9df406f
LB		 2170 cmd->port = PORT_MII;
2171 cmd->transceiver = XCVR_INTERNAL;
2172 cmd->phy_address = phy_address;
2173
2174 if (speed == 0) {
2175 cmd->autoneg = AUTONEG_ENABLE;
2176 /* mii lib checks, but doesn't use speed on AUTONEG_ENABLE */
2177 cmd->speed = SPEED_100;
2178 cmd->advertising = ADVERTISED_10baseT_Half |
2179 ADVERTISED_10baseT_Full |
2180 ADVERTISED_100baseT_Half |
2181 ADVERTISED_100baseT_Full;
2182 if (mp->mii.supports_gmii)
2183 cmd->advertising |= ADVERTISED_1000baseT_Full;
2184 } else {
2185 cmd->autoneg = AUTONEG_DISABLE;
2186 cmd->speed = speed;
2187 cmd->duplex = duplex;
2188 }
c28a4f89
JC		 2189}
2190
c9df406f 2191static int mv643xx_eth_probe(struct platform_device *pdev)
1da177e4 2192{
c9df406f
LB		 2193 struct mv643xx_eth_platform_data *pd;
2194 int port_num;
e5371493 2195 struct mv643xx_eth_private *mp;
c9df406f
LB		 2196 struct net_device *dev;
2197 u8 *p;
2198 struct resource *res;
2199 int err;
2200 struct ethtool_cmd cmd;
2201 int duplex = DUPLEX_HALF;
2202 int speed = 0; /* default to auto-negotiation */
2203 DECLARE_MAC_BUF(mac);
1da177e4 2204
c9df406f
LB		 2205 pd = pdev->dev.platform_data;
2206 if (pd == NULL) {
2207 printk(KERN_ERR "No mv643xx_eth_platform_data\n");
2208 return -ENODEV;
2209 }
1da177e4 2210
c9df406f
LB		 2211 if (pd->shared == NULL) {
2212 printk(KERN_ERR "No mv643xx_eth_platform_data->shared\n");
2213 return -ENODEV;
2214 }
8f518703 2215
e5371493 2216 dev = alloc_etherdev(sizeof(struct mv643xx_eth_private));
c9df406f
LB		 2217 if (!dev)
2218 return -ENOMEM;
1da177e4 2219
c9df406f 2220 platform_set_drvdata(pdev, dev);
1da177e4 2221
c9df406f
LB		 2222 mp = netdev_priv(dev);
2223 mp->dev = dev;
e5371493
LB		 2224#ifdef MV643XX_ETH_NAPI
2225 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 64);
c9df406f 2226#endif
1da177e4 2227
c9df406f
LB		 2228 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2229 BUG_ON(!res);
2230 dev->irq = res->start;
1da177e4 2231
c9df406f
LB		 2232 dev->open = mv643xx_eth_open;
2233 dev->stop = mv643xx_eth_stop;
2234 dev->hard_start_xmit = mv643xx_eth_start_xmit;
2235 dev->set_mac_address = mv643xx_eth_set_mac_address;
2236 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
2237
2238 /* No need to Tx Timeout */
2239 dev->tx_timeout = mv643xx_eth_tx_timeout;
2240
2241#ifdef CONFIG_NET_POLL_CONTROLLER
e5371493 2242 dev->poll_controller = mv643xx_eth_netpoll;
c9df406f
LB		 2243#endif
2244
2245 dev->watchdog_timeo = 2 * HZ;
2246 dev->base_addr = 0;
2247 dev->change_mtu = mv643xx_eth_change_mtu;
2248 dev->do_ioctl = mv643xx_eth_do_ioctl;
e5371493 2249 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
1da177e4 2250
e5371493 2251#ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
c9df406f 2252#ifdef MAX_SKB_FRAGS
b4de9051 2253 /*
c9df406f
LB		 2254 * Zero copy can only work if we use Discovery II memory. Else, we will
2255 * have to map the buffers to ISA memory which is only 16 MB
b4de9051 2256 */
c9df406f
LB		 2257 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2258#endif
2259#endif
1da177e4 2260
c9df406f
LB		 2261 /* Configure the timeout task */
2262 INIT_WORK(&mp->tx_timeout_task, mv643xx_eth_tx_timeout_task);
1da177e4 2263
c9df406f 2264 spin_lock_init(&mp->lock);
1da177e4 2265
c9df406f
LB		 2266 mp->shared = platform_get_drvdata(pd->shared);
2267 port_num = mp->port_num = pd->port_number;
8f518703 2268
c9df406f
LB		 2269 if (mp->shared->win_protect)
2270 wrl(mp, WINDOW_PROTECT(port_num), mp->shared->win_protect);
1da177e4 2271
c9df406f
LB		 2272 mp->shared_smi = mp->shared;
2273 if (pd->shared_smi != NULL)
2274 mp->shared_smi = platform_get_drvdata(pd->shared_smi);
2275
2276 /* set default config values */
cc9754b3
LB		 2277 uc_addr_get(mp, dev->dev_addr);
2278 mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2279 mp->tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
c9df406f
LB		 2280
2281 if (is_valid_ether_addr(pd->mac_addr))
2282 memcpy(dev->dev_addr, pd->mac_addr, 6);
2283
2284 if (pd->phy_addr || pd->force_phy_addr)
cc9754b3 2285 phy_addr_set(mp, pd->phy_addr);
8f518703 2286
c9df406f
LB		 2287 if (pd->rx_queue_size)
2288 mp->rx_ring_size = pd->rx_queue_size;
1da177e4 2289
c9df406f
LB		 2290 if (pd->tx_queue_size)
2291 mp->tx_ring_size = pd->tx_queue_size;
1da177e4 2292
c9df406f
LB		 2293 if (pd->tx_sram_size) {
2294 mp->tx_sram_size = pd->tx_sram_size;
2295 mp->tx_sram_addr = pd->tx_sram_addr;
2296 }
1da177e4 2297
c9df406f
LB		 2298 if (pd->rx_sram_size) {
2299 mp->rx_sram_size = pd->rx_sram_size;
2300 mp->rx_sram_addr = pd->rx_sram_addr;
2301 }
1da177e4 2302
c9df406f
LB		 2303 duplex = pd->duplex;
2304 speed = pd->speed;
1da177e4 2305
c9df406f
LB		 2306 /* Hook up MII support for ethtool */
2307 mp->mii.dev = dev;
e5371493
LB		 2308 mp->mii.mdio_read = mv643xx_eth_mdio_read;
2309 mp->mii.mdio_write = mv643xx_eth_mdio_write;
cc9754b3 2310 mp->mii.phy_id = phy_addr_get(mp);
c9df406f
LB		 2311 mp->mii.phy_id_mask = 0x3f;
2312 mp->mii.reg_num_mask = 0x1f;
1da177e4 2313
cc9754b3 2314 err = phy_detect(mp);
c9df406f
LB		 2315 if (err) {
2316 pr_debug("%s: No PHY detected at addr %d\n",
cc9754b3 2317 dev->name, phy_addr_get(mp));
c9df406f
LB		 2318 goto out;
2319 }
1da177e4 2320
cc9754b3 2321 phy_reset(mp);
c9df406f
LB		 2322 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
2323 mv643xx_init_ethtool_cmd(dev, mp->mii.phy_id, speed, duplex, &cmd);
2324 mv643xx_eth_update_pscr(dev, &cmd);
e5371493 2325 mv643xx_eth_set_settings(dev, &cmd);
8f518703 2326
c9df406f
LB		 2327 SET_NETDEV_DEV(dev, &pdev->dev);
2328 err = register_netdev(dev);
2329 if (err)
2330 goto out;
1da177e4 2331
c9df406f
LB		 2332 p = dev->dev_addr;
2333 printk(KERN_NOTICE
2334 "%s: port %d with MAC address %s\n",
2335 dev->name, port_num, print_mac(mac, p));
1da177e4 2336
c9df406f
LB		 2337 if (dev->features & NETIF_F_SG)
2338 printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name);
1da177e4 2339
c9df406f
LB		 2340 if (dev->features & NETIF_F_IP_CSUM)
2341 printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n",
2342 dev->name);
1da177e4 2343
e5371493 2344#ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
c9df406f
LB		 2345 printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name);
2346#endif
1da177e4 2347
e5371493 2348#ifdef MV643XX_ETH_COAL
c9df406f
LB		 2349 printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n",
2350 dev->name);
2351#endif
1da177e4 2352
e5371493 2353#ifdef MV643XX_ETH_NAPI
c9df406f
LB		 2354 printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name);
2355#endif
1da177e4 2356
c9df406f
LB		 2357 if (mp->tx_sram_size > 0)
2358 printk(KERN_NOTICE "%s: Using SRAM\n", dev->name);
1da177e4 2359
c9df406f 2360 return 0;
1da177e4 2361
c9df406f
LB		 2362out:
2363 free_netdev(dev);
1da177e4 2364
c9df406f 2365 return err;
1da177e4
LT		 2366}
2367
c9df406f 2368static int mv643xx_eth_remove(struct platform_device *pdev)
1da177e4 2369{
c9df406f 2370 struct net_device *dev = platform_get_drvdata(pdev);
1da177e4 2371
c9df406f
LB		 2372 unregister_netdev(dev);
2373 flush_scheduled_work();
2374
2375 free_netdev(dev);
2376 platform_set_drvdata(pdev, NULL);
2377 return 0;
1da177e4
LT		 2378}
2379
c9df406f 2380static void mv643xx_eth_shutdown(struct platform_device *pdev)
d0412d96 2381{
c9df406f 2382 struct net_device *dev = platform_get_drvdata(pdev);
e5371493 2383 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2384 unsigned int port_num = mp->port_num;
d0412d96 2385
c9df406f 2386 /* Mask all interrupts on ethernet port */
3cb4667c
LB		 2387 wrl(mp, INT_MASK(port_num), 0);
2388 rdl(mp, INT_MASK(port_num));
c9df406f 2389
cc9754b3 2390 port_reset(mp);
d0412d96
JC		 2391}
2392
c9df406f
LB		 2393static struct platform_driver mv643xx_eth_driver = {
2394 .probe = mv643xx_eth_probe,
2395 .remove = mv643xx_eth_remove,
2396 .shutdown = mv643xx_eth_shutdown,
2397 .driver = {
2398 .name = MV643XX_ETH_NAME,
2399 .owner = THIS_MODULE,
2400 },
2401};
2402
e5371493 2403static int __init mv643xx_eth_init_module(void)
d0412d96 2404{
c9df406f 2405 int rc;
d0412d96 2406
c9df406f
LB		 2407 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2408 if (!rc) {
2409 rc = platform_driver_register(&mv643xx_eth_driver);
2410 if (rc)
2411 platform_driver_unregister(&mv643xx_eth_shared_driver);
2412 }
2413 return rc;
d0412d96
JC		 2414}
2415
e5371493 2416static void __exit mv643xx_eth_cleanup_module(void)
d0412d96 2417{
c9df406f
LB		 2418 platform_driver_unregister(&mv643xx_eth_driver);
2419 platform_driver_unregister(&mv643xx_eth_shared_driver);
d0412d96
JC		 2420}
2421
e5371493
LB		 2422module_init(mv643xx_eth_init_module);
2423module_exit(mv643xx_eth_cleanup_module);
1da177e4 2424
c9df406f
LB		 2425MODULE_LICENSE("GPL");
2426MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani"
2427 " and Dale Farnsworth");
2428MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
2429MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
2430MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
Linux 6.x block layer and io_uring tree(s)