Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * drivers/net/mv643xx_eth.c - Driver for MV643XX ethernet ports | |
3 | * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com> | |
4 | * | |
5 | * Based on the 64360 driver from: | |
6 | * Copyright (C) 2002 rabeeh@galileo.co.il | |
7 | * | |
8 | * Copyright (C) 2003 PMC-Sierra, Inc., | |
3bb8a18a | 9 | * written by Manish Lachwani |
1da177e4 LT |
10 | * |
11 | * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org> | |
12 | * | |
13 | * Copyright (C) 2004-2005 MontaVista Software, Inc. | |
14 | * Dale Farnsworth <dale@farnsworth.org> | |
15 | * | |
16 | * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com> | |
17 | * <sjhill@realitydiluted.com> | |
18 | * | |
19 | * This program is free software; you can redistribute it and/or | |
20 | * modify it under the terms of the GNU General Public License | |
21 | * as published by the Free Software Foundation; either version 2 | |
22 | * of the License, or (at your option) any later version. | |
23 | * | |
24 | * This program is distributed in the hope that it will be useful, | |
25 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
26 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
27 | * GNU General Public License for more details. | |
28 | * | |
29 | * You should have received a copy of the GNU General Public License | |
30 | * along with this program; if not, write to the Free Software | |
31 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
32 | */ | |
33 | #include <linux/init.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | #include <linux/tcp.h> | |
36 | #include <linux/udp.h> | |
37 | #include <linux/etherdevice.h> | |
78a5e534 OH |
38 | #include <linux/in.h> |
39 | #include <linux/ip.h> | |
1da177e4 LT |
40 | |
41 | #include <linux/bitops.h> | |
42 | #include <linux/delay.h> | |
43 | #include <linux/ethtool.h> | |
d052d1be RK |
44 | #include <linux/platform_device.h> |
45 | ||
1da177e4 LT |
46 | #include <asm/io.h> |
47 | #include <asm/types.h> | |
48 | #include <asm/pgtable.h> | |
49 | #include <asm/system.h> | |
50 | #include <asm/delay.h> | |
51 | #include "mv643xx_eth.h" | |
52 | ||
53 | /* | |
54 | * The first part is the high level driver of the gigE ethernet ports. | |
55 | */ | |
56 | ||
57 | /* Constants */ | |
58 | #define VLAN_HLEN 4 | |
59 | #define FCS_LEN 4 | |
b44cd572 DF |
60 | #define DMA_ALIGN 8 /* hw requires 8-byte alignment */ |
61 | #define HW_IP_ALIGN 2 /* hw aligns IP header */ | |
62 | #define WRAP HW_IP_ALIGN + ETH_HLEN + VLAN_HLEN + FCS_LEN | |
1da177e4 LT |
63 | #define RX_SKB_SIZE ((dev->mtu + WRAP + 7) & ~0x7) |
64 | ||
c2e5b352 DF |
65 | #define INT_UNMASK_ALL 0x0007ffff |
66 | #define INT_UNMASK_ALL_EXT 0x0011ffff | |
67 | #define INT_MASK_ALL 0x00000000 | |
68 | #define INT_MASK_ALL_EXT 0x00000000 | |
1da177e4 LT |
69 | #define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL |
70 | #define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT | |
1da177e4 LT |
71 | |
72 | #ifdef MV643XX_CHECKSUM_OFFLOAD_TX | |
73 | #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1) | |
74 | #else | |
75 | #define MAX_DESCS_PER_SKB 1 | |
76 | #endif | |
77 | ||
78 | #define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */ | |
79 | #define PHY_WAIT_MICRO_SECONDS 10 | |
80 | ||
81 | /* Static function declarations */ | |
82 | static int eth_port_link_is_up(unsigned int eth_port_num); | |
83 | static void eth_port_uc_addr_get(struct net_device *dev, | |
84 | unsigned char *MacAddr); | |
16e03018 | 85 | static void eth_port_set_multicast_list(struct net_device *); |
ab4384a6 DF |
86 | static int mv643xx_eth_open(struct net_device *); |
87 | static int mv643xx_eth_stop(struct net_device *); | |
1da177e4 LT |
88 | static int mv643xx_eth_change_mtu(struct net_device *, int); |
89 | static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *); | |
90 | static void eth_port_init_mac_tables(unsigned int eth_port_num); | |
91 | #ifdef MV643XX_NAPI | |
92 | static int mv643xx_poll(struct net_device *dev, int *budget); | |
93 | #endif | |
94 | static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr); | |
95 | static int ethernet_phy_detect(unsigned int eth_port_num); | |
96 | static struct ethtool_ops mv643xx_ethtool_ops; | |
97 | ||
98 | static char mv643xx_driver_name[] = "mv643xx_eth"; | |
99 | static char mv643xx_driver_version[] = "1.0"; | |
100 | ||
101 | static void __iomem *mv643xx_eth_shared_base; | |
102 | ||
103 | /* used to protect MV643XX_ETH_SMI_REG, which is shared across ports */ | |
a9f6a0dd | 104 | static DEFINE_SPINLOCK(mv643xx_eth_phy_lock); |
1da177e4 LT |
105 | |
106 | static inline u32 mv_read(int offset) | |
107 | { | |
dc074a8a | 108 | void __iomem *reg_base; |
1da177e4 LT |
109 | |
110 | reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS; | |
111 | ||
112 | return readl(reg_base + offset); | |
113 | } | |
114 | ||
115 | static inline void mv_write(int offset, u32 data) | |
116 | { | |
dc074a8a | 117 | void __iomem *reg_base; |
1da177e4 LT |
118 | |
119 | reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS; | |
120 | writel(data, reg_base + offset); | |
121 | } | |
122 | ||
123 | /* | |
124 | * Changes MTU (maximum transfer unit) of the gigabit ethenret port | |
125 | * | |
126 | * Input : pointer to ethernet interface network device structure | |
127 | * new mtu size | |
128 | * Output : 0 upon success, -EINVAL upon failure | |
129 | */ | |
130 | static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu) | |
131 | { | |
8f518703 | 132 | if ((new_mtu > 9500) || (new_mtu < 64)) |
1da177e4 | 133 | return -EINVAL; |
1da177e4 LT |
134 | |
135 | dev->mtu = new_mtu; | |
136 | /* | |
137 | * Stop then re-open the interface. This will allocate RX skb's with | |
138 | * the new MTU. | |
139 | * There is a possible danger that the open will not successed, due | |
140 | * to memory is full, which might fail the open function. | |
141 | */ | |
142 | if (netif_running(dev)) { | |
ab4384a6 DF |
143 | mv643xx_eth_stop(dev); |
144 | if (mv643xx_eth_open(dev)) | |
1da177e4 LT |
145 | printk(KERN_ERR |
146 | "%s: Fatal error on opening device\n", | |
147 | dev->name); | |
148 | } | |
149 | ||
1da177e4 LT |
150 | return 0; |
151 | } | |
152 | ||
153 | /* | |
154 | * mv643xx_eth_rx_task | |
155 | * | |
156 | * Fills / refills RX queue on a certain gigabit ethernet port | |
157 | * | |
158 | * Input : pointer to ethernet interface network device structure | |
159 | * Output : N/A | |
160 | */ | |
161 | static void mv643xx_eth_rx_task(void *data) | |
162 | { | |
163 | struct net_device *dev = (struct net_device *)data; | |
164 | struct mv643xx_private *mp = netdev_priv(dev); | |
165 | struct pkt_info pkt_info; | |
166 | struct sk_buff *skb; | |
b44cd572 | 167 | int unaligned; |
1da177e4 LT |
168 | |
169 | if (test_and_set_bit(0, &mp->rx_task_busy)) | |
170 | panic("%s: Error in test_set_bit / clear_bit", dev->name); | |
171 | ||
f98e36f1 | 172 | while (mp->rx_desc_count < (mp->rx_ring_size - 5)) { |
b44cd572 | 173 | skb = dev_alloc_skb(RX_SKB_SIZE + DMA_ALIGN); |
1da177e4 LT |
174 | if (!skb) |
175 | break; | |
f98e36f1 | 176 | mp->rx_desc_count++; |
b44cd572 DF |
177 | unaligned = (u32)skb->data & (DMA_ALIGN - 1); |
178 | if (unaligned) | |
179 | skb_reserve(skb, DMA_ALIGN - unaligned); | |
1da177e4 LT |
180 | pkt_info.cmd_sts = ETH_RX_ENABLE_INTERRUPT; |
181 | pkt_info.byte_cnt = RX_SKB_SIZE; | |
182 | pkt_info.buf_ptr = dma_map_single(NULL, skb->data, RX_SKB_SIZE, | |
183 | DMA_FROM_DEVICE); | |
184 | pkt_info.return_info = skb; | |
185 | if (eth_rx_return_buff(mp, &pkt_info) != ETH_OK) { | |
186 | printk(KERN_ERR | |
187 | "%s: Error allocating RX Ring\n", dev->name); | |
188 | break; | |
189 | } | |
b44cd572 | 190 | skb_reserve(skb, HW_IP_ALIGN); |
1da177e4 LT |
191 | } |
192 | clear_bit(0, &mp->rx_task_busy); | |
193 | /* | |
194 | * If RX ring is empty of SKB, set a timer to try allocating | |
195 | * again in a later time . | |
196 | */ | |
f98e36f1 | 197 | if ((mp->rx_desc_count == 0) && (mp->rx_timer_flag == 0)) { |
1da177e4 LT |
198 | printk(KERN_INFO "%s: Rx ring is empty\n", dev->name); |
199 | /* After 100mSec */ | |
200 | mp->timeout.expires = jiffies + (HZ / 10); | |
201 | add_timer(&mp->timeout); | |
202 | mp->rx_timer_flag = 1; | |
203 | } | |
204 | #ifdef MV643XX_RX_QUEUE_FILL_ON_TASK | |
205 | else { | |
206 | /* Return interrupts */ | |
207 | mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(mp->port_num), | |
c2e5b352 | 208 | INT_UNMASK_ALL); |
1da177e4 LT |
209 | } |
210 | #endif | |
211 | } | |
212 | ||
213 | /* | |
214 | * mv643xx_eth_rx_task_timer_wrapper | |
215 | * | |
216 | * Timer routine to wake up RX queue filling task. This function is | |
217 | * used only in case the RX queue is empty, and all alloc_skb has | |
218 | * failed (due to out of memory event). | |
219 | * | |
220 | * Input : pointer to ethernet interface network device structure | |
221 | * Output : N/A | |
222 | */ | |
223 | static void mv643xx_eth_rx_task_timer_wrapper(unsigned long data) | |
224 | { | |
225 | struct net_device *dev = (struct net_device *)data; | |
226 | struct mv643xx_private *mp = netdev_priv(dev); | |
227 | ||
228 | mp->rx_timer_flag = 0; | |
229 | mv643xx_eth_rx_task((void *)data); | |
230 | } | |
231 | ||
232 | /* | |
233 | * mv643xx_eth_update_mac_address | |
234 | * | |
235 | * Update the MAC address of the port in the address table | |
236 | * | |
237 | * Input : pointer to ethernet interface network device structure | |
238 | * Output : N/A | |
239 | */ | |
240 | static void mv643xx_eth_update_mac_address(struct net_device *dev) | |
241 | { | |
242 | struct mv643xx_private *mp = netdev_priv(dev); | |
243 | unsigned int port_num = mp->port_num; | |
244 | ||
245 | eth_port_init_mac_tables(port_num); | |
ed9b5d45 | 246 | eth_port_uc_addr_set(port_num, dev->dev_addr); |
1da177e4 LT |
247 | } |
248 | ||
249 | /* | |
250 | * mv643xx_eth_set_rx_mode | |
251 | * | |
252 | * Change from promiscuos to regular rx mode | |
253 | * | |
254 | * Input : pointer to ethernet interface network device structure | |
255 | * Output : N/A | |
256 | */ | |
257 | static void mv643xx_eth_set_rx_mode(struct net_device *dev) | |
258 | { | |
259 | struct mv643xx_private *mp = netdev_priv(dev); | |
1da177e4 | 260 | |
1da177e4 | 261 | if (dev->flags & IFF_PROMISC) |
7342cd81 | 262 | mp->port_config |= (u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE; |
1da177e4 | 263 | else |
7342cd81 DF |
264 | mp->port_config &= ~(u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE; |
265 | ||
266 | mv_write(MV643XX_ETH_PORT_CONFIG_REG(mp->port_num), mp->port_config); | |
16e03018 DF |
267 | |
268 | eth_port_set_multicast_list(dev); | |
1da177e4 LT |
269 | } |
270 | ||
271 | /* | |
272 | * mv643xx_eth_set_mac_address | |
273 | * | |
274 | * Change the interface's mac address. | |
275 | * No special hardware thing should be done because interface is always | |
276 | * put in promiscuous mode. | |
277 | * | |
278 | * Input : pointer to ethernet interface network device structure and | |
279 | * a pointer to the designated entry to be added to the cache. | |
280 | * Output : zero upon success, negative upon failure | |
281 | */ | |
282 | static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr) | |
283 | { | |
284 | int i; | |
285 | ||
286 | for (i = 0; i < 6; i++) | |
287 | /* +2 is for the offset of the HW addr type */ | |
288 | dev->dev_addr[i] = ((unsigned char *)addr)[i + 2]; | |
289 | mv643xx_eth_update_mac_address(dev); | |
290 | return 0; | |
291 | } | |
292 | ||
293 | /* | |
294 | * mv643xx_eth_tx_timeout | |
295 | * | |
296 | * Called upon a timeout on transmitting a packet | |
297 | * | |
298 | * Input : pointer to ethernet interface network device structure. | |
299 | * Output : N/A | |
300 | */ | |
301 | static void mv643xx_eth_tx_timeout(struct net_device *dev) | |
302 | { | |
303 | struct mv643xx_private *mp = netdev_priv(dev); | |
304 | ||
305 | printk(KERN_INFO "%s: TX timeout ", dev->name); | |
306 | ||
307 | /* Do the reset outside of interrupt context */ | |
308 | schedule_work(&mp->tx_timeout_task); | |
309 | } | |
310 | ||
311 | /* | |
312 | * mv643xx_eth_tx_timeout_task | |
313 | * | |
314 | * Actual routine to reset the adapter when a timeout on Tx has occurred | |
315 | */ | |
316 | static void mv643xx_eth_tx_timeout_task(struct net_device *dev) | |
317 | { | |
318 | struct mv643xx_private *mp = netdev_priv(dev); | |
319 | ||
320 | netif_device_detach(dev); | |
321 | eth_port_reset(mp->port_num); | |
ed9b5d45 | 322 | eth_port_start(dev); |
1da177e4 LT |
323 | netif_device_attach(dev); |
324 | } | |
325 | ||
326 | /* | |
327 | * mv643xx_eth_free_tx_queue | |
328 | * | |
329 | * Input : dev - a pointer to the required interface | |
330 | * | |
331 | * Output : 0 if was able to release skb , nonzero otherwise | |
332 | */ | |
333 | static int mv643xx_eth_free_tx_queue(struct net_device *dev, | |
334 | unsigned int eth_int_cause_ext) | |
335 | { | |
336 | struct mv643xx_private *mp = netdev_priv(dev); | |
337 | struct net_device_stats *stats = &mp->stats; | |
338 | struct pkt_info pkt_info; | |
339 | int released = 1; | |
340 | ||
341 | if (!(eth_int_cause_ext & (BIT0 | BIT8))) | |
342 | return released; | |
343 | ||
1da177e4 LT |
344 | /* Check only queue 0 */ |
345 | while (eth_tx_return_desc(mp, &pkt_info) == ETH_OK) { | |
346 | if (pkt_info.cmd_sts & BIT0) { | |
347 | printk("%s: Error in TX\n", dev->name); | |
348 | stats->tx_errors++; | |
349 | } | |
350 | ||
cb415d30 PG |
351 | if (pkt_info.cmd_sts & ETH_TX_FIRST_DESC) |
352 | dma_unmap_single(NULL, pkt_info.buf_ptr, | |
353 | pkt_info.byte_cnt, | |
354 | DMA_TO_DEVICE); | |
355 | else | |
356 | dma_unmap_page(NULL, pkt_info.buf_ptr, | |
357 | pkt_info.byte_cnt, | |
358 | DMA_TO_DEVICE); | |
1da177e4 | 359 | |
cb415d30 | 360 | if (pkt_info.return_info) { |
1da177e4 LT |
361 | dev_kfree_skb_irq(pkt_info.return_info); |
362 | released = 0; | |
cb415d30 | 363 | } |
1da177e4 LT |
364 | } |
365 | ||
1da177e4 LT |
366 | return released; |
367 | } | |
368 | ||
369 | /* | |
370 | * mv643xx_eth_receive | |
371 | * | |
372 | * This function is forward packets that are received from the port's | |
373 | * queues toward kernel core or FastRoute them to another interface. | |
374 | * | |
375 | * Input : dev - a pointer to the required interface | |
376 | * max - maximum number to receive (0 means unlimted) | |
377 | * | |
378 | * Output : number of served packets | |
379 | */ | |
380 | #ifdef MV643XX_NAPI | |
381 | static int mv643xx_eth_receive_queue(struct net_device *dev, int budget) | |
382 | #else | |
383 | static int mv643xx_eth_receive_queue(struct net_device *dev) | |
384 | #endif | |
385 | { | |
386 | struct mv643xx_private *mp = netdev_priv(dev); | |
387 | struct net_device_stats *stats = &mp->stats; | |
388 | unsigned int received_packets = 0; | |
389 | struct sk_buff *skb; | |
390 | struct pkt_info pkt_info; | |
391 | ||
392 | #ifdef MV643XX_NAPI | |
b1dd9ca1 | 393 | while (budget-- > 0 && eth_port_receive(mp, &pkt_info) == ETH_OK) { |
1da177e4 LT |
394 | #else |
395 | while (eth_port_receive(mp, &pkt_info) == ETH_OK) { | |
396 | #endif | |
f98e36f1 | 397 | mp->rx_desc_count--; |
1da177e4 | 398 | received_packets++; |
b1dd9ca1 | 399 | |
1da177e4 LT |
400 | /* Update statistics. Note byte count includes 4 byte CRC count */ |
401 | stats->rx_packets++; | |
402 | stats->rx_bytes += pkt_info.byte_cnt; | |
403 | skb = pkt_info.return_info; | |
404 | /* | |
405 | * In case received a packet without first / last bits on OR | |
406 | * the error summary bit is on, the packets needs to be dropeed. | |
407 | */ | |
408 | if (((pkt_info.cmd_sts | |
409 | & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) != | |
410 | (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) | |
411 | || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) { | |
412 | stats->rx_dropped++; | |
413 | if ((pkt_info.cmd_sts & (ETH_RX_FIRST_DESC | | |
414 | ETH_RX_LAST_DESC)) != | |
415 | (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) { | |
416 | if (net_ratelimit()) | |
417 | printk(KERN_ERR | |
418 | "%s: Received packet spread " | |
419 | "on multiple descriptors\n", | |
420 | dev->name); | |
421 | } | |
422 | if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) | |
423 | stats->rx_errors++; | |
424 | ||
425 | dev_kfree_skb_irq(skb); | |
426 | } else { | |
427 | /* | |
428 | * The -4 is for the CRC in the trailer of the | |
429 | * received packet | |
430 | */ | |
431 | skb_put(skb, pkt_info.byte_cnt - 4); | |
432 | skb->dev = dev; | |
433 | ||
434 | if (pkt_info.cmd_sts & ETH_LAYER_4_CHECKSUM_OK) { | |
435 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
436 | skb->csum = htons( | |
437 | (pkt_info.cmd_sts & 0x0007fff8) >> 3); | |
438 | } | |
439 | skb->protocol = eth_type_trans(skb, dev); | |
440 | #ifdef MV643XX_NAPI | |
441 | netif_receive_skb(skb); | |
442 | #else | |
443 | netif_rx(skb); | |
444 | #endif | |
445 | } | |
12ad74f8 | 446 | dev->last_rx = jiffies; |
1da177e4 LT |
447 | } |
448 | ||
449 | return received_packets; | |
450 | } | |
451 | ||
452 | /* | |
453 | * mv643xx_eth_int_handler | |
454 | * | |
455 | * Main interrupt handler for the gigbit ethernet ports | |
456 | * | |
457 | * Input : irq - irq number (not used) | |
458 | * dev_id - a pointer to the required interface's data structure | |
459 | * regs - not used | |
460 | * Output : N/A | |
461 | */ | |
462 | ||
463 | static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id, | |
b4de9051 | 464 | struct pt_regs *regs) |
1da177e4 LT |
465 | { |
466 | struct net_device *dev = (struct net_device *)dev_id; | |
467 | struct mv643xx_private *mp = netdev_priv(dev); | |
468 | u32 eth_int_cause, eth_int_cause_ext = 0; | |
469 | unsigned int port_num = mp->port_num; | |
470 | ||
471 | /* Read interrupt cause registers */ | |
472 | eth_int_cause = mv_read(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num)) & | |
c2e5b352 | 473 | INT_UNMASK_ALL; |
1da177e4 LT |
474 | |
475 | if (eth_int_cause & BIT1) | |
476 | eth_int_cause_ext = mv_read( | |
477 | MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num)) & | |
c2e5b352 | 478 | INT_UNMASK_ALL_EXT; |
1da177e4 LT |
479 | |
480 | #ifdef MV643XX_NAPI | |
481 | if (!(eth_int_cause & 0x0007fffd)) { | |
482 | /* Dont ack the Rx interrupt */ | |
483 | #endif | |
484 | /* | |
485 | * Clear specific ethernet port intrerrupt registers by | |
486 | * acknowleding relevant bits. | |
487 | */ | |
488 | mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), | |
489 | ~eth_int_cause); | |
490 | if (eth_int_cause_ext != 0x0) | |
491 | mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG | |
492 | (port_num), ~eth_int_cause_ext); | |
493 | ||
494 | /* UDP change : We may need this */ | |
495 | if ((eth_int_cause_ext & 0x0000ffff) && | |
496 | (mv643xx_eth_free_tx_queue(dev, eth_int_cause_ext) == 0) && | |
f98e36f1 | 497 | (mp->tx_ring_size > mp->tx_desc_count + MAX_DESCS_PER_SKB)) |
1da177e4 LT |
498 | netif_wake_queue(dev); |
499 | #ifdef MV643XX_NAPI | |
500 | } else { | |
501 | if (netif_rx_schedule_prep(dev)) { | |
502 | /* Mask all the interrupts */ | |
c2e5b352 DF |
503 | mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), |
504 | INT_MASK_ALL); | |
505 | /* wait for previous write to complete */ | |
506 | mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num)); | |
1da177e4 LT |
507 | __netif_rx_schedule(dev); |
508 | } | |
509 | #else | |
510 | if (eth_int_cause & (BIT2 | BIT11)) | |
511 | mv643xx_eth_receive_queue(dev, 0); | |
512 | ||
513 | /* | |
514 | * After forwarded received packets to upper layer, add a task | |
515 | * in an interrupts enabled context that refills the RX ring | |
516 | * with skb's. | |
517 | */ | |
518 | #ifdef MV643XX_RX_QUEUE_FILL_ON_TASK | |
c2e5b352 | 519 | /* Mask all interrupts on ethernet port */ |
1da177e4 | 520 | mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), |
c2e5b352 | 521 | INT_MASK_ALL); |
8f518703 DF |
522 | /* wait for previous write to take effect */ |
523 | mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num)); | |
524 | ||
1da177e4 LT |
525 | queue_task(&mp->rx_task, &tq_immediate); |
526 | mark_bh(IMMEDIATE_BH); | |
527 | #else | |
528 | mp->rx_task.func(dev); | |
529 | #endif | |
530 | #endif | |
531 | } | |
532 | /* PHY status changed */ | |
533 | if (eth_int_cause_ext & (BIT16 | BIT20)) { | |
534 | if (eth_port_link_is_up(port_num)) { | |
535 | netif_carrier_on(dev); | |
536 | netif_wake_queue(dev); | |
537 | /* Start TX queue */ | |
538 | mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG | |
539 | (port_num), 1); | |
540 | } else { | |
541 | netif_carrier_off(dev); | |
542 | netif_stop_queue(dev); | |
543 | } | |
544 | } | |
545 | ||
546 | /* | |
547 | * If no real interrupt occured, exit. | |
548 | * This can happen when using gigE interrupt coalescing mechanism. | |
549 | */ | |
550 | if ((eth_int_cause == 0x0) && (eth_int_cause_ext == 0x0)) | |
551 | return IRQ_NONE; | |
552 | ||
553 | return IRQ_HANDLED; | |
554 | } | |
555 | ||
556 | #ifdef MV643XX_COAL | |
557 | ||
558 | /* | |
559 | * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path | |
560 | * | |
561 | * DESCRIPTION: | |
562 | * This routine sets the RX coalescing interrupt mechanism parameter. | |
563 | * This parameter is a timeout counter, that counts in 64 t_clk | |
564 | * chunks ; that when timeout event occurs a maskable interrupt | |
565 | * occurs. | |
566 | * The parameter is calculated using the tClk of the MV-643xx chip | |
567 | * , and the required delay of the interrupt in usec. | |
568 | * | |
569 | * INPUT: | |
570 | * unsigned int eth_port_num Ethernet port number | |
571 | * unsigned int t_clk t_clk of the MV-643xx chip in HZ units | |
572 | * unsigned int delay Delay in usec | |
573 | * | |
574 | * OUTPUT: | |
575 | * Interrupt coalescing mechanism value is set in MV-643xx chip. | |
576 | * | |
577 | * RETURN: | |
578 | * The interrupt coalescing value set in the gigE port. | |
579 | * | |
580 | */ | |
581 | static unsigned int eth_port_set_rx_coal(unsigned int eth_port_num, | |
582 | unsigned int t_clk, unsigned int delay) | |
583 | { | |
584 | unsigned int coal = ((t_clk / 1000000) * delay) / 64; | |
585 | ||
586 | /* Set RX Coalescing mechanism */ | |
587 | mv_write(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num), | |
588 | ((coal & 0x3fff) << 8) | | |
589 | (mv_read(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num)) | |
590 | & 0xffc000ff)); | |
591 | ||
592 | return coal; | |
593 | } | |
594 | #endif | |
595 | ||
596 | /* | |
597 | * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path | |
598 | * | |
599 | * DESCRIPTION: | |
600 | * This routine sets the TX coalescing interrupt mechanism parameter. | |
601 | * This parameter is a timeout counter, that counts in 64 t_clk | |
602 | * chunks ; that when timeout event occurs a maskable interrupt | |
603 | * occurs. | |
604 | * The parameter is calculated using the t_cLK frequency of the | |
605 | * MV-643xx chip and the required delay in the interrupt in uSec | |
606 | * | |
607 | * INPUT: | |
608 | * unsigned int eth_port_num Ethernet port number | |
609 | * unsigned int t_clk t_clk of the MV-643xx chip in HZ units | |
610 | * unsigned int delay Delay in uSeconds | |
611 | * | |
612 | * OUTPUT: | |
613 | * Interrupt coalescing mechanism value is set in MV-643xx chip. | |
614 | * | |
615 | * RETURN: | |
616 | * The interrupt coalescing value set in the gigE port. | |
617 | * | |
618 | */ | |
619 | static unsigned int eth_port_set_tx_coal(unsigned int eth_port_num, | |
620 | unsigned int t_clk, unsigned int delay) | |
621 | { | |
622 | unsigned int coal; | |
623 | coal = ((t_clk / 1000000) * delay) / 64; | |
624 | /* Set TX Coalescing mechanism */ | |
625 | mv_write(MV643XX_ETH_TX_FIFO_URGENT_THRESHOLD_REG(eth_port_num), | |
626 | coal << 4); | |
627 | return coal; | |
628 | } | |
629 | ||
1da177e4 LT |
630 | /* |
631 | * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory. | |
632 | * | |
633 | * DESCRIPTION: | |
634 | * This function prepares a Rx chained list of descriptors and packet | |
635 | * buffers in a form of a ring. The routine must be called after port | |
636 | * initialization routine and before port start routine. | |
637 | * The Ethernet SDMA engine uses CPU bus addresses to access the various | |
638 | * devices in the system (i.e. DRAM). This function uses the ethernet | |
639 | * struct 'virtual to physical' routine (set by the user) to set the ring | |
640 | * with physical addresses. | |
641 | * | |
642 | * INPUT: | |
643 | * struct mv643xx_private *mp Ethernet Port Control srtuct. | |
644 | * | |
645 | * OUTPUT: | |
646 | * The routine updates the Ethernet port control struct with information | |
647 | * regarding the Rx descriptors and buffers. | |
648 | * | |
649 | * RETURN: | |
650 | * None. | |
651 | */ | |
652 | static void ether_init_rx_desc_ring(struct mv643xx_private *mp) | |
653 | { | |
654 | volatile struct eth_rx_desc *p_rx_desc; | |
655 | int rx_desc_num = mp->rx_ring_size; | |
656 | int i; | |
657 | ||
658 | /* initialize the next_desc_ptr links in the Rx descriptors ring */ | |
659 | p_rx_desc = (struct eth_rx_desc *)mp->p_rx_desc_area; | |
660 | for (i = 0; i < rx_desc_num; i++) { | |
661 | p_rx_desc[i].next_desc_ptr = mp->rx_desc_dma + | |
662 | ((i + 1) % rx_desc_num) * sizeof(struct eth_rx_desc); | |
663 | } | |
664 | ||
665 | /* Save Rx desc pointer to driver struct. */ | |
666 | mp->rx_curr_desc_q = 0; | |
667 | mp->rx_used_desc_q = 0; | |
668 | ||
669 | mp->rx_desc_area_size = rx_desc_num * sizeof(struct eth_rx_desc); | |
670 | ||
671 | /* Add the queue to the list of RX queues of this port */ | |
672 | mp->port_rx_queue_command |= 1; | |
673 | } | |
674 | ||
675 | /* | |
676 | * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory. | |
677 | * | |
678 | * DESCRIPTION: | |
679 | * This function prepares a Tx chained list of descriptors and packet | |
680 | * buffers in a form of a ring. The routine must be called after port | |
681 | * initialization routine and before port start routine. | |
682 | * The Ethernet SDMA engine uses CPU bus addresses to access the various | |
683 | * devices in the system (i.e. DRAM). This function uses the ethernet | |
684 | * struct 'virtual to physical' routine (set by the user) to set the ring | |
685 | * with physical addresses. | |
686 | * | |
687 | * INPUT: | |
688 | * struct mv643xx_private *mp Ethernet Port Control srtuct. | |
689 | * | |
690 | * OUTPUT: | |
691 | * The routine updates the Ethernet port control struct with information | |
692 | * regarding the Tx descriptors and buffers. | |
693 | * | |
694 | * RETURN: | |
695 | * None. | |
696 | */ | |
697 | static void ether_init_tx_desc_ring(struct mv643xx_private *mp) | |
698 | { | |
699 | int tx_desc_num = mp->tx_ring_size; | |
700 | struct eth_tx_desc *p_tx_desc; | |
701 | int i; | |
702 | ||
703 | /* Initialize the next_desc_ptr links in the Tx descriptors ring */ | |
704 | p_tx_desc = (struct eth_tx_desc *)mp->p_tx_desc_area; | |
705 | for (i = 0; i < tx_desc_num; i++) { | |
706 | p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma + | |
707 | ((i + 1) % tx_desc_num) * sizeof(struct eth_tx_desc); | |
708 | } | |
709 | ||
710 | mp->tx_curr_desc_q = 0; | |
711 | mp->tx_used_desc_q = 0; | |
712 | #ifdef MV643XX_CHECKSUM_OFFLOAD_TX | |
713 | mp->tx_first_desc_q = 0; | |
714 | #endif | |
715 | ||
716 | mp->tx_desc_area_size = tx_desc_num * sizeof(struct eth_tx_desc); | |
717 | ||
718 | /* Add the queue to the list of Tx queues of this port */ | |
719 | mp->port_tx_queue_command |= 1; | |
720 | } | |
721 | ||
ab4384a6 DF |
722 | /* |
723 | * mv643xx_eth_open | |
724 | * | |
725 | * This function is called when openning the network device. The function | |
726 | * should initialize all the hardware, initialize cyclic Rx/Tx | |
727 | * descriptors chain and buffers and allocate an IRQ to the network | |
728 | * device. | |
729 | * | |
730 | * Input : a pointer to the network device structure | |
731 | * | |
732 | * Output : zero of success , nonzero if fails. | |
733 | */ | |
734 | ||
735 | static int mv643xx_eth_open(struct net_device *dev) | |
1da177e4 LT |
736 | { |
737 | struct mv643xx_private *mp = netdev_priv(dev); | |
738 | unsigned int port_num = mp->port_num; | |
739 | unsigned int size; | |
ab4384a6 DF |
740 | int err; |
741 | ||
742 | err = request_irq(dev->irq, mv643xx_eth_int_handler, | |
743 | SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev); | |
744 | if (err) { | |
745 | printk(KERN_ERR "Can not assign IRQ number to MV643XX_eth%d\n", | |
746 | port_num); | |
747 | return -EAGAIN; | |
748 | } | |
1da177e4 LT |
749 | |
750 | /* Stop RX Queues */ | |
751 | mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), 0x0000ff00); | |
752 | ||
1da177e4 LT |
753 | eth_port_init(mp); |
754 | ||
755 | INIT_WORK(&mp->rx_task, (void (*)(void *))mv643xx_eth_rx_task, dev); | |
756 | ||
757 | memset(&mp->timeout, 0, sizeof(struct timer_list)); | |
758 | mp->timeout.function = mv643xx_eth_rx_task_timer_wrapper; | |
759 | mp->timeout.data = (unsigned long)dev; | |
760 | ||
761 | mp->rx_task_busy = 0; | |
762 | mp->rx_timer_flag = 0; | |
763 | ||
764 | /* Allocate RX and TX skb rings */ | |
765 | mp->rx_skb = kmalloc(sizeof(*mp->rx_skb) * mp->rx_ring_size, | |
766 | GFP_KERNEL); | |
767 | if (!mp->rx_skb) { | |
768 | printk(KERN_ERR "%s: Cannot allocate Rx skb ring\n", dev->name); | |
ab4384a6 DF |
769 | err = -ENOMEM; |
770 | goto out_free_irq; | |
1da177e4 LT |
771 | } |
772 | mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size, | |
773 | GFP_KERNEL); | |
774 | if (!mp->tx_skb) { | |
775 | printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name); | |
ab4384a6 DF |
776 | err = -ENOMEM; |
777 | goto out_free_rx_skb; | |
1da177e4 LT |
778 | } |
779 | ||
780 | /* Allocate TX ring */ | |
f98e36f1 | 781 | mp->tx_desc_count = 0; |
1da177e4 LT |
782 | size = mp->tx_ring_size * sizeof(struct eth_tx_desc); |
783 | mp->tx_desc_area_size = size; | |
784 | ||
785 | if (mp->tx_sram_size) { | |
786 | mp->p_tx_desc_area = ioremap(mp->tx_sram_addr, | |
787 | mp->tx_sram_size); | |
788 | mp->tx_desc_dma = mp->tx_sram_addr; | |
789 | } else | |
790 | mp->p_tx_desc_area = dma_alloc_coherent(NULL, size, | |
791 | &mp->tx_desc_dma, | |
792 | GFP_KERNEL); | |
793 | ||
794 | if (!mp->p_tx_desc_area) { | |
795 | printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n", | |
796 | dev->name, size); | |
ab4384a6 DF |
797 | err = -ENOMEM; |
798 | goto out_free_tx_skb; | |
1da177e4 LT |
799 | } |
800 | BUG_ON((u32) mp->p_tx_desc_area & 0xf); /* check 16-byte alignment */ | |
801 | memset((void *)mp->p_tx_desc_area, 0, mp->tx_desc_area_size); | |
802 | ||
803 | ether_init_tx_desc_ring(mp); | |
804 | ||
805 | /* Allocate RX ring */ | |
f98e36f1 | 806 | mp->rx_desc_count = 0; |
1da177e4 LT |
807 | size = mp->rx_ring_size * sizeof(struct eth_rx_desc); |
808 | mp->rx_desc_area_size = size; | |
809 | ||
810 | if (mp->rx_sram_size) { | |
811 | mp->p_rx_desc_area = ioremap(mp->rx_sram_addr, | |
812 | mp->rx_sram_size); | |
813 | mp->rx_desc_dma = mp->rx_sram_addr; | |
814 | } else | |
815 | mp->p_rx_desc_area = dma_alloc_coherent(NULL, size, | |
816 | &mp->rx_desc_dma, | |
817 | GFP_KERNEL); | |
818 | ||
819 | if (!mp->p_rx_desc_area) { | |
820 | printk(KERN_ERR "%s: Cannot allocate Rx ring (size %d bytes)\n", | |
821 | dev->name, size); | |
822 | printk(KERN_ERR "%s: Freeing previously allocated TX queues...", | |
823 | dev->name); | |
824 | if (mp->rx_sram_size) | |
dd09b1de | 825 | iounmap(mp->p_tx_desc_area); |
1da177e4 LT |
826 | else |
827 | dma_free_coherent(NULL, mp->tx_desc_area_size, | |
828 | mp->p_tx_desc_area, mp->tx_desc_dma); | |
ab4384a6 DF |
829 | err = -ENOMEM; |
830 | goto out_free_tx_skb; | |
1da177e4 LT |
831 | } |
832 | memset((void *)mp->p_rx_desc_area, 0, size); | |
833 | ||
834 | ether_init_rx_desc_ring(mp); | |
835 | ||
836 | mv643xx_eth_rx_task(dev); /* Fill RX ring with skb's */ | |
837 | ||
ed9b5d45 | 838 | eth_port_start(dev); |
1da177e4 LT |
839 | |
840 | /* Interrupt Coalescing */ | |
841 | ||
842 | #ifdef MV643XX_COAL | |
843 | mp->rx_int_coal = | |
844 | eth_port_set_rx_coal(port_num, 133000000, MV643XX_RX_COAL); | |
845 | #endif | |
846 | ||
847 | mp->tx_int_coal = | |
848 | eth_port_set_tx_coal(port_num, 133000000, MV643XX_TX_COAL); | |
849 | ||
8f518703 DF |
850 | /* Clear any pending ethernet port interrupts */ |
851 | mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0); | |
852 | mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0); | |
853 | ||
854 | /* Unmask phy and link status changes interrupts */ | |
855 | mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num), | |
c2e5b352 | 856 | INT_UNMASK_ALL_EXT); |
1da177e4 | 857 | |
8f518703 | 858 | /* Unmask RX buffer and TX end interrupt */ |
c2e5b352 | 859 | mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), INT_UNMASK_ALL); |
1da177e4 | 860 | return 0; |
ab4384a6 DF |
861 | |
862 | out_free_tx_skb: | |
863 | kfree(mp->tx_skb); | |
864 | out_free_rx_skb: | |
865 | kfree(mp->rx_skb); | |
866 | out_free_irq: | |
867 | free_irq(dev->irq, dev); | |
868 | ||
869 | return err; | |
1da177e4 LT |
870 | } |
871 | ||
872 | static void mv643xx_eth_free_tx_rings(struct net_device *dev) | |
873 | { | |
874 | struct mv643xx_private *mp = netdev_priv(dev); | |
875 | unsigned int port_num = mp->port_num; | |
876 | unsigned int curr; | |
4476e0e4 | 877 | struct sk_buff *skb; |
1da177e4 LT |
878 | |
879 | /* Stop Tx Queues */ | |
880 | mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num), 0x0000ff00); | |
881 | ||
882 | /* Free outstanding skb's on TX rings */ | |
f98e36f1 | 883 | for (curr = 0; mp->tx_desc_count && curr < mp->tx_ring_size; curr++) { |
4476e0e4 DF |
884 | skb = mp->tx_skb[curr]; |
885 | if (skb) { | |
f98e36f1 | 886 | mp->tx_desc_count -= skb_shinfo(skb)->nr_frags; |
4476e0e4 | 887 | dev_kfree_skb(skb); |
f98e36f1 | 888 | mp->tx_desc_count--; |
1da177e4 LT |
889 | } |
890 | } | |
f98e36f1 | 891 | if (mp->tx_desc_count) |
1da177e4 | 892 | printk("%s: Error on Tx descriptor free - could not free %d" |
f98e36f1 | 893 | " descriptors\n", dev->name, mp->tx_desc_count); |
1da177e4 LT |
894 | |
895 | /* Free TX ring */ | |
896 | if (mp->tx_sram_size) | |
897 | iounmap(mp->p_tx_desc_area); | |
898 | else | |
899 | dma_free_coherent(NULL, mp->tx_desc_area_size, | |
900 | mp->p_tx_desc_area, mp->tx_desc_dma); | |
901 | } | |
902 | ||
903 | static void mv643xx_eth_free_rx_rings(struct net_device *dev) | |
904 | { | |
905 | struct mv643xx_private *mp = netdev_priv(dev); | |
906 | unsigned int port_num = mp->port_num; | |
907 | int curr; | |
908 | ||
909 | /* Stop RX Queues */ | |
910 | mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), 0x0000ff00); | |
911 | ||
912 | /* Free preallocated skb's on RX rings */ | |
f98e36f1 | 913 | for (curr = 0; mp->rx_desc_count && curr < mp->rx_ring_size; curr++) { |
1da177e4 LT |
914 | if (mp->rx_skb[curr]) { |
915 | dev_kfree_skb(mp->rx_skb[curr]); | |
f98e36f1 | 916 | mp->rx_desc_count--; |
1da177e4 LT |
917 | } |
918 | } | |
919 | ||
f98e36f1 | 920 | if (mp->rx_desc_count) |
1da177e4 LT |
921 | printk(KERN_ERR |
922 | "%s: Error in freeing Rx Ring. %d skb's still" | |
923 | " stuck in RX Ring - ignoring them\n", dev->name, | |
f98e36f1 | 924 | mp->rx_desc_count); |
1da177e4 LT |
925 | /* Free RX ring */ |
926 | if (mp->rx_sram_size) | |
927 | iounmap(mp->p_rx_desc_area); | |
928 | else | |
929 | dma_free_coherent(NULL, mp->rx_desc_area_size, | |
930 | mp->p_rx_desc_area, mp->rx_desc_dma); | |
931 | } | |
932 | ||
933 | /* | |
934 | * mv643xx_eth_stop | |
935 | * | |
936 | * This function is used when closing the network device. | |
937 | * It updates the hardware, | |
938 | * release all memory that holds buffers and descriptors and release the IRQ. | |
939 | * Input : a pointer to the device structure | |
940 | * Output : zero if success , nonzero if fails | |
941 | */ | |
942 | ||
ab4384a6 | 943 | static int mv643xx_eth_stop(struct net_device *dev) |
1da177e4 LT |
944 | { |
945 | struct mv643xx_private *mp = netdev_priv(dev); | |
946 | unsigned int port_num = mp->port_num; | |
947 | ||
c2e5b352 DF |
948 | /* Mask all interrupts on ethernet port */ |
949 | mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), INT_MASK_ALL); | |
950 | /* wait for previous write to complete */ | |
8f518703 DF |
951 | mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num)); |
952 | ||
953 | #ifdef MV643XX_NAPI | |
954 | netif_poll_disable(dev); | |
955 | #endif | |
1da177e4 LT |
956 | netif_carrier_off(dev); |
957 | netif_stop_queue(dev); | |
958 | ||
1da177e4 LT |
959 | eth_port_reset(mp->port_num); |
960 | ||
8f518703 DF |
961 | mv643xx_eth_free_tx_rings(dev); |
962 | mv643xx_eth_free_rx_rings(dev); | |
1da177e4 | 963 | |
8f518703 DF |
964 | #ifdef MV643XX_NAPI |
965 | netif_poll_enable(dev); | |
966 | #endif | |
1da177e4 | 967 | |
1da177e4 | 968 | free_irq(dev->irq, dev); |
1da177e4 LT |
969 | |
970 | return 0; | |
971 | } | |
972 | ||
973 | #ifdef MV643XX_NAPI | |
974 | static void mv643xx_tx(struct net_device *dev) | |
975 | { | |
976 | struct mv643xx_private *mp = netdev_priv(dev); | |
977 | struct pkt_info pkt_info; | |
978 | ||
979 | while (eth_tx_return_desc(mp, &pkt_info) == ETH_OK) { | |
cb415d30 PG |
980 | if (pkt_info.cmd_sts & ETH_TX_FIRST_DESC) |
981 | dma_unmap_single(NULL, pkt_info.buf_ptr, | |
982 | pkt_info.byte_cnt, | |
983 | DMA_TO_DEVICE); | |
984 | else | |
985 | dma_unmap_page(NULL, pkt_info.buf_ptr, | |
986 | pkt_info.byte_cnt, | |
987 | DMA_TO_DEVICE); | |
1da177e4 | 988 | |
cb415d30 | 989 | if (pkt_info.return_info) |
1da177e4 | 990 | dev_kfree_skb_irq(pkt_info.return_info); |
1da177e4 LT |
991 | } |
992 | ||
993 | if (netif_queue_stopped(dev) && | |
f98e36f1 DF |
994 | mp->tx_ring_size > |
995 | mp->tx_desc_count + MAX_DESCS_PER_SKB) | |
1da177e4 LT |
996 | netif_wake_queue(dev); |
997 | } | |
998 | ||
999 | /* | |
1000 | * mv643xx_poll | |
1001 | * | |
1002 | * This function is used in case of NAPI | |
1003 | */ | |
1004 | static int mv643xx_poll(struct net_device *dev, int *budget) | |
1005 | { | |
1006 | struct mv643xx_private *mp = netdev_priv(dev); | |
1007 | int done = 1, orig_budget, work_done; | |
1008 | unsigned int port_num = mp->port_num; | |
1da177e4 LT |
1009 | |
1010 | #ifdef MV643XX_TX_FAST_REFILL | |
1011 | if (++mp->tx_clean_threshold > 5) { | |
1da177e4 LT |
1012 | mv643xx_tx(dev); |
1013 | mp->tx_clean_threshold = 0; | |
1da177e4 LT |
1014 | } |
1015 | #endif | |
1016 | ||
1017 | if ((mv_read(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num))) | |
1018 | != (u32) mp->rx_used_desc_q) { | |
1019 | orig_budget = *budget; | |
1020 | if (orig_budget > dev->quota) | |
1021 | orig_budget = dev->quota; | |
1022 | work_done = mv643xx_eth_receive_queue(dev, orig_budget); | |
1023 | mp->rx_task.func(dev); | |
1024 | *budget -= work_done; | |
1025 | dev->quota -= work_done; | |
1026 | if (work_done >= orig_budget) | |
1027 | done = 0; | |
1028 | } | |
1029 | ||
1030 | if (done) { | |
8f518703 | 1031 | netif_rx_complete(dev); |
1da177e4 LT |
1032 | mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0); |
1033 | mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0); | |
1034 | mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), | |
c2e5b352 | 1035 | INT_UNMASK_ALL); |
1da177e4 LT |
1036 | } |
1037 | ||
1038 | return done ? 0 : 1; | |
1039 | } | |
1040 | #endif | |
1041 | ||
f7ea3337 PJ |
1042 | /* Hardware can't handle unaligned fragments smaller than 9 bytes. |
1043 | * This helper function detects that case. | |
1044 | */ | |
1045 | ||
1046 | static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb) | |
1047 | { | |
b4de9051 DF |
1048 | unsigned int frag; |
1049 | skb_frag_t *fragp; | |
f7ea3337 | 1050 | |
b4de9051 DF |
1051 | for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { |
1052 | fragp = &skb_shinfo(skb)->frags[frag]; | |
1053 | if (fragp->size <= 8 && fragp->page_offset & 0x7) | |
1054 | return 1; | |
1055 | } | |
1056 | return 0; | |
f7ea3337 PJ |
1057 | } |
1058 | ||
1059 | ||
1da177e4 LT |
1060 | /* |
1061 | * mv643xx_eth_start_xmit | |
1062 | * | |
1063 | * This function is queues a packet in the Tx descriptor for | |
1064 | * required port. | |
1065 | * | |
1066 | * Input : skb - a pointer to socket buffer | |
1067 | * dev - a pointer to the required port | |
1068 | * | |
1069 | * Output : zero upon success | |
1070 | */ | |
1071 | static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
1072 | { | |
1073 | struct mv643xx_private *mp = netdev_priv(dev); | |
1074 | struct net_device_stats *stats = &mp->stats; | |
1075 | ETH_FUNC_RET_STATUS status; | |
1076 | unsigned long flags; | |
1077 | struct pkt_info pkt_info; | |
1078 | ||
1079 | if (netif_queue_stopped(dev)) { | |
1080 | printk(KERN_ERR | |
1081 | "%s: Tried sending packet when interface is stopped\n", | |
1082 | dev->name); | |
1083 | return 1; | |
1084 | } | |
1085 | ||
1086 | /* This is a hard error, log it. */ | |
f98e36f1 | 1087 | if ((mp->tx_ring_size - mp->tx_desc_count) <= |
1da177e4 LT |
1088 | (skb_shinfo(skb)->nr_frags + 1)) { |
1089 | netif_stop_queue(dev); | |
1090 | printk(KERN_ERR | |
1091 | "%s: Bug in mv643xx_eth - Trying to transmit when" | |
1092 | " queue full !\n", dev->name); | |
1093 | return 1; | |
1094 | } | |
1095 | ||
1096 | /* Paranoid check - this shouldn't happen */ | |
1097 | if (skb == NULL) { | |
1098 | stats->tx_dropped++; | |
1099 | printk(KERN_ERR "mv64320_eth paranoid check failed\n"); | |
1100 | return 1; | |
1101 | } | |
1102 | ||
f7ea3337 PJ |
1103 | #ifdef MV643XX_CHECKSUM_OFFLOAD_TX |
1104 | if (has_tiny_unaligned_frags(skb)) { | |
1105 | if ((skb_linearize(skb, GFP_ATOMIC) != 0)) { | |
1106 | stats->tx_dropped++; | |
1107 | printk(KERN_DEBUG "%s: failed to linearize tiny " | |
1108 | "unaligned fragment\n", dev->name); | |
1109 | return 1; | |
1110 | } | |
1111 | } | |
1112 | ||
1da177e4 LT |
1113 | spin_lock_irqsave(&mp->lock, flags); |
1114 | ||
1da177e4 | 1115 | if (!skb_shinfo(skb)->nr_frags) { |
1da177e4 | 1116 | if (skb->ip_summed != CHECKSUM_HW) { |
26006360 | 1117 | /* Errata BTS #50, IHL must be 5 if no HW checksum */ |
1da177e4 | 1118 | pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT | |
26006360 DF |
1119 | ETH_TX_FIRST_DESC | |
1120 | ETH_TX_LAST_DESC | | |
1121 | 5 << ETH_TX_IHL_SHIFT; | |
1da177e4 LT |
1122 | pkt_info.l4i_chk = 0; |
1123 | } else { | |
1da177e4 | 1124 | pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT | |
26006360 DF |
1125 | ETH_TX_FIRST_DESC | |
1126 | ETH_TX_LAST_DESC | | |
1127 | ETH_GEN_TCP_UDP_CHECKSUM | | |
1128 | ETH_GEN_IP_V_4_CHECKSUM | | |
1129 | skb->nh.iph->ihl << ETH_TX_IHL_SHIFT; | |
1da177e4 | 1130 | /* CPU already calculated pseudo header checksum. */ |
63890576 WJ |
1131 | if ((skb->protocol == ETH_P_IP) && |
1132 | (skb->nh.iph->protocol == IPPROTO_UDP) ) { | |
1da177e4 LT |
1133 | pkt_info.cmd_sts |= ETH_UDP_FRAME; |
1134 | pkt_info.l4i_chk = skb->h.uh->check; | |
63890576 WJ |
1135 | } else if ((skb->protocol == ETH_P_IP) && |
1136 | (skb->nh.iph->protocol == IPPROTO_TCP)) | |
1da177e4 LT |
1137 | pkt_info.l4i_chk = skb->h.th->check; |
1138 | else { | |
1139 | printk(KERN_ERR | |
63890576 | 1140 | "%s: chksum proto != IPv4 TCP or UDP\n", |
1da177e4 LT |
1141 | dev->name); |
1142 | spin_unlock_irqrestore(&mp->lock, flags); | |
1143 | return 1; | |
1144 | } | |
1145 | } | |
1146 | pkt_info.byte_cnt = skb->len; | |
1147 | pkt_info.buf_ptr = dma_map_single(NULL, skb->data, skb->len, | |
1148 | DMA_TO_DEVICE); | |
1149 | pkt_info.return_info = skb; | |
1da177e4 LT |
1150 | status = eth_port_send(mp, &pkt_info); |
1151 | if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) | |
1152 | printk(KERN_ERR "%s: Error on transmitting packet\n", | |
1153 | dev->name); | |
1154 | stats->tx_bytes += pkt_info.byte_cnt; | |
1155 | } else { | |
1156 | unsigned int frag; | |
1da177e4 | 1157 | |
1da177e4 LT |
1158 | /* first frag which is skb header */ |
1159 | pkt_info.byte_cnt = skb_headlen(skb); | |
1160 | pkt_info.buf_ptr = dma_map_single(NULL, skb->data, | |
1161 | skb_headlen(skb), | |
1162 | DMA_TO_DEVICE); | |
1163 | pkt_info.l4i_chk = 0; | |
1164 | pkt_info.return_info = 0; | |
1da177e4 | 1165 | |
26006360 DF |
1166 | if (skb->ip_summed != CHECKSUM_HW) |
1167 | /* Errata BTS #50, IHL must be 5 if no HW checksum */ | |
1168 | pkt_info.cmd_sts = ETH_TX_FIRST_DESC | | |
1169 | 5 << ETH_TX_IHL_SHIFT; | |
1170 | else { | |
1171 | pkt_info.cmd_sts = ETH_TX_FIRST_DESC | | |
1172 | ETH_GEN_TCP_UDP_CHECKSUM | | |
1173 | ETH_GEN_IP_V_4_CHECKSUM | | |
1174 | skb->nh.iph->ihl << ETH_TX_IHL_SHIFT; | |
1da177e4 | 1175 | /* CPU already calculated pseudo header checksum. */ |
63890576 WJ |
1176 | if ((skb->protocol == ETH_P_IP) && |
1177 | (skb->nh.iph->protocol == IPPROTO_UDP)) { | |
1da177e4 LT |
1178 | pkt_info.cmd_sts |= ETH_UDP_FRAME; |
1179 | pkt_info.l4i_chk = skb->h.uh->check; | |
63890576 WJ |
1180 | } else if ((skb->protocol == ETH_P_IP) && |
1181 | (skb->nh.iph->protocol == IPPROTO_TCP)) | |
1da177e4 LT |
1182 | pkt_info.l4i_chk = skb->h.th->check; |
1183 | else { | |
1184 | printk(KERN_ERR | |
63890576 | 1185 | "%s: chksum proto != IPv4 TCP or UDP\n", |
1da177e4 LT |
1186 | dev->name); |
1187 | spin_unlock_irqrestore(&mp->lock, flags); | |
1188 | return 1; | |
1189 | } | |
1190 | } | |
1191 | ||
1192 | status = eth_port_send(mp, &pkt_info); | |
1193 | if (status != ETH_OK) { | |
1194 | if ((status == ETH_ERROR)) | |
1195 | printk(KERN_ERR | |
1196 | "%s: Error on transmitting packet\n", | |
1197 | dev->name); | |
1198 | if (status == ETH_QUEUE_FULL) | |
1199 | printk("Error on Queue Full \n"); | |
1200 | if (status == ETH_QUEUE_LAST_RESOURCE) | |
1201 | printk("Tx resource error \n"); | |
1202 | } | |
1203 | stats->tx_bytes += pkt_info.byte_cnt; | |
1204 | ||
1205 | /* Check for the remaining frags */ | |
1206 | for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { | |
1207 | skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag]; | |
1208 | pkt_info.l4i_chk = 0x0000; | |
1209 | pkt_info.cmd_sts = 0x00000000; | |
1210 | ||
1211 | /* Last Frag enables interrupt and frees the skb */ | |
1212 | if (frag == (skb_shinfo(skb)->nr_frags - 1)) { | |
1213 | pkt_info.cmd_sts |= ETH_TX_ENABLE_INTERRUPT | | |
1214 | ETH_TX_LAST_DESC; | |
1215 | pkt_info.return_info = skb; | |
1da177e4 LT |
1216 | } else { |
1217 | pkt_info.return_info = 0; | |
1218 | } | |
1219 | pkt_info.l4i_chk = 0; | |
1220 | pkt_info.byte_cnt = this_frag->size; | |
1221 | ||
1222 | pkt_info.buf_ptr = dma_map_page(NULL, this_frag->page, | |
1223 | this_frag->page_offset, | |
1224 | this_frag->size, | |
1225 | DMA_TO_DEVICE); | |
1226 | ||
1227 | status = eth_port_send(mp, &pkt_info); | |
1228 | ||
1229 | if (status != ETH_OK) { | |
1230 | if ((status == ETH_ERROR)) | |
1231 | printk(KERN_ERR "%s: Error on " | |
1232 | "transmitting packet\n", | |
1233 | dev->name); | |
1234 | ||
1235 | if (status == ETH_QUEUE_LAST_RESOURCE) | |
1236 | printk("Tx resource error \n"); | |
1237 | ||
1238 | if (status == ETH_QUEUE_FULL) | |
1239 | printk("Queue is full \n"); | |
1240 | } | |
1241 | stats->tx_bytes += pkt_info.byte_cnt; | |
1242 | } | |
1243 | } | |
1244 | #else | |
f7ea3337 PJ |
1245 | spin_lock_irqsave(&mp->lock, flags); |
1246 | ||
1da177e4 LT |
1247 | pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT | ETH_TX_FIRST_DESC | |
1248 | ETH_TX_LAST_DESC; | |
1249 | pkt_info.l4i_chk = 0; | |
1250 | pkt_info.byte_cnt = skb->len; | |
1251 | pkt_info.buf_ptr = dma_map_single(NULL, skb->data, skb->len, | |
1252 | DMA_TO_DEVICE); | |
1253 | pkt_info.return_info = skb; | |
1da177e4 LT |
1254 | status = eth_port_send(mp, &pkt_info); |
1255 | if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) | |
1256 | printk(KERN_ERR "%s: Error on transmitting packet\n", | |
1257 | dev->name); | |
1258 | stats->tx_bytes += pkt_info.byte_cnt; | |
1259 | #endif | |
1260 | ||
1261 | /* Check if TX queue can handle another skb. If not, then | |
1262 | * signal higher layers to stop requesting TX | |
1263 | */ | |
f98e36f1 | 1264 | if (mp->tx_ring_size <= (mp->tx_desc_count + MAX_DESCS_PER_SKB)) |
1da177e4 LT |
1265 | /* |
1266 | * Stop getting skb's from upper layers. | |
1267 | * Getting skb's from upper layers will be enabled again after | |
1268 | * packets are released. | |
1269 | */ | |
1270 | netif_stop_queue(dev); | |
1271 | ||
1272 | /* Update statistics and start of transmittion time */ | |
1273 | stats->tx_packets++; | |
1274 | dev->trans_start = jiffies; | |
1275 | ||
1276 | spin_unlock_irqrestore(&mp->lock, flags); | |
1277 | ||
1278 | return 0; /* success */ | |
1279 | } | |
1280 | ||
1281 | /* | |
1282 | * mv643xx_eth_get_stats | |
1283 | * | |
1284 | * Returns a pointer to the interface statistics. | |
1285 | * | |
1286 | * Input : dev - a pointer to the required interface | |
1287 | * | |
1288 | * Output : a pointer to the interface's statistics | |
1289 | */ | |
1290 | ||
1291 | static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev) | |
1292 | { | |
1293 | struct mv643xx_private *mp = netdev_priv(dev); | |
1294 | ||
1295 | return &mp->stats; | |
1296 | } | |
1297 | ||
63c9e549 | 1298 | #ifdef CONFIG_NET_POLL_CONTROLLER |
63c9e549 DF |
1299 | static void mv643xx_netpoll(struct net_device *netdev) |
1300 | { | |
1301 | struct mv643xx_private *mp = netdev_priv(netdev); | |
c2e5b352 DF |
1302 | int port_num = mp->port_num; |
1303 | ||
1304 | mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), INT_MASK_ALL); | |
1305 | /* wait for previous write to complete */ | |
1306 | mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num)); | |
63c9e549 | 1307 | |
63c9e549 | 1308 | mv643xx_eth_int_handler(netdev->irq, netdev, NULL); |
c2e5b352 DF |
1309 | |
1310 | mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), INT_UNMASK_ALL); | |
63c9e549 DF |
1311 | } |
1312 | #endif | |
1313 | ||
1da177e4 LT |
1314 | /*/ |
1315 | * mv643xx_eth_probe | |
1316 | * | |
1317 | * First function called after registering the network device. | |
1318 | * It's purpose is to initialize the device as an ethernet device, | |
1319 | * fill the ethernet device structure with pointers * to functions, | |
1320 | * and set the MAC address of the interface | |
1321 | * | |
1322 | * Input : struct device * | |
1323 | * Output : -ENOMEM if failed , 0 if success | |
1324 | */ | |
3ae5eaec | 1325 | static int mv643xx_eth_probe(struct platform_device *pdev) |
1da177e4 | 1326 | { |
1da177e4 LT |
1327 | struct mv643xx_eth_platform_data *pd; |
1328 | int port_num = pdev->id; | |
1329 | struct mv643xx_private *mp; | |
1330 | struct net_device *dev; | |
1331 | u8 *p; | |
1332 | struct resource *res; | |
1333 | int err; | |
1334 | ||
1335 | dev = alloc_etherdev(sizeof(struct mv643xx_private)); | |
1336 | if (!dev) | |
1337 | return -ENOMEM; | |
1338 | ||
3ae5eaec | 1339 | platform_set_drvdata(pdev, dev); |
1da177e4 LT |
1340 | |
1341 | mp = netdev_priv(dev); | |
1342 | ||
1343 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
1344 | BUG_ON(!res); | |
1345 | dev->irq = res->start; | |
1346 | ||
1347 | mp->port_num = port_num; | |
1348 | ||
1349 | dev->open = mv643xx_eth_open; | |
1350 | dev->stop = mv643xx_eth_stop; | |
1351 | dev->hard_start_xmit = mv643xx_eth_start_xmit; | |
1352 | dev->get_stats = mv643xx_eth_get_stats; | |
1353 | dev->set_mac_address = mv643xx_eth_set_mac_address; | |
1354 | dev->set_multicast_list = mv643xx_eth_set_rx_mode; | |
1355 | ||
1356 | /* No need to Tx Timeout */ | |
1357 | dev->tx_timeout = mv643xx_eth_tx_timeout; | |
1358 | #ifdef MV643XX_NAPI | |
1359 | dev->poll = mv643xx_poll; | |
1360 | dev->weight = 64; | |
1361 | #endif | |
1362 | ||
63c9e549 DF |
1363 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1364 | dev->poll_controller = mv643xx_netpoll; | |
1365 | #endif | |
1366 | ||
1da177e4 LT |
1367 | dev->watchdog_timeo = 2 * HZ; |
1368 | dev->tx_queue_len = mp->tx_ring_size; | |
1369 | dev->base_addr = 0; | |
1370 | dev->change_mtu = mv643xx_eth_change_mtu; | |
1371 | SET_ETHTOOL_OPS(dev, &mv643xx_ethtool_ops); | |
1372 | ||
1373 | #ifdef MV643XX_CHECKSUM_OFFLOAD_TX | |
1374 | #ifdef MAX_SKB_FRAGS | |
1375 | /* | |
1376 | * Zero copy can only work if we use Discovery II memory. Else, we will | |
1377 | * have to map the buffers to ISA memory which is only 16 MB | |
1378 | */ | |
63890576 | 1379 | dev->features = NETIF_F_SG | NETIF_F_IP_CSUM; |
1da177e4 LT |
1380 | #endif |
1381 | #endif | |
1382 | ||
1383 | /* Configure the timeout task */ | |
1384 | INIT_WORK(&mp->tx_timeout_task, | |
1385 | (void (*)(void *))mv643xx_eth_tx_timeout_task, dev); | |
1386 | ||
1387 | spin_lock_init(&mp->lock); | |
1388 | ||
1389 | /* set default config values */ | |
1390 | eth_port_uc_addr_get(dev, dev->dev_addr); | |
1391 | mp->port_config = MV643XX_ETH_PORT_CONFIG_DEFAULT_VALUE; | |
1392 | mp->port_config_extend = MV643XX_ETH_PORT_CONFIG_EXTEND_DEFAULT_VALUE; | |
1393 | mp->port_sdma_config = MV643XX_ETH_PORT_SDMA_CONFIG_DEFAULT_VALUE; | |
1394 | mp->port_serial_control = MV643XX_ETH_PORT_SERIAL_CONTROL_DEFAULT_VALUE; | |
1395 | mp->rx_ring_size = MV643XX_ETH_PORT_DEFAULT_RECEIVE_QUEUE_SIZE; | |
1396 | mp->tx_ring_size = MV643XX_ETH_PORT_DEFAULT_TRANSMIT_QUEUE_SIZE; | |
1397 | ||
1398 | pd = pdev->dev.platform_data; | |
1399 | if (pd) { | |
1400 | if (pd->mac_addr != NULL) | |
1401 | memcpy(dev->dev_addr, pd->mac_addr, 6); | |
1402 | ||
1403 | if (pd->phy_addr || pd->force_phy_addr) | |
1404 | ethernet_phy_set(port_num, pd->phy_addr); | |
1405 | ||
1406 | if (pd->port_config || pd->force_port_config) | |
1407 | mp->port_config = pd->port_config; | |
1408 | ||
1409 | if (pd->port_config_extend || pd->force_port_config_extend) | |
1410 | mp->port_config_extend = pd->port_config_extend; | |
1411 | ||
1412 | if (pd->port_sdma_config || pd->force_port_sdma_config) | |
1413 | mp->port_sdma_config = pd->port_sdma_config; | |
1414 | ||
1415 | if (pd->port_serial_control || pd->force_port_serial_control) | |
1416 | mp->port_serial_control = pd->port_serial_control; | |
1417 | ||
1418 | if (pd->rx_queue_size) | |
1419 | mp->rx_ring_size = pd->rx_queue_size; | |
1420 | ||
1421 | if (pd->tx_queue_size) | |
1422 | mp->tx_ring_size = pd->tx_queue_size; | |
1423 | ||
1424 | if (pd->tx_sram_size) { | |
1425 | mp->tx_sram_size = pd->tx_sram_size; | |
1426 | mp->tx_sram_addr = pd->tx_sram_addr; | |
1427 | } | |
1428 | ||
1429 | if (pd->rx_sram_size) { | |
1430 | mp->rx_sram_size = pd->rx_sram_size; | |
1431 | mp->rx_sram_addr = pd->rx_sram_addr; | |
1432 | } | |
1433 | } | |
1434 | ||
1435 | err = ethernet_phy_detect(port_num); | |
1436 | if (err) { | |
1437 | pr_debug("MV643xx ethernet port %d: " | |
1438 | "No PHY detected at addr %d\n", | |
1439 | port_num, ethernet_phy_get(port_num)); | |
1440 | return err; | |
1441 | } | |
1442 | ||
1443 | err = register_netdev(dev); | |
1444 | if (err) | |
1445 | goto out; | |
1446 | ||
1447 | p = dev->dev_addr; | |
1448 | printk(KERN_NOTICE | |
1449 | "%s: port %d with MAC address %02x:%02x:%02x:%02x:%02x:%02x\n", | |
1450 | dev->name, port_num, p[0], p[1], p[2], p[3], p[4], p[5]); | |
1451 | ||
1452 | if (dev->features & NETIF_F_SG) | |
1453 | printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name); | |
1454 | ||
1455 | if (dev->features & NETIF_F_IP_CSUM) | |
1456 | printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n", | |
1457 | dev->name); | |
1458 | ||
1459 | #ifdef MV643XX_CHECKSUM_OFFLOAD_TX | |
1460 | printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name); | |
1461 | #endif | |
1462 | ||
1463 | #ifdef MV643XX_COAL | |
1464 | printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n", | |
1465 | dev->name); | |
1466 | #endif | |
1467 | ||
1468 | #ifdef MV643XX_NAPI | |
1469 | printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name); | |
1470 | #endif | |
1471 | ||
b1529871 ND |
1472 | if (mp->tx_sram_size > 0) |
1473 | printk(KERN_NOTICE "%s: Using SRAM\n", dev->name); | |
1474 | ||
1da177e4 LT |
1475 | return 0; |
1476 | ||
1477 | out: | |
1478 | free_netdev(dev); | |
1479 | ||
1480 | return err; | |
1481 | } | |
1482 | ||
3ae5eaec | 1483 | static int mv643xx_eth_remove(struct platform_device *pdev) |
1da177e4 | 1484 | { |
3ae5eaec | 1485 | struct net_device *dev = platform_get_drvdata(pdev); |
1da177e4 LT |
1486 | |
1487 | unregister_netdev(dev); | |
1488 | flush_scheduled_work(); | |
1489 | ||
1490 | free_netdev(dev); | |
3ae5eaec | 1491 | platform_set_drvdata(pdev, NULL); |
1da177e4 LT |
1492 | return 0; |
1493 | } | |
1494 | ||
3ae5eaec | 1495 | static int mv643xx_eth_shared_probe(struct platform_device *pdev) |
1da177e4 | 1496 | { |
1da177e4 LT |
1497 | struct resource *res; |
1498 | ||
1499 | printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n"); | |
1500 | ||
1501 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1502 | if (res == NULL) | |
1503 | return -ENODEV; | |
1504 | ||
1505 | mv643xx_eth_shared_base = ioremap(res->start, | |
1506 | MV643XX_ETH_SHARED_REGS_SIZE); | |
1507 | if (mv643xx_eth_shared_base == NULL) | |
1508 | return -ENOMEM; | |
1509 | ||
1510 | return 0; | |
1511 | ||
1512 | } | |
1513 | ||
3ae5eaec | 1514 | static int mv643xx_eth_shared_remove(struct platform_device *pdev) |
1da177e4 LT |
1515 | { |
1516 | iounmap(mv643xx_eth_shared_base); | |
1517 | mv643xx_eth_shared_base = NULL; | |
1518 | ||
1519 | return 0; | |
1520 | } | |
1521 | ||
3ae5eaec | 1522 | static struct platform_driver mv643xx_eth_driver = { |
1da177e4 LT |
1523 | .probe = mv643xx_eth_probe, |
1524 | .remove = mv643xx_eth_remove, | |
3ae5eaec RK |
1525 | .driver = { |
1526 | .name = MV643XX_ETH_NAME, | |
1527 | }, | |
1da177e4 LT |
1528 | }; |
1529 | ||
3ae5eaec | 1530 | static struct platform_driver mv643xx_eth_shared_driver = { |
1da177e4 LT |
1531 | .probe = mv643xx_eth_shared_probe, |
1532 | .remove = mv643xx_eth_shared_remove, | |
3ae5eaec RK |
1533 | .driver = { |
1534 | .name = MV643XX_ETH_SHARED_NAME, | |
1535 | }, | |
1da177e4 LT |
1536 | }; |
1537 | ||
1538 | /* | |
1539 | * mv643xx_init_module | |
1540 | * | |
1541 | * Registers the network drivers into the Linux kernel | |
1542 | * | |
1543 | * Input : N/A | |
1544 | * | |
1545 | * Output : N/A | |
1546 | */ | |
1547 | static int __init mv643xx_init_module(void) | |
1548 | { | |
1549 | int rc; | |
1550 | ||
3ae5eaec | 1551 | rc = platform_driver_register(&mv643xx_eth_shared_driver); |
1da177e4 | 1552 | if (!rc) { |
3ae5eaec | 1553 | rc = platform_driver_register(&mv643xx_eth_driver); |
1da177e4 | 1554 | if (rc) |
3ae5eaec | 1555 | platform_driver_unregister(&mv643xx_eth_shared_driver); |
1da177e4 LT |
1556 | } |
1557 | return rc; | |
1558 | } | |
1559 | ||
1560 | /* | |
1561 | * mv643xx_cleanup_module | |
1562 | * | |
1563 | * Registers the network drivers into the Linux kernel | |
1564 | * | |
1565 | * Input : N/A | |
1566 | * | |
1567 | * Output : N/A | |
1568 | */ | |
1569 | static void __exit mv643xx_cleanup_module(void) | |
1570 | { | |
3ae5eaec RK |
1571 | platform_driver_unregister(&mv643xx_eth_driver); |
1572 | platform_driver_unregister(&mv643xx_eth_shared_driver); | |
1da177e4 LT |
1573 | } |
1574 | ||
1575 | module_init(mv643xx_init_module); | |
1576 | module_exit(mv643xx_cleanup_module); | |
1577 | ||
1578 | MODULE_LICENSE("GPL"); | |
1579 | MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani" | |
1580 | " and Dale Farnsworth"); | |
1581 | MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX"); | |
1582 | ||
1583 | /* | |
1584 | * The second part is the low level driver of the gigE ethernet ports. | |
1585 | */ | |
1586 | ||
1587 | /* | |
1588 | * Marvell's Gigabit Ethernet controller low level driver | |
1589 | * | |
1590 | * DESCRIPTION: | |
1591 | * This file introduce low level API to Marvell's Gigabit Ethernet | |
1592 | * controller. This Gigabit Ethernet Controller driver API controls | |
1593 | * 1) Operations (i.e. port init, start, reset etc'). | |
1594 | * 2) Data flow (i.e. port send, receive etc'). | |
1595 | * Each Gigabit Ethernet port is controlled via | |
1596 | * struct mv643xx_private. | |
1597 | * This struct includes user configuration information as well as | |
1598 | * driver internal data needed for its operations. | |
1599 | * | |
1600 | * Supported Features: | |
1601 | * - This low level driver is OS independent. Allocating memory for | |
1602 | * the descriptor rings and buffers are not within the scope of | |
1603 | * this driver. | |
1604 | * - The user is free from Rx/Tx queue managing. | |
1605 | * - This low level driver introduce functionality API that enable | |
1606 | * the to operate Marvell's Gigabit Ethernet Controller in a | |
1607 | * convenient way. | |
1608 | * - Simple Gigabit Ethernet port operation API. | |
1609 | * - Simple Gigabit Ethernet port data flow API. | |
1610 | * - Data flow and operation API support per queue functionality. | |
1611 | * - Support cached descriptors for better performance. | |
1612 | * - Enable access to all four DRAM banks and internal SRAM memory | |
1613 | * spaces. | |
1614 | * - PHY access and control API. | |
1615 | * - Port control register configuration API. | |
1616 | * - Full control over Unicast and Multicast MAC configurations. | |
1617 | * | |
1618 | * Operation flow: | |
1619 | * | |
1620 | * Initialization phase | |
1621 | * This phase complete the initialization of the the | |
1622 | * mv643xx_private struct. | |
1623 | * User information regarding port configuration has to be set | |
1624 | * prior to calling the port initialization routine. | |
1625 | * | |
1626 | * In this phase any port Tx/Rx activity is halted, MIB counters | |
1627 | * are cleared, PHY address is set according to user parameter and | |
1628 | * access to DRAM and internal SRAM memory spaces. | |
1629 | * | |
1630 | * Driver ring initialization | |
1631 | * Allocating memory for the descriptor rings and buffers is not | |
1632 | * within the scope of this driver. Thus, the user is required to | |
1633 | * allocate memory for the descriptors ring and buffers. Those | |
1634 | * memory parameters are used by the Rx and Tx ring initialization | |
1635 | * routines in order to curve the descriptor linked list in a form | |
1636 | * of a ring. | |
1637 | * Note: Pay special attention to alignment issues when using | |
1638 | * cached descriptors/buffers. In this phase the driver store | |
1639 | * information in the mv643xx_private struct regarding each queue | |
1640 | * ring. | |
1641 | * | |
1642 | * Driver start | |
1643 | * This phase prepares the Ethernet port for Rx and Tx activity. | |
1644 | * It uses the information stored in the mv643xx_private struct to | |
1645 | * initialize the various port registers. | |
1646 | * | |
1647 | * Data flow: | |
1648 | * All packet references to/from the driver are done using | |
1649 | * struct pkt_info. | |
1650 | * This struct is a unified struct used with Rx and Tx operations. | |
1651 | * This way the user is not required to be familiar with neither | |
1652 | * Tx nor Rx descriptors structures. | |
1653 | * The driver's descriptors rings are management by indexes. | |
1654 | * Those indexes controls the ring resources and used to indicate | |
1655 | * a SW resource error: | |
1656 | * 'current' | |
1657 | * This index points to the current available resource for use. For | |
1658 | * example in Rx process this index will point to the descriptor | |
1659 | * that will be passed to the user upon calling the receive | |
1660 | * routine. In Tx process, this index will point to the descriptor | |
1661 | * that will be assigned with the user packet info and transmitted. | |
1662 | * 'used' | |
1663 | * This index points to the descriptor that need to restore its | |
1664 | * resources. For example in Rx process, using the Rx buffer return | |
1665 | * API will attach the buffer returned in packet info to the | |
1666 | * descriptor pointed by 'used'. In Tx process, using the Tx | |
1667 | * descriptor return will merely return the user packet info with | |
1668 | * the command status of the transmitted buffer pointed by the | |
1669 | * 'used' index. Nevertheless, it is essential to use this routine | |
1670 | * to update the 'used' index. | |
1671 | * 'first' | |
1672 | * This index supports Tx Scatter-Gather. It points to the first | |
1673 | * descriptor of a packet assembled of multiple buffers. For | |
1674 | * example when in middle of Such packet we have a Tx resource | |
1675 | * error the 'curr' index get the value of 'first' to indicate | |
1676 | * that the ring returned to its state before trying to transmit | |
1677 | * this packet. | |
1678 | * | |
1679 | * Receive operation: | |
1680 | * The eth_port_receive API set the packet information struct, | |
1681 | * passed by the caller, with received information from the | |
1682 | * 'current' SDMA descriptor. | |
1683 | * It is the user responsibility to return this resource back | |
1684 | * to the Rx descriptor ring to enable the reuse of this source. | |
1685 | * Return Rx resource is done using the eth_rx_return_buff API. | |
1686 | * | |
1687 | * Transmit operation: | |
1688 | * The eth_port_send API supports Scatter-Gather which enables to | |
1689 | * send a packet spanned over multiple buffers. This means that | |
1690 | * for each packet info structure given by the user and put into | |
1691 | * the Tx descriptors ring, will be transmitted only if the 'LAST' | |
1692 | * bit will be set in the packet info command status field. This | |
1693 | * API also consider restriction regarding buffer alignments and | |
1694 | * sizes. | |
1695 | * The user must return a Tx resource after ensuring the buffer | |
1696 | * has been transmitted to enable the Tx ring indexes to update. | |
1697 | * | |
1698 | * BOARD LAYOUT | |
1699 | * This device is on-board. No jumper diagram is necessary. | |
1700 | * | |
1701 | * EXTERNAL INTERFACE | |
1702 | * | |
1703 | * Prior to calling the initialization routine eth_port_init() the user | |
1704 | * must set the following fields under mv643xx_private struct: | |
1705 | * port_num User Ethernet port number. | |
1da177e4 LT |
1706 | * port_config User port configuration value. |
1707 | * port_config_extend User port config extend value. | |
1708 | * port_sdma_config User port SDMA config value. | |
1709 | * port_serial_control User port serial control value. | |
1710 | * | |
1711 | * This driver data flow is done using the struct pkt_info which | |
1712 | * is a unified struct for Rx and Tx operations: | |
1713 | * | |
1714 | * byte_cnt Tx/Rx descriptor buffer byte count. | |
1715 | * l4i_chk CPU provided TCP Checksum. For Tx operation | |
1716 | * only. | |
1717 | * cmd_sts Tx/Rx descriptor command status. | |
1718 | * buf_ptr Tx/Rx descriptor buffer pointer. | |
1719 | * return_info Tx/Rx user resource return information. | |
1720 | */ | |
1721 | ||
1722 | /* defines */ | |
1723 | /* SDMA command macros */ | |
1724 | #define ETH_ENABLE_TX_QUEUE(eth_port) \ | |
1725 | mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), 1) | |
1726 | ||
1727 | /* locals */ | |
1728 | ||
1729 | /* PHY routines */ | |
1730 | static int ethernet_phy_get(unsigned int eth_port_num); | |
1731 | static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr); | |
1732 | ||
1733 | /* Ethernet Port routines */ | |
cf4086c7 | 1734 | static void eth_port_set_filter_table_entry(int table, unsigned char entry); |
1da177e4 LT |
1735 | |
1736 | /* | |
1737 | * eth_port_init - Initialize the Ethernet port driver | |
1738 | * | |
1739 | * DESCRIPTION: | |
1740 | * This function prepares the ethernet port to start its activity: | |
1741 | * 1) Completes the ethernet port driver struct initialization toward port | |
1742 | * start routine. | |
1743 | * 2) Resets the device to a quiescent state in case of warm reboot. | |
1744 | * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM. | |
1745 | * 4) Clean MAC tables. The reset status of those tables is unknown. | |
1746 | * 5) Set PHY address. | |
1747 | * Note: Call this routine prior to eth_port_start routine and after | |
1748 | * setting user values in the user fields of Ethernet port control | |
1749 | * struct. | |
1750 | * | |
1751 | * INPUT: | |
1752 | * struct mv643xx_private *mp Ethernet port control struct | |
1753 | * | |
1754 | * OUTPUT: | |
1755 | * See description. | |
1756 | * | |
1757 | * RETURN: | |
1758 | * None. | |
1759 | */ | |
1760 | static void eth_port_init(struct mv643xx_private *mp) | |
1761 | { | |
1762 | mp->port_rx_queue_command = 0; | |
1763 | mp->port_tx_queue_command = 0; | |
1764 | ||
1765 | mp->rx_resource_err = 0; | |
1766 | mp->tx_resource_err = 0; | |
1767 | ||
1768 | eth_port_reset(mp->port_num); | |
1769 | ||
1770 | eth_port_init_mac_tables(mp->port_num); | |
1771 | ||
1772 | ethernet_phy_reset(mp->port_num); | |
1773 | } | |
1774 | ||
1775 | /* | |
1776 | * eth_port_start - Start the Ethernet port activity. | |
1777 | * | |
1778 | * DESCRIPTION: | |
1779 | * This routine prepares the Ethernet port for Rx and Tx activity: | |
1780 | * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that | |
1781 | * has been initialized a descriptor's ring (using | |
1782 | * ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx) | |
1783 | * 2. Initialize and enable the Ethernet configuration port by writing to | |
1784 | * the port's configuration and command registers. | |
1785 | * 3. Initialize and enable the SDMA by writing to the SDMA's | |
1786 | * configuration and command registers. After completing these steps, | |
1787 | * the ethernet port SDMA can starts to perform Rx and Tx activities. | |
1788 | * | |
1789 | * Note: Each Rx and Tx queue descriptor's list must be initialized prior | |
1790 | * to calling this function (use ether_init_tx_desc_ring for Tx queues | |
1791 | * and ether_init_rx_desc_ring for Rx queues). | |
1792 | * | |
1793 | * INPUT: | |
ed9b5d45 | 1794 | * dev - a pointer to the required interface |
1da177e4 LT |
1795 | * |
1796 | * OUTPUT: | |
1797 | * Ethernet port is ready to receive and transmit. | |
1798 | * | |
1799 | * RETURN: | |
1800 | * None. | |
1801 | */ | |
ed9b5d45 | 1802 | static void eth_port_start(struct net_device *dev) |
1da177e4 | 1803 | { |
ed9b5d45 | 1804 | struct mv643xx_private *mp = netdev_priv(dev); |
1da177e4 LT |
1805 | unsigned int port_num = mp->port_num; |
1806 | int tx_curr_desc, rx_curr_desc; | |
1807 | ||
1808 | /* Assignment of Tx CTRP of given queue */ | |
1809 | tx_curr_desc = mp->tx_curr_desc_q; | |
1810 | mv_write(MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port_num), | |
1811 | (u32)((struct eth_tx_desc *)mp->tx_desc_dma + tx_curr_desc)); | |
1812 | ||
1813 | /* Assignment of Rx CRDP of given queue */ | |
1814 | rx_curr_desc = mp->rx_curr_desc_q; | |
1815 | mv_write(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num), | |
1816 | (u32)((struct eth_rx_desc *)mp->rx_desc_dma + rx_curr_desc)); | |
1817 | ||
1818 | /* Add the assigned Ethernet address to the port's address table */ | |
ed9b5d45 | 1819 | eth_port_uc_addr_set(port_num, dev->dev_addr); |
1da177e4 LT |
1820 | |
1821 | /* Assign port configuration and command. */ | |
1822 | mv_write(MV643XX_ETH_PORT_CONFIG_REG(port_num), mp->port_config); | |
1823 | ||
1824 | mv_write(MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port_num), | |
1825 | mp->port_config_extend); | |
1826 | ||
1827 | ||
1828 | /* Increase the Rx side buffer size if supporting GigE */ | |
1829 | if (mp->port_serial_control & MV643XX_ETH_SET_GMII_SPEED_TO_1000) | |
1830 | mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), | |
1831 | (mp->port_serial_control & 0xfff1ffff) | (0x5 << 17)); | |
1832 | else | |
1833 | mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), | |
1834 | mp->port_serial_control); | |
1835 | ||
1836 | mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), | |
1837 | mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num)) | | |
1838 | MV643XX_ETH_SERIAL_PORT_ENABLE); | |
1839 | ||
1840 | /* Assign port SDMA configuration */ | |
1841 | mv_write(MV643XX_ETH_SDMA_CONFIG_REG(port_num), | |
1842 | mp->port_sdma_config); | |
1843 | ||
1844 | /* Enable port Rx. */ | |
1845 | mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), | |
1846 | mp->port_rx_queue_command); | |
8f543718 DF |
1847 | |
1848 | /* Disable port bandwidth limits by clearing MTU register */ | |
1849 | mv_write(MV643XX_ETH_MAXIMUM_TRANSMIT_UNIT(port_num), 0); | |
1da177e4 LT |
1850 | } |
1851 | ||
1852 | /* | |
1853 | * eth_port_uc_addr_set - This function Set the port Unicast address. | |
1854 | * | |
1855 | * DESCRIPTION: | |
1856 | * This function Set the port Ethernet MAC address. | |
1857 | * | |
1858 | * INPUT: | |
1859 | * unsigned int eth_port_num Port number. | |
1860 | * char * p_addr Address to be set | |
1861 | * | |
1862 | * OUTPUT: | |
cf4086c7 DF |
1863 | * Set MAC address low and high registers. also calls |
1864 | * eth_port_set_filter_table_entry() to set the unicast | |
1865 | * table with the proper information. | |
1da177e4 LT |
1866 | * |
1867 | * RETURN: | |
1868 | * N/A. | |
1869 | * | |
1870 | */ | |
1871 | static void eth_port_uc_addr_set(unsigned int eth_port_num, | |
1872 | unsigned char *p_addr) | |
1873 | { | |
1874 | unsigned int mac_h; | |
1875 | unsigned int mac_l; | |
cf4086c7 | 1876 | int table; |
1da177e4 LT |
1877 | |
1878 | mac_l = (p_addr[4] << 8) | (p_addr[5]); | |
1879 | mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) | | |
1880 | (p_addr[3] << 0); | |
1881 | ||
1882 | mv_write(MV643XX_ETH_MAC_ADDR_LOW(eth_port_num), mac_l); | |
1883 | mv_write(MV643XX_ETH_MAC_ADDR_HIGH(eth_port_num), mac_h); | |
1884 | ||
1885 | /* Accept frames of this address */ | |
cf4086c7 DF |
1886 | table = MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE(eth_port_num); |
1887 | eth_port_set_filter_table_entry(table, p_addr[5] & 0x0f); | |
1da177e4 LT |
1888 | } |
1889 | ||
1890 | /* | |
1891 | * eth_port_uc_addr_get - This function retrieves the port Unicast address | |
1892 | * (MAC address) from the ethernet hw registers. | |
1893 | * | |
1894 | * DESCRIPTION: | |
1895 | * This function retrieves the port Ethernet MAC address. | |
1896 | * | |
1897 | * INPUT: | |
1898 | * unsigned int eth_port_num Port number. | |
1899 | * char *MacAddr pointer where the MAC address is stored | |
1900 | * | |
1901 | * OUTPUT: | |
1902 | * Copy the MAC address to the location pointed to by MacAddr | |
1903 | * | |
1904 | * RETURN: | |
1905 | * N/A. | |
1906 | * | |
1907 | */ | |
1908 | static void eth_port_uc_addr_get(struct net_device *dev, unsigned char *p_addr) | |
1909 | { | |
1910 | struct mv643xx_private *mp = netdev_priv(dev); | |
1911 | unsigned int mac_h; | |
1912 | unsigned int mac_l; | |
1913 | ||
1914 | mac_h = mv_read(MV643XX_ETH_MAC_ADDR_HIGH(mp->port_num)); | |
1915 | mac_l = mv_read(MV643XX_ETH_MAC_ADDR_LOW(mp->port_num)); | |
1916 | ||
1917 | p_addr[0] = (mac_h >> 24) & 0xff; | |
1918 | p_addr[1] = (mac_h >> 16) & 0xff; | |
1919 | p_addr[2] = (mac_h >> 8) & 0xff; | |
1920 | p_addr[3] = mac_h & 0xff; | |
1921 | p_addr[4] = (mac_l >> 8) & 0xff; | |
1922 | p_addr[5] = mac_l & 0xff; | |
1923 | } | |
1924 | ||
16e03018 DF |
1925 | /* |
1926 | * The entries in each table are indexed by a hash of a packet's MAC | |
1927 | * address. One bit in each entry determines whether the packet is | |
1928 | * accepted. There are 4 entries (each 8 bits wide) in each register | |
1929 | * of the table. The bits in each entry are defined as follows: | |
1930 | * 0 Accept=1, Drop=0 | |
1931 | * 3-1 Queue (ETH_Q0=0) | |
1932 | * 7-4 Reserved = 0; | |
1933 | */ | |
1934 | static void eth_port_set_filter_table_entry(int table, unsigned char entry) | |
1935 | { | |
1936 | unsigned int table_reg; | |
1937 | unsigned int tbl_offset; | |
1938 | unsigned int reg_offset; | |
1939 | ||
1940 | tbl_offset = (entry / 4) * 4; /* Register offset of DA table entry */ | |
1941 | reg_offset = entry % 4; /* Entry offset within the register */ | |
1942 | ||
1943 | /* Set "accepts frame bit" at specified table entry */ | |
1944 | table_reg = mv_read(table + tbl_offset); | |
1945 | table_reg |= 0x01 << (8 * reg_offset); | |
1946 | mv_write(table + tbl_offset, table_reg); | |
1947 | } | |
1948 | ||
1949 | /* | |
1950 | * eth_port_mc_addr - Multicast address settings. | |
1951 | * | |
1952 | * The MV device supports multicast using two tables: | |
1953 | * 1) Special Multicast Table for MAC addresses of the form | |
1954 | * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_FF). | |
1955 | * The MAC DA[7:0] bits are used as a pointer to the Special Multicast | |
1956 | * Table entries in the DA-Filter table. | |
1957 | * 2) Other Multicast Table for multicast of another type. A CRC-8bit | |
1958 | * is used as an index to the Other Multicast Table entries in the | |
1959 | * DA-Filter table. This function calculates the CRC-8bit value. | |
1960 | * In either case, eth_port_set_filter_table_entry() is then called | |
1961 | * to set to set the actual table entry. | |
1962 | */ | |
1963 | static void eth_port_mc_addr(unsigned int eth_port_num, unsigned char *p_addr) | |
1964 | { | |
1965 | unsigned int mac_h; | |
1966 | unsigned int mac_l; | |
1967 | unsigned char crc_result = 0; | |
1968 | int table; | |
1969 | int mac_array[48]; | |
1970 | int crc[8]; | |
1971 | int i; | |
1972 | ||
1973 | if ((p_addr[0] == 0x01) && (p_addr[1] == 0x00) && | |
1974 | (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) { | |
1975 | table = MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE | |
1976 | (eth_port_num); | |
1977 | eth_port_set_filter_table_entry(table, p_addr[5]); | |
1978 | return; | |
1979 | } | |
1980 | ||
1981 | /* Calculate CRC-8 out of the given address */ | |
1982 | mac_h = (p_addr[0] << 8) | (p_addr[1]); | |
1983 | mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) | | |
1984 | (p_addr[4] << 8) | (p_addr[5] << 0); | |
1985 | ||
1986 | for (i = 0; i < 32; i++) | |
1987 | mac_array[i] = (mac_l >> i) & 0x1; | |
1988 | for (i = 32; i < 48; i++) | |
1989 | mac_array[i] = (mac_h >> (i - 32)) & 0x1; | |
1990 | ||
1991 | crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ mac_array[39] ^ | |
1992 | mac_array[35] ^ mac_array[34] ^ mac_array[31] ^ mac_array[30] ^ | |
1993 | mac_array[28] ^ mac_array[23] ^ mac_array[21] ^ mac_array[19] ^ | |
1994 | mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ mac_array[12] ^ | |
1995 | mac_array[8] ^ mac_array[7] ^ mac_array[6] ^ mac_array[0]; | |
1996 | ||
1997 | crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^ | |
1998 | mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ mac_array[34] ^ | |
1999 | mac_array[32] ^ mac_array[30] ^ mac_array[29] ^ mac_array[28] ^ | |
2000 | mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ mac_array[21] ^ | |
2001 | mac_array[20] ^ mac_array[18] ^ mac_array[17] ^ mac_array[16] ^ | |
2002 | mac_array[15] ^ mac_array[14] ^ mac_array[13] ^ mac_array[12] ^ | |
2003 | mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ mac_array[0]; | |
2004 | ||
2005 | crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ mac_array[43] ^ | |
2006 | mac_array[42] ^ mac_array[39] ^ mac_array[37] ^ mac_array[34] ^ | |
2007 | mac_array[33] ^ mac_array[29] ^ mac_array[28] ^ mac_array[25] ^ | |
2008 | mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ mac_array[15] ^ | |
2009 | mac_array[13] ^ mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ | |
2010 | mac_array[6] ^ mac_array[2] ^ mac_array[1] ^ mac_array[0]; | |
2011 | ||
2012 | crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^ | |
2013 | mac_array[40] ^ mac_array[38] ^ mac_array[35] ^ mac_array[34] ^ | |
2014 | mac_array[30] ^ mac_array[29] ^ mac_array[26] ^ mac_array[25] ^ | |
2015 | mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ | |
2016 | mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[7] ^ | |
2017 | mac_array[3] ^ mac_array[2] ^ mac_array[1]; | |
2018 | ||
2019 | crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[41] ^ | |
2020 | mac_array[39] ^ mac_array[36] ^ mac_array[35] ^ mac_array[31] ^ | |
2021 | mac_array[30] ^ mac_array[27] ^ mac_array[26] ^ mac_array[24] ^ | |
2022 | mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ mac_array[14] ^ | |
2023 | mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ mac_array[4] ^ | |
2024 | mac_array[3] ^ mac_array[2]; | |
2025 | ||
2026 | crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ mac_array[42] ^ | |
2027 | mac_array[40] ^ mac_array[37] ^ mac_array[36] ^ mac_array[32] ^ | |
2028 | mac_array[31] ^ mac_array[28] ^ mac_array[27] ^ mac_array[25] ^ | |
2029 | mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ mac_array[15] ^ | |
2030 | mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[5] ^ | |
2031 | mac_array[4] ^ mac_array[3]; | |
2032 | ||
2033 | crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ mac_array[41] ^ | |
2034 | mac_array[38] ^ mac_array[37] ^ mac_array[33] ^ mac_array[32] ^ | |
2035 | mac_array[29] ^ mac_array[28] ^ mac_array[26] ^ mac_array[21] ^ | |
2036 | mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ mac_array[14] ^ | |
2037 | mac_array[12] ^ mac_array[10] ^ mac_array[6] ^ mac_array[5] ^ | |
2038 | mac_array[4]; | |
2039 | ||
2040 | crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ mac_array[39] ^ | |
2041 | mac_array[38] ^ mac_array[34] ^ mac_array[33] ^ mac_array[30] ^ | |
2042 | mac_array[29] ^ mac_array[27] ^ mac_array[22] ^ mac_array[20] ^ | |
2043 | mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ mac_array[13] ^ | |
2044 | mac_array[11] ^ mac_array[7] ^ mac_array[6] ^ mac_array[5]; | |
2045 | ||
2046 | for (i = 0; i < 8; i++) | |
2047 | crc_result = crc_result | (crc[i] << i); | |
2048 | ||
2049 | table = MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num); | |
2050 | eth_port_set_filter_table_entry(table, crc_result); | |
2051 | } | |
2052 | ||
2053 | /* | |
2054 | * Set the entire multicast list based on dev->mc_list. | |
2055 | */ | |
2056 | static void eth_port_set_multicast_list(struct net_device *dev) | |
2057 | { | |
2058 | ||
2059 | struct dev_mc_list *mc_list; | |
2060 | int i; | |
2061 | int table_index; | |
2062 | struct mv643xx_private *mp = netdev_priv(dev); | |
2063 | unsigned int eth_port_num = mp->port_num; | |
2064 | ||
2065 | /* If the device is in promiscuous mode or in all multicast mode, | |
2066 | * we will fully populate both multicast tables with accept. | |
2067 | * This is guaranteed to yield a match on all multicast addresses... | |
2068 | */ | |
2069 | if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) { | |
2070 | for (table_index = 0; table_index <= 0xFC; table_index += 4) { | |
b4de9051 DF |
2071 | /* Set all entries in DA filter special multicast |
2072 | * table (Ex_dFSMT) | |
2073 | * Set for ETH_Q0 for now | |
2074 | * Bits | |
2075 | * 0 Accept=1, Drop=0 | |
2076 | * 3-1 Queue ETH_Q0=0 | |
2077 | * 7-4 Reserved = 0; | |
2078 | */ | |
2079 | mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101); | |
2080 | ||
2081 | /* Set all entries in DA filter other multicast | |
2082 | * table (Ex_dFOMT) | |
2083 | * Set for ETH_Q0 for now | |
2084 | * Bits | |
2085 | * 0 Accept=1, Drop=0 | |
2086 | * 3-1 Queue ETH_Q0=0 | |
2087 | * 7-4 Reserved = 0; | |
2088 | */ | |
2089 | mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101); | |
2090 | } | |
16e03018 DF |
2091 | return; |
2092 | } | |
2093 | ||
2094 | /* We will clear out multicast tables every time we get the list. | |
2095 | * Then add the entire new list... | |
2096 | */ | |
2097 | for (table_index = 0; table_index <= 0xFC; table_index += 4) { | |
2098 | /* Clear DA filter special multicast table (Ex_dFSMT) */ | |
2099 | mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE | |
2100 | (eth_port_num) + table_index, 0); | |
2101 | ||
2102 | /* Clear DA filter other multicast table (Ex_dFOMT) */ | |
2103 | mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE | |
2104 | (eth_port_num) + table_index, 0); | |
2105 | } | |
2106 | ||
2107 | /* Get pointer to net_device multicast list and add each one... */ | |
2108 | for (i = 0, mc_list = dev->mc_list; | |
2109 | (i < 256) && (mc_list != NULL) && (i < dev->mc_count); | |
2110 | i++, mc_list = mc_list->next) | |
2111 | if (mc_list->dmi_addrlen == 6) | |
2112 | eth_port_mc_addr(eth_port_num, mc_list->dmi_addr); | |
2113 | } | |
2114 | ||
1da177e4 LT |
2115 | /* |
2116 | * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables | |
2117 | * | |
2118 | * DESCRIPTION: | |
2119 | * Go through all the DA filter tables (Unicast, Special Multicast & | |
2120 | * Other Multicast) and set each entry to 0. | |
2121 | * | |
2122 | * INPUT: | |
2123 | * unsigned int eth_port_num Ethernet Port number. | |
2124 | * | |
2125 | * OUTPUT: | |
2126 | * Multicast and Unicast packets are rejected. | |
2127 | * | |
2128 | * RETURN: | |
2129 | * None. | |
2130 | */ | |
2131 | static void eth_port_init_mac_tables(unsigned int eth_port_num) | |
2132 | { | |
2133 | int table_index; | |
2134 | ||
2135 | /* Clear DA filter unicast table (Ex_dFUT) */ | |
2136 | for (table_index = 0; table_index <= 0xC; table_index += 4) | |
cf4086c7 DF |
2137 | mv_write(MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE |
2138 | (eth_port_num) + table_index, 0); | |
1da177e4 LT |
2139 | |
2140 | for (table_index = 0; table_index <= 0xFC; table_index += 4) { | |
2141 | /* Clear DA filter special multicast table (Ex_dFSMT) */ | |
16e03018 DF |
2142 | mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE |
2143 | (eth_port_num) + table_index, 0); | |
1da177e4 | 2144 | /* Clear DA filter other multicast table (Ex_dFOMT) */ |
16e03018 DF |
2145 | mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE |
2146 | (eth_port_num) + table_index, 0); | |
1da177e4 LT |
2147 | } |
2148 | } | |
2149 | ||
2150 | /* | |
2151 | * eth_clear_mib_counters - Clear all MIB counters | |
2152 | * | |
2153 | * DESCRIPTION: | |
2154 | * This function clears all MIB counters of a specific ethernet port. | |
2155 | * A read from the MIB counter will reset the counter. | |
2156 | * | |
2157 | * INPUT: | |
2158 | * unsigned int eth_port_num Ethernet Port number. | |
2159 | * | |
2160 | * OUTPUT: | |
2161 | * After reading all MIB counters, the counters resets. | |
2162 | * | |
2163 | * RETURN: | |
2164 | * MIB counter value. | |
2165 | * | |
2166 | */ | |
2167 | static void eth_clear_mib_counters(unsigned int eth_port_num) | |
2168 | { | |
2169 | int i; | |
2170 | ||
2171 | /* Perform dummy reads from MIB counters */ | |
2172 | for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION; | |
2173 | i += 4) | |
2174 | mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(eth_port_num) + i); | |
2175 | } | |
2176 | ||
2177 | static inline u32 read_mib(struct mv643xx_private *mp, int offset) | |
2178 | { | |
2179 | return mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(mp->port_num) + offset); | |
2180 | } | |
2181 | ||
2182 | static void eth_update_mib_counters(struct mv643xx_private *mp) | |
2183 | { | |
2184 | struct mv643xx_mib_counters *p = &mp->mib_counters; | |
2185 | int offset; | |
2186 | ||
2187 | p->good_octets_received += | |
2188 | read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW); | |
2189 | p->good_octets_received += | |
2190 | (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32; | |
2191 | ||
2192 | for (offset = ETH_MIB_BAD_OCTETS_RECEIVED; | |
2193 | offset <= ETH_MIB_FRAMES_1024_TO_MAX_OCTETS; | |
2194 | offset += 4) | |
2195 | *(u32 *)((char *)p + offset) = read_mib(mp, offset); | |
2196 | ||
2197 | p->good_octets_sent += read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_LOW); | |
2198 | p->good_octets_sent += | |
2199 | (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_HIGH) << 32; | |
2200 | ||
2201 | for (offset = ETH_MIB_GOOD_FRAMES_SENT; | |
2202 | offset <= ETH_MIB_LATE_COLLISION; | |
2203 | offset += 4) | |
2204 | *(u32 *)((char *)p + offset) = read_mib(mp, offset); | |
2205 | } | |
2206 | ||
2207 | /* | |
2208 | * ethernet_phy_detect - Detect whether a phy is present | |
2209 | * | |
2210 | * DESCRIPTION: | |
2211 | * This function tests whether there is a PHY present on | |
2212 | * the specified port. | |
2213 | * | |
2214 | * INPUT: | |
2215 | * unsigned int eth_port_num Ethernet Port number. | |
2216 | * | |
2217 | * OUTPUT: | |
2218 | * None | |
2219 | * | |
2220 | * RETURN: | |
2221 | * 0 on success | |
2222 | * -ENODEV on failure | |
2223 | * | |
2224 | */ | |
2225 | static int ethernet_phy_detect(unsigned int port_num) | |
2226 | { | |
2227 | unsigned int phy_reg_data0; | |
2228 | int auto_neg; | |
2229 | ||
2230 | eth_port_read_smi_reg(port_num, 0, &phy_reg_data0); | |
2231 | auto_neg = phy_reg_data0 & 0x1000; | |
2232 | phy_reg_data0 ^= 0x1000; /* invert auto_neg */ | |
2233 | eth_port_write_smi_reg(port_num, 0, phy_reg_data0); | |
2234 | ||
2235 | eth_port_read_smi_reg(port_num, 0, &phy_reg_data0); | |
2236 | if ((phy_reg_data0 & 0x1000) == auto_neg) | |
2237 | return -ENODEV; /* change didn't take */ | |
2238 | ||
2239 | phy_reg_data0 ^= 0x1000; | |
2240 | eth_port_write_smi_reg(port_num, 0, phy_reg_data0); | |
2241 | return 0; | |
2242 | } | |
2243 | ||
2244 | /* | |
2245 | * ethernet_phy_get - Get the ethernet port PHY address. | |
2246 | * | |
2247 | * DESCRIPTION: | |
2248 | * This routine returns the given ethernet port PHY address. | |
2249 | * | |
2250 | * INPUT: | |
2251 | * unsigned int eth_port_num Ethernet Port number. | |
2252 | * | |
2253 | * OUTPUT: | |
2254 | * None. | |
2255 | * | |
2256 | * RETURN: | |
2257 | * PHY address. | |
2258 | * | |
2259 | */ | |
2260 | static int ethernet_phy_get(unsigned int eth_port_num) | |
2261 | { | |
2262 | unsigned int reg_data; | |
2263 | ||
2264 | reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG); | |
2265 | ||
2266 | return ((reg_data >> (5 * eth_port_num)) & 0x1f); | |
2267 | } | |
2268 | ||
2269 | /* | |
2270 | * ethernet_phy_set - Set the ethernet port PHY address. | |
2271 | * | |
2272 | * DESCRIPTION: | |
2273 | * This routine sets the given ethernet port PHY address. | |
2274 | * | |
2275 | * INPUT: | |
2276 | * unsigned int eth_port_num Ethernet Port number. | |
2277 | * int phy_addr PHY address. | |
2278 | * | |
2279 | * OUTPUT: | |
2280 | * None. | |
2281 | * | |
2282 | * RETURN: | |
2283 | * None. | |
2284 | * | |
2285 | */ | |
2286 | static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr) | |
2287 | { | |
2288 | u32 reg_data; | |
2289 | int addr_shift = 5 * eth_port_num; | |
2290 | ||
2291 | reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG); | |
2292 | reg_data &= ~(0x1f << addr_shift); | |
2293 | reg_data |= (phy_addr & 0x1f) << addr_shift; | |
2294 | mv_write(MV643XX_ETH_PHY_ADDR_REG, reg_data); | |
2295 | } | |
2296 | ||
2297 | /* | |
2298 | * ethernet_phy_reset - Reset Ethernet port PHY. | |
2299 | * | |
2300 | * DESCRIPTION: | |
2301 | * This routine utilizes the SMI interface to reset the ethernet port PHY. | |
2302 | * | |
2303 | * INPUT: | |
2304 | * unsigned int eth_port_num Ethernet Port number. | |
2305 | * | |
2306 | * OUTPUT: | |
2307 | * The PHY is reset. | |
2308 | * | |
2309 | * RETURN: | |
2310 | * None. | |
2311 | * | |
2312 | */ | |
2313 | static void ethernet_phy_reset(unsigned int eth_port_num) | |
2314 | { | |
2315 | unsigned int phy_reg_data; | |
2316 | ||
2317 | /* Reset the PHY */ | |
2318 | eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data); | |
2319 | phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */ | |
2320 | eth_port_write_smi_reg(eth_port_num, 0, phy_reg_data); | |
2321 | } | |
2322 | ||
2323 | /* | |
2324 | * eth_port_reset - Reset Ethernet port | |
2325 | * | |
2326 | * DESCRIPTION: | |
2327 | * This routine resets the chip by aborting any SDMA engine activity and | |
2328 | * clearing the MIB counters. The Receiver and the Transmit unit are in | |
2329 | * idle state after this command is performed and the port is disabled. | |
2330 | * | |
2331 | * INPUT: | |
2332 | * unsigned int eth_port_num Ethernet Port number. | |
2333 | * | |
2334 | * OUTPUT: | |
2335 | * Channel activity is halted. | |
2336 | * | |
2337 | * RETURN: | |
2338 | * None. | |
2339 | * | |
2340 | */ | |
2341 | static void eth_port_reset(unsigned int port_num) | |
2342 | { | |
2343 | unsigned int reg_data; | |
2344 | ||
2345 | /* Stop Tx port activity. Check port Tx activity. */ | |
2346 | reg_data = mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num)); | |
2347 | ||
2348 | if (reg_data & 0xFF) { | |
2349 | /* Issue stop command for active channels only */ | |
2350 | mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num), | |
2351 | (reg_data << 8)); | |
2352 | ||
2353 | /* Wait for all Tx activity to terminate. */ | |
2354 | /* Check port cause register that all Tx queues are stopped */ | |
2355 | while (mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num)) | |
2356 | & 0xFF) | |
2357 | udelay(10); | |
2358 | } | |
2359 | ||
2360 | /* Stop Rx port activity. Check port Rx activity. */ | |
2361 | reg_data = mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num)); | |
2362 | ||
2363 | if (reg_data & 0xFF) { | |
2364 | /* Issue stop command for active channels only */ | |
2365 | mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), | |
2366 | (reg_data << 8)); | |
2367 | ||
2368 | /* Wait for all Rx activity to terminate. */ | |
2369 | /* Check port cause register that all Rx queues are stopped */ | |
2370 | while (mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num)) | |
2371 | & 0xFF) | |
2372 | udelay(10); | |
2373 | } | |
2374 | ||
2375 | /* Clear all MIB counters */ | |
2376 | eth_clear_mib_counters(port_num); | |
2377 | ||
2378 | /* Reset the Enable bit in the Configuration Register */ | |
2379 | reg_data = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num)); | |
2380 | reg_data &= ~MV643XX_ETH_SERIAL_PORT_ENABLE; | |
2381 | mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), reg_data); | |
2382 | } | |
2383 | ||
1da177e4 LT |
2384 | |
2385 | static int eth_port_autoneg_supported(unsigned int eth_port_num) | |
2386 | { | |
2387 | unsigned int phy_reg_data0; | |
2388 | ||
2389 | eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data0); | |
2390 | ||
2391 | return phy_reg_data0 & 0x1000; | |
2392 | } | |
2393 | ||
2394 | static int eth_port_link_is_up(unsigned int eth_port_num) | |
2395 | { | |
2396 | unsigned int phy_reg_data1; | |
2397 | ||
2398 | eth_port_read_smi_reg(eth_port_num, 1, &phy_reg_data1); | |
2399 | ||
2400 | if (eth_port_autoneg_supported(eth_port_num)) { | |
2401 | if (phy_reg_data1 & 0x20) /* auto-neg complete */ | |
2402 | return 1; | |
2403 | } else if (phy_reg_data1 & 0x4) /* link up */ | |
2404 | return 1; | |
2405 | ||
2406 | return 0; | |
2407 | } | |
2408 | ||
1da177e4 LT |
2409 | /* |
2410 | * eth_port_read_smi_reg - Read PHY registers | |
2411 | * | |
2412 | * DESCRIPTION: | |
2413 | * This routine utilize the SMI interface to interact with the PHY in | |
2414 | * order to perform PHY register read. | |
2415 | * | |
2416 | * INPUT: | |
2417 | * unsigned int port_num Ethernet Port number. | |
2418 | * unsigned int phy_reg PHY register address offset. | |
2419 | * unsigned int *value Register value buffer. | |
2420 | * | |
2421 | * OUTPUT: | |
2422 | * Write the value of a specified PHY register into given buffer. | |
2423 | * | |
2424 | * RETURN: | |
2425 | * false if the PHY is busy or read data is not in valid state. | |
2426 | * true otherwise. | |
2427 | * | |
2428 | */ | |
2429 | static void eth_port_read_smi_reg(unsigned int port_num, | |
2430 | unsigned int phy_reg, unsigned int *value) | |
2431 | { | |
2432 | int phy_addr = ethernet_phy_get(port_num); | |
2433 | unsigned long flags; | |
2434 | int i; | |
2435 | ||
2436 | /* the SMI register is a shared resource */ | |
2437 | spin_lock_irqsave(&mv643xx_eth_phy_lock, flags); | |
2438 | ||
2439 | /* wait for the SMI register to become available */ | |
2440 | for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) { | |
2441 | if (i == PHY_WAIT_ITERATIONS) { | |
2442 | printk("mv643xx PHY busy timeout, port %d\n", port_num); | |
2443 | goto out; | |
2444 | } | |
2445 | udelay(PHY_WAIT_MICRO_SECONDS); | |
2446 | } | |
2447 | ||
2448 | mv_write(MV643XX_ETH_SMI_REG, | |
2449 | (phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ); | |
2450 | ||
2451 | /* now wait for the data to be valid */ | |
2452 | for (i = 0; !(mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_READ_VALID); i++) { | |
2453 | if (i == PHY_WAIT_ITERATIONS) { | |
2454 | printk("mv643xx PHY read timeout, port %d\n", port_num); | |
2455 | goto out; | |
2456 | } | |
2457 | udelay(PHY_WAIT_MICRO_SECONDS); | |
2458 | } | |
2459 | ||
2460 | *value = mv_read(MV643XX_ETH_SMI_REG) & 0xffff; | |
2461 | out: | |
2462 | spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags); | |
2463 | } | |
2464 | ||
2465 | /* | |
2466 | * eth_port_write_smi_reg - Write to PHY registers | |
2467 | * | |
2468 | * DESCRIPTION: | |
2469 | * This routine utilize the SMI interface to interact with the PHY in | |
2470 | * order to perform writes to PHY registers. | |
2471 | * | |
2472 | * INPUT: | |
2473 | * unsigned int eth_port_num Ethernet Port number. | |
2474 | * unsigned int phy_reg PHY register address offset. | |
2475 | * unsigned int value Register value. | |
2476 | * | |
2477 | * OUTPUT: | |
2478 | * Write the given value to the specified PHY register. | |
2479 | * | |
2480 | * RETURN: | |
2481 | * false if the PHY is busy. | |
2482 | * true otherwise. | |
2483 | * | |
2484 | */ | |
2485 | static void eth_port_write_smi_reg(unsigned int eth_port_num, | |
2486 | unsigned int phy_reg, unsigned int value) | |
2487 | { | |
2488 | int phy_addr; | |
2489 | int i; | |
2490 | unsigned long flags; | |
2491 | ||
2492 | phy_addr = ethernet_phy_get(eth_port_num); | |
2493 | ||
2494 | /* the SMI register is a shared resource */ | |
2495 | spin_lock_irqsave(&mv643xx_eth_phy_lock, flags); | |
2496 | ||
2497 | /* wait for the SMI register to become available */ | |
2498 | for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) { | |
2499 | if (i == PHY_WAIT_ITERATIONS) { | |
2500 | printk("mv643xx PHY busy timeout, port %d\n", | |
2501 | eth_port_num); | |
2502 | goto out; | |
2503 | } | |
2504 | udelay(PHY_WAIT_MICRO_SECONDS); | |
2505 | } | |
2506 | ||
2507 | mv_write(MV643XX_ETH_SMI_REG, (phy_addr << 16) | (phy_reg << 21) | | |
2508 | ETH_SMI_OPCODE_WRITE | (value & 0xffff)); | |
2509 | out: | |
2510 | spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags); | |
2511 | } | |
2512 | ||
2513 | /* | |
2514 | * eth_port_send - Send an Ethernet packet | |
2515 | * | |
2516 | * DESCRIPTION: | |
2517 | * This routine send a given packet described by p_pktinfo parameter. It | |
2518 | * supports transmitting of a packet spaned over multiple buffers. The | |
2519 | * routine updates 'curr' and 'first' indexes according to the packet | |
2520 | * segment passed to the routine. In case the packet segment is first, | |
2521 | * the 'first' index is update. In any case, the 'curr' index is updated. | |
2522 | * If the routine get into Tx resource error it assigns 'curr' index as | |
2523 | * 'first'. This way the function can abort Tx process of multiple | |
2524 | * descriptors per packet. | |
2525 | * | |
2526 | * INPUT: | |
2527 | * struct mv643xx_private *mp Ethernet Port Control srtuct. | |
2528 | * struct pkt_info *p_pkt_info User packet buffer. | |
2529 | * | |
2530 | * OUTPUT: | |
2531 | * Tx ring 'curr' and 'first' indexes are updated. | |
2532 | * | |
2533 | * RETURN: | |
2534 | * ETH_QUEUE_FULL in case of Tx resource error. | |
2535 | * ETH_ERROR in case the routine can not access Tx desc ring. | |
2536 | * ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource. | |
2537 | * ETH_OK otherwise. | |
2538 | * | |
2539 | */ | |
2540 | #ifdef MV643XX_CHECKSUM_OFFLOAD_TX | |
2541 | /* | |
2542 | * Modified to include the first descriptor pointer in case of SG | |
2543 | */ | |
2544 | static ETH_FUNC_RET_STATUS eth_port_send(struct mv643xx_private *mp, | |
2545 | struct pkt_info *p_pkt_info) | |
2546 | { | |
2547 | int tx_desc_curr, tx_desc_used, tx_first_desc, tx_next_desc; | |
2548 | struct eth_tx_desc *current_descriptor; | |
2549 | struct eth_tx_desc *first_descriptor; | |
2550 | u32 command; | |
2551 | ||
2552 | /* Do not process Tx ring in case of Tx ring resource error */ | |
2553 | if (mp->tx_resource_err) | |
2554 | return ETH_QUEUE_FULL; | |
2555 | ||
2556 | /* | |
2557 | * The hardware requires that each buffer that is <= 8 bytes | |
2558 | * in length must be aligned on an 8 byte boundary. | |
2559 | */ | |
2560 | if (p_pkt_info->byte_cnt <= 8 && p_pkt_info->buf_ptr & 0x7) { | |
2561 | printk(KERN_ERR | |
2562 | "mv643xx_eth port %d: packet size <= 8 problem\n", | |
2563 | mp->port_num); | |
2564 | return ETH_ERROR; | |
2565 | } | |
2566 | ||
f98e36f1 DF |
2567 | mp->tx_desc_count++; |
2568 | BUG_ON(mp->tx_desc_count > mp->tx_ring_size); | |
b111ceb6 | 2569 | |
1da177e4 LT |
2570 | /* Get the Tx Desc ring indexes */ |
2571 | tx_desc_curr = mp->tx_curr_desc_q; | |
2572 | tx_desc_used = mp->tx_used_desc_q; | |
2573 | ||
2574 | current_descriptor = &mp->p_tx_desc_area[tx_desc_curr]; | |
2575 | ||
2576 | tx_next_desc = (tx_desc_curr + 1) % mp->tx_ring_size; | |
2577 | ||
2578 | current_descriptor->buf_ptr = p_pkt_info->buf_ptr; | |
2579 | current_descriptor->byte_cnt = p_pkt_info->byte_cnt; | |
2580 | current_descriptor->l4i_chk = p_pkt_info->l4i_chk; | |
2581 | mp->tx_skb[tx_desc_curr] = p_pkt_info->return_info; | |
2582 | ||
2583 | command = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC | | |
2584 | ETH_BUFFER_OWNED_BY_DMA; | |
2585 | if (command & ETH_TX_FIRST_DESC) { | |
2586 | tx_first_desc = tx_desc_curr; | |
2587 | mp->tx_first_desc_q = tx_first_desc; | |
2588 | first_descriptor = current_descriptor; | |
2589 | mp->tx_first_command = command; | |
2590 | } else { | |
2591 | tx_first_desc = mp->tx_first_desc_q; | |
2592 | first_descriptor = &mp->p_tx_desc_area[tx_first_desc]; | |
2593 | BUG_ON(first_descriptor == NULL); | |
2594 | current_descriptor->cmd_sts = command; | |
2595 | } | |
2596 | ||
2597 | if (command & ETH_TX_LAST_DESC) { | |
2598 | wmb(); | |
2599 | first_descriptor->cmd_sts = mp->tx_first_command; | |
2600 | ||
2601 | wmb(); | |
2602 | ETH_ENABLE_TX_QUEUE(mp->port_num); | |
2603 | ||
2604 | /* | |
2605 | * Finish Tx packet. Update first desc in case of Tx resource | |
2606 | * error */ | |
2607 | tx_first_desc = tx_next_desc; | |
2608 | mp->tx_first_desc_q = tx_first_desc; | |
2609 | } | |
2610 | ||
2611 | /* Check for ring index overlap in the Tx desc ring */ | |
2612 | if (tx_next_desc == tx_desc_used) { | |
2613 | mp->tx_resource_err = 1; | |
2614 | mp->tx_curr_desc_q = tx_first_desc; | |
2615 | ||
2616 | return ETH_QUEUE_LAST_RESOURCE; | |
2617 | } | |
2618 | ||
2619 | mp->tx_curr_desc_q = tx_next_desc; | |
2620 | ||
2621 | return ETH_OK; | |
2622 | } | |
2623 | #else | |
2624 | static ETH_FUNC_RET_STATUS eth_port_send(struct mv643xx_private *mp, | |
2625 | struct pkt_info *p_pkt_info) | |
2626 | { | |
2627 | int tx_desc_curr; | |
2628 | int tx_desc_used; | |
2629 | struct eth_tx_desc *current_descriptor; | |
2630 | unsigned int command_status; | |
2631 | ||
2632 | /* Do not process Tx ring in case of Tx ring resource error */ | |
2633 | if (mp->tx_resource_err) | |
2634 | return ETH_QUEUE_FULL; | |
2635 | ||
f98e36f1 DF |
2636 | mp->tx_desc_count++; |
2637 | BUG_ON(mp->tx_desc_count > mp->tx_ring_size); | |
b111ceb6 | 2638 | |
1da177e4 LT |
2639 | /* Get the Tx Desc ring indexes */ |
2640 | tx_desc_curr = mp->tx_curr_desc_q; | |
2641 | tx_desc_used = mp->tx_used_desc_q; | |
2642 | current_descriptor = &mp->p_tx_desc_area[tx_desc_curr]; | |
2643 | ||
2644 | command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC; | |
2645 | current_descriptor->buf_ptr = p_pkt_info->buf_ptr; | |
2646 | current_descriptor->byte_cnt = p_pkt_info->byte_cnt; | |
2647 | mp->tx_skb[tx_desc_curr] = p_pkt_info->return_info; | |
2648 | ||
2649 | /* Set last desc with DMA ownership and interrupt enable. */ | |
2650 | wmb(); | |
2651 | current_descriptor->cmd_sts = command_status | | |
2652 | ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT; | |
2653 | ||
2654 | wmb(); | |
2655 | ETH_ENABLE_TX_QUEUE(mp->port_num); | |
2656 | ||
2657 | /* Finish Tx packet. Update first desc in case of Tx resource error */ | |
2658 | tx_desc_curr = (tx_desc_curr + 1) % mp->tx_ring_size; | |
2659 | ||
2660 | /* Update the current descriptor */ | |
2661 | mp->tx_curr_desc_q = tx_desc_curr; | |
2662 | ||
2663 | /* Check for ring index overlap in the Tx desc ring */ | |
2664 | if (tx_desc_curr == tx_desc_used) { | |
2665 | mp->tx_resource_err = 1; | |
2666 | return ETH_QUEUE_LAST_RESOURCE; | |
2667 | } | |
2668 | ||
2669 | return ETH_OK; | |
2670 | } | |
2671 | #endif | |
2672 | ||
2673 | /* | |
2674 | * eth_tx_return_desc - Free all used Tx descriptors | |
2675 | * | |
2676 | * DESCRIPTION: | |
2677 | * This routine returns the transmitted packet information to the caller. | |
2678 | * It uses the 'first' index to support Tx desc return in case a transmit | |
2679 | * of a packet spanned over multiple buffer still in process. | |
2680 | * In case the Tx queue was in "resource error" condition, where there are | |
2681 | * no available Tx resources, the function resets the resource error flag. | |
2682 | * | |
2683 | * INPUT: | |
2684 | * struct mv643xx_private *mp Ethernet Port Control srtuct. | |
2685 | * struct pkt_info *p_pkt_info User packet buffer. | |
2686 | * | |
2687 | * OUTPUT: | |
2688 | * Tx ring 'first' and 'used' indexes are updated. | |
2689 | * | |
2690 | * RETURN: | |
8f518703 DF |
2691 | * ETH_OK on success |
2692 | * ETH_ERROR otherwise. | |
1da177e4 LT |
2693 | * |
2694 | */ | |
2695 | static ETH_FUNC_RET_STATUS eth_tx_return_desc(struct mv643xx_private *mp, | |
2696 | struct pkt_info *p_pkt_info) | |
2697 | { | |
2698 | int tx_desc_used; | |
8f518703 DF |
2699 | int tx_busy_desc; |
2700 | struct eth_tx_desc *p_tx_desc_used; | |
2701 | unsigned int command_status; | |
2702 | unsigned long flags; | |
2703 | int err = ETH_OK; | |
2704 | ||
2705 | spin_lock_irqsave(&mp->lock, flags); | |
2706 | ||
1da177e4 | 2707 | #ifdef MV643XX_CHECKSUM_OFFLOAD_TX |
8f518703 | 2708 | tx_busy_desc = mp->tx_first_desc_q; |
1da177e4 | 2709 | #else |
8f518703 | 2710 | tx_busy_desc = mp->tx_curr_desc_q; |
1da177e4 | 2711 | #endif |
1da177e4 LT |
2712 | |
2713 | /* Get the Tx Desc ring indexes */ | |
2714 | tx_desc_used = mp->tx_used_desc_q; | |
2715 | ||
2716 | p_tx_desc_used = &mp->p_tx_desc_area[tx_desc_used]; | |
2717 | ||
2718 | /* Sanity check */ | |
8f518703 DF |
2719 | if (p_tx_desc_used == NULL) { |
2720 | err = ETH_ERROR; | |
2721 | goto out; | |
2722 | } | |
1da177e4 LT |
2723 | |
2724 | /* Stop release. About to overlap the current available Tx descriptor */ | |
8f518703 DF |
2725 | if (tx_desc_used == tx_busy_desc && !mp->tx_resource_err) { |
2726 | err = ETH_ERROR; | |
2727 | goto out; | |
2728 | } | |
1da177e4 LT |
2729 | |
2730 | command_status = p_tx_desc_used->cmd_sts; | |
2731 | ||
2732 | /* Still transmitting... */ | |
8f518703 DF |
2733 | if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { |
2734 | err = ETH_ERROR; | |
2735 | goto out; | |
2736 | } | |
1da177e4 LT |
2737 | |
2738 | /* Pass the packet information to the caller */ | |
2739 | p_pkt_info->cmd_sts = command_status; | |
2740 | p_pkt_info->return_info = mp->tx_skb[tx_desc_used]; | |
4eaa3cb3 PG |
2741 | p_pkt_info->buf_ptr = p_tx_desc_used->buf_ptr; |
2742 | p_pkt_info->byte_cnt = p_tx_desc_used->byte_cnt; | |
1da177e4 LT |
2743 | mp->tx_skb[tx_desc_used] = NULL; |
2744 | ||
2745 | /* Update the next descriptor to release. */ | |
2746 | mp->tx_used_desc_q = (tx_desc_used + 1) % mp->tx_ring_size; | |
2747 | ||
2748 | /* Any Tx return cancels the Tx resource error status */ | |
2749 | mp->tx_resource_err = 0; | |
2750 | ||
f98e36f1 DF |
2751 | BUG_ON(mp->tx_desc_count == 0); |
2752 | mp->tx_desc_count--; | |
b111ceb6 | 2753 | |
8f518703 DF |
2754 | out: |
2755 | spin_unlock_irqrestore(&mp->lock, flags); | |
2756 | ||
2757 | return err; | |
1da177e4 LT |
2758 | } |
2759 | ||
2760 | /* | |
2761 | * eth_port_receive - Get received information from Rx ring. | |
2762 | * | |
2763 | * DESCRIPTION: | |
2764 | * This routine returns the received data to the caller. There is no | |
2765 | * data copying during routine operation. All information is returned | |
2766 | * using pointer to packet information struct passed from the caller. | |
2767 | * If the routine exhausts Rx ring resources then the resource error flag | |
2768 | * is set. | |
2769 | * | |
2770 | * INPUT: | |
2771 | * struct mv643xx_private *mp Ethernet Port Control srtuct. | |
2772 | * struct pkt_info *p_pkt_info User packet buffer. | |
2773 | * | |
2774 | * OUTPUT: | |
2775 | * Rx ring current and used indexes are updated. | |
2776 | * | |
2777 | * RETURN: | |
2778 | * ETH_ERROR in case the routine can not access Rx desc ring. | |
2779 | * ETH_QUEUE_FULL if Rx ring resources are exhausted. | |
2780 | * ETH_END_OF_JOB if there is no received data. | |
2781 | * ETH_OK otherwise. | |
2782 | */ | |
2783 | static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp, | |
2784 | struct pkt_info *p_pkt_info) | |
2785 | { | |
2786 | int rx_next_curr_desc, rx_curr_desc, rx_used_desc; | |
2787 | volatile struct eth_rx_desc *p_rx_desc; | |
2788 | unsigned int command_status; | |
8f518703 | 2789 | unsigned long flags; |
1da177e4 LT |
2790 | |
2791 | /* Do not process Rx ring in case of Rx ring resource error */ | |
2792 | if (mp->rx_resource_err) | |
2793 | return ETH_QUEUE_FULL; | |
2794 | ||
8f518703 DF |
2795 | spin_lock_irqsave(&mp->lock, flags); |
2796 | ||
1da177e4 LT |
2797 | /* Get the Rx Desc ring 'curr and 'used' indexes */ |
2798 | rx_curr_desc = mp->rx_curr_desc_q; | |
2799 | rx_used_desc = mp->rx_used_desc_q; | |
2800 | ||
2801 | p_rx_desc = &mp->p_rx_desc_area[rx_curr_desc]; | |
2802 | ||
2803 | /* The following parameters are used to save readings from memory */ | |
2804 | command_status = p_rx_desc->cmd_sts; | |
2805 | rmb(); | |
2806 | ||
2807 | /* Nothing to receive... */ | |
8f518703 DF |
2808 | if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { |
2809 | spin_unlock_irqrestore(&mp->lock, flags); | |
1da177e4 | 2810 | return ETH_END_OF_JOB; |
8f518703 | 2811 | } |
1da177e4 LT |
2812 | |
2813 | p_pkt_info->byte_cnt = (p_rx_desc->byte_cnt) - RX_BUF_OFFSET; | |
2814 | p_pkt_info->cmd_sts = command_status; | |
2815 | p_pkt_info->buf_ptr = (p_rx_desc->buf_ptr) + RX_BUF_OFFSET; | |
2816 | p_pkt_info->return_info = mp->rx_skb[rx_curr_desc]; | |
2817 | p_pkt_info->l4i_chk = p_rx_desc->buf_size; | |
2818 | ||
b4de9051 DF |
2819 | /* |
2820 | * Clean the return info field to indicate that the | |
2821 | * packet has been moved to the upper layers | |
2822 | */ | |
1da177e4 LT |
2823 | mp->rx_skb[rx_curr_desc] = NULL; |
2824 | ||
2825 | /* Update current index in data structure */ | |
2826 | rx_next_curr_desc = (rx_curr_desc + 1) % mp->rx_ring_size; | |
2827 | mp->rx_curr_desc_q = rx_next_curr_desc; | |
2828 | ||
2829 | /* Rx descriptors exhausted. Set the Rx ring resource error flag */ | |
2830 | if (rx_next_curr_desc == rx_used_desc) | |
2831 | mp->rx_resource_err = 1; | |
2832 | ||
8f518703 DF |
2833 | spin_unlock_irqrestore(&mp->lock, flags); |
2834 | ||
1da177e4 LT |
2835 | return ETH_OK; |
2836 | } | |
2837 | ||
2838 | /* | |
2839 | * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring. | |
2840 | * | |
2841 | * DESCRIPTION: | |
2842 | * This routine returns a Rx buffer back to the Rx ring. It retrieves the | |
2843 | * next 'used' descriptor and attached the returned buffer to it. | |
2844 | * In case the Rx ring was in "resource error" condition, where there are | |
2845 | * no available Rx resources, the function resets the resource error flag. | |
2846 | * | |
2847 | * INPUT: | |
2848 | * struct mv643xx_private *mp Ethernet Port Control srtuct. | |
2849 | * struct pkt_info *p_pkt_info Information on returned buffer. | |
2850 | * | |
2851 | * OUTPUT: | |
2852 | * New available Rx resource in Rx descriptor ring. | |
2853 | * | |
2854 | * RETURN: | |
2855 | * ETH_ERROR in case the routine can not access Rx desc ring. | |
2856 | * ETH_OK otherwise. | |
2857 | */ | |
2858 | static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp, | |
2859 | struct pkt_info *p_pkt_info) | |
2860 | { | |
2861 | int used_rx_desc; /* Where to return Rx resource */ | |
2862 | volatile struct eth_rx_desc *p_used_rx_desc; | |
8f518703 DF |
2863 | unsigned long flags; |
2864 | ||
2865 | spin_lock_irqsave(&mp->lock, flags); | |
1da177e4 LT |
2866 | |
2867 | /* Get 'used' Rx descriptor */ | |
2868 | used_rx_desc = mp->rx_used_desc_q; | |
2869 | p_used_rx_desc = &mp->p_rx_desc_area[used_rx_desc]; | |
2870 | ||
2871 | p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr; | |
2872 | p_used_rx_desc->buf_size = p_pkt_info->byte_cnt; | |
2873 | mp->rx_skb[used_rx_desc] = p_pkt_info->return_info; | |
2874 | ||
2875 | /* Flush the write pipe */ | |
2876 | ||
2877 | /* Return the descriptor to DMA ownership */ | |
2878 | wmb(); | |
2879 | p_used_rx_desc->cmd_sts = | |
2880 | ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT; | |
2881 | wmb(); | |
2882 | ||
2883 | /* Move the used descriptor pointer to the next descriptor */ | |
2884 | mp->rx_used_desc_q = (used_rx_desc + 1) % mp->rx_ring_size; | |
2885 | ||
2886 | /* Any Rx return cancels the Rx resource error status */ | |
2887 | mp->rx_resource_err = 0; | |
2888 | ||
8f518703 DF |
2889 | spin_unlock_irqrestore(&mp->lock, flags); |
2890 | ||
1da177e4 LT |
2891 | return ETH_OK; |
2892 | } | |
2893 | ||
2894 | /************* Begin ethtool support *************************/ | |
2895 | ||
2896 | struct mv643xx_stats { | |
2897 | char stat_string[ETH_GSTRING_LEN]; | |
2898 | int sizeof_stat; | |
2899 | int stat_offset; | |
2900 | }; | |
2901 | ||
2902 | #define MV643XX_STAT(m) sizeof(((struct mv643xx_private *)0)->m), \ | |
b4de9051 | 2903 | offsetof(struct mv643xx_private, m) |
1da177e4 LT |
2904 | |
2905 | static const struct mv643xx_stats mv643xx_gstrings_stats[] = { | |
2906 | { "rx_packets", MV643XX_STAT(stats.rx_packets) }, | |
2907 | { "tx_packets", MV643XX_STAT(stats.tx_packets) }, | |
2908 | { "rx_bytes", MV643XX_STAT(stats.rx_bytes) }, | |
2909 | { "tx_bytes", MV643XX_STAT(stats.tx_bytes) }, | |
2910 | { "rx_errors", MV643XX_STAT(stats.rx_errors) }, | |
2911 | { "tx_errors", MV643XX_STAT(stats.tx_errors) }, | |
2912 | { "rx_dropped", MV643XX_STAT(stats.rx_dropped) }, | |
2913 | { "tx_dropped", MV643XX_STAT(stats.tx_dropped) }, | |
2914 | { "good_octets_received", MV643XX_STAT(mib_counters.good_octets_received) }, | |
2915 | { "bad_octets_received", MV643XX_STAT(mib_counters.bad_octets_received) }, | |
2916 | { "internal_mac_transmit_err", MV643XX_STAT(mib_counters.internal_mac_transmit_err) }, | |
2917 | { "good_frames_received", MV643XX_STAT(mib_counters.good_frames_received) }, | |
2918 | { "bad_frames_received", MV643XX_STAT(mib_counters.bad_frames_received) }, | |
2919 | { "broadcast_frames_received", MV643XX_STAT(mib_counters.broadcast_frames_received) }, | |
2920 | { "multicast_frames_received", MV643XX_STAT(mib_counters.multicast_frames_received) }, | |
2921 | { "frames_64_octets", MV643XX_STAT(mib_counters.frames_64_octets) }, | |
2922 | { "frames_65_to_127_octets", MV643XX_STAT(mib_counters.frames_65_to_127_octets) }, | |
2923 | { "frames_128_to_255_octets", MV643XX_STAT(mib_counters.frames_128_to_255_octets) }, | |
2924 | { "frames_256_to_511_octets", MV643XX_STAT(mib_counters.frames_256_to_511_octets) }, | |
2925 | { "frames_512_to_1023_octets", MV643XX_STAT(mib_counters.frames_512_to_1023_octets) }, | |
2926 | { "frames_1024_to_max_octets", MV643XX_STAT(mib_counters.frames_1024_to_max_octets) }, | |
2927 | { "good_octets_sent", MV643XX_STAT(mib_counters.good_octets_sent) }, | |
2928 | { "good_frames_sent", MV643XX_STAT(mib_counters.good_frames_sent) }, | |
2929 | { "excessive_collision", MV643XX_STAT(mib_counters.excessive_collision) }, | |
2930 | { "multicast_frames_sent", MV643XX_STAT(mib_counters.multicast_frames_sent) }, | |
2931 | { "broadcast_frames_sent", MV643XX_STAT(mib_counters.broadcast_frames_sent) }, | |
2932 | { "unrec_mac_control_received", MV643XX_STAT(mib_counters.unrec_mac_control_received) }, | |
2933 | { "fc_sent", MV643XX_STAT(mib_counters.fc_sent) }, | |
2934 | { "good_fc_received", MV643XX_STAT(mib_counters.good_fc_received) }, | |
2935 | { "bad_fc_received", MV643XX_STAT(mib_counters.bad_fc_received) }, | |
2936 | { "undersize_received", MV643XX_STAT(mib_counters.undersize_received) }, | |
2937 | { "fragments_received", MV643XX_STAT(mib_counters.fragments_received) }, | |
2938 | { "oversize_received", MV643XX_STAT(mib_counters.oversize_received) }, | |
2939 | { "jabber_received", MV643XX_STAT(mib_counters.jabber_received) }, | |
2940 | { "mac_receive_error", MV643XX_STAT(mib_counters.mac_receive_error) }, | |
2941 | { "bad_crc_event", MV643XX_STAT(mib_counters.bad_crc_event) }, | |
2942 | { "collision", MV643XX_STAT(mib_counters.collision) }, | |
2943 | { "late_collision", MV643XX_STAT(mib_counters.late_collision) }, | |
2944 | }; | |
2945 | ||
2946 | #define MV643XX_STATS_LEN \ | |
2947 | sizeof(mv643xx_gstrings_stats) / sizeof(struct mv643xx_stats) | |
2948 | ||
2949 | static int | |
2950 | mv643xx_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd) | |
2951 | { | |
2952 | struct mv643xx_private *mp = netdev->priv; | |
2953 | int port_num = mp->port_num; | |
2954 | int autoneg = eth_port_autoneg_supported(port_num); | |
2955 | int mode_10_bit; | |
2956 | int auto_duplex; | |
2957 | int half_duplex = 0; | |
2958 | int full_duplex = 0; | |
2959 | int auto_speed; | |
2960 | int speed_10 = 0; | |
2961 | int speed_100 = 0; | |
2962 | int speed_1000 = 0; | |
2963 | ||
2964 | u32 pcs = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num)); | |
2965 | u32 psr = mv_read(MV643XX_ETH_PORT_STATUS_REG(port_num)); | |
2966 | ||
2967 | mode_10_bit = psr & MV643XX_ETH_PORT_STATUS_MODE_10_BIT; | |
2968 | ||
2969 | if (mode_10_bit) { | |
2970 | ecmd->supported = SUPPORTED_10baseT_Half; | |
2971 | } else { | |
2972 | ecmd->supported = (SUPPORTED_10baseT_Half | | |
2973 | SUPPORTED_10baseT_Full | | |
2974 | SUPPORTED_100baseT_Half | | |
2975 | SUPPORTED_100baseT_Full | | |
2976 | SUPPORTED_1000baseT_Full | | |
2977 | (autoneg ? SUPPORTED_Autoneg : 0) | | |
2978 | SUPPORTED_TP); | |
2979 | ||
2980 | auto_duplex = !(pcs & MV643XX_ETH_DISABLE_AUTO_NEG_FOR_DUPLX); | |
2981 | auto_speed = !(pcs & MV643XX_ETH_DISABLE_AUTO_NEG_SPEED_GMII); | |
2982 | ||
2983 | ecmd->advertising = ADVERTISED_TP; | |
2984 | ||
2985 | if (autoneg) { | |
2986 | ecmd->advertising |= ADVERTISED_Autoneg; | |
2987 | ||
2988 | if (auto_duplex) { | |
2989 | half_duplex = 1; | |
2990 | full_duplex = 1; | |
2991 | } else { | |
2992 | if (pcs & MV643XX_ETH_SET_FULL_DUPLEX_MODE) | |
2993 | full_duplex = 1; | |
2994 | else | |
2995 | half_duplex = 1; | |
2996 | } | |
2997 | ||
2998 | if (auto_speed) { | |
2999 | speed_10 = 1; | |
3000 | speed_100 = 1; | |
3001 | speed_1000 = 1; | |
3002 | } else { | |
3003 | if (pcs & MV643XX_ETH_SET_GMII_SPEED_TO_1000) | |
3004 | speed_1000 = 1; | |
3005 | else if (pcs & MV643XX_ETH_SET_MII_SPEED_TO_100) | |
3006 | speed_100 = 1; | |
3007 | else | |
3008 | speed_10 = 1; | |
3009 | } | |
3010 | ||
3011 | if (speed_10 & half_duplex) | |
3012 | ecmd->advertising |= ADVERTISED_10baseT_Half; | |
3013 | if (speed_10 & full_duplex) | |
3014 | ecmd->advertising |= ADVERTISED_10baseT_Full; | |
3015 | if (speed_100 & half_duplex) | |
3016 | ecmd->advertising |= ADVERTISED_100baseT_Half; | |
3017 | if (speed_100 & full_duplex) | |
3018 | ecmd->advertising |= ADVERTISED_100baseT_Full; | |
3019 | if (speed_1000) | |
3020 | ecmd->advertising |= ADVERTISED_1000baseT_Full; | |
3021 | } | |
3022 | } | |
3023 | ||
3024 | ecmd->port = PORT_TP; | |
3025 | ecmd->phy_address = ethernet_phy_get(port_num); | |
3026 | ||
3027 | ecmd->transceiver = XCVR_EXTERNAL; | |
3028 | ||
3029 | if (netif_carrier_ok(netdev)) { | |
3030 | if (mode_10_bit) | |
3031 | ecmd->speed = SPEED_10; | |
3032 | else { | |
3033 | if (psr & MV643XX_ETH_PORT_STATUS_GMII_1000) | |
3034 | ecmd->speed = SPEED_1000; | |
3035 | else if (psr & MV643XX_ETH_PORT_STATUS_MII_100) | |
3036 | ecmd->speed = SPEED_100; | |
3037 | else | |
3038 | ecmd->speed = SPEED_10; | |
3039 | } | |
3040 | ||
3041 | if (psr & MV643XX_ETH_PORT_STATUS_FULL_DUPLEX) | |
3042 | ecmd->duplex = DUPLEX_FULL; | |
3043 | else | |
3044 | ecmd->duplex = DUPLEX_HALF; | |
3045 | } else { | |
3046 | ecmd->speed = -1; | |
3047 | ecmd->duplex = -1; | |
3048 | } | |
3049 | ||
3050 | ecmd->autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE; | |
3051 | return 0; | |
3052 | } | |
3053 | ||
b4de9051 DF |
3054 | static void mv643xx_get_drvinfo(struct net_device *netdev, |
3055 | struct ethtool_drvinfo *drvinfo) | |
1da177e4 LT |
3056 | { |
3057 | strncpy(drvinfo->driver, mv643xx_driver_name, 32); | |
3058 | strncpy(drvinfo->version, mv643xx_driver_version, 32); | |
3059 | strncpy(drvinfo->fw_version, "N/A", 32); | |
3060 | strncpy(drvinfo->bus_info, "mv643xx", 32); | |
3061 | drvinfo->n_stats = MV643XX_STATS_LEN; | |
3062 | } | |
3063 | ||
b4de9051 | 3064 | static int mv643xx_get_stats_count(struct net_device *netdev) |
1da177e4 LT |
3065 | { |
3066 | return MV643XX_STATS_LEN; | |
3067 | } | |
3068 | ||
b4de9051 DF |
3069 | static void mv643xx_get_ethtool_stats(struct net_device *netdev, |
3070 | struct ethtool_stats *stats, uint64_t *data) | |
1da177e4 LT |
3071 | { |
3072 | struct mv643xx_private *mp = netdev->priv; | |
3073 | int i; | |
3074 | ||
3075 | eth_update_mib_counters(mp); | |
3076 | ||
b4de9051 | 3077 | for (i = 0; i < MV643XX_STATS_LEN; i++) { |
1da177e4 | 3078 | char *p = (char *)mp+mv643xx_gstrings_stats[i].stat_offset; |
b4de9051 | 3079 | data[i] = (mv643xx_gstrings_stats[i].sizeof_stat == |
1da177e4 LT |
3080 | sizeof(uint64_t)) ? *(uint64_t *)p : *(uint32_t *)p; |
3081 | } | |
3082 | } | |
3083 | ||
b4de9051 DF |
3084 | static void mv643xx_get_strings(struct net_device *netdev, uint32_t stringset, |
3085 | uint8_t *data) | |
1da177e4 LT |
3086 | { |
3087 | int i; | |
3088 | ||
3089 | switch(stringset) { | |
3090 | case ETH_SS_STATS: | |
3091 | for (i=0; i < MV643XX_STATS_LEN; i++) { | |
b4de9051 DF |
3092 | memcpy(data + i * ETH_GSTRING_LEN, |
3093 | mv643xx_gstrings_stats[i].stat_string, | |
3094 | ETH_GSTRING_LEN); | |
1da177e4 LT |
3095 | } |
3096 | break; | |
3097 | } | |
3098 | } | |
3099 | ||
3100 | static struct ethtool_ops mv643xx_ethtool_ops = { | |
3101 | .get_settings = mv643xx_get_settings, | |
3102 | .get_drvinfo = mv643xx_get_drvinfo, | |
3103 | .get_link = ethtool_op_get_link, | |
3104 | .get_sg = ethtool_op_get_sg, | |
3105 | .set_sg = ethtool_op_set_sg, | |
3106 | .get_strings = mv643xx_get_strings, | |
3107 | .get_stats_count = mv643xx_get_stats_count, | |
3108 | .get_ethtool_stats = mv643xx_get_ethtool_stats, | |
3109 | }; | |
3110 | ||
3111 | /************* End ethtool support *************************/ |