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Revert "mv643xx_eth: use longer DMA bursts".
[linux-2.6-block.git] / drivers / net / mv643xx_eth.c
CommitLineData
1da177e4 1/*
9c1bbdfe 2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
1da177e4
LT		 3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
4547fa61
LB		 6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
1da177e4
LT		 8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
3bb8a18a 10 * written by Manish Lachwani
1da177e4
LT		 11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
c8aaea25 14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
1da177e4
LT		 15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
4547fa61
LB		 20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
1da177e4
LT		 23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36 */
a779d38c 37
1da177e4
LT		 38#include <linux/init.h>
39#include <linux/dma-mapping.h>
b6298c22 40#include <linux/in.h>
c3efab8e 41#include <linux/ip.h>
1da177e4
LT		 42#include <linux/tcp.h>
43#include <linux/udp.h>
44#include <linux/etherdevice.h>
1da177e4
LT		 45#include <linux/delay.h>
46#include <linux/ethtool.h>
d052d1be 47#include <linux/platform_device.h>
fbd6a754
LB		 48#include <linux/module.h>
49#include <linux/kernel.h>
50#include <linux/spinlock.h>
51#include <linux/workqueue.h>
ed94493f 52#include <linux/phy.h>
fbd6a754 53#include <linux/mv643xx_eth.h>
10a9948d
LB		 54#include <linux/io.h>
55#include <linux/types.h>
1da177e4 56#include <asm/system.h>
fbd6a754 57
e5371493 58static char mv643xx_eth_driver_name[] = "mv643xx_eth";
042af53c 59static char mv643xx_eth_driver_version[] = "1.4";
c9df406f 60
fbd6a754 61
fbd6a754
LB		 62/*
63 * Registers shared between all ports.
64 */
3cb4667c
LB		 65#define PHY_ADDR 0x0000
66#define SMI_REG 0x0004
45c5d3bc
LB		 67#define SMI_BUSY 0x10000000
68#define SMI_READ_VALID 0x08000000
69#define SMI_OPCODE_READ 0x04000000
70#define SMI_OPCODE_WRITE 0x00000000
71#define ERR_INT_CAUSE 0x0080
72#define ERR_INT_SMI_DONE 0x00000010
73#define ERR_INT_MASK 0x0084
3cb4667c
LB		 74#define WINDOW_BASE(w) (0x0200 + ((w) << 3))
75#define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
76#define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
77#define WINDOW_BAR_ENABLE 0x0290
78#define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
fbd6a754
LB		 79
80/*
37a6084f
LB		 81 * Main per-port registers. These live at offset 0x0400 for
82 * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
fbd6a754 83 */
37a6084f 84#define PORT_CONFIG 0x0000
d9a073ea 85#define UNICAST_PROMISCUOUS_MODE 0x00000001
37a6084f
LB		 86#define PORT_CONFIG_EXT 0x0004
87#define MAC_ADDR_LOW 0x0014
88#define MAC_ADDR_HIGH 0x0018
89#define SDMA_CONFIG 0x001c
90#define PORT_SERIAL_CONTROL 0x003c
91#define PORT_STATUS 0x0044
a2a41689 92#define TX_FIFO_EMPTY 0x00000400
ae9ae064 93#define TX_IN_PROGRESS 0x00000080
2f7eb47a
LB		 94#define PORT_SPEED_MASK 0x00000030
95#define PORT_SPEED_1000 0x00000010
96#define PORT_SPEED_100 0x00000020
97#define PORT_SPEED_10 0x00000000
98#define FLOW_CONTROL_ENABLED 0x00000008
99#define FULL_DUPLEX 0x00000004
81600eea 100#define LINK_UP 0x00000002
37a6084f
LB		 101#define TXQ_COMMAND 0x0048
102#define TXQ_FIX_PRIO_CONF 0x004c
103#define TX_BW_RATE 0x0050
104#define TX_BW_MTU 0x0058
105#define TX_BW_BURST 0x005c
106#define INT_CAUSE 0x0060
226bb6b7 107#define INT_TX_END 0x07f80000
befefe21 108#define INT_RX 0x000003fc
073a345c 109#define INT_EXT 0x00000002
37a6084f 110#define INT_CAUSE_EXT 0x0064
befefe21
LB		 111#define INT_EXT_LINK_PHY 0x00110000
112#define INT_EXT_TX 0x000000ff
37a6084f
LB		 113#define INT_MASK 0x0068
114#define INT_MASK_EXT 0x006c
115#define TX_FIFO_URGENT_THRESHOLD 0x0074
116#define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
117#define TX_BW_RATE_MOVED 0x00e0
118#define TX_BW_MTU_MOVED 0x00e8
119#define TX_BW_BURST_MOVED 0x00ec
120#define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4))
121#define RXQ_COMMAND 0x0280
122#define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2))
123#define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4))
124#define TXQ_BW_CONF(q) (0x0304 + ((q) << 4))
125#define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4))
126
127/*
128 * Misc per-port registers.
129 */
3cb4667c
LB		 130#define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
131#define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
132#define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
133#define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
fbd6a754 134
2679a550
LB		 135
136/*
137 * SDMA configuration register.
138 */
e0c6ef93 139#define RX_BURST_SIZE_4_64BIT (2 << 1)
cd4ccf76 140#define RX_BURST_SIZE_16_64BIT (4 << 1)
fbd6a754 141#define BLM_RX_NO_SWAP (1 << 4)
fbd6a754 142#define BLM_TX_NO_SWAP (1 << 5)
e0c6ef93 143#define TX_BURST_SIZE_4_64BIT (2 << 22)
cd4ccf76 144#define TX_BURST_SIZE_16_64BIT (4 << 22)
fbd6a754
LB		 145
146#if defined(__BIG_ENDIAN)
147#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
e0c6ef93
LB		 148 (RX_BURST_SIZE_4_64BIT | \
149 TX_BURST_SIZE_4_64BIT)
fbd6a754
LB		 150#elif defined(__LITTLE_ENDIAN)
151#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
e0c6ef93
LB		 152 (RX_BURST_SIZE_4_64BIT | \
153 BLM_RX_NO_SWAP | \
154 BLM_TX_NO_SWAP | \
155 TX_BURST_SIZE_4_64BIT)
fbd6a754
LB		 156#else
157#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
158#endif
159
2beff77b
LB		 160
161/*
162 * Port serial control register.
163 */
164#define SET_MII_SPEED_TO_100 (1 << 24)
165#define SET_GMII_SPEED_TO_1000 (1 << 23)
166#define SET_FULL_DUPLEX_MODE (1 << 21)
fbd6a754 167#define MAX_RX_PACKET_9700BYTE (5 << 17)
2beff77b
LB		 168#define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
169#define DO_NOT_FORCE_LINK_FAIL (1 << 10)
170#define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
171#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
172#define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
173#define FORCE_LINK_PASS (1 << 1)
174#define SERIAL_PORT_ENABLE (1 << 0)
fbd6a754 175
2b4a624d
LB		 176#define DEFAULT_RX_QUEUE_SIZE 128
177#define DEFAULT_TX_QUEUE_SIZE 256
fbd6a754 178
fbd6a754 179
7ca72a3b
LB		 180/*
181 * RX/TX descriptors.
fbd6a754
LB		 182 */
183#if defined(__BIG_ENDIAN)
cc9754b3 184struct rx_desc {
fbd6a754
LB		 185 u16 byte_cnt; /* Descriptor buffer byte count */
186 u16 buf_size; /* Buffer size */
187 u32 cmd_sts; /* Descriptor command status */
188 u32 next_desc_ptr; /* Next descriptor pointer */
189 u32 buf_ptr; /* Descriptor buffer pointer */
190};
191
cc9754b3 192struct tx_desc {
fbd6a754
LB		 193 u16 byte_cnt; /* buffer byte count */
194 u16 l4i_chk; /* CPU provided TCP checksum */
195 u32 cmd_sts; /* Command/status field */
196 u32 next_desc_ptr; /* Pointer to next descriptor */
197 u32 buf_ptr; /* pointer to buffer for this descriptor*/
198};
199#elif defined(__LITTLE_ENDIAN)
cc9754b3 200struct rx_desc {
fbd6a754
LB		 201 u32 cmd_sts; /* Descriptor command status */
202 u16 buf_size; /* Buffer size */
203 u16 byte_cnt; /* Descriptor buffer byte count */
204 u32 buf_ptr; /* Descriptor buffer pointer */
205 u32 next_desc_ptr; /* Next descriptor pointer */
206};
207
cc9754b3 208struct tx_desc {
fbd6a754
LB		 209 u32 cmd_sts; /* Command/status field */
210 u16 l4i_chk; /* CPU provided TCP checksum */
211 u16 byte_cnt; /* buffer byte count */
212 u32 buf_ptr; /* pointer to buffer for this descriptor*/
213 u32 next_desc_ptr; /* Pointer to next descriptor */
214};
215#else
216#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
217#endif
218
7ca72a3b 219/* RX & TX descriptor command */
cc9754b3 220#define BUFFER_OWNED_BY_DMA 0x80000000
7ca72a3b
LB		 221
222/* RX & TX descriptor status */
cc9754b3 223#define ERROR_SUMMARY 0x00000001
7ca72a3b
LB		 224
225/* RX descriptor status */
cc9754b3
LB		 226#define LAYER_4_CHECKSUM_OK 0x40000000
227#define RX_ENABLE_INTERRUPT 0x20000000
228#define RX_FIRST_DESC 0x08000000
229#define RX_LAST_DESC 0x04000000
7ca72a3b
LB		 230
231/* TX descriptor command */
cc9754b3
LB		 232#define TX_ENABLE_INTERRUPT 0x00800000
233#define GEN_CRC 0x00400000
234#define TX_FIRST_DESC 0x00200000
235#define TX_LAST_DESC 0x00100000
236#define ZERO_PADDING 0x00080000
237#define GEN_IP_V4_CHECKSUM 0x00040000
238#define GEN_TCP_UDP_CHECKSUM 0x00020000
239#define UDP_FRAME 0x00010000
e32b6617
LB		 240#define MAC_HDR_EXTRA_4_BYTES 0x00008000
241#define MAC_HDR_EXTRA_8_BYTES 0x00000200
7ca72a3b 242
cc9754b3 243#define TX_IHL_SHIFT 11
7ca72a3b
LB		 244
245
c9df406f 246/* global *******************************************************************/
e5371493 247struct mv643xx_eth_shared_private {
fc32b0e2
LB		 248 /*
249 * Ethernet controller base address.
250 */
cc9754b3 251 void __iomem *base;
c9df406f 252
fc0eb9f2
LB		 253 /*
254 * Points at the right SMI instance to use.
255 */
256 struct mv643xx_eth_shared_private *smi;
257
fc32b0e2 258 /*
ed94493f 259 * Provides access to local SMI interface.
fc32b0e2 260 */
298cf9be 261 struct mii_bus *smi_bus;
c9df406f 262
45c5d3bc
LB		 263 /*
264 * If we have access to the error interrupt pin (which is
265 * somewhat misnamed as it not only reflects internal errors
266 * but also reflects SMI completion), use that to wait for
267 * SMI access completion instead of polling the SMI busy bit.
268 */
269 int err_interrupt;
270 wait_queue_head_t smi_busy_wait;
271
fc32b0e2
LB		 272 /*
273 * Per-port MBUS window access register value.
274 */
c9df406f
LB		 275 u32 win_protect;
276
fc32b0e2
LB		 277 /*
278 * Hardware-specific parameters.
279 */
c9df406f 280 unsigned int t_clk;
773fc3ee 281 int extended_rx_coal_limit;
457b1d5a 282 int tx_bw_control;
c9df406f
LB		 283};
284
457b1d5a
LB		 285#define TX_BW_CONTROL_ABSENT 0
286#define TX_BW_CONTROL_OLD_LAYOUT 1
287#define TX_BW_CONTROL_NEW_LAYOUT 2
288
c9df406f
LB		 289
290/* per-port *****************************************************************/
e5371493 291struct mib_counters {
fbd6a754
LB		 292 u64 good_octets_received;
293 u32 bad_octets_received;
294 u32 internal_mac_transmit_err;
295 u32 good_frames_received;
296 u32 bad_frames_received;
297 u32 broadcast_frames_received;
298 u32 multicast_frames_received;
299 u32 frames_64_octets;
300 u32 frames_65_to_127_octets;
301 u32 frames_128_to_255_octets;
302 u32 frames_256_to_511_octets;
303 u32 frames_512_to_1023_octets;
304 u32 frames_1024_to_max_octets;
305 u64 good_octets_sent;
306 u32 good_frames_sent;
307 u32 excessive_collision;
308 u32 multicast_frames_sent;
309 u32 broadcast_frames_sent;
310 u32 unrec_mac_control_received;
311 u32 fc_sent;
312 u32 good_fc_received;
313 u32 bad_fc_received;
314 u32 undersize_received;
315 u32 fragments_received;
316 u32 oversize_received;
317 u32 jabber_received;
318 u32 mac_receive_error;
319 u32 bad_crc_event;
320 u32 collision;
321 u32 late_collision;
322};
323
8a578111 324struct rx_queue {
64da80a2
LB		 325 int index;
326
8a578111
LB		 327 int rx_ring_size;
328
329 int rx_desc_count;
330 int rx_curr_desc;
331 int rx_used_desc;
332
333 struct rx_desc *rx_desc_area;
334 dma_addr_t rx_desc_dma;
335 int rx_desc_area_size;
336 struct sk_buff **rx_skb;
8a578111
LB		 337};
338
13d64285 339struct tx_queue {
3d6b35bc
LB		 340 int index;
341
13d64285 342 int tx_ring_size;
fbd6a754 343
13d64285
LB		 344 int tx_desc_count;
345 int tx_curr_desc;
346 int tx_used_desc;
fbd6a754 347
5daffe94 348 struct tx_desc *tx_desc_area;
fbd6a754
LB		 349 dma_addr_t tx_desc_dma;
350 int tx_desc_area_size;
99ab08e0
LB		 351
352 struct sk_buff_head tx_skb;
8fd89211
LB		 353
354 unsigned long tx_packets;
355 unsigned long tx_bytes;
356 unsigned long tx_dropped;
13d64285
LB		 357};
358
359struct mv643xx_eth_private {
360 struct mv643xx_eth_shared_private *shared;
37a6084f 361 void __iomem *base;
fc32b0e2 362 int port_num;
13d64285 363
fc32b0e2 364 struct net_device *dev;
fbd6a754 365
ed94493f 366 struct phy_device *phy;
fbd6a754 367
4ff3495a
LB		 368 struct timer_list mib_counters_timer;
369 spinlock_t mib_counters_lock;
fc32b0e2 370 struct mib_counters mib_counters;
4ff3495a 371
fc32b0e2 372 struct work_struct tx_timeout_task;
8a578111 373
1fa38c58
LB		 374 struct napi_struct napi;
375 u8 work_link;
376 u8 work_tx;
377 u8 work_tx_end;
378 u8 work_rx;
379 u8 work_rx_refill;
380 u8 work_rx_oom;
381
2bcb4b0f
LB		 382 int skb_size;
383 struct sk_buff_head rx_recycle;
384
8a578111
LB		 385 /*
386 * RX state.
387 */
388 int default_rx_ring_size;
389 unsigned long rx_desc_sram_addr;
390 int rx_desc_sram_size;
f7981c1c 391 int rxq_count;
2257e05c 392 struct timer_list rx_oom;
64da80a2 393 struct rx_queue rxq[8];
13d64285
LB		 394
395 /*
396 * TX state.
397 */
398 int default_tx_ring_size;
399 unsigned long tx_desc_sram_addr;
400 int tx_desc_sram_size;
f7981c1c 401 int txq_count;
3d6b35bc 402 struct tx_queue txq[8];
fbd6a754 403};
1da177e4 404
fbd6a754 405
c9df406f 406/* port register accessors **************************************************/
e5371493 407static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
c9df406f 408{
cc9754b3 409 return readl(mp->shared->base + offset);
c9df406f 410}
fbd6a754 411
37a6084f
LB		 412static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset)
413{
414 return readl(mp->base + offset);
415}
416
e5371493 417static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
c9df406f 418{
cc9754b3 419 writel(data, mp->shared->base + offset);
c9df406f 420}
fbd6a754 421
37a6084f
LB		 422static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)
423{
424 writel(data, mp->base + offset);
425}
426
fbd6a754 427
c9df406f 428/* rxq/txq helper functions *************************************************/
8a578111 429static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
c9df406f 430{
64da80a2 431 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
c9df406f 432}
fbd6a754 433
13d64285
LB		 434static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
435{
3d6b35bc 436 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
13d64285
LB		 437}
438
8a578111 439static void rxq_enable(struct rx_queue *rxq)
c9df406f 440{
8a578111 441 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
37a6084f 442 wrlp(mp, RXQ_COMMAND, 1 << rxq->index);
8a578111 443}
1da177e4 444
8a578111
LB		 445static void rxq_disable(struct rx_queue *rxq)
446{
447 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
64da80a2 448 u8 mask = 1 << rxq->index;
1da177e4 449
37a6084f
LB		 450 wrlp(mp, RXQ_COMMAND, mask << 8);
451 while (rdlp(mp, RXQ_COMMAND) & mask)
8a578111 452 udelay(10);
c9df406f
LB		 453}
454
6b368f68
LB		 455static void txq_reset_hw_ptr(struct tx_queue *txq)
456{
457 struct mv643xx_eth_private *mp = txq_to_mp(txq);
6b368f68
LB		 458 u32 addr;
459
460 addr = (u32)txq->tx_desc_dma;
461 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
37a6084f 462 wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);
6b368f68
LB		 463}
464
13d64285 465static void txq_enable(struct tx_queue *txq)
1da177e4 466{
13d64285 467 struct mv643xx_eth_private *mp = txq_to_mp(txq);
37a6084f 468 wrlp(mp, TXQ_COMMAND, 1 << txq->index);
1da177e4
LT		 469}
470
13d64285 471static void txq_disable(struct tx_queue *txq)
1da177e4 472{
13d64285 473 struct mv643xx_eth_private *mp = txq_to_mp(txq);
3d6b35bc 474 u8 mask = 1 << txq->index;
c9df406f 475
37a6084f
LB		 476 wrlp(mp, TXQ_COMMAND, mask << 8);
477 while (rdlp(mp, TXQ_COMMAND) & mask)
13d64285
LB		 478 udelay(10);
479}
480
1fa38c58 481static void txq_maybe_wake(struct tx_queue *txq)
13d64285
LB		 482{
483 struct mv643xx_eth_private *mp = txq_to_mp(txq);
e5ef1de1 484 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
3d6b35bc 485
8fd89211
LB		 486 if (netif_tx_queue_stopped(nq)) {
487 __netif_tx_lock(nq, smp_processor_id());
488 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
489 netif_tx_wake_queue(nq);
490 __netif_tx_unlock(nq);
491 }
1da177e4
LT		 492}
493
c9df406f 494
1fa38c58 495/* rx napi ******************************************************************/
8a578111 496static int rxq_process(struct rx_queue *rxq, int budget)
1da177e4 497{
8a578111
LB		 498 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
499 struct net_device_stats *stats = &mp->dev->stats;
500 int rx;
1da177e4 501
8a578111 502 rx = 0;
9e1f3772 503 while (rx < budget && rxq->rx_desc_count) {
fc32b0e2 504 struct rx_desc *rx_desc;
96587661 505 unsigned int cmd_sts;
fc32b0e2 506 struct sk_buff *skb;
6b8f90c2 507 u16 byte_cnt;
ff561eef 508
8a578111 509 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
1da177e4 510
96587661 511 cmd_sts = rx_desc->cmd_sts;
2257e05c 512 if (cmd_sts & BUFFER_OWNED_BY_DMA)
96587661 513 break;
96587661 514 rmb();
1da177e4 515
8a578111
LB		 516 skb = rxq->rx_skb[rxq->rx_curr_desc];
517 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
ff561eef 518
9da78745
LB		 519 rxq->rx_curr_desc++;
520 if (rxq->rx_curr_desc == rxq->rx_ring_size)
521 rxq->rx_curr_desc = 0;
ff561eef 522
3a499481 523 dma_unmap_single(NULL, rx_desc->buf_ptr,
abe78717 524 rx_desc->buf_size, DMA_FROM_DEVICE);
8a578111
LB		 525 rxq->rx_desc_count--;
526 rx++;
b1dd9ca1 527
1fa38c58
LB		 528 mp->work_rx_refill |= 1 << rxq->index;
529
6b8f90c2
LB		 530 byte_cnt = rx_desc->byte_cnt;
531
468d09f8
DF		 532 /*
533 * Update statistics.
fc32b0e2
LB		 534 *
535 * Note that the descriptor byte count includes 2 dummy
536 * bytes automatically inserted by the hardware at the
537 * start of the packet (which we don't count), and a 4
538 * byte CRC at the end of the packet (which we do count).
468d09f8 539 */
1da177e4 540 stats->rx_packets++;
6b8f90c2 541 stats->rx_bytes += byte_cnt - 2;
96587661 542
1da177e4 543 /*
fc32b0e2
LB		 544 * In case we received a packet without first / last bits
545 * on, or the error summary bit is set, the packet needs
546 * to be dropped.
1da177e4 547 */
f61e5547
LB		 548 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY))
549 != (RX_FIRST_DESC | RX_LAST_DESC))
550 goto err;
551
552 /*
553 * The -4 is for the CRC in the trailer of the
554 * received packet
555 */
556 skb_put(skb, byte_cnt - 2 - 4);
557
558 if (cmd_sts & LAYER_4_CHECKSUM_OK)
559 skb->ip_summed = CHECKSUM_UNNECESSARY;
560 skb->protocol = eth_type_trans(skb, mp->dev);
561 netif_receive_skb(skb);
562
563 continue;
564
565err:
566 stats->rx_dropped++;
567
568 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
569 (RX_FIRST_DESC | RX_LAST_DESC)) {
570 if (net_ratelimit())
571 dev_printk(KERN_ERR, &mp->dev->dev,
572 "received packet spanning "
573 "multiple descriptors\n");
1da177e4 574 }
f61e5547
LB		 575
576 if (cmd_sts & ERROR_SUMMARY)
577 stats->rx_errors++;
578
579 dev_kfree_skb(skb);
1da177e4 580 }
fc32b0e2 581
1fa38c58
LB		 582 if (rx < budget)
583 mp->work_rx &= ~(1 << rxq->index);
584
8a578111 585 return rx;
1da177e4
LT		 586}
587
1fa38c58 588static int rxq_refill(struct rx_queue *rxq, int budget)
d0412d96 589{
1fa38c58 590 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1fa38c58 591 int refilled;
8a578111 592
1fa38c58
LB		 593 refilled = 0;
594 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
595 struct sk_buff *skb;
596 int unaligned;
597 int rx;
53771522 598 struct rx_desc *rx_desc;
d0412d96 599
2bcb4b0f
LB		 600 skb = __skb_dequeue(&mp->rx_recycle);
601 if (skb == NULL)
602 skb = dev_alloc_skb(mp->skb_size +
603 dma_get_cache_alignment() - 1);
604
1fa38c58
LB		 605 if (skb == NULL) {
606 mp->work_rx_oom |= 1 << rxq->index;
607 goto oom;
608 }
d0412d96 609
1fa38c58
LB		 610 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
611 if (unaligned)
612 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
2257e05c 613
1fa38c58
LB		 614 refilled++;
615 rxq->rx_desc_count++;
c9df406f 616
1fa38c58
LB		 617 rx = rxq->rx_used_desc++;
618 if (rxq->rx_used_desc == rxq->rx_ring_size)
619 rxq->rx_used_desc = 0;
2257e05c 620
53771522
LB		 621 rx_desc = rxq->rx_desc_area + rx;
622
623 rx_desc->buf_ptr = dma_map_single(NULL, skb->data,
624 mp->skb_size, DMA_FROM_DEVICE);
625 rx_desc->buf_size = mp->skb_size;
1fa38c58
LB		 626 rxq->rx_skb[rx] = skb;
627 wmb();
53771522 628 rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT;
1fa38c58 629 wmb();
2257e05c 630
1fa38c58
LB		 631 /*
632 * The hardware automatically prepends 2 bytes of
633 * dummy data to each received packet, so that the
634 * IP header ends up 16-byte aligned.
635 */
636 skb_reserve(skb, 2);
637 }
638
639 if (refilled < budget)
640 mp->work_rx_refill &= ~(1 << rxq->index);
641
642oom:
643 return refilled;
d0412d96
JC		 644}
645
c9df406f
LB		 646
647/* tx ***********************************************************************/
c9df406f 648static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1da177e4 649{
13d64285 650 int frag;
1da177e4 651
c9df406f 652 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
13d64285
LB		 653 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
654 if (fragp->size <= 8 && fragp->page_offset & 7)
c9df406f 655 return 1;
1da177e4 656 }
13d64285 657
c9df406f
LB		 658 return 0;
659}
7303fde8 660
13d64285 661static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
c9df406f 662{
13d64285 663 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 664 int frag;
1da177e4 665
13d64285
LB		 666 for (frag = 0; frag < nr_frags; frag++) {
667 skb_frag_t *this_frag;
668 int tx_index;
669 struct tx_desc *desc;
670
671 this_frag = &skb_shinfo(skb)->frags[frag];
66823b92
LB		 672 tx_index = txq->tx_curr_desc++;
673 if (txq->tx_curr_desc == txq->tx_ring_size)
674 txq->tx_curr_desc = 0;
13d64285
LB		 675 desc = &txq->tx_desc_area[tx_index];
676
677 /*
678 * The last fragment will generate an interrupt
679 * which will free the skb on TX completion.
680 */
681 if (frag == nr_frags - 1) {
682 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
683 ZERO_PADDING | TX_LAST_DESC |
684 TX_ENABLE_INTERRUPT;
13d64285
LB		 685 } else {
686 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
13d64285
LB		 687 }
688
c9df406f
LB		 689 desc->l4i_chk = 0;
690 desc->byte_cnt = this_frag->size;
691 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
692 this_frag->page_offset,
693 this_frag->size,
694 DMA_TO_DEVICE);
695 }
1da177e4
LT		 696}
697
c9df406f
LB		 698static inline __be16 sum16_as_be(__sum16 sum)
699{
700 return (__force __be16)sum;
701}
1da177e4 702
4df89bd5 703static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
1da177e4 704{
8fa89bf5 705 struct mv643xx_eth_private *mp = txq_to_mp(txq);
13d64285 706 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 707 int tx_index;
cc9754b3 708 struct tx_desc *desc;
c9df406f 709 u32 cmd_sts;
4df89bd5 710 u16 l4i_chk;
c9df406f 711 int length;
1da177e4 712
cc9754b3 713 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
4df89bd5 714 l4i_chk = 0;
c9df406f
LB		 715
716 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4df89bd5 717 int tag_bytes;
e32b6617
LB		 718
719 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
720 skb->protocol != htons(ETH_P_8021Q));
c9df406f 721
4df89bd5
LB		 722 tag_bytes = (void *)ip_hdr(skb) - (void *)skb->data - ETH_HLEN;
723 if (unlikely(tag_bytes & ~12)) {
724 if (skb_checksum_help(skb) == 0)
725 goto no_csum;
726 kfree_skb(skb);
727 return 1;
728 }
c9df406f 729
4df89bd5 730 if (tag_bytes & 4)
e32b6617 731 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
4df89bd5 732 if (tag_bytes & 8)
e32b6617 733 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
4df89bd5
LB		 734
735 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
736 GEN_IP_V4_CHECKSUM |
737 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
e32b6617 738
c9df406f
LB		 739 switch (ip_hdr(skb)->protocol) {
740 case IPPROTO_UDP:
cc9754b3 741 cmd_sts |= UDP_FRAME;
4df89bd5 742 l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
c9df406f
LB		 743 break;
744 case IPPROTO_TCP:
4df89bd5 745 l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
c9df406f
LB		 746 break;
747 default:
748 BUG();
749 }
750 } else {
4df89bd5 751no_csum:
c9df406f 752 /* Errata BTS #50, IHL must be 5 if no HW checksum */
cc9754b3 753 cmd_sts |= 5 << TX_IHL_SHIFT;
c9df406f
LB		 754 }
755
66823b92
LB		 756 tx_index = txq->tx_curr_desc++;
757 if (txq->tx_curr_desc == txq->tx_ring_size)
758 txq->tx_curr_desc = 0;
4df89bd5
LB		 759 desc = &txq->tx_desc_area[tx_index];
760
761 if (nr_frags) {
762 txq_submit_frag_skb(txq, skb);
763 length = skb_headlen(skb);
764 } else {
765 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
766 length = skb->len;
767 }
768
769 desc->l4i_chk = l4i_chk;
770 desc->byte_cnt = length;
771 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
772
99ab08e0
LB		 773 __skb_queue_tail(&txq->tx_skb, skb);
774
c9df406f
LB		 775 /* ensure all other descriptors are written before first cmd_sts */
776 wmb();
777 desc->cmd_sts = cmd_sts;
778
1fa38c58
LB		 779 /* clear TX_END status */
780 mp->work_tx_end &= ~(1 << txq->index);
8fa89bf5 781
c9df406f
LB		 782 /* ensure all descriptors are written before poking hardware */
783 wmb();
13d64285 784 txq_enable(txq);
c9df406f 785
13d64285 786 txq->tx_desc_count += nr_frags + 1;
4df89bd5
LB		 787
788 return 0;
1da177e4 789}
1da177e4 790
fc32b0e2 791static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 792{
e5371493 793 struct mv643xx_eth_private *mp = netdev_priv(dev);
e5ef1de1 794 int queue;
13d64285 795 struct tx_queue *txq;
e5ef1de1 796 struct netdev_queue *nq;
afdb57a2 797
8fd89211
LB		 798 queue = skb_get_queue_mapping(skb);
799 txq = mp->txq + queue;
800 nq = netdev_get_tx_queue(dev, queue);
801
c9df406f 802 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
8fd89211 803 txq->tx_dropped++;
fc32b0e2
LB		 804 dev_printk(KERN_DEBUG, &dev->dev,
805 "failed to linearize skb with tiny "
806 "unaligned fragment\n");
c9df406f
LB		 807 return NETDEV_TX_BUSY;
808 }
809
17cd0a59 810 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
e5ef1de1
LB		 811 if (net_ratelimit())
812 dev_printk(KERN_ERR, &dev->dev, "tx queue full?!\n");
3d6b35bc
LB		 813 kfree_skb(skb);
814 return NETDEV_TX_OK;
c9df406f
LB		 815 }
816
4df89bd5
LB		 817 if (!txq_submit_skb(txq, skb)) {
818 int entries_left;
819
820 txq->tx_bytes += skb->len;
821 txq->tx_packets++;
822 dev->trans_start = jiffies;
c9df406f 823
4df89bd5
LB		 824 entries_left = txq->tx_ring_size - txq->tx_desc_count;
825 if (entries_left < MAX_SKB_FRAGS + 1)
826 netif_tx_stop_queue(nq);
827 }
c9df406f 828
c9df406f 829 return NETDEV_TX_OK;
1da177e4
LT		 830}
831
c9df406f 832
1fa38c58
LB		 833/* tx napi ******************************************************************/
834static void txq_kick(struct tx_queue *txq)
835{
836 struct mv643xx_eth_private *mp = txq_to_mp(txq);
8fd89211 837 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1fa38c58
LB		 838 u32 hw_desc_ptr;
839 u32 expected_ptr;
840
8fd89211 841 __netif_tx_lock(nq, smp_processor_id());
1fa38c58 842
37a6084f 843 if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
1fa38c58
LB		 844 goto out;
845
37a6084f 846 hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
1fa38c58
LB		 847 expected_ptr = (u32)txq->tx_desc_dma +
848 txq->tx_curr_desc * sizeof(struct tx_desc);
849
850 if (hw_desc_ptr != expected_ptr)
851 txq_enable(txq);
852
853out:
8fd89211 854 __netif_tx_unlock(nq);
1fa38c58
LB		 855
856 mp->work_tx_end &= ~(1 << txq->index);
857}
858
859static int txq_reclaim(struct tx_queue *txq, int budget, int force)
860{
861 struct mv643xx_eth_private *mp = txq_to_mp(txq);
8fd89211 862 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1fa38c58
LB		 863 int reclaimed;
864
8fd89211 865 __netif_tx_lock(nq, smp_processor_id());
1fa38c58
LB		 866
867 reclaimed = 0;
868 while (reclaimed < budget && txq->tx_desc_count > 0) {
869 int tx_index;
870 struct tx_desc *desc;
871 u32 cmd_sts;
872 struct sk_buff *skb;
1fa38c58
LB		 873
874 tx_index = txq->tx_used_desc;
875 desc = &txq->tx_desc_area[tx_index];
876 cmd_sts = desc->cmd_sts;
877
878 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
879 if (!force)
880 break;
881 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
882 }
883
884 txq->tx_used_desc = tx_index + 1;
885 if (txq->tx_used_desc == txq->tx_ring_size)
886 txq->tx_used_desc = 0;
887
888 reclaimed++;
889 txq->tx_desc_count--;
890
99ab08e0
LB		 891 skb = NULL;
892 if (cmd_sts & TX_LAST_DESC)
893 skb = __skb_dequeue(&txq->tx_skb);
1fa38c58
LB		 894
895 if (cmd_sts & ERROR_SUMMARY) {
896 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
897 mp->dev->stats.tx_errors++;
898 }
899
a418950c
LB		 900 if (cmd_sts & TX_FIRST_DESC) {
901 dma_unmap_single(NULL, desc->buf_ptr,
902 desc->byte_cnt, DMA_TO_DEVICE);
903 } else {
904 dma_unmap_page(NULL, desc->buf_ptr,
905 desc->byte_cnt, DMA_TO_DEVICE);
906 }
1fa38c58 907
2bcb4b0f
LB		 908 if (skb != NULL) {
909 if (skb_queue_len(&mp->rx_recycle) <
910 mp->default_rx_ring_size &&
11b4aa03
LB		 911 skb_recycle_check(skb, mp->skb_size +
912 dma_get_cache_alignment() - 1))
2bcb4b0f
LB		 913 __skb_queue_head(&mp->rx_recycle, skb);
914 else
915 dev_kfree_skb(skb);
916 }
1fa38c58
LB		 917 }
918
8fd89211
LB		 919 __netif_tx_unlock(nq);
920
1fa38c58
LB		 921 if (reclaimed < budget)
922 mp->work_tx &= ~(1 << txq->index);
923
1fa38c58
LB		 924 return reclaimed;
925}
926
927
89df5fdc
LB		 928/* tx rate control **********************************************************/
929/*
930 * Set total maximum TX rate (shared by all TX queues for this port)
931 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
932 */
933static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
934{
935 int token_rate;
936 int mtu;
937 int bucket_size;
938
939 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
940 if (token_rate > 1023)
941 token_rate = 1023;
942
943 mtu = (mp->dev->mtu + 255) >> 8;
944 if (mtu > 63)
945 mtu = 63;
946
947 bucket_size = (burst + 255) >> 8;
948 if (bucket_size > 65535)
949 bucket_size = 65535;
950
457b1d5a
LB		 951 switch (mp->shared->tx_bw_control) {
952 case TX_BW_CONTROL_OLD_LAYOUT:
37a6084f
LB		 953 wrlp(mp, TX_BW_RATE, token_rate);
954 wrlp(mp, TX_BW_MTU, mtu);
955 wrlp(mp, TX_BW_BURST, bucket_size);
457b1d5a
LB		 956 break;
957 case TX_BW_CONTROL_NEW_LAYOUT:
37a6084f
LB		 958 wrlp(mp, TX_BW_RATE_MOVED, token_rate);
959 wrlp(mp, TX_BW_MTU_MOVED, mtu);
960 wrlp(mp, TX_BW_BURST_MOVED, bucket_size);
457b1d5a 961 break;
1e881592 962 }
89df5fdc
LB		 963}
964
965static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
966{
967 struct mv643xx_eth_private *mp = txq_to_mp(txq);
968 int token_rate;
969 int bucket_size;
970
971 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
972 if (token_rate > 1023)
973 token_rate = 1023;
974
975 bucket_size = (burst + 255) >> 8;
976 if (bucket_size > 65535)
977 bucket_size = 65535;
978
37a6084f
LB		 979 wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);
980 wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);
89df5fdc
LB		 981}
982
983static void txq_set_fixed_prio_mode(struct tx_queue *txq)
984{
985 struct mv643xx_eth_private *mp = txq_to_mp(txq);
986 int off;
987 u32 val;
988
989 /*
990 * Turn on fixed priority mode.
991 */
457b1d5a
LB		 992 off = 0;
993 switch (mp->shared->tx_bw_control) {
994 case TX_BW_CONTROL_OLD_LAYOUT:
37a6084f 995 off = TXQ_FIX_PRIO_CONF;
457b1d5a
LB		 996 break;
997 case TX_BW_CONTROL_NEW_LAYOUT:
37a6084f 998 off = TXQ_FIX_PRIO_CONF_MOVED;
457b1d5a
LB		 999 break;
1000 }
89df5fdc 1001
457b1d5a 1002 if (off) {
37a6084f 1003 val = rdlp(mp, off);
457b1d5a 1004 val |= 1 << txq->index;
37a6084f 1005 wrlp(mp, off, val);
457b1d5a 1006 }
89df5fdc
LB		 1007}
1008
1009static void txq_set_wrr(struct tx_queue *txq, int weight)
1010{
1011 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1012 int off;
1013 u32 val;
1014
1015 /*
1016 * Turn off fixed priority mode.
1017 */
457b1d5a
LB		 1018 off = 0;
1019 switch (mp->shared->tx_bw_control) {
1020 case TX_BW_CONTROL_OLD_LAYOUT:
37a6084f 1021 off = TXQ_FIX_PRIO_CONF;
457b1d5a
LB		 1022 break;
1023 case TX_BW_CONTROL_NEW_LAYOUT:
37a6084f 1024 off = TXQ_FIX_PRIO_CONF_MOVED;
457b1d5a
LB		 1025 break;
1026 }
89df5fdc 1027
457b1d5a 1028 if (off) {
37a6084f 1029 val = rdlp(mp, off);
457b1d5a 1030 val &= ~(1 << txq->index);
37a6084f 1031 wrlp(mp, off, val);
89df5fdc 1032
457b1d5a
LB		 1033 /*
1034 * Configure WRR weight for this queue.
1035 */
89df5fdc 1036
37a6084f 1037 val = rdlp(mp, off);
457b1d5a 1038 val = (val & ~0xff) | (weight & 0xff);
37a6084f 1039 wrlp(mp, TXQ_BW_WRR_CONF(txq->index), val);
457b1d5a 1040 }
89df5fdc
LB		 1041}
1042
1043
c9df406f 1044/* mii management interface *************************************************/
45c5d3bc
LB		 1045static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id)
1046{
1047 struct mv643xx_eth_shared_private *msp = dev_id;
1048
1049 if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) {
1050 writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE);
1051 wake_up(&msp->smi_busy_wait);
1052 return IRQ_HANDLED;
1053 }
1054
1055 return IRQ_NONE;
1056}
c9df406f 1057
45c5d3bc 1058static int smi_is_done(struct mv643xx_eth_shared_private *msp)
1da177e4 1059{
45c5d3bc
LB		 1060 return !(readl(msp->base + SMI_REG) & SMI_BUSY);
1061}
1da177e4 1062
45c5d3bc
LB		 1063static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
1064{
1065 if (msp->err_interrupt == NO_IRQ) {
1066 int i;
c9df406f 1067
45c5d3bc
LB		 1068 for (i = 0; !smi_is_done(msp); i++) {
1069 if (i == 10)
1070 return -ETIMEDOUT;
1071 msleep(10);
c9df406f 1072 }
45c5d3bc
LB		 1073
1074 return 0;
1075 }
1076
ee04448d
LB		 1077 if (!smi_is_done(msp)) {
1078 wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
1079 msecs_to_jiffies(100));
1080 if (!smi_is_done(msp))
1081 return -ETIMEDOUT;
1082 }
45c5d3bc
LB		 1083
1084 return 0;
1085}
1086
ed94493f 1087static int smi_bus_read(struct mii_bus *bus, int addr, int reg)
45c5d3bc 1088{
ed94493f 1089 struct mv643xx_eth_shared_private *msp = bus->priv;
45c5d3bc
LB		 1090 void __iomem *smi_reg = msp->base + SMI_REG;
1091 int ret;
1092
45c5d3bc 1093 if (smi_wait_ready(msp)) {
10a9948d 1094 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
ed94493f 1095 return -ETIMEDOUT;
1da177e4
LT		 1096 }
1097
fc32b0e2 1098 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1da177e4 1099
45c5d3bc 1100 if (smi_wait_ready(msp)) {
10a9948d 1101 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
ed94493f 1102 return -ETIMEDOUT;
45c5d3bc
LB		 1103 }
1104
1105 ret = readl(smi_reg);
1106 if (!(ret & SMI_READ_VALID)) {
10a9948d 1107 printk(KERN_WARNING "mv643xx_eth: SMI bus read not valid\n");
ed94493f 1108 return -ENODEV;
c9df406f
LB		 1109 }
1110
ed94493f 1111 return ret & 0xffff;
1da177e4
LT		 1112}
1113
ed94493f 1114static int smi_bus_write(struct mii_bus *bus, int addr, int reg, u16 val)
1da177e4 1115{
ed94493f 1116 struct mv643xx_eth_shared_private *msp = bus->priv;
45c5d3bc 1117 void __iomem *smi_reg = msp->base + SMI_REG;
1da177e4 1118
45c5d3bc 1119 if (smi_wait_ready(msp)) {
10a9948d 1120 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
45c5d3bc 1121 return -ETIMEDOUT;
1da177e4
LT		 1122 }
1123
fc32b0e2 1124 writel(SMI_OPCODE_WRITE | (reg << 21) |
ed94493f 1125 (addr << 16) | (val & 0xffff), smi_reg);
45c5d3bc 1126
ed94493f 1127 if (smi_wait_ready(msp)) {
10a9948d 1128 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
ed94493f
LB		 1129 return -ETIMEDOUT;
1130 }
45c5d3bc
LB		 1131
1132 return 0;
c9df406f 1133}
1da177e4 1134
c9df406f 1135
8fd89211
LB		 1136/* statistics ***************************************************************/
1137static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1138{
1139 struct mv643xx_eth_private *mp = netdev_priv(dev);
1140 struct net_device_stats *stats = &dev->stats;
1141 unsigned long tx_packets = 0;
1142 unsigned long tx_bytes = 0;
1143 unsigned long tx_dropped = 0;
1144 int i;
1145
1146 for (i = 0; i < mp->txq_count; i++) {
1147 struct tx_queue *txq = mp->txq + i;
1148
1149 tx_packets += txq->tx_packets;
1150 tx_bytes += txq->tx_bytes;
1151 tx_dropped += txq->tx_dropped;
1152 }
1153
1154 stats->tx_packets = tx_packets;
1155 stats->tx_bytes = tx_bytes;
1156 stats->tx_dropped = tx_dropped;
1157
1158 return stats;
1159}
1160
fc32b0e2 1161static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
c9df406f 1162{
fc32b0e2 1163 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1da177e4
LT		 1164}
1165
fc32b0e2 1166static void mib_counters_clear(struct mv643xx_eth_private *mp)
d0412d96 1167{
fc32b0e2
LB		 1168 int i;
1169
1170 for (i = 0; i < 0x80; i += 4)
1171 mib_read(mp, i);
c9df406f 1172}
d0412d96 1173
fc32b0e2 1174static void mib_counters_update(struct mv643xx_eth_private *mp)
c9df406f 1175{
e5371493 1176 struct mib_counters *p = &mp->mib_counters;
4b8e3655 1177
4ff3495a 1178 spin_lock(&mp->mib_counters_lock);
fc32b0e2
LB		 1179 p->good_octets_received += mib_read(mp, 0x00);
1180 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
1181 p->bad_octets_received += mib_read(mp, 0x08);
1182 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1183 p->good_frames_received += mib_read(mp, 0x10);
1184 p->bad_frames_received += mib_read(mp, 0x14);
1185 p->broadcast_frames_received += mib_read(mp, 0x18);
1186 p->multicast_frames_received += mib_read(mp, 0x1c);
1187 p->frames_64_octets += mib_read(mp, 0x20);
1188 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1189 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1190 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1191 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1192 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1193 p->good_octets_sent += mib_read(mp, 0x38);
1194 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1195 p->good_frames_sent += mib_read(mp, 0x40);
1196 p->excessive_collision += mib_read(mp, 0x44);
1197 p->multicast_frames_sent += mib_read(mp, 0x48);
1198 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1199 p->unrec_mac_control_received += mib_read(mp, 0x50);
1200 p->fc_sent += mib_read(mp, 0x54);
1201 p->good_fc_received += mib_read(mp, 0x58);
1202 p->bad_fc_received += mib_read(mp, 0x5c);
1203 p->undersize_received += mib_read(mp, 0x60);
1204 p->fragments_received += mib_read(mp, 0x64);
1205 p->oversize_received += mib_read(mp, 0x68);
1206 p->jabber_received += mib_read(mp, 0x6c);
1207 p->mac_receive_error += mib_read(mp, 0x70);
1208 p->bad_crc_event += mib_read(mp, 0x74);
1209 p->collision += mib_read(mp, 0x78);
1210 p->late_collision += mib_read(mp, 0x7c);
4ff3495a
LB		 1211 spin_unlock(&mp->mib_counters_lock);
1212
1213 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1214}
1215
1216static void mib_counters_timer_wrapper(unsigned long _mp)
1217{
1218 struct mv643xx_eth_private *mp = (void *)_mp;
1219
1220 mib_counters_update(mp);
d0412d96
JC		 1221}
1222
c9df406f
LB		 1223
1224/* ethtool ******************************************************************/
e5371493 1225struct mv643xx_eth_stats {
c9df406f
LB		 1226 char stat_string[ETH_GSTRING_LEN];
1227 int sizeof_stat;
16820054
LB		 1228 int netdev_off;
1229 int mp_off;
c9df406f
LB		 1230};
1231
16820054
LB		 1232#define SSTAT(m) \
1233 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1234 offsetof(struct net_device, stats.m), -1 }
1235
1236#define MIBSTAT(m) \
1237 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1238 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1239
1240static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1241 SSTAT(rx_packets),
1242 SSTAT(tx_packets),
1243 SSTAT(rx_bytes),
1244 SSTAT(tx_bytes),
1245 SSTAT(rx_errors),
1246 SSTAT(tx_errors),
1247 SSTAT(rx_dropped),
1248 SSTAT(tx_dropped),
1249 MIBSTAT(good_octets_received),
1250 MIBSTAT(bad_octets_received),
1251 MIBSTAT(internal_mac_transmit_err),
1252 MIBSTAT(good_frames_received),
1253 MIBSTAT(bad_frames_received),
1254 MIBSTAT(broadcast_frames_received),
1255 MIBSTAT(multicast_frames_received),
1256 MIBSTAT(frames_64_octets),
1257 MIBSTAT(frames_65_to_127_octets),
1258 MIBSTAT(frames_128_to_255_octets),
1259 MIBSTAT(frames_256_to_511_octets),
1260 MIBSTAT(frames_512_to_1023_octets),
1261 MIBSTAT(frames_1024_to_max_octets),
1262 MIBSTAT(good_octets_sent),
1263 MIBSTAT(good_frames_sent),
1264 MIBSTAT(excessive_collision),
1265 MIBSTAT(multicast_frames_sent),
1266 MIBSTAT(broadcast_frames_sent),
1267 MIBSTAT(unrec_mac_control_received),
1268 MIBSTAT(fc_sent),
1269 MIBSTAT(good_fc_received),
1270 MIBSTAT(bad_fc_received),
1271 MIBSTAT(undersize_received),
1272 MIBSTAT(fragments_received),
1273 MIBSTAT(oversize_received),
1274 MIBSTAT(jabber_received),
1275 MIBSTAT(mac_receive_error),
1276 MIBSTAT(bad_crc_event),
1277 MIBSTAT(collision),
1278 MIBSTAT(late_collision),
c9df406f
LB		 1279};
1280
10a9948d
LB		 1281static int
1282mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
d0412d96 1283{
e5371493 1284 struct mv643xx_eth_private *mp = netdev_priv(dev);
d0412d96
JC		 1285 int err;
1286
ed94493f
LB		 1287 err = phy_read_status(mp->phy);
1288 if (err == 0)
1289 err = phy_ethtool_gset(mp->phy, cmd);
d0412d96 1290
fc32b0e2
LB		 1291 /*
1292 * The MAC does not support 1000baseT_Half.
1293 */
d0412d96
JC		 1294 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1295 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1296
1297 return err;
1298}
1299
10a9948d
LB		 1300static int
1301mv643xx_eth_get_settings_phyless(struct net_device *dev,
1302 struct ethtool_cmd *cmd)
bedfe324 1303{
81600eea
LB		 1304 struct mv643xx_eth_private *mp = netdev_priv(dev);
1305 u32 port_status;
1306
37a6084f 1307 port_status = rdlp(mp, PORT_STATUS);
81600eea 1308
bedfe324
LB		 1309 cmd->supported = SUPPORTED_MII;
1310 cmd->advertising = ADVERTISED_MII;
81600eea
LB		 1311 switch (port_status & PORT_SPEED_MASK) {
1312 case PORT_SPEED_10:
1313 cmd->speed = SPEED_10;
1314 break;
1315 case PORT_SPEED_100:
1316 cmd->speed = SPEED_100;
1317 break;
1318 case PORT_SPEED_1000:
1319 cmd->speed = SPEED_1000;
1320 break;
1321 default:
1322 cmd->speed = -1;
1323 break;
1324 }
1325 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
bedfe324
LB		 1326 cmd->port = PORT_MII;
1327 cmd->phy_address = 0;
1328 cmd->transceiver = XCVR_INTERNAL;
1329 cmd->autoneg = AUTONEG_DISABLE;
1330 cmd->maxtxpkt = 1;
1331 cmd->maxrxpkt = 1;
1332
1333 return 0;
1334}
1335
10a9948d
LB		 1336static int
1337mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4 1338{
e5371493 1339 struct mv643xx_eth_private *mp = netdev_priv(dev);
ab4384a6 1340
fc32b0e2
LB		 1341 /*
1342 * The MAC does not support 1000baseT_Half.
1343 */
1344 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1345
ed94493f 1346 return phy_ethtool_sset(mp->phy, cmd);
c9df406f 1347}
1da177e4 1348
10a9948d
LB		 1349static int
1350mv643xx_eth_set_settings_phyless(struct net_device *dev,
1351 struct ethtool_cmd *cmd)
bedfe324
LB		 1352{
1353 return -EINVAL;
1354}
1355
fc32b0e2
LB		 1356static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1357 struct ethtool_drvinfo *drvinfo)
c9df406f 1358{
e5371493
LB		 1359 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1360 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
c9df406f 1361 strncpy(drvinfo->fw_version, "N/A", 32);
fc32b0e2 1362 strncpy(drvinfo->bus_info, "platform", 32);
16820054 1363 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
c9df406f 1364}
1da177e4 1365
fc32b0e2 1366static int mv643xx_eth_nway_reset(struct net_device *dev)
c9df406f 1367{
e5371493 1368 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1369
ed94493f 1370 return genphy_restart_aneg(mp->phy);
c9df406f 1371}
1da177e4 1372
bedfe324
LB		 1373static int mv643xx_eth_nway_reset_phyless(struct net_device *dev)
1374{
1375 return -EINVAL;
1376}
1377
c9df406f
LB		 1378static u32 mv643xx_eth_get_link(struct net_device *dev)
1379{
ed94493f 1380 return !!netif_carrier_ok(dev);
bedfe324
LB		 1381}
1382
fc32b0e2
LB		 1383static void mv643xx_eth_get_strings(struct net_device *dev,
1384 uint32_t stringset, uint8_t *data)
c9df406f
LB		 1385{
1386 int i;
1da177e4 1387
fc32b0e2
LB		 1388 if (stringset == ETH_SS_STATS) {
1389 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
c9df406f 1390 memcpy(data + i * ETH_GSTRING_LEN,
16820054 1391 mv643xx_eth_stats[i].stat_string,
e5371493 1392 ETH_GSTRING_LEN);
c9df406f 1393 }
c9df406f
LB		 1394 }
1395}
1da177e4 1396
fc32b0e2
LB		 1397static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1398 struct ethtool_stats *stats,
1399 uint64_t *data)
c9df406f 1400{
b9873841 1401 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 1402 int i;
1da177e4 1403
8fd89211 1404 mv643xx_eth_get_stats(dev);
fc32b0e2 1405 mib_counters_update(mp);
1da177e4 1406
16820054
LB		 1407 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1408 const struct mv643xx_eth_stats *stat;
1409 void *p;
1410
1411 stat = mv643xx_eth_stats + i;
1412
1413 if (stat->netdev_off >= 0)
1414 p = ((void *)mp->dev) + stat->netdev_off;
1415 else
1416 p = ((void *)mp) + stat->mp_off;
1417
1418 data[i] = (stat->sizeof_stat == 8) ?
1419 *(uint64_t *)p : *(uint32_t *)p;
1da177e4 1420 }
c9df406f 1421}
1da177e4 1422
fc32b0e2 1423static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
c9df406f 1424{
fc32b0e2 1425 if (sset == ETH_SS_STATS)
16820054 1426 return ARRAY_SIZE(mv643xx_eth_stats);
fc32b0e2
LB		 1427
1428 return -EOPNOTSUPP;
c9df406f 1429}
1da177e4 1430
e5371493 1431static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
fc32b0e2
LB		 1432 .get_settings = mv643xx_eth_get_settings,
1433 .set_settings = mv643xx_eth_set_settings,
1434 .get_drvinfo = mv643xx_eth_get_drvinfo,
1435 .nway_reset = mv643xx_eth_nway_reset,
1436 .get_link = mv643xx_eth_get_link,
c9df406f 1437 .set_sg = ethtool_op_set_sg,
fc32b0e2
LB		 1438 .get_strings = mv643xx_eth_get_strings,
1439 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
e5371493 1440 .get_sset_count = mv643xx_eth_get_sset_count,
c9df406f 1441};
1da177e4 1442
bedfe324
LB		 1443static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless = {
1444 .get_settings = mv643xx_eth_get_settings_phyless,
1445 .set_settings = mv643xx_eth_set_settings_phyless,
1446 .get_drvinfo = mv643xx_eth_get_drvinfo,
1447 .nway_reset = mv643xx_eth_nway_reset_phyless,
ed94493f 1448 .get_link = mv643xx_eth_get_link,
bedfe324
LB		 1449 .set_sg = ethtool_op_set_sg,
1450 .get_strings = mv643xx_eth_get_strings,
1451 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1452 .get_sset_count = mv643xx_eth_get_sset_count,
1453};
1454
bea3348e 1455
c9df406f 1456/* address handling *********************************************************/
5daffe94 1457static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
c9df406f 1458{
66e63ffb
LB		 1459 unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH);
1460 unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW);
1da177e4 1461
5daffe94
LB		 1462 addr[0] = (mac_h >> 24) & 0xff;
1463 addr[1] = (mac_h >> 16) & 0xff;
1464 addr[2] = (mac_h >> 8) & 0xff;
1465 addr[3] = mac_h & 0xff;
1466 addr[4] = (mac_l >> 8) & 0xff;
1467 addr[5] = mac_l & 0xff;
c9df406f 1468}
1da177e4 1469
66e63ffb 1470static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
c9df406f 1471{
66e63ffb
LB		 1472 wrlp(mp, MAC_ADDR_HIGH,
1473 (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]);
1474 wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]);
c9df406f 1475}
d0412d96 1476
66e63ffb 1477static u32 uc_addr_filter_mask(struct net_device *dev)
c9df406f 1478{
66e63ffb
LB		 1479 struct dev_addr_list *uc_ptr;
1480 u32 nibbles;
1da177e4 1481
66e63ffb
LB		 1482 if (dev->flags & IFF_PROMISC)
1483 return 0;
1da177e4 1484
66e63ffb
LB		 1485 nibbles = 1 << (dev->dev_addr[5] & 0x0f);
1486 for (uc_ptr = dev->uc_list; uc_ptr != NULL; uc_ptr = uc_ptr->next) {
1487 if (memcmp(dev->dev_addr, uc_ptr->da_addr, 5))
1488 return 0;
1489 if ((dev->dev_addr[5] ^ uc_ptr->da_addr[5]) & 0xf0)
1490 return 0;
ff561eef 1491
66e63ffb
LB		 1492 nibbles |= 1 << (uc_ptr->da_addr[5] & 0x0f);
1493 }
1da177e4 1494
66e63ffb 1495 return nibbles;
1da177e4
LT		 1496}
1497
66e63ffb 1498static void mv643xx_eth_program_unicast_filter(struct net_device *dev)
1da177e4 1499{
e5371493 1500 struct mv643xx_eth_private *mp = netdev_priv(dev);
66e63ffb
LB		 1501 u32 port_config;
1502 u32 nibbles;
1503 int i;
1da177e4 1504
cc9754b3 1505 uc_addr_set(mp, dev->dev_addr);
1da177e4 1506
66e63ffb
LB		 1507 port_config = rdlp(mp, PORT_CONFIG);
1508 nibbles = uc_addr_filter_mask(dev);
1509 if (!nibbles) {
1510 port_config |= UNICAST_PROMISCUOUS_MODE;
1511 wrlp(mp, PORT_CONFIG, port_config);
1512 return;
1513 }
1514
1515 for (i = 0; i < 16; i += 4) {
1516 int off = UNICAST_TABLE(mp->port_num) + i;
1517 u32 v;
1518
1519 v = 0;
1520 if (nibbles & 1)
1521 v |= 0x00000001;
1522 if (nibbles & 2)
1523 v |= 0x00000100;
1524 if (nibbles & 4)
1525 v |= 0x00010000;
1526 if (nibbles & 8)
1527 v |= 0x01000000;
1528 nibbles >>= 4;
1529
1530 wrl(mp, off, v);
1531 }
1532
1533 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1534 wrlp(mp, PORT_CONFIG, port_config);
1da177e4
LT		 1535}
1536
69876569
LB		 1537static int addr_crc(unsigned char *addr)
1538{
1539 int crc = 0;
1540 int i;
1541
1542 for (i = 0; i < 6; i++) {
1543 int j;
1544
1545 crc = (crc ^ addr[i]) << 8;
1546 for (j = 7; j >= 0; j--) {
1547 if (crc & (0x100 << j))
1548 crc ^= 0x107 << j;
1549 }
1550 }
1551
1552 return crc;
1553}
1554
66e63ffb 1555static void mv643xx_eth_program_multicast_filter(struct net_device *dev)
1da177e4 1556{
fc32b0e2 1557 struct mv643xx_eth_private *mp = netdev_priv(dev);
66e63ffb
LB		 1558 u32 *mc_spec;
1559 u32 *mc_other;
fc32b0e2
LB		 1560 struct dev_addr_list *addr;
1561 int i;
c8aaea25 1562
fc32b0e2 1563 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
66e63ffb
LB		 1564 int port_num;
1565 u32 accept;
1566 int i;
c8aaea25 1567
66e63ffb
LB		 1568oom:
1569 port_num = mp->port_num;
1570 accept = 0x01010101;
fc32b0e2
LB		 1571 for (i = 0; i < 0x100; i += 4) {
1572 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1573 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
c9df406f
LB		 1574 }
1575 return;
1576 }
c8aaea25 1577
66e63ffb
LB		 1578 mc_spec = kmalloc(0x200, GFP_KERNEL);
1579 if (mc_spec == NULL)
1580 goto oom;
1581 mc_other = mc_spec + (0x100 >> 2);
1582
1583 memset(mc_spec, 0, 0x100);
1584 memset(mc_other, 0, 0x100);
1da177e4 1585
fc32b0e2
LB		 1586 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1587 u8 *a = addr->da_addr;
66e63ffb
LB		 1588 u32 *table;
1589 int entry;
1da177e4 1590
fc32b0e2 1591 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
66e63ffb
LB		 1592 table = mc_spec;
1593 entry = a[5];
fc32b0e2 1594 } else {
66e63ffb
LB		 1595 table = mc_other;
1596 entry = addr_crc(a);
fc32b0e2 1597 }
66e63ffb
LB		 1598
1599 table[entry >> 2] |= 1 << (entry & 3);
fc32b0e2 1600 }
66e63ffb
LB		 1601
1602 for (i = 0; i < 0x100; i += 4) {
1603 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, mc_spec[i >> 2]);
1604 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, mc_other[i >> 2]);
1605 }
1606
1607 kfree(mc_spec);
1608}
1609
1610static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1611{
1612 mv643xx_eth_program_unicast_filter(dev);
1613 mv643xx_eth_program_multicast_filter(dev);
1614}
1615
1616static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1617{
1618 struct sockaddr *sa = addr;
1619
1620 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
1621
1622 netif_addr_lock_bh(dev);
1623 mv643xx_eth_program_unicast_filter(dev);
1624 netif_addr_unlock_bh(dev);
1625
1626 return 0;
c9df406f 1627}
c8aaea25 1628
c8aaea25 1629
c9df406f 1630/* rx/tx queue initialisation ***********************************************/
64da80a2 1631static int rxq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1632{
64da80a2 1633 struct rx_queue *rxq = mp->rxq + index;
8a578111
LB		 1634 struct rx_desc *rx_desc;
1635 int size;
c9df406f
LB		 1636 int i;
1637
64da80a2
LB		 1638 rxq->index = index;
1639
8a578111
LB		 1640 rxq->rx_ring_size = mp->default_rx_ring_size;
1641
1642 rxq->rx_desc_count = 0;
1643 rxq->rx_curr_desc = 0;
1644 rxq->rx_used_desc = 0;
1645
1646 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1647
f7981c1c 1648 if (index == 0 && size <= mp->rx_desc_sram_size) {
8a578111
LB		 1649 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1650 mp->rx_desc_sram_size);
1651 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1652 } else {
1653 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1654 &rxq->rx_desc_dma,
1655 GFP_KERNEL);
f7ea3337
PJ		 1656 }
1657
8a578111
LB		 1658 if (rxq->rx_desc_area == NULL) {
1659 dev_printk(KERN_ERR, &mp->dev->dev,
1660 "can't allocate rx ring (%d bytes)\n", size);
1661 goto out;
1662 }
1663 memset(rxq->rx_desc_area, 0, size);
1da177e4 1664
8a578111
LB		 1665 rxq->rx_desc_area_size = size;
1666 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1667 GFP_KERNEL);
1668 if (rxq->rx_skb == NULL) {
1669 dev_printk(KERN_ERR, &mp->dev->dev,
1670 "can't allocate rx skb ring\n");
1671 goto out_free;
1672 }
1673
1674 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1675 for (i = 0; i < rxq->rx_ring_size; i++) {
9da78745
LB		 1676 int nexti;
1677
1678 nexti = i + 1;
1679 if (nexti == rxq->rx_ring_size)
1680 nexti = 0;
1681
8a578111
LB		 1682 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1683 nexti * sizeof(struct rx_desc);
1684 }
1685
8a578111
LB		 1686 return 0;
1687
1688
1689out_free:
f7981c1c 1690 if (index == 0 && size <= mp->rx_desc_sram_size)
8a578111
LB		 1691 iounmap(rxq->rx_desc_area);
1692 else
1693 dma_free_coherent(NULL, size,
1694 rxq->rx_desc_area,
1695 rxq->rx_desc_dma);
1696
1697out:
1698 return -ENOMEM;
c9df406f 1699}
c8aaea25 1700
8a578111 1701static void rxq_deinit(struct rx_queue *rxq)
c9df406f 1702{
8a578111
LB		 1703 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1704 int i;
1705
1706 rxq_disable(rxq);
c8aaea25 1707
8a578111
LB		 1708 for (i = 0; i < rxq->rx_ring_size; i++) {
1709 if (rxq->rx_skb[i]) {
1710 dev_kfree_skb(rxq->rx_skb[i]);
1711 rxq->rx_desc_count--;
1da177e4 1712 }
c8aaea25 1713 }
1da177e4 1714
8a578111
LB		 1715 if (rxq->rx_desc_count) {
1716 dev_printk(KERN_ERR, &mp->dev->dev,
1717 "error freeing rx ring -- %d skbs stuck\n",
1718 rxq->rx_desc_count);
1719 }
1720
f7981c1c 1721 if (rxq->index == 0 &&
64da80a2 1722 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
8a578111 1723 iounmap(rxq->rx_desc_area);
c9df406f 1724 else
8a578111
LB		 1725 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1726 rxq->rx_desc_area, rxq->rx_desc_dma);
1727
1728 kfree(rxq->rx_skb);
c9df406f 1729}
1da177e4 1730
3d6b35bc 1731static int txq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1732{
3d6b35bc 1733 struct tx_queue *txq = mp->txq + index;
13d64285
LB		 1734 struct tx_desc *tx_desc;
1735 int size;
c9df406f 1736 int i;
1da177e4 1737
3d6b35bc
LB		 1738 txq->index = index;
1739
13d64285
LB		 1740 txq->tx_ring_size = mp->default_tx_ring_size;
1741
1742 txq->tx_desc_count = 0;
1743 txq->tx_curr_desc = 0;
1744 txq->tx_used_desc = 0;
1745
1746 size = txq->tx_ring_size * sizeof(struct tx_desc);
1747
f7981c1c 1748 if (index == 0 && size <= mp->tx_desc_sram_size) {
13d64285
LB		 1749 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1750 mp->tx_desc_sram_size);
1751 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1752 } else {
1753 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1754 &txq->tx_desc_dma,
1755 GFP_KERNEL);
1756 }
1757
1758 if (txq->tx_desc_area == NULL) {
1759 dev_printk(KERN_ERR, &mp->dev->dev,
1760 "can't allocate tx ring (%d bytes)\n", size);
99ab08e0 1761 return -ENOMEM;
c9df406f 1762 }
13d64285
LB		 1763 memset(txq->tx_desc_area, 0, size);
1764
1765 txq->tx_desc_area_size = size;
13d64285
LB		 1766
1767 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1768 for (i = 0; i < txq->tx_ring_size; i++) {
6b368f68 1769 struct tx_desc *txd = tx_desc + i;
9da78745
LB		 1770 int nexti;
1771
1772 nexti = i + 1;
1773 if (nexti == txq->tx_ring_size)
1774 nexti = 0;
6b368f68
LB		 1775
1776 txd->cmd_sts = 0;
1777 txd->next_desc_ptr = txq->tx_desc_dma +
13d64285
LB		 1778 nexti * sizeof(struct tx_desc);
1779 }
1780
99ab08e0 1781 skb_queue_head_init(&txq->tx_skb);
c9df406f 1782
99ab08e0 1783 return 0;
c8aaea25 1784}
1da177e4 1785
13d64285 1786static void txq_deinit(struct tx_queue *txq)
c9df406f 1787{
13d64285 1788 struct mv643xx_eth_private *mp = txq_to_mp(txq);
fa3959f4 1789
13d64285 1790 txq_disable(txq);
1fa38c58 1791 txq_reclaim(txq, txq->tx_ring_size, 1);
1da177e4 1792
13d64285 1793 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1da177e4 1794
f7981c1c 1795 if (txq->index == 0 &&
3d6b35bc 1796 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
13d64285 1797 iounmap(txq->tx_desc_area);
c9df406f 1798 else
13d64285
LB		 1799 dma_free_coherent(NULL, txq->tx_desc_area_size,
1800 txq->tx_desc_area, txq->tx_desc_dma);
c9df406f 1801}
1da177e4 1802
1da177e4 1803
c9df406f 1804/* netdev ops and related ***************************************************/
1fa38c58
LB		 1805static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
1806{
1807 u32 int_cause;
1808 u32 int_cause_ext;
1809
37a6084f 1810 int_cause = rdlp(mp, INT_CAUSE) & (INT_TX_END | INT_RX | INT_EXT);
1fa38c58
LB		 1811 if (int_cause == 0)
1812 return 0;
1813
1814 int_cause_ext = 0;
1815 if (int_cause & INT_EXT)
37a6084f 1816 int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
1fa38c58
LB		 1817
1818 int_cause &= INT_TX_END | INT_RX;
1819 if (int_cause) {
37a6084f 1820 wrlp(mp, INT_CAUSE, ~int_cause);
1fa38c58 1821 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
37a6084f 1822 ~(rdlp(mp, TXQ_COMMAND) & 0xff);
1fa38c58
LB		 1823 mp->work_rx |= (int_cause & INT_RX) >> 2;
1824 }
1825
1826 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
1827 if (int_cause_ext) {
37a6084f 1828 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);
1fa38c58
LB		 1829 if (int_cause_ext & INT_EXT_LINK_PHY)
1830 mp->work_link = 1;
1831 mp->work_tx |= int_cause_ext & INT_EXT_TX;
1832 }
1833
1834 return 1;
1835}
1836
1837static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1838{
1839 struct net_device *dev = (struct net_device *)dev_id;
1840 struct mv643xx_eth_private *mp = netdev_priv(dev);
1841
1842 if (unlikely(!mv643xx_eth_collect_events(mp)))
1843 return IRQ_NONE;
1844
37a6084f 1845 wrlp(mp, INT_MASK, 0);
1fa38c58
LB		 1846 napi_schedule(&mp->napi);
1847
1848 return IRQ_HANDLED;
1849}
1850
2f7eb47a
LB		 1851static void handle_link_event(struct mv643xx_eth_private *mp)
1852{
1853 struct net_device *dev = mp->dev;
1854 u32 port_status;
1855 int speed;
1856 int duplex;
1857 int fc;
1858
37a6084f 1859 port_status = rdlp(mp, PORT_STATUS);
2f7eb47a
LB		 1860 if (!(port_status & LINK_UP)) {
1861 if (netif_carrier_ok(dev)) {
1862 int i;
1863
1864 printk(KERN_INFO "%s: link down\n", dev->name);
1865
1866 netif_carrier_off(dev);
2f7eb47a 1867
f7981c1c 1868 for (i = 0; i < mp->txq_count; i++) {
2f7eb47a
LB		 1869 struct tx_queue *txq = mp->txq + i;
1870
1fa38c58 1871 txq_reclaim(txq, txq->tx_ring_size, 1);
f7981c1c 1872 txq_reset_hw_ptr(txq);
2f7eb47a
LB		 1873 }
1874 }
1875 return;
1876 }
1877
1878 switch (port_status & PORT_SPEED_MASK) {
1879 case PORT_SPEED_10:
1880 speed = 10;
1881 break;
1882 case PORT_SPEED_100:
1883 speed = 100;
1884 break;
1885 case PORT_SPEED_1000:
1886 speed = 1000;
1887 break;
1888 default:
1889 speed = -1;
1890 break;
1891 }
1892 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
1893 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
1894
1895 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
1896 "flow control %sabled\n", dev->name,
1897 speed, duplex ? "full" : "half",
1898 fc ? "en" : "dis");
1899
4fdeca3f 1900 if (!netif_carrier_ok(dev))
2f7eb47a 1901 netif_carrier_on(dev);
2f7eb47a
LB		 1902}
1903
1fa38c58 1904static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
c9df406f 1905{
1fa38c58
LB		 1906 struct mv643xx_eth_private *mp;
1907 int work_done;
ce4e2e45 1908
1fa38c58 1909 mp = container_of(napi, struct mv643xx_eth_private, napi);
fc32b0e2 1910
1fa38c58
LB		 1911 mp->work_rx_refill |= mp->work_rx_oom;
1912 mp->work_rx_oom = 0;
1da177e4 1913
1fa38c58
LB		 1914 work_done = 0;
1915 while (work_done < budget) {
1916 u8 queue_mask;
1917 int queue;
1918 int work_tbd;
1919
1920 if (mp->work_link) {
1921 mp->work_link = 0;
1922 handle_link_event(mp);
1923 continue;
1924 }
1da177e4 1925
1fa38c58
LB		 1926 queue_mask = mp->work_tx | mp->work_tx_end |
1927 mp->work_rx | mp->work_rx_refill;
1928 if (!queue_mask) {
1929 if (mv643xx_eth_collect_events(mp))
1930 continue;
1931 break;
1932 }
1da177e4 1933
1fa38c58
LB		 1934 queue = fls(queue_mask) - 1;
1935 queue_mask = 1 << queue;
1936
1937 work_tbd = budget - work_done;
1938 if (work_tbd > 16)
1939 work_tbd = 16;
1940
1941 if (mp->work_tx_end & queue_mask) {
1942 txq_kick(mp->txq + queue);
1943 } else if (mp->work_tx & queue_mask) {
1944 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
1945 txq_maybe_wake(mp->txq + queue);
1946 } else if (mp->work_rx & queue_mask) {
1947 work_done += rxq_process(mp->rxq + queue, work_tbd);
1948 } else if (mp->work_rx_refill & queue_mask) {
1949 work_done += rxq_refill(mp->rxq + queue, work_tbd);
1950 } else {
1951 BUG();
1952 }
84dd619e 1953 }
fc32b0e2 1954
1fa38c58
LB		 1955 if (work_done < budget) {
1956 if (mp->work_rx_oom)
1957 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
1958 napi_complete(napi);
37a6084f 1959 wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT);
226bb6b7 1960 }
3d6b35bc 1961
1fa38c58
LB		 1962 return work_done;
1963}
8fa89bf5 1964
1fa38c58
LB		 1965static inline void oom_timer_wrapper(unsigned long data)
1966{
1967 struct mv643xx_eth_private *mp = (void *)data;
1da177e4 1968
1fa38c58 1969 napi_schedule(&mp->napi);
1da177e4
LT		 1970}
1971
e5371493 1972static void phy_reset(struct mv643xx_eth_private *mp)
1da177e4 1973{
45c5d3bc
LB		 1974 int data;
1975
ed94493f 1976 data = phy_read(mp->phy, MII_BMCR);
45c5d3bc
LB		 1977 if (data < 0)
1978 return;
1da177e4 1979
7f106c1d 1980 data |= BMCR_RESET;
ed94493f 1981 if (phy_write(mp->phy, MII_BMCR, data) < 0)
45c5d3bc 1982 return;
1da177e4 1983
c9df406f 1984 do {
ed94493f 1985 data = phy_read(mp->phy, MII_BMCR);
45c5d3bc 1986 } while (data >= 0 && data & BMCR_RESET);
1da177e4
LT		 1987}
1988
fc32b0e2 1989static void port_start(struct mv643xx_eth_private *mp)
1da177e4 1990{
d0412d96 1991 u32 pscr;
8a578111 1992 int i;
1da177e4 1993
bedfe324
LB		 1994 /*
1995 * Perform PHY reset, if there is a PHY.
1996 */
ed94493f 1997 if (mp->phy != NULL) {
bedfe324
LB		 1998 struct ethtool_cmd cmd;
1999
2000 mv643xx_eth_get_settings(mp->dev, &cmd);
2001 phy_reset(mp);
2002 mv643xx_eth_set_settings(mp->dev, &cmd);
2003 }
1da177e4 2004
81600eea
LB		 2005 /*
2006 * Configure basic link parameters.
2007 */
37a6084f 2008 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
81600eea
LB		 2009
2010 pscr |= SERIAL_PORT_ENABLE;
37a6084f 2011 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea
LB		 2012
2013 pscr |= DO_NOT_FORCE_LINK_FAIL;
ed94493f 2014 if (mp->phy == NULL)
81600eea 2015 pscr |= FORCE_LINK_PASS;
37a6084f 2016 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea 2017
37a6084f 2018 wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);
81600eea 2019
13d64285
LB		 2020 /*
2021 * Configure TX path and queues.
2022 */
89df5fdc 2023 tx_set_rate(mp, 1000000000, 16777216);
f7981c1c 2024 for (i = 0; i < mp->txq_count; i++) {
3d6b35bc 2025 struct tx_queue *txq = mp->txq + i;
13d64285 2026
6b368f68 2027 txq_reset_hw_ptr(txq);
89df5fdc
LB		 2028 txq_set_rate(txq, 1000000000, 16777216);
2029 txq_set_fixed_prio_mode(txq);
13d64285
LB		 2030 }
2031
fc32b0e2
LB		 2032 /*
2033 * Add configured unicast address to address filter table.
2034 */
66e63ffb 2035 mv643xx_eth_program_unicast_filter(mp->dev);
1da177e4 2036
d9a073ea
LB		 2037 /*
2038 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
170e7108
LB		 2039 * frames to RX queue #0, and include the pseudo-header when
2040 * calculating receive checksums.
d9a073ea 2041 */
37a6084f 2042 wrlp(mp, PORT_CONFIG, 0x02000000);
01999873 2043
376489a2
LB		 2044 /*
2045 * Treat BPDUs as normal multicasts, and disable partition mode.
2046 */
37a6084f 2047 wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
01999873 2048
8a578111 2049 /*
64da80a2 2050 * Enable the receive queues.
8a578111 2051 */
f7981c1c 2052 for (i = 0; i < mp->rxq_count; i++) {
64da80a2 2053 struct rx_queue *rxq = mp->rxq + i;
8a578111 2054 u32 addr;
1da177e4 2055
8a578111
LB		 2056 addr = (u32)rxq->rx_desc_dma;
2057 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
37a6084f 2058 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);
1da177e4 2059
8a578111
LB		 2060 rxq_enable(rxq);
2061 }
1da177e4
LT		 2062}
2063
ffd86bbe 2064static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1da177e4 2065{
c9df406f 2066 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
773fc3ee 2067 u32 val;
1da177e4 2068
37a6084f 2069 val = rdlp(mp, SDMA_CONFIG);
773fc3ee
LB		 2070 if (mp->shared->extended_rx_coal_limit) {
2071 if (coal > 0xffff)
2072 coal = 0xffff;
2073 val &= ~0x023fff80;
2074 val |= (coal & 0x8000) << 10;
2075 val |= (coal & 0x7fff) << 7;
2076 } else {
2077 if (coal > 0x3fff)
2078 coal = 0x3fff;
2079 val &= ~0x003fff00;
2080 val |= (coal & 0x3fff) << 8;
2081 }
37a6084f 2082 wrlp(mp, SDMA_CONFIG, val);
1da177e4
LT		 2083}
2084
ffd86bbe 2085static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1da177e4 2086{
c9df406f 2087 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1da177e4 2088
fc32b0e2
LB		 2089 if (coal > 0x3fff)
2090 coal = 0x3fff;
37a6084f 2091 wrlp(mp, TX_FIFO_URGENT_THRESHOLD, (coal & 0x3fff) << 4);
16e03018
DF		 2092}
2093
2bcb4b0f
LB		 2094static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
2095{
2096 int skb_size;
2097
2098 /*
2099 * Reserve 2+14 bytes for an ethernet header (the hardware
2100 * automatically prepends 2 bytes of dummy data to each
2101 * received packet), 16 bytes for up to four VLAN tags, and
2102 * 4 bytes for the trailing FCS -- 36 bytes total.
2103 */
2104 skb_size = mp->dev->mtu + 36;
2105
2106 /*
2107 * Make sure that the skb size is a multiple of 8 bytes, as
2108 * the lower three bits of the receive descriptor's buffer
2109 * size field are ignored by the hardware.
2110 */
2111 mp->skb_size = (skb_size + 7) & ~7;
2112}
2113
c9df406f 2114static int mv643xx_eth_open(struct net_device *dev)
16e03018 2115{
e5371493 2116 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2117 int err;
64da80a2 2118 int i;
16e03018 2119
37a6084f
LB		 2120 wrlp(mp, INT_CAUSE, 0);
2121 wrlp(mp, INT_CAUSE_EXT, 0);
2122 rdlp(mp, INT_CAUSE_EXT);
c9df406f 2123
fc32b0e2 2124 err = request_irq(dev->irq, mv643xx_eth_irq,
2a1867a7 2125 IRQF_SHARED, dev->name, dev);
c9df406f 2126 if (err) {
fc32b0e2 2127 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
c9df406f 2128 return -EAGAIN;
16e03018
DF		 2129 }
2130
2bcb4b0f
LB		 2131 mv643xx_eth_recalc_skb_size(mp);
2132
2257e05c
LB		 2133 napi_enable(&mp->napi);
2134
2bcb4b0f
LB		 2135 skb_queue_head_init(&mp->rx_recycle);
2136
f7981c1c 2137 for (i = 0; i < mp->rxq_count; i++) {
64da80a2
LB		 2138 err = rxq_init(mp, i);
2139 if (err) {
2140 while (--i >= 0)
f7981c1c 2141 rxq_deinit(mp->rxq + i);
64da80a2
LB		 2142 goto out;
2143 }
2144
1fa38c58 2145 rxq_refill(mp->rxq + i, INT_MAX);
2257e05c
LB		 2146 }
2147
1fa38c58 2148 if (mp->work_rx_oom) {
2257e05c
LB		 2149 mp->rx_oom.expires = jiffies + (HZ / 10);
2150 add_timer(&mp->rx_oom);
64da80a2 2151 }
8a578111 2152
f7981c1c 2153 for (i = 0; i < mp->txq_count; i++) {
3d6b35bc
LB		 2154 err = txq_init(mp, i);
2155 if (err) {
2156 while (--i >= 0)
f7981c1c 2157 txq_deinit(mp->txq + i);
3d6b35bc
LB		 2158 goto out_free;
2159 }
2160 }
16e03018 2161
2f7eb47a 2162 netif_carrier_off(dev);
2f7eb47a 2163
fc32b0e2 2164 port_start(mp);
16e03018 2165
ffd86bbe
LB		 2166 set_rx_coal(mp, 0);
2167 set_tx_coal(mp, 0);
16e03018 2168
37a6084f
LB		 2169 wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);
2170 wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT);
16e03018 2171
c9df406f
LB		 2172 return 0;
2173
13d64285 2174
fc32b0e2 2175out_free:
f7981c1c
LB		 2176 for (i = 0; i < mp->rxq_count; i++)
2177 rxq_deinit(mp->rxq + i);
fc32b0e2 2178out:
c9df406f
LB		 2179 free_irq(dev->irq, dev);
2180
2181 return err;
16e03018
DF		 2182}
2183
e5371493 2184static void port_reset(struct mv643xx_eth_private *mp)
1da177e4 2185{
fc32b0e2 2186 unsigned int data;
64da80a2 2187 int i;
1da177e4 2188
f7981c1c
LB		 2189 for (i = 0; i < mp->rxq_count; i++)
2190 rxq_disable(mp->rxq + i);
2191 for (i = 0; i < mp->txq_count; i++)
2192 txq_disable(mp->txq + i);
ae9ae064
LB		 2193
2194 while (1) {
37a6084f 2195 u32 ps = rdlp(mp, PORT_STATUS);
ae9ae064
LB		 2196
2197 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2198 break;
13d64285 2199 udelay(10);
ae9ae064 2200 }
1da177e4 2201
c9df406f 2202 /* Reset the Enable bit in the Configuration Register */
37a6084f 2203 data = rdlp(mp, PORT_SERIAL_CONTROL);
fc32b0e2
LB		 2204 data &= ~(SERIAL_PORT_ENABLE |
2205 DO_NOT_FORCE_LINK_FAIL |
2206 FORCE_LINK_PASS);
37a6084f 2207 wrlp(mp, PORT_SERIAL_CONTROL, data);
1da177e4
LT		 2208}
2209
c9df406f 2210static int mv643xx_eth_stop(struct net_device *dev)
1da177e4 2211{
e5371493 2212 struct mv643xx_eth_private *mp = netdev_priv(dev);
64da80a2 2213 int i;
1da177e4 2214
37a6084f
LB		 2215 wrlp(mp, INT_MASK, 0x00000000);
2216 rdlp(mp, INT_MASK);
1da177e4 2217
4ff3495a
LB		 2218 del_timer_sync(&mp->mib_counters_timer);
2219
c9df406f 2220 napi_disable(&mp->napi);
78fff83b 2221
2257e05c
LB		 2222 del_timer_sync(&mp->rx_oom);
2223
c9df406f 2224 netif_carrier_off(dev);
1da177e4 2225
fc32b0e2
LB		 2226 free_irq(dev->irq, dev);
2227
cc9754b3 2228 port_reset(mp);
8fd89211 2229 mv643xx_eth_get_stats(dev);
fc32b0e2 2230 mib_counters_update(mp);
1da177e4 2231
2bcb4b0f
LB		 2232 skb_queue_purge(&mp->rx_recycle);
2233
f7981c1c
LB		 2234 for (i = 0; i < mp->rxq_count; i++)
2235 rxq_deinit(mp->rxq + i);
2236 for (i = 0; i < mp->txq_count; i++)
2237 txq_deinit(mp->txq + i);
1da177e4 2238
c9df406f 2239 return 0;
1da177e4
LT		 2240}
2241
fc32b0e2 2242static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1da177e4 2243{
e5371493 2244 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2245
ed94493f
LB		 2246 if (mp->phy != NULL)
2247 return phy_mii_ioctl(mp->phy, if_mii(ifr), cmd);
bedfe324
LB		 2248
2249 return -EOPNOTSUPP;
1da177e4
LT		 2250}
2251
c9df406f 2252static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 2253{
89df5fdc
LB		 2254 struct mv643xx_eth_private *mp = netdev_priv(dev);
2255
fc32b0e2 2256 if (new_mtu < 64 || new_mtu > 9500)
c9df406f 2257 return -EINVAL;
1da177e4 2258
c9df406f 2259 dev->mtu = new_mtu;
2bcb4b0f 2260 mv643xx_eth_recalc_skb_size(mp);
89df5fdc
LB		 2261 tx_set_rate(mp, 1000000000, 16777216);
2262
c9df406f
LB		 2263 if (!netif_running(dev))
2264 return 0;
1da177e4 2265
c9df406f
LB		 2266 /*
2267 * Stop and then re-open the interface. This will allocate RX
2268 * skbs of the new MTU.
2269 * There is a possible danger that the open will not succeed,
fc32b0e2 2270 * due to memory being full.
c9df406f
LB		 2271 */
2272 mv643xx_eth_stop(dev);
2273 if (mv643xx_eth_open(dev)) {
fc32b0e2
LB		 2274 dev_printk(KERN_ERR, &dev->dev,
2275 "fatal error on re-opening device after "
2276 "MTU change\n");
c9df406f
LB		 2277 }
2278
2279 return 0;
1da177e4
LT		 2280}
2281
fc32b0e2 2282static void tx_timeout_task(struct work_struct *ugly)
1da177e4 2283{
fc32b0e2 2284 struct mv643xx_eth_private *mp;
1da177e4 2285
fc32b0e2
LB		 2286 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2287 if (netif_running(mp->dev)) {
e5ef1de1 2288 netif_tx_stop_all_queues(mp->dev);
fc32b0e2
LB		 2289 port_reset(mp);
2290 port_start(mp);
e5ef1de1 2291 netif_tx_wake_all_queues(mp->dev);
fc32b0e2 2292 }
c9df406f
LB		 2293}
2294
c9df406f 2295static void mv643xx_eth_tx_timeout(struct net_device *dev)
1da177e4 2296{
e5371493 2297 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2298
fc32b0e2 2299 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
d0412d96 2300
c9df406f 2301 schedule_work(&mp->tx_timeout_task);
1da177e4
LT		 2302}
2303
c9df406f 2304#ifdef CONFIG_NET_POLL_CONTROLLER
fc32b0e2 2305static void mv643xx_eth_netpoll(struct net_device *dev)
9f8dd319 2306{
fc32b0e2 2307 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2308
37a6084f
LB		 2309 wrlp(mp, INT_MASK, 0x00000000);
2310 rdlp(mp, INT_MASK);
c9df406f 2311
fc32b0e2 2312 mv643xx_eth_irq(dev->irq, dev);
c9df406f 2313
37a6084f 2314 wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT);
9f8dd319 2315}
c9df406f 2316#endif
9f8dd319 2317
9f8dd319 2318
c9df406f 2319/* platform glue ************************************************************/
e5371493
LB		 2320static void
2321mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2322 struct mbus_dram_target_info *dram)
c9df406f 2323{
cc9754b3 2324 void __iomem *base = msp->base;
c9df406f
LB		 2325 u32 win_enable;
2326 u32 win_protect;
2327 int i;
9f8dd319 2328
c9df406f
LB		 2329 for (i = 0; i < 6; i++) {
2330 writel(0, base + WINDOW_BASE(i));
2331 writel(0, base + WINDOW_SIZE(i));
2332 if (i < 4)
2333 writel(0, base + WINDOW_REMAP_HIGH(i));
9f8dd319
DF		 2334 }
2335
c9df406f
LB		 2336 win_enable = 0x3f;
2337 win_protect = 0;
2338
2339 for (i = 0; i < dram->num_cs; i++) {
2340 struct mbus_dram_window *cs = dram->cs + i;
2341
2342 writel((cs->base & 0xffff0000) |
2343 (cs->mbus_attr << 8) |
2344 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2345 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2346
2347 win_enable &= ~(1 << i);
2348 win_protect |= 3 << (2 * i);
2349 }
2350
2351 writel(win_enable, base + WINDOW_BAR_ENABLE);
2352 msp->win_protect = win_protect;
9f8dd319
DF		 2353}
2354
773fc3ee
LB		 2355static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2356{
2357 /*
2358 * Check whether we have a 14-bit coal limit field in bits
2359 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2360 * SDMA config register.
2361 */
37a6084f
LB		 2362 writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
2363 if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000)
773fc3ee
LB		 2364 msp->extended_rx_coal_limit = 1;
2365 else
2366 msp->extended_rx_coal_limit = 0;
1e881592
LB		 2367
2368 /*
457b1d5a
LB		 2369 * Check whether the MAC supports TX rate control, and if
2370 * yes, whether its associated registers are in the old or
2371 * the new place.
1e881592 2372 */
37a6084f
LB		 2373 writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
2374 if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) {
457b1d5a
LB		 2375 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2376 } else {
37a6084f
LB		 2377 writel(7, msp->base + 0x0400 + TX_BW_RATE);
2378 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7)
457b1d5a
LB		 2379 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2380 else
2381 msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2382 }
773fc3ee
LB		 2383}
2384
c9df406f 2385static int mv643xx_eth_shared_probe(struct platform_device *pdev)
9f8dd319 2386{
10a9948d 2387 static int mv643xx_eth_version_printed;
c9df406f 2388 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
e5371493 2389 struct mv643xx_eth_shared_private *msp;
c9df406f
LB		 2390 struct resource *res;
2391 int ret;
9f8dd319 2392
e5371493 2393 if (!mv643xx_eth_version_printed++)
7dde154d
LB		 2394 printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet "
2395 "driver version %s\n", mv643xx_eth_driver_version);
9f8dd319 2396
c9df406f
LB		 2397 ret = -EINVAL;
2398 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2399 if (res == NULL)
2400 goto out;
9f8dd319 2401
c9df406f
LB		 2402 ret = -ENOMEM;
2403 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2404 if (msp == NULL)
2405 goto out;
2406 memset(msp, 0, sizeof(*msp));
2407
cc9754b3
LB		 2408 msp->base = ioremap(res->start, res->end - res->start + 1);
2409 if (msp->base == NULL)
c9df406f
LB		 2410 goto out_free;
2411
ed94493f
LB		 2412 /*
2413 * Set up and register SMI bus.
2414 */
2415 if (pd == NULL || pd->shared_smi == NULL) {
298cf9be
LB		 2416 msp->smi_bus = mdiobus_alloc();
2417 if (msp->smi_bus == NULL)
ed94493f 2418 goto out_unmap;
298cf9be
LB		 2419
2420 msp->smi_bus->priv = msp;
2421 msp->smi_bus->name = "mv643xx_eth smi";
2422 msp->smi_bus->read = smi_bus_read;
2423 msp->smi_bus->write = smi_bus_write,
2424 snprintf(msp->smi_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id);
2425 msp->smi_bus->parent = &pdev->dev;
2426 msp->smi_bus->phy_mask = 0xffffffff;
2427 if (mdiobus_register(msp->smi_bus) < 0)
2428 goto out_free_mii_bus;
ed94493f
LB		 2429 msp->smi = msp;
2430 } else {
fc0eb9f2 2431 msp->smi = platform_get_drvdata(pd->shared_smi);
ed94493f 2432 }
c9df406f 2433
45c5d3bc
LB		 2434 msp->err_interrupt = NO_IRQ;
2435 init_waitqueue_head(&msp->smi_busy_wait);
2436
2437 /*
2438 * Check whether the error interrupt is hooked up.
2439 */
2440 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2441 if (res != NULL) {
2442 int err;
2443
2444 err = request_irq(res->start, mv643xx_eth_err_irq,
2445 IRQF_SHARED, "mv643xx_eth", msp);
2446 if (!err) {
2447 writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK);
2448 msp->err_interrupt = res->start;
2449 }
2450 }
2451
c9df406f
LB		 2452 /*
2453 * (Re-)program MBUS remapping windows if we are asked to.
2454 */
2455 if (pd != NULL && pd->dram != NULL)
2456 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2457
fc32b0e2
LB		 2458 /*
2459 * Detect hardware parameters.
2460 */
2461 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
773fc3ee 2462 infer_hw_params(msp);
fc32b0e2
LB		 2463
2464 platform_set_drvdata(pdev, msp);
2465
c9df406f
LB		 2466 return 0;
2467
298cf9be
LB		 2468out_free_mii_bus:
2469 mdiobus_free(msp->smi_bus);
ed94493f
LB		 2470out_unmap:
2471 iounmap(msp->base);
c9df406f
LB		 2472out_free:
2473 kfree(msp);
2474out:
2475 return ret;
2476}
2477
2478static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2479{
e5371493 2480 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
ed94493f 2481 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
c9df406f 2482
298cf9be 2483 if (pd == NULL || pd->shared_smi == NULL) {
298cf9be 2484 mdiobus_unregister(msp->smi_bus);
bcb3336c 2485 mdiobus_free(msp->smi_bus);
298cf9be 2486 }
45c5d3bc
LB		 2487 if (msp->err_interrupt != NO_IRQ)
2488 free_irq(msp->err_interrupt, msp);
cc9754b3 2489 iounmap(msp->base);
c9df406f
LB		 2490 kfree(msp);
2491
2492 return 0;
9f8dd319
DF		 2493}
2494
c9df406f 2495static struct platform_driver mv643xx_eth_shared_driver = {
fc32b0e2
LB		 2496 .probe = mv643xx_eth_shared_probe,
2497 .remove = mv643xx_eth_shared_remove,
c9df406f 2498 .driver = {
fc32b0e2 2499 .name = MV643XX_ETH_SHARED_NAME,
c9df406f
LB		 2500 .owner = THIS_MODULE,
2501 },
2502};
2503
e5371493 2504static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
1da177e4 2505{
c9df406f 2506 int addr_shift = 5 * mp->port_num;
fc32b0e2 2507 u32 data;
1da177e4 2508
fc32b0e2
LB		 2509 data = rdl(mp, PHY_ADDR);
2510 data &= ~(0x1f << addr_shift);
2511 data |= (phy_addr & 0x1f) << addr_shift;
2512 wrl(mp, PHY_ADDR, data);
1da177e4
LT		 2513}
2514
e5371493 2515static int phy_addr_get(struct mv643xx_eth_private *mp)
1da177e4 2516{
fc32b0e2
LB		 2517 unsigned int data;
2518
2519 data = rdl(mp, PHY_ADDR);
2520
2521 return (data >> (5 * mp->port_num)) & 0x1f;
2522}
2523
2524static void set_params(struct mv643xx_eth_private *mp,
2525 struct mv643xx_eth_platform_data *pd)
2526{
2527 struct net_device *dev = mp->dev;
2528
2529 if (is_valid_ether_addr(pd->mac_addr))
2530 memcpy(dev->dev_addr, pd->mac_addr, 6);
2531 else
2532 uc_addr_get(mp, dev->dev_addr);
2533
fc32b0e2
LB		 2534 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2535 if (pd->rx_queue_size)
2536 mp->default_rx_ring_size = pd->rx_queue_size;
2537 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2538 mp->rx_desc_sram_size = pd->rx_sram_size;
1da177e4 2539
f7981c1c 2540 mp->rxq_count = pd->rx_queue_count ? : 1;
64da80a2 2541
fc32b0e2
LB		 2542 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2543 if (pd->tx_queue_size)
2544 mp->default_tx_ring_size = pd->tx_queue_size;
2545 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2546 mp->tx_desc_sram_size = pd->tx_sram_size;
3d6b35bc 2547
f7981c1c 2548 mp->txq_count = pd->tx_queue_count ? : 1;
1da177e4
LT		 2549}
2550
ed94493f
LB		 2551static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
2552 int phy_addr)
1da177e4 2553{
298cf9be 2554 struct mii_bus *bus = mp->shared->smi->smi_bus;
ed94493f
LB		 2555 struct phy_device *phydev;
2556 int start;
2557 int num;
2558 int i;
45c5d3bc 2559
ed94493f
LB		 2560 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
2561 start = phy_addr_get(mp) & 0x1f;
2562 num = 32;
2563 } else {
2564 start = phy_addr & 0x1f;
2565 num = 1;
2566 }
45c5d3bc 2567
ed94493f
LB		 2568 phydev = NULL;
2569 for (i = 0; i < num; i++) {
2570 int addr = (start + i) & 0x1f;
fc32b0e2 2571
ed94493f
LB		 2572 if (bus->phy_map[addr] == NULL)
2573 mdiobus_scan(bus, addr);
1da177e4 2574
ed94493f
LB		 2575 if (phydev == NULL) {
2576 phydev = bus->phy_map[addr];
2577 if (phydev != NULL)
2578 phy_addr_set(mp, addr);
2579 }
2580 }
1da177e4 2581
ed94493f 2582 return phydev;
1da177e4
LT		 2583}
2584
ed94493f 2585static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
c28a4f89 2586{
ed94493f 2587 struct phy_device *phy = mp->phy;
c28a4f89 2588
fc32b0e2
LB		 2589 phy_reset(mp);
2590
ed94493f
LB		 2591 phy_attach(mp->dev, phy->dev.bus_id, 0, PHY_INTERFACE_MODE_GMII);
2592
2593 if (speed == 0) {
2594 phy->autoneg = AUTONEG_ENABLE;
2595 phy->speed = 0;
2596 phy->duplex = 0;
2597 phy->advertising = phy->supported | ADVERTISED_Autoneg;
c9df406f 2598 } else {
ed94493f
LB		 2599 phy->autoneg = AUTONEG_DISABLE;
2600 phy->advertising = 0;
2601 phy->speed = speed;
2602 phy->duplex = duplex;
c9df406f 2603 }
ed94493f 2604 phy_start_aneg(phy);
c28a4f89
JC		 2605}
2606
81600eea
LB		 2607static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2608{
2609 u32 pscr;
2610
37a6084f 2611 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
81600eea
LB		 2612 if (pscr & SERIAL_PORT_ENABLE) {
2613 pscr &= ~SERIAL_PORT_ENABLE;
37a6084f 2614 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea
LB		 2615 }
2616
2617 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
ed94493f 2618 if (mp->phy == NULL) {
81600eea
LB		 2619 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2620 if (speed == SPEED_1000)
2621 pscr |= SET_GMII_SPEED_TO_1000;
2622 else if (speed == SPEED_100)
2623 pscr |= SET_MII_SPEED_TO_100;
2624
2625 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2626
2627 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2628 if (duplex == DUPLEX_FULL)
2629 pscr |= SET_FULL_DUPLEX_MODE;
2630 }
2631
37a6084f 2632 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea
LB		 2633}
2634
c9df406f 2635static int mv643xx_eth_probe(struct platform_device *pdev)
1da177e4 2636{
c9df406f 2637 struct mv643xx_eth_platform_data *pd;
e5371493 2638 struct mv643xx_eth_private *mp;
c9df406f 2639 struct net_device *dev;
c9df406f 2640 struct resource *res;
fc32b0e2 2641 int err;
1da177e4 2642
c9df406f
LB		 2643 pd = pdev->dev.platform_data;
2644 if (pd == NULL) {
fc32b0e2
LB		 2645 dev_printk(KERN_ERR, &pdev->dev,
2646 "no mv643xx_eth_platform_data\n");
c9df406f
LB		 2647 return -ENODEV;
2648 }
1da177e4 2649
c9df406f 2650 if (pd->shared == NULL) {
fc32b0e2
LB		 2651 dev_printk(KERN_ERR, &pdev->dev,
2652 "no mv643xx_eth_platform_data->shared\n");
c9df406f
LB		 2653 return -ENODEV;
2654 }
8f518703 2655
e5ef1de1 2656 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
c9df406f
LB		 2657 if (!dev)
2658 return -ENOMEM;
1da177e4 2659
c9df406f 2660 mp = netdev_priv(dev);
fc32b0e2
LB		 2661 platform_set_drvdata(pdev, mp);
2662
2663 mp->shared = platform_get_drvdata(pd->shared);
37a6084f 2664 mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10);
fc32b0e2
LB		 2665 mp->port_num = pd->port_number;
2666
c9df406f 2667 mp->dev = dev;
78fff83b 2668
fc32b0e2 2669 set_params(mp, pd);
e5ef1de1 2670 dev->real_num_tx_queues = mp->txq_count;
fc32b0e2 2671
ed94493f
LB		 2672 if (pd->phy_addr != MV643XX_ETH_PHY_NONE)
2673 mp->phy = phy_scan(mp, pd->phy_addr);
bedfe324 2674
ed94493f
LB		 2675 if (mp->phy != NULL) {
2676 phy_init(mp, pd->speed, pd->duplex);
bedfe324
LB		 2677 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2678 } else {
2679 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless);
2680 }
ed94493f 2681
81600eea 2682 init_pscr(mp, pd->speed, pd->duplex);
fc32b0e2 2683
4ff3495a
LB		 2684
2685 mib_counters_clear(mp);
2686
2687 init_timer(&mp->mib_counters_timer);
2688 mp->mib_counters_timer.data = (unsigned long)mp;
2689 mp->mib_counters_timer.function = mib_counters_timer_wrapper;
2690 mp->mib_counters_timer.expires = jiffies + 30 * HZ;
2691 add_timer(&mp->mib_counters_timer);
2692
2693 spin_lock_init(&mp->mib_counters_lock);
2694
2695 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2696
2257e05c
LB		 2697 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
2698
2699 init_timer(&mp->rx_oom);
2700 mp->rx_oom.data = (unsigned long)mp;
2701 mp->rx_oom.function = oom_timer_wrapper;
2702
fc32b0e2 2703
c9df406f
LB		 2704 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2705 BUG_ON(!res);
2706 dev->irq = res->start;
1da177e4 2707
8fd89211 2708 dev->get_stats = mv643xx_eth_get_stats;
fc32b0e2 2709 dev->hard_start_xmit = mv643xx_eth_xmit;
c9df406f
LB		 2710 dev->open = mv643xx_eth_open;
2711 dev->stop = mv643xx_eth_stop;
66e63ffb 2712 dev->set_rx_mode = mv643xx_eth_set_rx_mode;
fc32b0e2
LB		 2713 dev->set_mac_address = mv643xx_eth_set_mac_address;
2714 dev->do_ioctl = mv643xx_eth_ioctl;
2715 dev->change_mtu = mv643xx_eth_change_mtu;
c9df406f 2716 dev->tx_timeout = mv643xx_eth_tx_timeout;
c9df406f 2717#ifdef CONFIG_NET_POLL_CONTROLLER
e5371493 2718 dev->poll_controller = mv643xx_eth_netpoll;
c9df406f 2719#endif
c9df406f
LB		 2720 dev->watchdog_timeo = 2 * HZ;
2721 dev->base_addr = 0;
1da177e4 2722
c9df406f 2723 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
e32b6617 2724 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
1da177e4 2725
fc32b0e2 2726 SET_NETDEV_DEV(dev, &pdev->dev);
8f518703 2727
c9df406f 2728 if (mp->shared->win_protect)
fc32b0e2 2729 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
1da177e4 2730
c9df406f
LB		 2731 err = register_netdev(dev);
2732 if (err)
2733 goto out;
1da177e4 2734
e174961c
JB		 2735 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %pM\n",
2736 mp->port_num, dev->dev_addr);
1da177e4 2737
13d64285 2738 if (mp->tx_desc_sram_size > 0)
fc32b0e2 2739 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
1da177e4 2740
c9df406f 2741 return 0;
1da177e4 2742
c9df406f
LB		 2743out:
2744 free_netdev(dev);
1da177e4 2745
c9df406f 2746 return err;
1da177e4
LT		 2747}
2748
c9df406f 2749static int mv643xx_eth_remove(struct platform_device *pdev)
1da177e4 2750{
fc32b0e2 2751 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
1da177e4 2752
fc32b0e2 2753 unregister_netdev(mp->dev);
ed94493f
LB		 2754 if (mp->phy != NULL)
2755 phy_detach(mp->phy);
c9df406f 2756 flush_scheduled_work();
fc32b0e2 2757 free_netdev(mp->dev);
c9df406f 2758
c9df406f 2759 platform_set_drvdata(pdev, NULL);
fc32b0e2 2760
c9df406f 2761 return 0;
1da177e4
LT		 2762}
2763
c9df406f 2764static void mv643xx_eth_shutdown(struct platform_device *pdev)
d0412d96 2765{
fc32b0e2 2766 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
d0412d96 2767
c9df406f 2768 /* Mask all interrupts on ethernet port */
37a6084f
LB		 2769 wrlp(mp, INT_MASK, 0);
2770 rdlp(mp, INT_MASK);
c9df406f 2771
fc32b0e2
LB		 2772 if (netif_running(mp->dev))
2773 port_reset(mp);
d0412d96
JC		 2774}
2775
c9df406f 2776static struct platform_driver mv643xx_eth_driver = {
fc32b0e2
LB		 2777 .probe = mv643xx_eth_probe,
2778 .remove = mv643xx_eth_remove,
2779 .shutdown = mv643xx_eth_shutdown,
c9df406f 2780 .driver = {
fc32b0e2 2781 .name = MV643XX_ETH_NAME,
c9df406f
LB		 2782 .owner = THIS_MODULE,
2783 },
2784};
2785
e5371493 2786static int __init mv643xx_eth_init_module(void)
d0412d96 2787{
c9df406f 2788 int rc;
d0412d96 2789
c9df406f
LB		 2790 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2791 if (!rc) {
2792 rc = platform_driver_register(&mv643xx_eth_driver);
2793 if (rc)
2794 platform_driver_unregister(&mv643xx_eth_shared_driver);
2795 }
fc32b0e2 2796
c9df406f 2797 return rc;
d0412d96 2798}
fc32b0e2 2799module_init(mv643xx_eth_init_module);
d0412d96 2800
e5371493 2801static void __exit mv643xx_eth_cleanup_module(void)
d0412d96 2802{
c9df406f
LB		 2803 platform_driver_unregister(&mv643xx_eth_driver);
2804 platform_driver_unregister(&mv643xx_eth_shared_driver);
d0412d96 2805}
e5371493 2806module_exit(mv643xx_eth_cleanup_module);
1da177e4 2807
45675bc6
LB		 2808MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2809 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
c9df406f 2810MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
fc32b0e2 2811MODULE_LICENSE("GPL");
c9df406f 2812MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
fc32b0e2 2813MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
Linux 6.x block layer and io_uring tree(s)