projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[PATCH] mv643xx_eth: Refactor tx command queuing code
[linux-2.6-block.git] / drivers / net / mv643xx_eth.c
CommitLineData
1da177e4
LT		 1/*
2 * drivers/net/mv643xx_eth.c - Driver for MV643XX ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 rabeeh@galileo.co.il
7 *
8 * Copyright (C) 2003 PMC-Sierra, Inc.,
3bb8a18a 9 * written by Manish Lachwani
1da177e4
LT		 10 *
11 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
12 *
c8aaea25 13 * Copyright (C) 2004-2006 MontaVista Software, Inc.
1da177e4
LT		 14 * Dale Farnsworth <dale@farnsworth.org>
15 *
16 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
17 * <sjhill@realitydiluted.com>
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version 2
22 * of the License, or (at your option) any later version.
23 *
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
28 *
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
32 */
33#include <linux/init.h>
34#include <linux/dma-mapping.h>
b6298c22
AV		 35#include <linux/in.h>
36#include <linux/ip.h>
1da177e4
LT		 37#include <linux/tcp.h>
38#include <linux/udp.h>
39#include <linux/etherdevice.h>
40
41#include <linux/bitops.h>
42#include <linux/delay.h>
43#include <linux/ethtool.h>
d052d1be
RK		 44#include <linux/platform_device.h>
45
1da177e4
LT		 46#include <asm/io.h>
47#include <asm/types.h>
48#include <asm/pgtable.h>
49#include <asm/system.h>
50#include <asm/delay.h>
51#include "mv643xx_eth.h"
52
53/*
54 * The first part is the high level driver of the gigE ethernet ports.
55 */
56
57/* Constants */
58#define VLAN_HLEN 4
59#define FCS_LEN 4
b44cd572
DF		 60#define DMA_ALIGN 8 /* hw requires 8-byte alignment */
61#define HW_IP_ALIGN 2 /* hw aligns IP header */
62#define WRAP HW_IP_ALIGN + ETH_HLEN + VLAN_HLEN + FCS_LEN
1da177e4
LT		 63#define RX_SKB_SIZE ((dev->mtu + WRAP + 7) & ~0x7)
64
c2e5b352
DF		 65#define INT_UNMASK_ALL 0x0007ffff
66#define INT_UNMASK_ALL_EXT 0x0011ffff
67#define INT_MASK_ALL 0x00000000
68#define INT_MASK_ALL_EXT 0x00000000
1da177e4
LT		 69#define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL
70#define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT
1da177e4
LT		 71
72#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
73#define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
74#else
75#define MAX_DESCS_PER_SKB 1
76#endif
77
78#define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */
79#define PHY_WAIT_MICRO_SECONDS 10
80
81/* Static function declarations */
1da177e4
LT		 82static void eth_port_uc_addr_get(struct net_device *dev,
83 unsigned char *MacAddr);
16e03018 84static void eth_port_set_multicast_list(struct net_device *);
9f8dd319 85static void mv643xx_eth_port_enable_tx(unsigned int port_num,
12a87c64 86 unsigned int queues);
9f8dd319 87static void mv643xx_eth_port_enable_rx(unsigned int port_num,
12a87c64 88 unsigned int queues);
9f8dd319
DF		 89static unsigned int mv643xx_eth_port_disable_tx(unsigned int port_num);
90static unsigned int mv643xx_eth_port_disable_rx(unsigned int port_num);
ab4384a6
DF		 91static int mv643xx_eth_open(struct net_device *);
92static int mv643xx_eth_stop(struct net_device *);
1da177e4
LT		 93static int mv643xx_eth_change_mtu(struct net_device *, int);
94static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *);
95static void eth_port_init_mac_tables(unsigned int eth_port_num);
96#ifdef MV643XX_NAPI
97static int mv643xx_poll(struct net_device *dev, int *budget);
98#endif
c28a4f89 99static int ethernet_phy_get(unsigned int eth_port_num);
1da177e4
LT		 100static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
101static int ethernet_phy_detect(unsigned int eth_port_num);
c28a4f89
JC		 102static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location);
103static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val);
d0412d96 104static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
1da177e4
LT		 105static struct ethtool_ops mv643xx_ethtool_ops;
106
107static char mv643xx_driver_name[] = "mv643xx_eth";
108static char mv643xx_driver_version[] = "1.0";
109
110static void __iomem *mv643xx_eth_shared_base;
111
112/* used to protect MV643XX_ETH_SMI_REG, which is shared across ports */
a9f6a0dd 113static DEFINE_SPINLOCK(mv643xx_eth_phy_lock);
1da177e4
LT		 114
115static inline u32 mv_read(int offset)
116{
dc074a8a 117 void __iomem *reg_base;
1da177e4
LT		 118
119 reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS;
120
121 return readl(reg_base + offset);
122}
123
124static inline void mv_write(int offset, u32 data)
125{
dc074a8a 126 void __iomem *reg_base;
1da177e4
LT		 127
128 reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS;
129 writel(data, reg_base + offset);
130}
131
132/*
133 * Changes MTU (maximum transfer unit) of the gigabit ethenret port
134 *
135 * Input : pointer to ethernet interface network device structure
136 * new mtu size
137 * Output : 0 upon success, -EINVAL upon failure
138 */
139static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
140{
8f518703 141 if ((new_mtu > 9500) || (new_mtu < 64))
1da177e4 142 return -EINVAL;
1da177e4
LT		 143
144 dev->mtu = new_mtu;
145 /*
146 * Stop then re-open the interface. This will allocate RX skb's with
147 * the new MTU.
148 * There is a possible danger that the open will not successed, due
149 * to memory is full, which might fail the open function.
150 */
151 if (netif_running(dev)) {
ab4384a6
DF		 152 mv643xx_eth_stop(dev);
153 if (mv643xx_eth_open(dev))
1da177e4
LT		 154 printk(KERN_ERR
155 "%s: Fatal error on opening device\n",
156 dev->name);
157 }
158
1da177e4
LT		 159 return 0;
160}
161
162/*
163 * mv643xx_eth_rx_task
164 *
165 * Fills / refills RX queue on a certain gigabit ethernet port
166 *
167 * Input : pointer to ethernet interface network device structure
168 * Output : N/A
169 */
170static void mv643xx_eth_rx_task(void *data)
171{
172 struct net_device *dev = (struct net_device *)data;
173 struct mv643xx_private *mp = netdev_priv(dev);
174 struct pkt_info pkt_info;
175 struct sk_buff *skb;
b44cd572 176 int unaligned;
1da177e4
LT		 177
178 if (test_and_set_bit(0, &mp->rx_task_busy))
179 panic("%s: Error in test_set_bit / clear_bit", dev->name);
180
f98e36f1 181 while (mp->rx_desc_count < (mp->rx_ring_size - 5)) {
b44cd572 182 skb = dev_alloc_skb(RX_SKB_SIZE + DMA_ALIGN);
1da177e4
LT		 183 if (!skb)
184 break;
f98e36f1 185 mp->rx_desc_count++;
b44cd572
DF		 186 unaligned = (u32)skb->data & (DMA_ALIGN - 1);
187 if (unaligned)
188 skb_reserve(skb, DMA_ALIGN - unaligned);
1da177e4
LT		 189 pkt_info.cmd_sts = ETH_RX_ENABLE_INTERRUPT;
190 pkt_info.byte_cnt = RX_SKB_SIZE;
191 pkt_info.buf_ptr = dma_map_single(NULL, skb->data, RX_SKB_SIZE,
192 DMA_FROM_DEVICE);
193 pkt_info.return_info = skb;
194 if (eth_rx_return_buff(mp, &pkt_info) != ETH_OK) {
195 printk(KERN_ERR
196 "%s: Error allocating RX Ring\n", dev->name);
197 break;
198 }
b44cd572 199 skb_reserve(skb, HW_IP_ALIGN);
1da177e4
LT		 200 }
201 clear_bit(0, &mp->rx_task_busy);
202 /*
203 * If RX ring is empty of SKB, set a timer to try allocating
204 * again in a later time .
205 */
f98e36f1 206 if ((mp->rx_desc_count == 0) && (mp->rx_timer_flag == 0)) {
1da177e4
LT		 207 printk(KERN_INFO "%s: Rx ring is empty\n", dev->name);
208 /* After 100mSec */
209 mp->timeout.expires = jiffies + (HZ / 10);
210 add_timer(&mp->timeout);
211 mp->rx_timer_flag = 1;
212 }
213#ifdef MV643XX_RX_QUEUE_FILL_ON_TASK
214 else {
215 /* Return interrupts */
216 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(mp->port_num),
c2e5b352 217 INT_UNMASK_ALL);
1da177e4
LT		 218 }
219#endif
220}
221
222/*
223 * mv643xx_eth_rx_task_timer_wrapper
224 *
225 * Timer routine to wake up RX queue filling task. This function is
226 * used only in case the RX queue is empty, and all alloc_skb has
227 * failed (due to out of memory event).
228 *
229 * Input : pointer to ethernet interface network device structure
230 * Output : N/A
231 */
232static void mv643xx_eth_rx_task_timer_wrapper(unsigned long data)
233{
234 struct net_device *dev = (struct net_device *)data;
235 struct mv643xx_private *mp = netdev_priv(dev);
236
237 mp->rx_timer_flag = 0;
238 mv643xx_eth_rx_task((void *)data);
239}
240
241/*
242 * mv643xx_eth_update_mac_address
243 *
244 * Update the MAC address of the port in the address table
245 *
246 * Input : pointer to ethernet interface network device structure
247 * Output : N/A
248 */
249static void mv643xx_eth_update_mac_address(struct net_device *dev)
250{
251 struct mv643xx_private *mp = netdev_priv(dev);
252 unsigned int port_num = mp->port_num;
253
254 eth_port_init_mac_tables(port_num);
ed9b5d45 255 eth_port_uc_addr_set(port_num, dev->dev_addr);
1da177e4
LT		 256}
257
258/*
259 * mv643xx_eth_set_rx_mode
260 *
261 * Change from promiscuos to regular rx mode
262 *
263 * Input : pointer to ethernet interface network device structure
264 * Output : N/A
265 */
266static void mv643xx_eth_set_rx_mode(struct net_device *dev)
267{
268 struct mv643xx_private *mp = netdev_priv(dev);
01999873 269 u32 config_reg;
1da177e4 270
01999873 271 config_reg = mv_read(MV643XX_ETH_PORT_CONFIG_REG(mp->port_num));
1da177e4 272 if (dev->flags & IFF_PROMISC)
01999873 273 config_reg |= (u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE;
1da177e4 274 else
01999873
DF		 275 config_reg &= ~(u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE;
276 mv_write(MV643XX_ETH_PORT_CONFIG_REG(mp->port_num), config_reg);
16e03018
DF		 277
278 eth_port_set_multicast_list(dev);
1da177e4
LT		 279}
280
281/*
282 * mv643xx_eth_set_mac_address
283 *
284 * Change the interface's mac address.
285 * No special hardware thing should be done because interface is always
286 * put in promiscuous mode.
287 *
288 * Input : pointer to ethernet interface network device structure and
289 * a pointer to the designated entry to be added to the cache.
290 * Output : zero upon success, negative upon failure
291 */
292static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
293{
294 int i;
295
296 for (i = 0; i < 6; i++)
297 /* +2 is for the offset of the HW addr type */
298 dev->dev_addr[i] = ((unsigned char *)addr)[i + 2];
299 mv643xx_eth_update_mac_address(dev);
300 return 0;
301}
302
303/*
304 * mv643xx_eth_tx_timeout
305 *
306 * Called upon a timeout on transmitting a packet
307 *
308 * Input : pointer to ethernet interface network device structure.
309 * Output : N/A
310 */
311static void mv643xx_eth_tx_timeout(struct net_device *dev)
312{
313 struct mv643xx_private *mp = netdev_priv(dev);
314
315 printk(KERN_INFO "%s: TX timeout ", dev->name);
316
317 /* Do the reset outside of interrupt context */
318 schedule_work(&mp->tx_timeout_task);
319}
320
321/*
322 * mv643xx_eth_tx_timeout_task
323 *
324 * Actual routine to reset the adapter when a timeout on Tx has occurred
325 */
326static void mv643xx_eth_tx_timeout_task(struct net_device *dev)
327{
328 struct mv643xx_private *mp = netdev_priv(dev);
329
330 netif_device_detach(dev);
331 eth_port_reset(mp->port_num);
ed9b5d45 332 eth_port_start(dev);
1da177e4
LT		 333 netif_device_attach(dev);
334}
335
336/*
337 * mv643xx_eth_free_tx_queue
338 *
339 * Input : dev - a pointer to the required interface
340 *
341 * Output : 0 if was able to release skb , nonzero otherwise
342 */
343static int mv643xx_eth_free_tx_queue(struct net_device *dev,
344 unsigned int eth_int_cause_ext)
345{
346 struct mv643xx_private *mp = netdev_priv(dev);
347 struct net_device_stats *stats = &mp->stats;
348 struct pkt_info pkt_info;
349 int released = 1;
350
351 if (!(eth_int_cause_ext & (BIT0 | BIT8)))
352 return released;
353
1da177e4
LT		 354 /* Check only queue 0 */
355 while (eth_tx_return_desc(mp, &pkt_info) == ETH_OK) {
356 if (pkt_info.cmd_sts & BIT0) {
357 printk("%s: Error in TX\n", dev->name);
358 stats->tx_errors++;
359 }
360
cb415d30
PG		 361 if (pkt_info.cmd_sts & ETH_TX_FIRST_DESC)
362 dma_unmap_single(NULL, pkt_info.buf_ptr,
363 pkt_info.byte_cnt,
364 DMA_TO_DEVICE);
365 else
366 dma_unmap_page(NULL, pkt_info.buf_ptr,
367 pkt_info.byte_cnt,
368 DMA_TO_DEVICE);
1da177e4 369
cb415d30 370 if (pkt_info.return_info) {
1da177e4
LT		 371 dev_kfree_skb_irq(pkt_info.return_info);
372 released = 0;
cb415d30 373 }
1da177e4
LT		 374 }
375
1da177e4
LT		 376 return released;
377}
378
379/*
380 * mv643xx_eth_receive
381 *
382 * This function is forward packets that are received from the port's
383 * queues toward kernel core or FastRoute them to another interface.
384 *
385 * Input : dev - a pointer to the required interface
386 * max - maximum number to receive (0 means unlimted)
387 *
388 * Output : number of served packets
389 */
390#ifdef MV643XX_NAPI
391static int mv643xx_eth_receive_queue(struct net_device *dev, int budget)
392#else
393static int mv643xx_eth_receive_queue(struct net_device *dev)
394#endif
395{
396 struct mv643xx_private *mp = netdev_priv(dev);
397 struct net_device_stats *stats = &mp->stats;
398 unsigned int received_packets = 0;
399 struct sk_buff *skb;
400 struct pkt_info pkt_info;
401
402#ifdef MV643XX_NAPI
b1dd9ca1 403 while (budget-- > 0 && eth_port_receive(mp, &pkt_info) == ETH_OK) {
1da177e4
LT		 404#else
405 while (eth_port_receive(mp, &pkt_info) == ETH_OK) {
406#endif
f98e36f1 407 mp->rx_desc_count--;
1da177e4 408 received_packets++;
b1dd9ca1 409
1da177e4
LT		 410 /* Update statistics. Note byte count includes 4 byte CRC count */
411 stats->rx_packets++;
412 stats->rx_bytes += pkt_info.byte_cnt;
413 skb = pkt_info.return_info;
414 /*
415 * In case received a packet without first / last bits on OR
416 * the error summary bit is on, the packets needs to be dropeed.
417 */
418 if (((pkt_info.cmd_sts
419 & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
420 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
421 || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
422 stats->rx_dropped++;
423 if ((pkt_info.cmd_sts & (ETH_RX_FIRST_DESC |
424 ETH_RX_LAST_DESC)) !=
425 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) {
426 if (net_ratelimit())
427 printk(KERN_ERR
428 "%s: Received packet spread "
429 "on multiple descriptors\n",
430 dev->name);
431 }
432 if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)
433 stats->rx_errors++;
434
435 dev_kfree_skb_irq(skb);
436 } else {
437 /*
438 * The -4 is for the CRC in the trailer of the
439 * received packet
440 */
441 skb_put(skb, pkt_info.byte_cnt - 4);
442 skb->dev = dev;
443
444 if (pkt_info.cmd_sts & ETH_LAYER_4_CHECKSUM_OK) {
445 skb->ip_summed = CHECKSUM_UNNECESSARY;
446 skb->csum = htons(
447 (pkt_info.cmd_sts & 0x0007fff8) >> 3);
448 }
449 skb->protocol = eth_type_trans(skb, dev);
450#ifdef MV643XX_NAPI
451 netif_receive_skb(skb);
452#else
453 netif_rx(skb);
454#endif
455 }
12ad74f8 456 dev->last_rx = jiffies;
1da177e4
LT		 457 }
458
459 return received_packets;
460}
461
d0412d96
JC		 462/* Set the mv643xx port configuration register for the speed/duplex mode. */
463static void mv643xx_eth_update_pscr(struct net_device *dev,
464 struct ethtool_cmd *ecmd)
465{
466 struct mv643xx_private *mp = netdev_priv(dev);
467 int port_num = mp->port_num;
468 u32 o_pscr, n_pscr;
12a87c64 469 unsigned int queues;
d0412d96
JC		 470
471 o_pscr = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
472 n_pscr = o_pscr;
473
474 /* clear speed, duplex and rx buffer size fields */
475 n_pscr &= ~(MV643XX_ETH_SET_MII_SPEED_TO_100 |
476 MV643XX_ETH_SET_GMII_SPEED_TO_1000 |
477 MV643XX_ETH_SET_FULL_DUPLEX_MODE |
478 MV643XX_ETH_MAX_RX_PACKET_MASK);
479
480 if (ecmd->duplex == DUPLEX_FULL)
481 n_pscr |= MV643XX_ETH_SET_FULL_DUPLEX_MODE;
482
483 if (ecmd->speed == SPEED_1000)
484 n_pscr |= MV643XX_ETH_SET_GMII_SPEED_TO_1000 |
485 MV643XX_ETH_MAX_RX_PACKET_9700BYTE;
486 else {
487 if (ecmd->speed == SPEED_100)
488 n_pscr |= MV643XX_ETH_SET_MII_SPEED_TO_100;
489 n_pscr |= MV643XX_ETH_MAX_RX_PACKET_1522BYTE;
490 }
491
492 if (n_pscr != o_pscr) {
493 if ((o_pscr & MV643XX_ETH_SERIAL_PORT_ENABLE) == 0)
494 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
495 n_pscr);
496 else {
12a87c64 497 queues = mv643xx_eth_port_disable_tx(port_num);
d0412d96
JC		 498
499 o_pscr &= ~MV643XX_ETH_SERIAL_PORT_ENABLE;
500 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
501 o_pscr);
502 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
503 n_pscr);
504 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
505 n_pscr);
12a87c64
DF		 506 if (queues)
507 mv643xx_eth_port_enable_tx(port_num, queues);
d0412d96
JC		 508 }
509 }
510}
511
1da177e4
LT		 512/*
513 * mv643xx_eth_int_handler
514 *
515 * Main interrupt handler for the gigbit ethernet ports
516 *
517 * Input : irq - irq number (not used)
518 * dev_id - a pointer to the required interface's data structure
519 * regs - not used
520 * Output : N/A
521 */
522
523static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id,
b4de9051 524 struct pt_regs *regs)
1da177e4
LT		 525{
526 struct net_device *dev = (struct net_device *)dev_id;
527 struct mv643xx_private *mp = netdev_priv(dev);
528 u32 eth_int_cause, eth_int_cause_ext = 0;
529 unsigned int port_num = mp->port_num;
530
531 /* Read interrupt cause registers */
532 eth_int_cause = mv_read(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num)) &
c2e5b352 533 INT_UNMASK_ALL;
1da177e4
LT		 534
535 if (eth_int_cause & BIT1)
536 eth_int_cause_ext = mv_read(
537 MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num)) &
c2e5b352 538 INT_UNMASK_ALL_EXT;
1da177e4
LT		 539
540#ifdef MV643XX_NAPI
541 if (!(eth_int_cause & 0x0007fffd)) {
542 /* Dont ack the Rx interrupt */
543#endif
544 /*
545 * Clear specific ethernet port intrerrupt registers by
546 * acknowleding relevant bits.
547 */
548 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num),
549 ~eth_int_cause);
550 if (eth_int_cause_ext != 0x0)
551 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG
552 (port_num), ~eth_int_cause_ext);
553
554 /* UDP change : We may need this */
555 if ((eth_int_cause_ext & 0x0000ffff) &&
556 (mv643xx_eth_free_tx_queue(dev, eth_int_cause_ext) == 0) &&
c8aaea25 557 (mp->tx_ring_size - mp->tx_desc_count > MAX_DESCS_PER_SKB))
1da177e4
LT		 558 netif_wake_queue(dev);
559#ifdef MV643XX_NAPI
560 } else {
561 if (netif_rx_schedule_prep(dev)) {
562 /* Mask all the interrupts */
c2e5b352
DF		 563 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
564 INT_MASK_ALL);
565 /* wait for previous write to complete */
566 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
1da177e4
LT		 567 __netif_rx_schedule(dev);
568 }
569#else
570 if (eth_int_cause & (BIT2 | BIT11))
571 mv643xx_eth_receive_queue(dev, 0);
572
573 /*
574 * After forwarded received packets to upper layer, add a task
575 * in an interrupts enabled context that refills the RX ring
576 * with skb's.
577 */
578#ifdef MV643XX_RX_QUEUE_FILL_ON_TASK
c2e5b352 579 /* Mask all interrupts on ethernet port */
1da177e4 580 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
c2e5b352 581 INT_MASK_ALL);
8f518703
DF		 582 /* wait for previous write to take effect */
583 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
584
1da177e4
LT		 585 queue_task(&mp->rx_task, &tq_immediate);
586 mark_bh(IMMEDIATE_BH);
587#else
588 mp->rx_task.func(dev);
589#endif
590#endif
591 }
592 /* PHY status changed */
593 if (eth_int_cause_ext & (BIT16 | BIT20)) {
d0412d96
JC		 594 struct ethtool_cmd cmd;
595
c28a4f89 596 if (mii_link_ok(&mp->mii)) {
d0412d96
JC		 597 mii_ethtool_gset(&mp->mii, &cmd);
598 mv643xx_eth_update_pscr(dev, &cmd);
c28a4f89
JC		 599 if (!netif_carrier_ok(dev)) {
600 netif_carrier_on(dev);
c8aaea25 601 if (mp->tx_ring_size - mp->tx_desc_count >
d0412d96
JC		 602 MAX_DESCS_PER_SKB) {
603 netif_wake_queue(dev);
604 /* Start TX queue */
605 mv643xx_eth_port_enable_tx(port_num, mp->port_tx_queue_command);
606 }
c28a4f89
JC		 607 }
608 } else if (netif_carrier_ok(dev)) {
1da177e4 609 netif_stop_queue(dev);
c28a4f89 610 netif_carrier_off(dev);
1da177e4
LT		 611 }
612 }
613
614 /*
615 * If no real interrupt occured, exit.
616 * This can happen when using gigE interrupt coalescing mechanism.
617 */
618 if ((eth_int_cause == 0x0) && (eth_int_cause_ext == 0x0))
619 return IRQ_NONE;
620
621 return IRQ_HANDLED;
622}
623
624#ifdef MV643XX_COAL
625
626/*
627 * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
628 *
629 * DESCRIPTION:
630 * This routine sets the RX coalescing interrupt mechanism parameter.
631 * This parameter is a timeout counter, that counts in 64 t_clk
632 * chunks ; that when timeout event occurs a maskable interrupt
633 * occurs.
634 * The parameter is calculated using the tClk of the MV-643xx chip
635 * , and the required delay of the interrupt in usec.
636 *
637 * INPUT:
638 * unsigned int eth_port_num Ethernet port number
639 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
640 * unsigned int delay Delay in usec
641 *
642 * OUTPUT:
643 * Interrupt coalescing mechanism value is set in MV-643xx chip.
644 *
645 * RETURN:
646 * The interrupt coalescing value set in the gigE port.
647 *
648 */
649static unsigned int eth_port_set_rx_coal(unsigned int eth_port_num,
650 unsigned int t_clk, unsigned int delay)
651{
652 unsigned int coal = ((t_clk / 1000000) * delay) / 64;
653
654 /* Set RX Coalescing mechanism */
655 mv_write(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num),
656 ((coal & 0x3fff) << 8) |
657 (mv_read(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num))
658 & 0xffc000ff));
659
660 return coal;
661}
662#endif
663
664/*
665 * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
666 *
667 * DESCRIPTION:
668 * This routine sets the TX coalescing interrupt mechanism parameter.
669 * This parameter is a timeout counter, that counts in 64 t_clk
670 * chunks ; that when timeout event occurs a maskable interrupt
671 * occurs.
672 * The parameter is calculated using the t_cLK frequency of the
673 * MV-643xx chip and the required delay in the interrupt in uSec
674 *
675 * INPUT:
676 * unsigned int eth_port_num Ethernet port number
677 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
678 * unsigned int delay Delay in uSeconds
679 *
680 * OUTPUT:
681 * Interrupt coalescing mechanism value is set in MV-643xx chip.
682 *
683 * RETURN:
684 * The interrupt coalescing value set in the gigE port.
685 *
686 */
687static unsigned int eth_port_set_tx_coal(unsigned int eth_port_num,
688 unsigned int t_clk, unsigned int delay)
689{
690 unsigned int coal;
691 coal = ((t_clk / 1000000) * delay) / 64;
692 /* Set TX Coalescing mechanism */
693 mv_write(MV643XX_ETH_TX_FIFO_URGENT_THRESHOLD_REG(eth_port_num),
694 coal << 4);
695 return coal;
696}
697
1da177e4
LT		 698/*
699 * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
700 *
701 * DESCRIPTION:
702 * This function prepares a Rx chained list of descriptors and packet
703 * buffers in a form of a ring. The routine must be called after port
704 * initialization routine and before port start routine.
705 * The Ethernet SDMA engine uses CPU bus addresses to access the various
706 * devices in the system (i.e. DRAM). This function uses the ethernet
707 * struct 'virtual to physical' routine (set by the user) to set the ring
708 * with physical addresses.
709 *
710 * INPUT:
711 * struct mv643xx_private *mp Ethernet Port Control srtuct.
712 *
713 * OUTPUT:
714 * The routine updates the Ethernet port control struct with information
715 * regarding the Rx descriptors and buffers.
716 *
717 * RETURN:
718 * None.
719 */
720static void ether_init_rx_desc_ring(struct mv643xx_private *mp)
721{
722 volatile struct eth_rx_desc *p_rx_desc;
723 int rx_desc_num = mp->rx_ring_size;
724 int i;
725
726 /* initialize the next_desc_ptr links in the Rx descriptors ring */
727 p_rx_desc = (struct eth_rx_desc *)mp->p_rx_desc_area;
728 for (i = 0; i < rx_desc_num; i++) {
729 p_rx_desc[i].next_desc_ptr = mp->rx_desc_dma +
730 ((i + 1) % rx_desc_num) * sizeof(struct eth_rx_desc);
731 }
732
733 /* Save Rx desc pointer to driver struct. */
734 mp->rx_curr_desc_q = 0;
735 mp->rx_used_desc_q = 0;
736
737 mp->rx_desc_area_size = rx_desc_num * sizeof(struct eth_rx_desc);
738
9f8dd319
DF		 739 /* Enable queue 0 for this port */
740 mp->port_rx_queue_command = 1;
1da177e4
LT		 741}
742
743/*
744 * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
745 *
746 * DESCRIPTION:
747 * This function prepares a Tx chained list of descriptors and packet
748 * buffers in a form of a ring. The routine must be called after port
749 * initialization routine and before port start routine.
750 * The Ethernet SDMA engine uses CPU bus addresses to access the various
751 * devices in the system (i.e. DRAM). This function uses the ethernet
752 * struct 'virtual to physical' routine (set by the user) to set the ring
753 * with physical addresses.
754 *
755 * INPUT:
756 * struct mv643xx_private *mp Ethernet Port Control srtuct.
757 *
758 * OUTPUT:
759 * The routine updates the Ethernet port control struct with information
760 * regarding the Tx descriptors and buffers.
761 *
762 * RETURN:
763 * None.
764 */
765static void ether_init_tx_desc_ring(struct mv643xx_private *mp)
766{
767 int tx_desc_num = mp->tx_ring_size;
768 struct eth_tx_desc *p_tx_desc;
769 int i;
770
771 /* Initialize the next_desc_ptr links in the Tx descriptors ring */
772 p_tx_desc = (struct eth_tx_desc *)mp->p_tx_desc_area;
773 for (i = 0; i < tx_desc_num; i++) {
774 p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma +
775 ((i + 1) % tx_desc_num) * sizeof(struct eth_tx_desc);
776 }
777
778 mp->tx_curr_desc_q = 0;
779 mp->tx_used_desc_q = 0;
1da177e4
LT		 780
781 mp->tx_desc_area_size = tx_desc_num * sizeof(struct eth_tx_desc);
782
9f8dd319
DF		 783 /* Enable queue 0 for this port */
784 mp->port_tx_queue_command = 1;
1da177e4
LT		 785}
786
d0412d96
JC		 787static int mv643xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
788{
789 struct mv643xx_private *mp = netdev_priv(dev);
790 int err;
791
792 spin_lock_irq(&mp->lock);
793 err = mii_ethtool_sset(&mp->mii, cmd);
794 spin_unlock_irq(&mp->lock);
795
796 return err;
797}
798
799static int mv643xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
800{
801 struct mv643xx_private *mp = netdev_priv(dev);
802 int err;
803
804 spin_lock_irq(&mp->lock);
805 err = mii_ethtool_gset(&mp->mii, cmd);
806 spin_unlock_irq(&mp->lock);
807
808 /* The PHY may support 1000baseT_Half, but the mv643xx does not */
809 cmd->supported &= ~SUPPORTED_1000baseT_Half;
810 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
811
812 return err;
813}
814
ab4384a6
DF		 815/*
816 * mv643xx_eth_open
817 *
818 * This function is called when openning the network device. The function
819 * should initialize all the hardware, initialize cyclic Rx/Tx
820 * descriptors chain and buffers and allocate an IRQ to the network
821 * device.
822 *
823 * Input : a pointer to the network device structure
824 *
825 * Output : zero of success , nonzero if fails.
826 */
827
828static int mv643xx_eth_open(struct net_device *dev)
1da177e4
LT		 829{
830 struct mv643xx_private *mp = netdev_priv(dev);
831 unsigned int port_num = mp->port_num;
832 unsigned int size;
ab4384a6
DF		 833 int err;
834
835 err = request_irq(dev->irq, mv643xx_eth_int_handler,
836 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
837 if (err) {
838 printk(KERN_ERR "Can not assign IRQ number to MV643XX_eth%d\n",
839 port_num);
840 return -EAGAIN;
841 }
1da177e4 842
1da177e4
LT		 843 eth_port_init(mp);
844
845 INIT_WORK(&mp->rx_task, (void (*)(void *))mv643xx_eth_rx_task, dev);
846
847 memset(&mp->timeout, 0, sizeof(struct timer_list));
848 mp->timeout.function = mv643xx_eth_rx_task_timer_wrapper;
849 mp->timeout.data = (unsigned long)dev;
850
851 mp->rx_task_busy = 0;
852 mp->rx_timer_flag = 0;
853
854 /* Allocate RX and TX skb rings */
855 mp->rx_skb = kmalloc(sizeof(*mp->rx_skb) * mp->rx_ring_size,
856 GFP_KERNEL);
857 if (!mp->rx_skb) {
858 printk(KERN_ERR "%s: Cannot allocate Rx skb ring\n", dev->name);
ab4384a6
DF		 859 err = -ENOMEM;
860 goto out_free_irq;
1da177e4
LT		 861 }
862 mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size,
863 GFP_KERNEL);
864 if (!mp->tx_skb) {
865 printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name);
ab4384a6
DF		 866 err = -ENOMEM;
867 goto out_free_rx_skb;
1da177e4
LT		 868 }
869
870 /* Allocate TX ring */
f98e36f1 871 mp->tx_desc_count = 0;
1da177e4
LT		 872 size = mp->tx_ring_size * sizeof(struct eth_tx_desc);
873 mp->tx_desc_area_size = size;
874
875 if (mp->tx_sram_size) {
876 mp->p_tx_desc_area = ioremap(mp->tx_sram_addr,
877 mp->tx_sram_size);
878 mp->tx_desc_dma = mp->tx_sram_addr;
879 } else
880 mp->p_tx_desc_area = dma_alloc_coherent(NULL, size,
881 &mp->tx_desc_dma,
882 GFP_KERNEL);
883
884 if (!mp->p_tx_desc_area) {
885 printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n",
886 dev->name, size);
ab4384a6
DF		 887 err = -ENOMEM;
888 goto out_free_tx_skb;
1da177e4
LT		 889 }
890 BUG_ON((u32) mp->p_tx_desc_area & 0xf); /* check 16-byte alignment */
891 memset((void *)mp->p_tx_desc_area, 0, mp->tx_desc_area_size);
892
893 ether_init_tx_desc_ring(mp);
894
895 /* Allocate RX ring */
f98e36f1 896 mp->rx_desc_count = 0;
1da177e4
LT		 897 size = mp->rx_ring_size * sizeof(struct eth_rx_desc);
898 mp->rx_desc_area_size = size;
899
900 if (mp->rx_sram_size) {
901 mp->p_rx_desc_area = ioremap(mp->rx_sram_addr,
902 mp->rx_sram_size);
903 mp->rx_desc_dma = mp->rx_sram_addr;
904 } else
905 mp->p_rx_desc_area = dma_alloc_coherent(NULL, size,
906 &mp->rx_desc_dma,
907 GFP_KERNEL);
908
909 if (!mp->p_rx_desc_area) {
910 printk(KERN_ERR "%s: Cannot allocate Rx ring (size %d bytes)\n",
911 dev->name, size);
912 printk(KERN_ERR "%s: Freeing previously allocated TX queues...",
913 dev->name);
914 if (mp->rx_sram_size)
dd09b1de 915 iounmap(mp->p_tx_desc_area);
1da177e4
LT		 916 else
917 dma_free_coherent(NULL, mp->tx_desc_area_size,
918 mp->p_tx_desc_area, mp->tx_desc_dma);
ab4384a6
DF		 919 err = -ENOMEM;
920 goto out_free_tx_skb;
1da177e4
LT		 921 }
922 memset((void *)mp->p_rx_desc_area, 0, size);
923
924 ether_init_rx_desc_ring(mp);
925
926 mv643xx_eth_rx_task(dev); /* Fill RX ring with skb's */
927
d0412d96
JC		 928 /* Clear any pending ethernet port interrupts */
929 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
930 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
931
ed9b5d45 932 eth_port_start(dev);
1da177e4
LT		 933
934 /* Interrupt Coalescing */
935
936#ifdef MV643XX_COAL
937 mp->rx_int_coal =
938 eth_port_set_rx_coal(port_num, 133000000, MV643XX_RX_COAL);
939#endif
940
941 mp->tx_int_coal =
942 eth_port_set_tx_coal(port_num, 133000000, MV643XX_TX_COAL);
943
8f518703
DF		 944 /* Unmask phy and link status changes interrupts */
945 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
c2e5b352 946 INT_UNMASK_ALL_EXT);
1da177e4 947
8f518703 948 /* Unmask RX buffer and TX end interrupt */
c2e5b352 949 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), INT_UNMASK_ALL);
d0412d96 950
1da177e4 951 return 0;
ab4384a6
DF		 952
953out_free_tx_skb:
954 kfree(mp->tx_skb);
955out_free_rx_skb:
956 kfree(mp->rx_skb);
957out_free_irq:
958 free_irq(dev->irq, dev);
959
960 return err;
1da177e4
LT		 961}
962
963static void mv643xx_eth_free_tx_rings(struct net_device *dev)
964{
965 struct mv643xx_private *mp = netdev_priv(dev);
966 unsigned int port_num = mp->port_num;
967 unsigned int curr;
4476e0e4 968 struct sk_buff *skb;
1da177e4
LT		 969
970 /* Stop Tx Queues */
9f8dd319 971 mv643xx_eth_port_disable_tx(port_num);
1da177e4
LT		 972
973 /* Free outstanding skb's on TX rings */
f98e36f1 974 for (curr = 0; mp->tx_desc_count && curr < mp->tx_ring_size; curr++) {
4476e0e4
DF		 975 skb = mp->tx_skb[curr];
976 if (skb) {
f98e36f1 977 mp->tx_desc_count -= skb_shinfo(skb)->nr_frags;
4476e0e4 978 dev_kfree_skb(skb);
f98e36f1 979 mp->tx_desc_count--;
1da177e4
LT		 980 }
981 }
f98e36f1 982 if (mp->tx_desc_count)
1da177e4 983 printk("%s: Error on Tx descriptor free - could not free %d"
f98e36f1 984 " descriptors\n", dev->name, mp->tx_desc_count);
1da177e4
LT		 985
986 /* Free TX ring */
987 if (mp->tx_sram_size)
988 iounmap(mp->p_tx_desc_area);
989 else
990 dma_free_coherent(NULL, mp->tx_desc_area_size,
991 mp->p_tx_desc_area, mp->tx_desc_dma);
992}
993
994static void mv643xx_eth_free_rx_rings(struct net_device *dev)
995{
996 struct mv643xx_private *mp = netdev_priv(dev);
997 unsigned int port_num = mp->port_num;
998 int curr;
999
1000 /* Stop RX Queues */
9f8dd319 1001 mv643xx_eth_port_disable_rx(port_num);
1da177e4
LT		 1002
1003 /* Free preallocated skb's on RX rings */
f98e36f1 1004 for (curr = 0; mp->rx_desc_count && curr < mp->rx_ring_size; curr++) {
1da177e4
LT		 1005 if (mp->rx_skb[curr]) {
1006 dev_kfree_skb(mp->rx_skb[curr]);
f98e36f1 1007 mp->rx_desc_count--;
1da177e4
LT		 1008 }
1009 }
1010
f98e36f1 1011 if (mp->rx_desc_count)
1da177e4
LT		 1012 printk(KERN_ERR
1013 "%s: Error in freeing Rx Ring. %d skb's still"
1014 " stuck in RX Ring - ignoring them\n", dev->name,
f98e36f1 1015 mp->rx_desc_count);
1da177e4
LT		 1016 /* Free RX ring */
1017 if (mp->rx_sram_size)
1018 iounmap(mp->p_rx_desc_area);
1019 else
1020 dma_free_coherent(NULL, mp->rx_desc_area_size,
1021 mp->p_rx_desc_area, mp->rx_desc_dma);
1022}
1023
1024/*
1025 * mv643xx_eth_stop
1026 *
1027 * This function is used when closing the network device.
1028 * It updates the hardware,
1029 * release all memory that holds buffers and descriptors and release the IRQ.
1030 * Input : a pointer to the device structure
1031 * Output : zero if success , nonzero if fails
1032 */
1033
ab4384a6 1034static int mv643xx_eth_stop(struct net_device *dev)
1da177e4
LT		 1035{
1036 struct mv643xx_private *mp = netdev_priv(dev);
1037 unsigned int port_num = mp->port_num;
1038
c2e5b352
DF		 1039 /* Mask all interrupts on ethernet port */
1040 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), INT_MASK_ALL);
1041 /* wait for previous write to complete */
8f518703
DF		 1042 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
1043
1044#ifdef MV643XX_NAPI
1045 netif_poll_disable(dev);
1046#endif
1da177e4
LT		 1047 netif_carrier_off(dev);
1048 netif_stop_queue(dev);
1049
1da177e4
LT		 1050 eth_port_reset(mp->port_num);
1051
8f518703
DF		 1052 mv643xx_eth_free_tx_rings(dev);
1053 mv643xx_eth_free_rx_rings(dev);
1da177e4 1054
8f518703
DF		 1055#ifdef MV643XX_NAPI
1056 netif_poll_enable(dev);
1057#endif
1da177e4 1058
1da177e4 1059 free_irq(dev->irq, dev);
1da177e4
LT		 1060
1061 return 0;
1062}
1063
1064#ifdef MV643XX_NAPI
1065static void mv643xx_tx(struct net_device *dev)
1066{
1067 struct mv643xx_private *mp = netdev_priv(dev);
1068 struct pkt_info pkt_info;
1069
1070 while (eth_tx_return_desc(mp, &pkt_info) == ETH_OK) {
cb415d30
PG		 1071 if (pkt_info.cmd_sts & ETH_TX_FIRST_DESC)
1072 dma_unmap_single(NULL, pkt_info.buf_ptr,
1073 pkt_info.byte_cnt,
1074 DMA_TO_DEVICE);
1075 else
1076 dma_unmap_page(NULL, pkt_info.buf_ptr,
1077 pkt_info.byte_cnt,
1078 DMA_TO_DEVICE);
1da177e4 1079
cb415d30 1080 if (pkt_info.return_info)
1da177e4 1081 dev_kfree_skb_irq(pkt_info.return_info);
1da177e4
LT		 1082 }
1083
1084 if (netif_queue_stopped(dev) &&
c8aaea25 1085 mp->tx_ring_size - mp->tx_desc_count > MAX_DESCS_PER_SKB)
1da177e4
LT		 1086 netif_wake_queue(dev);
1087}
1088
1089/*
1090 * mv643xx_poll
1091 *
1092 * This function is used in case of NAPI
1093 */
1094static int mv643xx_poll(struct net_device *dev, int *budget)
1095{
1096 struct mv643xx_private *mp = netdev_priv(dev);
1097 int done = 1, orig_budget, work_done;
1098 unsigned int port_num = mp->port_num;
1da177e4
LT		 1099
1100#ifdef MV643XX_TX_FAST_REFILL
1101 if (++mp->tx_clean_threshold > 5) {
1da177e4
LT		 1102 mv643xx_tx(dev);
1103 mp->tx_clean_threshold = 0;
1da177e4
LT		 1104 }
1105#endif
1106
1107 if ((mv_read(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num)))
1108 != (u32) mp->rx_used_desc_q) {
1109 orig_budget = *budget;
1110 if (orig_budget > dev->quota)
1111 orig_budget = dev->quota;
1112 work_done = mv643xx_eth_receive_queue(dev, orig_budget);
1113 mp->rx_task.func(dev);
1114 *budget -= work_done;
1115 dev->quota -= work_done;
1116 if (work_done >= orig_budget)
1117 done = 0;
1118 }
1119
1120 if (done) {
8f518703 1121 netif_rx_complete(dev);
1da177e4
LT		 1122 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
1123 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
1124 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
c2e5b352 1125 INT_UNMASK_ALL);
1da177e4
LT		 1126 }
1127
1128 return done ? 0 : 1;
1129}
1130#endif
1131
c8aaea25
DF		 1132/**
1133 * has_tiny_unaligned_frags - check if skb has any small, unaligned fragments
1134 *
1135 * Hardware can't handle unaligned fragments smaller than 9 bytes.
f7ea3337
PJ		 1136 * This helper function detects that case.
1137 */
1138
1139static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1140{
b4de9051
DF		 1141 unsigned int frag;
1142 skb_frag_t *fragp;
f7ea3337 1143
b4de9051
DF		 1144 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1145 fragp = &skb_shinfo(skb)->frags[frag];
1146 if (fragp->size <= 8 && fragp->page_offset & 0x7)
1147 return 1;
1148 }
1149 return 0;
f7ea3337
PJ		 1150}
1151
c8aaea25
DF		 1152/**
1153 * eth_alloc_tx_desc_index - return the index of the next available tx desc
1154 */
1155static int eth_alloc_tx_desc_index(struct mv643xx_private *mp)
1156{
1157 int tx_desc_curr;
1158
1159 tx_desc_curr = mp->tx_curr_desc_q;
f7ea3337 1160
c8aaea25
DF		 1161 BUG_ON(mp->tx_desc_count >= mp->tx_ring_size);
1162 mp->tx_desc_count++;
1163
1164 mp->tx_curr_desc_q = (tx_desc_curr + 1) % mp->tx_ring_size;
1165
1166 BUG_ON(mp->tx_curr_desc_q == mp->tx_used_desc_q);
1167
1168 return tx_desc_curr;
1169}
1170
1171/**
1172 * eth_tx_fill_frag_descs - fill tx hw descriptors for an skb's fragments.
1da177e4 1173 *
c8aaea25
DF		 1174 * Ensure the data for each fragment to be transmitted is mapped properly,
1175 * then fill in descriptors in the tx hw queue.
1da177e4 1176 */
c8aaea25
DF		 1177static void eth_tx_fill_frag_descs(struct mv643xx_private *mp,
1178 struct sk_buff *skb)
1da177e4 1179{
c8aaea25
DF		 1180 int frag;
1181 int tx_index;
1182 struct eth_tx_desc *desc;
1da177e4 1183 struct net_device_stats *stats = &mp->stats;
1da177e4 1184
c8aaea25
DF		 1185 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1186 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
1187
1188 tx_index = eth_alloc_tx_desc_index(mp);
1189 desc = &mp->p_tx_desc_area[tx_index];
1190
1191 desc->cmd_sts = ETH_BUFFER_OWNED_BY_DMA;
1192 /* Last Frag enables interrupt and frees the skb */
1193 if (frag == (skb_shinfo(skb)->nr_frags - 1)) {
1194 desc->cmd_sts |= ETH_ZERO_PADDING |
1195 ETH_TX_LAST_DESC |
1196 ETH_TX_ENABLE_INTERRUPT;
1197 mp->tx_skb[tx_index] = skb;
1198 } else
1199 mp->tx_skb[tx_index] = 0;
1200
1201 desc = &mp->p_tx_desc_area[tx_index];
1202 desc->l4i_chk = 0;
1203 desc->byte_cnt = this_frag->size;
1204 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
1205 this_frag->page_offset,
1206 this_frag->size,
1207 DMA_TO_DEVICE);
1208 stats->tx_bytes += this_frag->size;
1da177e4 1209 }
c8aaea25 1210}
1da177e4 1211
c8aaea25
DF		 1212/**
1213 * eth_tx_submit_descs_for_skb - submit data from an skb to the tx hw
1214 *
1215 * Ensure the data for an skb to be transmitted is mapped properly,
1216 * then fill in descriptors in the tx hw queue and start the hardware.
1217 */
1218static int eth_tx_submit_descs_for_skb(struct mv643xx_private *mp,
1219 struct sk_buff *skb)
1220{
1221 int tx_index;
1222 struct eth_tx_desc *desc;
1223 u32 cmd_sts;
1224 int length;
1225 int tx_bytes = 0;
1da177e4 1226
c8aaea25 1227 cmd_sts = ETH_TX_FIRST_DESC | ETH_GEN_CRC | ETH_BUFFER_OWNED_BY_DMA;
1da177e4 1228
c8aaea25
DF		 1229 tx_index = eth_alloc_tx_desc_index(mp);
1230 desc = &mp->p_tx_desc_area[tx_index];
1231
1232 if (skb_shinfo(skb)->nr_frags) {
1233 eth_tx_fill_frag_descs(mp, skb);
1234
1235 length = skb_headlen(skb);
1236 mp->tx_skb[tx_index] = 0;
1237 } else {
1238 cmd_sts |= ETH_ZERO_PADDING |
1239 ETH_TX_LAST_DESC |
1240 ETH_TX_ENABLE_INTERRUPT;
1241 length = skb->len;
1242 mp->tx_skb[tx_index] = skb;
f7ea3337
PJ		 1243 }
1244
c8aaea25
DF		 1245 desc->byte_cnt = length;
1246 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
1247 tx_bytes += length;
1da177e4 1248
c8aaea25
DF		 1249 if (skb->ip_summed == CHECKSUM_HW) {
1250 BUG_ON(skb->protocol != ETH_P_IP);
1251
1252 cmd_sts |= ETH_GEN_TCP_UDP_CHECKSUM |
1253 ETH_GEN_IP_V_4_CHECKSUM |
1254 skb->nh.iph->ihl << ETH_TX_IHL_SHIFT;
1255
1256 switch (skb->nh.iph->protocol) {
1257 case IPPROTO_UDP:
1258 cmd_sts |= ETH_UDP_FRAME;
1259 desc->l4i_chk = skb->h.uh->check;
1260 break;
1261 case IPPROTO_TCP:
1262 desc->l4i_chk = skb->h.th->check;
1263 break;
1264 default:
1265 BUG();
1da177e4 1266 }
1da177e4 1267 } else {
c8aaea25
DF		 1268 /* Errata BTS #50, IHL must be 5 if no HW checksum */
1269 cmd_sts |= 5 << ETH_TX_IHL_SHIFT;
1270 desc->l4i_chk = 0;
1271 }
1da177e4 1272
c8aaea25
DF		 1273 /* ensure all other descriptors are written before first cmd_sts */
1274 wmb();
1275 desc->cmd_sts = cmd_sts;
1da177e4 1276
c8aaea25
DF		 1277 /* ensure all descriptors are written before poking hardware */
1278 wmb();
1279 mv643xx_eth_port_enable_tx(mp->port_num, mp->port_tx_queue_command);
1da177e4 1280
c8aaea25
DF		 1281 return tx_bytes;
1282}
1da177e4 1283
c8aaea25
DF		 1284/**
1285 * mv643xx_eth_start_xmit - queue an skb to the hardware for transmission
1286 *
1287 */
1288static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
1289{
1290 struct mv643xx_private *mp = netdev_priv(dev);
1291 struct net_device_stats *stats = &mp->stats;
1292 unsigned long flags;
1da177e4 1293
c8aaea25
DF		 1294 BUG_ON(netif_queue_stopped(dev));
1295 BUG_ON(skb == NULL);
1296 BUG_ON(mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB);
1da177e4 1297
c8aaea25
DF		 1298 if (has_tiny_unaligned_frags(skb)) {
1299 if ((skb_linearize(skb, GFP_ATOMIC) != 0)) {
1300 stats->tx_dropped++;
1301 printk(KERN_DEBUG "%s: failed to linearize tiny "
1302 "unaligned fragment\n", dev->name);
1303 return 1;
1da177e4
LT		 1304 }
1305 }
f7ea3337 1306
c8aaea25 1307 spin_lock_irqsave(&mp->lock, flags);
1da177e4 1308
c8aaea25 1309 stats->tx_bytes = eth_tx_submit_descs_for_skb(mp, skb);
1da177e4
LT		 1310 stats->tx_packets++;
1311 dev->trans_start = jiffies;
1312
c8aaea25
DF		 1313 if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB)
1314 netif_stop_queue(dev);
1315
1da177e4
LT		 1316 spin_unlock_irqrestore(&mp->lock, flags);
1317
1318 return 0; /* success */
1319}
1320
1321/*
1322 * mv643xx_eth_get_stats
1323 *
1324 * Returns a pointer to the interface statistics.
1325 *
1326 * Input : dev - a pointer to the required interface
1327 *
1328 * Output : a pointer to the interface's statistics
1329 */
1330
1331static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1332{
1333 struct mv643xx_private *mp = netdev_priv(dev);
1334
1335 return &mp->stats;
1336}
1337
63c9e549 1338#ifdef CONFIG_NET_POLL_CONTROLLER
63c9e549
DF		 1339static void mv643xx_netpoll(struct net_device *netdev)
1340{
1341 struct mv643xx_private *mp = netdev_priv(netdev);
c2e5b352
DF		 1342 int port_num = mp->port_num;
1343
1344 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), INT_MASK_ALL);
1345 /* wait for previous write to complete */
1346 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
63c9e549 1347
63c9e549 1348 mv643xx_eth_int_handler(netdev->irq, netdev, NULL);
c2e5b352
DF		 1349
1350 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), INT_UNMASK_ALL);
63c9e549
DF		 1351}
1352#endif
1353
d0412d96
JC		 1354static void mv643xx_init_ethtool_cmd(struct net_device *dev, int phy_address,
1355 int speed, int duplex,
1356 struct ethtool_cmd *cmd)
1357{
1358 struct mv643xx_private *mp = netdev_priv(dev);
1359
1360 memset(cmd, 0, sizeof(*cmd));
1361
1362 cmd->port = PORT_MII;
1363 cmd->transceiver = XCVR_INTERNAL;
1364 cmd->phy_address = phy_address;
1365
1366 if (speed == 0) {
1367 cmd->autoneg = AUTONEG_ENABLE;
1368 /* mii lib checks, but doesn't use speed on AUTONEG_ENABLE */
1369 cmd->speed = SPEED_100;
1370 cmd->advertising = ADVERTISED_10baseT_Half |
1371 ADVERTISED_10baseT_Full |
1372 ADVERTISED_100baseT_Half |
1373 ADVERTISED_100baseT_Full;
1374 if (mp->mii.supports_gmii)
1375 cmd->advertising |= ADVERTISED_1000baseT_Full;
1376 } else {
1377 cmd->autoneg = AUTONEG_DISABLE;
1378 cmd->speed = speed;
1379 cmd->duplex = duplex;
1380 }
1381}
1382
1da177e4
LT		 1383/*/
1384 * mv643xx_eth_probe
1385 *
1386 * First function called after registering the network device.
1387 * It's purpose is to initialize the device as an ethernet device,
1388 * fill the ethernet device structure with pointers * to functions,
1389 * and set the MAC address of the interface
1390 *
1391 * Input : struct device *
1392 * Output : -ENOMEM if failed , 0 if success
1393 */
3ae5eaec 1394static int mv643xx_eth_probe(struct platform_device *pdev)
1da177e4 1395{
1da177e4
LT		 1396 struct mv643xx_eth_platform_data *pd;
1397 int port_num = pdev->id;
1398 struct mv643xx_private *mp;
1399 struct net_device *dev;
1400 u8 *p;
1401 struct resource *res;
1402 int err;
d0412d96 1403 struct ethtool_cmd cmd;
01999873
DF		 1404 int duplex = DUPLEX_HALF;
1405 int speed = 0; /* default to auto-negotiation */
1da177e4
LT		 1406
1407 dev = alloc_etherdev(sizeof(struct mv643xx_private));
1408 if (!dev)
1409 return -ENOMEM;
1410
3ae5eaec 1411 platform_set_drvdata(pdev, dev);
1da177e4
LT		 1412
1413 mp = netdev_priv(dev);
1414
1415 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1416 BUG_ON(!res);
1417 dev->irq = res->start;
1418
1419 mp->port_num = port_num;
1420
1421 dev->open = mv643xx_eth_open;
1422 dev->stop = mv643xx_eth_stop;
1423 dev->hard_start_xmit = mv643xx_eth_start_xmit;
1424 dev->get_stats = mv643xx_eth_get_stats;
1425 dev->set_mac_address = mv643xx_eth_set_mac_address;
1426 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
1427
1428 /* No need to Tx Timeout */
1429 dev->tx_timeout = mv643xx_eth_tx_timeout;
1430#ifdef MV643XX_NAPI
1431 dev->poll = mv643xx_poll;
1432 dev->weight = 64;
1433#endif
1434
63c9e549
DF		 1435#ifdef CONFIG_NET_POLL_CONTROLLER
1436 dev->poll_controller = mv643xx_netpoll;
1437#endif
1438
1da177e4
LT		 1439 dev->watchdog_timeo = 2 * HZ;
1440 dev->tx_queue_len = mp->tx_ring_size;
1441 dev->base_addr = 0;
1442 dev->change_mtu = mv643xx_eth_change_mtu;
d0412d96 1443 dev->do_ioctl = mv643xx_eth_do_ioctl;
1da177e4
LT		 1444 SET_ETHTOOL_OPS(dev, &mv643xx_ethtool_ops);
1445
1446#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1447#ifdef MAX_SKB_FRAGS
1448 /*
1449 * Zero copy can only work if we use Discovery II memory. Else, we will
1450 * have to map the buffers to ISA memory which is only 16 MB
1451 */
63890576 1452 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
1da177e4
LT		 1453#endif
1454#endif
1455
1456 /* Configure the timeout task */
1457 INIT_WORK(&mp->tx_timeout_task,
1458 (void (*)(void *))mv643xx_eth_tx_timeout_task, dev);
1459
1460 spin_lock_init(&mp->lock);
1461
1462 /* set default config values */
1463 eth_port_uc_addr_get(dev, dev->dev_addr);
1da177e4
LT		 1464 mp->rx_ring_size = MV643XX_ETH_PORT_DEFAULT_RECEIVE_QUEUE_SIZE;
1465 mp->tx_ring_size = MV643XX_ETH_PORT_DEFAULT_TRANSMIT_QUEUE_SIZE;
1466
1467 pd = pdev->dev.platform_data;
1468 if (pd) {
01999873 1469 if (pd->mac_addr)
1da177e4
LT		 1470 memcpy(dev->dev_addr, pd->mac_addr, 6);
1471
1472 if (pd->phy_addr || pd->force_phy_addr)
1473 ethernet_phy_set(port_num, pd->phy_addr);
1474
1da177e4
LT		 1475 if (pd->rx_queue_size)
1476 mp->rx_ring_size = pd->rx_queue_size;
1477
1478 if (pd->tx_queue_size)
1479 mp->tx_ring_size = pd->tx_queue_size;
1480
1481 if (pd->tx_sram_size) {
1482 mp->tx_sram_size = pd->tx_sram_size;
1483 mp->tx_sram_addr = pd->tx_sram_addr;
1484 }
1485
1486 if (pd->rx_sram_size) {
1487 mp->rx_sram_size = pd->rx_sram_size;
1488 mp->rx_sram_addr = pd->rx_sram_addr;
1489 }
01999873
DF		 1490
1491 duplex = pd->duplex;
1492 speed = pd->speed;
1da177e4
LT		 1493 }
1494
c28a4f89
JC		 1495 /* Hook up MII support for ethtool */
1496 mp->mii.dev = dev;
1497 mp->mii.mdio_read = mv643xx_mdio_read;
1498 mp->mii.mdio_write = mv643xx_mdio_write;
1499 mp->mii.phy_id = ethernet_phy_get(port_num);
1500 mp->mii.phy_id_mask = 0x3f;
1501 mp->mii.reg_num_mask = 0x1f;
1502
1da177e4
LT		 1503 err = ethernet_phy_detect(port_num);
1504 if (err) {
1505 pr_debug("MV643xx ethernet port %d: "
1506 "No PHY detected at addr %d\n",
1507 port_num, ethernet_phy_get(port_num));
d0412d96 1508 goto out;
1da177e4
LT		 1509 }
1510
01999873 1511 ethernet_phy_reset(port_num);
c28a4f89 1512 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
d0412d96
JC		 1513 mv643xx_init_ethtool_cmd(dev, mp->mii.phy_id, speed, duplex, &cmd);
1514 mv643xx_eth_update_pscr(dev, &cmd);
1515 mv643xx_set_settings(dev, &cmd);
c28a4f89 1516
1da177e4
LT		 1517 err = register_netdev(dev);
1518 if (err)
1519 goto out;
1520
1521 p = dev->dev_addr;
1522 printk(KERN_NOTICE
1523 "%s: port %d with MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
1524 dev->name, port_num, p[0], p[1], p[2], p[3], p[4], p[5]);
1525
1526 if (dev->features & NETIF_F_SG)
1527 printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name);
1528
1529 if (dev->features & NETIF_F_IP_CSUM)
1530 printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n",
1531 dev->name);
1532
1533#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1534 printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name);
1535#endif
1536
1537#ifdef MV643XX_COAL
1538 printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n",
1539 dev->name);
1540#endif
1541
1542#ifdef MV643XX_NAPI
1543 printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name);
1544#endif
1545
b1529871
ND		 1546 if (mp->tx_sram_size > 0)
1547 printk(KERN_NOTICE "%s: Using SRAM\n", dev->name);
1548
1da177e4
LT		 1549 return 0;
1550
1551out:
1552 free_netdev(dev);
1553
1554 return err;
1555}
1556
3ae5eaec 1557static int mv643xx_eth_remove(struct platform_device *pdev)
1da177e4 1558{
3ae5eaec 1559 struct net_device *dev = platform_get_drvdata(pdev);
1da177e4
LT		 1560
1561 unregister_netdev(dev);
1562 flush_scheduled_work();
1563
1564 free_netdev(dev);
3ae5eaec 1565 platform_set_drvdata(pdev, NULL);
1da177e4
LT		 1566 return 0;
1567}
1568
3ae5eaec 1569static int mv643xx_eth_shared_probe(struct platform_device *pdev)
1da177e4 1570{
1da177e4
LT		 1571 struct resource *res;
1572
1573 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
1574
1575 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1576 if (res == NULL)
1577 return -ENODEV;
1578
1579 mv643xx_eth_shared_base = ioremap(res->start,
1580 MV643XX_ETH_SHARED_REGS_SIZE);
1581 if (mv643xx_eth_shared_base == NULL)
1582 return -ENOMEM;
1583
1584 return 0;
1585
1586}
1587
3ae5eaec 1588static int mv643xx_eth_shared_remove(struct platform_device *pdev)
1da177e4
LT		 1589{
1590 iounmap(mv643xx_eth_shared_base);
1591 mv643xx_eth_shared_base = NULL;
1592
1593 return 0;
1594}
1595
3ae5eaec 1596static struct platform_driver mv643xx_eth_driver = {
1da177e4
LT		 1597 .probe = mv643xx_eth_probe,
1598 .remove = mv643xx_eth_remove,
3ae5eaec
RK		 1599 .driver = {
1600 .name = MV643XX_ETH_NAME,
1601 },
1da177e4
LT		 1602};
1603
3ae5eaec 1604static struct platform_driver mv643xx_eth_shared_driver = {
1da177e4
LT		 1605 .probe = mv643xx_eth_shared_probe,
1606 .remove = mv643xx_eth_shared_remove,
3ae5eaec
RK		 1607 .driver = {
1608 .name = MV643XX_ETH_SHARED_NAME,
1609 },
1da177e4
LT		 1610};
1611
1612/*
1613 * mv643xx_init_module
1614 *
1615 * Registers the network drivers into the Linux kernel
1616 *
1617 * Input : N/A
1618 *
1619 * Output : N/A
1620 */
1621static int __init mv643xx_init_module(void)
1622{
1623 int rc;
1624
3ae5eaec 1625 rc = platform_driver_register(&mv643xx_eth_shared_driver);
1da177e4 1626 if (!rc) {
3ae5eaec 1627 rc = platform_driver_register(&mv643xx_eth_driver);
1da177e4 1628 if (rc)
3ae5eaec 1629 platform_driver_unregister(&mv643xx_eth_shared_driver);
1da177e4
LT		 1630 }
1631 return rc;
1632}
1633
1634/*
1635 * mv643xx_cleanup_module
1636 *
1637 * Registers the network drivers into the Linux kernel
1638 *
1639 * Input : N/A
1640 *
1641 * Output : N/A
1642 */
1643static void __exit mv643xx_cleanup_module(void)
1644{
3ae5eaec
RK		 1645 platform_driver_unregister(&mv643xx_eth_driver);
1646 platform_driver_unregister(&mv643xx_eth_shared_driver);
1da177e4
LT		 1647}
1648
1649module_init(mv643xx_init_module);
1650module_exit(mv643xx_cleanup_module);
1651
1652MODULE_LICENSE("GPL");
1653MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani"
1654 " and Dale Farnsworth");
1655MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
1656
1657/*
1658 * The second part is the low level driver of the gigE ethernet ports.
1659 */
1660
1661/*
1662 * Marvell's Gigabit Ethernet controller low level driver
1663 *
1664 * DESCRIPTION:
1665 * This file introduce low level API to Marvell's Gigabit Ethernet
1666 * controller. This Gigabit Ethernet Controller driver API controls
1667 * 1) Operations (i.e. port init, start, reset etc').
1668 * 2) Data flow (i.e. port send, receive etc').
1669 * Each Gigabit Ethernet port is controlled via
1670 * struct mv643xx_private.
1671 * This struct includes user configuration information as well as
1672 * driver internal data needed for its operations.
1673 *
1674 * Supported Features:
1675 * - This low level driver is OS independent. Allocating memory for
1676 * the descriptor rings and buffers are not within the scope of
1677 * this driver.
1678 * - The user is free from Rx/Tx queue managing.
1679 * - This low level driver introduce functionality API that enable
1680 * the to operate Marvell's Gigabit Ethernet Controller in a
1681 * convenient way.
1682 * - Simple Gigabit Ethernet port operation API.
1683 * - Simple Gigabit Ethernet port data flow API.
1684 * - Data flow and operation API support per queue functionality.
1685 * - Support cached descriptors for better performance.
1686 * - Enable access to all four DRAM banks and internal SRAM memory
1687 * spaces.
1688 * - PHY access and control API.
1689 * - Port control register configuration API.
1690 * - Full control over Unicast and Multicast MAC configurations.
1691 *
1692 * Operation flow:
1693 *
1694 * Initialization phase
1695 * This phase complete the initialization of the the
1696 * mv643xx_private struct.
1697 * User information regarding port configuration has to be set
1698 * prior to calling the port initialization routine.
1699 *
1700 * In this phase any port Tx/Rx activity is halted, MIB counters
1701 * are cleared, PHY address is set according to user parameter and
1702 * access to DRAM and internal SRAM memory spaces.
1703 *
1704 * Driver ring initialization
1705 * Allocating memory for the descriptor rings and buffers is not
1706 * within the scope of this driver. Thus, the user is required to
1707 * allocate memory for the descriptors ring and buffers. Those
1708 * memory parameters are used by the Rx and Tx ring initialization
1709 * routines in order to curve the descriptor linked list in a form
1710 * of a ring.
1711 * Note: Pay special attention to alignment issues when using
1712 * cached descriptors/buffers. In this phase the driver store
1713 * information in the mv643xx_private struct regarding each queue
1714 * ring.
1715 *
1716 * Driver start
1717 * This phase prepares the Ethernet port for Rx and Tx activity.
1718 * It uses the information stored in the mv643xx_private struct to
1719 * initialize the various port registers.
1720 *
1721 * Data flow:
1722 * All packet references to/from the driver are done using
1723 * struct pkt_info.
1724 * This struct is a unified struct used with Rx and Tx operations.
1725 * This way the user is not required to be familiar with neither
1726 * Tx nor Rx descriptors structures.
1727 * The driver's descriptors rings are management by indexes.
1728 * Those indexes controls the ring resources and used to indicate
1729 * a SW resource error:
1730 * 'current'
1731 * This index points to the current available resource for use. For
1732 * example in Rx process this index will point to the descriptor
1733 * that will be passed to the user upon calling the receive
1734 * routine. In Tx process, this index will point to the descriptor
1735 * that will be assigned with the user packet info and transmitted.
1736 * 'used'
1737 * This index points to the descriptor that need to restore its
1738 * resources. For example in Rx process, using the Rx buffer return
1739 * API will attach the buffer returned in packet info to the
1740 * descriptor pointed by 'used'. In Tx process, using the Tx
1741 * descriptor return will merely return the user packet info with
1742 * the command status of the transmitted buffer pointed by the
1743 * 'used' index. Nevertheless, it is essential to use this routine
1744 * to update the 'used' index.
1745 * 'first'
1746 * This index supports Tx Scatter-Gather. It points to the first
1747 * descriptor of a packet assembled of multiple buffers. For
1748 * example when in middle of Such packet we have a Tx resource
1749 * error the 'curr' index get the value of 'first' to indicate
1750 * that the ring returned to its state before trying to transmit
1751 * this packet.
1752 *
1753 * Receive operation:
1754 * The eth_port_receive API set the packet information struct,
1755 * passed by the caller, with received information from the
1756 * 'current' SDMA descriptor.
1757 * It is the user responsibility to return this resource back
1758 * to the Rx descriptor ring to enable the reuse of this source.
1759 * Return Rx resource is done using the eth_rx_return_buff API.
1760 *
1da177e4
LT		 1761 * Prior to calling the initialization routine eth_port_init() the user
1762 * must set the following fields under mv643xx_private struct:
1763 * port_num User Ethernet port number.
1da177e4
LT		 1764 * port_config User port configuration value.
1765 * port_config_extend User port config extend value.
1766 * port_sdma_config User port SDMA config value.
1767 * port_serial_control User port serial control value.
1768 *
1769 * This driver data flow is done using the struct pkt_info which
1770 * is a unified struct for Rx and Tx operations:
1771 *
1772 * byte_cnt Tx/Rx descriptor buffer byte count.
1773 * l4i_chk CPU provided TCP Checksum. For Tx operation
1774 * only.
1775 * cmd_sts Tx/Rx descriptor command status.
1776 * buf_ptr Tx/Rx descriptor buffer pointer.
1777 * return_info Tx/Rx user resource return information.
1778 */
1779
1da177e4
LT		 1780/* PHY routines */
1781static int ethernet_phy_get(unsigned int eth_port_num);
1782static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
1783
1784/* Ethernet Port routines */
cf4086c7 1785static void eth_port_set_filter_table_entry(int table, unsigned char entry);
1da177e4
LT		 1786
1787/*
1788 * eth_port_init - Initialize the Ethernet port driver
1789 *
1790 * DESCRIPTION:
1791 * This function prepares the ethernet port to start its activity:
1792 * 1) Completes the ethernet port driver struct initialization toward port
1793 * start routine.
1794 * 2) Resets the device to a quiescent state in case of warm reboot.
1795 * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
1796 * 4) Clean MAC tables. The reset status of those tables is unknown.
1797 * 5) Set PHY address.
1798 * Note: Call this routine prior to eth_port_start routine and after
1799 * setting user values in the user fields of Ethernet port control
1800 * struct.
1801 *
1802 * INPUT:
1803 * struct mv643xx_private *mp Ethernet port control struct
1804 *
1805 * OUTPUT:
1806 * See description.
1807 *
1808 * RETURN:
1809 * None.
1810 */
1811static void eth_port_init(struct mv643xx_private *mp)
1812{
1da177e4 1813 mp->rx_resource_err = 0;
1da177e4
LT		 1814
1815 eth_port_reset(mp->port_num);
1816
1817 eth_port_init_mac_tables(mp->port_num);
1da177e4
LT		 1818}
1819
1820/*
1821 * eth_port_start - Start the Ethernet port activity.
1822 *
1823 * DESCRIPTION:
1824 * This routine prepares the Ethernet port for Rx and Tx activity:
1825 * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
1826 * has been initialized a descriptor's ring (using
1827 * ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx)
1828 * 2. Initialize and enable the Ethernet configuration port by writing to
1829 * the port's configuration and command registers.
1830 * 3. Initialize and enable the SDMA by writing to the SDMA's
1831 * configuration and command registers. After completing these steps,
1832 * the ethernet port SDMA can starts to perform Rx and Tx activities.
1833 *
1834 * Note: Each Rx and Tx queue descriptor's list must be initialized prior
1835 * to calling this function (use ether_init_tx_desc_ring for Tx queues
1836 * and ether_init_rx_desc_ring for Rx queues).
1837 *
1838 * INPUT:
ed9b5d45 1839 * dev - a pointer to the required interface
1da177e4
LT		 1840 *
1841 * OUTPUT:
1842 * Ethernet port is ready to receive and transmit.
1843 *
1844 * RETURN:
1845 * None.
1846 */
ed9b5d45 1847static void eth_port_start(struct net_device *dev)
1da177e4 1848{
ed9b5d45 1849 struct mv643xx_private *mp = netdev_priv(dev);
1da177e4
LT		 1850 unsigned int port_num = mp->port_num;
1851 int tx_curr_desc, rx_curr_desc;
d0412d96
JC		 1852 u32 pscr;
1853 struct ethtool_cmd ethtool_cmd;
1da177e4
LT		 1854
1855 /* Assignment of Tx CTRP of given queue */
1856 tx_curr_desc = mp->tx_curr_desc_q;
1857 mv_write(MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port_num),
1858 (u32)((struct eth_tx_desc *)mp->tx_desc_dma + tx_curr_desc));
1859
1860 /* Assignment of Rx CRDP of given queue */
1861 rx_curr_desc = mp->rx_curr_desc_q;
1862 mv_write(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num),
1863 (u32)((struct eth_rx_desc *)mp->rx_desc_dma + rx_curr_desc));
1864
1865 /* Add the assigned Ethernet address to the port's address table */
ed9b5d45 1866 eth_port_uc_addr_set(port_num, dev->dev_addr);
1da177e4
LT		 1867
1868 /* Assign port configuration and command. */
01999873
DF		 1869 mv_write(MV643XX_ETH_PORT_CONFIG_REG(port_num),
1870 MV643XX_ETH_PORT_CONFIG_DEFAULT_VALUE);
1871
1872 mv_write(MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port_num),
1873 MV643XX_ETH_PORT_CONFIG_EXTEND_DEFAULT_VALUE);
1da177e4 1874
d0412d96 1875 pscr = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
01999873
DF		 1876
1877 pscr &= ~(MV643XX_ETH_SERIAL_PORT_ENABLE | MV643XX_ETH_FORCE_LINK_PASS);
d0412d96 1878 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), pscr);
1da177e4 1879
d0412d96
JC		 1880 pscr |= MV643XX_ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1881 MV643XX_ETH_DISABLE_AUTO_NEG_SPEED_GMII |
1882 MV643XX_ETH_DISABLE_AUTO_NEG_FOR_DUPLX |
1883 MV643XX_ETH_DO_NOT_FORCE_LINK_FAIL |
1884 MV643XX_ETH_SERIAL_PORT_CONTROL_RESERVED;
1da177e4 1885
d0412d96 1886 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), pscr);
1da177e4 1887
d0412d96
JC		 1888 pscr |= MV643XX_ETH_SERIAL_PORT_ENABLE;
1889 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), pscr);
1da177e4
LT		 1890
1891 /* Assign port SDMA configuration */
01999873
DF		 1892 mv_write(MV643XX_ETH_SDMA_CONFIG_REG(port_num),
1893 MV643XX_ETH_PORT_SDMA_CONFIG_DEFAULT_VALUE);
1da177e4
LT		 1894
1895 /* Enable port Rx. */
9f8dd319 1896 mv643xx_eth_port_enable_rx(port_num, mp->port_rx_queue_command);
8f543718
DF		 1897
1898 /* Disable port bandwidth limits by clearing MTU register */
1899 mv_write(MV643XX_ETH_MAXIMUM_TRANSMIT_UNIT(port_num), 0);
d0412d96
JC		 1900
1901 /* save phy settings across reset */
1902 mv643xx_get_settings(dev, &ethtool_cmd);
1903 ethernet_phy_reset(mp->port_num);
1904 mv643xx_set_settings(dev, &ethtool_cmd);
1da177e4
LT		 1905}
1906
1907/*
1908 * eth_port_uc_addr_set - This function Set the port Unicast address.
1909 *
1910 * DESCRIPTION:
1911 * This function Set the port Ethernet MAC address.
1912 *
1913 * INPUT:
1914 * unsigned int eth_port_num Port number.
1915 * char * p_addr Address to be set
1916 *
1917 * OUTPUT:
cf4086c7
DF		 1918 * Set MAC address low and high registers. also calls
1919 * eth_port_set_filter_table_entry() to set the unicast
1920 * table with the proper information.
1da177e4
LT		 1921 *
1922 * RETURN:
1923 * N/A.
1924 *
1925 */
1926static void eth_port_uc_addr_set(unsigned int eth_port_num,
1927 unsigned char *p_addr)
1928{
1929 unsigned int mac_h;
1930 unsigned int mac_l;
cf4086c7 1931 int table;
1da177e4
LT		 1932
1933 mac_l = (p_addr[4] << 8) | (p_addr[5]);
1934 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
1935 (p_addr[3] << 0);
1936
1937 mv_write(MV643XX_ETH_MAC_ADDR_LOW(eth_port_num), mac_l);
1938 mv_write(MV643XX_ETH_MAC_ADDR_HIGH(eth_port_num), mac_h);
1939
1940 /* Accept frames of this address */
cf4086c7
DF		 1941 table = MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE(eth_port_num);
1942 eth_port_set_filter_table_entry(table, p_addr[5] & 0x0f);
1da177e4
LT		 1943}
1944
1945/*
1946 * eth_port_uc_addr_get - This function retrieves the port Unicast address
1947 * (MAC address) from the ethernet hw registers.
1948 *
1949 * DESCRIPTION:
1950 * This function retrieves the port Ethernet MAC address.
1951 *
1952 * INPUT:
1953 * unsigned int eth_port_num Port number.
1954 * char *MacAddr pointer where the MAC address is stored
1955 *
1956 * OUTPUT:
1957 * Copy the MAC address to the location pointed to by MacAddr
1958 *
1959 * RETURN:
1960 * N/A.
1961 *
1962 */
1963static void eth_port_uc_addr_get(struct net_device *dev, unsigned char *p_addr)
1964{
1965 struct mv643xx_private *mp = netdev_priv(dev);
1966 unsigned int mac_h;
1967 unsigned int mac_l;
1968
1969 mac_h = mv_read(MV643XX_ETH_MAC_ADDR_HIGH(mp->port_num));
1970 mac_l = mv_read(MV643XX_ETH_MAC_ADDR_LOW(mp->port_num));
1971
1972 p_addr[0] = (mac_h >> 24) & 0xff;
1973 p_addr[1] = (mac_h >> 16) & 0xff;
1974 p_addr[2] = (mac_h >> 8) & 0xff;
1975 p_addr[3] = mac_h & 0xff;
1976 p_addr[4] = (mac_l >> 8) & 0xff;
1977 p_addr[5] = mac_l & 0xff;
1978}
1979
16e03018
DF		 1980/*
1981 * The entries in each table are indexed by a hash of a packet's MAC
1982 * address. One bit in each entry determines whether the packet is
1983 * accepted. There are 4 entries (each 8 bits wide) in each register
1984 * of the table. The bits in each entry are defined as follows:
1985 * 0 Accept=1, Drop=0
1986 * 3-1 Queue (ETH_Q0=0)
1987 * 7-4 Reserved = 0;
1988 */
1989static void eth_port_set_filter_table_entry(int table, unsigned char entry)
1990{
1991 unsigned int table_reg;
1992 unsigned int tbl_offset;
1993 unsigned int reg_offset;
1994
1995 tbl_offset = (entry / 4) * 4; /* Register offset of DA table entry */
1996 reg_offset = entry % 4; /* Entry offset within the register */
1997
1998 /* Set "accepts frame bit" at specified table entry */
1999 table_reg = mv_read(table + tbl_offset);
2000 table_reg |= 0x01 << (8 * reg_offset);
2001 mv_write(table + tbl_offset, table_reg);
2002}
2003
2004/*
2005 * eth_port_mc_addr - Multicast address settings.
2006 *
2007 * The MV device supports multicast using two tables:
2008 * 1) Special Multicast Table for MAC addresses of the form
2009 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_FF).
2010 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
2011 * Table entries in the DA-Filter table.
2012 * 2) Other Multicast Table for multicast of another type. A CRC-8bit
2013 * is used as an index to the Other Multicast Table entries in the
2014 * DA-Filter table. This function calculates the CRC-8bit value.
2015 * In either case, eth_port_set_filter_table_entry() is then called
2016 * to set to set the actual table entry.
2017 */
2018static void eth_port_mc_addr(unsigned int eth_port_num, unsigned char *p_addr)
2019{
2020 unsigned int mac_h;
2021 unsigned int mac_l;
2022 unsigned char crc_result = 0;
2023 int table;
2024 int mac_array[48];
2025 int crc[8];
2026 int i;
2027
2028 if ((p_addr[0] == 0x01) && (p_addr[1] == 0x00) &&
2029 (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) {
2030 table = MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2031 (eth_port_num);
2032 eth_port_set_filter_table_entry(table, p_addr[5]);
2033 return;
2034 }
2035
2036 /* Calculate CRC-8 out of the given address */
2037 mac_h = (p_addr[0] << 8) | (p_addr[1]);
2038 mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
2039 (p_addr[4] << 8) | (p_addr[5] << 0);
2040
2041 for (i = 0; i < 32; i++)
2042 mac_array[i] = (mac_l >> i) & 0x1;
2043 for (i = 32; i < 48; i++)
2044 mac_array[i] = (mac_h >> (i - 32)) & 0x1;
2045
2046 crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ mac_array[39] ^
2047 mac_array[35] ^ mac_array[34] ^ mac_array[31] ^ mac_array[30] ^
2048 mac_array[28] ^ mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
2049 mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ mac_array[12] ^
2050 mac_array[8] ^ mac_array[7] ^ mac_array[6] ^ mac_array[0];
2051
2052 crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
2053 mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ mac_array[34] ^
2054 mac_array[32] ^ mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
2055 mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ mac_array[21] ^
2056 mac_array[20] ^ mac_array[18] ^ mac_array[17] ^ mac_array[16] ^
2057 mac_array[15] ^ mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
2058 mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ mac_array[0];
2059
2060 crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ mac_array[43] ^
2061 mac_array[42] ^ mac_array[39] ^ mac_array[37] ^ mac_array[34] ^
2062 mac_array[33] ^ mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
2063 mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ mac_array[15] ^
2064 mac_array[13] ^ mac_array[12] ^ mac_array[10] ^ mac_array[8] ^
2065 mac_array[6] ^ mac_array[2] ^ mac_array[1] ^ mac_array[0];
2066
2067 crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
2068 mac_array[40] ^ mac_array[38] ^ mac_array[35] ^ mac_array[34] ^
2069 mac_array[30] ^ mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
2070 mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
2071 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[7] ^
2072 mac_array[3] ^ mac_array[2] ^ mac_array[1];
2073
2074 crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[41] ^
2075 mac_array[39] ^ mac_array[36] ^ mac_array[35] ^ mac_array[31] ^
2076 mac_array[30] ^ mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
2077 mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ mac_array[14] ^
2078 mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ mac_array[4] ^
2079 mac_array[3] ^ mac_array[2];
2080
2081 crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ mac_array[42] ^
2082 mac_array[40] ^ mac_array[37] ^ mac_array[36] ^ mac_array[32] ^
2083 mac_array[31] ^ mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
2084 mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ mac_array[15] ^
2085 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[5] ^
2086 mac_array[4] ^ mac_array[3];
2087
2088 crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ mac_array[41] ^
2089 mac_array[38] ^ mac_array[37] ^ mac_array[33] ^ mac_array[32] ^
2090 mac_array[29] ^ mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
2091 mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ mac_array[14] ^
2092 mac_array[12] ^ mac_array[10] ^ mac_array[6] ^ mac_array[5] ^
2093 mac_array[4];
2094
2095 crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ mac_array[39] ^
2096 mac_array[38] ^ mac_array[34] ^ mac_array[33] ^ mac_array[30] ^
2097 mac_array[29] ^ mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
2098 mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ mac_array[13] ^
2099 mac_array[11] ^ mac_array[7] ^ mac_array[6] ^ mac_array[5];
2100
2101 for (i = 0; i < 8; i++)
2102 crc_result = crc_result | (crc[i] << i);
2103
2104 table = MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num);
2105 eth_port_set_filter_table_entry(table, crc_result);
2106}
2107
2108/*
2109 * Set the entire multicast list based on dev->mc_list.
2110 */
2111static void eth_port_set_multicast_list(struct net_device *dev)
2112{
2113
2114 struct dev_mc_list *mc_list;
2115 int i;
2116 int table_index;
2117 struct mv643xx_private *mp = netdev_priv(dev);
2118 unsigned int eth_port_num = mp->port_num;
2119
2120 /* If the device is in promiscuous mode or in all multicast mode,
2121 * we will fully populate both multicast tables with accept.
2122 * This is guaranteed to yield a match on all multicast addresses...
2123 */
2124 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) {
2125 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
b4de9051
DF		 2126 /* Set all entries in DA filter special multicast
2127 * table (Ex_dFSMT)
2128 * Set for ETH_Q0 for now
2129 * Bits
2130 * 0 Accept=1, Drop=0
2131 * 3-1 Queue ETH_Q0=0
2132 * 7-4 Reserved = 0;
2133 */
2134 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
2135
2136 /* Set all entries in DA filter other multicast
2137 * table (Ex_dFOMT)
2138 * Set for ETH_Q0 for now
2139 * Bits
2140 * 0 Accept=1, Drop=0
2141 * 3-1 Queue ETH_Q0=0
2142 * 7-4 Reserved = 0;
2143 */
2144 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
2145 }
16e03018
DF		 2146 return;
2147 }
2148
2149 /* We will clear out multicast tables every time we get the list.
2150 * Then add the entire new list...
2151 */
2152 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2153 /* Clear DA filter special multicast table (Ex_dFSMT) */
2154 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2155 (eth_port_num) + table_index, 0);
2156
2157 /* Clear DA filter other multicast table (Ex_dFOMT) */
2158 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2159 (eth_port_num) + table_index, 0);
2160 }
2161
2162 /* Get pointer to net_device multicast list and add each one... */
2163 for (i = 0, mc_list = dev->mc_list;
2164 (i < 256) && (mc_list != NULL) && (i < dev->mc_count);
2165 i++, mc_list = mc_list->next)
2166 if (mc_list->dmi_addrlen == 6)
2167 eth_port_mc_addr(eth_port_num, mc_list->dmi_addr);
2168}
2169
1da177e4
LT		 2170/*
2171 * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
2172 *
2173 * DESCRIPTION:
2174 * Go through all the DA filter tables (Unicast, Special Multicast &
2175 * Other Multicast) and set each entry to 0.
2176 *
2177 * INPUT:
2178 * unsigned int eth_port_num Ethernet Port number.
2179 *
2180 * OUTPUT:
2181 * Multicast and Unicast packets are rejected.
2182 *
2183 * RETURN:
2184 * None.
2185 */
2186static void eth_port_init_mac_tables(unsigned int eth_port_num)
2187{
2188 int table_index;
2189
2190 /* Clear DA filter unicast table (Ex_dFUT) */
2191 for (table_index = 0; table_index <= 0xC; table_index += 4)
cf4086c7
DF		 2192 mv_write(MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2193 (eth_port_num) + table_index, 0);
1da177e4
LT		 2194
2195 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2196 /* Clear DA filter special multicast table (Ex_dFSMT) */
16e03018
DF		 2197 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2198 (eth_port_num) + table_index, 0);
1da177e4 2199 /* Clear DA filter other multicast table (Ex_dFOMT) */
16e03018
DF		 2200 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2201 (eth_port_num) + table_index, 0);
1da177e4
LT		 2202 }
2203}
2204
2205/*
2206 * eth_clear_mib_counters - Clear all MIB counters
2207 *
2208 * DESCRIPTION:
2209 * This function clears all MIB counters of a specific ethernet port.
2210 * A read from the MIB counter will reset the counter.
2211 *
2212 * INPUT:
2213 * unsigned int eth_port_num Ethernet Port number.
2214 *
2215 * OUTPUT:
2216 * After reading all MIB counters, the counters resets.
2217 *
2218 * RETURN:
2219 * MIB counter value.
2220 *
2221 */
2222static void eth_clear_mib_counters(unsigned int eth_port_num)
2223{
2224 int i;
2225
2226 /* Perform dummy reads from MIB counters */
2227 for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
2228 i += 4)
2229 mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(eth_port_num) + i);
2230}
2231
2232static inline u32 read_mib(struct mv643xx_private *mp, int offset)
2233{
2234 return mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(mp->port_num) + offset);
2235}
2236
2237static void eth_update_mib_counters(struct mv643xx_private *mp)
2238{
2239 struct mv643xx_mib_counters *p = &mp->mib_counters;
2240 int offset;
2241
2242 p->good_octets_received +=
2243 read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
2244 p->good_octets_received +=
2245 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32;
2246
2247 for (offset = ETH_MIB_BAD_OCTETS_RECEIVED;
2248 offset <= ETH_MIB_FRAMES_1024_TO_MAX_OCTETS;
2249 offset += 4)
2250 *(u32 *)((char *)p + offset) = read_mib(mp, offset);
2251
2252 p->good_octets_sent += read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_LOW);
2253 p->good_octets_sent +=
2254 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_HIGH) << 32;
2255
2256 for (offset = ETH_MIB_GOOD_FRAMES_SENT;
2257 offset <= ETH_MIB_LATE_COLLISION;
2258 offset += 4)
2259 *(u32 *)((char *)p + offset) = read_mib(mp, offset);
2260}
2261
2262/*
2263 * ethernet_phy_detect - Detect whether a phy is present
2264 *
2265 * DESCRIPTION:
2266 * This function tests whether there is a PHY present on
2267 * the specified port.
2268 *
2269 * INPUT:
2270 * unsigned int eth_port_num Ethernet Port number.
2271 *
2272 * OUTPUT:
2273 * None
2274 *
2275 * RETURN:
2276 * 0 on success
2277 * -ENODEV on failure
2278 *
2279 */
2280static int ethernet_phy_detect(unsigned int port_num)
2281{
2282 unsigned int phy_reg_data0;
2283 int auto_neg;
2284
2285 eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
2286 auto_neg = phy_reg_data0 & 0x1000;
2287 phy_reg_data0 ^= 0x1000; /* invert auto_neg */
2288 eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
2289
2290 eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
2291 if ((phy_reg_data0 & 0x1000) == auto_neg)
2292 return -ENODEV; /* change didn't take */
2293
2294 phy_reg_data0 ^= 0x1000;
2295 eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
2296 return 0;
2297}
2298
2299/*
2300 * ethernet_phy_get - Get the ethernet port PHY address.
2301 *
2302 * DESCRIPTION:
2303 * This routine returns the given ethernet port PHY address.
2304 *
2305 * INPUT:
2306 * unsigned int eth_port_num Ethernet Port number.
2307 *
2308 * OUTPUT:
2309 * None.
2310 *
2311 * RETURN:
2312 * PHY address.
2313 *
2314 */
2315static int ethernet_phy_get(unsigned int eth_port_num)
2316{
2317 unsigned int reg_data;
2318
2319 reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG);
2320
2321 return ((reg_data >> (5 * eth_port_num)) & 0x1f);
2322}
2323
2324/*
2325 * ethernet_phy_set - Set the ethernet port PHY address.
2326 *
2327 * DESCRIPTION:
2328 * This routine sets the given ethernet port PHY address.
2329 *
2330 * INPUT:
2331 * unsigned int eth_port_num Ethernet Port number.
2332 * int phy_addr PHY address.
2333 *
2334 * OUTPUT:
2335 * None.
2336 *
2337 * RETURN:
2338 * None.
2339 *
2340 */
2341static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr)
2342{
2343 u32 reg_data;
2344 int addr_shift = 5 * eth_port_num;
2345
2346 reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG);
2347 reg_data &= ~(0x1f << addr_shift);
2348 reg_data |= (phy_addr & 0x1f) << addr_shift;
2349 mv_write(MV643XX_ETH_PHY_ADDR_REG, reg_data);
2350}
2351
2352/*
2353 * ethernet_phy_reset - Reset Ethernet port PHY.
2354 *
2355 * DESCRIPTION:
2356 * This routine utilizes the SMI interface to reset the ethernet port PHY.
2357 *
2358 * INPUT:
2359 * unsigned int eth_port_num Ethernet Port number.
2360 *
2361 * OUTPUT:
2362 * The PHY is reset.
2363 *
2364 * RETURN:
2365 * None.
2366 *
2367 */
2368static void ethernet_phy_reset(unsigned int eth_port_num)
2369{
2370 unsigned int phy_reg_data;
2371
2372 /* Reset the PHY */
2373 eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data);
2374 phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
2375 eth_port_write_smi_reg(eth_port_num, 0, phy_reg_data);
d0412d96
JC		 2376
2377 /* wait for PHY to come out of reset */
2378 do {
2379 udelay(1);
2380 eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data);
2381 } while (phy_reg_data & 0x8000);
1da177e4
LT		 2382}
2383
9f8dd319 2384static void mv643xx_eth_port_enable_tx(unsigned int port_num,
12a87c64 2385 unsigned int queues)
9f8dd319 2386{
12a87c64 2387 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num), queues);
9f8dd319
DF		 2388}
2389
2390static void mv643xx_eth_port_enable_rx(unsigned int port_num,
12a87c64 2391 unsigned int queues)
9f8dd319 2392{
12a87c64 2393 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), queues);
9f8dd319
DF		 2394}
2395
2396static unsigned int mv643xx_eth_port_disable_tx(unsigned int port_num)
2397{
12a87c64 2398 u32 queues;
9f8dd319
DF		 2399
2400 /* Stop Tx port activity. Check port Tx activity. */
12a87c64 2401 queues = mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num))
9f8dd319 2402 & 0xFF;
12a87c64
DF		 2403 if (queues) {
2404 /* Issue stop command for active queues only */
9f8dd319 2405 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num),
12a87c64 2406 (queues << 8));
9f8dd319
DF		 2407
2408 /* Wait for all Tx activity to terminate. */
2409 /* Check port cause register that all Tx queues are stopped */
2410 while (mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num))
2411 & 0xFF)
2412 udelay(PHY_WAIT_MICRO_SECONDS);
2413
2414 /* Wait for Tx FIFO to empty */
2415 while (mv_read(MV643XX_ETH_PORT_STATUS_REG(port_num)) &
2416 ETH_PORT_TX_FIFO_EMPTY)
2417 udelay(PHY_WAIT_MICRO_SECONDS);
2418 }
2419
12a87c64 2420 return queues;
9f8dd319
DF		 2421}
2422
2423static unsigned int mv643xx_eth_port_disable_rx(unsigned int port_num)
2424{
12a87c64 2425 u32 queues;
9f8dd319
DF		 2426
2427 /* Stop Rx port activity. Check port Rx activity. */
12a87c64 2428 queues = mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num))
e38fd1a0 2429 & 0xFF;
12a87c64
DF		 2430 if (queues) {
2431 /* Issue stop command for active queues only */
9f8dd319 2432 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num),
12a87c64 2433 (queues << 8));
9f8dd319
DF		 2434
2435 /* Wait for all Rx activity to terminate. */
2436 /* Check port cause register that all Rx queues are stopped */
2437 while (mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num))
2438 & 0xFF)
2439 udelay(PHY_WAIT_MICRO_SECONDS);
2440 }
2441
12a87c64 2442 return queues;
9f8dd319
DF		 2443}
2444
1da177e4
LT		 2445/*
2446 * eth_port_reset - Reset Ethernet port
2447 *
2448 * DESCRIPTION:
2449 * This routine resets the chip by aborting any SDMA engine activity and
2450 * clearing the MIB counters. The Receiver and the Transmit unit are in
2451 * idle state after this command is performed and the port is disabled.
2452 *
2453 * INPUT:
2454 * unsigned int eth_port_num Ethernet Port number.
2455 *
2456 * OUTPUT:
2457 * Channel activity is halted.
2458 *
2459 * RETURN:
2460 * None.
2461 *
2462 */
2463static void eth_port_reset(unsigned int port_num)
2464{
2465 unsigned int reg_data;
2466
9f8dd319
DF		 2467 mv643xx_eth_port_disable_tx(port_num);
2468 mv643xx_eth_port_disable_rx(port_num);
1da177e4
LT		 2469
2470 /* Clear all MIB counters */
2471 eth_clear_mib_counters(port_num);
2472
2473 /* Reset the Enable bit in the Configuration Register */
2474 reg_data = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
d0412d96
JC		 2475 reg_data &= ~(MV643XX_ETH_SERIAL_PORT_ENABLE |
2476 MV643XX_ETH_DO_NOT_FORCE_LINK_FAIL |
2477 MV643XX_ETH_FORCE_LINK_PASS);
1da177e4
LT		 2478 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), reg_data);
2479}
2480
1da177e4 2481
1da177e4
LT		 2482/*
2483 * eth_port_read_smi_reg - Read PHY registers
2484 *
2485 * DESCRIPTION:
2486 * This routine utilize the SMI interface to interact with the PHY in
2487 * order to perform PHY register read.
2488 *
2489 * INPUT:
2490 * unsigned int port_num Ethernet Port number.
2491 * unsigned int phy_reg PHY register address offset.
2492 * unsigned int *value Register value buffer.
2493 *
2494 * OUTPUT:
2495 * Write the value of a specified PHY register into given buffer.
2496 *
2497 * RETURN:
2498 * false if the PHY is busy or read data is not in valid state.
2499 * true otherwise.
2500 *
2501 */
2502static void eth_port_read_smi_reg(unsigned int port_num,
2503 unsigned int phy_reg, unsigned int *value)
2504{
2505 int phy_addr = ethernet_phy_get(port_num);
2506 unsigned long flags;
2507 int i;
2508
2509 /* the SMI register is a shared resource */
2510 spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
2511
2512 /* wait for the SMI register to become available */
2513 for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) {
2514 if (i == PHY_WAIT_ITERATIONS) {
2515 printk("mv643xx PHY busy timeout, port %d\n", port_num);
2516 goto out;
2517 }
2518 udelay(PHY_WAIT_MICRO_SECONDS);
2519 }
2520
2521 mv_write(MV643XX_ETH_SMI_REG,
2522 (phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ);
2523
2524 /* now wait for the data to be valid */
2525 for (i = 0; !(mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_READ_VALID); i++) {
2526 if (i == PHY_WAIT_ITERATIONS) {
2527 printk("mv643xx PHY read timeout, port %d\n", port_num);
2528 goto out;
2529 }
2530 udelay(PHY_WAIT_MICRO_SECONDS);
2531 }
2532
2533 *value = mv_read(MV643XX_ETH_SMI_REG) & 0xffff;
2534out:
2535 spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
2536}
2537
2538/*
2539 * eth_port_write_smi_reg - Write to PHY registers
2540 *
2541 * DESCRIPTION:
2542 * This routine utilize the SMI interface to interact with the PHY in
2543 * order to perform writes to PHY registers.
2544 *
2545 * INPUT:
2546 * unsigned int eth_port_num Ethernet Port number.
2547 * unsigned int phy_reg PHY register address offset.
2548 * unsigned int value Register value.
2549 *
2550 * OUTPUT:
2551 * Write the given value to the specified PHY register.
2552 *
2553 * RETURN:
2554 * false if the PHY is busy.
2555 * true otherwise.
2556 *
2557 */
2558static void eth_port_write_smi_reg(unsigned int eth_port_num,
2559 unsigned int phy_reg, unsigned int value)
2560{
2561 int phy_addr;
2562 int i;
2563 unsigned long flags;
2564
2565 phy_addr = ethernet_phy_get(eth_port_num);
2566
2567 /* the SMI register is a shared resource */
2568 spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
2569
2570 /* wait for the SMI register to become available */
2571 for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) {
2572 if (i == PHY_WAIT_ITERATIONS) {
2573 printk("mv643xx PHY busy timeout, port %d\n",
2574 eth_port_num);
2575 goto out;
2576 }
2577 udelay(PHY_WAIT_MICRO_SECONDS);
2578 }
2579
2580 mv_write(MV643XX_ETH_SMI_REG, (phy_addr << 16) | (phy_reg << 21) |
2581 ETH_SMI_OPCODE_WRITE | (value & 0xffff));
2582out:
2583 spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
2584}
2585
c28a4f89
JC		 2586/*
2587 * Wrappers for MII support library.
2588 */
2589static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location)
2590{
2591 int val;
2592 struct mv643xx_private *mp = netdev_priv(dev);
2593
2594 eth_port_read_smi_reg(mp->port_num, location, &val);
2595 return val;
2596}
2597
2598static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val)
2599{
2600 struct mv643xx_private *mp = netdev_priv(dev);
2601 eth_port_write_smi_reg(mp->port_num, location, val);
2602}
2603
1da177e4
LT		 2604/*
2605 * eth_tx_return_desc - Free all used Tx descriptors
2606 *
2607 * DESCRIPTION:
2608 * This routine returns the transmitted packet information to the caller.
2609 * It uses the 'first' index to support Tx desc return in case a transmit
2610 * of a packet spanned over multiple buffer still in process.
2611 * In case the Tx queue was in "resource error" condition, where there are
2612 * no available Tx resources, the function resets the resource error flag.
2613 *
2614 * INPUT:
2615 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2616 * struct pkt_info *p_pkt_info User packet buffer.
2617 *
2618 * OUTPUT:
2619 * Tx ring 'first' and 'used' indexes are updated.
2620 *
2621 * RETURN:
8f518703
DF		 2622 * ETH_OK on success
2623 * ETH_ERROR otherwise.
1da177e4
LT		 2624 *
2625 */
2626static ETH_FUNC_RET_STATUS eth_tx_return_desc(struct mv643xx_private *mp,
2627 struct pkt_info *p_pkt_info)
2628{
2629 int tx_desc_used;
8f518703
DF		 2630 struct eth_tx_desc *p_tx_desc_used;
2631 unsigned int command_status;
2632 unsigned long flags;
2633 int err = ETH_OK;
2634
2635 spin_lock_irqsave(&mp->lock, flags);
2636
c8aaea25
DF		 2637 BUG_ON(mp->tx_desc_count < 0);
2638 if (mp->tx_desc_count == 0) {
2639 /* no more tx descs in use */
2640 err = ETH_ERROR;
2641 goto out;
2642 }
1da177e4
LT		 2643
2644 /* Get the Tx Desc ring indexes */
2645 tx_desc_used = mp->tx_used_desc_q;
2646
2647 p_tx_desc_used = &mp->p_tx_desc_area[tx_desc_used];
2648
c8aaea25 2649 BUG_ON(p_tx_desc_used == NULL);
1da177e4
LT		 2650
2651 command_status = p_tx_desc_used->cmd_sts;
8f518703 2652 if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
c8aaea25 2653 /* Still transmitting... */
8f518703
DF		 2654 err = ETH_ERROR;
2655 goto out;
2656 }
1da177e4
LT		 2657
2658 /* Pass the packet information to the caller */
2659 p_pkt_info->cmd_sts = command_status;
2660 p_pkt_info->return_info = mp->tx_skb[tx_desc_used];
4eaa3cb3
PG		 2661 p_pkt_info->buf_ptr = p_tx_desc_used->buf_ptr;
2662 p_pkt_info->byte_cnt = p_tx_desc_used->byte_cnt;
1da177e4
LT		 2663 mp->tx_skb[tx_desc_used] = NULL;
2664
2665 /* Update the next descriptor to release. */
2666 mp->tx_used_desc_q = (tx_desc_used + 1) % mp->tx_ring_size;
2667
f98e36f1
DF		 2668 BUG_ON(mp->tx_desc_count == 0);
2669 mp->tx_desc_count--;
b111ceb6 2670
8f518703
DF		 2671out:
2672 spin_unlock_irqrestore(&mp->lock, flags);
2673
2674 return err;
1da177e4
LT		 2675}
2676
2677/*
2678 * eth_port_receive - Get received information from Rx ring.
2679 *
2680 * DESCRIPTION:
2681 * This routine returns the received data to the caller. There is no
2682 * data copying during routine operation. All information is returned
2683 * using pointer to packet information struct passed from the caller.
2684 * If the routine exhausts Rx ring resources then the resource error flag
2685 * is set.
2686 *
2687 * INPUT:
2688 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2689 * struct pkt_info *p_pkt_info User packet buffer.
2690 *
2691 * OUTPUT:
2692 * Rx ring current and used indexes are updated.
2693 *
2694 * RETURN:
2695 * ETH_ERROR in case the routine can not access Rx desc ring.
2696 * ETH_QUEUE_FULL if Rx ring resources are exhausted.
2697 * ETH_END_OF_JOB if there is no received data.
2698 * ETH_OK otherwise.
2699 */
2700static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
2701 struct pkt_info *p_pkt_info)
2702{
2703 int rx_next_curr_desc, rx_curr_desc, rx_used_desc;
2704 volatile struct eth_rx_desc *p_rx_desc;
2705 unsigned int command_status;
8f518703 2706 unsigned long flags;
1da177e4
LT		 2707
2708 /* Do not process Rx ring in case of Rx ring resource error */
2709 if (mp->rx_resource_err)
2710 return ETH_QUEUE_FULL;
2711
8f518703
DF		 2712 spin_lock_irqsave(&mp->lock, flags);
2713
1da177e4
LT		 2714 /* Get the Rx Desc ring 'curr and 'used' indexes */
2715 rx_curr_desc = mp->rx_curr_desc_q;
2716 rx_used_desc = mp->rx_used_desc_q;
2717
2718 p_rx_desc = &mp->p_rx_desc_area[rx_curr_desc];
2719
2720 /* The following parameters are used to save readings from memory */
2721 command_status = p_rx_desc->cmd_sts;
2722 rmb();
2723
2724 /* Nothing to receive... */
8f518703
DF		 2725 if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
2726 spin_unlock_irqrestore(&mp->lock, flags);
1da177e4 2727 return ETH_END_OF_JOB;
8f518703 2728 }
1da177e4
LT		 2729
2730 p_pkt_info->byte_cnt = (p_rx_desc->byte_cnt) - RX_BUF_OFFSET;
2731 p_pkt_info->cmd_sts = command_status;
2732 p_pkt_info->buf_ptr = (p_rx_desc->buf_ptr) + RX_BUF_OFFSET;
2733 p_pkt_info->return_info = mp->rx_skb[rx_curr_desc];
2734 p_pkt_info->l4i_chk = p_rx_desc->buf_size;
2735
b4de9051
DF		 2736 /*
2737 * Clean the return info field to indicate that the
2738 * packet has been moved to the upper layers
2739 */
1da177e4
LT		 2740 mp->rx_skb[rx_curr_desc] = NULL;
2741
2742 /* Update current index in data structure */
2743 rx_next_curr_desc = (rx_curr_desc + 1) % mp->rx_ring_size;
2744 mp->rx_curr_desc_q = rx_next_curr_desc;
2745
2746 /* Rx descriptors exhausted. Set the Rx ring resource error flag */
2747 if (rx_next_curr_desc == rx_used_desc)
2748 mp->rx_resource_err = 1;
2749
8f518703
DF		 2750 spin_unlock_irqrestore(&mp->lock, flags);
2751
1da177e4
LT		 2752 return ETH_OK;
2753}
2754
2755/*
2756 * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
2757 *
2758 * DESCRIPTION:
2759 * This routine returns a Rx buffer back to the Rx ring. It retrieves the
2760 * next 'used' descriptor and attached the returned buffer to it.
2761 * In case the Rx ring was in "resource error" condition, where there are
2762 * no available Rx resources, the function resets the resource error flag.
2763 *
2764 * INPUT:
2765 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2766 * struct pkt_info *p_pkt_info Information on returned buffer.
2767 *
2768 * OUTPUT:
2769 * New available Rx resource in Rx descriptor ring.
2770 *
2771 * RETURN:
2772 * ETH_ERROR in case the routine can not access Rx desc ring.
2773 * ETH_OK otherwise.
2774 */
2775static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
2776 struct pkt_info *p_pkt_info)
2777{
2778 int used_rx_desc; /* Where to return Rx resource */
2779 volatile struct eth_rx_desc *p_used_rx_desc;
8f518703
DF		 2780 unsigned long flags;
2781
2782 spin_lock_irqsave(&mp->lock, flags);
1da177e4
LT		 2783
2784 /* Get 'used' Rx descriptor */
2785 used_rx_desc = mp->rx_used_desc_q;
2786 p_used_rx_desc = &mp->p_rx_desc_area[used_rx_desc];
2787
2788 p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
2789 p_used_rx_desc->buf_size = p_pkt_info->byte_cnt;
2790 mp->rx_skb[used_rx_desc] = p_pkt_info->return_info;
2791
2792 /* Flush the write pipe */
2793
2794 /* Return the descriptor to DMA ownership */
2795 wmb();
2796 p_used_rx_desc->cmd_sts =
2797 ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
2798 wmb();
2799
2800 /* Move the used descriptor pointer to the next descriptor */
2801 mp->rx_used_desc_q = (used_rx_desc + 1) % mp->rx_ring_size;
2802
2803 /* Any Rx return cancels the Rx resource error status */
2804 mp->rx_resource_err = 0;
2805
8f518703
DF		 2806 spin_unlock_irqrestore(&mp->lock, flags);
2807
1da177e4
LT		 2808 return ETH_OK;
2809}
2810
2811/************* Begin ethtool support *************************/
2812
2813struct mv643xx_stats {
2814 char stat_string[ETH_GSTRING_LEN];
2815 int sizeof_stat;
2816 int stat_offset;
2817};
2818
2819#define MV643XX_STAT(m) sizeof(((struct mv643xx_private *)0)->m), \
b4de9051 2820 offsetof(struct mv643xx_private, m)
1da177e4
LT		 2821
2822static const struct mv643xx_stats mv643xx_gstrings_stats[] = {
2823 { "rx_packets", MV643XX_STAT(stats.rx_packets) },
2824 { "tx_packets", MV643XX_STAT(stats.tx_packets) },
2825 { "rx_bytes", MV643XX_STAT(stats.rx_bytes) },
2826 { "tx_bytes", MV643XX_STAT(stats.tx_bytes) },
2827 { "rx_errors", MV643XX_STAT(stats.rx_errors) },
2828 { "tx_errors", MV643XX_STAT(stats.tx_errors) },
2829 { "rx_dropped", MV643XX_STAT(stats.rx_dropped) },
2830 { "tx_dropped", MV643XX_STAT(stats.tx_dropped) },
2831 { "good_octets_received", MV643XX_STAT(mib_counters.good_octets_received) },
2832 { "bad_octets_received", MV643XX_STAT(mib_counters.bad_octets_received) },
2833 { "internal_mac_transmit_err", MV643XX_STAT(mib_counters.internal_mac_transmit_err) },
2834 { "good_frames_received", MV643XX_STAT(mib_counters.good_frames_received) },
2835 { "bad_frames_received", MV643XX_STAT(mib_counters.bad_frames_received) },
2836 { "broadcast_frames_received", MV643XX_STAT(mib_counters.broadcast_frames_received) },
2837 { "multicast_frames_received", MV643XX_STAT(mib_counters.multicast_frames_received) },
2838 { "frames_64_octets", MV643XX_STAT(mib_counters.frames_64_octets) },
2839 { "frames_65_to_127_octets", MV643XX_STAT(mib_counters.frames_65_to_127_octets) },
2840 { "frames_128_to_255_octets", MV643XX_STAT(mib_counters.frames_128_to_255_octets) },
2841 { "frames_256_to_511_octets", MV643XX_STAT(mib_counters.frames_256_to_511_octets) },
2842 { "frames_512_to_1023_octets", MV643XX_STAT(mib_counters.frames_512_to_1023_octets) },
2843 { "frames_1024_to_max_octets", MV643XX_STAT(mib_counters.frames_1024_to_max_octets) },
2844 { "good_octets_sent", MV643XX_STAT(mib_counters.good_octets_sent) },
2845 { "good_frames_sent", MV643XX_STAT(mib_counters.good_frames_sent) },
2846 { "excessive_collision", MV643XX_STAT(mib_counters.excessive_collision) },
2847 { "multicast_frames_sent", MV643XX_STAT(mib_counters.multicast_frames_sent) },
2848 { "broadcast_frames_sent", MV643XX_STAT(mib_counters.broadcast_frames_sent) },
2849 { "unrec_mac_control_received", MV643XX_STAT(mib_counters.unrec_mac_control_received) },
2850 { "fc_sent", MV643XX_STAT(mib_counters.fc_sent) },
2851 { "good_fc_received", MV643XX_STAT(mib_counters.good_fc_received) },
2852 { "bad_fc_received", MV643XX_STAT(mib_counters.bad_fc_received) },
2853 { "undersize_received", MV643XX_STAT(mib_counters.undersize_received) },
2854 { "fragments_received", MV643XX_STAT(mib_counters.fragments_received) },
2855 { "oversize_received", MV643XX_STAT(mib_counters.oversize_received) },
2856 { "jabber_received", MV643XX_STAT(mib_counters.jabber_received) },
2857 { "mac_receive_error", MV643XX_STAT(mib_counters.mac_receive_error) },
2858 { "bad_crc_event", MV643XX_STAT(mib_counters.bad_crc_event) },
2859 { "collision", MV643XX_STAT(mib_counters.collision) },
2860 { "late_collision", MV643XX_STAT(mib_counters.late_collision) },
2861};
2862
2863#define MV643XX_STATS_LEN \
2864 sizeof(mv643xx_gstrings_stats) / sizeof(struct mv643xx_stats)
2865
b4de9051
DF		 2866static void mv643xx_get_drvinfo(struct net_device *netdev,
2867 struct ethtool_drvinfo *drvinfo)
1da177e4
LT		 2868{
2869 strncpy(drvinfo->driver, mv643xx_driver_name, 32);
2870 strncpy(drvinfo->version, mv643xx_driver_version, 32);
2871 strncpy(drvinfo->fw_version, "N/A", 32);
2872 strncpy(drvinfo->bus_info, "mv643xx", 32);
2873 drvinfo->n_stats = MV643XX_STATS_LEN;
2874}
2875
b4de9051 2876static int mv643xx_get_stats_count(struct net_device *netdev)
1da177e4
LT		 2877{
2878 return MV643XX_STATS_LEN;
2879}
2880
b4de9051
DF		 2881static void mv643xx_get_ethtool_stats(struct net_device *netdev,
2882 struct ethtool_stats *stats, uint64_t *data)
1da177e4
LT		 2883{
2884 struct mv643xx_private *mp = netdev->priv;
2885 int i;
2886
2887 eth_update_mib_counters(mp);
2888
b4de9051 2889 for (i = 0; i < MV643XX_STATS_LEN; i++) {
1da177e4 2890 char *p = (char *)mp+mv643xx_gstrings_stats[i].stat_offset;
b4de9051 2891 data[i] = (mv643xx_gstrings_stats[i].sizeof_stat ==
1da177e4
LT		 2892 sizeof(uint64_t)) ? *(uint64_t *)p : *(uint32_t *)p;
2893 }
2894}
2895
b4de9051
DF		 2896static void mv643xx_get_strings(struct net_device *netdev, uint32_t stringset,
2897 uint8_t *data)
1da177e4
LT		 2898{
2899 int i;
2900
2901 switch(stringset) {
2902 case ETH_SS_STATS:
2903 for (i=0; i < MV643XX_STATS_LEN; i++) {
b4de9051
DF		 2904 memcpy(data + i * ETH_GSTRING_LEN,
2905 mv643xx_gstrings_stats[i].stat_string,
2906 ETH_GSTRING_LEN);
1da177e4
LT		 2907 }
2908 break;
2909 }
2910}
2911
d0412d96
JC		 2912static u32 mv643xx_eth_get_link(struct net_device *dev)
2913{
2914 struct mv643xx_private *mp = netdev_priv(dev);
2915
2916 return mii_link_ok(&mp->mii);
2917}
2918
2919static int mv643xx_eth_nway_restart(struct net_device *dev)
2920{
2921 struct mv643xx_private *mp = netdev_priv(dev);
2922
2923 return mii_nway_restart(&mp->mii);
2924}
2925
2926static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2927{
2928 struct mv643xx_private *mp = netdev_priv(dev);
2929
2930 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
2931}
2932
1da177e4
LT		 2933static struct ethtool_ops mv643xx_ethtool_ops = {
2934 .get_settings = mv643xx_get_settings,
d0412d96 2935 .set_settings = mv643xx_set_settings,
1da177e4 2936 .get_drvinfo = mv643xx_get_drvinfo,
d0412d96 2937 .get_link = mv643xx_eth_get_link,
1da177e4
LT		 2938 .get_sg = ethtool_op_get_sg,
2939 .set_sg = ethtool_op_set_sg,
2940 .get_strings = mv643xx_get_strings,
2941 .get_stats_count = mv643xx_get_stats_count,
2942 .get_ethtool_stats = mv643xx_get_ethtool_stats,
d0412d96
JC		 2943 .get_strings = mv643xx_get_strings,
2944 .get_stats_count = mv643xx_get_stats_count,
2945 .get_ethtool_stats = mv643xx_get_ethtool_stats,
2946 .nway_reset = mv643xx_eth_nway_restart,
1da177e4
LT		 2947};
2948
2949/************* End ethtool support *************************/
Linux 6.x block layer and io_uring tree(s)