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mv643xx_eth: delete unused and uninteresting interrupt source mask bits
[linux-2.6-block.git] / drivers / net / mv643xx_eth.c
CommitLineData
1da177e4 1/*
9c1bbdfe 2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
1da177e4
LT		 3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
4547fa61
LB		 6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
1da177e4
LT		 8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
3bb8a18a 10 * written by Manish Lachwani
1da177e4
LT		 11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
c8aaea25 14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
1da177e4
LT		 15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
4547fa61
LB		 20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
1da177e4
LT		 23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36 */
a779d38c 37
1da177e4
LT		 38#include <linux/init.h>
39#include <linux/dma-mapping.h>
b6298c22 40#include <linux/in.h>
1da177e4
LT		 41#include <linux/tcp.h>
42#include <linux/udp.h>
43#include <linux/etherdevice.h>
1da177e4
LT		 44#include <linux/delay.h>
45#include <linux/ethtool.h>
d052d1be 46#include <linux/platform_device.h>
fbd6a754
LB		 47#include <linux/module.h>
48#include <linux/kernel.h>
49#include <linux/spinlock.h>
50#include <linux/workqueue.h>
51#include <linux/mii.h>
fbd6a754 52#include <linux/mv643xx_eth.h>
1da177e4
LT		 53#include <asm/io.h>
54#include <asm/types.h>
1da177e4 55#include <asm/system.h>
fbd6a754 56
e5371493 57static char mv643xx_eth_driver_name[] = "mv643xx_eth";
c4560318 58static char mv643xx_eth_driver_version[] = "1.3";
c9df406f 59
e5371493 60#define MV643XX_ETH_TX_FAST_REFILL
fbd6a754 61
fbd6a754
LB		 62/*
63 * Registers shared between all ports.
64 */
3cb4667c
LB		 65#define PHY_ADDR 0x0000
66#define SMI_REG 0x0004
45c5d3bc
LB		 67#define SMI_BUSY 0x10000000
68#define SMI_READ_VALID 0x08000000
69#define SMI_OPCODE_READ 0x04000000
70#define SMI_OPCODE_WRITE 0x00000000
71#define ERR_INT_CAUSE 0x0080
72#define ERR_INT_SMI_DONE 0x00000010
73#define ERR_INT_MASK 0x0084
3cb4667c
LB		 74#define WINDOW_BASE(w) (0x0200 + ((w) << 3))
75#define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
76#define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
77#define WINDOW_BAR_ENABLE 0x0290
78#define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
fbd6a754
LB		 79
80/*
81 * Per-port registers.
82 */
3cb4667c 83#define PORT_CONFIG(p) (0x0400 + ((p) << 10))
d9a073ea 84#define UNICAST_PROMISCUOUS_MODE 0x00000001
3cb4667c
LB		 85#define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
86#define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
87#define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
88#define SDMA_CONFIG(p) (0x041c + ((p) << 10))
89#define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
90#define PORT_STATUS(p) (0x0444 + ((p) << 10))
a2a41689 91#define TX_FIFO_EMPTY 0x00000400
ae9ae064 92#define TX_IN_PROGRESS 0x00000080
2f7eb47a
LB		 93#define PORT_SPEED_MASK 0x00000030
94#define PORT_SPEED_1000 0x00000010
95#define PORT_SPEED_100 0x00000020
96#define PORT_SPEED_10 0x00000000
97#define FLOW_CONTROL_ENABLED 0x00000008
98#define FULL_DUPLEX 0x00000004
81600eea 99#define LINK_UP 0x00000002
3cb4667c 100#define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
89df5fdc
LB		 101#define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10))
102#define TX_BW_RATE(p) (0x0450 + ((p) << 10))
3cb4667c 103#define TX_BW_MTU(p) (0x0458 + ((p) << 10))
89df5fdc 104#define TX_BW_BURST(p) (0x045c + ((p) << 10))
3cb4667c 105#define INT_CAUSE(p) (0x0460 + ((p) << 10))
8fa89bf5 106#define INT_TX_END_0 0x00080000
226bb6b7 107#define INT_TX_END 0x07f80000
befefe21 108#define INT_RX 0x000003fc
073a345c 109#define INT_EXT 0x00000002
3cb4667c 110#define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
befefe21
LB		 111#define INT_EXT_LINK_PHY 0x00110000
112#define INT_EXT_TX 0x000000ff
3cb4667c
LB		 113#define INT_MASK(p) (0x0468 + ((p) << 10))
114#define INT_MASK_EXT(p) (0x046c + ((p) << 10))
115#define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
1e881592
LB		 116#define TXQ_FIX_PRIO_CONF_MOVED(p) (0x04dc + ((p) << 10))
117#define TX_BW_RATE_MOVED(p) (0x04e0 + ((p) << 10))
118#define TX_BW_MTU_MOVED(p) (0x04e8 + ((p) << 10))
119#define TX_BW_BURST_MOVED(p) (0x04ec + ((p) << 10))
64da80a2 120#define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4))
3cb4667c 121#define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
3d6b35bc
LB		 122#define TXQ_CURRENT_DESC_PTR(p, q) (0x06c0 + ((p) << 10) + ((q) << 2))
123#define TXQ_BW_TOKENS(p, q) (0x0700 + ((p) << 10) + ((q) << 4))
124#define TXQ_BW_CONF(p, q) (0x0704 + ((p) << 10) + ((q) << 4))
125#define TXQ_BW_WRR_CONF(p, q) (0x0708 + ((p) << 10) + ((q) << 4))
3cb4667c
LB		 126#define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
127#define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
128#define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
129#define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
fbd6a754 130
2679a550
LB		 131
132/*
133 * SDMA configuration register.
134 */
cd4ccf76 135#define RX_BURST_SIZE_16_64BIT (4 << 1)
fbd6a754 136#define BLM_RX_NO_SWAP (1 << 4)
fbd6a754 137#define BLM_TX_NO_SWAP (1 << 5)
cd4ccf76 138#define TX_BURST_SIZE_16_64BIT (4 << 22)
fbd6a754
LB		 139
140#if defined(__BIG_ENDIAN)
141#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
cd4ccf76
LB		 142 RX_BURST_SIZE_16_64BIT | \
143 TX_BURST_SIZE_16_64BIT
fbd6a754
LB		 144#elif defined(__LITTLE_ENDIAN)
145#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
cd4ccf76 146 RX_BURST_SIZE_16_64BIT | \
fbd6a754
LB		 147 BLM_RX_NO_SWAP | \
148 BLM_TX_NO_SWAP | \
cd4ccf76 149 TX_BURST_SIZE_16_64BIT
fbd6a754
LB		 150#else
151#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
152#endif
153
2beff77b
LB		 154
155/*
156 * Port serial control register.
157 */
158#define SET_MII_SPEED_TO_100 (1 << 24)
159#define SET_GMII_SPEED_TO_1000 (1 << 23)
160#define SET_FULL_DUPLEX_MODE (1 << 21)
fbd6a754 161#define MAX_RX_PACKET_9700BYTE (5 << 17)
2beff77b
LB		 162#define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
163#define DO_NOT_FORCE_LINK_FAIL (1 << 10)
164#define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
165#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
166#define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
167#define FORCE_LINK_PASS (1 << 1)
168#define SERIAL_PORT_ENABLE (1 << 0)
fbd6a754 169
cc9754b3
LB		 170#define DEFAULT_RX_QUEUE_SIZE 400
171#define DEFAULT_TX_QUEUE_SIZE 800
fbd6a754 172
fbd6a754 173
7ca72a3b
LB		 174/*
175 * RX/TX descriptors.
fbd6a754
LB		 176 */
177#if defined(__BIG_ENDIAN)
cc9754b3 178struct rx_desc {
fbd6a754
LB		 179 u16 byte_cnt; /* Descriptor buffer byte count */
180 u16 buf_size; /* Buffer size */
181 u32 cmd_sts; /* Descriptor command status */
182 u32 next_desc_ptr; /* Next descriptor pointer */
183 u32 buf_ptr; /* Descriptor buffer pointer */
184};
185
cc9754b3 186struct tx_desc {
fbd6a754
LB		 187 u16 byte_cnt; /* buffer byte count */
188 u16 l4i_chk; /* CPU provided TCP checksum */
189 u32 cmd_sts; /* Command/status field */
190 u32 next_desc_ptr; /* Pointer to next descriptor */
191 u32 buf_ptr; /* pointer to buffer for this descriptor*/
192};
193#elif defined(__LITTLE_ENDIAN)
cc9754b3 194struct rx_desc {
fbd6a754
LB		 195 u32 cmd_sts; /* Descriptor command status */
196 u16 buf_size; /* Buffer size */
197 u16 byte_cnt; /* Descriptor buffer byte count */
198 u32 buf_ptr; /* Descriptor buffer pointer */
199 u32 next_desc_ptr; /* Next descriptor pointer */
200};
201
cc9754b3 202struct tx_desc {
fbd6a754
LB		 203 u32 cmd_sts; /* Command/status field */
204 u16 l4i_chk; /* CPU provided TCP checksum */
205 u16 byte_cnt; /* buffer byte count */
206 u32 buf_ptr; /* pointer to buffer for this descriptor*/
207 u32 next_desc_ptr; /* Pointer to next descriptor */
208};
209#else
210#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
211#endif
212
7ca72a3b 213/* RX & TX descriptor command */
cc9754b3 214#define BUFFER_OWNED_BY_DMA 0x80000000
7ca72a3b
LB		 215
216/* RX & TX descriptor status */
cc9754b3 217#define ERROR_SUMMARY 0x00000001
7ca72a3b
LB		 218
219/* RX descriptor status */
cc9754b3
LB		 220#define LAYER_4_CHECKSUM_OK 0x40000000
221#define RX_ENABLE_INTERRUPT 0x20000000
222#define RX_FIRST_DESC 0x08000000
223#define RX_LAST_DESC 0x04000000
7ca72a3b
LB		 224
225/* TX descriptor command */
cc9754b3
LB		 226#define TX_ENABLE_INTERRUPT 0x00800000
227#define GEN_CRC 0x00400000
228#define TX_FIRST_DESC 0x00200000
229#define TX_LAST_DESC 0x00100000
230#define ZERO_PADDING 0x00080000
231#define GEN_IP_V4_CHECKSUM 0x00040000
232#define GEN_TCP_UDP_CHECKSUM 0x00020000
233#define UDP_FRAME 0x00010000
e32b6617
LB		 234#define MAC_HDR_EXTRA_4_BYTES 0x00008000
235#define MAC_HDR_EXTRA_8_BYTES 0x00000200
7ca72a3b 236
cc9754b3 237#define TX_IHL_SHIFT 11
7ca72a3b
LB		 238
239
c9df406f 240/* global *******************************************************************/
e5371493 241struct mv643xx_eth_shared_private {
fc32b0e2
LB		 242 /*
243 * Ethernet controller base address.
244 */
cc9754b3 245 void __iomem *base;
c9df406f 246
fc0eb9f2
LB		 247 /*
248 * Points at the right SMI instance to use.
249 */
250 struct mv643xx_eth_shared_private *smi;
251
fc32b0e2
LB		 252 /*
253 * Protects access to SMI_REG, which is shared between ports.
254 */
2b3ba0e3 255 struct mutex phy_lock;
c9df406f 256
45c5d3bc
LB		 257 /*
258 * If we have access to the error interrupt pin (which is
259 * somewhat misnamed as it not only reflects internal errors
260 * but also reflects SMI completion), use that to wait for
261 * SMI access completion instead of polling the SMI busy bit.
262 */
263 int err_interrupt;
264 wait_queue_head_t smi_busy_wait;
265
fc32b0e2
LB		 266 /*
267 * Per-port MBUS window access register value.
268 */
c9df406f
LB		 269 u32 win_protect;
270
fc32b0e2
LB		 271 /*
272 * Hardware-specific parameters.
273 */
c9df406f 274 unsigned int t_clk;
773fc3ee 275 int extended_rx_coal_limit;
1e881592 276 int tx_bw_control_moved;
c9df406f
LB		 277};
278
279
280/* per-port *****************************************************************/
e5371493 281struct mib_counters {
fbd6a754
LB		 282 u64 good_octets_received;
283 u32 bad_octets_received;
284 u32 internal_mac_transmit_err;
285 u32 good_frames_received;
286 u32 bad_frames_received;
287 u32 broadcast_frames_received;
288 u32 multicast_frames_received;
289 u32 frames_64_octets;
290 u32 frames_65_to_127_octets;
291 u32 frames_128_to_255_octets;
292 u32 frames_256_to_511_octets;
293 u32 frames_512_to_1023_octets;
294 u32 frames_1024_to_max_octets;
295 u64 good_octets_sent;
296 u32 good_frames_sent;
297 u32 excessive_collision;
298 u32 multicast_frames_sent;
299 u32 broadcast_frames_sent;
300 u32 unrec_mac_control_received;
301 u32 fc_sent;
302 u32 good_fc_received;
303 u32 bad_fc_received;
304 u32 undersize_received;
305 u32 fragments_received;
306 u32 oversize_received;
307 u32 jabber_received;
308 u32 mac_receive_error;
309 u32 bad_crc_event;
310 u32 collision;
311 u32 late_collision;
312};
313
8a578111 314struct rx_queue {
64da80a2
LB		 315 int index;
316
8a578111
LB		 317 int rx_ring_size;
318
319 int rx_desc_count;
320 int rx_curr_desc;
321 int rx_used_desc;
322
323 struct rx_desc *rx_desc_area;
324 dma_addr_t rx_desc_dma;
325 int rx_desc_area_size;
326 struct sk_buff **rx_skb;
8a578111
LB		 327};
328
13d64285 329struct tx_queue {
3d6b35bc
LB		 330 int index;
331
13d64285 332 int tx_ring_size;
fbd6a754 333
13d64285
LB		 334 int tx_desc_count;
335 int tx_curr_desc;
336 int tx_used_desc;
fbd6a754 337
5daffe94 338 struct tx_desc *tx_desc_area;
fbd6a754
LB		 339 dma_addr_t tx_desc_dma;
340 int tx_desc_area_size;
341 struct sk_buff **tx_skb;
13d64285
LB		 342};
343
344struct mv643xx_eth_private {
345 struct mv643xx_eth_shared_private *shared;
fc32b0e2 346 int port_num;
13d64285 347
fc32b0e2 348 struct net_device *dev;
fbd6a754 349
fc32b0e2 350 int phy_addr;
fbd6a754 351
fbd6a754 352 spinlock_t lock;
fbd6a754 353
fc32b0e2
LB		 354 struct mib_counters mib_counters;
355 struct work_struct tx_timeout_task;
fbd6a754 356 struct mii_if_info mii;
8a578111
LB		 357
358 /*
359 * RX state.
360 */
361 int default_rx_ring_size;
362 unsigned long rx_desc_sram_addr;
363 int rx_desc_sram_size;
f7981c1c 364 int rxq_count;
8a578111 365 struct napi_struct napi;
2257e05c 366 struct timer_list rx_oom;
64da80a2 367 struct rx_queue rxq[8];
13d64285
LB		 368
369 /*
370 * TX state.
371 */
372 int default_tx_ring_size;
373 unsigned long tx_desc_sram_addr;
374 int tx_desc_sram_size;
f7981c1c 375 int txq_count;
3d6b35bc 376 struct tx_queue txq[8];
13d64285
LB		 377#ifdef MV643XX_ETH_TX_FAST_REFILL
378 int tx_clean_threshold;
379#endif
fbd6a754 380};
1da177e4 381
fbd6a754 382
c9df406f 383/* port register accessors **************************************************/
e5371493 384static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
c9df406f 385{
cc9754b3 386 return readl(mp->shared->base + offset);
c9df406f 387}
fbd6a754 388
e5371493 389static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
c9df406f 390{
cc9754b3 391 writel(data, mp->shared->base + offset);
c9df406f 392}
fbd6a754 393
fbd6a754 394
c9df406f 395/* rxq/txq helper functions *************************************************/
8a578111 396static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
c9df406f 397{
64da80a2 398 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
c9df406f 399}
fbd6a754 400
13d64285
LB		 401static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
402{
3d6b35bc 403 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
13d64285
LB		 404}
405
8a578111 406static void rxq_enable(struct rx_queue *rxq)
c9df406f 407{
8a578111 408 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
64da80a2 409 wrl(mp, RXQ_COMMAND(mp->port_num), 1 << rxq->index);
8a578111 410}
1da177e4 411
8a578111
LB		 412static void rxq_disable(struct rx_queue *rxq)
413{
414 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
64da80a2 415 u8 mask = 1 << rxq->index;
1da177e4 416
8a578111
LB		 417 wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8);
418 while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask)
419 udelay(10);
c9df406f
LB		 420}
421
6b368f68
LB		 422static void txq_reset_hw_ptr(struct tx_queue *txq)
423{
424 struct mv643xx_eth_private *mp = txq_to_mp(txq);
425 int off = TXQ_CURRENT_DESC_PTR(mp->port_num, txq->index);
426 u32 addr;
427
428 addr = (u32)txq->tx_desc_dma;
429 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
430 wrl(mp, off, addr);
431}
432
13d64285 433static void txq_enable(struct tx_queue *txq)
1da177e4 434{
13d64285 435 struct mv643xx_eth_private *mp = txq_to_mp(txq);
3d6b35bc 436 wrl(mp, TXQ_COMMAND(mp->port_num), 1 << txq->index);
1da177e4
LT		 437}
438
13d64285 439static void txq_disable(struct tx_queue *txq)
1da177e4 440{
13d64285 441 struct mv643xx_eth_private *mp = txq_to_mp(txq);
3d6b35bc 442 u8 mask = 1 << txq->index;
c9df406f 443
13d64285
LB		 444 wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8);
445 while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask)
446 udelay(10);
447}
448
449static void __txq_maybe_wake(struct tx_queue *txq)
450{
451 struct mv643xx_eth_private *mp = txq_to_mp(txq);
452
3d6b35bc
LB		 453 /*
454 * netif_{stop,wake}_queue() flow control only applies to
455 * the primary queue.
456 */
f7981c1c 457 BUG_ON(txq->index != 0);
3d6b35bc 458
17cd0a59 459 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
13d64285 460 netif_wake_queue(mp->dev);
1da177e4
LT		 461}
462
c9df406f
LB		 463
464/* rx ***********************************************************************/
13d64285 465static void txq_reclaim(struct tx_queue *txq, int force);
c9df406f 466
2257e05c 467static int rxq_refill(struct rx_queue *rxq, int budget, int *oom)
1da177e4 468{
2257e05c
LB		 469 int skb_size;
470 int refilled;
1da177e4 471
2257e05c
LB		 472 /*
473 * Reserve 2+14 bytes for an ethernet header (the hardware
474 * automatically prepends 2 bytes of dummy data to each
475 * received packet), 16 bytes for up to four VLAN tags, and
476 * 4 bytes for the trailing FCS -- 36 bytes total.
477 */
478 skb_size = rxq_to_mp(rxq)->dev->mtu + 36;
479
480 /*
481 * Make sure that the skb size is a multiple of 8 bytes, as
482 * the lower three bits of the receive descriptor's buffer
483 * size field are ignored by the hardware.
484 */
485 skb_size = (skb_size + 7) & ~7;
c0d0f2ca 486
2257e05c
LB		 487 refilled = 0;
488 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
de34f225
LB		 489 struct sk_buff *skb;
490 int unaligned;
491 int rx;
492
8a578111 493 skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1);
2257e05c
LB		 494 if (skb == NULL) {
495 *oom = 1;
1da177e4 496 break;
2257e05c 497 }
de34f225 498
908b637f 499 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
b44cd572 500 if (unaligned)
908b637f 501 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
de34f225 502
2257e05c 503 refilled++;
8a578111 504 rxq->rx_desc_count++;
9da78745
LB		 505
506 rx = rxq->rx_used_desc++;
507 if (rxq->rx_used_desc == rxq->rx_ring_size)
508 rxq->rx_used_desc = 0;
de34f225 509
8a578111
LB		 510 rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
511 skb_size, DMA_FROM_DEVICE);
512 rxq->rx_desc_area[rx].buf_size = skb_size;
513 rxq->rx_skb[rx] = skb;
de34f225 514 wmb();
8a578111 515 rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
de34f225
LB		 516 RX_ENABLE_INTERRUPT;
517 wmb();
518
fc32b0e2
LB		 519 /*
520 * The hardware automatically prepends 2 bytes of
521 * dummy data to each received packet, so that the
522 * IP header ends up 16-byte aligned.
523 */
524 skb_reserve(skb, 2);
1da177e4 525 }
de34f225 526
2257e05c 527 return refilled;
1da177e4
LT		 528}
529
8a578111 530static int rxq_process(struct rx_queue *rxq, int budget)
1da177e4 531{
8a578111
LB		 532 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
533 struct net_device_stats *stats = &mp->dev->stats;
534 int rx;
1da177e4 535
8a578111 536 rx = 0;
9e1f3772 537 while (rx < budget && rxq->rx_desc_count) {
fc32b0e2 538 struct rx_desc *rx_desc;
96587661 539 unsigned int cmd_sts;
fc32b0e2 540 struct sk_buff *skb;
ff561eef 541
8a578111 542 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
1da177e4 543
96587661 544 cmd_sts = rx_desc->cmd_sts;
2257e05c 545 if (cmd_sts & BUFFER_OWNED_BY_DMA)
96587661 546 break;
96587661 547 rmb();
1da177e4 548
8a578111
LB		 549 skb = rxq->rx_skb[rxq->rx_curr_desc];
550 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
ff561eef 551
9da78745
LB		 552 rxq->rx_curr_desc++;
553 if (rxq->rx_curr_desc == rxq->rx_ring_size)
554 rxq->rx_curr_desc = 0;
ff561eef 555
3a499481 556 dma_unmap_single(NULL, rx_desc->buf_ptr,
abe78717 557 rx_desc->buf_size, DMA_FROM_DEVICE);
8a578111
LB		 558 rxq->rx_desc_count--;
559 rx++;
b1dd9ca1 560
468d09f8
DF		 561 /*
562 * Update statistics.
fc32b0e2
LB		 563 *
564 * Note that the descriptor byte count includes 2 dummy
565 * bytes automatically inserted by the hardware at the
566 * start of the packet (which we don't count), and a 4
567 * byte CRC at the end of the packet (which we do count).
468d09f8 568 */
1da177e4 569 stats->rx_packets++;
fc32b0e2 570 stats->rx_bytes += rx_desc->byte_cnt - 2;
96587661 571
1da177e4 572 /*
fc32b0e2
LB		 573 * In case we received a packet without first / last bits
574 * on, or the error summary bit is set, the packet needs
575 * to be dropped.
1da177e4 576 */
96587661 577 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
cc9754b3 578 (RX_FIRST_DESC | RX_LAST_DESC))
96587661 579 || (cmd_sts & ERROR_SUMMARY)) {
1da177e4 580 stats->rx_dropped++;
fc32b0e2 581
96587661 582 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
cc9754b3 583 (RX_FIRST_DESC | RX_LAST_DESC)) {
1da177e4 584 if (net_ratelimit())
fc32b0e2
LB		 585 dev_printk(KERN_ERR, &mp->dev->dev,
586 "received packet spanning "
587 "multiple descriptors\n");
1da177e4 588 }
fc32b0e2 589
96587661 590 if (cmd_sts & ERROR_SUMMARY)
1da177e4
LT		 591 stats->rx_errors++;
592
78fff83b 593 dev_kfree_skb(skb);
1da177e4
LT		 594 } else {
595 /*
596 * The -4 is for the CRC in the trailer of the
597 * received packet
598 */
fc32b0e2 599 skb_put(skb, rx_desc->byte_cnt - 2 - 4);
1da177e4 600
96587661 601 if (cmd_sts & LAYER_4_CHECKSUM_OK) {
1da177e4
LT		 602 skb->ip_summed = CHECKSUM_UNNECESSARY;
603 skb->csum = htons(
96587661 604 (cmd_sts & 0x0007fff8) >> 3);
1da177e4 605 }
8a578111 606 skb->protocol = eth_type_trans(skb, mp->dev);
1da177e4 607 netif_receive_skb(skb);
1da177e4 608 }
fc32b0e2 609
8a578111 610 mp->dev->last_rx = jiffies;
1da177e4 611 }
fc32b0e2 612
8a578111 613 return rx;
1da177e4
LT		 614}
615
e5371493 616static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
d0412d96 617{
8a578111 618 struct mv643xx_eth_private *mp;
2257e05c
LB		 619 int work_done;
620 int oom;
64da80a2 621 int i;
8a578111
LB		 622
623 mp = container_of(napi, struct mv643xx_eth_private, napi);
d0412d96 624
e5371493 625#ifdef MV643XX_ETH_TX_FAST_REFILL
c9df406f 626 if (++mp->tx_clean_threshold > 5) {
c9df406f 627 mp->tx_clean_threshold = 0;
f7981c1c
LB		 628 for (i = 0; i < mp->txq_count; i++)
629 txq_reclaim(mp->txq + i, 0);
4dfc1c87 630
4fdeca3f
LB		 631 spin_lock_irq(&mp->lock);
632 __txq_maybe_wake(mp->txq);
633 spin_unlock_irq(&mp->lock);
d0412d96 634 }
c9df406f 635#endif
d0412d96 636
2257e05c
LB		 637 work_done = 0;
638 oom = 0;
f7981c1c
LB		 639 for (i = mp->rxq_count - 1; work_done < budget && i >= 0; i--) {
640 struct rx_queue *rxq = mp->rxq + i;
d0412d96 641
f7981c1c
LB		 642 work_done += rxq_process(rxq, budget - work_done);
643 work_done += rxq_refill(rxq, budget - work_done, &oom);
2257e05c
LB		 644 }
645
646 if (work_done < budget) {
647 if (oom)
648 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
8a578111 649 netif_rx_complete(mp->dev, napi);
226bb6b7 650 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
d0412d96 651 }
c9df406f 652
2257e05c
LB		 653 return work_done;
654}
655
656static inline void oom_timer_wrapper(unsigned long data)
657{
658 struct mv643xx_eth_private *mp = (void *)data;
659
660 napi_schedule(&mp->napi);
d0412d96
JC		 661}
662
c9df406f
LB		 663
664/* tx ***********************************************************************/
c9df406f 665static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1da177e4 666{
13d64285 667 int frag;
1da177e4 668
c9df406f 669 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
13d64285
LB		 670 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
671 if (fragp->size <= 8 && fragp->page_offset & 7)
c9df406f 672 return 1;
1da177e4 673 }
13d64285 674
c9df406f
LB		 675 return 0;
676}
7303fde8 677
13d64285 678static int txq_alloc_desc_index(struct tx_queue *txq)
c9df406f
LB		 679{
680 int tx_desc_curr;
d0412d96 681
13d64285 682 BUG_ON(txq->tx_desc_count >= txq->tx_ring_size);
1da177e4 683
9da78745
LB		 684 tx_desc_curr = txq->tx_curr_desc++;
685 if (txq->tx_curr_desc == txq->tx_ring_size)
686 txq->tx_curr_desc = 0;
e4d00fa9 687
13d64285 688 BUG_ON(txq->tx_curr_desc == txq->tx_used_desc);
468d09f8 689
c9df406f
LB		 690 return tx_desc_curr;
691}
468d09f8 692
13d64285 693static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
c9df406f 694{
13d64285 695 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 696 int frag;
1da177e4 697
13d64285
LB		 698 for (frag = 0; frag < nr_frags; frag++) {
699 skb_frag_t *this_frag;
700 int tx_index;
701 struct tx_desc *desc;
702
703 this_frag = &skb_shinfo(skb)->frags[frag];
704 tx_index = txq_alloc_desc_index(txq);
705 desc = &txq->tx_desc_area[tx_index];
706
707 /*
708 * The last fragment will generate an interrupt
709 * which will free the skb on TX completion.
710 */
711 if (frag == nr_frags - 1) {
712 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
713 ZERO_PADDING | TX_LAST_DESC |
714 TX_ENABLE_INTERRUPT;
715 txq->tx_skb[tx_index] = skb;
716 } else {
717 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
718 txq->tx_skb[tx_index] = NULL;
719 }
720
c9df406f
LB		 721 desc->l4i_chk = 0;
722 desc->byte_cnt = this_frag->size;
723 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
724 this_frag->page_offset,
725 this_frag->size,
726 DMA_TO_DEVICE);
727 }
1da177e4
LT		 728}
729
c9df406f
LB		 730static inline __be16 sum16_as_be(__sum16 sum)
731{
732 return (__force __be16)sum;
733}
1da177e4 734
13d64285 735static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
1da177e4 736{
8fa89bf5 737 struct mv643xx_eth_private *mp = txq_to_mp(txq);
13d64285 738 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 739 int tx_index;
cc9754b3 740 struct tx_desc *desc;
c9df406f
LB		 741 u32 cmd_sts;
742 int length;
1da177e4 743
cc9754b3 744 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
1da177e4 745
13d64285
LB		 746 tx_index = txq_alloc_desc_index(txq);
747 desc = &txq->tx_desc_area[tx_index];
c9df406f
LB		 748
749 if (nr_frags) {
13d64285 750 txq_submit_frag_skb(txq, skb);
c9df406f
LB		 751
752 length = skb_headlen(skb);
13d64285 753 txq->tx_skb[tx_index] = NULL;
c9df406f 754 } else {
cc9754b3 755 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
c9df406f 756 length = skb->len;
13d64285 757 txq->tx_skb[tx_index] = skb;
c9df406f
LB		 758 }
759
760 desc->byte_cnt = length;
761 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
762
763 if (skb->ip_summed == CHECKSUM_PARTIAL) {
e32b6617
LB		 764 int mac_hdr_len;
765
766 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
767 skb->protocol != htons(ETH_P_8021Q));
c9df406f 768
cc9754b3
LB		 769 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
770 GEN_IP_V4_CHECKSUM |
771 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
c9df406f 772
e32b6617
LB		 773 mac_hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
774 switch (mac_hdr_len - ETH_HLEN) {
775 case 0:
776 break;
777 case 4:
778 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
779 break;
780 case 8:
781 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
782 break;
783 case 12:
784 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
785 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
786 break;
787 default:
788 if (net_ratelimit())
789 dev_printk(KERN_ERR, &txq_to_mp(txq)->dev->dev,
790 "mac header length is %d?!\n", mac_hdr_len);
791 break;
792 }
793
c9df406f
LB		 794 switch (ip_hdr(skb)->protocol) {
795 case IPPROTO_UDP:
cc9754b3 796 cmd_sts |= UDP_FRAME;
c9df406f
LB		 797 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
798 break;
799 case IPPROTO_TCP:
800 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
801 break;
802 default:
803 BUG();
804 }
805 } else {
806 /* Errata BTS #50, IHL must be 5 if no HW checksum */
cc9754b3 807 cmd_sts |= 5 << TX_IHL_SHIFT;
c9df406f
LB		 808 desc->l4i_chk = 0;
809 }
810
811 /* ensure all other descriptors are written before first cmd_sts */
812 wmb();
813 desc->cmd_sts = cmd_sts;
814
8fa89bf5
LB		 815 /* clear TX_END interrupt status */
816 wrl(mp, INT_CAUSE(mp->port_num), ~(INT_TX_END_0 << txq->index));
817 rdl(mp, INT_CAUSE(mp->port_num));
818
c9df406f
LB		 819 /* ensure all descriptors are written before poking hardware */
820 wmb();
13d64285 821 txq_enable(txq);
c9df406f 822
13d64285 823 txq->tx_desc_count += nr_frags + 1;
1da177e4 824}
1da177e4 825
fc32b0e2 826static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 827{
e5371493 828 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 829 struct net_device_stats *stats = &dev->stats;
13d64285 830 struct tx_queue *txq;
c9df406f 831 unsigned long flags;
afdb57a2 832
c9df406f
LB		 833 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
834 stats->tx_dropped++;
fc32b0e2
LB		 835 dev_printk(KERN_DEBUG, &dev->dev,
836 "failed to linearize skb with tiny "
837 "unaligned fragment\n");
c9df406f
LB		 838 return NETDEV_TX_BUSY;
839 }
840
841 spin_lock_irqsave(&mp->lock, flags);
842
f7981c1c 843 txq = mp->txq;
13d64285 844
17cd0a59 845 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
c9df406f 846 spin_unlock_irqrestore(&mp->lock, flags);
f7981c1c 847 if (txq->index == 0 && net_ratelimit())
3d6b35bc
LB		 848 dev_printk(KERN_ERR, &dev->dev,
849 "primary tx queue full?!\n");
850 kfree_skb(skb);
851 return NETDEV_TX_OK;
c9df406f
LB		 852 }
853
13d64285 854 txq_submit_skb(txq, skb);
c9df406f
LB		 855 stats->tx_bytes += skb->len;
856 stats->tx_packets++;
857 dev->trans_start = jiffies;
858
f7981c1c 859 if (txq->index == 0) {
3d6b35bc
LB		 860 int entries_left;
861
862 entries_left = txq->tx_ring_size - txq->tx_desc_count;
17cd0a59 863 if (entries_left < MAX_SKB_FRAGS + 1)
3d6b35bc
LB		 864 netif_stop_queue(dev);
865 }
c9df406f
LB		 866
867 spin_unlock_irqrestore(&mp->lock, flags);
868
869 return NETDEV_TX_OK;
1da177e4
LT		 870}
871
c9df406f 872
89df5fdc
LB		 873/* tx rate control **********************************************************/
874/*
875 * Set total maximum TX rate (shared by all TX queues for this port)
876 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
877 */
878static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
879{
880 int token_rate;
881 int mtu;
882 int bucket_size;
883
884 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
885 if (token_rate > 1023)
886 token_rate = 1023;
887
888 mtu = (mp->dev->mtu + 255) >> 8;
889 if (mtu > 63)
890 mtu = 63;
891
892 bucket_size = (burst + 255) >> 8;
893 if (bucket_size > 65535)
894 bucket_size = 65535;
895
1e881592
LB		 896 if (mp->shared->tx_bw_control_moved) {
897 wrl(mp, TX_BW_RATE_MOVED(mp->port_num), token_rate);
898 wrl(mp, TX_BW_MTU_MOVED(mp->port_num), mtu);
899 wrl(mp, TX_BW_BURST_MOVED(mp->port_num), bucket_size);
900 } else {
901 wrl(mp, TX_BW_RATE(mp->port_num), token_rate);
902 wrl(mp, TX_BW_MTU(mp->port_num), mtu);
903 wrl(mp, TX_BW_BURST(mp->port_num), bucket_size);
904 }
89df5fdc
LB		 905}
906
907static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
908{
909 struct mv643xx_eth_private *mp = txq_to_mp(txq);
910 int token_rate;
911 int bucket_size;
912
913 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
914 if (token_rate > 1023)
915 token_rate = 1023;
916
917 bucket_size = (burst + 255) >> 8;
918 if (bucket_size > 65535)
919 bucket_size = 65535;
920
3d6b35bc
LB		 921 wrl(mp, TXQ_BW_TOKENS(mp->port_num, txq->index), token_rate << 14);
922 wrl(mp, TXQ_BW_CONF(mp->port_num, txq->index),
89df5fdc
LB		 923 (bucket_size << 10) | token_rate);
924}
925
926static void txq_set_fixed_prio_mode(struct tx_queue *txq)
927{
928 struct mv643xx_eth_private *mp = txq_to_mp(txq);
929 int off;
930 u32 val;
931
932 /*
933 * Turn on fixed priority mode.
934 */
1e881592
LB		 935 if (mp->shared->tx_bw_control_moved)
936 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
937 else
938 off = TXQ_FIX_PRIO_CONF(mp->port_num);
89df5fdc
LB		 939
940 val = rdl(mp, off);
3d6b35bc 941 val |= 1 << txq->index;
89df5fdc
LB		 942 wrl(mp, off, val);
943}
944
945static void txq_set_wrr(struct tx_queue *txq, int weight)
946{
947 struct mv643xx_eth_private *mp = txq_to_mp(txq);
948 int off;
949 u32 val;
950
951 /*
952 * Turn off fixed priority mode.
953 */
1e881592
LB		 954 if (mp->shared->tx_bw_control_moved)
955 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
956 else
957 off = TXQ_FIX_PRIO_CONF(mp->port_num);
89df5fdc
LB		 958
959 val = rdl(mp, off);
3d6b35bc 960 val &= ~(1 << txq->index);
89df5fdc
LB		 961 wrl(mp, off, val);
962
963 /*
964 * Configure WRR weight for this queue.
965 */
3d6b35bc 966 off = TXQ_BW_WRR_CONF(mp->port_num, txq->index);
89df5fdc
LB		 967
968 val = rdl(mp, off);
969 val = (val & ~0xff) | (weight & 0xff);
970 wrl(mp, off, val);
971}
972
973
c9df406f 974/* mii management interface *************************************************/
45c5d3bc
LB		 975static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id)
976{
977 struct mv643xx_eth_shared_private *msp = dev_id;
978
979 if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) {
980 writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE);
981 wake_up(&msp->smi_busy_wait);
982 return IRQ_HANDLED;
983 }
984
985 return IRQ_NONE;
986}
c9df406f 987
45c5d3bc 988static int smi_is_done(struct mv643xx_eth_shared_private *msp)
1da177e4 989{
45c5d3bc
LB		 990 return !(readl(msp->base + SMI_REG) & SMI_BUSY);
991}
1da177e4 992
45c5d3bc
LB		 993static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
994{
995 if (msp->err_interrupt == NO_IRQ) {
996 int i;
c9df406f 997
45c5d3bc
LB		 998 for (i = 0; !smi_is_done(msp); i++) {
999 if (i == 10)
1000 return -ETIMEDOUT;
1001 msleep(10);
c9df406f 1002 }
45c5d3bc
LB		 1003
1004 return 0;
1005 }
1006
1007 if (!wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
1008 msecs_to_jiffies(100)))
1009 return -ETIMEDOUT;
1010
1011 return 0;
1012}
1013
1014static int smi_reg_read(struct mv643xx_eth_private *mp,
1015 unsigned int addr, unsigned int reg)
1016{
fc0eb9f2 1017 struct mv643xx_eth_shared_private *msp = mp->shared->smi;
45c5d3bc
LB		 1018 void __iomem *smi_reg = msp->base + SMI_REG;
1019 int ret;
1020
1021 mutex_lock(&msp->phy_lock);
1022
1023 if (smi_wait_ready(msp)) {
1024 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1025 ret = -ETIMEDOUT;
1026 goto out;
1da177e4
LT		 1027 }
1028
fc32b0e2 1029 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1da177e4 1030
45c5d3bc
LB		 1031 if (smi_wait_ready(msp)) {
1032 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1033 ret = -ETIMEDOUT;
1034 goto out;
1035 }
1036
1037 ret = readl(smi_reg);
1038 if (!(ret & SMI_READ_VALID)) {
1039 printk("%s: SMI bus read not valid\n", mp->dev->name);
1040 ret = -ENODEV;
1041 goto out;
c9df406f
LB		 1042 }
1043
45c5d3bc
LB		 1044 ret &= 0xffff;
1045
c9df406f 1046out:
45c5d3bc
LB		 1047 mutex_unlock(&msp->phy_lock);
1048
1049 return ret;
1da177e4
LT		 1050}
1051
45c5d3bc
LB		 1052static int smi_reg_write(struct mv643xx_eth_private *mp, unsigned int addr,
1053 unsigned int reg, unsigned int value)
1da177e4 1054{
fc0eb9f2 1055 struct mv643xx_eth_shared_private *msp = mp->shared->smi;
45c5d3bc 1056 void __iomem *smi_reg = msp->base + SMI_REG;
1da177e4 1057
45c5d3bc 1058 mutex_lock(&msp->phy_lock);
c9df406f 1059
45c5d3bc
LB		 1060 if (smi_wait_ready(msp)) {
1061 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1062 mutex_unlock(&msp->phy_lock);
1063 return -ETIMEDOUT;
1da177e4
LT		 1064 }
1065
fc32b0e2
LB		 1066 writel(SMI_OPCODE_WRITE | (reg << 21) |
1067 (addr << 16) | (value & 0xffff), smi_reg);
45c5d3bc
LB		 1068
1069 mutex_unlock(&msp->phy_lock);
1070
1071 return 0;
c9df406f 1072}
1da177e4 1073
c9df406f
LB		 1074
1075/* mib counters *************************************************************/
fc32b0e2 1076static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
c9df406f 1077{
fc32b0e2 1078 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1da177e4
LT		 1079}
1080
fc32b0e2 1081static void mib_counters_clear(struct mv643xx_eth_private *mp)
d0412d96 1082{
fc32b0e2
LB		 1083 int i;
1084
1085 for (i = 0; i < 0x80; i += 4)
1086 mib_read(mp, i);
c9df406f 1087}
d0412d96 1088
fc32b0e2 1089static void mib_counters_update(struct mv643xx_eth_private *mp)
c9df406f 1090{
e5371493 1091 struct mib_counters *p = &mp->mib_counters;
4b8e3655 1092
fc32b0e2
LB		 1093 p->good_octets_received += mib_read(mp, 0x00);
1094 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
1095 p->bad_octets_received += mib_read(mp, 0x08);
1096 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1097 p->good_frames_received += mib_read(mp, 0x10);
1098 p->bad_frames_received += mib_read(mp, 0x14);
1099 p->broadcast_frames_received += mib_read(mp, 0x18);
1100 p->multicast_frames_received += mib_read(mp, 0x1c);
1101 p->frames_64_octets += mib_read(mp, 0x20);
1102 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1103 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1104 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1105 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1106 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1107 p->good_octets_sent += mib_read(mp, 0x38);
1108 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1109 p->good_frames_sent += mib_read(mp, 0x40);
1110 p->excessive_collision += mib_read(mp, 0x44);
1111 p->multicast_frames_sent += mib_read(mp, 0x48);
1112 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1113 p->unrec_mac_control_received += mib_read(mp, 0x50);
1114 p->fc_sent += mib_read(mp, 0x54);
1115 p->good_fc_received += mib_read(mp, 0x58);
1116 p->bad_fc_received += mib_read(mp, 0x5c);
1117 p->undersize_received += mib_read(mp, 0x60);
1118 p->fragments_received += mib_read(mp, 0x64);
1119 p->oversize_received += mib_read(mp, 0x68);
1120 p->jabber_received += mib_read(mp, 0x6c);
1121 p->mac_receive_error += mib_read(mp, 0x70);
1122 p->bad_crc_event += mib_read(mp, 0x74);
1123 p->collision += mib_read(mp, 0x78);
1124 p->late_collision += mib_read(mp, 0x7c);
d0412d96
JC		 1125}
1126
c9df406f
LB		 1127
1128/* ethtool ******************************************************************/
e5371493 1129struct mv643xx_eth_stats {
c9df406f
LB		 1130 char stat_string[ETH_GSTRING_LEN];
1131 int sizeof_stat;
16820054
LB		 1132 int netdev_off;
1133 int mp_off;
c9df406f
LB		 1134};
1135
16820054
LB		 1136#define SSTAT(m) \
1137 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1138 offsetof(struct net_device, stats.m), -1 }
1139
1140#define MIBSTAT(m) \
1141 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1142 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1143
1144static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1145 SSTAT(rx_packets),
1146 SSTAT(tx_packets),
1147 SSTAT(rx_bytes),
1148 SSTAT(tx_bytes),
1149 SSTAT(rx_errors),
1150 SSTAT(tx_errors),
1151 SSTAT(rx_dropped),
1152 SSTAT(tx_dropped),
1153 MIBSTAT(good_octets_received),
1154 MIBSTAT(bad_octets_received),
1155 MIBSTAT(internal_mac_transmit_err),
1156 MIBSTAT(good_frames_received),
1157 MIBSTAT(bad_frames_received),
1158 MIBSTAT(broadcast_frames_received),
1159 MIBSTAT(multicast_frames_received),
1160 MIBSTAT(frames_64_octets),
1161 MIBSTAT(frames_65_to_127_octets),
1162 MIBSTAT(frames_128_to_255_octets),
1163 MIBSTAT(frames_256_to_511_octets),
1164 MIBSTAT(frames_512_to_1023_octets),
1165 MIBSTAT(frames_1024_to_max_octets),
1166 MIBSTAT(good_octets_sent),
1167 MIBSTAT(good_frames_sent),
1168 MIBSTAT(excessive_collision),
1169 MIBSTAT(multicast_frames_sent),
1170 MIBSTAT(broadcast_frames_sent),
1171 MIBSTAT(unrec_mac_control_received),
1172 MIBSTAT(fc_sent),
1173 MIBSTAT(good_fc_received),
1174 MIBSTAT(bad_fc_received),
1175 MIBSTAT(undersize_received),
1176 MIBSTAT(fragments_received),
1177 MIBSTAT(oversize_received),
1178 MIBSTAT(jabber_received),
1179 MIBSTAT(mac_receive_error),
1180 MIBSTAT(bad_crc_event),
1181 MIBSTAT(collision),
1182 MIBSTAT(late_collision),
c9df406f
LB		 1183};
1184
e5371493 1185static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
d0412d96 1186{
e5371493 1187 struct mv643xx_eth_private *mp = netdev_priv(dev);
d0412d96
JC		 1188 int err;
1189
d0412d96 1190 err = mii_ethtool_gset(&mp->mii, cmd);
d0412d96 1191
fc32b0e2
LB		 1192 /*
1193 * The MAC does not support 1000baseT_Half.
1194 */
d0412d96
JC		 1195 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1196 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1197
1198 return err;
1199}
1200
bedfe324
LB		 1201static int mv643xx_eth_get_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1202{
81600eea
LB		 1203 struct mv643xx_eth_private *mp = netdev_priv(dev);
1204 u32 port_status;
1205
1206 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1207
bedfe324
LB		 1208 cmd->supported = SUPPORTED_MII;
1209 cmd->advertising = ADVERTISED_MII;
81600eea
LB		 1210 switch (port_status & PORT_SPEED_MASK) {
1211 case PORT_SPEED_10:
1212 cmd->speed = SPEED_10;
1213 break;
1214 case PORT_SPEED_100:
1215 cmd->speed = SPEED_100;
1216 break;
1217 case PORT_SPEED_1000:
1218 cmd->speed = SPEED_1000;
1219 break;
1220 default:
1221 cmd->speed = -1;
1222 break;
1223 }
1224 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
bedfe324
LB		 1225 cmd->port = PORT_MII;
1226 cmd->phy_address = 0;
1227 cmd->transceiver = XCVR_INTERNAL;
1228 cmd->autoneg = AUTONEG_DISABLE;
1229 cmd->maxtxpkt = 1;
1230 cmd->maxrxpkt = 1;
1231
1232 return 0;
1233}
1234
e5371493 1235static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4 1236{
e5371493 1237 struct mv643xx_eth_private *mp = netdev_priv(dev);
ab4384a6 1238
fc32b0e2
LB		 1239 /*
1240 * The MAC does not support 1000baseT_Half.
1241 */
1242 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1243
2b3ba0e3 1244 return mii_ethtool_sset(&mp->mii, cmd);
c9df406f 1245}
1da177e4 1246
bedfe324
LB		 1247static int mv643xx_eth_set_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1248{
1249 return -EINVAL;
1250}
1251
fc32b0e2
LB		 1252static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1253 struct ethtool_drvinfo *drvinfo)
c9df406f 1254{
e5371493
LB		 1255 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1256 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
c9df406f 1257 strncpy(drvinfo->fw_version, "N/A", 32);
fc32b0e2 1258 strncpy(drvinfo->bus_info, "platform", 32);
16820054 1259 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
c9df406f 1260}
1da177e4 1261
fc32b0e2 1262static int mv643xx_eth_nway_reset(struct net_device *dev)
c9df406f 1263{
e5371493 1264 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1265
c9df406f
LB		 1266 return mii_nway_restart(&mp->mii);
1267}
1da177e4 1268
bedfe324
LB		 1269static int mv643xx_eth_nway_reset_phyless(struct net_device *dev)
1270{
1271 return -EINVAL;
1272}
1273
c9df406f
LB		 1274static u32 mv643xx_eth_get_link(struct net_device *dev)
1275{
e5371493 1276 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1277
c9df406f
LB		 1278 return mii_link_ok(&mp->mii);
1279}
1da177e4 1280
bedfe324
LB		 1281static u32 mv643xx_eth_get_link_phyless(struct net_device *dev)
1282{
1283 return 1;
1284}
1285
fc32b0e2
LB		 1286static void mv643xx_eth_get_strings(struct net_device *dev,
1287 uint32_t stringset, uint8_t *data)
c9df406f
LB		 1288{
1289 int i;
1da177e4 1290
fc32b0e2
LB		 1291 if (stringset == ETH_SS_STATS) {
1292 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
c9df406f 1293 memcpy(data + i * ETH_GSTRING_LEN,
16820054 1294 mv643xx_eth_stats[i].stat_string,
e5371493 1295 ETH_GSTRING_LEN);
c9df406f 1296 }
c9df406f
LB		 1297 }
1298}
1da177e4 1299
fc32b0e2
LB		 1300static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1301 struct ethtool_stats *stats,
1302 uint64_t *data)
c9df406f 1303{
b9873841 1304 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 1305 int i;
1da177e4 1306
fc32b0e2 1307 mib_counters_update(mp);
1da177e4 1308
16820054
LB		 1309 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1310 const struct mv643xx_eth_stats *stat;
1311 void *p;
1312
1313 stat = mv643xx_eth_stats + i;
1314
1315 if (stat->netdev_off >= 0)
1316 p = ((void *)mp->dev) + stat->netdev_off;
1317 else
1318 p = ((void *)mp) + stat->mp_off;
1319
1320 data[i] = (stat->sizeof_stat == 8) ?
1321 *(uint64_t *)p : *(uint32_t *)p;
1da177e4 1322 }
c9df406f 1323}
1da177e4 1324
fc32b0e2 1325static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
c9df406f 1326{
fc32b0e2 1327 if (sset == ETH_SS_STATS)
16820054 1328 return ARRAY_SIZE(mv643xx_eth_stats);
fc32b0e2
LB		 1329
1330 return -EOPNOTSUPP;
c9df406f 1331}
1da177e4 1332
e5371493 1333static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
fc32b0e2
LB		 1334 .get_settings = mv643xx_eth_get_settings,
1335 .set_settings = mv643xx_eth_set_settings,
1336 .get_drvinfo = mv643xx_eth_get_drvinfo,
1337 .nway_reset = mv643xx_eth_nway_reset,
1338 .get_link = mv643xx_eth_get_link,
c9df406f 1339 .set_sg = ethtool_op_set_sg,
fc32b0e2
LB		 1340 .get_strings = mv643xx_eth_get_strings,
1341 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
e5371493 1342 .get_sset_count = mv643xx_eth_get_sset_count,
c9df406f 1343};
1da177e4 1344
bedfe324
LB		 1345static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless = {
1346 .get_settings = mv643xx_eth_get_settings_phyless,
1347 .set_settings = mv643xx_eth_set_settings_phyless,
1348 .get_drvinfo = mv643xx_eth_get_drvinfo,
1349 .nway_reset = mv643xx_eth_nway_reset_phyless,
1350 .get_link = mv643xx_eth_get_link_phyless,
1351 .set_sg = ethtool_op_set_sg,
1352 .get_strings = mv643xx_eth_get_strings,
1353 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1354 .get_sset_count = mv643xx_eth_get_sset_count,
1355};
1356
bea3348e 1357
c9df406f 1358/* address handling *********************************************************/
5daffe94 1359static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
c9df406f 1360{
c9df406f
LB		 1361 unsigned int mac_h;
1362 unsigned int mac_l;
1da177e4 1363
fc32b0e2
LB		 1364 mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num));
1365 mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num));
1da177e4 1366
5daffe94
LB		 1367 addr[0] = (mac_h >> 24) & 0xff;
1368 addr[1] = (mac_h >> 16) & 0xff;
1369 addr[2] = (mac_h >> 8) & 0xff;
1370 addr[3] = mac_h & 0xff;
1371 addr[4] = (mac_l >> 8) & 0xff;
1372 addr[5] = mac_l & 0xff;
c9df406f 1373}
1da177e4 1374
e5371493 1375static void init_mac_tables(struct mv643xx_eth_private *mp)
c9df406f 1376{
fc32b0e2 1377 int i;
1da177e4 1378
fc32b0e2
LB		 1379 for (i = 0; i < 0x100; i += 4) {
1380 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1381 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
c9df406f 1382 }
fc32b0e2
LB		 1383
1384 for (i = 0; i < 0x10; i += 4)
1385 wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
c9df406f 1386}
d0412d96 1387
e5371493 1388static void set_filter_table_entry(struct mv643xx_eth_private *mp,
fc32b0e2 1389 int table, unsigned char entry)
c9df406f
LB		 1390{
1391 unsigned int table_reg;
ab4384a6 1392
c9df406f 1393 /* Set "accepts frame bit" at specified table entry */
fc32b0e2
LB		 1394 table_reg = rdl(mp, table + (entry & 0xfc));
1395 table_reg |= 0x01 << (8 * (entry & 3));
1396 wrl(mp, table + (entry & 0xfc), table_reg);
1da177e4
LT		 1397}
1398
5daffe94 1399static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1da177e4 1400{
c9df406f
LB		 1401 unsigned int mac_h;
1402 unsigned int mac_l;
1403 int table;
1da177e4 1404
fc32b0e2
LB		 1405 mac_l = (addr[4] << 8) | addr[5];
1406 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
ff561eef 1407
fc32b0e2
LB		 1408 wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l);
1409 wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h);
1da177e4 1410
fc32b0e2 1411 table = UNICAST_TABLE(mp->port_num);
5daffe94 1412 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1da177e4
LT		 1413}
1414
fc32b0e2 1415static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1da177e4 1416{
e5371493 1417 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1418
fc32b0e2
LB		 1419 /* +2 is for the offset of the HW addr type */
1420 memcpy(dev->dev_addr, addr + 2, 6);
1421
cc9754b3
LB		 1422 init_mac_tables(mp);
1423 uc_addr_set(mp, dev->dev_addr);
1da177e4
LT		 1424
1425 return 0;
1426}
1427
69876569
LB		 1428static int addr_crc(unsigned char *addr)
1429{
1430 int crc = 0;
1431 int i;
1432
1433 for (i = 0; i < 6; i++) {
1434 int j;
1435
1436 crc = (crc ^ addr[i]) << 8;
1437 for (j = 7; j >= 0; j--) {
1438 if (crc & (0x100 << j))
1439 crc ^= 0x107 << j;
1440 }
1441 }
1442
1443 return crc;
1444}
1445
fc32b0e2 1446static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1da177e4 1447{
fc32b0e2
LB		 1448 struct mv643xx_eth_private *mp = netdev_priv(dev);
1449 u32 port_config;
1450 struct dev_addr_list *addr;
1451 int i;
c8aaea25 1452
fc32b0e2
LB		 1453 port_config = rdl(mp, PORT_CONFIG(mp->port_num));
1454 if (dev->flags & IFF_PROMISC)
1455 port_config |= UNICAST_PROMISCUOUS_MODE;
1456 else
1457 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1458 wrl(mp, PORT_CONFIG(mp->port_num), port_config);
1da177e4 1459
fc32b0e2
LB		 1460 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1461 int port_num = mp->port_num;
1462 u32 accept = 0x01010101;
c8aaea25 1463
fc32b0e2
LB		 1464 for (i = 0; i < 0x100; i += 4) {
1465 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1466 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
c9df406f
LB		 1467 }
1468 return;
1469 }
c8aaea25 1470
fc32b0e2
LB		 1471 for (i = 0; i < 0x100; i += 4) {
1472 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1473 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1da177e4
LT		 1474 }
1475
fc32b0e2
LB		 1476 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1477 u8 *a = addr->da_addr;
1478 int table;
324ff2c1 1479
fc32b0e2
LB		 1480 if (addr->da_addrlen != 6)
1481 continue;
1da177e4 1482
fc32b0e2
LB		 1483 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1484 table = SPECIAL_MCAST_TABLE(mp->port_num);
1485 set_filter_table_entry(mp, table, a[5]);
1486 } else {
1487 int crc = addr_crc(a);
1da177e4 1488
fc32b0e2
LB		 1489 table = OTHER_MCAST_TABLE(mp->port_num);
1490 set_filter_table_entry(mp, table, crc);
1491 }
1492 }
c9df406f 1493}
c8aaea25 1494
c8aaea25 1495
c9df406f 1496/* rx/tx queue initialisation ***********************************************/
64da80a2 1497static int rxq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1498{
64da80a2 1499 struct rx_queue *rxq = mp->rxq + index;
8a578111
LB		 1500 struct rx_desc *rx_desc;
1501 int size;
c9df406f
LB		 1502 int i;
1503
64da80a2
LB		 1504 rxq->index = index;
1505
8a578111
LB		 1506 rxq->rx_ring_size = mp->default_rx_ring_size;
1507
1508 rxq->rx_desc_count = 0;
1509 rxq->rx_curr_desc = 0;
1510 rxq->rx_used_desc = 0;
1511
1512 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1513
f7981c1c 1514 if (index == 0 && size <= mp->rx_desc_sram_size) {
8a578111
LB		 1515 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1516 mp->rx_desc_sram_size);
1517 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1518 } else {
1519 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1520 &rxq->rx_desc_dma,
1521 GFP_KERNEL);
f7ea3337
PJ		 1522 }
1523
8a578111
LB		 1524 if (rxq->rx_desc_area == NULL) {
1525 dev_printk(KERN_ERR, &mp->dev->dev,
1526 "can't allocate rx ring (%d bytes)\n", size);
1527 goto out;
1528 }
1529 memset(rxq->rx_desc_area, 0, size);
1da177e4 1530
8a578111
LB		 1531 rxq->rx_desc_area_size = size;
1532 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1533 GFP_KERNEL);
1534 if (rxq->rx_skb == NULL) {
1535 dev_printk(KERN_ERR, &mp->dev->dev,
1536 "can't allocate rx skb ring\n");
1537 goto out_free;
1538 }
1539
1540 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1541 for (i = 0; i < rxq->rx_ring_size; i++) {
9da78745
LB		 1542 int nexti;
1543
1544 nexti = i + 1;
1545 if (nexti == rxq->rx_ring_size)
1546 nexti = 0;
1547
8a578111
LB		 1548 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1549 nexti * sizeof(struct rx_desc);
1550 }
1551
8a578111
LB		 1552 return 0;
1553
1554
1555out_free:
f7981c1c 1556 if (index == 0 && size <= mp->rx_desc_sram_size)
8a578111
LB		 1557 iounmap(rxq->rx_desc_area);
1558 else
1559 dma_free_coherent(NULL, size,
1560 rxq->rx_desc_area,
1561 rxq->rx_desc_dma);
1562
1563out:
1564 return -ENOMEM;
c9df406f 1565}
c8aaea25 1566
8a578111 1567static void rxq_deinit(struct rx_queue *rxq)
c9df406f 1568{
8a578111
LB		 1569 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1570 int i;
1571
1572 rxq_disable(rxq);
c8aaea25 1573
8a578111
LB		 1574 for (i = 0; i < rxq->rx_ring_size; i++) {
1575 if (rxq->rx_skb[i]) {
1576 dev_kfree_skb(rxq->rx_skb[i]);
1577 rxq->rx_desc_count--;
1da177e4 1578 }
c8aaea25 1579 }
1da177e4 1580
8a578111
LB		 1581 if (rxq->rx_desc_count) {
1582 dev_printk(KERN_ERR, &mp->dev->dev,
1583 "error freeing rx ring -- %d skbs stuck\n",
1584 rxq->rx_desc_count);
1585 }
1586
f7981c1c 1587 if (rxq->index == 0 &&
64da80a2 1588 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
8a578111 1589 iounmap(rxq->rx_desc_area);
c9df406f 1590 else
8a578111
LB		 1591 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1592 rxq->rx_desc_area, rxq->rx_desc_dma);
1593
1594 kfree(rxq->rx_skb);
c9df406f 1595}
1da177e4 1596
3d6b35bc 1597static int txq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1598{
3d6b35bc 1599 struct tx_queue *txq = mp->txq + index;
13d64285
LB		 1600 struct tx_desc *tx_desc;
1601 int size;
c9df406f 1602 int i;
1da177e4 1603
3d6b35bc
LB		 1604 txq->index = index;
1605
13d64285
LB		 1606 txq->tx_ring_size = mp->default_tx_ring_size;
1607
1608 txq->tx_desc_count = 0;
1609 txq->tx_curr_desc = 0;
1610 txq->tx_used_desc = 0;
1611
1612 size = txq->tx_ring_size * sizeof(struct tx_desc);
1613
f7981c1c 1614 if (index == 0 && size <= mp->tx_desc_sram_size) {
13d64285
LB		 1615 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1616 mp->tx_desc_sram_size);
1617 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1618 } else {
1619 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1620 &txq->tx_desc_dma,
1621 GFP_KERNEL);
1622 }
1623
1624 if (txq->tx_desc_area == NULL) {
1625 dev_printk(KERN_ERR, &mp->dev->dev,
1626 "can't allocate tx ring (%d bytes)\n", size);
1627 goto out;
c9df406f 1628 }
13d64285
LB		 1629 memset(txq->tx_desc_area, 0, size);
1630
1631 txq->tx_desc_area_size = size;
1632 txq->tx_skb = kmalloc(txq->tx_ring_size * sizeof(*txq->tx_skb),
1633 GFP_KERNEL);
1634 if (txq->tx_skb == NULL) {
1635 dev_printk(KERN_ERR, &mp->dev->dev,
1636 "can't allocate tx skb ring\n");
1637 goto out_free;
1638 }
1639
1640 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1641 for (i = 0; i < txq->tx_ring_size; i++) {
6b368f68 1642 struct tx_desc *txd = tx_desc + i;
9da78745
LB		 1643 int nexti;
1644
1645 nexti = i + 1;
1646 if (nexti == txq->tx_ring_size)
1647 nexti = 0;
6b368f68
LB		 1648
1649 txd->cmd_sts = 0;
1650 txd->next_desc_ptr = txq->tx_desc_dma +
13d64285
LB		 1651 nexti * sizeof(struct tx_desc);
1652 }
1653
1654 return 0;
1655
c9df406f 1656
13d64285 1657out_free:
f7981c1c 1658 if (index == 0 && size <= mp->tx_desc_sram_size)
13d64285
LB		 1659 iounmap(txq->tx_desc_area);
1660 else
1661 dma_free_coherent(NULL, size,
1662 txq->tx_desc_area,
1663 txq->tx_desc_dma);
c9df406f 1664
13d64285
LB		 1665out:
1666 return -ENOMEM;
c8aaea25 1667}
1da177e4 1668
13d64285 1669static void txq_reclaim(struct tx_queue *txq, int force)
c8aaea25 1670{
13d64285 1671 struct mv643xx_eth_private *mp = txq_to_mp(txq);
c8aaea25 1672 unsigned long flags;
1da177e4 1673
13d64285
LB		 1674 spin_lock_irqsave(&mp->lock, flags);
1675 while (txq->tx_desc_count > 0) {
1676 int tx_index;
1677 struct tx_desc *desc;
1678 u32 cmd_sts;
1679 struct sk_buff *skb;
1680 dma_addr_t addr;
1681 int count;
4d64e718 1682
13d64285
LB		 1683 tx_index = txq->tx_used_desc;
1684 desc = &txq->tx_desc_area[tx_index];
c9df406f 1685 cmd_sts = desc->cmd_sts;
4d64e718 1686
6b368f68
LB		 1687 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
1688 if (!force)
1689 break;
1690 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
1691 }
1da177e4 1692
9da78745
LB		 1693 txq->tx_used_desc = tx_index + 1;
1694 if (txq->tx_used_desc == txq->tx_ring_size)
1695 txq->tx_used_desc = 0;
13d64285 1696 txq->tx_desc_count--;
1da177e4 1697
c9df406f
LB		 1698 addr = desc->buf_ptr;
1699 count = desc->byte_cnt;
13d64285
LB		 1700 skb = txq->tx_skb[tx_index];
1701 txq->tx_skb[tx_index] = NULL;
c8aaea25 1702
cc9754b3 1703 if (cmd_sts & ERROR_SUMMARY) {
13d64285
LB		 1704 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
1705 mp->dev->stats.tx_errors++;
c9df406f 1706 }
1da177e4 1707
13d64285
LB		 1708 /*
1709 * Drop mp->lock while we free the skb.
1710 */
c9df406f 1711 spin_unlock_irqrestore(&mp->lock, flags);
1da177e4 1712
cc9754b3 1713 if (cmd_sts & TX_FIRST_DESC)
c9df406f
LB		 1714 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
1715 else
1716 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
c2e5b352 1717
c9df406f
LB		 1718 if (skb)
1719 dev_kfree_skb_irq(skb);
63c9e549 1720
13d64285 1721 spin_lock_irqsave(&mp->lock, flags);
c9df406f 1722 }
13d64285 1723 spin_unlock_irqrestore(&mp->lock, flags);
c9df406f 1724}
1da177e4 1725
13d64285 1726static void txq_deinit(struct tx_queue *txq)
c9df406f 1727{
13d64285 1728 struct mv643xx_eth_private *mp = txq_to_mp(txq);
fa3959f4 1729
13d64285
LB		 1730 txq_disable(txq);
1731 txq_reclaim(txq, 1);
1da177e4 1732
13d64285 1733 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1da177e4 1734
f7981c1c 1735 if (txq->index == 0 &&
3d6b35bc 1736 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
13d64285 1737 iounmap(txq->tx_desc_area);
c9df406f 1738 else
13d64285
LB		 1739 dma_free_coherent(NULL, txq->tx_desc_area_size,
1740 txq->tx_desc_area, txq->tx_desc_dma);
1741
1742 kfree(txq->tx_skb);
c9df406f 1743}
1da177e4 1744
1da177e4 1745
c9df406f 1746/* netdev ops and related ***************************************************/
2f7eb47a
LB		 1747static void handle_link_event(struct mv643xx_eth_private *mp)
1748{
1749 struct net_device *dev = mp->dev;
1750 u32 port_status;
1751 int speed;
1752 int duplex;
1753 int fc;
1754
1755 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1756 if (!(port_status & LINK_UP)) {
1757 if (netif_carrier_ok(dev)) {
1758 int i;
1759
1760 printk(KERN_INFO "%s: link down\n", dev->name);
1761
1762 netif_carrier_off(dev);
2f7eb47a 1763
f7981c1c 1764 for (i = 0; i < mp->txq_count; i++) {
2f7eb47a
LB		 1765 struct tx_queue *txq = mp->txq + i;
1766
f7981c1c
LB		 1767 txq_reclaim(txq, 1);
1768 txq_reset_hw_ptr(txq);
2f7eb47a
LB		 1769 }
1770 }
1771 return;
1772 }
1773
1774 switch (port_status & PORT_SPEED_MASK) {
1775 case PORT_SPEED_10:
1776 speed = 10;
1777 break;
1778 case PORT_SPEED_100:
1779 speed = 100;
1780 break;
1781 case PORT_SPEED_1000:
1782 speed = 1000;
1783 break;
1784 default:
1785 speed = -1;
1786 break;
1787 }
1788 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
1789 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
1790
1791 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
1792 "flow control %sabled\n", dev->name,
1793 speed, duplex ? "full" : "half",
1794 fc ? "en" : "dis");
1795
4fdeca3f 1796 if (!netif_carrier_ok(dev))
2f7eb47a 1797 netif_carrier_on(dev);
2f7eb47a
LB		 1798}
1799
fc32b0e2 1800static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
c9df406f
LB		 1801{
1802 struct net_device *dev = (struct net_device *)dev_id;
e5371493 1803 struct mv643xx_eth_private *mp = netdev_priv(dev);
fc32b0e2
LB		 1804 u32 int_cause;
1805 u32 int_cause_ext;
ce4e2e45 1806
226bb6b7
LB		 1807 int_cause = rdl(mp, INT_CAUSE(mp->port_num)) &
1808 (INT_TX_END | INT_RX | INT_EXT);
fc32b0e2
LB		 1809 if (int_cause == 0)
1810 return IRQ_NONE;
1811
1812 int_cause_ext = 0;
cc9754b3 1813 if (int_cause & INT_EXT) {
13d64285 1814 int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num))
befefe21 1815 & (INT_EXT_LINK_PHY | INT_EXT_TX);
13d64285 1816 wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext);
c9df406f 1817 }
1da177e4 1818
befefe21 1819 if (int_cause_ext & INT_EXT_LINK_PHY)
2f7eb47a 1820 handle_link_event(mp);
1da177e4 1821
64da80a2
LB		 1822 /*
1823 * RxBuffer or RxError set for any of the 8 queues?
1824 */
cc9754b3 1825 if (int_cause & INT_RX) {
819ddcaf 1826 wrl(mp, INT_CAUSE(mp->port_num), ~(int_cause & INT_RX));
13d64285 1827 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
13d64285 1828 rdl(mp, INT_MASK(mp->port_num));
1da177e4 1829
2257e05c 1830 napi_schedule(&mp->napi);
84dd619e 1831 }
fc32b0e2 1832
3d6b35bc
LB		 1833 /*
1834 * TxBuffer or TxError set for any of the 8 queues?
1835 */
13d64285 1836 if (int_cause_ext & INT_EXT_TX) {
3d6b35bc
LB		 1837 int i;
1838
f7981c1c
LB		 1839 for (i = 0; i < mp->txq_count; i++)
1840 txq_reclaim(mp->txq + i, 0);
8fa89bf5
LB		 1841
1842 /*
1843 * Enough space again in the primary TX queue for a
1844 * full packet?
1845 */
4fdeca3f
LB		 1846 spin_lock(&mp->lock);
1847 __txq_maybe_wake(mp->txq);
1848 spin_unlock(&mp->lock);
226bb6b7 1849 }
3d6b35bc 1850
226bb6b7
LB		 1851 /*
1852 * Any TxEnd interrupts?
1853 */
1854 if (int_cause & INT_TX_END) {
1855 int i;
1856
1857 wrl(mp, INT_CAUSE(mp->port_num), ~(int_cause & INT_TX_END));
8fa89bf5
LB		 1858
1859 spin_lock(&mp->lock);
226bb6b7
LB		 1860 for (i = 0; i < 8; i++) {
1861 struct tx_queue *txq = mp->txq + i;
8fa89bf5
LB		 1862 u32 hw_desc_ptr;
1863 u32 expected_ptr;
1864
1865 if ((int_cause & (INT_TX_END_0 << i)) == 0)
1866 continue;
1867
1868 hw_desc_ptr =
1869 rdl(mp, TXQ_CURRENT_DESC_PTR(mp->port_num, i));
1870 expected_ptr = (u32)txq->tx_desc_dma +
1871 txq->tx_curr_desc * sizeof(struct tx_desc);
1872
1873 if (hw_desc_ptr != expected_ptr)
226bb6b7
LB		 1874 txq_enable(txq);
1875 }
8fa89bf5 1876 spin_unlock(&mp->lock);
13d64285 1877 }
1da177e4 1878
c9df406f 1879 return IRQ_HANDLED;
1da177e4
LT		 1880}
1881
e5371493 1882static void phy_reset(struct mv643xx_eth_private *mp)
1da177e4 1883{
45c5d3bc
LB		 1884 int data;
1885
1886 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
1887 if (data < 0)
1888 return;
1da177e4 1889
7f106c1d 1890 data |= BMCR_RESET;
45c5d3bc
LB		 1891 if (smi_reg_write(mp, mp->phy_addr, MII_BMCR, data) < 0)
1892 return;
1da177e4 1893
c9df406f 1894 do {
45c5d3bc
LB		 1895 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
1896 } while (data >= 0 && data & BMCR_RESET);
1da177e4
LT		 1897}
1898
fc32b0e2 1899static void port_start(struct mv643xx_eth_private *mp)
1da177e4 1900{
d0412d96 1901 u32 pscr;
8a578111 1902 int i;
1da177e4 1903
bedfe324
LB		 1904 /*
1905 * Perform PHY reset, if there is a PHY.
1906 */
1907 if (mp->phy_addr != -1) {
1908 struct ethtool_cmd cmd;
1909
1910 mv643xx_eth_get_settings(mp->dev, &cmd);
1911 phy_reset(mp);
1912 mv643xx_eth_set_settings(mp->dev, &cmd);
1913 }
1da177e4 1914
81600eea
LB		 1915 /*
1916 * Configure basic link parameters.
1917 */
1918 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1919
1920 pscr |= SERIAL_PORT_ENABLE;
1921 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1922
1923 pscr |= DO_NOT_FORCE_LINK_FAIL;
1924 if (mp->phy_addr == -1)
1925 pscr |= FORCE_LINK_PASS;
1926 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1927
1928 wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1929
13d64285
LB		 1930 /*
1931 * Configure TX path and queues.
1932 */
89df5fdc 1933 tx_set_rate(mp, 1000000000, 16777216);
f7981c1c 1934 for (i = 0; i < mp->txq_count; i++) {
3d6b35bc 1935 struct tx_queue *txq = mp->txq + i;
13d64285 1936
6b368f68 1937 txq_reset_hw_ptr(txq);
89df5fdc
LB		 1938 txq_set_rate(txq, 1000000000, 16777216);
1939 txq_set_fixed_prio_mode(txq);
13d64285
LB		 1940 }
1941
fc32b0e2
LB		 1942 /*
1943 * Add configured unicast address to address filter table.
1944 */
1945 uc_addr_set(mp, mp->dev->dev_addr);
1da177e4 1946
d9a073ea
LB		 1947 /*
1948 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
1949 * frames to RX queue #0.
1950 */
8a578111 1951 wrl(mp, PORT_CONFIG(mp->port_num), 0x00000000);
01999873 1952
376489a2
LB		 1953 /*
1954 * Treat BPDUs as normal multicasts, and disable partition mode.
1955 */
8a578111 1956 wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000);
01999873 1957
8a578111 1958 /*
64da80a2 1959 * Enable the receive queues.
8a578111 1960 */
f7981c1c 1961 for (i = 0; i < mp->rxq_count; i++) {
64da80a2
LB		 1962 struct rx_queue *rxq = mp->rxq + i;
1963 int off = RXQ_CURRENT_DESC_PTR(mp->port_num, i);
8a578111 1964 u32 addr;
1da177e4 1965
8a578111
LB		 1966 addr = (u32)rxq->rx_desc_dma;
1967 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
1968 wrl(mp, off, addr);
1da177e4 1969
8a578111
LB		 1970 rxq_enable(rxq);
1971 }
1da177e4
LT		 1972}
1973
ffd86bbe 1974static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1da177e4 1975{
c9df406f 1976 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
773fc3ee 1977 u32 val;
1da177e4 1978
773fc3ee
LB		 1979 val = rdl(mp, SDMA_CONFIG(mp->port_num));
1980 if (mp->shared->extended_rx_coal_limit) {
1981 if (coal > 0xffff)
1982 coal = 0xffff;
1983 val &= ~0x023fff80;
1984 val |= (coal & 0x8000) << 10;
1985 val |= (coal & 0x7fff) << 7;
1986 } else {
1987 if (coal > 0x3fff)
1988 coal = 0x3fff;
1989 val &= ~0x003fff00;
1990 val |= (coal & 0x3fff) << 8;
1991 }
1992 wrl(mp, SDMA_CONFIG(mp->port_num), val);
1da177e4
LT		 1993}
1994
ffd86bbe 1995static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1da177e4 1996{
c9df406f 1997 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1da177e4 1998
fc32b0e2
LB		 1999 if (coal > 0x3fff)
2000 coal = 0x3fff;
2001 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4);
16e03018
DF		 2002}
2003
c9df406f 2004static int mv643xx_eth_open(struct net_device *dev)
16e03018 2005{
e5371493 2006 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2007 int err;
2257e05c 2008 int oom;
64da80a2 2009 int i;
16e03018 2010
fc32b0e2
LB		 2011 wrl(mp, INT_CAUSE(mp->port_num), 0);
2012 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
2013 rdl(mp, INT_CAUSE_EXT(mp->port_num));
c9df406f 2014
fc32b0e2 2015 err = request_irq(dev->irq, mv643xx_eth_irq,
2a1867a7 2016 IRQF_SHARED, dev->name, dev);
c9df406f 2017 if (err) {
fc32b0e2 2018 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
c9df406f 2019 return -EAGAIN;
16e03018
DF		 2020 }
2021
fc32b0e2 2022 init_mac_tables(mp);
16e03018 2023
2257e05c
LB		 2024 napi_enable(&mp->napi);
2025
2026 oom = 0;
f7981c1c 2027 for (i = 0; i < mp->rxq_count; i++) {
64da80a2
LB		 2028 err = rxq_init(mp, i);
2029 if (err) {
2030 while (--i >= 0)
f7981c1c 2031 rxq_deinit(mp->rxq + i);
64da80a2
LB		 2032 goto out;
2033 }
2034
2257e05c
LB		 2035 rxq_refill(mp->rxq + i, INT_MAX, &oom);
2036 }
2037
2038 if (oom) {
2039 mp->rx_oom.expires = jiffies + (HZ / 10);
2040 add_timer(&mp->rx_oom);
64da80a2 2041 }
8a578111 2042
f7981c1c 2043 for (i = 0; i < mp->txq_count; i++) {
3d6b35bc
LB		 2044 err = txq_init(mp, i);
2045 if (err) {
2046 while (--i >= 0)
f7981c1c 2047 txq_deinit(mp->txq + i);
3d6b35bc
LB		 2048 goto out_free;
2049 }
2050 }
16e03018 2051
2f7eb47a 2052 netif_carrier_off(dev);
2f7eb47a 2053
fc32b0e2 2054 port_start(mp);
16e03018 2055
ffd86bbe
LB		 2056 set_rx_coal(mp, 0);
2057 set_tx_coal(mp, 0);
16e03018 2058
befefe21 2059 wrl(mp, INT_MASK_EXT(mp->port_num), INT_EXT_LINK_PHY | INT_EXT_TX);
226bb6b7 2060 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
16e03018 2061
c9df406f
LB		 2062 return 0;
2063
13d64285 2064
fc32b0e2 2065out_free:
f7981c1c
LB		 2066 for (i = 0; i < mp->rxq_count; i++)
2067 rxq_deinit(mp->rxq + i);
fc32b0e2 2068out:
c9df406f
LB		 2069 free_irq(dev->irq, dev);
2070
2071 return err;
16e03018
DF		 2072}
2073
e5371493 2074static void port_reset(struct mv643xx_eth_private *mp)
1da177e4 2075{
fc32b0e2 2076 unsigned int data;
64da80a2 2077 int i;
1da177e4 2078
f7981c1c
LB		 2079 for (i = 0; i < mp->rxq_count; i++)
2080 rxq_disable(mp->rxq + i);
2081 for (i = 0; i < mp->txq_count; i++)
2082 txq_disable(mp->txq + i);
ae9ae064
LB		 2083
2084 while (1) {
2085 u32 ps = rdl(mp, PORT_STATUS(mp->port_num));
2086
2087 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2088 break;
13d64285 2089 udelay(10);
ae9ae064 2090 }
1da177e4 2091
c9df406f 2092 /* Reset the Enable bit in the Configuration Register */
fc32b0e2
LB		 2093 data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2094 data &= ~(SERIAL_PORT_ENABLE |
2095 DO_NOT_FORCE_LINK_FAIL |
2096 FORCE_LINK_PASS);
2097 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data);
1da177e4
LT		 2098}
2099
c9df406f 2100static int mv643xx_eth_stop(struct net_device *dev)
1da177e4 2101{
e5371493 2102 struct mv643xx_eth_private *mp = netdev_priv(dev);
64da80a2 2103 int i;
1da177e4 2104
fc32b0e2
LB		 2105 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2106 rdl(mp, INT_MASK(mp->port_num));
1da177e4 2107
c9df406f 2108 napi_disable(&mp->napi);
78fff83b 2109
2257e05c
LB		 2110 del_timer_sync(&mp->rx_oom);
2111
c9df406f 2112 netif_carrier_off(dev);
1da177e4 2113
fc32b0e2
LB		 2114 free_irq(dev->irq, dev);
2115
cc9754b3 2116 port_reset(mp);
fc32b0e2 2117 mib_counters_update(mp);
1da177e4 2118
f7981c1c
LB		 2119 for (i = 0; i < mp->rxq_count; i++)
2120 rxq_deinit(mp->rxq + i);
2121 for (i = 0; i < mp->txq_count; i++)
2122 txq_deinit(mp->txq + i);
1da177e4 2123
c9df406f 2124 return 0;
1da177e4
LT		 2125}
2126
fc32b0e2 2127static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1da177e4 2128{
e5371493 2129 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2130
bedfe324
LB		 2131 if (mp->phy_addr != -1)
2132 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
2133
2134 return -EOPNOTSUPP;
1da177e4
LT		 2135}
2136
c9df406f 2137static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 2138{
89df5fdc
LB		 2139 struct mv643xx_eth_private *mp = netdev_priv(dev);
2140
fc32b0e2 2141 if (new_mtu < 64 || new_mtu > 9500)
c9df406f 2142 return -EINVAL;
1da177e4 2143
c9df406f 2144 dev->mtu = new_mtu;
89df5fdc
LB		 2145 tx_set_rate(mp, 1000000000, 16777216);
2146
c9df406f
LB		 2147 if (!netif_running(dev))
2148 return 0;
1da177e4 2149
c9df406f
LB		 2150 /*
2151 * Stop and then re-open the interface. This will allocate RX
2152 * skbs of the new MTU.
2153 * There is a possible danger that the open will not succeed,
fc32b0e2 2154 * due to memory being full.
c9df406f
LB		 2155 */
2156 mv643xx_eth_stop(dev);
2157 if (mv643xx_eth_open(dev)) {
fc32b0e2
LB		 2158 dev_printk(KERN_ERR, &dev->dev,
2159 "fatal error on re-opening device after "
2160 "MTU change\n");
c9df406f
LB		 2161 }
2162
2163 return 0;
1da177e4
LT		 2164}
2165
fc32b0e2 2166static void tx_timeout_task(struct work_struct *ugly)
1da177e4 2167{
fc32b0e2 2168 struct mv643xx_eth_private *mp;
1da177e4 2169
fc32b0e2
LB		 2170 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2171 if (netif_running(mp->dev)) {
2172 netif_stop_queue(mp->dev);
fc32b0e2
LB		 2173 port_reset(mp);
2174 port_start(mp);
4fdeca3f 2175 netif_wake_queue(mp->dev);
fc32b0e2 2176 }
c9df406f
LB		 2177}
2178
c9df406f 2179static void mv643xx_eth_tx_timeout(struct net_device *dev)
1da177e4 2180{
e5371493 2181 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2182
fc32b0e2 2183 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
d0412d96 2184
c9df406f 2185 schedule_work(&mp->tx_timeout_task);
1da177e4
LT		 2186}
2187
c9df406f 2188#ifdef CONFIG_NET_POLL_CONTROLLER
fc32b0e2 2189static void mv643xx_eth_netpoll(struct net_device *dev)
9f8dd319 2190{
fc32b0e2 2191 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2192
fc32b0e2
LB		 2193 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2194 rdl(mp, INT_MASK(mp->port_num));
c9df406f 2195
fc32b0e2 2196 mv643xx_eth_irq(dev->irq, dev);
c9df406f 2197
f2ca60f2 2198 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
9f8dd319 2199}
c9df406f 2200#endif
9f8dd319 2201
fc32b0e2 2202static int mv643xx_eth_mdio_read(struct net_device *dev, int addr, int reg)
9f8dd319 2203{
e5371493 2204 struct mv643xx_eth_private *mp = netdev_priv(dev);
45c5d3bc 2205 return smi_reg_read(mp, addr, reg);
9f8dd319
DF		 2206}
2207
fc32b0e2 2208static void mv643xx_eth_mdio_write(struct net_device *dev, int addr, int reg, int val)
9f8dd319 2209{
e5371493 2210 struct mv643xx_eth_private *mp = netdev_priv(dev);
fc32b0e2 2211 smi_reg_write(mp, addr, reg, val);
c9df406f 2212}
9f8dd319 2213
9f8dd319 2214
c9df406f 2215/* platform glue ************************************************************/
e5371493
LB		 2216static void
2217mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2218 struct mbus_dram_target_info *dram)
c9df406f 2219{
cc9754b3 2220 void __iomem *base = msp->base;
c9df406f
LB		 2221 u32 win_enable;
2222 u32 win_protect;
2223 int i;
9f8dd319 2224
c9df406f
LB		 2225 for (i = 0; i < 6; i++) {
2226 writel(0, base + WINDOW_BASE(i));
2227 writel(0, base + WINDOW_SIZE(i));
2228 if (i < 4)
2229 writel(0, base + WINDOW_REMAP_HIGH(i));
9f8dd319
DF		 2230 }
2231
c9df406f
LB		 2232 win_enable = 0x3f;
2233 win_protect = 0;
2234
2235 for (i = 0; i < dram->num_cs; i++) {
2236 struct mbus_dram_window *cs = dram->cs + i;
2237
2238 writel((cs->base & 0xffff0000) |
2239 (cs->mbus_attr << 8) |
2240 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2241 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2242
2243 win_enable &= ~(1 << i);
2244 win_protect |= 3 << (2 * i);
2245 }
2246
2247 writel(win_enable, base + WINDOW_BAR_ENABLE);
2248 msp->win_protect = win_protect;
9f8dd319
DF		 2249}
2250
773fc3ee
LB		 2251static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2252{
2253 /*
2254 * Check whether we have a 14-bit coal limit field in bits
2255 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2256 * SDMA config register.
2257 */
2258 writel(0x02000000, msp->base + SDMA_CONFIG(0));
2259 if (readl(msp->base + SDMA_CONFIG(0)) & 0x02000000)
2260 msp->extended_rx_coal_limit = 1;
2261 else
2262 msp->extended_rx_coal_limit = 0;
1e881592
LB		 2263
2264 /*
2265 * Check whether the TX rate control registers are in the
2266 * old or the new place.
2267 */
2268 writel(1, msp->base + TX_BW_MTU_MOVED(0));
2269 if (readl(msp->base + TX_BW_MTU_MOVED(0)) & 1)
2270 msp->tx_bw_control_moved = 1;
2271 else
2272 msp->tx_bw_control_moved = 0;
773fc3ee
LB		 2273}
2274
c9df406f 2275static int mv643xx_eth_shared_probe(struct platform_device *pdev)
9f8dd319 2276{
e5371493 2277 static int mv643xx_eth_version_printed = 0;
c9df406f 2278 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
e5371493 2279 struct mv643xx_eth_shared_private *msp;
c9df406f
LB		 2280 struct resource *res;
2281 int ret;
9f8dd319 2282
e5371493 2283 if (!mv643xx_eth_version_printed++)
7dde154d
LB		 2284 printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet "
2285 "driver version %s\n", mv643xx_eth_driver_version);
9f8dd319 2286
c9df406f
LB		 2287 ret = -EINVAL;
2288 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2289 if (res == NULL)
2290 goto out;
9f8dd319 2291
c9df406f
LB		 2292 ret = -ENOMEM;
2293 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2294 if (msp == NULL)
2295 goto out;
2296 memset(msp, 0, sizeof(*msp));
2297
cc9754b3
LB		 2298 msp->base = ioremap(res->start, res->end - res->start + 1);
2299 if (msp->base == NULL)
c9df406f
LB		 2300 goto out_free;
2301
fc0eb9f2
LB		 2302 msp->smi = msp;
2303 if (pd != NULL && pd->shared_smi != NULL)
2304 msp->smi = platform_get_drvdata(pd->shared_smi);
2305
2b3ba0e3 2306 mutex_init(&msp->phy_lock);
c9df406f 2307
45c5d3bc
LB		 2308 msp->err_interrupt = NO_IRQ;
2309 init_waitqueue_head(&msp->smi_busy_wait);
2310
2311 /*
2312 * Check whether the error interrupt is hooked up.
2313 */
2314 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2315 if (res != NULL) {
2316 int err;
2317
2318 err = request_irq(res->start, mv643xx_eth_err_irq,
2319 IRQF_SHARED, "mv643xx_eth", msp);
2320 if (!err) {
2321 writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK);
2322 msp->err_interrupt = res->start;
2323 }
2324 }
2325
c9df406f
LB		 2326 /*
2327 * (Re-)program MBUS remapping windows if we are asked to.
2328 */
2329 if (pd != NULL && pd->dram != NULL)
2330 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2331
fc32b0e2
LB		 2332 /*
2333 * Detect hardware parameters.
2334 */
2335 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
773fc3ee 2336 infer_hw_params(msp);
fc32b0e2
LB		 2337
2338 platform_set_drvdata(pdev, msp);
2339
c9df406f
LB		 2340 return 0;
2341
2342out_free:
2343 kfree(msp);
2344out:
2345 return ret;
2346}
2347
2348static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2349{
e5371493 2350 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
c9df406f 2351
45c5d3bc
LB		 2352 if (msp->err_interrupt != NO_IRQ)
2353 free_irq(msp->err_interrupt, msp);
cc9754b3 2354 iounmap(msp->base);
c9df406f
LB		 2355 kfree(msp);
2356
2357 return 0;
9f8dd319
DF		 2358}
2359
c9df406f 2360static struct platform_driver mv643xx_eth_shared_driver = {
fc32b0e2
LB		 2361 .probe = mv643xx_eth_shared_probe,
2362 .remove = mv643xx_eth_shared_remove,
c9df406f 2363 .driver = {
fc32b0e2 2364 .name = MV643XX_ETH_SHARED_NAME,
c9df406f
LB		 2365 .owner = THIS_MODULE,
2366 },
2367};
2368
e5371493 2369static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
1da177e4 2370{
c9df406f 2371 int addr_shift = 5 * mp->port_num;
fc32b0e2 2372 u32 data;
1da177e4 2373
fc32b0e2
LB		 2374 data = rdl(mp, PHY_ADDR);
2375 data &= ~(0x1f << addr_shift);
2376 data |= (phy_addr & 0x1f) << addr_shift;
2377 wrl(mp, PHY_ADDR, data);
1da177e4
LT		 2378}
2379
e5371493 2380static int phy_addr_get(struct mv643xx_eth_private *mp)
1da177e4 2381{
fc32b0e2
LB		 2382 unsigned int data;
2383
2384 data = rdl(mp, PHY_ADDR);
2385
2386 return (data >> (5 * mp->port_num)) & 0x1f;
2387}
2388
2389static void set_params(struct mv643xx_eth_private *mp,
2390 struct mv643xx_eth_platform_data *pd)
2391{
2392 struct net_device *dev = mp->dev;
2393
2394 if (is_valid_ether_addr(pd->mac_addr))
2395 memcpy(dev->dev_addr, pd->mac_addr, 6);
2396 else
2397 uc_addr_get(mp, dev->dev_addr);
2398
ac840605 2399 if (pd->phy_addr == MV643XX_ETH_PHY_NONE) {
fc32b0e2
LB		 2400 mp->phy_addr = -1;
2401 } else {
ac840605 2402 if (pd->phy_addr != MV643XX_ETH_PHY_ADDR_DEFAULT) {
fc32b0e2
LB		 2403 mp->phy_addr = pd->phy_addr & 0x3f;
2404 phy_addr_set(mp, mp->phy_addr);
2405 } else {
2406 mp->phy_addr = phy_addr_get(mp);
2407 }
2408 }
1da177e4 2409
fc32b0e2
LB		 2410 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2411 if (pd->rx_queue_size)
2412 mp->default_rx_ring_size = pd->rx_queue_size;
2413 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2414 mp->rx_desc_sram_size = pd->rx_sram_size;
1da177e4 2415
f7981c1c 2416 mp->rxq_count = pd->rx_queue_count ? : 1;
64da80a2 2417
fc32b0e2
LB		 2418 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2419 if (pd->tx_queue_size)
2420 mp->default_tx_ring_size = pd->tx_queue_size;
2421 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2422 mp->tx_desc_sram_size = pd->tx_sram_size;
3d6b35bc 2423
f7981c1c 2424 mp->txq_count = pd->tx_queue_count ? : 1;
1da177e4
LT		 2425}
2426
e5371493 2427static int phy_detect(struct mv643xx_eth_private *mp)
1da177e4 2428{
45c5d3bc
LB		 2429 int data;
2430 int data2;
2431
2432 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
2433 if (data < 0)
2434 return -ENODEV;
2435
2436 if (smi_reg_write(mp, mp->phy_addr, MII_BMCR, data ^ BMCR_ANENABLE) < 0)
2437 return -ENODEV;
fc32b0e2 2438
45c5d3bc
LB		 2439 data2 = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
2440 if (data2 < 0)
2441 return -ENODEV;
1da177e4 2442
7f106c1d 2443 if (((data ^ data2) & BMCR_ANENABLE) == 0)
fc32b0e2 2444 return -ENODEV;
1da177e4 2445
7f106c1d 2446 smi_reg_write(mp, mp->phy_addr, MII_BMCR, data);
1da177e4 2447
c9df406f 2448 return 0;
1da177e4
LT		 2449}
2450
fc32b0e2
LB		 2451static int phy_init(struct mv643xx_eth_private *mp,
2452 struct mv643xx_eth_platform_data *pd)
c28a4f89 2453{
fc32b0e2
LB		 2454 struct ethtool_cmd cmd;
2455 int err;
c28a4f89 2456
fc32b0e2
LB		 2457 err = phy_detect(mp);
2458 if (err) {
2459 dev_printk(KERN_INFO, &mp->dev->dev,
2460 "no PHY detected at addr %d\n", mp->phy_addr);
2461 return err;
2462 }
2463 phy_reset(mp);
2464
2465 mp->mii.phy_id = mp->phy_addr;
2466 mp->mii.phy_id_mask = 0x3f;
2467 mp->mii.reg_num_mask = 0x1f;
2468 mp->mii.dev = mp->dev;
2469 mp->mii.mdio_read = mv643xx_eth_mdio_read;
2470 mp->mii.mdio_write = mv643xx_eth_mdio_write;
c28a4f89 2471
fc32b0e2 2472 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
c9df406f 2473
fc32b0e2
LB		 2474 memset(&cmd, 0, sizeof(cmd));
2475
2476 cmd.port = PORT_MII;
2477 cmd.transceiver = XCVR_INTERNAL;
2478 cmd.phy_address = mp->phy_addr;
2479 if (pd->speed == 0) {
2480 cmd.autoneg = AUTONEG_ENABLE;
2481 cmd.speed = SPEED_100;
2482 cmd.advertising = ADVERTISED_10baseT_Half |
2483 ADVERTISED_10baseT_Full |
2484 ADVERTISED_100baseT_Half |
2485 ADVERTISED_100baseT_Full;
c9df406f 2486 if (mp->mii.supports_gmii)
fc32b0e2 2487 cmd.advertising |= ADVERTISED_1000baseT_Full;
c9df406f 2488 } else {
fc32b0e2
LB		 2489 cmd.autoneg = AUTONEG_DISABLE;
2490 cmd.speed = pd->speed;
2491 cmd.duplex = pd->duplex;
c9df406f 2492 }
fc32b0e2 2493
fc32b0e2
LB		 2494 mv643xx_eth_set_settings(mp->dev, &cmd);
2495
2496 return 0;
c28a4f89
JC		 2497}
2498
81600eea
LB		 2499static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2500{
2501 u32 pscr;
2502
2503 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2504 if (pscr & SERIAL_PORT_ENABLE) {
2505 pscr &= ~SERIAL_PORT_ENABLE;
2506 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2507 }
2508
2509 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
2510 if (mp->phy_addr == -1) {
2511 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2512 if (speed == SPEED_1000)
2513 pscr |= SET_GMII_SPEED_TO_1000;
2514 else if (speed == SPEED_100)
2515 pscr |= SET_MII_SPEED_TO_100;
2516
2517 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2518
2519 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2520 if (duplex == DUPLEX_FULL)
2521 pscr |= SET_FULL_DUPLEX_MODE;
2522 }
2523
2524 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2525}
2526
c9df406f 2527static int mv643xx_eth_probe(struct platform_device *pdev)
1da177e4 2528{
c9df406f 2529 struct mv643xx_eth_platform_data *pd;
e5371493 2530 struct mv643xx_eth_private *mp;
c9df406f 2531 struct net_device *dev;
c9df406f 2532 struct resource *res;
c9df406f 2533 DECLARE_MAC_BUF(mac);
fc32b0e2 2534 int err;
1da177e4 2535
c9df406f
LB		 2536 pd = pdev->dev.platform_data;
2537 if (pd == NULL) {
fc32b0e2
LB		 2538 dev_printk(KERN_ERR, &pdev->dev,
2539 "no mv643xx_eth_platform_data\n");
c9df406f
LB		 2540 return -ENODEV;
2541 }
1da177e4 2542
c9df406f 2543 if (pd->shared == NULL) {
fc32b0e2
LB		 2544 dev_printk(KERN_ERR, &pdev->dev,
2545 "no mv643xx_eth_platform_data->shared\n");
c9df406f
LB		 2546 return -ENODEV;
2547 }
8f518703 2548
e5371493 2549 dev = alloc_etherdev(sizeof(struct mv643xx_eth_private));
c9df406f
LB		 2550 if (!dev)
2551 return -ENOMEM;
1da177e4 2552
c9df406f 2553 mp = netdev_priv(dev);
fc32b0e2
LB		 2554 platform_set_drvdata(pdev, mp);
2555
2556 mp->shared = platform_get_drvdata(pd->shared);
2557 mp->port_num = pd->port_number;
2558
c9df406f 2559 mp->dev = dev;
78fff83b 2560
fc32b0e2
LB		 2561 set_params(mp, pd);
2562
2563 spin_lock_init(&mp->lock);
2564
2565 mib_counters_clear(mp);
2566 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2567
bedfe324
LB		 2568 if (mp->phy_addr != -1) {
2569 err = phy_init(mp, pd);
2570 if (err)
2571 goto out;
2572
2573 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2574 } else {
2575 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless);
2576 }
81600eea 2577 init_pscr(mp, pd->speed, pd->duplex);
fc32b0e2 2578
2257e05c
LB		 2579 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
2580
2581 init_timer(&mp->rx_oom);
2582 mp->rx_oom.data = (unsigned long)mp;
2583 mp->rx_oom.function = oom_timer_wrapper;
2584
fc32b0e2 2585
c9df406f
LB		 2586 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2587 BUG_ON(!res);
2588 dev->irq = res->start;
1da177e4 2589
fc32b0e2 2590 dev->hard_start_xmit = mv643xx_eth_xmit;
c9df406f
LB		 2591 dev->open = mv643xx_eth_open;
2592 dev->stop = mv643xx_eth_stop;
c9df406f 2593 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
fc32b0e2
LB		 2594 dev->set_mac_address = mv643xx_eth_set_mac_address;
2595 dev->do_ioctl = mv643xx_eth_ioctl;
2596 dev->change_mtu = mv643xx_eth_change_mtu;
c9df406f 2597 dev->tx_timeout = mv643xx_eth_tx_timeout;
c9df406f 2598#ifdef CONFIG_NET_POLL_CONTROLLER
e5371493 2599 dev->poll_controller = mv643xx_eth_netpoll;
c9df406f 2600#endif
c9df406f
LB		 2601 dev->watchdog_timeo = 2 * HZ;
2602 dev->base_addr = 0;
1da177e4 2603
c9df406f 2604 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
e32b6617 2605 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
1da177e4 2606
fc32b0e2 2607 SET_NETDEV_DEV(dev, &pdev->dev);
8f518703 2608
c9df406f 2609 if (mp->shared->win_protect)
fc32b0e2 2610 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
1da177e4 2611
c9df406f
LB		 2612 err = register_netdev(dev);
2613 if (err)
2614 goto out;
1da177e4 2615
fc32b0e2
LB		 2616 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %s\n",
2617 mp->port_num, print_mac(mac, dev->dev_addr));
1da177e4 2618
13d64285 2619 if (mp->tx_desc_sram_size > 0)
fc32b0e2 2620 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
1da177e4 2621
c9df406f 2622 return 0;
1da177e4 2623
c9df406f
LB		 2624out:
2625 free_netdev(dev);
1da177e4 2626
c9df406f 2627 return err;
1da177e4
LT		 2628}
2629
c9df406f 2630static int mv643xx_eth_remove(struct platform_device *pdev)
1da177e4 2631{
fc32b0e2 2632 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
1da177e4 2633
fc32b0e2 2634 unregister_netdev(mp->dev);
c9df406f 2635 flush_scheduled_work();
fc32b0e2 2636 free_netdev(mp->dev);
c9df406f 2637
c9df406f 2638 platform_set_drvdata(pdev, NULL);
fc32b0e2 2639
c9df406f 2640 return 0;
1da177e4
LT		 2641}
2642
c9df406f 2643static void mv643xx_eth_shutdown(struct platform_device *pdev)
d0412d96 2644{
fc32b0e2 2645 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
d0412d96 2646
c9df406f 2647 /* Mask all interrupts on ethernet port */
fc32b0e2
LB		 2648 wrl(mp, INT_MASK(mp->port_num), 0);
2649 rdl(mp, INT_MASK(mp->port_num));
c9df406f 2650
fc32b0e2
LB		 2651 if (netif_running(mp->dev))
2652 port_reset(mp);
d0412d96
JC		 2653}
2654
c9df406f 2655static struct platform_driver mv643xx_eth_driver = {
fc32b0e2
LB		 2656 .probe = mv643xx_eth_probe,
2657 .remove = mv643xx_eth_remove,
2658 .shutdown = mv643xx_eth_shutdown,
c9df406f 2659 .driver = {
fc32b0e2 2660 .name = MV643XX_ETH_NAME,
c9df406f
LB		 2661 .owner = THIS_MODULE,
2662 },
2663};
2664
e5371493 2665static int __init mv643xx_eth_init_module(void)
d0412d96 2666{
c9df406f 2667 int rc;
d0412d96 2668
c9df406f
LB		 2669 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2670 if (!rc) {
2671 rc = platform_driver_register(&mv643xx_eth_driver);
2672 if (rc)
2673 platform_driver_unregister(&mv643xx_eth_shared_driver);
2674 }
fc32b0e2 2675
c9df406f 2676 return rc;
d0412d96 2677}
fc32b0e2 2678module_init(mv643xx_eth_init_module);
d0412d96 2679
e5371493 2680static void __exit mv643xx_eth_cleanup_module(void)
d0412d96 2681{
c9df406f
LB		 2682 platform_driver_unregister(&mv643xx_eth_driver);
2683 platform_driver_unregister(&mv643xx_eth_shared_driver);
d0412d96 2684}
e5371493 2685module_exit(mv643xx_eth_cleanup_module);
1da177e4 2686
45675bc6
LB		 2687MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2688 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
c9df406f 2689MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
fc32b0e2 2690MODULE_LICENSE("GPL");
c9df406f 2691MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
fc32b0e2 2692MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
Linux 6.x block layer and io_uring tree(s)