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[PATCH] mv643xx_eth: Receive buffers require 8 byte alignment
[linux-2.6-block.git] / drivers / net / mv643xx_eth.c
CommitLineData
1da177e4
LT		 1/*
2 * drivers/net/mv643xx_eth.c - Driver for MV643XX ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 rabeeh@galileo.co.il
7 *
8 * Copyright (C) 2003 PMC-Sierra, Inc.,
3bb8a18a 9 * written by Manish Lachwani
1da177e4
LT		 10 *
11 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
12 *
13 * Copyright (C) 2004-2005 MontaVista Software, Inc.
14 * Dale Farnsworth <dale@farnsworth.org>
15 *
16 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
17 * <sjhill@realitydiluted.com>
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version 2
22 * of the License, or (at your option) any later version.
23 *
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
28 *
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
32 */
33#include <linux/init.h>
34#include <linux/dma-mapping.h>
35#include <linux/tcp.h>
36#include <linux/udp.h>
37#include <linux/etherdevice.h>
78a5e534
OH		 38#include <linux/in.h>
39#include <linux/ip.h>
1da177e4
LT		 40
41#include <linux/bitops.h>
42#include <linux/delay.h>
43#include <linux/ethtool.h>
d052d1be
RK		 44#include <linux/platform_device.h>
45
1da177e4
LT		 46#include <asm/io.h>
47#include <asm/types.h>
48#include <asm/pgtable.h>
49#include <asm/system.h>
50#include <asm/delay.h>
51#include "mv643xx_eth.h"
52
53/*
54 * The first part is the high level driver of the gigE ethernet ports.
55 */
56
57/* Constants */
58#define VLAN_HLEN 4
59#define FCS_LEN 4
b44cd572
DF		 60#define DMA_ALIGN 8 /* hw requires 8-byte alignment */
61#define HW_IP_ALIGN 2 /* hw aligns IP header */
62#define WRAP HW_IP_ALIGN + ETH_HLEN + VLAN_HLEN + FCS_LEN
1da177e4
LT		 63#define RX_SKB_SIZE ((dev->mtu + WRAP + 7) & ~0x7)
64
65#define INT_CAUSE_UNMASK_ALL 0x0007ffff
66#define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff
1da177e4 67#define INT_CAUSE_MASK_ALL 0x00000000
63c9e549 68#define INT_CAUSE_MASK_ALL_EXT 0x00000000
1da177e4
LT		 69#define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL
70#define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT
1da177e4
LT		 71
72#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
73#define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
74#else
75#define MAX_DESCS_PER_SKB 1
76#endif
77
78#define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */
79#define PHY_WAIT_MICRO_SECONDS 10
80
81/* Static function declarations */
82static int eth_port_link_is_up(unsigned int eth_port_num);
83static void eth_port_uc_addr_get(struct net_device *dev,
84 unsigned char *MacAddr);
16e03018 85static void eth_port_set_multicast_list(struct net_device *);
1da177e4
LT		 86static int mv643xx_eth_real_open(struct net_device *);
87static int mv643xx_eth_real_stop(struct net_device *);
88static int mv643xx_eth_change_mtu(struct net_device *, int);
89static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *);
90static void eth_port_init_mac_tables(unsigned int eth_port_num);
91#ifdef MV643XX_NAPI
92static int mv643xx_poll(struct net_device *dev, int *budget);
93#endif
94static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
95static int ethernet_phy_detect(unsigned int eth_port_num);
96static struct ethtool_ops mv643xx_ethtool_ops;
97
98static char mv643xx_driver_name[] = "mv643xx_eth";
99static char mv643xx_driver_version[] = "1.0";
100
101static void __iomem *mv643xx_eth_shared_base;
102
103/* used to protect MV643XX_ETH_SMI_REG, which is shared across ports */
a9f6a0dd 104static DEFINE_SPINLOCK(mv643xx_eth_phy_lock);
1da177e4
LT		 105
106static inline u32 mv_read(int offset)
107{
dc074a8a 108 void __iomem *reg_base;
1da177e4
LT		 109
110 reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS;
111
112 return readl(reg_base + offset);
113}
114
115static inline void mv_write(int offset, u32 data)
116{
dc074a8a 117 void __iomem *reg_base;
1da177e4
LT		 118
119 reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS;
120 writel(data, reg_base + offset);
121}
122
123/*
124 * Changes MTU (maximum transfer unit) of the gigabit ethenret port
125 *
126 * Input : pointer to ethernet interface network device structure
127 * new mtu size
128 * Output : 0 upon success, -EINVAL upon failure
129 */
130static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
131{
132 struct mv643xx_private *mp = netdev_priv(dev);
133 unsigned long flags;
134
135 spin_lock_irqsave(&mp->lock, flags);
136
137 if ((new_mtu > 9500) || (new_mtu < 64)) {
138 spin_unlock_irqrestore(&mp->lock, flags);
139 return -EINVAL;
140 }
141
142 dev->mtu = new_mtu;
143 /*
144 * Stop then re-open the interface. This will allocate RX skb's with
145 * the new MTU.
146 * There is a possible danger that the open will not successed, due
147 * to memory is full, which might fail the open function.
148 */
149 if (netif_running(dev)) {
150 if (mv643xx_eth_real_stop(dev))
151 printk(KERN_ERR
152 "%s: Fatal error on stopping device\n",
153 dev->name);
154 if (mv643xx_eth_real_open(dev))
155 printk(KERN_ERR
156 "%s: Fatal error on opening device\n",
157 dev->name);
158 }
159
160 spin_unlock_irqrestore(&mp->lock, flags);
161 return 0;
162}
163
164/*
165 * mv643xx_eth_rx_task
166 *
167 * Fills / refills RX queue on a certain gigabit ethernet port
168 *
169 * Input : pointer to ethernet interface network device structure
170 * Output : N/A
171 */
172static void mv643xx_eth_rx_task(void *data)
173{
174 struct net_device *dev = (struct net_device *)data;
175 struct mv643xx_private *mp = netdev_priv(dev);
176 struct pkt_info pkt_info;
177 struct sk_buff *skb;
b44cd572 178 int unaligned;
1da177e4
LT		 179
180 if (test_and_set_bit(0, &mp->rx_task_busy))
181 panic("%s: Error in test_set_bit / clear_bit", dev->name);
182
183 while (mp->rx_ring_skbs < (mp->rx_ring_size - 5)) {
b44cd572 184 skb = dev_alloc_skb(RX_SKB_SIZE + DMA_ALIGN);
1da177e4
LT		 185 if (!skb)
186 break;
187 mp->rx_ring_skbs++;
b44cd572
DF		 188 unaligned = (u32)skb->data & (DMA_ALIGN - 1);
189 if (unaligned)
190 skb_reserve(skb, DMA_ALIGN - unaligned);
1da177e4
LT		 191 pkt_info.cmd_sts = ETH_RX_ENABLE_INTERRUPT;
192 pkt_info.byte_cnt = RX_SKB_SIZE;
193 pkt_info.buf_ptr = dma_map_single(NULL, skb->data, RX_SKB_SIZE,
194 DMA_FROM_DEVICE);
195 pkt_info.return_info = skb;
196 if (eth_rx_return_buff(mp, &pkt_info) != ETH_OK) {
197 printk(KERN_ERR
198 "%s: Error allocating RX Ring\n", dev->name);
199 break;
200 }
b44cd572 201 skb_reserve(skb, HW_IP_ALIGN);
1da177e4
LT		 202 }
203 clear_bit(0, &mp->rx_task_busy);
204 /*
205 * If RX ring is empty of SKB, set a timer to try allocating
206 * again in a later time .
207 */
208 if ((mp->rx_ring_skbs == 0) && (mp->rx_timer_flag == 0)) {
209 printk(KERN_INFO "%s: Rx ring is empty\n", dev->name);
210 /* After 100mSec */
211 mp->timeout.expires = jiffies + (HZ / 10);
212 add_timer(&mp->timeout);
213 mp->rx_timer_flag = 1;
214 }
215#ifdef MV643XX_RX_QUEUE_FILL_ON_TASK
216 else {
217 /* Return interrupts */
218 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(mp->port_num),
219 INT_CAUSE_UNMASK_ALL);
220 }
221#endif
222}
223
224/*
225 * mv643xx_eth_rx_task_timer_wrapper
226 *
227 * Timer routine to wake up RX queue filling task. This function is
228 * used only in case the RX queue is empty, and all alloc_skb has
229 * failed (due to out of memory event).
230 *
231 * Input : pointer to ethernet interface network device structure
232 * Output : N/A
233 */
234static void mv643xx_eth_rx_task_timer_wrapper(unsigned long data)
235{
236 struct net_device *dev = (struct net_device *)data;
237 struct mv643xx_private *mp = netdev_priv(dev);
238
239 mp->rx_timer_flag = 0;
240 mv643xx_eth_rx_task((void *)data);
241}
242
243/*
244 * mv643xx_eth_update_mac_address
245 *
246 * Update the MAC address of the port in the address table
247 *
248 * Input : pointer to ethernet interface network device structure
249 * Output : N/A
250 */
251static void mv643xx_eth_update_mac_address(struct net_device *dev)
252{
253 struct mv643xx_private *mp = netdev_priv(dev);
254 unsigned int port_num = mp->port_num;
255
256 eth_port_init_mac_tables(port_num);
257 memcpy(mp->port_mac_addr, dev->dev_addr, 6);
258 eth_port_uc_addr_set(port_num, mp->port_mac_addr);
259}
260
261/*
262 * mv643xx_eth_set_rx_mode
263 *
264 * Change from promiscuos to regular rx mode
265 *
266 * Input : pointer to ethernet interface network device structure
267 * Output : N/A
268 */
269static void mv643xx_eth_set_rx_mode(struct net_device *dev)
270{
271 struct mv643xx_private *mp = netdev_priv(dev);
1da177e4 272
1da177e4 273 if (dev->flags & IFF_PROMISC)
7342cd81 274 mp->port_config |= (u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE;
1da177e4 275 else
7342cd81
DF		 276 mp->port_config &= ~(u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE;
277
278 mv_write(MV643XX_ETH_PORT_CONFIG_REG(mp->port_num), mp->port_config);
16e03018
DF		 279
280 eth_port_set_multicast_list(dev);
1da177e4
LT		 281}
282
283/*
284 * mv643xx_eth_set_mac_address
285 *
286 * Change the interface's mac address.
287 * No special hardware thing should be done because interface is always
288 * put in promiscuous mode.
289 *
290 * Input : pointer to ethernet interface network device structure and
291 * a pointer to the designated entry to be added to the cache.
292 * Output : zero upon success, negative upon failure
293 */
294static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
295{
296 int i;
297
298 for (i = 0; i < 6; i++)
299 /* +2 is for the offset of the HW addr type */
300 dev->dev_addr[i] = ((unsigned char *)addr)[i + 2];
301 mv643xx_eth_update_mac_address(dev);
302 return 0;
303}
304
305/*
306 * mv643xx_eth_tx_timeout
307 *
308 * Called upon a timeout on transmitting a packet
309 *
310 * Input : pointer to ethernet interface network device structure.
311 * Output : N/A
312 */
313static void mv643xx_eth_tx_timeout(struct net_device *dev)
314{
315 struct mv643xx_private *mp = netdev_priv(dev);
316
317 printk(KERN_INFO "%s: TX timeout ", dev->name);
318
319 /* Do the reset outside of interrupt context */
320 schedule_work(&mp->tx_timeout_task);
321}
322
323/*
324 * mv643xx_eth_tx_timeout_task
325 *
326 * Actual routine to reset the adapter when a timeout on Tx has occurred
327 */
328static void mv643xx_eth_tx_timeout_task(struct net_device *dev)
329{
330 struct mv643xx_private *mp = netdev_priv(dev);
331
332 netif_device_detach(dev);
333 eth_port_reset(mp->port_num);
334 eth_port_start(mp);
335 netif_device_attach(dev);
336}
337
338/*
339 * mv643xx_eth_free_tx_queue
340 *
341 * Input : dev - a pointer to the required interface
342 *
343 * Output : 0 if was able to release skb , nonzero otherwise
344 */
345static int mv643xx_eth_free_tx_queue(struct net_device *dev,
346 unsigned int eth_int_cause_ext)
347{
348 struct mv643xx_private *mp = netdev_priv(dev);
349 struct net_device_stats *stats = &mp->stats;
350 struct pkt_info pkt_info;
351 int released = 1;
352
353 if (!(eth_int_cause_ext & (BIT0 | BIT8)))
354 return released;
355
356 spin_lock(&mp->lock);
357
358 /* Check only queue 0 */
359 while (eth_tx_return_desc(mp, &pkt_info) == ETH_OK) {
360 if (pkt_info.cmd_sts & BIT0) {
361 printk("%s: Error in TX\n", dev->name);
362 stats->tx_errors++;
363 }
364
cb415d30
PG		 365 if (pkt_info.cmd_sts & ETH_TX_FIRST_DESC)
366 dma_unmap_single(NULL, pkt_info.buf_ptr,
367 pkt_info.byte_cnt,
368 DMA_TO_DEVICE);
369 else
370 dma_unmap_page(NULL, pkt_info.buf_ptr,
371 pkt_info.byte_cnt,
372 DMA_TO_DEVICE);
1da177e4 373
cb415d30 374 if (pkt_info.return_info) {
1da177e4
LT		 375 dev_kfree_skb_irq(pkt_info.return_info);
376 released = 0;
cb415d30 377 }
1da177e4
LT		 378 }
379
380 spin_unlock(&mp->lock);
381
382 return released;
383}
384
385/*
386 * mv643xx_eth_receive
387 *
388 * This function is forward packets that are received from the port's
389 * queues toward kernel core or FastRoute them to another interface.
390 *
391 * Input : dev - a pointer to the required interface
392 * max - maximum number to receive (0 means unlimted)
393 *
394 * Output : number of served packets
395 */
396#ifdef MV643XX_NAPI
397static int mv643xx_eth_receive_queue(struct net_device *dev, int budget)
398#else
399static int mv643xx_eth_receive_queue(struct net_device *dev)
400#endif
401{
402 struct mv643xx_private *mp = netdev_priv(dev);
403 struct net_device_stats *stats = &mp->stats;
404 unsigned int received_packets = 0;
405 struct sk_buff *skb;
406 struct pkt_info pkt_info;
407
408#ifdef MV643XX_NAPI
b1dd9ca1 409 while (budget-- > 0 && eth_port_receive(mp, &pkt_info) == ETH_OK) {
1da177e4
LT		 410#else
411 while (eth_port_receive(mp, &pkt_info) == ETH_OK) {
412#endif
413 mp->rx_ring_skbs--;
414 received_packets++;
b1dd9ca1 415
1da177e4
LT		 416 /* Update statistics. Note byte count includes 4 byte CRC count */
417 stats->rx_packets++;
418 stats->rx_bytes += pkt_info.byte_cnt;
419 skb = pkt_info.return_info;
420 /*
421 * In case received a packet without first / last bits on OR
422 * the error summary bit is on, the packets needs to be dropeed.
423 */
424 if (((pkt_info.cmd_sts
425 & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
426 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
427 || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
428 stats->rx_dropped++;
429 if ((pkt_info.cmd_sts & (ETH_RX_FIRST_DESC |
430 ETH_RX_LAST_DESC)) !=
431 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) {
432 if (net_ratelimit())
433 printk(KERN_ERR
434 "%s: Received packet spread "
435 "on multiple descriptors\n",
436 dev->name);
437 }
438 if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)
439 stats->rx_errors++;
440
441 dev_kfree_skb_irq(skb);
442 } else {
443 /*
444 * The -4 is for the CRC in the trailer of the
445 * received packet
446 */
447 skb_put(skb, pkt_info.byte_cnt - 4);
448 skb->dev = dev;
449
450 if (pkt_info.cmd_sts & ETH_LAYER_4_CHECKSUM_OK) {
451 skb->ip_summed = CHECKSUM_UNNECESSARY;
452 skb->csum = htons(
453 (pkt_info.cmd_sts & 0x0007fff8) >> 3);
454 }
455 skb->protocol = eth_type_trans(skb, dev);
456#ifdef MV643XX_NAPI
457 netif_receive_skb(skb);
458#else
459 netif_rx(skb);
460#endif
461 }
462 }
463
464 return received_packets;
465}
466
467/*
468 * mv643xx_eth_int_handler
469 *
470 * Main interrupt handler for the gigbit ethernet ports
471 *
472 * Input : irq - irq number (not used)
473 * dev_id - a pointer to the required interface's data structure
474 * regs - not used
475 * Output : N/A
476 */
477
478static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id,
479 struct pt_regs *regs)
480{
481 struct net_device *dev = (struct net_device *)dev_id;
482 struct mv643xx_private *mp = netdev_priv(dev);
483 u32 eth_int_cause, eth_int_cause_ext = 0;
484 unsigned int port_num = mp->port_num;
485
486 /* Read interrupt cause registers */
487 eth_int_cause = mv_read(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num)) &
488 INT_CAUSE_UNMASK_ALL;
489
490 if (eth_int_cause & BIT1)
491 eth_int_cause_ext = mv_read(
492 MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num)) &
493 INT_CAUSE_UNMASK_ALL_EXT;
494
495#ifdef MV643XX_NAPI
496 if (!(eth_int_cause & 0x0007fffd)) {
497 /* Dont ack the Rx interrupt */
498#endif
499 /*
500 * Clear specific ethernet port intrerrupt registers by
501 * acknowleding relevant bits.
502 */
503 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num),
504 ~eth_int_cause);
505 if (eth_int_cause_ext != 0x0)
506 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG
507 (port_num), ~eth_int_cause_ext);
508
509 /* UDP change : We may need this */
510 if ((eth_int_cause_ext & 0x0000ffff) &&
511 (mv643xx_eth_free_tx_queue(dev, eth_int_cause_ext) == 0) &&
512 (mp->tx_ring_size > mp->tx_ring_skbs + MAX_DESCS_PER_SKB))
513 netif_wake_queue(dev);
514#ifdef MV643XX_NAPI
515 } else {
516 if (netif_rx_schedule_prep(dev)) {
517 /* Mask all the interrupts */
518 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), 0);
519 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG
520 (port_num), 0);
521 __netif_rx_schedule(dev);
522 }
523#else
524 if (eth_int_cause & (BIT2 | BIT11))
525 mv643xx_eth_receive_queue(dev, 0);
526
527 /*
528 * After forwarded received packets to upper layer, add a task
529 * in an interrupts enabled context that refills the RX ring
530 * with skb's.
531 */
532#ifdef MV643XX_RX_QUEUE_FILL_ON_TASK
533 /* Unmask all interrupts on ethernet port */
534 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
535 INT_CAUSE_MASK_ALL);
536 queue_task(&mp->rx_task, &tq_immediate);
537 mark_bh(IMMEDIATE_BH);
538#else
539 mp->rx_task.func(dev);
540#endif
541#endif
542 }
543 /* PHY status changed */
544 if (eth_int_cause_ext & (BIT16 | BIT20)) {
545 if (eth_port_link_is_up(port_num)) {
546 netif_carrier_on(dev);
547 netif_wake_queue(dev);
548 /* Start TX queue */
549 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG
550 (port_num), 1);
551 } else {
552 netif_carrier_off(dev);
553 netif_stop_queue(dev);
554 }
555 }
556
557 /*
558 * If no real interrupt occured, exit.
559 * This can happen when using gigE interrupt coalescing mechanism.
560 */
561 if ((eth_int_cause == 0x0) && (eth_int_cause_ext == 0x0))
562 return IRQ_NONE;
563
564 return IRQ_HANDLED;
565}
566
567#ifdef MV643XX_COAL
568
569/*
570 * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
571 *
572 * DESCRIPTION:
573 * This routine sets the RX coalescing interrupt mechanism parameter.
574 * This parameter is a timeout counter, that counts in 64 t_clk
575 * chunks ; that when timeout event occurs a maskable interrupt
576 * occurs.
577 * The parameter is calculated using the tClk of the MV-643xx chip
578 * , and the required delay of the interrupt in usec.
579 *
580 * INPUT:
581 * unsigned int eth_port_num Ethernet port number
582 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
583 * unsigned int delay Delay in usec
584 *
585 * OUTPUT:
586 * Interrupt coalescing mechanism value is set in MV-643xx chip.
587 *
588 * RETURN:
589 * The interrupt coalescing value set in the gigE port.
590 *
591 */
592static unsigned int eth_port_set_rx_coal(unsigned int eth_port_num,
593 unsigned int t_clk, unsigned int delay)
594{
595 unsigned int coal = ((t_clk / 1000000) * delay) / 64;
596
597 /* Set RX Coalescing mechanism */
598 mv_write(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num),
599 ((coal & 0x3fff) << 8) |
600 (mv_read(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num))
601 & 0xffc000ff));
602
603 return coal;
604}
605#endif
606
607/*
608 * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
609 *
610 * DESCRIPTION:
611 * This routine sets the TX coalescing interrupt mechanism parameter.
612 * This parameter is a timeout counter, that counts in 64 t_clk
613 * chunks ; that when timeout event occurs a maskable interrupt
614 * occurs.
615 * The parameter is calculated using the t_cLK frequency of the
616 * MV-643xx chip and the required delay in the interrupt in uSec
617 *
618 * INPUT:
619 * unsigned int eth_port_num Ethernet port number
620 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
621 * unsigned int delay Delay in uSeconds
622 *
623 * OUTPUT:
624 * Interrupt coalescing mechanism value is set in MV-643xx chip.
625 *
626 * RETURN:
627 * The interrupt coalescing value set in the gigE port.
628 *
629 */
630static unsigned int eth_port_set_tx_coal(unsigned int eth_port_num,
631 unsigned int t_clk, unsigned int delay)
632{
633 unsigned int coal;
634 coal = ((t_clk / 1000000) * delay) / 64;
635 /* Set TX Coalescing mechanism */
636 mv_write(MV643XX_ETH_TX_FIFO_URGENT_THRESHOLD_REG(eth_port_num),
637 coal << 4);
638 return coal;
639}
640
641/*
642 * mv643xx_eth_open
643 *
644 * This function is called when openning the network device. The function
645 * should initialize all the hardware, initialize cyclic Rx/Tx
646 * descriptors chain and buffers and allocate an IRQ to the network
647 * device.
648 *
649 * Input : a pointer to the network device structure
650 *
651 * Output : zero of success , nonzero if fails.
652 */
653
654static int mv643xx_eth_open(struct net_device *dev)
655{
656 struct mv643xx_private *mp = netdev_priv(dev);
657 unsigned int port_num = mp->port_num;
658 int err;
659
660 spin_lock_irq(&mp->lock);
661
662 err = request_irq(dev->irq, mv643xx_eth_int_handler,
16b81757 663 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
1da177e4
LT		 664
665 if (err) {
666 printk(KERN_ERR "Can not assign IRQ number to MV643XX_eth%d\n",
667 port_num);
668 err = -EAGAIN;
669 goto out;
670 }
671
672 if (mv643xx_eth_real_open(dev)) {
673 printk("%s: Error opening interface\n", dev->name);
674 err = -EBUSY;
675 goto out_free;
676 }
677
678 spin_unlock_irq(&mp->lock);
679
680 return 0;
681
682out_free:
683 free_irq(dev->irq, dev);
684
685out:
686 spin_unlock_irq(&mp->lock);
687
688 return err;
689}
690
691/*
692 * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
693 *
694 * DESCRIPTION:
695 * This function prepares a Rx chained list of descriptors and packet
696 * buffers in a form of a ring. The routine must be called after port
697 * initialization routine and before port start routine.
698 * The Ethernet SDMA engine uses CPU bus addresses to access the various
699 * devices in the system (i.e. DRAM). This function uses the ethernet
700 * struct 'virtual to physical' routine (set by the user) to set the ring
701 * with physical addresses.
702 *
703 * INPUT:
704 * struct mv643xx_private *mp Ethernet Port Control srtuct.
705 *
706 * OUTPUT:
707 * The routine updates the Ethernet port control struct with information
708 * regarding the Rx descriptors and buffers.
709 *
710 * RETURN:
711 * None.
712 */
713static void ether_init_rx_desc_ring(struct mv643xx_private *mp)
714{
715 volatile struct eth_rx_desc *p_rx_desc;
716 int rx_desc_num = mp->rx_ring_size;
717 int i;
718
719 /* initialize the next_desc_ptr links in the Rx descriptors ring */
720 p_rx_desc = (struct eth_rx_desc *)mp->p_rx_desc_area;
721 for (i = 0; i < rx_desc_num; i++) {
722 p_rx_desc[i].next_desc_ptr = mp->rx_desc_dma +
723 ((i + 1) % rx_desc_num) * sizeof(struct eth_rx_desc);
724 }
725
726 /* Save Rx desc pointer to driver struct. */
727 mp->rx_curr_desc_q = 0;
728 mp->rx_used_desc_q = 0;
729
730 mp->rx_desc_area_size = rx_desc_num * sizeof(struct eth_rx_desc);
731
732 /* Add the queue to the list of RX queues of this port */
733 mp->port_rx_queue_command |= 1;
734}
735
736/*
737 * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
738 *
739 * DESCRIPTION:
740 * This function prepares a Tx chained list of descriptors and packet
741 * buffers in a form of a ring. The routine must be called after port
742 * initialization routine and before port start routine.
743 * The Ethernet SDMA engine uses CPU bus addresses to access the various
744 * devices in the system (i.e. DRAM). This function uses the ethernet
745 * struct 'virtual to physical' routine (set by the user) to set the ring
746 * with physical addresses.
747 *
748 * INPUT:
749 * struct mv643xx_private *mp Ethernet Port Control srtuct.
750 *
751 * OUTPUT:
752 * The routine updates the Ethernet port control struct with information
753 * regarding the Tx descriptors and buffers.
754 *
755 * RETURN:
756 * None.
757 */
758static void ether_init_tx_desc_ring(struct mv643xx_private *mp)
759{
760 int tx_desc_num = mp->tx_ring_size;
761 struct eth_tx_desc *p_tx_desc;
762 int i;
763
764 /* Initialize the next_desc_ptr links in the Tx descriptors ring */
765 p_tx_desc = (struct eth_tx_desc *)mp->p_tx_desc_area;
766 for (i = 0; i < tx_desc_num; i++) {
767 p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma +
768 ((i + 1) % tx_desc_num) * sizeof(struct eth_tx_desc);
769 }
770
771 mp->tx_curr_desc_q = 0;
772 mp->tx_used_desc_q = 0;
773#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
774 mp->tx_first_desc_q = 0;
775#endif
776
777 mp->tx_desc_area_size = tx_desc_num * sizeof(struct eth_tx_desc);
778
779 /* Add the queue to the list of Tx queues of this port */
780 mp->port_tx_queue_command |= 1;
781}
782
783/* Helper function for mv643xx_eth_open */
784static int mv643xx_eth_real_open(struct net_device *dev)
785{
786 struct mv643xx_private *mp = netdev_priv(dev);
787 unsigned int port_num = mp->port_num;
788 unsigned int size;
789
790 /* Stop RX Queues */
791 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), 0x0000ff00);
792
793 /* Clear the ethernet port interrupts */
794 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
795 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
796
797 /* Unmask RX buffer and TX end interrupt */
798 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
799 INT_CAUSE_UNMASK_ALL);
800
801 /* Unmask phy and link status changes interrupts */
802 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
803 INT_CAUSE_UNMASK_ALL_EXT);
804
805 /* Set the MAC Address */
806 memcpy(mp->port_mac_addr, dev->dev_addr, 6);
807
808 eth_port_init(mp);
809
810 INIT_WORK(&mp->rx_task, (void (*)(void *))mv643xx_eth_rx_task, dev);
811
812 memset(&mp->timeout, 0, sizeof(struct timer_list));
813 mp->timeout.function = mv643xx_eth_rx_task_timer_wrapper;
814 mp->timeout.data = (unsigned long)dev;
815
816 mp->rx_task_busy = 0;
817 mp->rx_timer_flag = 0;
818
819 /* Allocate RX and TX skb rings */
820 mp->rx_skb = kmalloc(sizeof(*mp->rx_skb) * mp->rx_ring_size,
821 GFP_KERNEL);
822 if (!mp->rx_skb) {
823 printk(KERN_ERR "%s: Cannot allocate Rx skb ring\n", dev->name);
824 return -ENOMEM;
825 }
826 mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size,
827 GFP_KERNEL);
828 if (!mp->tx_skb) {
829 printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name);
830 kfree(mp->rx_skb);
831 return -ENOMEM;
832 }
833
834 /* Allocate TX ring */
835 mp->tx_ring_skbs = 0;
836 size = mp->tx_ring_size * sizeof(struct eth_tx_desc);
837 mp->tx_desc_area_size = size;
838
839 if (mp->tx_sram_size) {
840 mp->p_tx_desc_area = ioremap(mp->tx_sram_addr,
841 mp->tx_sram_size);
842 mp->tx_desc_dma = mp->tx_sram_addr;
843 } else
844 mp->p_tx_desc_area = dma_alloc_coherent(NULL, size,
845 &mp->tx_desc_dma,
846 GFP_KERNEL);
847
848 if (!mp->p_tx_desc_area) {
849 printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n",
850 dev->name, size);
851 kfree(mp->rx_skb);
852 kfree(mp->tx_skb);
853 return -ENOMEM;
854 }
855 BUG_ON((u32) mp->p_tx_desc_area & 0xf); /* check 16-byte alignment */
856 memset((void *)mp->p_tx_desc_area, 0, mp->tx_desc_area_size);
857
858 ether_init_tx_desc_ring(mp);
859
860 /* Allocate RX ring */
861 mp->rx_ring_skbs = 0;
862 size = mp->rx_ring_size * sizeof(struct eth_rx_desc);
863 mp->rx_desc_area_size = size;
864
865 if (mp->rx_sram_size) {
866 mp->p_rx_desc_area = ioremap(mp->rx_sram_addr,
867 mp->rx_sram_size);
868 mp->rx_desc_dma = mp->rx_sram_addr;
869 } else
870 mp->p_rx_desc_area = dma_alloc_coherent(NULL, size,
871 &mp->rx_desc_dma,
872 GFP_KERNEL);
873
874 if (!mp->p_rx_desc_area) {
875 printk(KERN_ERR "%s: Cannot allocate Rx ring (size %d bytes)\n",
876 dev->name, size);
877 printk(KERN_ERR "%s: Freeing previously allocated TX queues...",
878 dev->name);
879 if (mp->rx_sram_size)
880 iounmap(mp->p_rx_desc_area);
881 else
882 dma_free_coherent(NULL, mp->tx_desc_area_size,
883 mp->p_tx_desc_area, mp->tx_desc_dma);
884 kfree(mp->rx_skb);
885 kfree(mp->tx_skb);
886 return -ENOMEM;
887 }
888 memset((void *)mp->p_rx_desc_area, 0, size);
889
890 ether_init_rx_desc_ring(mp);
891
892 mv643xx_eth_rx_task(dev); /* Fill RX ring with skb's */
893
894 eth_port_start(mp);
895
896 /* Interrupt Coalescing */
897
898#ifdef MV643XX_COAL
899 mp->rx_int_coal =
900 eth_port_set_rx_coal(port_num, 133000000, MV643XX_RX_COAL);
901#endif
902
903 mp->tx_int_coal =
904 eth_port_set_tx_coal(port_num, 133000000, MV643XX_TX_COAL);
905
906 netif_start_queue(dev);
907
908 return 0;
909}
910
911static void mv643xx_eth_free_tx_rings(struct net_device *dev)
912{
913 struct mv643xx_private *mp = netdev_priv(dev);
914 unsigned int port_num = mp->port_num;
915 unsigned int curr;
916
917 /* Stop Tx Queues */
918 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num), 0x0000ff00);
919
920 /* Free outstanding skb's on TX rings */
921 for (curr = 0; mp->tx_ring_skbs && curr < mp->tx_ring_size; curr++) {
922 if (mp->tx_skb[curr]) {
923 dev_kfree_skb(mp->tx_skb[curr]);
924 mp->tx_ring_skbs--;
925 }
926 }
927 if (mp->tx_ring_skbs)
928 printk("%s: Error on Tx descriptor free - could not free %d"
929 " descriptors\n", dev->name, mp->tx_ring_skbs);
930
931 /* Free TX ring */
932 if (mp->tx_sram_size)
933 iounmap(mp->p_tx_desc_area);
934 else
935 dma_free_coherent(NULL, mp->tx_desc_area_size,
936 mp->p_tx_desc_area, mp->tx_desc_dma);
937}
938
939static void mv643xx_eth_free_rx_rings(struct net_device *dev)
940{
941 struct mv643xx_private *mp = netdev_priv(dev);
942 unsigned int port_num = mp->port_num;
943 int curr;
944
945 /* Stop RX Queues */
946 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), 0x0000ff00);
947
948 /* Free preallocated skb's on RX rings */
949 for (curr = 0; mp->rx_ring_skbs && curr < mp->rx_ring_size; curr++) {
950 if (mp->rx_skb[curr]) {
951 dev_kfree_skb(mp->rx_skb[curr]);
952 mp->rx_ring_skbs--;
953 }
954 }
955
956 if (mp->rx_ring_skbs)
957 printk(KERN_ERR
958 "%s: Error in freeing Rx Ring. %d skb's still"
959 " stuck in RX Ring - ignoring them\n", dev->name,
960 mp->rx_ring_skbs);
961 /* Free RX ring */
962 if (mp->rx_sram_size)
963 iounmap(mp->p_rx_desc_area);
964 else
965 dma_free_coherent(NULL, mp->rx_desc_area_size,
966 mp->p_rx_desc_area, mp->rx_desc_dma);
967}
968
969/*
970 * mv643xx_eth_stop
971 *
972 * This function is used when closing the network device.
973 * It updates the hardware,
974 * release all memory that holds buffers and descriptors and release the IRQ.
975 * Input : a pointer to the device structure
976 * Output : zero if success , nonzero if fails
977 */
978
979/* Helper function for mv643xx_eth_stop */
980
981static int mv643xx_eth_real_stop(struct net_device *dev)
982{
983 struct mv643xx_private *mp = netdev_priv(dev);
984 unsigned int port_num = mp->port_num;
985
986 netif_carrier_off(dev);
987 netif_stop_queue(dev);
988
989 mv643xx_eth_free_tx_rings(dev);
990 mv643xx_eth_free_rx_rings(dev);
991
992 eth_port_reset(mp->port_num);
993
994 /* Disable ethernet port interrupts */
995 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
996 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
997
998 /* Mask RX buffer and TX end interrupt */
999 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), 0);
1000
1001 /* Mask phy and link status changes interrupts */
1002 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num), 0);
1003
1004 return 0;
1005}
1006
1007static int mv643xx_eth_stop(struct net_device *dev)
1008{
1009 struct mv643xx_private *mp = netdev_priv(dev);
1010
1011 spin_lock_irq(&mp->lock);
1012
1013 mv643xx_eth_real_stop(dev);
1014
1015 free_irq(dev->irq, dev);
1016 spin_unlock_irq(&mp->lock);
1017
1018 return 0;
1019}
1020
1021#ifdef MV643XX_NAPI
1022static void mv643xx_tx(struct net_device *dev)
1023{
1024 struct mv643xx_private *mp = netdev_priv(dev);
1025 struct pkt_info pkt_info;
1026
1027 while (eth_tx_return_desc(mp, &pkt_info) == ETH_OK) {
cb415d30
PG		 1028 if (pkt_info.cmd_sts & ETH_TX_FIRST_DESC)
1029 dma_unmap_single(NULL, pkt_info.buf_ptr,
1030 pkt_info.byte_cnt,
1031 DMA_TO_DEVICE);
1032 else
1033 dma_unmap_page(NULL, pkt_info.buf_ptr,
1034 pkt_info.byte_cnt,
1035 DMA_TO_DEVICE);
1da177e4 1036
cb415d30 1037 if (pkt_info.return_info)
1da177e4 1038 dev_kfree_skb_irq(pkt_info.return_info);
1da177e4
LT		 1039 }
1040
1041 if (netif_queue_stopped(dev) &&
1042 mp->tx_ring_size > mp->tx_ring_skbs + MAX_DESCS_PER_SKB)
1043 netif_wake_queue(dev);
1044}
1045
1046/*
1047 * mv643xx_poll
1048 *
1049 * This function is used in case of NAPI
1050 */
1051static int mv643xx_poll(struct net_device *dev, int *budget)
1052{
1053 struct mv643xx_private *mp = netdev_priv(dev);
1054 int done = 1, orig_budget, work_done;
1055 unsigned int port_num = mp->port_num;
1056 unsigned long flags;
1057
1058#ifdef MV643XX_TX_FAST_REFILL
1059 if (++mp->tx_clean_threshold > 5) {
1060 spin_lock_irqsave(&mp->lock, flags);
1061 mv643xx_tx(dev);
1062 mp->tx_clean_threshold = 0;
1063 spin_unlock_irqrestore(&mp->lock, flags);
1064 }
1065#endif
1066
1067 if ((mv_read(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num)))
1068 != (u32) mp->rx_used_desc_q) {
1069 orig_budget = *budget;
1070 if (orig_budget > dev->quota)
1071 orig_budget = dev->quota;
1072 work_done = mv643xx_eth_receive_queue(dev, orig_budget);
1073 mp->rx_task.func(dev);
1074 *budget -= work_done;
1075 dev->quota -= work_done;
1076 if (work_done >= orig_budget)
1077 done = 0;
1078 }
1079
1080 if (done) {
1081 spin_lock_irqsave(&mp->lock, flags);
1082 __netif_rx_complete(dev);
1083 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
1084 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
1085 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
1086 INT_CAUSE_UNMASK_ALL);
1087 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
1088 INT_CAUSE_UNMASK_ALL_EXT);
1089 spin_unlock_irqrestore(&mp->lock, flags);
1090 }
1091
1092 return done ? 0 : 1;
1093}
1094#endif
1095
1096/*
1097 * mv643xx_eth_start_xmit
1098 *
1099 * This function is queues a packet in the Tx descriptor for
1100 * required port.
1101 *
1102 * Input : skb - a pointer to socket buffer
1103 * dev - a pointer to the required port
1104 *
1105 * Output : zero upon success
1106 */
1107static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
1108{
1109 struct mv643xx_private *mp = netdev_priv(dev);
1110 struct net_device_stats *stats = &mp->stats;
1111 ETH_FUNC_RET_STATUS status;
1112 unsigned long flags;
1113 struct pkt_info pkt_info;
1114
1115 if (netif_queue_stopped(dev)) {
1116 printk(KERN_ERR
1117 "%s: Tried sending packet when interface is stopped\n",
1118 dev->name);
1119 return 1;
1120 }
1121
1122 /* This is a hard error, log it. */
1123 if ((mp->tx_ring_size - mp->tx_ring_skbs) <=
1124 (skb_shinfo(skb)->nr_frags + 1)) {
1125 netif_stop_queue(dev);
1126 printk(KERN_ERR
1127 "%s: Bug in mv643xx_eth - Trying to transmit when"
1128 " queue full !\n", dev->name);
1129 return 1;
1130 }
1131
1132 /* Paranoid check - this shouldn't happen */
1133 if (skb == NULL) {
1134 stats->tx_dropped++;
1135 printk(KERN_ERR "mv64320_eth paranoid check failed\n");
1136 return 1;
1137 }
1138
1139 spin_lock_irqsave(&mp->lock, flags);
1140
1141 /* Update packet info data structure -- DMA owned, first last */
1142#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1143 if (!skb_shinfo(skb)->nr_frags) {
1144linear:
1145 if (skb->ip_summed != CHECKSUM_HW) {
26006360 1146 /* Errata BTS #50, IHL must be 5 if no HW checksum */
1da177e4 1147 pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT |
26006360
DF		 1148 ETH_TX_FIRST_DESC |
1149 ETH_TX_LAST_DESC |
1150 5 << ETH_TX_IHL_SHIFT;
1da177e4
LT		 1151 pkt_info.l4i_chk = 0;
1152 } else {
1da177e4
LT		 1153
1154 pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT |
26006360
DF		 1155 ETH_TX_FIRST_DESC |
1156 ETH_TX_LAST_DESC |
1157 ETH_GEN_TCP_UDP_CHECKSUM |
1158 ETH_GEN_IP_V_4_CHECKSUM |
1159 skb->nh.iph->ihl << ETH_TX_IHL_SHIFT;
1da177e4
LT		 1160 /* CPU already calculated pseudo header checksum. */
1161 if (skb->nh.iph->protocol == IPPROTO_UDP) {
1162 pkt_info.cmd_sts |= ETH_UDP_FRAME;
1163 pkt_info.l4i_chk = skb->h.uh->check;
1164 } else if (skb->nh.iph->protocol == IPPROTO_TCP)
1165 pkt_info.l4i_chk = skb->h.th->check;
1166 else {
1167 printk(KERN_ERR
1168 "%s: chksum proto != TCP or UDP\n",
1169 dev->name);
1170 spin_unlock_irqrestore(&mp->lock, flags);
1171 return 1;
1172 }
1173 }
1174 pkt_info.byte_cnt = skb->len;
1175 pkt_info.buf_ptr = dma_map_single(NULL, skb->data, skb->len,
1176 DMA_TO_DEVICE);
1177 pkt_info.return_info = skb;
1da177e4
LT		 1178 status = eth_port_send(mp, &pkt_info);
1179 if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL))
1180 printk(KERN_ERR "%s: Error on transmitting packet\n",
1181 dev->name);
1182 stats->tx_bytes += pkt_info.byte_cnt;
1183 } else {
1184 unsigned int frag;
1da177e4
LT		 1185
1186 /* Since hardware can't handle unaligned fragments smaller
1187 * than 9 bytes, if we find any, we linearize the skb
1188 * and start again. When I've seen it, it's always been
1189 * the first frag (probably near the end of the page),
1190 * but we check all frags to be safe.
1191 */
1192 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1193 skb_frag_t *fragp;
1194
1195 fragp = &skb_shinfo(skb)->frags[frag];
1196 if (fragp->size <= 8 && fragp->page_offset & 0x7) {
1197 skb_linearize(skb, GFP_ATOMIC);
1198 printk(KERN_DEBUG "%s: unaligned tiny fragment"
1199 "%d of %d, fixed\n",
1200 dev->name, frag,
1201 skb_shinfo(skb)->nr_frags);
1202 goto linear;
1203 }
1204 }
1205
1206 /* first frag which is skb header */
1207 pkt_info.byte_cnt = skb_headlen(skb);
1208 pkt_info.buf_ptr = dma_map_single(NULL, skb->data,
1209 skb_headlen(skb),
1210 DMA_TO_DEVICE);
1211 pkt_info.l4i_chk = 0;
1212 pkt_info.return_info = 0;
1da177e4 1213
26006360
DF		 1214 if (skb->ip_summed != CHECKSUM_HW)
1215 /* Errata BTS #50, IHL must be 5 if no HW checksum */
1216 pkt_info.cmd_sts = ETH_TX_FIRST_DESC |
1217 5 << ETH_TX_IHL_SHIFT;
1218 else {
1219 pkt_info.cmd_sts = ETH_TX_FIRST_DESC |
1220 ETH_GEN_TCP_UDP_CHECKSUM |
1221 ETH_GEN_IP_V_4_CHECKSUM |
1222 skb->nh.iph->ihl << ETH_TX_IHL_SHIFT;
1da177e4
LT		 1223 /* CPU already calculated pseudo header checksum. */
1224 if (skb->nh.iph->protocol == IPPROTO_UDP) {
1225 pkt_info.cmd_sts |= ETH_UDP_FRAME;
1226 pkt_info.l4i_chk = skb->h.uh->check;
1227 } else if (skb->nh.iph->protocol == IPPROTO_TCP)
1228 pkt_info.l4i_chk = skb->h.th->check;
1229 else {
1230 printk(KERN_ERR
1231 "%s: chksum proto != TCP or UDP\n",
1232 dev->name);
1233 spin_unlock_irqrestore(&mp->lock, flags);
1234 return 1;
1235 }
1236 }
1237
1238 status = eth_port_send(mp, &pkt_info);
1239 if (status != ETH_OK) {
1240 if ((status == ETH_ERROR))
1241 printk(KERN_ERR
1242 "%s: Error on transmitting packet\n",
1243 dev->name);
1244 if (status == ETH_QUEUE_FULL)
1245 printk("Error on Queue Full \n");
1246 if (status == ETH_QUEUE_LAST_RESOURCE)
1247 printk("Tx resource error \n");
1248 }
1249 stats->tx_bytes += pkt_info.byte_cnt;
1250
1251 /* Check for the remaining frags */
1252 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1253 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
1254 pkt_info.l4i_chk = 0x0000;
1255 pkt_info.cmd_sts = 0x00000000;
1256
1257 /* Last Frag enables interrupt and frees the skb */
1258 if (frag == (skb_shinfo(skb)->nr_frags - 1)) {
1259 pkt_info.cmd_sts |= ETH_TX_ENABLE_INTERRUPT |
1260 ETH_TX_LAST_DESC;
1261 pkt_info.return_info = skb;
1da177e4
LT		 1262 } else {
1263 pkt_info.return_info = 0;
1264 }
1265 pkt_info.l4i_chk = 0;
1266 pkt_info.byte_cnt = this_frag->size;
1267
1268 pkt_info.buf_ptr = dma_map_page(NULL, this_frag->page,
1269 this_frag->page_offset,
1270 this_frag->size,
1271 DMA_TO_DEVICE);
1272
1273 status = eth_port_send(mp, &pkt_info);
1274
1275 if (status != ETH_OK) {
1276 if ((status == ETH_ERROR))
1277 printk(KERN_ERR "%s: Error on "
1278 "transmitting packet\n",
1279 dev->name);
1280
1281 if (status == ETH_QUEUE_LAST_RESOURCE)
1282 printk("Tx resource error \n");
1283
1284 if (status == ETH_QUEUE_FULL)
1285 printk("Queue is full \n");
1286 }
1287 stats->tx_bytes += pkt_info.byte_cnt;
1288 }
1289 }
1290#else
1291 pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT | ETH_TX_FIRST_DESC |
1292 ETH_TX_LAST_DESC;
1293 pkt_info.l4i_chk = 0;
1294 pkt_info.byte_cnt = skb->len;
1295 pkt_info.buf_ptr = dma_map_single(NULL, skb->data, skb->len,
1296 DMA_TO_DEVICE);
1297 pkt_info.return_info = skb;
1da177e4
LT		 1298 status = eth_port_send(mp, &pkt_info);
1299 if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL))
1300 printk(KERN_ERR "%s: Error on transmitting packet\n",
1301 dev->name);
1302 stats->tx_bytes += pkt_info.byte_cnt;
1303#endif
1304
1305 /* Check if TX queue can handle another skb. If not, then
1306 * signal higher layers to stop requesting TX
1307 */
1308 if (mp->tx_ring_size <= (mp->tx_ring_skbs + MAX_DESCS_PER_SKB))
1309 /*
1310 * Stop getting skb's from upper layers.
1311 * Getting skb's from upper layers will be enabled again after
1312 * packets are released.
1313 */
1314 netif_stop_queue(dev);
1315
1316 /* Update statistics and start of transmittion time */
1317 stats->tx_packets++;
1318 dev->trans_start = jiffies;
1319
1320 spin_unlock_irqrestore(&mp->lock, flags);
1321
1322 return 0; /* success */
1323}
1324
1325/*
1326 * mv643xx_eth_get_stats
1327 *
1328 * Returns a pointer to the interface statistics.
1329 *
1330 * Input : dev - a pointer to the required interface
1331 *
1332 * Output : a pointer to the interface's statistics
1333 */
1334
1335static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1336{
1337 struct mv643xx_private *mp = netdev_priv(dev);
1338
1339 return &mp->stats;
1340}
1341
63c9e549
DF		 1342#ifdef CONFIG_NET_POLL_CONTROLLER
1343static inline void mv643xx_enable_irq(struct mv643xx_private *mp)
1344{
1345 int port_num = mp->port_num;
1346 unsigned long flags;
1347
1348 spin_lock_irqsave(&mp->lock, flags);
1349 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
1350 INT_CAUSE_UNMASK_ALL);
1351 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
1352 INT_CAUSE_UNMASK_ALL_EXT);
1353 spin_unlock_irqrestore(&mp->lock, flags);
1354}
1355
1356static inline void mv643xx_disable_irq(struct mv643xx_private *mp)
1357{
1358 int port_num = mp->port_num;
1359 unsigned long flags;
1360
1361 spin_lock_irqsave(&mp->lock, flags);
1362 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
1363 INT_CAUSE_MASK_ALL);
1364 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
1365 INT_CAUSE_MASK_ALL_EXT);
1366 spin_unlock_irqrestore(&mp->lock, flags);
1367}
1368
1369static void mv643xx_netpoll(struct net_device *netdev)
1370{
1371 struct mv643xx_private *mp = netdev_priv(netdev);
1372
1373 mv643xx_disable_irq(mp);
1374 mv643xx_eth_int_handler(netdev->irq, netdev, NULL);
1375 mv643xx_enable_irq(mp);
1376}
1377#endif
1378
1da177e4
LT		 1379/*/
1380 * mv643xx_eth_probe
1381 *
1382 * First function called after registering the network device.
1383 * It's purpose is to initialize the device as an ethernet device,
1384 * fill the ethernet device structure with pointers * to functions,
1385 * and set the MAC address of the interface
1386 *
1387 * Input : struct device *
1388 * Output : -ENOMEM if failed , 0 if success
1389 */
3ae5eaec 1390static int mv643xx_eth_probe(struct platform_device *pdev)
1da177e4 1391{
1da177e4
LT		 1392 struct mv643xx_eth_platform_data *pd;
1393 int port_num = pdev->id;
1394 struct mv643xx_private *mp;
1395 struct net_device *dev;
1396 u8 *p;
1397 struct resource *res;
1398 int err;
1399
1400 dev = alloc_etherdev(sizeof(struct mv643xx_private));
1401 if (!dev)
1402 return -ENOMEM;
1403
3ae5eaec 1404 platform_set_drvdata(pdev, dev);
1da177e4
LT		 1405
1406 mp = netdev_priv(dev);
1407
1408 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1409 BUG_ON(!res);
1410 dev->irq = res->start;
1411
1412 mp->port_num = port_num;
1413
1414 dev->open = mv643xx_eth_open;
1415 dev->stop = mv643xx_eth_stop;
1416 dev->hard_start_xmit = mv643xx_eth_start_xmit;
1417 dev->get_stats = mv643xx_eth_get_stats;
1418 dev->set_mac_address = mv643xx_eth_set_mac_address;
1419 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
1420
1421 /* No need to Tx Timeout */
1422 dev->tx_timeout = mv643xx_eth_tx_timeout;
1423#ifdef MV643XX_NAPI
1424 dev->poll = mv643xx_poll;
1425 dev->weight = 64;
1426#endif
1427
63c9e549
DF		 1428#ifdef CONFIG_NET_POLL_CONTROLLER
1429 dev->poll_controller = mv643xx_netpoll;
1430#endif
1431
1da177e4
LT		 1432 dev->watchdog_timeo = 2 * HZ;
1433 dev->tx_queue_len = mp->tx_ring_size;
1434 dev->base_addr = 0;
1435 dev->change_mtu = mv643xx_eth_change_mtu;
1436 SET_ETHTOOL_OPS(dev, &mv643xx_ethtool_ops);
1437
1438#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1439#ifdef MAX_SKB_FRAGS
1440 /*
1441 * Zero copy can only work if we use Discovery II memory. Else, we will
1442 * have to map the buffers to ISA memory which is only 16 MB
1443 */
1444 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_HW_CSUM;
1445#endif
1446#endif
1447
1448 /* Configure the timeout task */
1449 INIT_WORK(&mp->tx_timeout_task,
1450 (void (*)(void *))mv643xx_eth_tx_timeout_task, dev);
1451
1452 spin_lock_init(&mp->lock);
1453
1454 /* set default config values */
1455 eth_port_uc_addr_get(dev, dev->dev_addr);
1456 mp->port_config = MV643XX_ETH_PORT_CONFIG_DEFAULT_VALUE;
1457 mp->port_config_extend = MV643XX_ETH_PORT_CONFIG_EXTEND_DEFAULT_VALUE;
1458 mp->port_sdma_config = MV643XX_ETH_PORT_SDMA_CONFIG_DEFAULT_VALUE;
1459 mp->port_serial_control = MV643XX_ETH_PORT_SERIAL_CONTROL_DEFAULT_VALUE;
1460 mp->rx_ring_size = MV643XX_ETH_PORT_DEFAULT_RECEIVE_QUEUE_SIZE;
1461 mp->tx_ring_size = MV643XX_ETH_PORT_DEFAULT_TRANSMIT_QUEUE_SIZE;
1462
1463 pd = pdev->dev.platform_data;
1464 if (pd) {
1465 if (pd->mac_addr != NULL)
1466 memcpy(dev->dev_addr, pd->mac_addr, 6);
1467
1468 if (pd->phy_addr || pd->force_phy_addr)
1469 ethernet_phy_set(port_num, pd->phy_addr);
1470
1471 if (pd->port_config || pd->force_port_config)
1472 mp->port_config = pd->port_config;
1473
1474 if (pd->port_config_extend || pd->force_port_config_extend)
1475 mp->port_config_extend = pd->port_config_extend;
1476
1477 if (pd->port_sdma_config || pd->force_port_sdma_config)
1478 mp->port_sdma_config = pd->port_sdma_config;
1479
1480 if (pd->port_serial_control || pd->force_port_serial_control)
1481 mp->port_serial_control = pd->port_serial_control;
1482
1483 if (pd->rx_queue_size)
1484 mp->rx_ring_size = pd->rx_queue_size;
1485
1486 if (pd->tx_queue_size)
1487 mp->tx_ring_size = pd->tx_queue_size;
1488
1489 if (pd->tx_sram_size) {
1490 mp->tx_sram_size = pd->tx_sram_size;
1491 mp->tx_sram_addr = pd->tx_sram_addr;
1492 }
1493
1494 if (pd->rx_sram_size) {
1495 mp->rx_sram_size = pd->rx_sram_size;
1496 mp->rx_sram_addr = pd->rx_sram_addr;
1497 }
1498 }
1499
1500 err = ethernet_phy_detect(port_num);
1501 if (err) {
1502 pr_debug("MV643xx ethernet port %d: "
1503 "No PHY detected at addr %d\n",
1504 port_num, ethernet_phy_get(port_num));
1505 return err;
1506 }
1507
1508 err = register_netdev(dev);
1509 if (err)
1510 goto out;
1511
1512 p = dev->dev_addr;
1513 printk(KERN_NOTICE
1514 "%s: port %d with MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
1515 dev->name, port_num, p[0], p[1], p[2], p[3], p[4], p[5]);
1516
1517 if (dev->features & NETIF_F_SG)
1518 printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name);
1519
1520 if (dev->features & NETIF_F_IP_CSUM)
1521 printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n",
1522 dev->name);
1523
1524#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1525 printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name);
1526#endif
1527
1528#ifdef MV643XX_COAL
1529 printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n",
1530 dev->name);
1531#endif
1532
1533#ifdef MV643XX_NAPI
1534 printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name);
1535#endif
1536
b1529871
ND		 1537 if (mp->tx_sram_size > 0)
1538 printk(KERN_NOTICE "%s: Using SRAM\n", dev->name);
1539
1da177e4
LT		 1540 return 0;
1541
1542out:
1543 free_netdev(dev);
1544
1545 return err;
1546}
1547
3ae5eaec 1548static int mv643xx_eth_remove(struct platform_device *pdev)
1da177e4 1549{
3ae5eaec 1550 struct net_device *dev = platform_get_drvdata(pdev);
1da177e4
LT		 1551
1552 unregister_netdev(dev);
1553 flush_scheduled_work();
1554
1555 free_netdev(dev);
3ae5eaec 1556 platform_set_drvdata(pdev, NULL);
1da177e4
LT		 1557 return 0;
1558}
1559
3ae5eaec 1560static int mv643xx_eth_shared_probe(struct platform_device *pdev)
1da177e4 1561{
1da177e4
LT		 1562 struct resource *res;
1563
1564 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
1565
1566 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1567 if (res == NULL)
1568 return -ENODEV;
1569
1570 mv643xx_eth_shared_base = ioremap(res->start,
1571 MV643XX_ETH_SHARED_REGS_SIZE);
1572 if (mv643xx_eth_shared_base == NULL)
1573 return -ENOMEM;
1574
1575 return 0;
1576
1577}
1578
3ae5eaec 1579static int mv643xx_eth_shared_remove(struct platform_device *pdev)
1da177e4
LT		 1580{
1581 iounmap(mv643xx_eth_shared_base);
1582 mv643xx_eth_shared_base = NULL;
1583
1584 return 0;
1585}
1586
3ae5eaec 1587static struct platform_driver mv643xx_eth_driver = {
1da177e4
LT		 1588 .probe = mv643xx_eth_probe,
1589 .remove = mv643xx_eth_remove,
3ae5eaec
RK		 1590 .driver = {
1591 .name = MV643XX_ETH_NAME,
1592 },
1da177e4
LT		 1593};
1594
3ae5eaec 1595static struct platform_driver mv643xx_eth_shared_driver = {
1da177e4
LT		 1596 .probe = mv643xx_eth_shared_probe,
1597 .remove = mv643xx_eth_shared_remove,
3ae5eaec
RK		 1598 .driver = {
1599 .name = MV643XX_ETH_SHARED_NAME,
1600 },
1da177e4
LT		 1601};
1602
1603/*
1604 * mv643xx_init_module
1605 *
1606 * Registers the network drivers into the Linux kernel
1607 *
1608 * Input : N/A
1609 *
1610 * Output : N/A
1611 */
1612static int __init mv643xx_init_module(void)
1613{
1614 int rc;
1615
3ae5eaec 1616 rc = platform_driver_register(&mv643xx_eth_shared_driver);
1da177e4 1617 if (!rc) {
3ae5eaec 1618 rc = platform_driver_register(&mv643xx_eth_driver);
1da177e4 1619 if (rc)
3ae5eaec 1620 platform_driver_unregister(&mv643xx_eth_shared_driver);
1da177e4
LT		 1621 }
1622 return rc;
1623}
1624
1625/*
1626 * mv643xx_cleanup_module
1627 *
1628 * Registers the network drivers into the Linux kernel
1629 *
1630 * Input : N/A
1631 *
1632 * Output : N/A
1633 */
1634static void __exit mv643xx_cleanup_module(void)
1635{
3ae5eaec
RK		 1636 platform_driver_unregister(&mv643xx_eth_driver);
1637 platform_driver_unregister(&mv643xx_eth_shared_driver);
1da177e4
LT		 1638}
1639
1640module_init(mv643xx_init_module);
1641module_exit(mv643xx_cleanup_module);
1642
1643MODULE_LICENSE("GPL");
1644MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani"
1645 " and Dale Farnsworth");
1646MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
1647
1648/*
1649 * The second part is the low level driver of the gigE ethernet ports.
1650 */
1651
1652/*
1653 * Marvell's Gigabit Ethernet controller low level driver
1654 *
1655 * DESCRIPTION:
1656 * This file introduce low level API to Marvell's Gigabit Ethernet
1657 * controller. This Gigabit Ethernet Controller driver API controls
1658 * 1) Operations (i.e. port init, start, reset etc').
1659 * 2) Data flow (i.e. port send, receive etc').
1660 * Each Gigabit Ethernet port is controlled via
1661 * struct mv643xx_private.
1662 * This struct includes user configuration information as well as
1663 * driver internal data needed for its operations.
1664 *
1665 * Supported Features:
1666 * - This low level driver is OS independent. Allocating memory for
1667 * the descriptor rings and buffers are not within the scope of
1668 * this driver.
1669 * - The user is free from Rx/Tx queue managing.
1670 * - This low level driver introduce functionality API that enable
1671 * the to operate Marvell's Gigabit Ethernet Controller in a
1672 * convenient way.
1673 * - Simple Gigabit Ethernet port operation API.
1674 * - Simple Gigabit Ethernet port data flow API.
1675 * - Data flow and operation API support per queue functionality.
1676 * - Support cached descriptors for better performance.
1677 * - Enable access to all four DRAM banks and internal SRAM memory
1678 * spaces.
1679 * - PHY access and control API.
1680 * - Port control register configuration API.
1681 * - Full control over Unicast and Multicast MAC configurations.
1682 *
1683 * Operation flow:
1684 *
1685 * Initialization phase
1686 * This phase complete the initialization of the the
1687 * mv643xx_private struct.
1688 * User information regarding port configuration has to be set
1689 * prior to calling the port initialization routine.
1690 *
1691 * In this phase any port Tx/Rx activity is halted, MIB counters
1692 * are cleared, PHY address is set according to user parameter and
1693 * access to DRAM and internal SRAM memory spaces.
1694 *
1695 * Driver ring initialization
1696 * Allocating memory for the descriptor rings and buffers is not
1697 * within the scope of this driver. Thus, the user is required to
1698 * allocate memory for the descriptors ring and buffers. Those
1699 * memory parameters are used by the Rx and Tx ring initialization
1700 * routines in order to curve the descriptor linked list in a form
1701 * of a ring.
1702 * Note: Pay special attention to alignment issues when using
1703 * cached descriptors/buffers. In this phase the driver store
1704 * information in the mv643xx_private struct regarding each queue
1705 * ring.
1706 *
1707 * Driver start
1708 * This phase prepares the Ethernet port for Rx and Tx activity.
1709 * It uses the information stored in the mv643xx_private struct to
1710 * initialize the various port registers.
1711 *
1712 * Data flow:
1713 * All packet references to/from the driver are done using
1714 * struct pkt_info.
1715 * This struct is a unified struct used with Rx and Tx operations.
1716 * This way the user is not required to be familiar with neither
1717 * Tx nor Rx descriptors structures.
1718 * The driver's descriptors rings are management by indexes.
1719 * Those indexes controls the ring resources and used to indicate
1720 * a SW resource error:
1721 * 'current'
1722 * This index points to the current available resource for use. For
1723 * example in Rx process this index will point to the descriptor
1724 * that will be passed to the user upon calling the receive
1725 * routine. In Tx process, this index will point to the descriptor
1726 * that will be assigned with the user packet info and transmitted.
1727 * 'used'
1728 * This index points to the descriptor that need to restore its
1729 * resources. For example in Rx process, using the Rx buffer return
1730 * API will attach the buffer returned in packet info to the
1731 * descriptor pointed by 'used'. In Tx process, using the Tx
1732 * descriptor return will merely return the user packet info with
1733 * the command status of the transmitted buffer pointed by the
1734 * 'used' index. Nevertheless, it is essential to use this routine
1735 * to update the 'used' index.
1736 * 'first'
1737 * This index supports Tx Scatter-Gather. It points to the first
1738 * descriptor of a packet assembled of multiple buffers. For
1739 * example when in middle of Such packet we have a Tx resource
1740 * error the 'curr' index get the value of 'first' to indicate
1741 * that the ring returned to its state before trying to transmit
1742 * this packet.
1743 *
1744 * Receive operation:
1745 * The eth_port_receive API set the packet information struct,
1746 * passed by the caller, with received information from the
1747 * 'current' SDMA descriptor.
1748 * It is the user responsibility to return this resource back
1749 * to the Rx descriptor ring to enable the reuse of this source.
1750 * Return Rx resource is done using the eth_rx_return_buff API.
1751 *
1752 * Transmit operation:
1753 * The eth_port_send API supports Scatter-Gather which enables to
1754 * send a packet spanned over multiple buffers. This means that
1755 * for each packet info structure given by the user and put into
1756 * the Tx descriptors ring, will be transmitted only if the 'LAST'
1757 * bit will be set in the packet info command status field. This
1758 * API also consider restriction regarding buffer alignments and
1759 * sizes.
1760 * The user must return a Tx resource after ensuring the buffer
1761 * has been transmitted to enable the Tx ring indexes to update.
1762 *
1763 * BOARD LAYOUT
1764 * This device is on-board. No jumper diagram is necessary.
1765 *
1766 * EXTERNAL INTERFACE
1767 *
1768 * Prior to calling the initialization routine eth_port_init() the user
1769 * must set the following fields under mv643xx_private struct:
1770 * port_num User Ethernet port number.
1771 * port_mac_addr[6] User defined port MAC address.
1772 * port_config User port configuration value.
1773 * port_config_extend User port config extend value.
1774 * port_sdma_config User port SDMA config value.
1775 * port_serial_control User port serial control value.
1776 *
1777 * This driver data flow is done using the struct pkt_info which
1778 * is a unified struct for Rx and Tx operations:
1779 *
1780 * byte_cnt Tx/Rx descriptor buffer byte count.
1781 * l4i_chk CPU provided TCP Checksum. For Tx operation
1782 * only.
1783 * cmd_sts Tx/Rx descriptor command status.
1784 * buf_ptr Tx/Rx descriptor buffer pointer.
1785 * return_info Tx/Rx user resource return information.
1786 */
1787
1788/* defines */
1789/* SDMA command macros */
1790#define ETH_ENABLE_TX_QUEUE(eth_port) \
1791 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), 1)
1792
1793/* locals */
1794
1795/* PHY routines */
1796static int ethernet_phy_get(unsigned int eth_port_num);
1797static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
1798
1799/* Ethernet Port routines */
1800static int eth_port_uc_addr(unsigned int eth_port_num, unsigned char uc_nibble,
1801 int option);
1802
1803/*
1804 * eth_port_init - Initialize the Ethernet port driver
1805 *
1806 * DESCRIPTION:
1807 * This function prepares the ethernet port to start its activity:
1808 * 1) Completes the ethernet port driver struct initialization toward port
1809 * start routine.
1810 * 2) Resets the device to a quiescent state in case of warm reboot.
1811 * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
1812 * 4) Clean MAC tables. The reset status of those tables is unknown.
1813 * 5) Set PHY address.
1814 * Note: Call this routine prior to eth_port_start routine and after
1815 * setting user values in the user fields of Ethernet port control
1816 * struct.
1817 *
1818 * INPUT:
1819 * struct mv643xx_private *mp Ethernet port control struct
1820 *
1821 * OUTPUT:
1822 * See description.
1823 *
1824 * RETURN:
1825 * None.
1826 */
1827static void eth_port_init(struct mv643xx_private *mp)
1828{
1829 mp->port_rx_queue_command = 0;
1830 mp->port_tx_queue_command = 0;
1831
1832 mp->rx_resource_err = 0;
1833 mp->tx_resource_err = 0;
1834
1835 eth_port_reset(mp->port_num);
1836
1837 eth_port_init_mac_tables(mp->port_num);
1838
1839 ethernet_phy_reset(mp->port_num);
1840}
1841
1842/*
1843 * eth_port_start - Start the Ethernet port activity.
1844 *
1845 * DESCRIPTION:
1846 * This routine prepares the Ethernet port for Rx and Tx activity:
1847 * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
1848 * has been initialized a descriptor's ring (using
1849 * ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx)
1850 * 2. Initialize and enable the Ethernet configuration port by writing to
1851 * the port's configuration and command registers.
1852 * 3. Initialize and enable the SDMA by writing to the SDMA's
1853 * configuration and command registers. After completing these steps,
1854 * the ethernet port SDMA can starts to perform Rx and Tx activities.
1855 *
1856 * Note: Each Rx and Tx queue descriptor's list must be initialized prior
1857 * to calling this function (use ether_init_tx_desc_ring for Tx queues
1858 * and ether_init_rx_desc_ring for Rx queues).
1859 *
1860 * INPUT:
1861 * struct mv643xx_private *mp Ethernet port control struct
1862 *
1863 * OUTPUT:
1864 * Ethernet port is ready to receive and transmit.
1865 *
1866 * RETURN:
1867 * None.
1868 */
1869static void eth_port_start(struct mv643xx_private *mp)
1870{
1871 unsigned int port_num = mp->port_num;
1872 int tx_curr_desc, rx_curr_desc;
1873
1874 /* Assignment of Tx CTRP of given queue */
1875 tx_curr_desc = mp->tx_curr_desc_q;
1876 mv_write(MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port_num),
1877 (u32)((struct eth_tx_desc *)mp->tx_desc_dma + tx_curr_desc));
1878
1879 /* Assignment of Rx CRDP of given queue */
1880 rx_curr_desc = mp->rx_curr_desc_q;
1881 mv_write(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num),
1882 (u32)((struct eth_rx_desc *)mp->rx_desc_dma + rx_curr_desc));
1883
1884 /* Add the assigned Ethernet address to the port's address table */
1885 eth_port_uc_addr_set(port_num, mp->port_mac_addr);
1886
1887 /* Assign port configuration and command. */
1888 mv_write(MV643XX_ETH_PORT_CONFIG_REG(port_num), mp->port_config);
1889
1890 mv_write(MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port_num),
1891 mp->port_config_extend);
1892
1893
1894 /* Increase the Rx side buffer size if supporting GigE */
1895 if (mp->port_serial_control & MV643XX_ETH_SET_GMII_SPEED_TO_1000)
1896 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
1897 (mp->port_serial_control & 0xfff1ffff) | (0x5 << 17));
1898 else
1899 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
1900 mp->port_serial_control);
1901
1902 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
1903 mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num)) |
1904 MV643XX_ETH_SERIAL_PORT_ENABLE);
1905
1906 /* Assign port SDMA configuration */
1907 mv_write(MV643XX_ETH_SDMA_CONFIG_REG(port_num),
1908 mp->port_sdma_config);
1909
1910 /* Enable port Rx. */
1911 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num),
1912 mp->port_rx_queue_command);
8f543718
DF		 1913
1914 /* Disable port bandwidth limits by clearing MTU register */
1915 mv_write(MV643XX_ETH_MAXIMUM_TRANSMIT_UNIT(port_num), 0);
1da177e4
LT		 1916}
1917
1918/*
1919 * eth_port_uc_addr_set - This function Set the port Unicast address.
1920 *
1921 * DESCRIPTION:
1922 * This function Set the port Ethernet MAC address.
1923 *
1924 * INPUT:
1925 * unsigned int eth_port_num Port number.
1926 * char * p_addr Address to be set
1927 *
1928 * OUTPUT:
1929 * Set MAC address low and high registers. also calls eth_port_uc_addr()
1930 * To set the unicast table with the proper information.
1931 *
1932 * RETURN:
1933 * N/A.
1934 *
1935 */
1936static void eth_port_uc_addr_set(unsigned int eth_port_num,
1937 unsigned char *p_addr)
1938{
1939 unsigned int mac_h;
1940 unsigned int mac_l;
1941
1942 mac_l = (p_addr[4] << 8) | (p_addr[5]);
1943 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
1944 (p_addr[3] << 0);
1945
1946 mv_write(MV643XX_ETH_MAC_ADDR_LOW(eth_port_num), mac_l);
1947 mv_write(MV643XX_ETH_MAC_ADDR_HIGH(eth_port_num), mac_h);
1948
1949 /* Accept frames of this address */
1950 eth_port_uc_addr(eth_port_num, p_addr[5], ACCEPT_MAC_ADDR);
1951
1952 return;
1953}
1954
1955/*
1956 * eth_port_uc_addr_get - This function retrieves the port Unicast address
1957 * (MAC address) from the ethernet hw registers.
1958 *
1959 * DESCRIPTION:
1960 * This function retrieves the port Ethernet MAC address.
1961 *
1962 * INPUT:
1963 * unsigned int eth_port_num Port number.
1964 * char *MacAddr pointer where the MAC address is stored
1965 *
1966 * OUTPUT:
1967 * Copy the MAC address to the location pointed to by MacAddr
1968 *
1969 * RETURN:
1970 * N/A.
1971 *
1972 */
1973static void eth_port_uc_addr_get(struct net_device *dev, unsigned char *p_addr)
1974{
1975 struct mv643xx_private *mp = netdev_priv(dev);
1976 unsigned int mac_h;
1977 unsigned int mac_l;
1978
1979 mac_h = mv_read(MV643XX_ETH_MAC_ADDR_HIGH(mp->port_num));
1980 mac_l = mv_read(MV643XX_ETH_MAC_ADDR_LOW(mp->port_num));
1981
1982 p_addr[0] = (mac_h >> 24) & 0xff;
1983 p_addr[1] = (mac_h >> 16) & 0xff;
1984 p_addr[2] = (mac_h >> 8) & 0xff;
1985 p_addr[3] = mac_h & 0xff;
1986 p_addr[4] = (mac_l >> 8) & 0xff;
1987 p_addr[5] = mac_l & 0xff;
1988}
1989
1990/*
1991 * eth_port_uc_addr - This function Set the port unicast address table
1992 *
1993 * DESCRIPTION:
1994 * This function locates the proper entry in the Unicast table for the
1995 * specified MAC nibble and sets its properties according to function
1996 * parameters.
1997 *
1998 * INPUT:
1999 * unsigned int eth_port_num Port number.
2000 * unsigned char uc_nibble Unicast MAC Address last nibble.
2001 * int option 0 = Add, 1 = remove address.
2002 *
2003 * OUTPUT:
2004 * This function add/removes MAC addresses from the port unicast address
2005 * table.
2006 *
2007 * RETURN:
2008 * true is output succeeded.
2009 * false if option parameter is invalid.
2010 *
2011 */
2012static int eth_port_uc_addr(unsigned int eth_port_num, unsigned char uc_nibble,
2013 int option)
2014{
2015 unsigned int unicast_reg;
2016 unsigned int tbl_offset;
2017 unsigned int reg_offset;
2018
2019 /* Locate the Unicast table entry */
2020 uc_nibble = (0xf & uc_nibble);
2021 tbl_offset = (uc_nibble / 4) * 4; /* Register offset from unicast table base */
2022 reg_offset = uc_nibble % 4; /* Entry offset within the above register */
2023
2024 switch (option) {
2025 case REJECT_MAC_ADDR:
2026 /* Clear accepts frame bit at given unicast DA table entry */
2027 unicast_reg = mv_read((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2028 (eth_port_num) + tbl_offset));
2029
2030 unicast_reg &= (0x0E << (8 * reg_offset));
2031
2032 mv_write((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2033 (eth_port_num) + tbl_offset), unicast_reg);
2034 break;
2035
2036 case ACCEPT_MAC_ADDR:
2037 /* Set accepts frame bit at unicast DA filter table entry */
2038 unicast_reg =
2039 mv_read((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2040 (eth_port_num) + tbl_offset));
2041
2042 unicast_reg |= (0x01 << (8 * reg_offset));
2043
2044 mv_write((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2045 (eth_port_num) + tbl_offset), unicast_reg);
2046
2047 break;
2048
2049 default:
2050 return 0;
2051 }
2052
2053 return 1;
2054}
2055
16e03018
DF		 2056/*
2057 * The entries in each table are indexed by a hash of a packet's MAC
2058 * address. One bit in each entry determines whether the packet is
2059 * accepted. There are 4 entries (each 8 bits wide) in each register
2060 * of the table. The bits in each entry are defined as follows:
2061 * 0 Accept=1, Drop=0
2062 * 3-1 Queue (ETH_Q0=0)
2063 * 7-4 Reserved = 0;
2064 */
2065static void eth_port_set_filter_table_entry(int table, unsigned char entry)
2066{
2067 unsigned int table_reg;
2068 unsigned int tbl_offset;
2069 unsigned int reg_offset;
2070
2071 tbl_offset = (entry / 4) * 4; /* Register offset of DA table entry */
2072 reg_offset = entry % 4; /* Entry offset within the register */
2073
2074 /* Set "accepts frame bit" at specified table entry */
2075 table_reg = mv_read(table + tbl_offset);
2076 table_reg |= 0x01 << (8 * reg_offset);
2077 mv_write(table + tbl_offset, table_reg);
2078}
2079
2080/*
2081 * eth_port_mc_addr - Multicast address settings.
2082 *
2083 * The MV device supports multicast using two tables:
2084 * 1) Special Multicast Table for MAC addresses of the form
2085 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_FF).
2086 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
2087 * Table entries in the DA-Filter table.
2088 * 2) Other Multicast Table for multicast of another type. A CRC-8bit
2089 * is used as an index to the Other Multicast Table entries in the
2090 * DA-Filter table. This function calculates the CRC-8bit value.
2091 * In either case, eth_port_set_filter_table_entry() is then called
2092 * to set to set the actual table entry.
2093 */
2094static void eth_port_mc_addr(unsigned int eth_port_num, unsigned char *p_addr)
2095{
2096 unsigned int mac_h;
2097 unsigned int mac_l;
2098 unsigned char crc_result = 0;
2099 int table;
2100 int mac_array[48];
2101 int crc[8];
2102 int i;
2103
2104 if ((p_addr[0] == 0x01) && (p_addr[1] == 0x00) &&
2105 (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) {
2106 table = MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2107 (eth_port_num);
2108 eth_port_set_filter_table_entry(table, p_addr[5]);
2109 return;
2110 }
2111
2112 /* Calculate CRC-8 out of the given address */
2113 mac_h = (p_addr[0] << 8) | (p_addr[1]);
2114 mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
2115 (p_addr[4] << 8) | (p_addr[5] << 0);
2116
2117 for (i = 0; i < 32; i++)
2118 mac_array[i] = (mac_l >> i) & 0x1;
2119 for (i = 32; i < 48; i++)
2120 mac_array[i] = (mac_h >> (i - 32)) & 0x1;
2121
2122 crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ mac_array[39] ^
2123 mac_array[35] ^ mac_array[34] ^ mac_array[31] ^ mac_array[30] ^
2124 mac_array[28] ^ mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
2125 mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ mac_array[12] ^
2126 mac_array[8] ^ mac_array[7] ^ mac_array[6] ^ mac_array[0];
2127
2128 crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
2129 mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ mac_array[34] ^
2130 mac_array[32] ^ mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
2131 mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ mac_array[21] ^
2132 mac_array[20] ^ mac_array[18] ^ mac_array[17] ^ mac_array[16] ^
2133 mac_array[15] ^ mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
2134 mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ mac_array[0];
2135
2136 crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ mac_array[43] ^
2137 mac_array[42] ^ mac_array[39] ^ mac_array[37] ^ mac_array[34] ^
2138 mac_array[33] ^ mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
2139 mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ mac_array[15] ^
2140 mac_array[13] ^ mac_array[12] ^ mac_array[10] ^ mac_array[8] ^
2141 mac_array[6] ^ mac_array[2] ^ mac_array[1] ^ mac_array[0];
2142
2143 crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
2144 mac_array[40] ^ mac_array[38] ^ mac_array[35] ^ mac_array[34] ^
2145 mac_array[30] ^ mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
2146 mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
2147 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[7] ^
2148 mac_array[3] ^ mac_array[2] ^ mac_array[1];
2149
2150 crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[41] ^
2151 mac_array[39] ^ mac_array[36] ^ mac_array[35] ^ mac_array[31] ^
2152 mac_array[30] ^ mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
2153 mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ mac_array[14] ^
2154 mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ mac_array[4] ^
2155 mac_array[3] ^ mac_array[2];
2156
2157 crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ mac_array[42] ^
2158 mac_array[40] ^ mac_array[37] ^ mac_array[36] ^ mac_array[32] ^
2159 mac_array[31] ^ mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
2160 mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ mac_array[15] ^
2161 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[5] ^
2162 mac_array[4] ^ mac_array[3];
2163
2164 crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ mac_array[41] ^
2165 mac_array[38] ^ mac_array[37] ^ mac_array[33] ^ mac_array[32] ^
2166 mac_array[29] ^ mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
2167 mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ mac_array[14] ^
2168 mac_array[12] ^ mac_array[10] ^ mac_array[6] ^ mac_array[5] ^
2169 mac_array[4];
2170
2171 crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ mac_array[39] ^
2172 mac_array[38] ^ mac_array[34] ^ mac_array[33] ^ mac_array[30] ^
2173 mac_array[29] ^ mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
2174 mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ mac_array[13] ^
2175 mac_array[11] ^ mac_array[7] ^ mac_array[6] ^ mac_array[5];
2176
2177 for (i = 0; i < 8; i++)
2178 crc_result = crc_result | (crc[i] << i);
2179
2180 table = MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num);
2181 eth_port_set_filter_table_entry(table, crc_result);
2182}
2183
2184/*
2185 * Set the entire multicast list based on dev->mc_list.
2186 */
2187static void eth_port_set_multicast_list(struct net_device *dev)
2188{
2189
2190 struct dev_mc_list *mc_list;
2191 int i;
2192 int table_index;
2193 struct mv643xx_private *mp = netdev_priv(dev);
2194 unsigned int eth_port_num = mp->port_num;
2195
2196 /* If the device is in promiscuous mode or in all multicast mode,
2197 * we will fully populate both multicast tables with accept.
2198 * This is guaranteed to yield a match on all multicast addresses...
2199 */
2200 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) {
2201 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2202 /* Set all entries in DA filter special multicast
2203 * table (Ex_dFSMT)
2204 * Set for ETH_Q0 for now
2205 * Bits
2206 * 0 Accept=1, Drop=0
2207 * 3-1 Queue ETH_Q0=0
2208 * 7-4 Reserved = 0;
2209 */
2210 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
2211
2212 /* Set all entries in DA filter other multicast
2213 * table (Ex_dFOMT)
2214 * Set for ETH_Q0 for now
2215 * Bits
2216 * 0 Accept=1, Drop=0
2217 * 3-1 Queue ETH_Q0=0
2218 * 7-4 Reserved = 0;
2219 */
2220 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
2221 }
2222 return;
2223 }
2224
2225 /* We will clear out multicast tables every time we get the list.
2226 * Then add the entire new list...
2227 */
2228 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2229 /* Clear DA filter special multicast table (Ex_dFSMT) */
2230 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2231 (eth_port_num) + table_index, 0);
2232
2233 /* Clear DA filter other multicast table (Ex_dFOMT) */
2234 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2235 (eth_port_num) + table_index, 0);
2236 }
2237
2238 /* Get pointer to net_device multicast list and add each one... */
2239 for (i = 0, mc_list = dev->mc_list;
2240 (i < 256) && (mc_list != NULL) && (i < dev->mc_count);
2241 i++, mc_list = mc_list->next)
2242 if (mc_list->dmi_addrlen == 6)
2243 eth_port_mc_addr(eth_port_num, mc_list->dmi_addr);
2244}
2245
1da177e4
LT		 2246/*
2247 * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
2248 *
2249 * DESCRIPTION:
2250 * Go through all the DA filter tables (Unicast, Special Multicast &
2251 * Other Multicast) and set each entry to 0.
2252 *
2253 * INPUT:
2254 * unsigned int eth_port_num Ethernet Port number.
2255 *
2256 * OUTPUT:
2257 * Multicast and Unicast packets are rejected.
2258 *
2259 * RETURN:
2260 * None.
2261 */
2262static void eth_port_init_mac_tables(unsigned int eth_port_num)
2263{
2264 int table_index;
2265
2266 /* Clear DA filter unicast table (Ex_dFUT) */
2267 for (table_index = 0; table_index <= 0xC; table_index += 4)
2268 mv_write((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2269 (eth_port_num) + table_index), 0);
2270
2271 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2272 /* Clear DA filter special multicast table (Ex_dFSMT) */
16e03018
DF		 2273 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2274 (eth_port_num) + table_index, 0);
1da177e4 2275 /* Clear DA filter other multicast table (Ex_dFOMT) */
16e03018
DF		 2276 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2277 (eth_port_num) + table_index, 0);
1da177e4
LT		 2278 }
2279}
2280
2281/*
2282 * eth_clear_mib_counters - Clear all MIB counters
2283 *
2284 * DESCRIPTION:
2285 * This function clears all MIB counters of a specific ethernet port.
2286 * A read from the MIB counter will reset the counter.
2287 *
2288 * INPUT:
2289 * unsigned int eth_port_num Ethernet Port number.
2290 *
2291 * OUTPUT:
2292 * After reading all MIB counters, the counters resets.
2293 *
2294 * RETURN:
2295 * MIB counter value.
2296 *
2297 */
2298static void eth_clear_mib_counters(unsigned int eth_port_num)
2299{
2300 int i;
2301
2302 /* Perform dummy reads from MIB counters */
2303 for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
2304 i += 4)
2305 mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(eth_port_num) + i);
2306}
2307
2308static inline u32 read_mib(struct mv643xx_private *mp, int offset)
2309{
2310 return mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(mp->port_num) + offset);
2311}
2312
2313static void eth_update_mib_counters(struct mv643xx_private *mp)
2314{
2315 struct mv643xx_mib_counters *p = &mp->mib_counters;
2316 int offset;
2317
2318 p->good_octets_received +=
2319 read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
2320 p->good_octets_received +=
2321 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32;
2322
2323 for (offset = ETH_MIB_BAD_OCTETS_RECEIVED;
2324 offset <= ETH_MIB_FRAMES_1024_TO_MAX_OCTETS;
2325 offset += 4)
2326 *(u32 *)((char *)p + offset) = read_mib(mp, offset);
2327
2328 p->good_octets_sent += read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_LOW);
2329 p->good_octets_sent +=
2330 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_HIGH) << 32;
2331
2332 for (offset = ETH_MIB_GOOD_FRAMES_SENT;
2333 offset <= ETH_MIB_LATE_COLLISION;
2334 offset += 4)
2335 *(u32 *)((char *)p + offset) = read_mib(mp, offset);
2336}
2337
2338/*
2339 * ethernet_phy_detect - Detect whether a phy is present
2340 *
2341 * DESCRIPTION:
2342 * This function tests whether there is a PHY present on
2343 * the specified port.
2344 *
2345 * INPUT:
2346 * unsigned int eth_port_num Ethernet Port number.
2347 *
2348 * OUTPUT:
2349 * None
2350 *
2351 * RETURN:
2352 * 0 on success
2353 * -ENODEV on failure
2354 *
2355 */
2356static int ethernet_phy_detect(unsigned int port_num)
2357{
2358 unsigned int phy_reg_data0;
2359 int auto_neg;
2360
2361 eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
2362 auto_neg = phy_reg_data0 & 0x1000;
2363 phy_reg_data0 ^= 0x1000; /* invert auto_neg */
2364 eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
2365
2366 eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
2367 if ((phy_reg_data0 & 0x1000) == auto_neg)
2368 return -ENODEV; /* change didn't take */
2369
2370 phy_reg_data0 ^= 0x1000;
2371 eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
2372 return 0;
2373}
2374
2375/*
2376 * ethernet_phy_get - Get the ethernet port PHY address.
2377 *
2378 * DESCRIPTION:
2379 * This routine returns the given ethernet port PHY address.
2380 *
2381 * INPUT:
2382 * unsigned int eth_port_num Ethernet Port number.
2383 *
2384 * OUTPUT:
2385 * None.
2386 *
2387 * RETURN:
2388 * PHY address.
2389 *
2390 */
2391static int ethernet_phy_get(unsigned int eth_port_num)
2392{
2393 unsigned int reg_data;
2394
2395 reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG);
2396
2397 return ((reg_data >> (5 * eth_port_num)) & 0x1f);
2398}
2399
2400/*
2401 * ethernet_phy_set - Set the ethernet port PHY address.
2402 *
2403 * DESCRIPTION:
2404 * This routine sets the given ethernet port PHY address.
2405 *
2406 * INPUT:
2407 * unsigned int eth_port_num Ethernet Port number.
2408 * int phy_addr PHY address.
2409 *
2410 * OUTPUT:
2411 * None.
2412 *
2413 * RETURN:
2414 * None.
2415 *
2416 */
2417static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr)
2418{
2419 u32 reg_data;
2420 int addr_shift = 5 * eth_port_num;
2421
2422 reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG);
2423 reg_data &= ~(0x1f << addr_shift);
2424 reg_data |= (phy_addr & 0x1f) << addr_shift;
2425 mv_write(MV643XX_ETH_PHY_ADDR_REG, reg_data);
2426}
2427
2428/*
2429 * ethernet_phy_reset - Reset Ethernet port PHY.
2430 *
2431 * DESCRIPTION:
2432 * This routine utilizes the SMI interface to reset the ethernet port PHY.
2433 *
2434 * INPUT:
2435 * unsigned int eth_port_num Ethernet Port number.
2436 *
2437 * OUTPUT:
2438 * The PHY is reset.
2439 *
2440 * RETURN:
2441 * None.
2442 *
2443 */
2444static void ethernet_phy_reset(unsigned int eth_port_num)
2445{
2446 unsigned int phy_reg_data;
2447
2448 /* Reset the PHY */
2449 eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data);
2450 phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
2451 eth_port_write_smi_reg(eth_port_num, 0, phy_reg_data);
2452}
2453
2454/*
2455 * eth_port_reset - Reset Ethernet port
2456 *
2457 * DESCRIPTION:
2458 * This routine resets the chip by aborting any SDMA engine activity and
2459 * clearing the MIB counters. The Receiver and the Transmit unit are in
2460 * idle state after this command is performed and the port is disabled.
2461 *
2462 * INPUT:
2463 * unsigned int eth_port_num Ethernet Port number.
2464 *
2465 * OUTPUT:
2466 * Channel activity is halted.
2467 *
2468 * RETURN:
2469 * None.
2470 *
2471 */
2472static void eth_port_reset(unsigned int port_num)
2473{
2474 unsigned int reg_data;
2475
2476 /* Stop Tx port activity. Check port Tx activity. */
2477 reg_data = mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num));
2478
2479 if (reg_data & 0xFF) {
2480 /* Issue stop command for active channels only */
2481 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num),
2482 (reg_data << 8));
2483
2484 /* Wait for all Tx activity to terminate. */
2485 /* Check port cause register that all Tx queues are stopped */
2486 while (mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num))
2487 & 0xFF)
2488 udelay(10);
2489 }
2490
2491 /* Stop Rx port activity. Check port Rx activity. */
2492 reg_data = mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num));
2493
2494 if (reg_data & 0xFF) {
2495 /* Issue stop command for active channels only */
2496 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num),
2497 (reg_data << 8));
2498
2499 /* Wait for all Rx activity to terminate. */
2500 /* Check port cause register that all Rx queues are stopped */
2501 while (mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num))
2502 & 0xFF)
2503 udelay(10);
2504 }
2505
2506 /* Clear all MIB counters */
2507 eth_clear_mib_counters(port_num);
2508
2509 /* Reset the Enable bit in the Configuration Register */
2510 reg_data = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
2511 reg_data &= ~MV643XX_ETH_SERIAL_PORT_ENABLE;
2512 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), reg_data);
2513}
2514
1da177e4
LT		 2515
2516static int eth_port_autoneg_supported(unsigned int eth_port_num)
2517{
2518 unsigned int phy_reg_data0;
2519
2520 eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data0);
2521
2522 return phy_reg_data0 & 0x1000;
2523}
2524
2525static int eth_port_link_is_up(unsigned int eth_port_num)
2526{
2527 unsigned int phy_reg_data1;
2528
2529 eth_port_read_smi_reg(eth_port_num, 1, &phy_reg_data1);
2530
2531 if (eth_port_autoneg_supported(eth_port_num)) {
2532 if (phy_reg_data1 & 0x20) /* auto-neg complete */
2533 return 1;
2534 } else if (phy_reg_data1 & 0x4) /* link up */
2535 return 1;
2536
2537 return 0;
2538}
2539
1da177e4
LT		 2540/*
2541 * eth_port_read_smi_reg - Read PHY registers
2542 *
2543 * DESCRIPTION:
2544 * This routine utilize the SMI interface to interact with the PHY in
2545 * order to perform PHY register read.
2546 *
2547 * INPUT:
2548 * unsigned int port_num Ethernet Port number.
2549 * unsigned int phy_reg PHY register address offset.
2550 * unsigned int *value Register value buffer.
2551 *
2552 * OUTPUT:
2553 * Write the value of a specified PHY register into given buffer.
2554 *
2555 * RETURN:
2556 * false if the PHY is busy or read data is not in valid state.
2557 * true otherwise.
2558 *
2559 */
2560static void eth_port_read_smi_reg(unsigned int port_num,
2561 unsigned int phy_reg, unsigned int *value)
2562{
2563 int phy_addr = ethernet_phy_get(port_num);
2564 unsigned long flags;
2565 int i;
2566
2567 /* the SMI register is a shared resource */
2568 spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
2569
2570 /* wait for the SMI register to become available */
2571 for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) {
2572 if (i == PHY_WAIT_ITERATIONS) {
2573 printk("mv643xx PHY busy timeout, port %d\n", port_num);
2574 goto out;
2575 }
2576 udelay(PHY_WAIT_MICRO_SECONDS);
2577 }
2578
2579 mv_write(MV643XX_ETH_SMI_REG,
2580 (phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ);
2581
2582 /* now wait for the data to be valid */
2583 for (i = 0; !(mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_READ_VALID); i++) {
2584 if (i == PHY_WAIT_ITERATIONS) {
2585 printk("mv643xx PHY read timeout, port %d\n", port_num);
2586 goto out;
2587 }
2588 udelay(PHY_WAIT_MICRO_SECONDS);
2589 }
2590
2591 *value = mv_read(MV643XX_ETH_SMI_REG) & 0xffff;
2592out:
2593 spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
2594}
2595
2596/*
2597 * eth_port_write_smi_reg - Write to PHY registers
2598 *
2599 * DESCRIPTION:
2600 * This routine utilize the SMI interface to interact with the PHY in
2601 * order to perform writes to PHY registers.
2602 *
2603 * INPUT:
2604 * unsigned int eth_port_num Ethernet Port number.
2605 * unsigned int phy_reg PHY register address offset.
2606 * unsigned int value Register value.
2607 *
2608 * OUTPUT:
2609 * Write the given value to the specified PHY register.
2610 *
2611 * RETURN:
2612 * false if the PHY is busy.
2613 * true otherwise.
2614 *
2615 */
2616static void eth_port_write_smi_reg(unsigned int eth_port_num,
2617 unsigned int phy_reg, unsigned int value)
2618{
2619 int phy_addr;
2620 int i;
2621 unsigned long flags;
2622
2623 phy_addr = ethernet_phy_get(eth_port_num);
2624
2625 /* the SMI register is a shared resource */
2626 spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
2627
2628 /* wait for the SMI register to become available */
2629 for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) {
2630 if (i == PHY_WAIT_ITERATIONS) {
2631 printk("mv643xx PHY busy timeout, port %d\n",
2632 eth_port_num);
2633 goto out;
2634 }
2635 udelay(PHY_WAIT_MICRO_SECONDS);
2636 }
2637
2638 mv_write(MV643XX_ETH_SMI_REG, (phy_addr << 16) | (phy_reg << 21) |
2639 ETH_SMI_OPCODE_WRITE | (value & 0xffff));
2640out:
2641 spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
2642}
2643
2644/*
2645 * eth_port_send - Send an Ethernet packet
2646 *
2647 * DESCRIPTION:
2648 * This routine send a given packet described by p_pktinfo parameter. It
2649 * supports transmitting of a packet spaned over multiple buffers. The
2650 * routine updates 'curr' and 'first' indexes according to the packet
2651 * segment passed to the routine. In case the packet segment is first,
2652 * the 'first' index is update. In any case, the 'curr' index is updated.
2653 * If the routine get into Tx resource error it assigns 'curr' index as
2654 * 'first'. This way the function can abort Tx process of multiple
2655 * descriptors per packet.
2656 *
2657 * INPUT:
2658 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2659 * struct pkt_info *p_pkt_info User packet buffer.
2660 *
2661 * OUTPUT:
2662 * Tx ring 'curr' and 'first' indexes are updated.
2663 *
2664 * RETURN:
2665 * ETH_QUEUE_FULL in case of Tx resource error.
2666 * ETH_ERROR in case the routine can not access Tx desc ring.
2667 * ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource.
2668 * ETH_OK otherwise.
2669 *
2670 */
2671#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
2672/*
2673 * Modified to include the first descriptor pointer in case of SG
2674 */
2675static ETH_FUNC_RET_STATUS eth_port_send(struct mv643xx_private *mp,
2676 struct pkt_info *p_pkt_info)
2677{
2678 int tx_desc_curr, tx_desc_used, tx_first_desc, tx_next_desc;
2679 struct eth_tx_desc *current_descriptor;
2680 struct eth_tx_desc *first_descriptor;
2681 u32 command;
2682
2683 /* Do not process Tx ring in case of Tx ring resource error */
2684 if (mp->tx_resource_err)
2685 return ETH_QUEUE_FULL;
2686
2687 /*
2688 * The hardware requires that each buffer that is <= 8 bytes
2689 * in length must be aligned on an 8 byte boundary.
2690 */
2691 if (p_pkt_info->byte_cnt <= 8 && p_pkt_info->buf_ptr & 0x7) {
2692 printk(KERN_ERR
2693 "mv643xx_eth port %d: packet size <= 8 problem\n",
2694 mp->port_num);
2695 return ETH_ERROR;
2696 }
2697
b111ceb6
DF		 2698 mp->tx_ring_skbs++;
2699 BUG_ON(mp->tx_ring_skbs > mp->tx_ring_size);
2700
1da177e4
LT		 2701 /* Get the Tx Desc ring indexes */
2702 tx_desc_curr = mp->tx_curr_desc_q;
2703 tx_desc_used = mp->tx_used_desc_q;
2704
2705 current_descriptor = &mp->p_tx_desc_area[tx_desc_curr];
2706
2707 tx_next_desc = (tx_desc_curr + 1) % mp->tx_ring_size;
2708
2709 current_descriptor->buf_ptr = p_pkt_info->buf_ptr;
2710 current_descriptor->byte_cnt = p_pkt_info->byte_cnt;
2711 current_descriptor->l4i_chk = p_pkt_info->l4i_chk;
2712 mp->tx_skb[tx_desc_curr] = p_pkt_info->return_info;
2713
2714 command = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC |
2715 ETH_BUFFER_OWNED_BY_DMA;
2716 if (command & ETH_TX_FIRST_DESC) {
2717 tx_first_desc = tx_desc_curr;
2718 mp->tx_first_desc_q = tx_first_desc;
2719 first_descriptor = current_descriptor;
2720 mp->tx_first_command = command;
2721 } else {
2722 tx_first_desc = mp->tx_first_desc_q;
2723 first_descriptor = &mp->p_tx_desc_area[tx_first_desc];
2724 BUG_ON(first_descriptor == NULL);
2725 current_descriptor->cmd_sts = command;
2726 }
2727
2728 if (command & ETH_TX_LAST_DESC) {
2729 wmb();
2730 first_descriptor->cmd_sts = mp->tx_first_command;
2731
2732 wmb();
2733 ETH_ENABLE_TX_QUEUE(mp->port_num);
2734
2735 /*
2736 * Finish Tx packet. Update first desc in case of Tx resource
2737 * error */
2738 tx_first_desc = tx_next_desc;
2739 mp->tx_first_desc_q = tx_first_desc;
2740 }
2741
2742 /* Check for ring index overlap in the Tx desc ring */
2743 if (tx_next_desc == tx_desc_used) {
2744 mp->tx_resource_err = 1;
2745 mp->tx_curr_desc_q = tx_first_desc;
2746
2747 return ETH_QUEUE_LAST_RESOURCE;
2748 }
2749
2750 mp->tx_curr_desc_q = tx_next_desc;
2751
2752 return ETH_OK;
2753}
2754#else
2755static ETH_FUNC_RET_STATUS eth_port_send(struct mv643xx_private *mp,
2756 struct pkt_info *p_pkt_info)
2757{
2758 int tx_desc_curr;
2759 int tx_desc_used;
2760 struct eth_tx_desc *current_descriptor;
2761 unsigned int command_status;
2762
2763 /* Do not process Tx ring in case of Tx ring resource error */
2764 if (mp->tx_resource_err)
2765 return ETH_QUEUE_FULL;
2766
b111ceb6
DF		 2767 mp->tx_ring_skbs++;
2768 BUG_ON(mp->tx_ring_skbs > mp->tx_ring_size);
2769
1da177e4
LT		 2770 /* Get the Tx Desc ring indexes */
2771 tx_desc_curr = mp->tx_curr_desc_q;
2772 tx_desc_used = mp->tx_used_desc_q;
2773 current_descriptor = &mp->p_tx_desc_area[tx_desc_curr];
2774
2775 command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC;
2776 current_descriptor->buf_ptr = p_pkt_info->buf_ptr;
2777 current_descriptor->byte_cnt = p_pkt_info->byte_cnt;
2778 mp->tx_skb[tx_desc_curr] = p_pkt_info->return_info;
2779
2780 /* Set last desc with DMA ownership and interrupt enable. */
2781 wmb();
2782 current_descriptor->cmd_sts = command_status |
2783 ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT;
2784
2785 wmb();
2786 ETH_ENABLE_TX_QUEUE(mp->port_num);
2787
2788 /* Finish Tx packet. Update first desc in case of Tx resource error */
2789 tx_desc_curr = (tx_desc_curr + 1) % mp->tx_ring_size;
2790
2791 /* Update the current descriptor */
2792 mp->tx_curr_desc_q = tx_desc_curr;
2793
2794 /* Check for ring index overlap in the Tx desc ring */
2795 if (tx_desc_curr == tx_desc_used) {
2796 mp->tx_resource_err = 1;
2797 return ETH_QUEUE_LAST_RESOURCE;
2798 }
2799
2800 return ETH_OK;
2801}
2802#endif
2803
2804/*
2805 * eth_tx_return_desc - Free all used Tx descriptors
2806 *
2807 * DESCRIPTION:
2808 * This routine returns the transmitted packet information to the caller.
2809 * It uses the 'first' index to support Tx desc return in case a transmit
2810 * of a packet spanned over multiple buffer still in process.
2811 * In case the Tx queue was in "resource error" condition, where there are
2812 * no available Tx resources, the function resets the resource error flag.
2813 *
2814 * INPUT:
2815 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2816 * struct pkt_info *p_pkt_info User packet buffer.
2817 *
2818 * OUTPUT:
2819 * Tx ring 'first' and 'used' indexes are updated.
2820 *
2821 * RETURN:
2822 * ETH_ERROR in case the routine can not access Tx desc ring.
2823 * ETH_RETRY in case there is transmission in process.
2824 * ETH_END_OF_JOB if the routine has nothing to release.
2825 * ETH_OK otherwise.
2826 *
2827 */
2828static ETH_FUNC_RET_STATUS eth_tx_return_desc(struct mv643xx_private *mp,
2829 struct pkt_info *p_pkt_info)
2830{
2831 int tx_desc_used;
2832#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
2833 int tx_busy_desc = mp->tx_first_desc_q;
2834#else
2835 int tx_busy_desc = mp->tx_curr_desc_q;
2836#endif
2837 struct eth_tx_desc *p_tx_desc_used;
2838 unsigned int command_status;
2839
2840 /* Get the Tx Desc ring indexes */
2841 tx_desc_used = mp->tx_used_desc_q;
2842
2843 p_tx_desc_used = &mp->p_tx_desc_area[tx_desc_used];
2844
2845 /* Sanity check */
2846 if (p_tx_desc_used == NULL)
2847 return ETH_ERROR;
2848
2849 /* Stop release. About to overlap the current available Tx descriptor */
2850 if (tx_desc_used == tx_busy_desc && !mp->tx_resource_err)
2851 return ETH_END_OF_JOB;
2852
2853 command_status = p_tx_desc_used->cmd_sts;
2854
2855 /* Still transmitting... */
2856 if (command_status & (ETH_BUFFER_OWNED_BY_DMA))
2857 return ETH_RETRY;
2858
2859 /* Pass the packet information to the caller */
2860 p_pkt_info->cmd_sts = command_status;
2861 p_pkt_info->return_info = mp->tx_skb[tx_desc_used];
4eaa3cb3
PG		 2862 p_pkt_info->buf_ptr = p_tx_desc_used->buf_ptr;
2863 p_pkt_info->byte_cnt = p_tx_desc_used->byte_cnt;
1da177e4
LT		 2864 mp->tx_skb[tx_desc_used] = NULL;
2865
2866 /* Update the next descriptor to release. */
2867 mp->tx_used_desc_q = (tx_desc_used + 1) % mp->tx_ring_size;
2868
2869 /* Any Tx return cancels the Tx resource error status */
2870 mp->tx_resource_err = 0;
2871
b111ceb6
DF		 2872 BUG_ON(mp->tx_ring_skbs == 0);
2873 mp->tx_ring_skbs--;
2874
1da177e4
LT		 2875 return ETH_OK;
2876}
2877
2878/*
2879 * eth_port_receive - Get received information from Rx ring.
2880 *
2881 * DESCRIPTION:
2882 * This routine returns the received data to the caller. There is no
2883 * data copying during routine operation. All information is returned
2884 * using pointer to packet information struct passed from the caller.
2885 * If the routine exhausts Rx ring resources then the resource error flag
2886 * is set.
2887 *
2888 * INPUT:
2889 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2890 * struct pkt_info *p_pkt_info User packet buffer.
2891 *
2892 * OUTPUT:
2893 * Rx ring current and used indexes are updated.
2894 *
2895 * RETURN:
2896 * ETH_ERROR in case the routine can not access Rx desc ring.
2897 * ETH_QUEUE_FULL if Rx ring resources are exhausted.
2898 * ETH_END_OF_JOB if there is no received data.
2899 * ETH_OK otherwise.
2900 */
2901static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
2902 struct pkt_info *p_pkt_info)
2903{
2904 int rx_next_curr_desc, rx_curr_desc, rx_used_desc;
2905 volatile struct eth_rx_desc *p_rx_desc;
2906 unsigned int command_status;
2907
2908 /* Do not process Rx ring in case of Rx ring resource error */
2909 if (mp->rx_resource_err)
2910 return ETH_QUEUE_FULL;
2911
2912 /* Get the Rx Desc ring 'curr and 'used' indexes */
2913 rx_curr_desc = mp->rx_curr_desc_q;
2914 rx_used_desc = mp->rx_used_desc_q;
2915
2916 p_rx_desc = &mp->p_rx_desc_area[rx_curr_desc];
2917
2918 /* The following parameters are used to save readings from memory */
2919 command_status = p_rx_desc->cmd_sts;
2920 rmb();
2921
2922 /* Nothing to receive... */
2923 if (command_status & (ETH_BUFFER_OWNED_BY_DMA))
2924 return ETH_END_OF_JOB;
2925
2926 p_pkt_info->byte_cnt = (p_rx_desc->byte_cnt) - RX_BUF_OFFSET;
2927 p_pkt_info->cmd_sts = command_status;
2928 p_pkt_info->buf_ptr = (p_rx_desc->buf_ptr) + RX_BUF_OFFSET;
2929 p_pkt_info->return_info = mp->rx_skb[rx_curr_desc];
2930 p_pkt_info->l4i_chk = p_rx_desc->buf_size;
2931
2932 /* Clean the return info field to indicate that the packet has been */
2933 /* moved to the upper layers */
2934 mp->rx_skb[rx_curr_desc] = NULL;
2935
2936 /* Update current index in data structure */
2937 rx_next_curr_desc = (rx_curr_desc + 1) % mp->rx_ring_size;
2938 mp->rx_curr_desc_q = rx_next_curr_desc;
2939
2940 /* Rx descriptors exhausted. Set the Rx ring resource error flag */
2941 if (rx_next_curr_desc == rx_used_desc)
2942 mp->rx_resource_err = 1;
2943
2944 return ETH_OK;
2945}
2946
2947/*
2948 * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
2949 *
2950 * DESCRIPTION:
2951 * This routine returns a Rx buffer back to the Rx ring. It retrieves the
2952 * next 'used' descriptor and attached the returned buffer to it.
2953 * In case the Rx ring was in "resource error" condition, where there are
2954 * no available Rx resources, the function resets the resource error flag.
2955 *
2956 * INPUT:
2957 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2958 * struct pkt_info *p_pkt_info Information on returned buffer.
2959 *
2960 * OUTPUT:
2961 * New available Rx resource in Rx descriptor ring.
2962 *
2963 * RETURN:
2964 * ETH_ERROR in case the routine can not access Rx desc ring.
2965 * ETH_OK otherwise.
2966 */
2967static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
2968 struct pkt_info *p_pkt_info)
2969{
2970 int used_rx_desc; /* Where to return Rx resource */
2971 volatile struct eth_rx_desc *p_used_rx_desc;
2972
2973 /* Get 'used' Rx descriptor */
2974 used_rx_desc = mp->rx_used_desc_q;
2975 p_used_rx_desc = &mp->p_rx_desc_area[used_rx_desc];
2976
2977 p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
2978 p_used_rx_desc->buf_size = p_pkt_info->byte_cnt;
2979 mp->rx_skb[used_rx_desc] = p_pkt_info->return_info;
2980
2981 /* Flush the write pipe */
2982
2983 /* Return the descriptor to DMA ownership */
2984 wmb();
2985 p_used_rx_desc->cmd_sts =
2986 ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
2987 wmb();
2988
2989 /* Move the used descriptor pointer to the next descriptor */
2990 mp->rx_used_desc_q = (used_rx_desc + 1) % mp->rx_ring_size;
2991
2992 /* Any Rx return cancels the Rx resource error status */
2993 mp->rx_resource_err = 0;
2994
2995 return ETH_OK;
2996}
2997
2998/************* Begin ethtool support *************************/
2999
3000struct mv643xx_stats {
3001 char stat_string[ETH_GSTRING_LEN];
3002 int sizeof_stat;
3003 int stat_offset;
3004};
3005
3006#define MV643XX_STAT(m) sizeof(((struct mv643xx_private *)0)->m), \
3007 offsetof(struct mv643xx_private, m)
3008
3009static const struct mv643xx_stats mv643xx_gstrings_stats[] = {
3010 { "rx_packets", MV643XX_STAT(stats.rx_packets) },
3011 { "tx_packets", MV643XX_STAT(stats.tx_packets) },
3012 { "rx_bytes", MV643XX_STAT(stats.rx_bytes) },
3013 { "tx_bytes", MV643XX_STAT(stats.tx_bytes) },
3014 { "rx_errors", MV643XX_STAT(stats.rx_errors) },
3015 { "tx_errors", MV643XX_STAT(stats.tx_errors) },
3016 { "rx_dropped", MV643XX_STAT(stats.rx_dropped) },
3017 { "tx_dropped", MV643XX_STAT(stats.tx_dropped) },
3018 { "good_octets_received", MV643XX_STAT(mib_counters.good_octets_received) },
3019 { "bad_octets_received", MV643XX_STAT(mib_counters.bad_octets_received) },
3020 { "internal_mac_transmit_err", MV643XX_STAT(mib_counters.internal_mac_transmit_err) },
3021 { "good_frames_received", MV643XX_STAT(mib_counters.good_frames_received) },
3022 { "bad_frames_received", MV643XX_STAT(mib_counters.bad_frames_received) },
3023 { "broadcast_frames_received", MV643XX_STAT(mib_counters.broadcast_frames_received) },
3024 { "multicast_frames_received", MV643XX_STAT(mib_counters.multicast_frames_received) },
3025 { "frames_64_octets", MV643XX_STAT(mib_counters.frames_64_octets) },
3026 { "frames_65_to_127_octets", MV643XX_STAT(mib_counters.frames_65_to_127_octets) },
3027 { "frames_128_to_255_octets", MV643XX_STAT(mib_counters.frames_128_to_255_octets) },
3028 { "frames_256_to_511_octets", MV643XX_STAT(mib_counters.frames_256_to_511_octets) },
3029 { "frames_512_to_1023_octets", MV643XX_STAT(mib_counters.frames_512_to_1023_octets) },
3030 { "frames_1024_to_max_octets", MV643XX_STAT(mib_counters.frames_1024_to_max_octets) },
3031 { "good_octets_sent", MV643XX_STAT(mib_counters.good_octets_sent) },
3032 { "good_frames_sent", MV643XX_STAT(mib_counters.good_frames_sent) },
3033 { "excessive_collision", MV643XX_STAT(mib_counters.excessive_collision) },
3034 { "multicast_frames_sent", MV643XX_STAT(mib_counters.multicast_frames_sent) },
3035 { "broadcast_frames_sent", MV643XX_STAT(mib_counters.broadcast_frames_sent) },
3036 { "unrec_mac_control_received", MV643XX_STAT(mib_counters.unrec_mac_control_received) },
3037 { "fc_sent", MV643XX_STAT(mib_counters.fc_sent) },
3038 { "good_fc_received", MV643XX_STAT(mib_counters.good_fc_received) },
3039 { "bad_fc_received", MV643XX_STAT(mib_counters.bad_fc_received) },
3040 { "undersize_received", MV643XX_STAT(mib_counters.undersize_received) },
3041 { "fragments_received", MV643XX_STAT(mib_counters.fragments_received) },
3042 { "oversize_received", MV643XX_STAT(mib_counters.oversize_received) },
3043 { "jabber_received", MV643XX_STAT(mib_counters.jabber_received) },
3044 { "mac_receive_error", MV643XX_STAT(mib_counters.mac_receive_error) },
3045 { "bad_crc_event", MV643XX_STAT(mib_counters.bad_crc_event) },
3046 { "collision", MV643XX_STAT(mib_counters.collision) },
3047 { "late_collision", MV643XX_STAT(mib_counters.late_collision) },
3048};
3049
3050#define MV643XX_STATS_LEN \
3051 sizeof(mv643xx_gstrings_stats) / sizeof(struct mv643xx_stats)
3052
3053static int
3054mv643xx_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
3055{
3056 struct mv643xx_private *mp = netdev->priv;
3057 int port_num = mp->port_num;
3058 int autoneg = eth_port_autoneg_supported(port_num);
3059 int mode_10_bit;
3060 int auto_duplex;
3061 int half_duplex = 0;
3062 int full_duplex = 0;
3063 int auto_speed;
3064 int speed_10 = 0;
3065 int speed_100 = 0;
3066 int speed_1000 = 0;
3067
3068 u32 pcs = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
3069 u32 psr = mv_read(MV643XX_ETH_PORT_STATUS_REG(port_num));
3070
3071 mode_10_bit = psr & MV643XX_ETH_PORT_STATUS_MODE_10_BIT;
3072
3073 if (mode_10_bit) {
3074 ecmd->supported = SUPPORTED_10baseT_Half;
3075 } else {
3076 ecmd->supported = (SUPPORTED_10baseT_Half |
3077 SUPPORTED_10baseT_Full |
3078 SUPPORTED_100baseT_Half |
3079 SUPPORTED_100baseT_Full |
3080 SUPPORTED_1000baseT_Full |
3081 (autoneg ? SUPPORTED_Autoneg : 0) |
3082 SUPPORTED_TP);
3083
3084 auto_duplex = !(pcs & MV643XX_ETH_DISABLE_AUTO_NEG_FOR_DUPLX);
3085 auto_speed = !(pcs & MV643XX_ETH_DISABLE_AUTO_NEG_SPEED_GMII);
3086
3087 ecmd->advertising = ADVERTISED_TP;
3088
3089 if (autoneg) {
3090 ecmd->advertising |= ADVERTISED_Autoneg;
3091
3092 if (auto_duplex) {
3093 half_duplex = 1;
3094 full_duplex = 1;
3095 } else {
3096 if (pcs & MV643XX_ETH_SET_FULL_DUPLEX_MODE)
3097 full_duplex = 1;
3098 else
3099 half_duplex = 1;
3100 }
3101
3102 if (auto_speed) {
3103 speed_10 = 1;
3104 speed_100 = 1;
3105 speed_1000 = 1;
3106 } else {
3107 if (pcs & MV643XX_ETH_SET_GMII_SPEED_TO_1000)
3108 speed_1000 = 1;
3109 else if (pcs & MV643XX_ETH_SET_MII_SPEED_TO_100)
3110 speed_100 = 1;
3111 else
3112 speed_10 = 1;
3113 }
3114
3115 if (speed_10 & half_duplex)
3116 ecmd->advertising |= ADVERTISED_10baseT_Half;
3117 if (speed_10 & full_duplex)
3118 ecmd->advertising |= ADVERTISED_10baseT_Full;
3119 if (speed_100 & half_duplex)
3120 ecmd->advertising |= ADVERTISED_100baseT_Half;
3121 if (speed_100 & full_duplex)
3122 ecmd->advertising |= ADVERTISED_100baseT_Full;
3123 if (speed_1000)
3124 ecmd->advertising |= ADVERTISED_1000baseT_Full;
3125 }
3126 }
3127
3128 ecmd->port = PORT_TP;
3129 ecmd->phy_address = ethernet_phy_get(port_num);
3130
3131 ecmd->transceiver = XCVR_EXTERNAL;
3132
3133 if (netif_carrier_ok(netdev)) {
3134 if (mode_10_bit)
3135 ecmd->speed = SPEED_10;
3136 else {
3137 if (psr & MV643XX_ETH_PORT_STATUS_GMII_1000)
3138 ecmd->speed = SPEED_1000;
3139 else if (psr & MV643XX_ETH_PORT_STATUS_MII_100)
3140 ecmd->speed = SPEED_100;
3141 else
3142 ecmd->speed = SPEED_10;
3143 }
3144
3145 if (psr & MV643XX_ETH_PORT_STATUS_FULL_DUPLEX)
3146 ecmd->duplex = DUPLEX_FULL;
3147 else
3148 ecmd->duplex = DUPLEX_HALF;
3149 } else {
3150 ecmd->speed = -1;
3151 ecmd->duplex = -1;
3152 }
3153
3154 ecmd->autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3155 return 0;
3156}
3157
3158static void
3159mv643xx_get_drvinfo(struct net_device *netdev,
3160 struct ethtool_drvinfo *drvinfo)
3161{
3162 strncpy(drvinfo->driver, mv643xx_driver_name, 32);
3163 strncpy(drvinfo->version, mv643xx_driver_version, 32);
3164 strncpy(drvinfo->fw_version, "N/A", 32);
3165 strncpy(drvinfo->bus_info, "mv643xx", 32);
3166 drvinfo->n_stats = MV643XX_STATS_LEN;
3167}
3168
3169static int
3170mv643xx_get_stats_count(struct net_device *netdev)
3171{
3172 return MV643XX_STATS_LEN;
3173}
3174
3175static void
3176mv643xx_get_ethtool_stats(struct net_device *netdev,
3177 struct ethtool_stats *stats, uint64_t *data)
3178{
3179 struct mv643xx_private *mp = netdev->priv;
3180 int i;
3181
3182 eth_update_mib_counters(mp);
3183
3184 for(i = 0; i < MV643XX_STATS_LEN; i++) {
3185 char *p = (char *)mp+mv643xx_gstrings_stats[i].stat_offset;
3186 data[i] = (mv643xx_gstrings_stats[i].sizeof_stat ==
3187 sizeof(uint64_t)) ? *(uint64_t *)p : *(uint32_t *)p;
3188 }
3189}
3190
3191static void
3192mv643xx_get_strings(struct net_device *netdev, uint32_t stringset, uint8_t *data)
3193{
3194 int i;
3195
3196 switch(stringset) {
3197 case ETH_SS_STATS:
3198 for (i=0; i < MV643XX_STATS_LEN; i++) {
3199 memcpy(data + i * ETH_GSTRING_LEN,
3200 mv643xx_gstrings_stats[i].stat_string,
3201 ETH_GSTRING_LEN);
3202 }
3203 break;
3204 }
3205}
3206
3207static struct ethtool_ops mv643xx_ethtool_ops = {
3208 .get_settings = mv643xx_get_settings,
3209 .get_drvinfo = mv643xx_get_drvinfo,
3210 .get_link = ethtool_op_get_link,
3211 .get_sg = ethtool_op_get_sg,
3212 .set_sg = ethtool_op_set_sg,
3213 .get_strings = mv643xx_get_strings,
3214 .get_stats_count = mv643xx_get_stats_count,
3215 .get_ethtool_stats = mv643xx_get_ethtool_stats,
3216};
3217
3218/************* End ethtool support *************************/
Linux 6.x block layer and io_uring tree(s)