Commit | Line | Data |
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1da177e4 | 1 | /* |
9c1bbdfe | 2 | * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports |
1da177e4 LT |
3 | * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com> |
4 | * | |
5 | * Based on the 64360 driver from: | |
4547fa61 LB |
6 | * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il> |
7 | * Rabeeh Khoury <rabeeh@marvell.com> | |
1da177e4 LT |
8 | * |
9 | * Copyright (C) 2003 PMC-Sierra, Inc., | |
3bb8a18a | 10 | * written by Manish Lachwani |
1da177e4 LT |
11 | * |
12 | * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org> | |
13 | * | |
c8aaea25 | 14 | * Copyright (C) 2004-2006 MontaVista Software, Inc. |
1da177e4 LT |
15 | * Dale Farnsworth <dale@farnsworth.org> |
16 | * | |
17 | * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com> | |
18 | * <sjhill@realitydiluted.com> | |
19 | * | |
4547fa61 LB |
20 | * Copyright (C) 2007-2008 Marvell Semiconductor |
21 | * Lennert Buytenhek <buytenh@marvell.com> | |
22 | * | |
1da177e4 LT |
23 | * This program is free software; you can redistribute it and/or |
24 | * modify it under the terms of the GNU General Public License | |
25 | * as published by the Free Software Foundation; either version 2 | |
26 | * of the License, or (at your option) any later version. | |
27 | * | |
28 | * This program is distributed in the hope that it will be useful, | |
29 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
30 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
31 | * GNU General Public License for more details. | |
32 | * | |
33 | * You should have received a copy of the GNU General Public License | |
34 | * along with this program; if not, write to the Free Software | |
35 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
36 | */ | |
a779d38c | 37 | |
1da177e4 LT |
38 | #include <linux/init.h> |
39 | #include <linux/dma-mapping.h> | |
b6298c22 | 40 | #include <linux/in.h> |
1da177e4 LT |
41 | #include <linux/tcp.h> |
42 | #include <linux/udp.h> | |
43 | #include <linux/etherdevice.h> | |
1da177e4 LT |
44 | #include <linux/delay.h> |
45 | #include <linux/ethtool.h> | |
d052d1be | 46 | #include <linux/platform_device.h> |
fbd6a754 LB |
47 | #include <linux/module.h> |
48 | #include <linux/kernel.h> | |
49 | #include <linux/spinlock.h> | |
50 | #include <linux/workqueue.h> | |
51 | #include <linux/mii.h> | |
fbd6a754 | 52 | #include <linux/mv643xx_eth.h> |
1da177e4 LT |
53 | #include <asm/io.h> |
54 | #include <asm/types.h> | |
1da177e4 | 55 | #include <asm/system.h> |
fbd6a754 | 56 | |
c9df406f LB |
57 | static char mv643xx_driver_name[] = "mv643xx_eth"; |
58 | static char mv643xx_driver_version[] = "1.0"; | |
59 | ||
fbd6a754 LB |
60 | #define MV643XX_CHECKSUM_OFFLOAD_TX |
61 | #define MV643XX_NAPI | |
62 | #define MV643XX_TX_FAST_REFILL | |
63 | #undef MV643XX_COAL | |
64 | ||
fbd6a754 LB |
65 | #define MV643XX_TX_COAL 100 |
66 | #ifdef MV643XX_COAL | |
67 | #define MV643XX_RX_COAL 100 | |
68 | #endif | |
69 | ||
70 | #ifdef MV643XX_CHECKSUM_OFFLOAD_TX | |
71 | #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1) | |
72 | #else | |
73 | #define MAX_DESCS_PER_SKB 1 | |
74 | #endif | |
75 | ||
76 | #define ETH_VLAN_HLEN 4 | |
77 | #define ETH_FCS_LEN 4 | |
78 | #define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */ | |
79 | #define ETH_WRAPPER_LEN (ETH_HW_IP_ALIGN + ETH_HLEN + \ | |
80 | ETH_VLAN_HLEN + ETH_FCS_LEN) | |
81 | #define ETH_RX_SKB_SIZE (dev->mtu + ETH_WRAPPER_LEN + \ | |
82 | dma_get_cache_alignment()) | |
83 | ||
84 | /* | |
85 | * Registers shared between all ports. | |
86 | */ | |
87 | #define PHY_ADDR_REG 0x0000 | |
88 | #define SMI_REG 0x0004 | |
f2ce825d LB |
89 | #define WINDOW_BASE(i) (0x0200 + ((i) << 3)) |
90 | #define WINDOW_SIZE(i) (0x0204 + ((i) << 3)) | |
91 | #define WINDOW_REMAP_HIGH(i) (0x0280 + ((i) << 2)) | |
92 | #define WINDOW_BAR_ENABLE 0x0290 | |
93 | #define WINDOW_PROTECT(i) (0x0294 + ((i) << 4)) | |
fbd6a754 LB |
94 | |
95 | /* | |
96 | * Per-port registers. | |
97 | */ | |
98 | #define PORT_CONFIG_REG(p) (0x0400 + ((p) << 10)) | |
99 | #define PORT_CONFIG_EXTEND_REG(p) (0x0404 + ((p) << 10)) | |
100 | #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10)) | |
101 | #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10)) | |
102 | #define SDMA_CONFIG_REG(p) (0x041c + ((p) << 10)) | |
103 | #define PORT_SERIAL_CONTROL_REG(p) (0x043c + ((p) << 10)) | |
104 | #define PORT_STATUS_REG(p) (0x0444 + ((p) << 10)) | |
105 | #define TRANSMIT_QUEUE_COMMAND_REG(p) (0x0448 + ((p) << 10)) | |
106 | #define MAXIMUM_TRANSMIT_UNIT(p) (0x0458 + ((p) << 10)) | |
107 | #define INTERRUPT_CAUSE_REG(p) (0x0460 + ((p) << 10)) | |
108 | #define INTERRUPT_CAUSE_EXTEND_REG(p) (0x0464 + ((p) << 10)) | |
109 | #define INTERRUPT_MASK_REG(p) (0x0468 + ((p) << 10)) | |
110 | #define INTERRUPT_EXTEND_MASK_REG(p) (0x046c + ((p) << 10)) | |
111 | #define TX_FIFO_URGENT_THRESHOLD_REG(p) (0x0474 + ((p) << 10)) | |
112 | #define RX_CURRENT_QUEUE_DESC_PTR_0(p) (0x060c + ((p) << 10)) | |
113 | #define RECEIVE_QUEUE_COMMAND_REG(p) (0x0680 + ((p) << 10)) | |
114 | #define TX_CURRENT_QUEUE_DESC_PTR_0(p) (0x06c0 + ((p) << 10)) | |
115 | #define MIB_COUNTERS_BASE(p) (0x1000 + ((p) << 7)) | |
116 | #define DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(p) (0x1400 + ((p) << 10)) | |
117 | #define DA_FILTER_OTHER_MULTICAST_TABLE_BASE(p) (0x1500 + ((p) << 10)) | |
118 | #define DA_FILTER_UNICAST_TABLE_BASE(p) (0x1600 + ((p) << 10)) | |
119 | ||
120 | /* These macros describe Ethernet Port configuration reg (Px_cR) bits */ | |
121 | #define UNICAST_NORMAL_MODE (0 << 0) | |
122 | #define UNICAST_PROMISCUOUS_MODE (1 << 0) | |
123 | #define DEFAULT_RX_QUEUE(queue) ((queue) << 1) | |
124 | #define DEFAULT_RX_ARP_QUEUE(queue) ((queue) << 4) | |
125 | #define RECEIVE_BC_IF_NOT_IP_OR_ARP (0 << 7) | |
126 | #define REJECT_BC_IF_NOT_IP_OR_ARP (1 << 7) | |
127 | #define RECEIVE_BC_IF_IP (0 << 8) | |
128 | #define REJECT_BC_IF_IP (1 << 8) | |
129 | #define RECEIVE_BC_IF_ARP (0 << 9) | |
130 | #define REJECT_BC_IF_ARP (1 << 9) | |
131 | #define TX_AM_NO_UPDATE_ERROR_SUMMARY (1 << 12) | |
132 | #define CAPTURE_TCP_FRAMES_DIS (0 << 14) | |
133 | #define CAPTURE_TCP_FRAMES_EN (1 << 14) | |
134 | #define CAPTURE_UDP_FRAMES_DIS (0 << 15) | |
135 | #define CAPTURE_UDP_FRAMES_EN (1 << 15) | |
136 | #define DEFAULT_RX_TCP_QUEUE(queue) ((queue) << 16) | |
137 | #define DEFAULT_RX_UDP_QUEUE(queue) ((queue) << 19) | |
138 | #define DEFAULT_RX_BPDU_QUEUE(queue) ((queue) << 22) | |
139 | ||
140 | #define PORT_CONFIG_DEFAULT_VALUE \ | |
141 | UNICAST_NORMAL_MODE | \ | |
142 | DEFAULT_RX_QUEUE(0) | \ | |
143 | DEFAULT_RX_ARP_QUEUE(0) | \ | |
144 | RECEIVE_BC_IF_NOT_IP_OR_ARP | \ | |
145 | RECEIVE_BC_IF_IP | \ | |
146 | RECEIVE_BC_IF_ARP | \ | |
147 | CAPTURE_TCP_FRAMES_DIS | \ | |
148 | CAPTURE_UDP_FRAMES_DIS | \ | |
149 | DEFAULT_RX_TCP_QUEUE(0) | \ | |
150 | DEFAULT_RX_UDP_QUEUE(0) | \ | |
151 | DEFAULT_RX_BPDU_QUEUE(0) | |
152 | ||
153 | /* These macros describe Ethernet Port configuration extend reg (Px_cXR) bits*/ | |
154 | #define CLASSIFY_EN (1 << 0) | |
155 | #define SPAN_BPDU_PACKETS_AS_NORMAL (0 << 1) | |
156 | #define SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 (1 << 1) | |
157 | #define PARTITION_DISABLE (0 << 2) | |
158 | #define PARTITION_ENABLE (1 << 2) | |
159 | ||
160 | #define PORT_CONFIG_EXTEND_DEFAULT_VALUE \ | |
161 | SPAN_BPDU_PACKETS_AS_NORMAL | \ | |
162 | PARTITION_DISABLE | |
163 | ||
164 | /* These macros describe Ethernet Port Sdma configuration reg (SDCR) bits */ | |
165 | #define RIFB (1 << 0) | |
166 | #define RX_BURST_SIZE_1_64BIT (0 << 1) | |
167 | #define RX_BURST_SIZE_2_64BIT (1 << 1) | |
168 | #define RX_BURST_SIZE_4_64BIT (2 << 1) | |
169 | #define RX_BURST_SIZE_8_64BIT (3 << 1) | |
170 | #define RX_BURST_SIZE_16_64BIT (4 << 1) | |
171 | #define BLM_RX_NO_SWAP (1 << 4) | |
172 | #define BLM_RX_BYTE_SWAP (0 << 4) | |
173 | #define BLM_TX_NO_SWAP (1 << 5) | |
174 | #define BLM_TX_BYTE_SWAP (0 << 5) | |
175 | #define DESCRIPTORS_BYTE_SWAP (1 << 6) | |
176 | #define DESCRIPTORS_NO_SWAP (0 << 6) | |
177 | #define IPG_INT_RX(value) (((value) & 0x3fff) << 8) | |
178 | #define TX_BURST_SIZE_1_64BIT (0 << 22) | |
179 | #define TX_BURST_SIZE_2_64BIT (1 << 22) | |
180 | #define TX_BURST_SIZE_4_64BIT (2 << 22) | |
181 | #define TX_BURST_SIZE_8_64BIT (3 << 22) | |
182 | #define TX_BURST_SIZE_16_64BIT (4 << 22) | |
183 | ||
184 | #if defined(__BIG_ENDIAN) | |
185 | #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ | |
186 | RX_BURST_SIZE_4_64BIT | \ | |
187 | IPG_INT_RX(0) | \ | |
188 | TX_BURST_SIZE_4_64BIT | |
189 | #elif defined(__LITTLE_ENDIAN) | |
190 | #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ | |
191 | RX_BURST_SIZE_4_64BIT | \ | |
192 | BLM_RX_NO_SWAP | \ | |
193 | BLM_TX_NO_SWAP | \ | |
194 | IPG_INT_RX(0) | \ | |
195 | TX_BURST_SIZE_4_64BIT | |
196 | #else | |
197 | #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined | |
198 | #endif | |
199 | ||
200 | /* These macros describe Ethernet Port serial control reg (PSCR) bits */ | |
201 | #define SERIAL_PORT_DISABLE (0 << 0) | |
202 | #define SERIAL_PORT_ENABLE (1 << 0) | |
203 | #define DO_NOT_FORCE_LINK_PASS (0 << 1) | |
204 | #define FORCE_LINK_PASS (1 << 1) | |
205 | #define ENABLE_AUTO_NEG_FOR_DUPLX (0 << 2) | |
206 | #define DISABLE_AUTO_NEG_FOR_DUPLX (1 << 2) | |
207 | #define ENABLE_AUTO_NEG_FOR_FLOW_CTRL (0 << 3) | |
208 | #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3) | |
209 | #define ADV_NO_FLOW_CTRL (0 << 4) | |
210 | #define ADV_SYMMETRIC_FLOW_CTRL (1 << 4) | |
211 | #define FORCE_FC_MODE_NO_PAUSE_DIS_TX (0 << 5) | |
212 | #define FORCE_FC_MODE_TX_PAUSE_DIS (1 << 5) | |
213 | #define FORCE_BP_MODE_NO_JAM (0 << 7) | |
214 | #define FORCE_BP_MODE_JAM_TX (1 << 7) | |
215 | #define FORCE_BP_MODE_JAM_TX_ON_RX_ERR (2 << 7) | |
216 | #define SERIAL_PORT_CONTROL_RESERVED (1 << 9) | |
217 | #define FORCE_LINK_FAIL (0 << 10) | |
218 | #define DO_NOT_FORCE_LINK_FAIL (1 << 10) | |
219 | #define RETRANSMIT_16_ATTEMPTS (0 << 11) | |
220 | #define RETRANSMIT_FOREVER (1 << 11) | |
221 | #define ENABLE_AUTO_NEG_SPEED_GMII (0 << 13) | |
222 | #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13) | |
223 | #define DTE_ADV_0 (0 << 14) | |
224 | #define DTE_ADV_1 (1 << 14) | |
225 | #define DISABLE_AUTO_NEG_BYPASS (0 << 15) | |
226 | #define ENABLE_AUTO_NEG_BYPASS (1 << 15) | |
227 | #define AUTO_NEG_NO_CHANGE (0 << 16) | |
228 | #define RESTART_AUTO_NEG (1 << 16) | |
229 | #define MAX_RX_PACKET_1518BYTE (0 << 17) | |
230 | #define MAX_RX_PACKET_1522BYTE (1 << 17) | |
231 | #define MAX_RX_PACKET_1552BYTE (2 << 17) | |
232 | #define MAX_RX_PACKET_9022BYTE (3 << 17) | |
233 | #define MAX_RX_PACKET_9192BYTE (4 << 17) | |
234 | #define MAX_RX_PACKET_9700BYTE (5 << 17) | |
235 | #define MAX_RX_PACKET_MASK (7 << 17) | |
236 | #define CLR_EXT_LOOPBACK (0 << 20) | |
237 | #define SET_EXT_LOOPBACK (1 << 20) | |
238 | #define SET_HALF_DUPLEX_MODE (0 << 21) | |
239 | #define SET_FULL_DUPLEX_MODE (1 << 21) | |
240 | #define DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (0 << 22) | |
241 | #define ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1 << 22) | |
242 | #define SET_GMII_SPEED_TO_10_100 (0 << 23) | |
243 | #define SET_GMII_SPEED_TO_1000 (1 << 23) | |
244 | #define SET_MII_SPEED_TO_10 (0 << 24) | |
245 | #define SET_MII_SPEED_TO_100 (1 << 24) | |
246 | ||
247 | #define PORT_SERIAL_CONTROL_DEFAULT_VALUE \ | |
248 | DO_NOT_FORCE_LINK_PASS | \ | |
249 | ENABLE_AUTO_NEG_FOR_DUPLX | \ | |
250 | DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \ | |
251 | ADV_SYMMETRIC_FLOW_CTRL | \ | |
252 | FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ | |
253 | FORCE_BP_MODE_NO_JAM | \ | |
254 | (1 << 9) /* reserved */ | \ | |
255 | DO_NOT_FORCE_LINK_FAIL | \ | |
256 | RETRANSMIT_16_ATTEMPTS | \ | |
257 | ENABLE_AUTO_NEG_SPEED_GMII | \ | |
258 | DTE_ADV_0 | \ | |
259 | DISABLE_AUTO_NEG_BYPASS | \ | |
260 | AUTO_NEG_NO_CHANGE | \ | |
261 | MAX_RX_PACKET_9700BYTE | \ | |
262 | CLR_EXT_LOOPBACK | \ | |
263 | SET_FULL_DUPLEX_MODE | \ | |
264 | ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX | |
265 | ||
266 | /* These macros describe Ethernet Serial Status reg (PSR) bits */ | |
267 | #define PORT_STATUS_MODE_10_BIT (1 << 0) | |
268 | #define PORT_STATUS_LINK_UP (1 << 1) | |
269 | #define PORT_STATUS_FULL_DUPLEX (1 << 2) | |
270 | #define PORT_STATUS_FLOW_CONTROL (1 << 3) | |
271 | #define PORT_STATUS_GMII_1000 (1 << 4) | |
272 | #define PORT_STATUS_MII_100 (1 << 5) | |
273 | /* PSR bit 6 is undocumented */ | |
274 | #define PORT_STATUS_TX_IN_PROGRESS (1 << 7) | |
275 | #define PORT_STATUS_AUTONEG_BYPASSED (1 << 8) | |
276 | #define PORT_STATUS_PARTITION (1 << 9) | |
277 | #define PORT_STATUS_TX_FIFO_EMPTY (1 << 10) | |
278 | /* PSR bits 11-31 are reserved */ | |
279 | ||
280 | #define PORT_DEFAULT_TRANSMIT_QUEUE_SIZE 800 | |
281 | #define PORT_DEFAULT_RECEIVE_QUEUE_SIZE 400 | |
282 | ||
283 | #define DESC_SIZE 64 | |
284 | ||
285 | #define ETH_RX_QUEUES_ENABLED (1 << 0) /* use only Q0 for receive */ | |
286 | #define ETH_TX_QUEUES_ENABLED (1 << 0) /* use only Q0 for transmit */ | |
287 | ||
288 | #define ETH_INT_CAUSE_RX_DONE (ETH_RX_QUEUES_ENABLED << 2) | |
289 | #define ETH_INT_CAUSE_RX_ERROR (ETH_RX_QUEUES_ENABLED << 9) | |
290 | #define ETH_INT_CAUSE_RX (ETH_INT_CAUSE_RX_DONE | ETH_INT_CAUSE_RX_ERROR) | |
291 | #define ETH_INT_CAUSE_EXT 0x00000002 | |
292 | #define ETH_INT_UNMASK_ALL (ETH_INT_CAUSE_RX | ETH_INT_CAUSE_EXT) | |
293 | ||
294 | #define ETH_INT_CAUSE_TX_DONE (ETH_TX_QUEUES_ENABLED << 0) | |
295 | #define ETH_INT_CAUSE_TX_ERROR (ETH_TX_QUEUES_ENABLED << 8) | |
296 | #define ETH_INT_CAUSE_TX (ETH_INT_CAUSE_TX_DONE | ETH_INT_CAUSE_TX_ERROR) | |
297 | #define ETH_INT_CAUSE_PHY 0x00010000 | |
298 | #define ETH_INT_CAUSE_STATE 0x00100000 | |
299 | #define ETH_INT_UNMASK_ALL_EXT (ETH_INT_CAUSE_TX | ETH_INT_CAUSE_PHY | \ | |
300 | ETH_INT_CAUSE_STATE) | |
301 | ||
302 | #define ETH_INT_MASK_ALL 0x00000000 | |
303 | #define ETH_INT_MASK_ALL_EXT 0x00000000 | |
304 | ||
305 | #define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */ | |
306 | #define PHY_WAIT_MICRO_SECONDS 10 | |
307 | ||
308 | /* Buffer offset from buffer pointer */ | |
309 | #define RX_BUF_OFFSET 0x2 | |
310 | ||
311 | /* Gigabit Ethernet Unit Global Registers */ | |
312 | ||
313 | /* MIB Counters register definitions */ | |
314 | #define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0 | |
315 | #define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4 | |
316 | #define ETH_MIB_BAD_OCTETS_RECEIVED 0x8 | |
317 | #define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc | |
318 | #define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10 | |
319 | #define ETH_MIB_BAD_FRAMES_RECEIVED 0x14 | |
320 | #define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18 | |
321 | #define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c | |
322 | #define ETH_MIB_FRAMES_64_OCTETS 0x20 | |
323 | #define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24 | |
324 | #define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28 | |
325 | #define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c | |
326 | #define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30 | |
327 | #define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34 | |
328 | #define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38 | |
329 | #define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c | |
330 | #define ETH_MIB_GOOD_FRAMES_SENT 0x40 | |
331 | #define ETH_MIB_EXCESSIVE_COLLISION 0x44 | |
332 | #define ETH_MIB_MULTICAST_FRAMES_SENT 0x48 | |
333 | #define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c | |
334 | #define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50 | |
335 | #define ETH_MIB_FC_SENT 0x54 | |
336 | #define ETH_MIB_GOOD_FC_RECEIVED 0x58 | |
337 | #define ETH_MIB_BAD_FC_RECEIVED 0x5c | |
338 | #define ETH_MIB_UNDERSIZE_RECEIVED 0x60 | |
339 | #define ETH_MIB_FRAGMENTS_RECEIVED 0x64 | |
340 | #define ETH_MIB_OVERSIZE_RECEIVED 0x68 | |
341 | #define ETH_MIB_JABBER_RECEIVED 0x6c | |
342 | #define ETH_MIB_MAC_RECEIVE_ERROR 0x70 | |
343 | #define ETH_MIB_BAD_CRC_EVENT 0x74 | |
344 | #define ETH_MIB_COLLISION 0x78 | |
345 | #define ETH_MIB_LATE_COLLISION 0x7c | |
346 | ||
347 | /* Port serial status reg (PSR) */ | |
348 | #define ETH_INTERFACE_PCM 0x00000001 | |
349 | #define ETH_LINK_IS_UP 0x00000002 | |
350 | #define ETH_PORT_AT_FULL_DUPLEX 0x00000004 | |
351 | #define ETH_RX_FLOW_CTRL_ENABLED 0x00000008 | |
352 | #define ETH_GMII_SPEED_1000 0x00000010 | |
353 | #define ETH_MII_SPEED_100 0x00000020 | |
354 | #define ETH_TX_IN_PROGRESS 0x00000080 | |
355 | #define ETH_BYPASS_ACTIVE 0x00000100 | |
356 | #define ETH_PORT_AT_PARTITION_STATE 0x00000200 | |
357 | #define ETH_PORT_TX_FIFO_EMPTY 0x00000400 | |
358 | ||
359 | /* SMI reg */ | |
360 | #define ETH_SMI_BUSY 0x10000000 /* 0 - Write, 1 - Read */ | |
361 | #define ETH_SMI_READ_VALID 0x08000000 /* 0 - Write, 1 - Read */ | |
362 | #define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read */ | |
363 | #define ETH_SMI_OPCODE_READ 0x04000000 /* Operation is in progress */ | |
364 | ||
365 | /* Interrupt Cause Register Bit Definitions */ | |
366 | ||
367 | /* SDMA command status fields macros */ | |
368 | ||
369 | /* Tx & Rx descriptors status */ | |
370 | #define ETH_ERROR_SUMMARY 0x00000001 | |
371 | ||
372 | /* Tx & Rx descriptors command */ | |
373 | #define ETH_BUFFER_OWNED_BY_DMA 0x80000000 | |
374 | ||
375 | /* Tx descriptors status */ | |
376 | #define ETH_LC_ERROR 0 | |
377 | #define ETH_UR_ERROR 0x00000002 | |
378 | #define ETH_RL_ERROR 0x00000004 | |
379 | #define ETH_LLC_SNAP_FORMAT 0x00000200 | |
380 | ||
381 | /* Rx descriptors status */ | |
382 | #define ETH_OVERRUN_ERROR 0x00000002 | |
383 | #define ETH_MAX_FRAME_LENGTH_ERROR 0x00000004 | |
384 | #define ETH_RESOURCE_ERROR 0x00000006 | |
385 | #define ETH_VLAN_TAGGED 0x00080000 | |
386 | #define ETH_BPDU_FRAME 0x00100000 | |
387 | #define ETH_UDP_FRAME_OVER_IP_V_4 0x00200000 | |
388 | #define ETH_OTHER_FRAME_TYPE 0x00400000 | |
389 | #define ETH_LAYER_2_IS_ETH_V_2 0x00800000 | |
390 | #define ETH_FRAME_TYPE_IP_V_4 0x01000000 | |
391 | #define ETH_FRAME_HEADER_OK 0x02000000 | |
392 | #define ETH_RX_LAST_DESC 0x04000000 | |
393 | #define ETH_RX_FIRST_DESC 0x08000000 | |
394 | #define ETH_UNKNOWN_DESTINATION_ADDR 0x10000000 | |
395 | #define ETH_RX_ENABLE_INTERRUPT 0x20000000 | |
396 | #define ETH_LAYER_4_CHECKSUM_OK 0x40000000 | |
397 | ||
398 | /* Rx descriptors byte count */ | |
399 | #define ETH_FRAME_FRAGMENTED 0x00000004 | |
400 | ||
401 | /* Tx descriptors command */ | |
402 | #define ETH_LAYER_4_CHECKSUM_FIRST_DESC 0x00000400 | |
403 | #define ETH_FRAME_SET_TO_VLAN 0x00008000 | |
404 | #define ETH_UDP_FRAME 0x00010000 | |
405 | #define ETH_GEN_TCP_UDP_CHECKSUM 0x00020000 | |
406 | #define ETH_GEN_IP_V_4_CHECKSUM 0x00040000 | |
407 | #define ETH_ZERO_PADDING 0x00080000 | |
408 | #define ETH_TX_LAST_DESC 0x00100000 | |
409 | #define ETH_TX_FIRST_DESC 0x00200000 | |
410 | #define ETH_GEN_CRC 0x00400000 | |
411 | #define ETH_TX_ENABLE_INTERRUPT 0x00800000 | |
412 | #define ETH_AUTO_MODE 0x40000000 | |
413 | ||
414 | #define ETH_TX_IHL_SHIFT 11 | |
415 | ||
416 | /* typedefs */ | |
417 | ||
418 | typedef enum _eth_func_ret_status { | |
419 | ETH_OK, /* Returned as expected. */ | |
420 | ETH_ERROR, /* Fundamental error. */ | |
421 | ETH_RETRY, /* Could not process request. Try later.*/ | |
422 | ETH_END_OF_JOB, /* Ring has nothing to process. */ | |
423 | ETH_QUEUE_FULL, /* Ring resource error. */ | |
424 | ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */ | |
425 | } ETH_FUNC_RET_STATUS; | |
426 | ||
fbd6a754 LB |
427 | /* These are for big-endian machines. Little endian needs different |
428 | * definitions. | |
429 | */ | |
430 | #if defined(__BIG_ENDIAN) | |
431 | struct eth_rx_desc { | |
432 | u16 byte_cnt; /* Descriptor buffer byte count */ | |
433 | u16 buf_size; /* Buffer size */ | |
434 | u32 cmd_sts; /* Descriptor command status */ | |
435 | u32 next_desc_ptr; /* Next descriptor pointer */ | |
436 | u32 buf_ptr; /* Descriptor buffer pointer */ | |
437 | }; | |
438 | ||
439 | struct eth_tx_desc { | |
440 | u16 byte_cnt; /* buffer byte count */ | |
441 | u16 l4i_chk; /* CPU provided TCP checksum */ | |
442 | u32 cmd_sts; /* Command/status field */ | |
443 | u32 next_desc_ptr; /* Pointer to next descriptor */ | |
444 | u32 buf_ptr; /* pointer to buffer for this descriptor*/ | |
445 | }; | |
446 | #elif defined(__LITTLE_ENDIAN) | |
447 | struct eth_rx_desc { | |
448 | u32 cmd_sts; /* Descriptor command status */ | |
449 | u16 buf_size; /* Buffer size */ | |
450 | u16 byte_cnt; /* Descriptor buffer byte count */ | |
451 | u32 buf_ptr; /* Descriptor buffer pointer */ | |
452 | u32 next_desc_ptr; /* Next descriptor pointer */ | |
453 | }; | |
454 | ||
455 | struct eth_tx_desc { | |
456 | u32 cmd_sts; /* Command/status field */ | |
457 | u16 l4i_chk; /* CPU provided TCP checksum */ | |
458 | u16 byte_cnt; /* buffer byte count */ | |
459 | u32 buf_ptr; /* pointer to buffer for this descriptor*/ | |
460 | u32 next_desc_ptr; /* Pointer to next descriptor */ | |
461 | }; | |
462 | #else | |
463 | #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined | |
464 | #endif | |
465 | ||
466 | /* Unified struct for Rx and Tx operations. The user is not required to */ | |
467 | /* be familier with neither Tx nor Rx descriptors. */ | |
468 | struct pkt_info { | |
469 | unsigned short byte_cnt; /* Descriptor buffer byte count */ | |
470 | unsigned short l4i_chk; /* Tx CPU provided TCP Checksum */ | |
471 | unsigned int cmd_sts; /* Descriptor command status */ | |
472 | dma_addr_t buf_ptr; /* Descriptor buffer pointer */ | |
473 | struct sk_buff *return_info; /* User resource return information */ | |
474 | }; | |
475 | ||
c9df406f LB |
476 | |
477 | /* global *******************************************************************/ | |
478 | struct mv643xx_shared_private { | |
479 | void __iomem *eth_base; | |
480 | ||
481 | /* used to protect SMI_REG, which is shared across ports */ | |
482 | spinlock_t phy_lock; | |
483 | ||
484 | u32 win_protect; | |
485 | ||
486 | unsigned int t_clk; | |
487 | }; | |
488 | ||
489 | ||
490 | /* per-port *****************************************************************/ | |
fbd6a754 LB |
491 | struct mv643xx_mib_counters { |
492 | u64 good_octets_received; | |
493 | u32 bad_octets_received; | |
494 | u32 internal_mac_transmit_err; | |
495 | u32 good_frames_received; | |
496 | u32 bad_frames_received; | |
497 | u32 broadcast_frames_received; | |
498 | u32 multicast_frames_received; | |
499 | u32 frames_64_octets; | |
500 | u32 frames_65_to_127_octets; | |
501 | u32 frames_128_to_255_octets; | |
502 | u32 frames_256_to_511_octets; | |
503 | u32 frames_512_to_1023_octets; | |
504 | u32 frames_1024_to_max_octets; | |
505 | u64 good_octets_sent; | |
506 | u32 good_frames_sent; | |
507 | u32 excessive_collision; | |
508 | u32 multicast_frames_sent; | |
509 | u32 broadcast_frames_sent; | |
510 | u32 unrec_mac_control_received; | |
511 | u32 fc_sent; | |
512 | u32 good_fc_received; | |
513 | u32 bad_fc_received; | |
514 | u32 undersize_received; | |
515 | u32 fragments_received; | |
516 | u32 oversize_received; | |
517 | u32 jabber_received; | |
518 | u32 mac_receive_error; | |
519 | u32 bad_crc_event; | |
520 | u32 collision; | |
521 | u32 late_collision; | |
522 | }; | |
523 | ||
524 | struct mv643xx_private { | |
fa3959f4 | 525 | struct mv643xx_shared_private *shared; |
fbd6a754 LB |
526 | int port_num; /* User Ethernet port number */ |
527 | ||
ce4e2e45 LB |
528 | struct mv643xx_shared_private *shared_smi; |
529 | ||
fbd6a754 LB |
530 | u32 rx_sram_addr; /* Base address of rx sram area */ |
531 | u32 rx_sram_size; /* Size of rx sram area */ | |
532 | u32 tx_sram_addr; /* Base address of tx sram area */ | |
533 | u32 tx_sram_size; /* Size of tx sram area */ | |
534 | ||
535 | int rx_resource_err; /* Rx ring resource error flag */ | |
536 | ||
537 | /* Tx/Rx rings managment indexes fields. For driver use */ | |
538 | ||
539 | /* Next available and first returning Rx resource */ | |
540 | int rx_curr_desc_q, rx_used_desc_q; | |
541 | ||
542 | /* Next available and first returning Tx resource */ | |
543 | int tx_curr_desc_q, tx_used_desc_q; | |
544 | ||
545 | #ifdef MV643XX_TX_FAST_REFILL | |
546 | u32 tx_clean_threshold; | |
547 | #endif | |
548 | ||
549 | struct eth_rx_desc *p_rx_desc_area; | |
550 | dma_addr_t rx_desc_dma; | |
551 | int rx_desc_area_size; | |
552 | struct sk_buff **rx_skb; | |
553 | ||
554 | struct eth_tx_desc *p_tx_desc_area; | |
555 | dma_addr_t tx_desc_dma; | |
556 | int tx_desc_area_size; | |
557 | struct sk_buff **tx_skb; | |
558 | ||
559 | struct work_struct tx_timeout_task; | |
560 | ||
561 | struct net_device *dev; | |
562 | struct napi_struct napi; | |
563 | struct net_device_stats stats; | |
564 | struct mv643xx_mib_counters mib_counters; | |
565 | spinlock_t lock; | |
566 | /* Size of Tx Ring per queue */ | |
567 | int tx_ring_size; | |
568 | /* Number of tx descriptors in use */ | |
569 | int tx_desc_count; | |
570 | /* Size of Rx Ring per queue */ | |
571 | int rx_ring_size; | |
572 | /* Number of rx descriptors in use */ | |
573 | int rx_desc_count; | |
574 | ||
575 | /* | |
576 | * Used in case RX Ring is empty, which can be caused when | |
577 | * system does not have resources (skb's) | |
578 | */ | |
579 | struct timer_list timeout; | |
580 | ||
581 | u32 rx_int_coal; | |
582 | u32 tx_int_coal; | |
583 | struct mii_if_info mii; | |
584 | }; | |
1da177e4 | 585 | |
fbd6a754 | 586 | |
c9df406f LB |
587 | /* port register accessors **************************************************/ |
588 | static inline u32 rdl(struct mv643xx_private *mp, int offset) | |
589 | { | |
590 | return readl(mp->shared->eth_base + offset); | |
591 | } | |
fbd6a754 | 592 | |
c9df406f LB |
593 | static inline void wrl(struct mv643xx_private *mp, int offset, u32 data) |
594 | { | |
595 | writel(data, mp->shared->eth_base + offset); | |
596 | } | |
fbd6a754 | 597 | |
fbd6a754 | 598 | |
c9df406f LB |
599 | /* rxq/txq helper functions *************************************************/ |
600 | static void mv643xx_eth_port_enable_rx(struct mv643xx_private *mp, | |
601 | unsigned int queues) | |
602 | { | |
603 | wrl(mp, RECEIVE_QUEUE_COMMAND_REG(mp->port_num), queues); | |
604 | } | |
fbd6a754 | 605 | |
c9df406f LB |
606 | static unsigned int mv643xx_eth_port_disable_rx(struct mv643xx_private *mp) |
607 | { | |
608 | unsigned int port_num = mp->port_num; | |
609 | u32 queues; | |
fbd6a754 | 610 | |
c9df406f LB |
611 | /* Stop Rx port activity. Check port Rx activity. */ |
612 | queues = rdl(mp, RECEIVE_QUEUE_COMMAND_REG(port_num)) & 0xFF; | |
613 | if (queues) { | |
614 | /* Issue stop command for active queues only */ | |
615 | wrl(mp, RECEIVE_QUEUE_COMMAND_REG(port_num), (queues << 8)); | |
1da177e4 | 616 | |
c9df406f LB |
617 | /* Wait for all Rx activity to terminate. */ |
618 | /* Check port cause register that all Rx queues are stopped */ | |
619 | while (rdl(mp, RECEIVE_QUEUE_COMMAND_REG(port_num)) & 0xFF) | |
620 | udelay(PHY_WAIT_MICRO_SECONDS); | |
621 | } | |
1da177e4 | 622 | |
c9df406f LB |
623 | return queues; |
624 | } | |
625 | ||
626 | static void mv643xx_eth_port_enable_tx(struct mv643xx_private *mp, | |
627 | unsigned int queues) | |
1da177e4 | 628 | { |
c9df406f | 629 | wrl(mp, TRANSMIT_QUEUE_COMMAND_REG(mp->port_num), queues); |
1da177e4 LT |
630 | } |
631 | ||
c9df406f | 632 | static unsigned int mv643xx_eth_port_disable_tx(struct mv643xx_private *mp) |
1da177e4 | 633 | { |
c9df406f LB |
634 | unsigned int port_num = mp->port_num; |
635 | u32 queues; | |
636 | ||
637 | /* Stop Tx port activity. Check port Tx activity. */ | |
638 | queues = rdl(mp, TRANSMIT_QUEUE_COMMAND_REG(port_num)) & 0xFF; | |
639 | if (queues) { | |
640 | /* Issue stop command for active queues only */ | |
641 | wrl(mp, TRANSMIT_QUEUE_COMMAND_REG(port_num), (queues << 8)); | |
642 | ||
643 | /* Wait for all Tx activity to terminate. */ | |
644 | /* Check port cause register that all Tx queues are stopped */ | |
645 | while (rdl(mp, TRANSMIT_QUEUE_COMMAND_REG(port_num)) & 0xFF) | |
646 | udelay(PHY_WAIT_MICRO_SECONDS); | |
647 | ||
648 | /* Wait for Tx FIFO to empty */ | |
649 | while (rdl(mp, PORT_STATUS_REG(port_num)) & | |
650 | ETH_PORT_TX_FIFO_EMPTY) | |
651 | udelay(PHY_WAIT_MICRO_SECONDS); | |
652 | } | |
653 | ||
654 | return queues; | |
1da177e4 LT |
655 | } |
656 | ||
c9df406f LB |
657 | |
658 | /* rx ***********************************************************************/ | |
659 | static void mv643xx_eth_free_completed_tx_descs(struct net_device *dev); | |
660 | ||
1da177e4 | 661 | /* |
c9df406f | 662 | * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring. |
1da177e4 | 663 | * |
c9df406f LB |
664 | * DESCRIPTION: |
665 | * This routine returns a Rx buffer back to the Rx ring. It retrieves the | |
666 | * next 'used' descriptor and attached the returned buffer to it. | |
667 | * In case the Rx ring was in "resource error" condition, where there are | |
668 | * no available Rx resources, the function resets the resource error flag. | |
669 | * | |
670 | * INPUT: | |
671 | * struct mv643xx_private *mp Ethernet Port Control srtuct. | |
672 | * struct pkt_info *p_pkt_info Information on returned buffer. | |
673 | * | |
674 | * OUTPUT: | |
675 | * New available Rx resource in Rx descriptor ring. | |
676 | * | |
677 | * RETURN: | |
678 | * ETH_ERROR in case the routine can not access Rx desc ring. | |
679 | * ETH_OK otherwise. | |
1da177e4 | 680 | */ |
c9df406f LB |
681 | static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp, |
682 | struct pkt_info *p_pkt_info) | |
1da177e4 | 683 | { |
c9df406f LB |
684 | int used_rx_desc; /* Where to return Rx resource */ |
685 | volatile struct eth_rx_desc *p_used_rx_desc; | |
686 | unsigned long flags; | |
1da177e4 | 687 | |
c9df406f | 688 | spin_lock_irqsave(&mp->lock, flags); |
c0d0f2ca | 689 | |
c9df406f LB |
690 | /* Get 'used' Rx descriptor */ |
691 | used_rx_desc = mp->rx_used_desc_q; | |
692 | p_used_rx_desc = &mp->p_rx_desc_area[used_rx_desc]; | |
1da177e4 | 693 | |
c9df406f LB |
694 | p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr; |
695 | p_used_rx_desc->buf_size = p_pkt_info->byte_cnt; | |
696 | mp->rx_skb[used_rx_desc] = p_pkt_info->return_info; | |
697 | ||
698 | /* Flush the write pipe */ | |
699 | ||
700 | /* Return the descriptor to DMA ownership */ | |
701 | wmb(); | |
702 | p_used_rx_desc->cmd_sts = | |
703 | ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT; | |
704 | wmb(); | |
705 | ||
706 | /* Move the used descriptor pointer to the next descriptor */ | |
707 | mp->rx_used_desc_q = (used_rx_desc + 1) % mp->rx_ring_size; | |
708 | ||
709 | /* Any Rx return cancels the Rx resource error status */ | |
710 | mp->rx_resource_err = 0; | |
711 | ||
712 | spin_unlock_irqrestore(&mp->lock, flags); | |
713 | ||
714 | return ETH_OK; | |
1da177e4 LT |
715 | } |
716 | ||
717 | /* | |
f78fb474 | 718 | * mv643xx_eth_rx_refill_descs |
1da177e4 LT |
719 | * |
720 | * Fills / refills RX queue on a certain gigabit ethernet port | |
721 | * | |
722 | * Input : pointer to ethernet interface network device structure | |
723 | * Output : N/A | |
724 | */ | |
f78fb474 | 725 | static void mv643xx_eth_rx_refill_descs(struct net_device *dev) |
1da177e4 | 726 | { |
1da177e4 LT |
727 | struct mv643xx_private *mp = netdev_priv(dev); |
728 | struct pkt_info pkt_info; | |
729 | struct sk_buff *skb; | |
b44cd572 | 730 | int unaligned; |
1da177e4 | 731 | |
f78fb474 | 732 | while (mp->rx_desc_count < mp->rx_ring_size) { |
908b637f | 733 | skb = dev_alloc_skb(ETH_RX_SKB_SIZE + dma_get_cache_alignment()); |
1da177e4 LT |
734 | if (!skb) |
735 | break; | |
f98e36f1 | 736 | mp->rx_desc_count++; |
908b637f | 737 | unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1); |
b44cd572 | 738 | if (unaligned) |
908b637f | 739 | skb_reserve(skb, dma_get_cache_alignment() - unaligned); |
1da177e4 | 740 | pkt_info.cmd_sts = ETH_RX_ENABLE_INTERRUPT; |
7303fde8 DF |
741 | pkt_info.byte_cnt = ETH_RX_SKB_SIZE; |
742 | pkt_info.buf_ptr = dma_map_single(NULL, skb->data, | |
743 | ETH_RX_SKB_SIZE, DMA_FROM_DEVICE); | |
1da177e4 LT |
744 | pkt_info.return_info = skb; |
745 | if (eth_rx_return_buff(mp, &pkt_info) != ETH_OK) { | |
746 | printk(KERN_ERR | |
747 | "%s: Error allocating RX Ring\n", dev->name); | |
748 | break; | |
749 | } | |
7303fde8 | 750 | skb_reserve(skb, ETH_HW_IP_ALIGN); |
1da177e4 | 751 | } |
1da177e4 LT |
752 | /* |
753 | * If RX ring is empty of SKB, set a timer to try allocating | |
f78fb474 | 754 | * again at a later time. |
1da177e4 | 755 | */ |
f78fb474 | 756 | if (mp->rx_desc_count == 0) { |
1da177e4 | 757 | printk(KERN_INFO "%s: Rx ring is empty\n", dev->name); |
f78fb474 | 758 | mp->timeout.expires = jiffies + (HZ / 10); /* 100 mSec */ |
1da177e4 | 759 | add_timer(&mp->timeout); |
1da177e4 | 760 | } |
1da177e4 LT |
761 | } |
762 | ||
763 | /* | |
f78fb474 | 764 | * mv643xx_eth_rx_refill_descs_timer_wrapper |
1da177e4 LT |
765 | * |
766 | * Timer routine to wake up RX queue filling task. This function is | |
767 | * used only in case the RX queue is empty, and all alloc_skb has | |
768 | * failed (due to out of memory event). | |
769 | * | |
770 | * Input : pointer to ethernet interface network device structure | |
771 | * Output : N/A | |
772 | */ | |
f78fb474 | 773 | static inline void mv643xx_eth_rx_refill_descs_timer_wrapper(unsigned long data) |
1da177e4 | 774 | { |
f78fb474 | 775 | mv643xx_eth_rx_refill_descs((struct net_device *)data); |
1da177e4 LT |
776 | } |
777 | ||
778 | /* | |
c9df406f | 779 | * eth_port_receive - Get received information from Rx ring. |
1da177e4 | 780 | * |
c9df406f LB |
781 | * DESCRIPTION: |
782 | * This routine returns the received data to the caller. There is no | |
783 | * data copying during routine operation. All information is returned | |
784 | * using pointer to packet information struct passed from the caller. | |
785 | * If the routine exhausts Rx ring resources then the resource error flag | |
786 | * is set. | |
1da177e4 | 787 | * |
c9df406f LB |
788 | * INPUT: |
789 | * struct mv643xx_private *mp Ethernet Port Control srtuct. | |
790 | * struct pkt_info *p_pkt_info User packet buffer. | |
1da177e4 | 791 | * |
c9df406f LB |
792 | * OUTPUT: |
793 | * Rx ring current and used indexes are updated. | |
1da177e4 | 794 | * |
c9df406f LB |
795 | * RETURN: |
796 | * ETH_ERROR in case the routine can not access Rx desc ring. | |
797 | * ETH_QUEUE_FULL if Rx ring resources are exhausted. | |
798 | * ETH_END_OF_JOB if there is no received data. | |
799 | * ETH_OK otherwise. | |
1da177e4 | 800 | */ |
c9df406f LB |
801 | static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp, |
802 | struct pkt_info *p_pkt_info) | |
1da177e4 | 803 | { |
c9df406f LB |
804 | int rx_next_curr_desc, rx_curr_desc, rx_used_desc; |
805 | volatile struct eth_rx_desc *p_rx_desc; | |
806 | unsigned int command_status; | |
807 | unsigned long flags; | |
1da177e4 | 808 | |
c9df406f LB |
809 | /* Do not process Rx ring in case of Rx ring resource error */ |
810 | if (mp->rx_resource_err) | |
811 | return ETH_QUEUE_FULL; | |
16e03018 | 812 | |
c9df406f | 813 | spin_lock_irqsave(&mp->lock, flags); |
1da177e4 | 814 | |
c9df406f LB |
815 | /* Get the Rx Desc ring 'curr and 'used' indexes */ |
816 | rx_curr_desc = mp->rx_curr_desc_q; | |
817 | rx_used_desc = mp->rx_used_desc_q; | |
1da177e4 | 818 | |
c9df406f | 819 | p_rx_desc = &mp->p_rx_desc_area[rx_curr_desc]; |
1da177e4 | 820 | |
c9df406f LB |
821 | /* The following parameters are used to save readings from memory */ |
822 | command_status = p_rx_desc->cmd_sts; | |
823 | rmb(); | |
1da177e4 | 824 | |
c9df406f LB |
825 | /* Nothing to receive... */ |
826 | if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { | |
d344bff9 | 827 | spin_unlock_irqrestore(&mp->lock, flags); |
c9df406f LB |
828 | return ETH_END_OF_JOB; |
829 | } | |
d344bff9 | 830 | |
c9df406f LB |
831 | p_pkt_info->byte_cnt = (p_rx_desc->byte_cnt) - RX_BUF_OFFSET; |
832 | p_pkt_info->cmd_sts = command_status; | |
833 | p_pkt_info->buf_ptr = (p_rx_desc->buf_ptr) + RX_BUF_OFFSET; | |
834 | p_pkt_info->return_info = mp->rx_skb[rx_curr_desc]; | |
835 | p_pkt_info->l4i_chk = p_rx_desc->buf_size; | |
ff561eef | 836 | |
c9df406f LB |
837 | /* |
838 | * Clean the return info field to indicate that the | |
839 | * packet has been moved to the upper layers | |
840 | */ | |
841 | mp->rx_skb[rx_curr_desc] = NULL; | |
1da177e4 | 842 | |
c9df406f LB |
843 | /* Update current index in data structure */ |
844 | rx_next_curr_desc = (rx_curr_desc + 1) % mp->rx_ring_size; | |
845 | mp->rx_curr_desc_q = rx_next_curr_desc; | |
1da177e4 | 846 | |
c9df406f LB |
847 | /* Rx descriptors exhausted. Set the Rx ring resource error flag */ |
848 | if (rx_next_curr_desc == rx_used_desc) | |
849 | mp->rx_resource_err = 1; | |
ff561eef | 850 | |
c9df406f | 851 | spin_unlock_irqrestore(&mp->lock, flags); |
ff561eef | 852 | |
c9df406f | 853 | return ETH_OK; |
ff561eef DF |
854 | } |
855 | ||
1da177e4 LT |
856 | /* |
857 | * mv643xx_eth_receive | |
858 | * | |
859 | * This function is forward packets that are received from the port's | |
860 | * queues toward kernel core or FastRoute them to another interface. | |
861 | * | |
862 | * Input : dev - a pointer to the required interface | |
863 | * max - maximum number to receive (0 means unlimted) | |
864 | * | |
865 | * Output : number of served packets | |
866 | */ | |
1da177e4 | 867 | static int mv643xx_eth_receive_queue(struct net_device *dev, int budget) |
1da177e4 LT |
868 | { |
869 | struct mv643xx_private *mp = netdev_priv(dev); | |
09f75cd7 | 870 | struct net_device_stats *stats = &dev->stats; |
1da177e4 LT |
871 | unsigned int received_packets = 0; |
872 | struct sk_buff *skb; | |
873 | struct pkt_info pkt_info; | |
874 | ||
b1dd9ca1 | 875 | while (budget-- > 0 && eth_port_receive(mp, &pkt_info) == ETH_OK) { |
54caf44d | 876 | dma_unmap_single(NULL, pkt_info.buf_ptr, ETH_RX_SKB_SIZE, |
71d28725 | 877 | DMA_FROM_DEVICE); |
f98e36f1 | 878 | mp->rx_desc_count--; |
1da177e4 | 879 | received_packets++; |
b1dd9ca1 | 880 | |
468d09f8 DF |
881 | /* |
882 | * Update statistics. | |
883 | * Note byte count includes 4 byte CRC count | |
884 | */ | |
1da177e4 LT |
885 | stats->rx_packets++; |
886 | stats->rx_bytes += pkt_info.byte_cnt; | |
887 | skb = pkt_info.return_info; | |
888 | /* | |
889 | * In case received a packet without first / last bits on OR | |
890 | * the error summary bit is on, the packets needs to be dropeed. | |
891 | */ | |
892 | if (((pkt_info.cmd_sts | |
893 | & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) != | |
894 | (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) | |
895 | || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) { | |
896 | stats->rx_dropped++; | |
897 | if ((pkt_info.cmd_sts & (ETH_RX_FIRST_DESC | | |
898 | ETH_RX_LAST_DESC)) != | |
899 | (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) { | |
900 | if (net_ratelimit()) | |
901 | printk(KERN_ERR | |
902 | "%s: Received packet spread " | |
903 | "on multiple descriptors\n", | |
904 | dev->name); | |
905 | } | |
906 | if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) | |
907 | stats->rx_errors++; | |
908 | ||
909 | dev_kfree_skb_irq(skb); | |
910 | } else { | |
911 | /* | |
912 | * The -4 is for the CRC in the trailer of the | |
913 | * received packet | |
914 | */ | |
915 | skb_put(skb, pkt_info.byte_cnt - 4); | |
1da177e4 LT |
916 | |
917 | if (pkt_info.cmd_sts & ETH_LAYER_4_CHECKSUM_OK) { | |
918 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
919 | skb->csum = htons( | |
920 | (pkt_info.cmd_sts & 0x0007fff8) >> 3); | |
921 | } | |
922 | skb->protocol = eth_type_trans(skb, dev); | |
923 | #ifdef MV643XX_NAPI | |
924 | netif_receive_skb(skb); | |
925 | #else | |
926 | netif_rx(skb); | |
927 | #endif | |
928 | } | |
12ad74f8 | 929 | dev->last_rx = jiffies; |
1da177e4 | 930 | } |
f78fb474 | 931 | mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */ |
1da177e4 LT |
932 | |
933 | return received_packets; | |
934 | } | |
935 | ||
c9df406f LB |
936 | #ifdef MV643XX_NAPI |
937 | /* | |
938 | * mv643xx_poll | |
939 | * | |
940 | * This function is used in case of NAPI | |
941 | */ | |
942 | static int mv643xx_poll(struct napi_struct *napi, int budget) | |
d0412d96 | 943 | { |
c9df406f LB |
944 | struct mv643xx_private *mp = container_of(napi, struct mv643xx_private, napi); |
945 | struct net_device *dev = mp->dev; | |
946 | unsigned int port_num = mp->port_num; | |
947 | int work_done; | |
d0412d96 | 948 | |
c9df406f LB |
949 | #ifdef MV643XX_TX_FAST_REFILL |
950 | if (++mp->tx_clean_threshold > 5) { | |
951 | mv643xx_eth_free_completed_tx_descs(dev); | |
952 | mp->tx_clean_threshold = 0; | |
d0412d96 | 953 | } |
c9df406f | 954 | #endif |
d0412d96 | 955 | |
c9df406f LB |
956 | work_done = 0; |
957 | if ((rdl(mp, RX_CURRENT_QUEUE_DESC_PTR_0(port_num))) | |
958 | != (u32) mp->rx_used_desc_q) | |
959 | work_done = mv643xx_eth_receive_queue(dev, budget); | |
d0412d96 | 960 | |
c9df406f LB |
961 | if (work_done < budget) { |
962 | netif_rx_complete(dev, napi); | |
963 | wrl(mp, INTERRUPT_CAUSE_REG(port_num), 0); | |
964 | wrl(mp, INTERRUPT_CAUSE_EXTEND_REG(port_num), 0); | |
965 | wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL); | |
d0412d96 | 966 | } |
c9df406f LB |
967 | |
968 | return work_done; | |
d0412d96 | 969 | } |
c9df406f | 970 | #endif |
d0412d96 | 971 | |
c9df406f LB |
972 | |
973 | /* tx ***********************************************************************/ | |
974 | /** | |
975 | * has_tiny_unaligned_frags - check if skb has any small, unaligned fragments | |
1da177e4 | 976 | * |
c9df406f LB |
977 | * Hardware can't handle unaligned fragments smaller than 9 bytes. |
978 | * This helper function detects that case. | |
1da177e4 LT |
979 | */ |
980 | ||
c9df406f | 981 | static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb) |
1da177e4 | 982 | { |
c9df406f LB |
983 | unsigned int frag; |
984 | skb_frag_t *fragp; | |
1da177e4 | 985 | |
c9df406f LB |
986 | for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { |
987 | fragp = &skb_shinfo(skb)->frags[frag]; | |
988 | if (fragp->size <= 8 && fragp->page_offset & 0x7) | |
989 | return 1; | |
1da177e4 | 990 | } |
c9df406f LB |
991 | return 0; |
992 | } | |
7303fde8 | 993 | |
c9df406f LB |
994 | /** |
995 | * eth_alloc_tx_desc_index - return the index of the next available tx desc | |
996 | */ | |
997 | static int eth_alloc_tx_desc_index(struct mv643xx_private *mp) | |
998 | { | |
999 | int tx_desc_curr; | |
d0412d96 | 1000 | |
c9df406f | 1001 | BUG_ON(mp->tx_desc_count >= mp->tx_ring_size); |
1da177e4 | 1002 | |
c9df406f LB |
1003 | tx_desc_curr = mp->tx_curr_desc_q; |
1004 | mp->tx_curr_desc_q = (tx_desc_curr + 1) % mp->tx_ring_size; | |
e4d00fa9 | 1005 | |
c9df406f | 1006 | BUG_ON(mp->tx_curr_desc_q == mp->tx_used_desc_q); |
468d09f8 | 1007 | |
c9df406f LB |
1008 | return tx_desc_curr; |
1009 | } | |
468d09f8 | 1010 | |
c9df406f LB |
1011 | /** |
1012 | * eth_tx_fill_frag_descs - fill tx hw descriptors for an skb's fragments. | |
1013 | * | |
1014 | * Ensure the data for each fragment to be transmitted is mapped properly, | |
1015 | * then fill in descriptors in the tx hw queue. | |
1016 | */ | |
1017 | static void eth_tx_fill_frag_descs(struct mv643xx_private *mp, | |
1018 | struct sk_buff *skb) | |
1019 | { | |
1020 | int frag; | |
1021 | int tx_index; | |
1022 | struct eth_tx_desc *desc; | |
1da177e4 | 1023 | |
c9df406f LB |
1024 | for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { |
1025 | skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag]; | |
1026 | ||
1027 | tx_index = eth_alloc_tx_desc_index(mp); | |
1028 | desc = &mp->p_tx_desc_area[tx_index]; | |
1029 | ||
1030 | desc->cmd_sts = ETH_BUFFER_OWNED_BY_DMA; | |
1031 | /* Last Frag enables interrupt and frees the skb */ | |
1032 | if (frag == (skb_shinfo(skb)->nr_frags - 1)) { | |
1033 | desc->cmd_sts |= ETH_ZERO_PADDING | | |
1034 | ETH_TX_LAST_DESC | | |
1035 | ETH_TX_ENABLE_INTERRUPT; | |
1036 | mp->tx_skb[tx_index] = skb; | |
1037 | } else | |
1038 | mp->tx_skb[tx_index] = NULL; | |
1039 | ||
1040 | desc = &mp->p_tx_desc_area[tx_index]; | |
1041 | desc->l4i_chk = 0; | |
1042 | desc->byte_cnt = this_frag->size; | |
1043 | desc->buf_ptr = dma_map_page(NULL, this_frag->page, | |
1044 | this_frag->page_offset, | |
1045 | this_frag->size, | |
1046 | DMA_TO_DEVICE); | |
1047 | } | |
1da177e4 LT |
1048 | } |
1049 | ||
c9df406f LB |
1050 | static inline __be16 sum16_as_be(__sum16 sum) |
1051 | { | |
1052 | return (__force __be16)sum; | |
1053 | } | |
1da177e4 | 1054 | |
c9df406f LB |
1055 | /** |
1056 | * eth_tx_submit_descs_for_skb - submit data from an skb to the tx hw | |
1da177e4 | 1057 | * |
c9df406f LB |
1058 | * Ensure the data for an skb to be transmitted is mapped properly, |
1059 | * then fill in descriptors in the tx hw queue and start the hardware. | |
1da177e4 | 1060 | */ |
c9df406f LB |
1061 | static void eth_tx_submit_descs_for_skb(struct mv643xx_private *mp, |
1062 | struct sk_buff *skb) | |
1da177e4 | 1063 | { |
c9df406f LB |
1064 | int tx_index; |
1065 | struct eth_tx_desc *desc; | |
1066 | u32 cmd_sts; | |
1067 | int length; | |
1068 | int nr_frags = skb_shinfo(skb)->nr_frags; | |
1da177e4 | 1069 | |
c9df406f | 1070 | cmd_sts = ETH_TX_FIRST_DESC | ETH_GEN_CRC | ETH_BUFFER_OWNED_BY_DMA; |
1da177e4 | 1071 | |
c9df406f LB |
1072 | tx_index = eth_alloc_tx_desc_index(mp); |
1073 | desc = &mp->p_tx_desc_area[tx_index]; | |
1074 | ||
1075 | if (nr_frags) { | |
1076 | eth_tx_fill_frag_descs(mp, skb); | |
1077 | ||
1078 | length = skb_headlen(skb); | |
1079 | mp->tx_skb[tx_index] = NULL; | |
1080 | } else { | |
1081 | cmd_sts |= ETH_ZERO_PADDING | | |
1082 | ETH_TX_LAST_DESC | | |
1083 | ETH_TX_ENABLE_INTERRUPT; | |
1084 | length = skb->len; | |
1085 | mp->tx_skb[tx_index] = skb; | |
1086 | } | |
1087 | ||
1088 | desc->byte_cnt = length; | |
1089 | desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE); | |
1090 | ||
1091 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
1092 | BUG_ON(skb->protocol != htons(ETH_P_IP)); | |
1093 | ||
1094 | cmd_sts |= ETH_GEN_TCP_UDP_CHECKSUM | | |
1095 | ETH_GEN_IP_V_4_CHECKSUM | | |
1096 | ip_hdr(skb)->ihl << ETH_TX_IHL_SHIFT; | |
1097 | ||
1098 | switch (ip_hdr(skb)->protocol) { | |
1099 | case IPPROTO_UDP: | |
1100 | cmd_sts |= ETH_UDP_FRAME; | |
1101 | desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check)); | |
1102 | break; | |
1103 | case IPPROTO_TCP: | |
1104 | desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check)); | |
1105 | break; | |
1106 | default: | |
1107 | BUG(); | |
1108 | } | |
1109 | } else { | |
1110 | /* Errata BTS #50, IHL must be 5 if no HW checksum */ | |
1111 | cmd_sts |= 5 << ETH_TX_IHL_SHIFT; | |
1112 | desc->l4i_chk = 0; | |
1113 | } | |
1114 | ||
1115 | /* ensure all other descriptors are written before first cmd_sts */ | |
1116 | wmb(); | |
1117 | desc->cmd_sts = cmd_sts; | |
1118 | ||
1119 | /* ensure all descriptors are written before poking hardware */ | |
1120 | wmb(); | |
1121 | mv643xx_eth_port_enable_tx(mp, ETH_TX_QUEUES_ENABLED); | |
1122 | ||
1123 | mp->tx_desc_count += nr_frags + 1; | |
1da177e4 | 1124 | } |
1da177e4 | 1125 | |
c9df406f LB |
1126 | /** |
1127 | * mv643xx_eth_start_xmit - queue an skb to the hardware for transmission | |
1da177e4 LT |
1128 | * |
1129 | */ | |
c9df406f | 1130 | static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev) |
1da177e4 | 1131 | { |
c9df406f LB |
1132 | struct mv643xx_private *mp = netdev_priv(dev); |
1133 | struct net_device_stats *stats = &dev->stats; | |
1134 | unsigned long flags; | |
afdb57a2 | 1135 | |
c9df406f | 1136 | BUG_ON(netif_queue_stopped(dev)); |
afdb57a2 | 1137 | |
c9df406f LB |
1138 | if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) { |
1139 | stats->tx_dropped++; | |
1140 | printk(KERN_DEBUG "%s: failed to linearize tiny " | |
1141 | "unaligned fragment\n", dev->name); | |
1142 | return NETDEV_TX_BUSY; | |
1143 | } | |
1144 | ||
1145 | spin_lock_irqsave(&mp->lock, flags); | |
1146 | ||
1147 | if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB) { | |
1148 | printk(KERN_ERR "%s: transmit with queue full\n", dev->name); | |
1149 | netif_stop_queue(dev); | |
1150 | spin_unlock_irqrestore(&mp->lock, flags); | |
1151 | return NETDEV_TX_BUSY; | |
1152 | } | |
1153 | ||
1154 | eth_tx_submit_descs_for_skb(mp, skb); | |
1155 | stats->tx_bytes += skb->len; | |
1156 | stats->tx_packets++; | |
1157 | dev->trans_start = jiffies; | |
1158 | ||
1159 | if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB) | |
1160 | netif_stop_queue(dev); | |
1161 | ||
1162 | spin_unlock_irqrestore(&mp->lock, flags); | |
1163 | ||
1164 | return NETDEV_TX_OK; | |
1da177e4 LT |
1165 | } |
1166 | ||
c9df406f LB |
1167 | |
1168 | /* mii management interface *************************************************/ | |
1169 | static int ethernet_phy_get(struct mv643xx_private *mp); | |
1170 | ||
1da177e4 | 1171 | /* |
c9df406f | 1172 | * eth_port_read_smi_reg - Read PHY registers |
1da177e4 LT |
1173 | * |
1174 | * DESCRIPTION: | |
c9df406f LB |
1175 | * This routine utilize the SMI interface to interact with the PHY in |
1176 | * order to perform PHY register read. | |
1da177e4 LT |
1177 | * |
1178 | * INPUT: | |
c9df406f LB |
1179 | * struct mv643xx_private *mp Ethernet Port. |
1180 | * unsigned int phy_reg PHY register address offset. | |
1181 | * unsigned int *value Register value buffer. | |
1da177e4 LT |
1182 | * |
1183 | * OUTPUT: | |
c9df406f | 1184 | * Write the value of a specified PHY register into given buffer. |
1da177e4 LT |
1185 | * |
1186 | * RETURN: | |
c9df406f LB |
1187 | * false if the PHY is busy or read data is not in valid state. |
1188 | * true otherwise. | |
1189 | * | |
1da177e4 | 1190 | */ |
c9df406f LB |
1191 | static void eth_port_read_smi_reg(struct mv643xx_private *mp, |
1192 | unsigned int phy_reg, unsigned int *value) | |
1da177e4 | 1193 | { |
c9df406f LB |
1194 | void __iomem *smi_reg = mp->shared_smi->eth_base + SMI_REG; |
1195 | int phy_addr = ethernet_phy_get(mp); | |
1196 | unsigned long flags; | |
1da177e4 LT |
1197 | int i; |
1198 | ||
c9df406f LB |
1199 | /* the SMI register is a shared resource */ |
1200 | spin_lock_irqsave(&mp->shared_smi->phy_lock, flags); | |
1201 | ||
1202 | /* wait for the SMI register to become available */ | |
1203 | for (i = 0; readl(smi_reg) & ETH_SMI_BUSY; i++) { | |
1204 | if (i == PHY_WAIT_ITERATIONS) { | |
1205 | printk("%s: PHY busy timeout\n", mp->dev->name); | |
1206 | goto out; | |
1207 | } | |
1208 | udelay(PHY_WAIT_MICRO_SECONDS); | |
1da177e4 LT |
1209 | } |
1210 | ||
c9df406f LB |
1211 | writel((phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ, |
1212 | smi_reg); | |
1da177e4 | 1213 | |
c9df406f LB |
1214 | /* now wait for the data to be valid */ |
1215 | for (i = 0; !(readl(smi_reg) & ETH_SMI_READ_VALID); i++) { | |
1216 | if (i == PHY_WAIT_ITERATIONS) { | |
1217 | printk("%s: PHY read timeout\n", mp->dev->name); | |
1218 | goto out; | |
1219 | } | |
1220 | udelay(PHY_WAIT_MICRO_SECONDS); | |
1221 | } | |
1222 | ||
1223 | *value = readl(smi_reg) & 0xffff; | |
1224 | out: | |
1225 | spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags); | |
1da177e4 LT |
1226 | } |
1227 | ||
1228 | /* | |
c9df406f | 1229 | * eth_port_write_smi_reg - Write to PHY registers |
1da177e4 LT |
1230 | * |
1231 | * DESCRIPTION: | |
c9df406f LB |
1232 | * This routine utilize the SMI interface to interact with the PHY in |
1233 | * order to perform writes to PHY registers. | |
1da177e4 LT |
1234 | * |
1235 | * INPUT: | |
c9df406f LB |
1236 | * struct mv643xx_private *mp Ethernet Port. |
1237 | * unsigned int phy_reg PHY register address offset. | |
1238 | * unsigned int value Register value. | |
1da177e4 LT |
1239 | * |
1240 | * OUTPUT: | |
c9df406f | 1241 | * Write the given value to the specified PHY register. |
1da177e4 LT |
1242 | * |
1243 | * RETURN: | |
c9df406f LB |
1244 | * false if the PHY is busy. |
1245 | * true otherwise. | |
1246 | * | |
1da177e4 | 1247 | */ |
c9df406f LB |
1248 | static void eth_port_write_smi_reg(struct mv643xx_private *mp, |
1249 | unsigned int phy_reg, unsigned int value) | |
1da177e4 | 1250 | { |
c9df406f LB |
1251 | void __iomem *smi_reg = mp->shared_smi->eth_base + SMI_REG; |
1252 | int phy_addr = ethernet_phy_get(mp); | |
1253 | unsigned long flags; | |
1da177e4 LT |
1254 | int i; |
1255 | ||
c9df406f LB |
1256 | /* the SMI register is a shared resource */ |
1257 | spin_lock_irqsave(&mp->shared_smi->phy_lock, flags); | |
1258 | ||
1259 | /* wait for the SMI register to become available */ | |
1260 | for (i = 0; readl(smi_reg) & ETH_SMI_BUSY; i++) { | |
1261 | if (i == PHY_WAIT_ITERATIONS) { | |
1262 | printk("%s: PHY busy timeout\n", mp->dev->name); | |
1263 | goto out; | |
1264 | } | |
1265 | udelay(PHY_WAIT_MICRO_SECONDS); | |
1da177e4 LT |
1266 | } |
1267 | ||
c9df406f LB |
1268 | writel((phy_addr << 16) | (phy_reg << 21) | |
1269 | ETH_SMI_OPCODE_WRITE | (value & 0xffff), smi_reg); | |
1270 | out: | |
1271 | spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags); | |
1272 | } | |
1da177e4 | 1273 | |
c9df406f LB |
1274 | |
1275 | /* mib counters *************************************************************/ | |
1276 | /* | |
1277 | * eth_clear_mib_counters - Clear all MIB counters | |
1278 | * | |
1279 | * DESCRIPTION: | |
1280 | * This function clears all MIB counters of a specific ethernet port. | |
1281 | * A read from the MIB counter will reset the counter. | |
1282 | * | |
1283 | * INPUT: | |
1284 | * struct mv643xx_private *mp Ethernet Port. | |
1285 | * | |
1286 | * OUTPUT: | |
1287 | * After reading all MIB counters, the counters resets. | |
1288 | * | |
1289 | * RETURN: | |
1290 | * MIB counter value. | |
1291 | * | |
1292 | */ | |
1293 | static void eth_clear_mib_counters(struct mv643xx_private *mp) | |
1294 | { | |
1295 | unsigned int port_num = mp->port_num; | |
1296 | int i; | |
1297 | ||
1298 | /* Perform dummy reads from MIB counters */ | |
1299 | for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION; | |
1300 | i += 4) | |
1301 | rdl(mp, MIB_COUNTERS_BASE(port_num) + i); | |
1da177e4 LT |
1302 | } |
1303 | ||
c9df406f | 1304 | static inline u32 read_mib(struct mv643xx_private *mp, int offset) |
d0412d96 | 1305 | { |
c9df406f LB |
1306 | return rdl(mp, MIB_COUNTERS_BASE(mp->port_num) + offset); |
1307 | } | |
d0412d96 | 1308 | |
c9df406f LB |
1309 | static void eth_update_mib_counters(struct mv643xx_private *mp) |
1310 | { | |
1311 | struct mv643xx_mib_counters *p = &mp->mib_counters; | |
1312 | int offset; | |
d0412d96 | 1313 | |
c9df406f LB |
1314 | p->good_octets_received += |
1315 | read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW); | |
1316 | p->good_octets_received += | |
1317 | (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32; | |
1318 | ||
1319 | for (offset = ETH_MIB_BAD_OCTETS_RECEIVED; | |
1320 | offset <= ETH_MIB_FRAMES_1024_TO_MAX_OCTETS; | |
1321 | offset += 4) | |
1322 | *(u32 *)((char *)p + offset) += read_mib(mp, offset); | |
1323 | ||
1324 | p->good_octets_sent += read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_LOW); | |
1325 | p->good_octets_sent += | |
1326 | (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_HIGH) << 32; | |
1327 | ||
1328 | for (offset = ETH_MIB_GOOD_FRAMES_SENT; | |
1329 | offset <= ETH_MIB_LATE_COLLISION; | |
1330 | offset += 4) | |
1331 | *(u32 *)((char *)p + offset) += read_mib(mp, offset); | |
d0412d96 JC |
1332 | } |
1333 | ||
c9df406f LB |
1334 | |
1335 | /* ethtool ******************************************************************/ | |
1336 | struct mv643xx_stats { | |
1337 | char stat_string[ETH_GSTRING_LEN]; | |
1338 | int sizeof_stat; | |
1339 | int stat_offset; | |
1340 | }; | |
1341 | ||
1342 | #define MV643XX_STAT(m) FIELD_SIZEOF(struct mv643xx_private, m), \ | |
1343 | offsetof(struct mv643xx_private, m) | |
1344 | ||
1345 | static const struct mv643xx_stats mv643xx_gstrings_stats[] = { | |
1346 | { "rx_packets", MV643XX_STAT(stats.rx_packets) }, | |
1347 | { "tx_packets", MV643XX_STAT(stats.tx_packets) }, | |
1348 | { "rx_bytes", MV643XX_STAT(stats.rx_bytes) }, | |
1349 | { "tx_bytes", MV643XX_STAT(stats.tx_bytes) }, | |
1350 | { "rx_errors", MV643XX_STAT(stats.rx_errors) }, | |
1351 | { "tx_errors", MV643XX_STAT(stats.tx_errors) }, | |
1352 | { "rx_dropped", MV643XX_STAT(stats.rx_dropped) }, | |
1353 | { "tx_dropped", MV643XX_STAT(stats.tx_dropped) }, | |
1354 | { "good_octets_received", MV643XX_STAT(mib_counters.good_octets_received) }, | |
1355 | { "bad_octets_received", MV643XX_STAT(mib_counters.bad_octets_received) }, | |
1356 | { "internal_mac_transmit_err", MV643XX_STAT(mib_counters.internal_mac_transmit_err) }, | |
1357 | { "good_frames_received", MV643XX_STAT(mib_counters.good_frames_received) }, | |
1358 | { "bad_frames_received", MV643XX_STAT(mib_counters.bad_frames_received) }, | |
1359 | { "broadcast_frames_received", MV643XX_STAT(mib_counters.broadcast_frames_received) }, | |
1360 | { "multicast_frames_received", MV643XX_STAT(mib_counters.multicast_frames_received) }, | |
1361 | { "frames_64_octets", MV643XX_STAT(mib_counters.frames_64_octets) }, | |
1362 | { "frames_65_to_127_octets", MV643XX_STAT(mib_counters.frames_65_to_127_octets) }, | |
1363 | { "frames_128_to_255_octets", MV643XX_STAT(mib_counters.frames_128_to_255_octets) }, | |
1364 | { "frames_256_to_511_octets", MV643XX_STAT(mib_counters.frames_256_to_511_octets) }, | |
1365 | { "frames_512_to_1023_octets", MV643XX_STAT(mib_counters.frames_512_to_1023_octets) }, | |
1366 | { "frames_1024_to_max_octets", MV643XX_STAT(mib_counters.frames_1024_to_max_octets) }, | |
1367 | { "good_octets_sent", MV643XX_STAT(mib_counters.good_octets_sent) }, | |
1368 | { "good_frames_sent", MV643XX_STAT(mib_counters.good_frames_sent) }, | |
1369 | { "excessive_collision", MV643XX_STAT(mib_counters.excessive_collision) }, | |
1370 | { "multicast_frames_sent", MV643XX_STAT(mib_counters.multicast_frames_sent) }, | |
1371 | { "broadcast_frames_sent", MV643XX_STAT(mib_counters.broadcast_frames_sent) }, | |
1372 | { "unrec_mac_control_received", MV643XX_STAT(mib_counters.unrec_mac_control_received) }, | |
1373 | { "fc_sent", MV643XX_STAT(mib_counters.fc_sent) }, | |
1374 | { "good_fc_received", MV643XX_STAT(mib_counters.good_fc_received) }, | |
1375 | { "bad_fc_received", MV643XX_STAT(mib_counters.bad_fc_received) }, | |
1376 | { "undersize_received", MV643XX_STAT(mib_counters.undersize_received) }, | |
1377 | { "fragments_received", MV643XX_STAT(mib_counters.fragments_received) }, | |
1378 | { "oversize_received", MV643XX_STAT(mib_counters.oversize_received) }, | |
1379 | { "jabber_received", MV643XX_STAT(mib_counters.jabber_received) }, | |
1380 | { "mac_receive_error", MV643XX_STAT(mib_counters.mac_receive_error) }, | |
1381 | { "bad_crc_event", MV643XX_STAT(mib_counters.bad_crc_event) }, | |
1382 | { "collision", MV643XX_STAT(mib_counters.collision) }, | |
1383 | { "late_collision", MV643XX_STAT(mib_counters.late_collision) }, | |
1384 | }; | |
1385 | ||
1386 | #define MV643XX_STATS_LEN ARRAY_SIZE(mv643xx_gstrings_stats) | |
1387 | ||
d0412d96 JC |
1388 | static int mv643xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
1389 | { | |
1390 | struct mv643xx_private *mp = netdev_priv(dev); | |
1391 | int err; | |
1392 | ||
1393 | spin_lock_irq(&mp->lock); | |
1394 | err = mii_ethtool_gset(&mp->mii, cmd); | |
1395 | spin_unlock_irq(&mp->lock); | |
1396 | ||
1397 | /* The PHY may support 1000baseT_Half, but the mv643xx does not */ | |
1398 | cmd->supported &= ~SUPPORTED_1000baseT_Half; | |
1399 | cmd->advertising &= ~ADVERTISED_1000baseT_Half; | |
1400 | ||
1401 | return err; | |
1402 | } | |
1403 | ||
c9df406f | 1404 | static int mv643xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
1da177e4 LT |
1405 | { |
1406 | struct mv643xx_private *mp = netdev_priv(dev); | |
ab4384a6 DF |
1407 | int err; |
1408 | ||
c9df406f LB |
1409 | spin_lock_irq(&mp->lock); |
1410 | err = mii_ethtool_sset(&mp->mii, cmd); | |
1411 | spin_unlock_irq(&mp->lock); | |
85cf572c | 1412 | |
c9df406f LB |
1413 | return err; |
1414 | } | |
1da177e4 | 1415 | |
c9df406f LB |
1416 | static void mv643xx_get_drvinfo(struct net_device *netdev, |
1417 | struct ethtool_drvinfo *drvinfo) | |
1418 | { | |
1419 | strncpy(drvinfo->driver, mv643xx_driver_name, 32); | |
1420 | strncpy(drvinfo->version, mv643xx_driver_version, 32); | |
1421 | strncpy(drvinfo->fw_version, "N/A", 32); | |
1422 | strncpy(drvinfo->bus_info, "mv643xx", 32); | |
1423 | drvinfo->n_stats = MV643XX_STATS_LEN; | |
1424 | } | |
1da177e4 | 1425 | |
c9df406f LB |
1426 | static int mv643xx_eth_nway_restart(struct net_device *dev) |
1427 | { | |
1428 | struct mv643xx_private *mp = netdev_priv(dev); | |
1da177e4 | 1429 | |
c9df406f LB |
1430 | return mii_nway_restart(&mp->mii); |
1431 | } | |
1da177e4 | 1432 | |
c9df406f LB |
1433 | static u32 mv643xx_eth_get_link(struct net_device *dev) |
1434 | { | |
1435 | struct mv643xx_private *mp = netdev_priv(dev); | |
1da177e4 | 1436 | |
c9df406f LB |
1437 | return mii_link_ok(&mp->mii); |
1438 | } | |
1da177e4 | 1439 | |
c9df406f LB |
1440 | static void mv643xx_get_strings(struct net_device *netdev, uint32_t stringset, |
1441 | uint8_t *data) | |
1442 | { | |
1443 | int i; | |
1da177e4 | 1444 | |
c9df406f LB |
1445 | switch(stringset) { |
1446 | case ETH_SS_STATS: | |
1447 | for (i=0; i < MV643XX_STATS_LEN; i++) { | |
1448 | memcpy(data + i * ETH_GSTRING_LEN, | |
1449 | mv643xx_gstrings_stats[i].stat_string, | |
1450 | ETH_GSTRING_LEN); | |
1451 | } | |
1452 | break; | |
1453 | } | |
1454 | } | |
1da177e4 | 1455 | |
c9df406f LB |
1456 | static void mv643xx_get_ethtool_stats(struct net_device *netdev, |
1457 | struct ethtool_stats *stats, uint64_t *data) | |
1458 | { | |
1459 | struct mv643xx_private *mp = netdev->priv; | |
1460 | int i; | |
1da177e4 | 1461 | |
c9df406f | 1462 | eth_update_mib_counters(mp); |
1da177e4 | 1463 | |
c9df406f LB |
1464 | for (i = 0; i < MV643XX_STATS_LEN; i++) { |
1465 | char *p = (char *)mp+mv643xx_gstrings_stats[i].stat_offset; | |
1466 | data[i] = (mv643xx_gstrings_stats[i].sizeof_stat == | |
1467 | sizeof(uint64_t)) ? *(uint64_t *)p : *(uint32_t *)p; | |
1da177e4 | 1468 | } |
c9df406f | 1469 | } |
1da177e4 | 1470 | |
c9df406f LB |
1471 | static int mv643xx_get_sset_count(struct net_device *netdev, int sset) |
1472 | { | |
1473 | switch (sset) { | |
1474 | case ETH_SS_STATS: | |
1475 | return MV643XX_STATS_LEN; | |
1476 | default: | |
1477 | return -EOPNOTSUPP; | |
1478 | } | |
1479 | } | |
1da177e4 | 1480 | |
c9df406f LB |
1481 | static const struct ethtool_ops mv643xx_ethtool_ops = { |
1482 | .get_settings = mv643xx_get_settings, | |
1483 | .set_settings = mv643xx_set_settings, | |
1484 | .get_drvinfo = mv643xx_get_drvinfo, | |
1485 | .get_link = mv643xx_eth_get_link, | |
1486 | .set_sg = ethtool_op_set_sg, | |
1487 | .get_sset_count = mv643xx_get_sset_count, | |
1488 | .get_ethtool_stats = mv643xx_get_ethtool_stats, | |
1489 | .get_strings = mv643xx_get_strings, | |
1490 | .nway_reset = mv643xx_eth_nway_restart, | |
1491 | }; | |
1da177e4 | 1492 | |
bea3348e | 1493 | |
c9df406f LB |
1494 | /* address handling *********************************************************/ |
1495 | /* | |
1496 | * eth_port_uc_addr_get - Read the MAC address from the port's hw registers | |
1497 | */ | |
1498 | static void eth_port_uc_addr_get(struct mv643xx_private *mp, | |
1499 | unsigned char *p_addr) | |
1500 | { | |
1501 | unsigned int port_num = mp->port_num; | |
1502 | unsigned int mac_h; | |
1503 | unsigned int mac_l; | |
1da177e4 | 1504 | |
c9df406f LB |
1505 | mac_h = rdl(mp, MAC_ADDR_HIGH(port_num)); |
1506 | mac_l = rdl(mp, MAC_ADDR_LOW(port_num)); | |
1da177e4 | 1507 | |
c9df406f LB |
1508 | p_addr[0] = (mac_h >> 24) & 0xff; |
1509 | p_addr[1] = (mac_h >> 16) & 0xff; | |
1510 | p_addr[2] = (mac_h >> 8) & 0xff; | |
1511 | p_addr[3] = mac_h & 0xff; | |
1512 | p_addr[4] = (mac_l >> 8) & 0xff; | |
1513 | p_addr[5] = mac_l & 0xff; | |
1514 | } | |
1da177e4 | 1515 | |
c9df406f LB |
1516 | /* |
1517 | * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables | |
1518 | * | |
1519 | * DESCRIPTION: | |
1520 | * Go through all the DA filter tables (Unicast, Special Multicast & | |
1521 | * Other Multicast) and set each entry to 0. | |
1522 | * | |
1523 | * INPUT: | |
1524 | * struct mv643xx_private *mp Ethernet Port. | |
1525 | * | |
1526 | * OUTPUT: | |
1527 | * Multicast and Unicast packets are rejected. | |
1528 | * | |
1529 | * RETURN: | |
1530 | * None. | |
1531 | */ | |
1532 | static void eth_port_init_mac_tables(struct mv643xx_private *mp) | |
1533 | { | |
1534 | unsigned int port_num = mp->port_num; | |
1535 | int table_index; | |
1da177e4 | 1536 | |
c9df406f LB |
1537 | /* Clear DA filter unicast table (Ex_dFUT) */ |
1538 | for (table_index = 0; table_index <= 0xC; table_index += 4) | |
1539 | wrl(mp, DA_FILTER_UNICAST_TABLE_BASE(port_num) + | |
1540 | table_index, 0); | |
1da177e4 | 1541 | |
c9df406f LB |
1542 | for (table_index = 0; table_index <= 0xFC; table_index += 4) { |
1543 | /* Clear DA filter special multicast table (Ex_dFSMT) */ | |
1544 | wrl(mp, DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port_num) + | |
1545 | table_index, 0); | |
1546 | /* Clear DA filter other multicast table (Ex_dFOMT) */ | |
1547 | wrl(mp, DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port_num) + | |
1548 | table_index, 0); | |
1549 | } | |
1550 | } | |
d0412d96 | 1551 | |
c9df406f LB |
1552 | /* |
1553 | * The entries in each table are indexed by a hash of a packet's MAC | |
1554 | * address. One bit in each entry determines whether the packet is | |
1555 | * accepted. There are 4 entries (each 8 bits wide) in each register | |
1556 | * of the table. The bits in each entry are defined as follows: | |
1557 | * 0 Accept=1, Drop=0 | |
1558 | * 3-1 Queue (ETH_Q0=0) | |
1559 | * 7-4 Reserved = 0; | |
1560 | */ | |
1561 | static void eth_port_set_filter_table_entry(struct mv643xx_private *mp, | |
1562 | int table, unsigned char entry) | |
1563 | { | |
1564 | unsigned int table_reg; | |
1565 | unsigned int tbl_offset; | |
1566 | unsigned int reg_offset; | |
ab4384a6 | 1567 | |
c9df406f LB |
1568 | tbl_offset = (entry / 4) * 4; /* Register offset of DA table entry */ |
1569 | reg_offset = entry % 4; /* Entry offset within the register */ | |
ab4384a6 | 1570 | |
c9df406f LB |
1571 | /* Set "accepts frame bit" at specified table entry */ |
1572 | table_reg = rdl(mp, table + tbl_offset); | |
1573 | table_reg |= 0x01 << (8 * reg_offset); | |
1574 | wrl(mp, table + tbl_offset, table_reg); | |
1da177e4 LT |
1575 | } |
1576 | ||
c9df406f LB |
1577 | /* |
1578 | * eth_port_uc_addr_set - Write a MAC address into the port's hw registers | |
1579 | */ | |
1580 | static void eth_port_uc_addr_set(struct mv643xx_private *mp, | |
1581 | unsigned char *p_addr) | |
1da177e4 | 1582 | { |
c9df406f LB |
1583 | unsigned int port_num = mp->port_num; |
1584 | unsigned int mac_h; | |
1585 | unsigned int mac_l; | |
1586 | int table; | |
1da177e4 | 1587 | |
c9df406f LB |
1588 | mac_l = (p_addr[4] << 8) | (p_addr[5]); |
1589 | mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) | | |
1590 | (p_addr[3] << 0); | |
ff561eef | 1591 | |
c9df406f LB |
1592 | wrl(mp, MAC_ADDR_LOW(port_num), mac_l); |
1593 | wrl(mp, MAC_ADDR_HIGH(port_num), mac_h); | |
1da177e4 | 1594 | |
c9df406f LB |
1595 | /* Accept frames with this address */ |
1596 | table = DA_FILTER_UNICAST_TABLE_BASE(port_num); | |
1597 | eth_port_set_filter_table_entry(mp, table, p_addr[5] & 0x0f); | |
1da177e4 LT |
1598 | } |
1599 | ||
c9df406f LB |
1600 | /* |
1601 | * mv643xx_eth_update_mac_address | |
1602 | * | |
1603 | * Update the MAC address of the port in the address table | |
1604 | * | |
1605 | * Input : pointer to ethernet interface network device structure | |
1606 | * Output : N/A | |
1607 | */ | |
1608 | static void mv643xx_eth_update_mac_address(struct net_device *dev) | |
1da177e4 LT |
1609 | { |
1610 | struct mv643xx_private *mp = netdev_priv(dev); | |
1da177e4 | 1611 | |
c9df406f LB |
1612 | eth_port_init_mac_tables(mp); |
1613 | eth_port_uc_addr_set(mp, dev->dev_addr); | |
1614 | } | |
1da177e4 LT |
1615 | |
1616 | /* | |
c9df406f | 1617 | * mv643xx_eth_set_mac_address |
1da177e4 | 1618 | * |
c9df406f LB |
1619 | * Change the interface's mac address. |
1620 | * No special hardware thing should be done because interface is always | |
1621 | * put in promiscuous mode. | |
1622 | * | |
1623 | * Input : pointer to ethernet interface network device structure and | |
1624 | * a pointer to the designated entry to be added to the cache. | |
1625 | * Output : zero upon success, negative upon failure | |
1da177e4 | 1626 | */ |
c9df406f | 1627 | static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr) |
1da177e4 | 1628 | { |
c9df406f | 1629 | int i; |
1da177e4 | 1630 | |
c9df406f LB |
1631 | for (i = 0; i < 6; i++) |
1632 | /* +2 is for the offset of the HW addr type */ | |
1633 | dev->dev_addr[i] = ((unsigned char *)addr)[i + 2]; | |
1634 | mv643xx_eth_update_mac_address(dev); | |
1da177e4 LT |
1635 | return 0; |
1636 | } | |
1637 | ||
1da177e4 | 1638 | /* |
c9df406f | 1639 | * eth_port_mc_addr - Multicast address settings. |
1da177e4 | 1640 | * |
c9df406f LB |
1641 | * The MV device supports multicast using two tables: |
1642 | * 1) Special Multicast Table for MAC addresses of the form | |
1643 | * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_FF). | |
1644 | * The MAC DA[7:0] bits are used as a pointer to the Special Multicast | |
1645 | * Table entries in the DA-Filter table. | |
1646 | * 2) Other Multicast Table for multicast of another type. A CRC-8bit | |
1647 | * is used as an index to the Other Multicast Table entries in the | |
1648 | * DA-Filter table. This function calculates the CRC-8bit value. | |
1649 | * In either case, eth_port_set_filter_table_entry() is then called | |
1650 | * to set to set the actual table entry. | |
1da177e4 | 1651 | */ |
c9df406f | 1652 | static void eth_port_mc_addr(struct mv643xx_private *mp, unsigned char *p_addr) |
1da177e4 | 1653 | { |
1da177e4 | 1654 | unsigned int port_num = mp->port_num; |
c9df406f LB |
1655 | unsigned int mac_h; |
1656 | unsigned int mac_l; | |
1657 | unsigned char crc_result = 0; | |
1658 | int table; | |
1659 | int mac_array[48]; | |
1660 | int crc[8]; | |
1661 | int i; | |
1da177e4 | 1662 | |
c9df406f LB |
1663 | if ((p_addr[0] == 0x01) && (p_addr[1] == 0x00) && |
1664 | (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) { | |
1665 | table = DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port_num); | |
1666 | eth_port_set_filter_table_entry(mp, table, p_addr[5]); | |
1667 | return; | |
1da177e4 | 1668 | } |
1da177e4 | 1669 | |
c9df406f LB |
1670 | /* Calculate CRC-8 out of the given address */ |
1671 | mac_h = (p_addr[0] << 8) | (p_addr[1]); | |
1672 | mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) | | |
1673 | (p_addr[4] << 8) | (p_addr[5] << 0); | |
1da177e4 | 1674 | |
c9df406f LB |
1675 | for (i = 0; i < 32; i++) |
1676 | mac_array[i] = (mac_l >> i) & 0x1; | |
1677 | for (i = 32; i < 48; i++) | |
1678 | mac_array[i] = (mac_h >> (i - 32)) & 0x1; | |
1da177e4 | 1679 | |
c9df406f LB |
1680 | crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ mac_array[39] ^ |
1681 | mac_array[35] ^ mac_array[34] ^ mac_array[31] ^ mac_array[30] ^ | |
1682 | mac_array[28] ^ mac_array[23] ^ mac_array[21] ^ mac_array[19] ^ | |
1683 | mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ mac_array[12] ^ | |
1684 | mac_array[8] ^ mac_array[7] ^ mac_array[6] ^ mac_array[0]; | |
1da177e4 | 1685 | |
c9df406f LB |
1686 | crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^ |
1687 | mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ mac_array[34] ^ | |
1688 | mac_array[32] ^ mac_array[30] ^ mac_array[29] ^ mac_array[28] ^ | |
1689 | mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ mac_array[21] ^ | |
1690 | mac_array[20] ^ mac_array[18] ^ mac_array[17] ^ mac_array[16] ^ | |
1691 | mac_array[15] ^ mac_array[14] ^ mac_array[13] ^ mac_array[12] ^ | |
1692 | mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ mac_array[0]; | |
f7ea3337 | 1693 | |
c9df406f LB |
1694 | crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ mac_array[43] ^ |
1695 | mac_array[42] ^ mac_array[39] ^ mac_array[37] ^ mac_array[34] ^ | |
1696 | mac_array[33] ^ mac_array[29] ^ mac_array[28] ^ mac_array[25] ^ | |
1697 | mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ mac_array[15] ^ | |
1698 | mac_array[13] ^ mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ | |
1699 | mac_array[6] ^ mac_array[2] ^ mac_array[1] ^ mac_array[0]; | |
f7ea3337 | 1700 | |
c9df406f LB |
1701 | crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^ |
1702 | mac_array[40] ^ mac_array[38] ^ mac_array[35] ^ mac_array[34] ^ | |
1703 | mac_array[30] ^ mac_array[29] ^ mac_array[26] ^ mac_array[25] ^ | |
1704 | mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ | |
1705 | mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[7] ^ | |
1706 | mac_array[3] ^ mac_array[2] ^ mac_array[1]; | |
f7ea3337 | 1707 | |
c9df406f LB |
1708 | crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[41] ^ |
1709 | mac_array[39] ^ mac_array[36] ^ mac_array[35] ^ mac_array[31] ^ | |
1710 | mac_array[30] ^ mac_array[27] ^ mac_array[26] ^ mac_array[24] ^ | |
1711 | mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ mac_array[14] ^ | |
1712 | mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ mac_array[4] ^ | |
1713 | mac_array[3] ^ mac_array[2]; | |
c8aaea25 | 1714 | |
c9df406f LB |
1715 | crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ mac_array[42] ^ |
1716 | mac_array[40] ^ mac_array[37] ^ mac_array[36] ^ mac_array[32] ^ | |
1717 | mac_array[31] ^ mac_array[28] ^ mac_array[27] ^ mac_array[25] ^ | |
1718 | mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ mac_array[15] ^ | |
1719 | mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[5] ^ | |
1720 | mac_array[4] ^ mac_array[3]; | |
c8aaea25 | 1721 | |
c9df406f LB |
1722 | crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ mac_array[41] ^ |
1723 | mac_array[38] ^ mac_array[37] ^ mac_array[33] ^ mac_array[32] ^ | |
1724 | mac_array[29] ^ mac_array[28] ^ mac_array[26] ^ mac_array[21] ^ | |
1725 | mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ mac_array[14] ^ | |
1726 | mac_array[12] ^ mac_array[10] ^ mac_array[6] ^ mac_array[5] ^ | |
1727 | mac_array[4]; | |
c8aaea25 | 1728 | |
c9df406f LB |
1729 | crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ mac_array[39] ^ |
1730 | mac_array[38] ^ mac_array[34] ^ mac_array[33] ^ mac_array[30] ^ | |
1731 | mac_array[29] ^ mac_array[27] ^ mac_array[22] ^ mac_array[20] ^ | |
1732 | mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ mac_array[13] ^ | |
1733 | mac_array[11] ^ mac_array[7] ^ mac_array[6] ^ mac_array[5]; | |
c8aaea25 | 1734 | |
c9df406f LB |
1735 | for (i = 0; i < 8; i++) |
1736 | crc_result = crc_result | (crc[i] << i); | |
1737 | ||
1738 | table = DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port_num); | |
1739 | eth_port_set_filter_table_entry(mp, table, crc_result); | |
c8aaea25 DF |
1740 | } |
1741 | ||
c9df406f LB |
1742 | /* |
1743 | * Set the entire multicast list based on dev->mc_list. | |
1da177e4 | 1744 | */ |
c9df406f | 1745 | static void eth_port_set_multicast_list(struct net_device *dev) |
1da177e4 | 1746 | { |
1da177e4 | 1747 | |
c9df406f LB |
1748 | struct dev_mc_list *mc_list; |
1749 | int i; | |
1750 | int table_index; | |
1751 | struct mv643xx_private *mp = netdev_priv(dev); | |
1752 | unsigned int eth_port_num = mp->port_num; | |
c8aaea25 | 1753 | |
c9df406f LB |
1754 | /* If the device is in promiscuous mode or in all multicast mode, |
1755 | * we will fully populate both multicast tables with accept. | |
1756 | * This is guaranteed to yield a match on all multicast addresses... | |
1757 | */ | |
1758 | if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) { | |
1759 | for (table_index = 0; table_index <= 0xFC; table_index += 4) { | |
1760 | /* Set all entries in DA filter special multicast | |
1761 | * table (Ex_dFSMT) | |
1762 | * Set for ETH_Q0 for now | |
1763 | * Bits | |
1764 | * 0 Accept=1, Drop=0 | |
1765 | * 3-1 Queue ETH_Q0=0 | |
1766 | * 7-4 Reserved = 0; | |
1767 | */ | |
1768 | wrl(mp, DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101); | |
c8aaea25 | 1769 | |
c9df406f LB |
1770 | /* Set all entries in DA filter other multicast |
1771 | * table (Ex_dFOMT) | |
1772 | * Set for ETH_Q0 for now | |
1773 | * Bits | |
1774 | * 0 Accept=1, Drop=0 | |
1775 | * 3-1 Queue ETH_Q0=0 | |
1776 | * 7-4 Reserved = 0; | |
1777 | */ | |
1778 | wrl(mp, DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101); | |
1779 | } | |
1780 | return; | |
1781 | } | |
c8aaea25 | 1782 | |
c9df406f LB |
1783 | /* We will clear out multicast tables every time we get the list. |
1784 | * Then add the entire new list... | |
1785 | */ | |
1786 | for (table_index = 0; table_index <= 0xFC; table_index += 4) { | |
1787 | /* Clear DA filter special multicast table (Ex_dFSMT) */ | |
1788 | wrl(mp, DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE | |
1789 | (eth_port_num) + table_index, 0); | |
1790 | ||
1791 | /* Clear DA filter other multicast table (Ex_dFOMT) */ | |
1792 | wrl(mp, DA_FILTER_OTHER_MULTICAST_TABLE_BASE | |
1793 | (eth_port_num) + table_index, 0); | |
1da177e4 LT |
1794 | } |
1795 | ||
c9df406f LB |
1796 | /* Get pointer to net_device multicast list and add each one... */ |
1797 | for (i = 0, mc_list = dev->mc_list; | |
1798 | (i < 256) && (mc_list != NULL) && (i < dev->mc_count); | |
1799 | i++, mc_list = mc_list->next) | |
1800 | if (mc_list->dmi_addrlen == 6) | |
1801 | eth_port_mc_addr(mp, mc_list->dmi_addr); | |
324ff2c1 BB |
1802 | } |
1803 | ||
c9df406f LB |
1804 | /* |
1805 | * mv643xx_eth_set_rx_mode | |
c8aaea25 | 1806 | * |
c9df406f LB |
1807 | * Change from promiscuos to regular rx mode |
1808 | * | |
1809 | * Input : pointer to ethernet interface network device structure | |
1810 | * Output : N/A | |
c8aaea25 | 1811 | */ |
c9df406f | 1812 | static void mv643xx_eth_set_rx_mode(struct net_device *dev) |
c8aaea25 | 1813 | { |
c9df406f LB |
1814 | struct mv643xx_private *mp = netdev_priv(dev); |
1815 | u32 config_reg; | |
1da177e4 | 1816 | |
c9df406f LB |
1817 | config_reg = rdl(mp, PORT_CONFIG_REG(mp->port_num)); |
1818 | if (dev->flags & IFF_PROMISC) | |
1819 | config_reg |= (u32) UNICAST_PROMISCUOUS_MODE; | |
1820 | else | |
1821 | config_reg &= ~(u32) UNICAST_PROMISCUOUS_MODE; | |
1822 | wrl(mp, PORT_CONFIG_REG(mp->port_num), config_reg); | |
1da177e4 | 1823 | |
c9df406f LB |
1824 | eth_port_set_multicast_list(dev); |
1825 | } | |
c8aaea25 | 1826 | |
c8aaea25 | 1827 | |
c9df406f LB |
1828 | /* rx/tx queue initialisation ***********************************************/ |
1829 | /* | |
1830 | * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory. | |
1831 | * | |
1832 | * DESCRIPTION: | |
1833 | * This function prepares a Rx chained list of descriptors and packet | |
1834 | * buffers in a form of a ring. The routine must be called after port | |
1835 | * initialization routine and before port start routine. | |
1836 | * The Ethernet SDMA engine uses CPU bus addresses to access the various | |
1837 | * devices in the system (i.e. DRAM). This function uses the ethernet | |
1838 | * struct 'virtual to physical' routine (set by the user) to set the ring | |
1839 | * with physical addresses. | |
1840 | * | |
1841 | * INPUT: | |
1842 | * struct mv643xx_private *mp Ethernet Port Control srtuct. | |
1843 | * | |
1844 | * OUTPUT: | |
1845 | * The routine updates the Ethernet port control struct with information | |
1846 | * regarding the Rx descriptors and buffers. | |
1847 | * | |
1848 | * RETURN: | |
1849 | * None. | |
1850 | */ | |
1851 | static void ether_init_rx_desc_ring(struct mv643xx_private *mp) | |
1852 | { | |
1853 | volatile struct eth_rx_desc *p_rx_desc; | |
1854 | int rx_desc_num = mp->rx_ring_size; | |
1855 | int i; | |
1856 | ||
1857 | /* initialize the next_desc_ptr links in the Rx descriptors ring */ | |
1858 | p_rx_desc = (struct eth_rx_desc *)mp->p_rx_desc_area; | |
1859 | for (i = 0; i < rx_desc_num; i++) { | |
1860 | p_rx_desc[i].next_desc_ptr = mp->rx_desc_dma + | |
1861 | ((i + 1) % rx_desc_num) * sizeof(struct eth_rx_desc); | |
f7ea3337 PJ |
1862 | } |
1863 | ||
c9df406f LB |
1864 | /* Save Rx desc pointer to driver struct. */ |
1865 | mp->rx_curr_desc_q = 0; | |
1866 | mp->rx_used_desc_q = 0; | |
1da177e4 | 1867 | |
c9df406f LB |
1868 | mp->rx_desc_area_size = rx_desc_num * sizeof(struct eth_rx_desc); |
1869 | } | |
c8aaea25 | 1870 | |
c9df406f LB |
1871 | static void mv643xx_eth_free_rx_rings(struct net_device *dev) |
1872 | { | |
1873 | struct mv643xx_private *mp = netdev_priv(dev); | |
1874 | int curr; | |
c8aaea25 | 1875 | |
c9df406f LB |
1876 | /* Stop RX Queues */ |
1877 | mv643xx_eth_port_disable_rx(mp); | |
1878 | ||
1879 | /* Free preallocated skb's on RX rings */ | |
1880 | for (curr = 0; mp->rx_desc_count && curr < mp->rx_ring_size; curr++) { | |
1881 | if (mp->rx_skb[curr]) { | |
1882 | dev_kfree_skb(mp->rx_skb[curr]); | |
1883 | mp->rx_desc_count--; | |
1da177e4 | 1884 | } |
c8aaea25 | 1885 | } |
1da177e4 | 1886 | |
c9df406f LB |
1887 | if (mp->rx_desc_count) |
1888 | printk(KERN_ERR | |
1889 | "%s: Error in freeing Rx Ring. %d skb's still" | |
1890 | " stuck in RX Ring - ignoring them\n", dev->name, | |
1891 | mp->rx_desc_count); | |
1892 | /* Free RX ring */ | |
1893 | if (mp->rx_sram_size) | |
1894 | iounmap(mp->p_rx_desc_area); | |
1895 | else | |
1896 | dma_free_coherent(NULL, mp->rx_desc_area_size, | |
1897 | mp->p_rx_desc_area, mp->rx_desc_dma); | |
1898 | } | |
1da177e4 | 1899 | |
c9df406f LB |
1900 | /* |
1901 | * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory. | |
1902 | * | |
1903 | * DESCRIPTION: | |
1904 | * This function prepares a Tx chained list of descriptors and packet | |
1905 | * buffers in a form of a ring. The routine must be called after port | |
1906 | * initialization routine and before port start routine. | |
1907 | * The Ethernet SDMA engine uses CPU bus addresses to access the various | |
1908 | * devices in the system (i.e. DRAM). This function uses the ethernet | |
1909 | * struct 'virtual to physical' routine (set by the user) to set the ring | |
1910 | * with physical addresses. | |
1911 | * | |
1912 | * INPUT: | |
1913 | * struct mv643xx_private *mp Ethernet Port Control srtuct. | |
1914 | * | |
1915 | * OUTPUT: | |
1916 | * The routine updates the Ethernet port control struct with information | |
1917 | * regarding the Tx descriptors and buffers. | |
1918 | * | |
1919 | * RETURN: | |
1920 | * None. | |
1921 | */ | |
1922 | static void ether_init_tx_desc_ring(struct mv643xx_private *mp) | |
1923 | { | |
1924 | int tx_desc_num = mp->tx_ring_size; | |
1925 | struct eth_tx_desc *p_tx_desc; | |
1926 | int i; | |
1da177e4 | 1927 | |
c9df406f LB |
1928 | /* Initialize the next_desc_ptr links in the Tx descriptors ring */ |
1929 | p_tx_desc = (struct eth_tx_desc *)mp->p_tx_desc_area; | |
1930 | for (i = 0; i < tx_desc_num; i++) { | |
1931 | p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma + | |
1932 | ((i + 1) % tx_desc_num) * sizeof(struct eth_tx_desc); | |
1933 | } | |
1934 | ||
1935 | mp->tx_curr_desc_q = 0; | |
1936 | mp->tx_used_desc_q = 0; | |
1937 | ||
1938 | mp->tx_desc_area_size = tx_desc_num * sizeof(struct eth_tx_desc); | |
c8aaea25 | 1939 | } |
1da177e4 | 1940 | |
c8aaea25 | 1941 | /** |
c9df406f | 1942 | * mv643xx_eth_free_tx_descs - Free the tx desc data for completed descriptors |
c8aaea25 | 1943 | * |
c9df406f | 1944 | * If force is non-zero, frees uncompleted descriptors as well |
c8aaea25 | 1945 | */ |
c9df406f | 1946 | static int mv643xx_eth_free_tx_descs(struct net_device *dev, int force) |
c8aaea25 DF |
1947 | { |
1948 | struct mv643xx_private *mp = netdev_priv(dev); | |
c9df406f LB |
1949 | struct eth_tx_desc *desc; |
1950 | u32 cmd_sts; | |
1951 | struct sk_buff *skb; | |
c8aaea25 | 1952 | unsigned long flags; |
c9df406f LB |
1953 | int tx_index; |
1954 | dma_addr_t addr; | |
1955 | int count; | |
1956 | int released = 0; | |
1da177e4 | 1957 | |
c9df406f LB |
1958 | while (mp->tx_desc_count > 0) { |
1959 | spin_lock_irqsave(&mp->lock, flags); | |
94843566 | 1960 | |
c9df406f LB |
1961 | /* tx_desc_count might have changed before acquiring the lock */ |
1962 | if (mp->tx_desc_count <= 0) { | |
1963 | spin_unlock_irqrestore(&mp->lock, flags); | |
1964 | return released; | |
1965 | } | |
4d64e718 | 1966 | |
c9df406f LB |
1967 | tx_index = mp->tx_used_desc_q; |
1968 | desc = &mp->p_tx_desc_area[tx_index]; | |
1969 | cmd_sts = desc->cmd_sts; | |
4d64e718 | 1970 | |
c9df406f LB |
1971 | if (!force && (cmd_sts & ETH_BUFFER_OWNED_BY_DMA)) { |
1972 | spin_unlock_irqrestore(&mp->lock, flags); | |
1973 | return released; | |
1974 | } | |
1da177e4 | 1975 | |
c9df406f LB |
1976 | mp->tx_used_desc_q = (tx_index + 1) % mp->tx_ring_size; |
1977 | mp->tx_desc_count--; | |
1da177e4 | 1978 | |
c9df406f LB |
1979 | addr = desc->buf_ptr; |
1980 | count = desc->byte_cnt; | |
1981 | skb = mp->tx_skb[tx_index]; | |
1982 | if (skb) | |
1983 | mp->tx_skb[tx_index] = NULL; | |
c8aaea25 | 1984 | |
c9df406f LB |
1985 | if (cmd_sts & ETH_ERROR_SUMMARY) { |
1986 | printk("%s: Error in TX\n", dev->name); | |
1987 | dev->stats.tx_errors++; | |
1988 | } | |
1da177e4 | 1989 | |
c9df406f | 1990 | spin_unlock_irqrestore(&mp->lock, flags); |
1da177e4 | 1991 | |
c9df406f LB |
1992 | if (cmd_sts & ETH_TX_FIRST_DESC) |
1993 | dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE); | |
1994 | else | |
1995 | dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE); | |
c2e5b352 | 1996 | |
c9df406f LB |
1997 | if (skb) |
1998 | dev_kfree_skb_irq(skb); | |
63c9e549 | 1999 | |
c9df406f LB |
2000 | released = 1; |
2001 | } | |
c2e5b352 | 2002 | |
c9df406f | 2003 | return released; |
63c9e549 | 2004 | } |
63c9e549 | 2005 | |
c9df406f | 2006 | static void mv643xx_eth_free_completed_tx_descs(struct net_device *dev) |
d0412d96 JC |
2007 | { |
2008 | struct mv643xx_private *mp = netdev_priv(dev); | |
2009 | ||
c9df406f LB |
2010 | if (mv643xx_eth_free_tx_descs(dev, 0) && |
2011 | mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB) | |
2012 | netif_wake_queue(dev); | |
d0412d96 JC |
2013 | } |
2014 | ||
c9df406f | 2015 | static void mv643xx_eth_free_all_tx_descs(struct net_device *dev) |
1da177e4 | 2016 | { |
c9df406f LB |
2017 | mv643xx_eth_free_tx_descs(dev, 1); |
2018 | } | |
1da177e4 | 2019 | |
c9df406f LB |
2020 | static void mv643xx_eth_free_tx_rings(struct net_device *dev) |
2021 | { | |
2022 | struct mv643xx_private *mp = netdev_priv(dev); | |
84dd619e | 2023 | |
c9df406f LB |
2024 | /* Stop Tx Queues */ |
2025 | mv643xx_eth_port_disable_tx(mp); | |
fa3959f4 | 2026 | |
c9df406f LB |
2027 | /* Free outstanding skb's on TX ring */ |
2028 | mv643xx_eth_free_all_tx_descs(dev); | |
1da177e4 | 2029 | |
c9df406f | 2030 | BUG_ON(mp->tx_used_desc_q != mp->tx_curr_desc_q); |
1da177e4 | 2031 | |
c9df406f LB |
2032 | /* Free TX ring */ |
2033 | if (mp->tx_sram_size) | |
2034 | iounmap(mp->p_tx_desc_area); | |
2035 | else | |
2036 | dma_free_coherent(NULL, mp->tx_desc_area_size, | |
2037 | mp->p_tx_desc_area, mp->tx_desc_dma); | |
2038 | } | |
1da177e4 | 2039 | |
1da177e4 | 2040 | |
c9df406f LB |
2041 | /* netdev ops and related ***************************************************/ |
2042 | static void eth_port_reset(struct mv643xx_private *mp); | |
1da177e4 | 2043 | |
c9df406f LB |
2044 | /* Set the mv643xx port configuration register for the speed/duplex mode. */ |
2045 | static void mv643xx_eth_update_pscr(struct net_device *dev, | |
2046 | struct ethtool_cmd *ecmd) | |
2047 | { | |
2048 | struct mv643xx_private *mp = netdev_priv(dev); | |
2049 | int port_num = mp->port_num; | |
2050 | u32 o_pscr, n_pscr; | |
2051 | unsigned int queues; | |
1da177e4 | 2052 | |
c9df406f LB |
2053 | o_pscr = rdl(mp, PORT_SERIAL_CONTROL_REG(port_num)); |
2054 | n_pscr = o_pscr; | |
63c9e549 | 2055 | |
c9df406f LB |
2056 | /* clear speed, duplex and rx buffer size fields */ |
2057 | n_pscr &= ~(SET_MII_SPEED_TO_100 | | |
2058 | SET_GMII_SPEED_TO_1000 | | |
2059 | SET_FULL_DUPLEX_MODE | | |
2060 | MAX_RX_PACKET_MASK); | |
1da177e4 | 2061 | |
c9df406f LB |
2062 | if (ecmd->duplex == DUPLEX_FULL) |
2063 | n_pscr |= SET_FULL_DUPLEX_MODE; | |
1da177e4 | 2064 | |
c9df406f LB |
2065 | if (ecmd->speed == SPEED_1000) |
2066 | n_pscr |= SET_GMII_SPEED_TO_1000 | | |
2067 | MAX_RX_PACKET_9700BYTE; | |
2068 | else { | |
2069 | if (ecmd->speed == SPEED_100) | |
2070 | n_pscr |= SET_MII_SPEED_TO_100; | |
2071 | n_pscr |= MAX_RX_PACKET_1522BYTE; | |
2072 | } | |
1da177e4 | 2073 | |
c9df406f LB |
2074 | if (n_pscr != o_pscr) { |
2075 | if ((o_pscr & SERIAL_PORT_ENABLE) == 0) | |
2076 | wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), n_pscr); | |
2077 | else { | |
2078 | queues = mv643xx_eth_port_disable_tx(mp); | |
1da177e4 | 2079 | |
c9df406f LB |
2080 | o_pscr &= ~SERIAL_PORT_ENABLE; |
2081 | wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), o_pscr); | |
2082 | wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), n_pscr); | |
2083 | wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), n_pscr); | |
2084 | if (queues) | |
2085 | mv643xx_eth_port_enable_tx(mp, queues); | |
2086 | } | |
2087 | } | |
2088 | } | |
84dd619e | 2089 | |
c9df406f LB |
2090 | /* |
2091 | * mv643xx_eth_int_handler | |
2092 | * | |
2093 | * Main interrupt handler for the gigbit ethernet ports | |
2094 | * | |
2095 | * Input : irq - irq number (not used) | |
2096 | * dev_id - a pointer to the required interface's data structure | |
2097 | * regs - not used | |
2098 | * Output : N/A | |
2099 | */ | |
f2ce825d | 2100 | |
c9df406f LB |
2101 | static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id) |
2102 | { | |
2103 | struct net_device *dev = (struct net_device *)dev_id; | |
2104 | struct mv643xx_private *mp = netdev_priv(dev); | |
2105 | u32 eth_int_cause, eth_int_cause_ext = 0; | |
2106 | unsigned int port_num = mp->port_num; | |
ce4e2e45 | 2107 | |
c9df406f LB |
2108 | /* Read interrupt cause registers */ |
2109 | eth_int_cause = rdl(mp, INTERRUPT_CAUSE_REG(port_num)) & | |
2110 | ETH_INT_UNMASK_ALL; | |
2111 | if (eth_int_cause & ETH_INT_CAUSE_EXT) { | |
2112 | eth_int_cause_ext = rdl(mp, | |
2113 | INTERRUPT_CAUSE_EXTEND_REG(port_num)) & | |
2114 | ETH_INT_UNMASK_ALL_EXT; | |
2115 | wrl(mp, INTERRUPT_CAUSE_EXTEND_REG(port_num), | |
2116 | ~eth_int_cause_ext); | |
2117 | } | |
1da177e4 | 2118 | |
c9df406f LB |
2119 | /* PHY status changed */ |
2120 | if (eth_int_cause_ext & (ETH_INT_CAUSE_PHY | ETH_INT_CAUSE_STATE)) { | |
2121 | struct ethtool_cmd cmd; | |
1da177e4 | 2122 | |
c9df406f LB |
2123 | if (mii_link_ok(&mp->mii)) { |
2124 | mii_ethtool_gset(&mp->mii, &cmd); | |
2125 | mv643xx_eth_update_pscr(dev, &cmd); | |
2126 | mv643xx_eth_port_enable_tx(mp, ETH_TX_QUEUES_ENABLED); | |
2127 | if (!netif_carrier_ok(dev)) { | |
2128 | netif_carrier_on(dev); | |
2129 | if (mp->tx_ring_size - mp->tx_desc_count >= | |
2130 | MAX_DESCS_PER_SKB) | |
2131 | netif_wake_queue(dev); | |
2132 | } | |
2133 | } else if (netif_carrier_ok(dev)) { | |
2134 | netif_stop_queue(dev); | |
2135 | netif_carrier_off(dev); | |
2136 | } | |
2137 | } | |
1da177e4 | 2138 | |
c9df406f LB |
2139 | #ifdef MV643XX_NAPI |
2140 | if (eth_int_cause & ETH_INT_CAUSE_RX) { | |
2141 | /* schedule the NAPI poll routine to maintain port */ | |
2142 | wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL); | |
1da177e4 | 2143 | |
c9df406f LB |
2144 | /* wait for previous write to complete */ |
2145 | rdl(mp, INTERRUPT_MASK_REG(port_num)); | |
1da177e4 | 2146 | |
c9df406f | 2147 | netif_rx_schedule(dev, &mp->napi); |
84dd619e | 2148 | } |
c9df406f LB |
2149 | #else |
2150 | if (eth_int_cause & ETH_INT_CAUSE_RX) | |
2151 | mv643xx_eth_receive_queue(dev, INT_MAX); | |
2152 | #endif | |
2153 | if (eth_int_cause_ext & ETH_INT_CAUSE_TX) | |
2154 | mv643xx_eth_free_completed_tx_descs(dev); | |
1da177e4 | 2155 | |
f2ce825d | 2156 | /* |
c9df406f LB |
2157 | * If no real interrupt occured, exit. |
2158 | * This can happen when using gigE interrupt coalescing mechanism. | |
f2ce825d | 2159 | */ |
c9df406f LB |
2160 | if ((eth_int_cause == 0x0) && (eth_int_cause_ext == 0x0)) |
2161 | return IRQ_NONE; | |
1da177e4 | 2162 | |
c9df406f | 2163 | return IRQ_HANDLED; |
1da177e4 LT |
2164 | } |
2165 | ||
1da177e4 | 2166 | /* |
c9df406f | 2167 | * ethernet_phy_reset - Reset Ethernet port PHY. |
1da177e4 LT |
2168 | * |
2169 | * DESCRIPTION: | |
c9df406f | 2170 | * This routine utilizes the SMI interface to reset the ethernet port PHY. |
1da177e4 LT |
2171 | * |
2172 | * INPUT: | |
c9df406f | 2173 | * struct mv643xx_private *mp Ethernet Port. |
1da177e4 LT |
2174 | * |
2175 | * OUTPUT: | |
c9df406f | 2176 | * The PHY is reset. |
1da177e4 LT |
2177 | * |
2178 | * RETURN: | |
2179 | * None. | |
c9df406f | 2180 | * |
1da177e4 | 2181 | */ |
c9df406f | 2182 | static void ethernet_phy_reset(struct mv643xx_private *mp) |
1da177e4 | 2183 | { |
c9df406f | 2184 | unsigned int phy_reg_data; |
1da177e4 | 2185 | |
c9df406f LB |
2186 | /* Reset the PHY */ |
2187 | eth_port_read_smi_reg(mp, 0, &phy_reg_data); | |
2188 | phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */ | |
2189 | eth_port_write_smi_reg(mp, 0, phy_reg_data); | |
1da177e4 | 2190 | |
c9df406f LB |
2191 | /* wait for PHY to come out of reset */ |
2192 | do { | |
2193 | udelay(1); | |
2194 | eth_port_read_smi_reg(mp, 0, &phy_reg_data); | |
2195 | } while (phy_reg_data & 0x8000); | |
1da177e4 LT |
2196 | } |
2197 | ||
2198 | /* | |
2199 | * eth_port_start - Start the Ethernet port activity. | |
2200 | * | |
2201 | * DESCRIPTION: | |
2202 | * This routine prepares the Ethernet port for Rx and Tx activity: | |
2203 | * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that | |
2204 | * has been initialized a descriptor's ring (using | |
2205 | * ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx) | |
2206 | * 2. Initialize and enable the Ethernet configuration port by writing to | |
2207 | * the port's configuration and command registers. | |
2208 | * 3. Initialize and enable the SDMA by writing to the SDMA's | |
2209 | * configuration and command registers. After completing these steps, | |
2210 | * the ethernet port SDMA can starts to perform Rx and Tx activities. | |
2211 | * | |
2212 | * Note: Each Rx and Tx queue descriptor's list must be initialized prior | |
2213 | * to calling this function (use ether_init_tx_desc_ring for Tx queues | |
2214 | * and ether_init_rx_desc_ring for Rx queues). | |
2215 | * | |
2216 | * INPUT: | |
ed9b5d45 | 2217 | * dev - a pointer to the required interface |
1da177e4 LT |
2218 | * |
2219 | * OUTPUT: | |
2220 | * Ethernet port is ready to receive and transmit. | |
2221 | * | |
2222 | * RETURN: | |
2223 | * None. | |
2224 | */ | |
ed9b5d45 | 2225 | static void eth_port_start(struct net_device *dev) |
1da177e4 | 2226 | { |
ed9b5d45 | 2227 | struct mv643xx_private *mp = netdev_priv(dev); |
1da177e4 LT |
2228 | unsigned int port_num = mp->port_num; |
2229 | int tx_curr_desc, rx_curr_desc; | |
d0412d96 JC |
2230 | u32 pscr; |
2231 | struct ethtool_cmd ethtool_cmd; | |
1da177e4 LT |
2232 | |
2233 | /* Assignment of Tx CTRP of given queue */ | |
2234 | tx_curr_desc = mp->tx_curr_desc_q; | |
ec69d651 | 2235 | wrl(mp, TX_CURRENT_QUEUE_DESC_PTR_0(port_num), |
1da177e4 LT |
2236 | (u32)((struct eth_tx_desc *)mp->tx_desc_dma + tx_curr_desc)); |
2237 | ||
2238 | /* Assignment of Rx CRDP of given queue */ | |
2239 | rx_curr_desc = mp->rx_curr_desc_q; | |
ec69d651 | 2240 | wrl(mp, RX_CURRENT_QUEUE_DESC_PTR_0(port_num), |
1da177e4 LT |
2241 | (u32)((struct eth_rx_desc *)mp->rx_desc_dma + rx_curr_desc)); |
2242 | ||
2243 | /* Add the assigned Ethernet address to the port's address table */ | |
afdb57a2 | 2244 | eth_port_uc_addr_set(mp, dev->dev_addr); |
1da177e4 LT |
2245 | |
2246 | /* Assign port configuration and command. */ | |
ec69d651 | 2247 | wrl(mp, PORT_CONFIG_REG(port_num), |
e4d00fa9 | 2248 | PORT_CONFIG_DEFAULT_VALUE); |
01999873 | 2249 | |
ec69d651 | 2250 | wrl(mp, PORT_CONFIG_EXTEND_REG(port_num), |
e4d00fa9 | 2251 | PORT_CONFIG_EXTEND_DEFAULT_VALUE); |
1da177e4 | 2252 | |
ec69d651 | 2253 | pscr = rdl(mp, PORT_SERIAL_CONTROL_REG(port_num)); |
01999873 | 2254 | |
e4d00fa9 | 2255 | pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS); |
ec69d651 | 2256 | wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), pscr); |
1da177e4 | 2257 | |
e4d00fa9 LB |
2258 | pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL | |
2259 | DISABLE_AUTO_NEG_SPEED_GMII | | |
2260 | DISABLE_AUTO_NEG_FOR_DUPLX | | |
2261 | DO_NOT_FORCE_LINK_FAIL | | |
2262 | SERIAL_PORT_CONTROL_RESERVED; | |
1da177e4 | 2263 | |
ec69d651 | 2264 | wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), pscr); |
1da177e4 | 2265 | |
e4d00fa9 | 2266 | pscr |= SERIAL_PORT_ENABLE; |
ec69d651 | 2267 | wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), pscr); |
1da177e4 LT |
2268 | |
2269 | /* Assign port SDMA configuration */ | |
ec69d651 | 2270 | wrl(mp, SDMA_CONFIG_REG(port_num), |
e4d00fa9 | 2271 | PORT_SDMA_CONFIG_DEFAULT_VALUE); |
1da177e4 LT |
2272 | |
2273 | /* Enable port Rx. */ | |
afdb57a2 | 2274 | mv643xx_eth_port_enable_rx(mp, ETH_RX_QUEUES_ENABLED); |
8f543718 DF |
2275 | |
2276 | /* Disable port bandwidth limits by clearing MTU register */ | |
ec69d651 | 2277 | wrl(mp, MAXIMUM_TRANSMIT_UNIT(port_num), 0); |
d0412d96 JC |
2278 | |
2279 | /* save phy settings across reset */ | |
2280 | mv643xx_get_settings(dev, ðtool_cmd); | |
afdb57a2 | 2281 | ethernet_phy_reset(mp); |
d0412d96 | 2282 | mv643xx_set_settings(dev, ðtool_cmd); |
1da177e4 LT |
2283 | } |
2284 | ||
c9df406f LB |
2285 | #ifdef MV643XX_COAL |
2286 | ||
1da177e4 | 2287 | /* |
c9df406f LB |
2288 | * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path |
2289 | * | |
2290 | * DESCRIPTION: | |
2291 | * This routine sets the RX coalescing interrupt mechanism parameter. | |
2292 | * This parameter is a timeout counter, that counts in 64 t_clk | |
2293 | * chunks ; that when timeout event occurs a maskable interrupt | |
2294 | * occurs. | |
2295 | * The parameter is calculated using the tClk of the MV-643xx chip | |
2296 | * , and the required delay of the interrupt in usec. | |
2297 | * | |
2298 | * INPUT: | |
2299 | * struct mv643xx_private *mp Ethernet port | |
2300 | * unsigned int delay Delay in usec | |
2301 | * | |
2302 | * OUTPUT: | |
2303 | * Interrupt coalescing mechanism value is set in MV-643xx chip. | |
2304 | * | |
2305 | * RETURN: | |
2306 | * The interrupt coalescing value set in the gigE port. | |
2307 | * | |
1da177e4 | 2308 | */ |
c9df406f LB |
2309 | static unsigned int eth_port_set_rx_coal(struct mv643xx_private *mp, |
2310 | unsigned int delay) | |
1da177e4 | 2311 | { |
afdb57a2 | 2312 | unsigned int port_num = mp->port_num; |
c9df406f | 2313 | unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64; |
1da177e4 | 2314 | |
c9df406f LB |
2315 | /* Set RX Coalescing mechanism */ |
2316 | wrl(mp, SDMA_CONFIG_REG(port_num), | |
2317 | ((coal & 0x3fff) << 8) | | |
2318 | (rdl(mp, SDMA_CONFIG_REG(port_num)) | |
2319 | & 0xffc000ff)); | |
1da177e4 | 2320 | |
c9df406f | 2321 | return coal; |
1da177e4 | 2322 | } |
c9df406f | 2323 | #endif |
1da177e4 LT |
2324 | |
2325 | /* | |
c9df406f LB |
2326 | * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path |
2327 | * | |
2328 | * DESCRIPTION: | |
2329 | * This routine sets the TX coalescing interrupt mechanism parameter. | |
2330 | * This parameter is a timeout counter, that counts in 64 t_clk | |
2331 | * chunks ; that when timeout event occurs a maskable interrupt | |
2332 | * occurs. | |
2333 | * The parameter is calculated using the t_cLK frequency of the | |
2334 | * MV-643xx chip and the required delay in the interrupt in uSec | |
2335 | * | |
2336 | * INPUT: | |
2337 | * struct mv643xx_private *mp Ethernet port | |
2338 | * unsigned int delay Delay in uSeconds | |
2339 | * | |
2340 | * OUTPUT: | |
2341 | * Interrupt coalescing mechanism value is set in MV-643xx chip. | |
2342 | * | |
2343 | * RETURN: | |
2344 | * The interrupt coalescing value set in the gigE port. | |
2345 | * | |
1da177e4 | 2346 | */ |
c9df406f LB |
2347 | static unsigned int eth_port_set_tx_coal(struct mv643xx_private *mp, |
2348 | unsigned int delay) | |
1da177e4 | 2349 | { |
c9df406f | 2350 | unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64; |
1da177e4 | 2351 | |
c9df406f LB |
2352 | /* Set TX Coalescing mechanism */ |
2353 | wrl(mp, TX_FIFO_URGENT_THRESHOLD_REG(mp->port_num), coal << 4); | |
1da177e4 | 2354 | |
c9df406f | 2355 | return coal; |
1da177e4 LT |
2356 | } |
2357 | ||
16e03018 | 2358 | /* |
c9df406f LB |
2359 | * eth_port_init - Initialize the Ethernet port driver |
2360 | * | |
2361 | * DESCRIPTION: | |
2362 | * This function prepares the ethernet port to start its activity: | |
2363 | * 1) Completes the ethernet port driver struct initialization toward port | |
2364 | * start routine. | |
2365 | * 2) Resets the device to a quiescent state in case of warm reboot. | |
2366 | * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM. | |
2367 | * 4) Clean MAC tables. The reset status of those tables is unknown. | |
2368 | * 5) Set PHY address. | |
2369 | * Note: Call this routine prior to eth_port_start routine and after | |
2370 | * setting user values in the user fields of Ethernet port control | |
2371 | * struct. | |
2372 | * | |
2373 | * INPUT: | |
2374 | * struct mv643xx_private *mp Ethernet port control struct | |
2375 | * | |
2376 | * OUTPUT: | |
2377 | * See description. | |
2378 | * | |
2379 | * RETURN: | |
2380 | * None. | |
16e03018 | 2381 | */ |
c9df406f | 2382 | static void eth_port_init(struct mv643xx_private *mp) |
16e03018 | 2383 | { |
c9df406f | 2384 | mp->rx_resource_err = 0; |
16e03018 | 2385 | |
c9df406f | 2386 | eth_port_reset(mp); |
16e03018 | 2387 | |
c9df406f | 2388 | eth_port_init_mac_tables(mp); |
16e03018 DF |
2389 | } |
2390 | ||
2391 | /* | |
c9df406f | 2392 | * mv643xx_eth_open |
16e03018 | 2393 | * |
c9df406f LB |
2394 | * This function is called when openning the network device. The function |
2395 | * should initialize all the hardware, initialize cyclic Rx/Tx | |
2396 | * descriptors chain and buffers and allocate an IRQ to the network | |
2397 | * device. | |
2398 | * | |
2399 | * Input : a pointer to the network device structure | |
2400 | * | |
2401 | * Output : zero of success , nonzero if fails. | |
16e03018 | 2402 | */ |
c9df406f LB |
2403 | |
2404 | static int mv643xx_eth_open(struct net_device *dev) | |
16e03018 | 2405 | { |
c9df406f | 2406 | struct mv643xx_private *mp = netdev_priv(dev); |
afdb57a2 | 2407 | unsigned int port_num = mp->port_num; |
c9df406f LB |
2408 | unsigned int size; |
2409 | int err; | |
16e03018 | 2410 | |
c9df406f LB |
2411 | /* Clear any pending ethernet port interrupts */ |
2412 | wrl(mp, INTERRUPT_CAUSE_REG(port_num), 0); | |
2413 | wrl(mp, INTERRUPT_CAUSE_EXTEND_REG(port_num), 0); | |
2414 | /* wait for previous write to complete */ | |
2415 | rdl(mp, INTERRUPT_CAUSE_EXTEND_REG(port_num)); | |
2416 | ||
2417 | err = request_irq(dev->irq, mv643xx_eth_int_handler, | |
2418 | IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev); | |
2419 | if (err) { | |
2420 | printk(KERN_ERR "%s: Can not assign IRQ\n", dev->name); | |
2421 | return -EAGAIN; | |
16e03018 DF |
2422 | } |
2423 | ||
c9df406f | 2424 | eth_port_init(mp); |
16e03018 | 2425 | |
c9df406f LB |
2426 | memset(&mp->timeout, 0, sizeof(struct timer_list)); |
2427 | mp->timeout.function = mv643xx_eth_rx_refill_descs_timer_wrapper; | |
2428 | mp->timeout.data = (unsigned long)dev; | |
16e03018 | 2429 | |
c9df406f LB |
2430 | /* Allocate RX and TX skb rings */ |
2431 | mp->rx_skb = kmalloc(sizeof(*mp->rx_skb) * mp->rx_ring_size, | |
2432 | GFP_KERNEL); | |
2433 | if (!mp->rx_skb) { | |
2434 | printk(KERN_ERR "%s: Cannot allocate Rx skb ring\n", dev->name); | |
2435 | err = -ENOMEM; | |
2436 | goto out_free_irq; | |
2437 | } | |
2438 | mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size, | |
2439 | GFP_KERNEL); | |
2440 | if (!mp->tx_skb) { | |
2441 | printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name); | |
2442 | err = -ENOMEM; | |
2443 | goto out_free_rx_skb; | |
2444 | } | |
16e03018 | 2445 | |
c9df406f LB |
2446 | /* Allocate TX ring */ |
2447 | mp->tx_desc_count = 0; | |
2448 | size = mp->tx_ring_size * sizeof(struct eth_tx_desc); | |
2449 | mp->tx_desc_area_size = size; | |
16e03018 | 2450 | |
c9df406f LB |
2451 | if (mp->tx_sram_size) { |
2452 | mp->p_tx_desc_area = ioremap(mp->tx_sram_addr, | |
2453 | mp->tx_sram_size); | |
2454 | mp->tx_desc_dma = mp->tx_sram_addr; | |
2455 | } else | |
2456 | mp->p_tx_desc_area = dma_alloc_coherent(NULL, size, | |
2457 | &mp->tx_desc_dma, | |
2458 | GFP_KERNEL); | |
16e03018 | 2459 | |
c9df406f LB |
2460 | if (!mp->p_tx_desc_area) { |
2461 | printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n", | |
2462 | dev->name, size); | |
2463 | err = -ENOMEM; | |
2464 | goto out_free_tx_skb; | |
2465 | } | |
2466 | BUG_ON((u32) mp->p_tx_desc_area & 0xf); /* check 16-byte alignment */ | |
2467 | memset((void *)mp->p_tx_desc_area, 0, mp->tx_desc_area_size); | |
16e03018 | 2468 | |
c9df406f | 2469 | ether_init_tx_desc_ring(mp); |
16e03018 | 2470 | |
c9df406f LB |
2471 | /* Allocate RX ring */ |
2472 | mp->rx_desc_count = 0; | |
2473 | size = mp->rx_ring_size * sizeof(struct eth_rx_desc); | |
2474 | mp->rx_desc_area_size = size; | |
16e03018 | 2475 | |
c9df406f LB |
2476 | if (mp->rx_sram_size) { |
2477 | mp->p_rx_desc_area = ioremap(mp->rx_sram_addr, | |
2478 | mp->rx_sram_size); | |
2479 | mp->rx_desc_dma = mp->rx_sram_addr; | |
2480 | } else | |
2481 | mp->p_rx_desc_area = dma_alloc_coherent(NULL, size, | |
2482 | &mp->rx_desc_dma, | |
2483 | GFP_KERNEL); | |
16e03018 | 2484 | |
c9df406f LB |
2485 | if (!mp->p_rx_desc_area) { |
2486 | printk(KERN_ERR "%s: Cannot allocate Rx ring (size %d bytes)\n", | |
2487 | dev->name, size); | |
2488 | printk(KERN_ERR "%s: Freeing previously allocated TX queues...", | |
2489 | dev->name); | |
2490 | if (mp->rx_sram_size) | |
2491 | iounmap(mp->p_tx_desc_area); | |
2492 | else | |
2493 | dma_free_coherent(NULL, mp->tx_desc_area_size, | |
2494 | mp->p_tx_desc_area, mp->tx_desc_dma); | |
2495 | err = -ENOMEM; | |
2496 | goto out_free_tx_skb; | |
2497 | } | |
2498 | memset((void *)mp->p_rx_desc_area, 0, size); | |
16e03018 | 2499 | |
c9df406f | 2500 | ether_init_rx_desc_ring(mp); |
16e03018 | 2501 | |
c9df406f | 2502 | mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */ |
16e03018 | 2503 | |
c9df406f LB |
2504 | #ifdef MV643XX_NAPI |
2505 | napi_enable(&mp->napi); | |
2506 | #endif | |
16e03018 | 2507 | |
c9df406f | 2508 | eth_port_start(dev); |
16e03018 | 2509 | |
c9df406f | 2510 | /* Interrupt Coalescing */ |
b4de9051 | 2511 | |
c9df406f LB |
2512 | #ifdef MV643XX_COAL |
2513 | mp->rx_int_coal = | |
2514 | eth_port_set_rx_coal(mp, MV643XX_RX_COAL); | |
2515 | #endif | |
2516 | ||
2517 | mp->tx_int_coal = | |
2518 | eth_port_set_tx_coal(mp, MV643XX_TX_COAL); | |
16e03018 | 2519 | |
c9df406f LB |
2520 | /* Unmask phy and link status changes interrupts */ |
2521 | wrl(mp, INTERRUPT_EXTEND_MASK_REG(port_num), ETH_INT_UNMASK_ALL_EXT); | |
16e03018 | 2522 | |
c9df406f LB |
2523 | /* Unmask RX buffer and TX end interrupt */ |
2524 | wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL); | |
16e03018 | 2525 | |
c9df406f LB |
2526 | return 0; |
2527 | ||
2528 | out_free_tx_skb: | |
2529 | kfree(mp->tx_skb); | |
2530 | out_free_rx_skb: | |
2531 | kfree(mp->rx_skb); | |
2532 | out_free_irq: | |
2533 | free_irq(dev->irq, dev); | |
2534 | ||
2535 | return err; | |
16e03018 DF |
2536 | } |
2537 | ||
1da177e4 | 2538 | /* |
c9df406f | 2539 | * eth_port_reset - Reset Ethernet port |
1da177e4 LT |
2540 | * |
2541 | * DESCRIPTION: | |
c9df406f LB |
2542 | * This routine resets the chip by aborting any SDMA engine activity and |
2543 | * clearing the MIB counters. The Receiver and the Transmit unit are in | |
2544 | * idle state after this command is performed and the port is disabled. | |
1da177e4 LT |
2545 | * |
2546 | * INPUT: | |
afdb57a2 | 2547 | * struct mv643xx_private *mp Ethernet Port. |
1da177e4 LT |
2548 | * |
2549 | * OUTPUT: | |
c9df406f | 2550 | * Channel activity is halted. |
1da177e4 LT |
2551 | * |
2552 | * RETURN: | |
2553 | * None. | |
c9df406f | 2554 | * |
1da177e4 | 2555 | */ |
c9df406f | 2556 | static void eth_port_reset(struct mv643xx_private *mp) |
1da177e4 | 2557 | { |
afdb57a2 | 2558 | unsigned int port_num = mp->port_num; |
c9df406f | 2559 | unsigned int reg_data; |
1da177e4 | 2560 | |
c9df406f LB |
2561 | mv643xx_eth_port_disable_tx(mp); |
2562 | mv643xx_eth_port_disable_rx(mp); | |
1da177e4 | 2563 | |
c9df406f LB |
2564 | /* Clear all MIB counters */ |
2565 | eth_clear_mib_counters(mp); | |
2566 | ||
2567 | /* Reset the Enable bit in the Configuration Register */ | |
2568 | reg_data = rdl(mp, PORT_SERIAL_CONTROL_REG(port_num)); | |
2569 | reg_data &= ~(SERIAL_PORT_ENABLE | | |
2570 | DO_NOT_FORCE_LINK_FAIL | | |
2571 | FORCE_LINK_PASS); | |
2572 | wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), reg_data); | |
1da177e4 LT |
2573 | } |
2574 | ||
2575 | /* | |
c9df406f | 2576 | * mv643xx_eth_stop |
1da177e4 | 2577 | * |
c9df406f LB |
2578 | * This function is used when closing the network device. |
2579 | * It updates the hardware, | |
2580 | * release all memory that holds buffers and descriptors and release the IRQ. | |
2581 | * Input : a pointer to the device structure | |
2582 | * Output : zero if success , nonzero if fails | |
1da177e4 | 2583 | */ |
c9df406f LB |
2584 | |
2585 | static int mv643xx_eth_stop(struct net_device *dev) | |
1da177e4 | 2586 | { |
c9df406f | 2587 | struct mv643xx_private *mp = netdev_priv(dev); |
afdb57a2 | 2588 | unsigned int port_num = mp->port_num; |
1da177e4 | 2589 | |
c9df406f LB |
2590 | /* Mask all interrupts on ethernet port */ |
2591 | wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL); | |
2592 | /* wait for previous write to complete */ | |
2593 | rdl(mp, INTERRUPT_MASK_REG(port_num)); | |
1da177e4 | 2594 | |
c9df406f LB |
2595 | #ifdef MV643XX_NAPI |
2596 | napi_disable(&mp->napi); | |
2597 | #endif | |
2598 | netif_carrier_off(dev); | |
2599 | netif_stop_queue(dev); | |
1da177e4 | 2600 | |
c9df406f | 2601 | eth_port_reset(mp); |
1da177e4 | 2602 | |
c9df406f LB |
2603 | mv643xx_eth_free_tx_rings(dev); |
2604 | mv643xx_eth_free_rx_rings(dev); | |
1da177e4 | 2605 | |
c9df406f | 2606 | free_irq(dev->irq, dev); |
1da177e4 | 2607 | |
c9df406f | 2608 | return 0; |
1da177e4 LT |
2609 | } |
2610 | ||
c9df406f | 2611 | static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
1da177e4 | 2612 | { |
c9df406f | 2613 | struct mv643xx_private *mp = netdev_priv(dev); |
1da177e4 | 2614 | |
c9df406f | 2615 | return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL); |
1da177e4 LT |
2616 | } |
2617 | ||
2618 | /* | |
c9df406f | 2619 | * Changes MTU (maximum transfer unit) of the gigabit ethenret port |
1da177e4 | 2620 | * |
c9df406f LB |
2621 | * Input : pointer to ethernet interface network device structure |
2622 | * new mtu size | |
2623 | * Output : 0 upon success, -EINVAL upon failure | |
1da177e4 | 2624 | */ |
c9df406f | 2625 | static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu) |
1da177e4 | 2626 | { |
c9df406f LB |
2627 | if ((new_mtu > 9500) || (new_mtu < 64)) |
2628 | return -EINVAL; | |
1da177e4 | 2629 | |
c9df406f LB |
2630 | dev->mtu = new_mtu; |
2631 | if (!netif_running(dev)) | |
2632 | return 0; | |
1da177e4 | 2633 | |
c9df406f LB |
2634 | /* |
2635 | * Stop and then re-open the interface. This will allocate RX | |
2636 | * skbs of the new MTU. | |
2637 | * There is a possible danger that the open will not succeed, | |
2638 | * due to memory being full, which might fail the open function. | |
2639 | */ | |
2640 | mv643xx_eth_stop(dev); | |
2641 | if (mv643xx_eth_open(dev)) { | |
2642 | printk(KERN_ERR "%s: Fatal error on opening device\n", | |
2643 | dev->name); | |
2644 | } | |
2645 | ||
2646 | return 0; | |
1da177e4 LT |
2647 | } |
2648 | ||
2649 | /* | |
c9df406f | 2650 | * mv643xx_eth_tx_timeout_task |
1da177e4 | 2651 | * |
c9df406f | 2652 | * Actual routine to reset the adapter when a timeout on Tx has occurred |
1da177e4 | 2653 | */ |
c9df406f | 2654 | static void mv643xx_eth_tx_timeout_task(struct work_struct *ugly) |
1da177e4 | 2655 | { |
c9df406f LB |
2656 | struct mv643xx_private *mp = container_of(ugly, struct mv643xx_private, |
2657 | tx_timeout_task); | |
2658 | struct net_device *dev = mp->dev; | |
1da177e4 | 2659 | |
c9df406f LB |
2660 | if (!netif_running(dev)) |
2661 | return; | |
1da177e4 | 2662 | |
c9df406f LB |
2663 | netif_stop_queue(dev); |
2664 | ||
2665 | eth_port_reset(mp); | |
2666 | eth_port_start(dev); | |
2667 | ||
2668 | if (mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB) | |
2669 | netif_wake_queue(dev); | |
2670 | } | |
2671 | ||
2672 | /* | |
2673 | * mv643xx_eth_tx_timeout | |
1da177e4 | 2674 | * |
c9df406f | 2675 | * Called upon a timeout on transmitting a packet |
1da177e4 | 2676 | * |
c9df406f LB |
2677 | * Input : pointer to ethernet interface network device structure. |
2678 | * Output : N/A | |
1da177e4 | 2679 | */ |
c9df406f | 2680 | static void mv643xx_eth_tx_timeout(struct net_device *dev) |
1da177e4 | 2681 | { |
c9df406f | 2682 | struct mv643xx_private *mp = netdev_priv(dev); |
1da177e4 | 2683 | |
c9df406f | 2684 | printk(KERN_INFO "%s: TX timeout ", dev->name); |
d0412d96 | 2685 | |
c9df406f LB |
2686 | /* Do the reset outside of interrupt context */ |
2687 | schedule_work(&mp->tx_timeout_task); | |
1da177e4 LT |
2688 | } |
2689 | ||
c9df406f LB |
2690 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2691 | static void mv643xx_netpoll(struct net_device *netdev) | |
9f8dd319 | 2692 | { |
c9df406f LB |
2693 | struct mv643xx_private *mp = netdev_priv(netdev); |
2694 | int port_num = mp->port_num; | |
2695 | ||
2696 | wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL); | |
2697 | /* wait for previous write to complete */ | |
2698 | rdl(mp, INTERRUPT_MASK_REG(port_num)); | |
2699 | ||
2700 | mv643xx_eth_int_handler(netdev->irq, netdev); | |
2701 | ||
2702 | wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL); | |
9f8dd319 | 2703 | } |
c9df406f | 2704 | #endif |
9f8dd319 | 2705 | |
c9df406f LB |
2706 | /* |
2707 | * Wrappers for MII support library. | |
2708 | */ | |
2709 | static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location) | |
9f8dd319 | 2710 | { |
c9df406f LB |
2711 | struct mv643xx_private *mp = netdev_priv(dev); |
2712 | int val; | |
2713 | ||
2714 | eth_port_read_smi_reg(mp, location, &val); | |
2715 | return val; | |
9f8dd319 DF |
2716 | } |
2717 | ||
c9df406f | 2718 | static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val) |
9f8dd319 | 2719 | { |
c9df406f LB |
2720 | struct mv643xx_private *mp = netdev_priv(dev); |
2721 | eth_port_write_smi_reg(mp, location, val); | |
2722 | } | |
9f8dd319 | 2723 | |
9f8dd319 | 2724 | |
c9df406f LB |
2725 | /* platform glue ************************************************************/ |
2726 | static void mv643xx_eth_conf_mbus_windows(struct mv643xx_shared_private *msp, | |
2727 | struct mbus_dram_target_info *dram) | |
2728 | { | |
2729 | void __iomem *base = msp->eth_base; | |
2730 | u32 win_enable; | |
2731 | u32 win_protect; | |
2732 | int i; | |
9f8dd319 | 2733 | |
c9df406f LB |
2734 | for (i = 0; i < 6; i++) { |
2735 | writel(0, base + WINDOW_BASE(i)); | |
2736 | writel(0, base + WINDOW_SIZE(i)); | |
2737 | if (i < 4) | |
2738 | writel(0, base + WINDOW_REMAP_HIGH(i)); | |
9f8dd319 DF |
2739 | } |
2740 | ||
c9df406f LB |
2741 | win_enable = 0x3f; |
2742 | win_protect = 0; | |
2743 | ||
2744 | for (i = 0; i < dram->num_cs; i++) { | |
2745 | struct mbus_dram_window *cs = dram->cs + i; | |
2746 | ||
2747 | writel((cs->base & 0xffff0000) | | |
2748 | (cs->mbus_attr << 8) | | |
2749 | dram->mbus_dram_target_id, base + WINDOW_BASE(i)); | |
2750 | writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i)); | |
2751 | ||
2752 | win_enable &= ~(1 << i); | |
2753 | win_protect |= 3 << (2 * i); | |
2754 | } | |
2755 | ||
2756 | writel(win_enable, base + WINDOW_BAR_ENABLE); | |
2757 | msp->win_protect = win_protect; | |
9f8dd319 DF |
2758 | } |
2759 | ||
c9df406f | 2760 | static int mv643xx_eth_shared_probe(struct platform_device *pdev) |
9f8dd319 | 2761 | { |
c9df406f LB |
2762 | static int mv643xx_version_printed = 0; |
2763 | struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data; | |
2764 | struct mv643xx_shared_private *msp; | |
2765 | struct resource *res; | |
2766 | int ret; | |
9f8dd319 | 2767 | |
c9df406f LB |
2768 | if (!mv643xx_version_printed++) |
2769 | printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n"); | |
9f8dd319 | 2770 | |
c9df406f LB |
2771 | ret = -EINVAL; |
2772 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2773 | if (res == NULL) | |
2774 | goto out; | |
9f8dd319 | 2775 | |
c9df406f LB |
2776 | ret = -ENOMEM; |
2777 | msp = kmalloc(sizeof(*msp), GFP_KERNEL); | |
2778 | if (msp == NULL) | |
2779 | goto out; | |
2780 | memset(msp, 0, sizeof(*msp)); | |
2781 | ||
2782 | msp->eth_base = ioremap(res->start, res->end - res->start + 1); | |
2783 | if (msp->eth_base == NULL) | |
2784 | goto out_free; | |
2785 | ||
2786 | spin_lock_init(&msp->phy_lock); | |
2787 | msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000; | |
2788 | ||
2789 | platform_set_drvdata(pdev, msp); | |
2790 | ||
2791 | /* | |
2792 | * (Re-)program MBUS remapping windows if we are asked to. | |
2793 | */ | |
2794 | if (pd != NULL && pd->dram != NULL) | |
2795 | mv643xx_eth_conf_mbus_windows(msp, pd->dram); | |
2796 | ||
2797 | return 0; | |
2798 | ||
2799 | out_free: | |
2800 | kfree(msp); | |
2801 | out: | |
2802 | return ret; | |
2803 | } | |
2804 | ||
2805 | static int mv643xx_eth_shared_remove(struct platform_device *pdev) | |
2806 | { | |
2807 | struct mv643xx_shared_private *msp = platform_get_drvdata(pdev); | |
2808 | ||
2809 | iounmap(msp->eth_base); | |
2810 | kfree(msp); | |
2811 | ||
2812 | return 0; | |
9f8dd319 DF |
2813 | } |
2814 | ||
c9df406f LB |
2815 | static struct platform_driver mv643xx_eth_shared_driver = { |
2816 | .probe = mv643xx_eth_shared_probe, | |
2817 | .remove = mv643xx_eth_shared_remove, | |
2818 | .driver = { | |
2819 | .name = MV643XX_ETH_SHARED_NAME, | |
2820 | .owner = THIS_MODULE, | |
2821 | }, | |
2822 | }; | |
2823 | ||
1da177e4 | 2824 | /* |
c9df406f | 2825 | * ethernet_phy_set - Set the ethernet port PHY address. |
1da177e4 LT |
2826 | * |
2827 | * DESCRIPTION: | |
c9df406f | 2828 | * This routine sets the given ethernet port PHY address. |
1da177e4 LT |
2829 | * |
2830 | * INPUT: | |
afdb57a2 | 2831 | * struct mv643xx_private *mp Ethernet Port. |
c9df406f | 2832 | * int phy_addr PHY address. |
1da177e4 LT |
2833 | * |
2834 | * OUTPUT: | |
c9df406f | 2835 | * None. |
1da177e4 LT |
2836 | * |
2837 | * RETURN: | |
2838 | * None. | |
2839 | * | |
2840 | */ | |
c9df406f | 2841 | static void ethernet_phy_set(struct mv643xx_private *mp, int phy_addr) |
1da177e4 | 2842 | { |
c9df406f LB |
2843 | u32 reg_data; |
2844 | int addr_shift = 5 * mp->port_num; | |
1da177e4 | 2845 | |
c9df406f LB |
2846 | reg_data = rdl(mp, PHY_ADDR_REG); |
2847 | reg_data &= ~(0x1f << addr_shift); | |
2848 | reg_data |= (phy_addr & 0x1f) << addr_shift; | |
2849 | wrl(mp, PHY_ADDR_REG, reg_data); | |
1da177e4 LT |
2850 | } |
2851 | ||
1da177e4 | 2852 | /* |
c9df406f | 2853 | * ethernet_phy_get - Get the ethernet port PHY address. |
1da177e4 LT |
2854 | * |
2855 | * DESCRIPTION: | |
c9df406f | 2856 | * This routine returns the given ethernet port PHY address. |
1da177e4 LT |
2857 | * |
2858 | * INPUT: | |
afdb57a2 | 2859 | * struct mv643xx_private *mp Ethernet Port. |
1da177e4 LT |
2860 | * |
2861 | * OUTPUT: | |
c9df406f | 2862 | * None. |
1da177e4 LT |
2863 | * |
2864 | * RETURN: | |
c9df406f | 2865 | * PHY address. |
1da177e4 LT |
2866 | * |
2867 | */ | |
c9df406f | 2868 | static int ethernet_phy_get(struct mv643xx_private *mp) |
1da177e4 | 2869 | { |
c9df406f | 2870 | unsigned int reg_data; |
1da177e4 | 2871 | |
c9df406f | 2872 | reg_data = rdl(mp, PHY_ADDR_REG); |
1da177e4 | 2873 | |
c9df406f | 2874 | return ((reg_data >> (5 * mp->port_num)) & 0x1f); |
1da177e4 LT |
2875 | } |
2876 | ||
2877 | /* | |
c9df406f | 2878 | * ethernet_phy_detect - Detect whether a phy is present |
1da177e4 LT |
2879 | * |
2880 | * DESCRIPTION: | |
c9df406f LB |
2881 | * This function tests whether there is a PHY present on |
2882 | * the specified port. | |
1da177e4 LT |
2883 | * |
2884 | * INPUT: | |
afdb57a2 | 2885 | * struct mv643xx_private *mp Ethernet Port. |
1da177e4 LT |
2886 | * |
2887 | * OUTPUT: | |
c9df406f | 2888 | * None |
1da177e4 LT |
2889 | * |
2890 | * RETURN: | |
c9df406f LB |
2891 | * 0 on success |
2892 | * -ENODEV on failure | |
1da177e4 LT |
2893 | * |
2894 | */ | |
c9df406f | 2895 | static int ethernet_phy_detect(struct mv643xx_private *mp) |
1da177e4 | 2896 | { |
c9df406f LB |
2897 | unsigned int phy_reg_data0; |
2898 | int auto_neg; | |
1da177e4 | 2899 | |
c9df406f LB |
2900 | eth_port_read_smi_reg(mp, 0, &phy_reg_data0); |
2901 | auto_neg = phy_reg_data0 & 0x1000; | |
2902 | phy_reg_data0 ^= 0x1000; /* invert auto_neg */ | |
2903 | eth_port_write_smi_reg(mp, 0, phy_reg_data0); | |
1da177e4 | 2904 | |
c9df406f LB |
2905 | eth_port_read_smi_reg(mp, 0, &phy_reg_data0); |
2906 | if ((phy_reg_data0 & 0x1000) == auto_neg) | |
2907 | return -ENODEV; /* change didn't take */ | |
1da177e4 | 2908 | |
c9df406f LB |
2909 | phy_reg_data0 ^= 0x1000; |
2910 | eth_port_write_smi_reg(mp, 0, phy_reg_data0); | |
2911 | return 0; | |
1da177e4 LT |
2912 | } |
2913 | ||
c9df406f LB |
2914 | static void mv643xx_init_ethtool_cmd(struct net_device *dev, int phy_address, |
2915 | int speed, int duplex, | |
2916 | struct ethtool_cmd *cmd) | |
c28a4f89 | 2917 | { |
c28a4f89 JC |
2918 | struct mv643xx_private *mp = netdev_priv(dev); |
2919 | ||
c9df406f | 2920 | memset(cmd, 0, sizeof(*cmd)); |
c28a4f89 | 2921 | |
c9df406f LB |
2922 | cmd->port = PORT_MII; |
2923 | cmd->transceiver = XCVR_INTERNAL; | |
2924 | cmd->phy_address = phy_address; | |
2925 | ||
2926 | if (speed == 0) { | |
2927 | cmd->autoneg = AUTONEG_ENABLE; | |
2928 | /* mii lib checks, but doesn't use speed on AUTONEG_ENABLE */ | |
2929 | cmd->speed = SPEED_100; | |
2930 | cmd->advertising = ADVERTISED_10baseT_Half | | |
2931 | ADVERTISED_10baseT_Full | | |
2932 | ADVERTISED_100baseT_Half | | |
2933 | ADVERTISED_100baseT_Full; | |
2934 | if (mp->mii.supports_gmii) | |
2935 | cmd->advertising |= ADVERTISED_1000baseT_Full; | |
2936 | } else { | |
2937 | cmd->autoneg = AUTONEG_DISABLE; | |
2938 | cmd->speed = speed; | |
2939 | cmd->duplex = duplex; | |
2940 | } | |
c28a4f89 JC |
2941 | } |
2942 | ||
c9df406f LB |
2943 | /*/ |
2944 | * mv643xx_eth_probe | |
1da177e4 | 2945 | * |
c9df406f LB |
2946 | * First function called after registering the network device. |
2947 | * It's purpose is to initialize the device as an ethernet device, | |
2948 | * fill the ethernet device structure with pointers * to functions, | |
2949 | * and set the MAC address of the interface | |
1da177e4 | 2950 | * |
c9df406f LB |
2951 | * Input : struct device * |
2952 | * Output : -ENOMEM if failed , 0 if success | |
1da177e4 | 2953 | */ |
c9df406f | 2954 | static int mv643xx_eth_probe(struct platform_device *pdev) |
1da177e4 | 2955 | { |
c9df406f LB |
2956 | struct mv643xx_eth_platform_data *pd; |
2957 | int port_num; | |
2958 | struct mv643xx_private *mp; | |
2959 | struct net_device *dev; | |
2960 | u8 *p; | |
2961 | struct resource *res; | |
2962 | int err; | |
2963 | struct ethtool_cmd cmd; | |
2964 | int duplex = DUPLEX_HALF; | |
2965 | int speed = 0; /* default to auto-negotiation */ | |
2966 | DECLARE_MAC_BUF(mac); | |
1da177e4 | 2967 | |
c9df406f LB |
2968 | pd = pdev->dev.platform_data; |
2969 | if (pd == NULL) { | |
2970 | printk(KERN_ERR "No mv643xx_eth_platform_data\n"); | |
2971 | return -ENODEV; | |
2972 | } | |
1da177e4 | 2973 | |
c9df406f LB |
2974 | if (pd->shared == NULL) { |
2975 | printk(KERN_ERR "No mv643xx_eth_platform_data->shared\n"); | |
2976 | return -ENODEV; | |
2977 | } | |
8f518703 | 2978 | |
c9df406f LB |
2979 | dev = alloc_etherdev(sizeof(struct mv643xx_private)); |
2980 | if (!dev) | |
2981 | return -ENOMEM; | |
1da177e4 | 2982 | |
c9df406f | 2983 | platform_set_drvdata(pdev, dev); |
1da177e4 | 2984 | |
c9df406f LB |
2985 | mp = netdev_priv(dev); |
2986 | mp->dev = dev; | |
2987 | #ifdef MV643XX_NAPI | |
2988 | netif_napi_add(dev, &mp->napi, mv643xx_poll, 64); | |
2989 | #endif | |
1da177e4 | 2990 | |
c9df406f LB |
2991 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
2992 | BUG_ON(!res); | |
2993 | dev->irq = res->start; | |
1da177e4 | 2994 | |
c9df406f LB |
2995 | dev->open = mv643xx_eth_open; |
2996 | dev->stop = mv643xx_eth_stop; | |
2997 | dev->hard_start_xmit = mv643xx_eth_start_xmit; | |
2998 | dev->set_mac_address = mv643xx_eth_set_mac_address; | |
2999 | dev->set_multicast_list = mv643xx_eth_set_rx_mode; | |
3000 | ||
3001 | /* No need to Tx Timeout */ | |
3002 | dev->tx_timeout = mv643xx_eth_tx_timeout; | |
3003 | ||
3004 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
3005 | dev->poll_controller = mv643xx_netpoll; | |
3006 | #endif | |
3007 | ||
3008 | dev->watchdog_timeo = 2 * HZ; | |
3009 | dev->base_addr = 0; | |
3010 | dev->change_mtu = mv643xx_eth_change_mtu; | |
3011 | dev->do_ioctl = mv643xx_eth_do_ioctl; | |
3012 | SET_ETHTOOL_OPS(dev, &mv643xx_ethtool_ops); | |
1da177e4 | 3013 | |
c9df406f LB |
3014 | #ifdef MV643XX_CHECKSUM_OFFLOAD_TX |
3015 | #ifdef MAX_SKB_FRAGS | |
b4de9051 | 3016 | /* |
c9df406f LB |
3017 | * Zero copy can only work if we use Discovery II memory. Else, we will |
3018 | * have to map the buffers to ISA memory which is only 16 MB | |
b4de9051 | 3019 | */ |
c9df406f LB |
3020 | dev->features = NETIF_F_SG | NETIF_F_IP_CSUM; |
3021 | #endif | |
3022 | #endif | |
1da177e4 | 3023 | |
c9df406f LB |
3024 | /* Configure the timeout task */ |
3025 | INIT_WORK(&mp->tx_timeout_task, mv643xx_eth_tx_timeout_task); | |
1da177e4 | 3026 | |
c9df406f | 3027 | spin_lock_init(&mp->lock); |
1da177e4 | 3028 | |
c9df406f LB |
3029 | mp->shared = platform_get_drvdata(pd->shared); |
3030 | port_num = mp->port_num = pd->port_number; | |
8f518703 | 3031 | |
c9df406f LB |
3032 | if (mp->shared->win_protect) |
3033 | wrl(mp, WINDOW_PROTECT(port_num), mp->shared->win_protect); | |
1da177e4 | 3034 | |
c9df406f LB |
3035 | mp->shared_smi = mp->shared; |
3036 | if (pd->shared_smi != NULL) | |
3037 | mp->shared_smi = platform_get_drvdata(pd->shared_smi); | |
3038 | ||
3039 | /* set default config values */ | |
3040 | eth_port_uc_addr_get(mp, dev->dev_addr); | |
3041 | mp->rx_ring_size = PORT_DEFAULT_RECEIVE_QUEUE_SIZE; | |
3042 | mp->tx_ring_size = PORT_DEFAULT_TRANSMIT_QUEUE_SIZE; | |
3043 | ||
3044 | if (is_valid_ether_addr(pd->mac_addr)) | |
3045 | memcpy(dev->dev_addr, pd->mac_addr, 6); | |
3046 | ||
3047 | if (pd->phy_addr || pd->force_phy_addr) | |
3048 | ethernet_phy_set(mp, pd->phy_addr); | |
8f518703 | 3049 | |
c9df406f LB |
3050 | if (pd->rx_queue_size) |
3051 | mp->rx_ring_size = pd->rx_queue_size; | |
1da177e4 | 3052 | |
c9df406f LB |
3053 | if (pd->tx_queue_size) |
3054 | mp->tx_ring_size = pd->tx_queue_size; | |
1da177e4 | 3055 | |
c9df406f LB |
3056 | if (pd->tx_sram_size) { |
3057 | mp->tx_sram_size = pd->tx_sram_size; | |
3058 | mp->tx_sram_addr = pd->tx_sram_addr; | |
3059 | } | |
1da177e4 | 3060 | |
c9df406f LB |
3061 | if (pd->rx_sram_size) { |
3062 | mp->rx_sram_size = pd->rx_sram_size; | |
3063 | mp->rx_sram_addr = pd->rx_sram_addr; | |
3064 | } | |
1da177e4 | 3065 | |
c9df406f LB |
3066 | duplex = pd->duplex; |
3067 | speed = pd->speed; | |
1da177e4 | 3068 | |
c9df406f LB |
3069 | /* Hook up MII support for ethtool */ |
3070 | mp->mii.dev = dev; | |
3071 | mp->mii.mdio_read = mv643xx_mdio_read; | |
3072 | mp->mii.mdio_write = mv643xx_mdio_write; | |
3073 | mp->mii.phy_id = ethernet_phy_get(mp); | |
3074 | mp->mii.phy_id_mask = 0x3f; | |
3075 | mp->mii.reg_num_mask = 0x1f; | |
1da177e4 | 3076 | |
c9df406f LB |
3077 | err = ethernet_phy_detect(mp); |
3078 | if (err) { | |
3079 | pr_debug("%s: No PHY detected at addr %d\n", | |
3080 | dev->name, ethernet_phy_get(mp)); | |
3081 | goto out; | |
3082 | } | |
1da177e4 | 3083 | |
c9df406f LB |
3084 | ethernet_phy_reset(mp); |
3085 | mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii); | |
3086 | mv643xx_init_ethtool_cmd(dev, mp->mii.phy_id, speed, duplex, &cmd); | |
3087 | mv643xx_eth_update_pscr(dev, &cmd); | |
3088 | mv643xx_set_settings(dev, &cmd); | |
8f518703 | 3089 | |
c9df406f LB |
3090 | SET_NETDEV_DEV(dev, &pdev->dev); |
3091 | err = register_netdev(dev); | |
3092 | if (err) | |
3093 | goto out; | |
1da177e4 | 3094 | |
c9df406f LB |
3095 | p = dev->dev_addr; |
3096 | printk(KERN_NOTICE | |
3097 | "%s: port %d with MAC address %s\n", | |
3098 | dev->name, port_num, print_mac(mac, p)); | |
1da177e4 | 3099 | |
c9df406f LB |
3100 | if (dev->features & NETIF_F_SG) |
3101 | printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name); | |
1da177e4 | 3102 | |
c9df406f LB |
3103 | if (dev->features & NETIF_F_IP_CSUM) |
3104 | printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n", | |
3105 | dev->name); | |
1da177e4 | 3106 | |
c9df406f LB |
3107 | #ifdef MV643XX_CHECKSUM_OFFLOAD_TX |
3108 | printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name); | |
3109 | #endif | |
1da177e4 | 3110 | |
c9df406f LB |
3111 | #ifdef MV643XX_COAL |
3112 | printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n", | |
3113 | dev->name); | |
3114 | #endif | |
1da177e4 | 3115 | |
c9df406f LB |
3116 | #ifdef MV643XX_NAPI |
3117 | printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name); | |
3118 | #endif | |
1da177e4 | 3119 | |
c9df406f LB |
3120 | if (mp->tx_sram_size > 0) |
3121 | printk(KERN_NOTICE "%s: Using SRAM\n", dev->name); | |
1da177e4 | 3122 | |
c9df406f | 3123 | return 0; |
1da177e4 | 3124 | |
c9df406f LB |
3125 | out: |
3126 | free_netdev(dev); | |
1da177e4 | 3127 | |
c9df406f | 3128 | return err; |
1da177e4 LT |
3129 | } |
3130 | ||
c9df406f | 3131 | static int mv643xx_eth_remove(struct platform_device *pdev) |
1da177e4 | 3132 | { |
c9df406f | 3133 | struct net_device *dev = platform_get_drvdata(pdev); |
1da177e4 | 3134 | |
c9df406f LB |
3135 | unregister_netdev(dev); |
3136 | flush_scheduled_work(); | |
3137 | ||
3138 | free_netdev(dev); | |
3139 | platform_set_drvdata(pdev, NULL); | |
3140 | return 0; | |
1da177e4 LT |
3141 | } |
3142 | ||
c9df406f | 3143 | static void mv643xx_eth_shutdown(struct platform_device *pdev) |
d0412d96 | 3144 | { |
c9df406f | 3145 | struct net_device *dev = platform_get_drvdata(pdev); |
d0412d96 | 3146 | struct mv643xx_private *mp = netdev_priv(dev); |
c9df406f | 3147 | unsigned int port_num = mp->port_num; |
d0412d96 | 3148 | |
c9df406f LB |
3149 | /* Mask all interrupts on ethernet port */ |
3150 | wrl(mp, INTERRUPT_MASK_REG(port_num), 0); | |
3151 | rdl(mp, INTERRUPT_MASK_REG(port_num)); | |
3152 | ||
3153 | eth_port_reset(mp); | |
d0412d96 JC |
3154 | } |
3155 | ||
c9df406f LB |
3156 | static struct platform_driver mv643xx_eth_driver = { |
3157 | .probe = mv643xx_eth_probe, | |
3158 | .remove = mv643xx_eth_remove, | |
3159 | .shutdown = mv643xx_eth_shutdown, | |
3160 | .driver = { | |
3161 | .name = MV643XX_ETH_NAME, | |
3162 | .owner = THIS_MODULE, | |
3163 | }, | |
3164 | }; | |
3165 | ||
3166 | /* | |
3167 | * mv643xx_init_module | |
3168 | * | |
3169 | * Registers the network drivers into the Linux kernel | |
3170 | * | |
3171 | * Input : N/A | |
3172 | * | |
3173 | * Output : N/A | |
3174 | */ | |
3175 | static int __init mv643xx_init_module(void) | |
d0412d96 | 3176 | { |
c9df406f | 3177 | int rc; |
d0412d96 | 3178 | |
c9df406f LB |
3179 | rc = platform_driver_register(&mv643xx_eth_shared_driver); |
3180 | if (!rc) { | |
3181 | rc = platform_driver_register(&mv643xx_eth_driver); | |
3182 | if (rc) | |
3183 | platform_driver_unregister(&mv643xx_eth_shared_driver); | |
3184 | } | |
3185 | return rc; | |
d0412d96 JC |
3186 | } |
3187 | ||
c9df406f LB |
3188 | /* |
3189 | * mv643xx_cleanup_module | |
3190 | * | |
3191 | * Registers the network drivers into the Linux kernel | |
3192 | * | |
3193 | * Input : N/A | |
3194 | * | |
3195 | * Output : N/A | |
3196 | */ | |
3197 | static void __exit mv643xx_cleanup_module(void) | |
d0412d96 | 3198 | { |
c9df406f LB |
3199 | platform_driver_unregister(&mv643xx_eth_driver); |
3200 | platform_driver_unregister(&mv643xx_eth_shared_driver); | |
d0412d96 JC |
3201 | } |
3202 | ||
c9df406f LB |
3203 | module_init(mv643xx_init_module); |
3204 | module_exit(mv643xx_cleanup_module); | |
1da177e4 | 3205 | |
c9df406f LB |
3206 | MODULE_LICENSE("GPL"); |
3207 | MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani" | |
3208 | " and Dale Farnsworth"); | |
3209 | MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX"); | |
3210 | MODULE_ALIAS("platform:" MV643XX_ETH_NAME); | |
3211 | MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME); |