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[PATCH] mv643xx_eth: Make port queue enable/disable code consistent
[linux-2.6-block.git] / drivers / net / mv643xx_eth.c
CommitLineData
1da177e4
LT		 1/*
2 * drivers/net/mv643xx_eth.c - Driver for MV643XX ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 rabeeh@galileo.co.il
7 *
8 * Copyright (C) 2003 PMC-Sierra, Inc.,
3bb8a18a 9 * written by Manish Lachwani
1da177e4
LT		 10 *
11 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
12 *
13 * Copyright (C) 2004-2005 MontaVista Software, Inc.
14 * Dale Farnsworth <dale@farnsworth.org>
15 *
16 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
17 * <sjhill@realitydiluted.com>
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version 2
22 * of the License, or (at your option) any later version.
23 *
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
28 *
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
32 */
33#include <linux/init.h>
34#include <linux/dma-mapping.h>
35#include <linux/tcp.h>
36#include <linux/udp.h>
37#include <linux/etherdevice.h>
78a5e534
OH		 38#include <linux/in.h>
39#include <linux/ip.h>
1da177e4
LT		 40
41#include <linux/bitops.h>
42#include <linux/delay.h>
43#include <linux/ethtool.h>
d052d1be
RK		 44#include <linux/platform_device.h>
45
1da177e4
LT		 46#include <asm/io.h>
47#include <asm/types.h>
48#include <asm/pgtable.h>
49#include <asm/system.h>
50#include <asm/delay.h>
51#include "mv643xx_eth.h"
52
53/*
54 * The first part is the high level driver of the gigE ethernet ports.
55 */
56
57/* Constants */
58#define VLAN_HLEN 4
59#define FCS_LEN 4
b44cd572
DF		 60#define DMA_ALIGN 8 /* hw requires 8-byte alignment */
61#define HW_IP_ALIGN 2 /* hw aligns IP header */
62#define WRAP HW_IP_ALIGN + ETH_HLEN + VLAN_HLEN + FCS_LEN
1da177e4
LT		 63#define RX_SKB_SIZE ((dev->mtu + WRAP + 7) & ~0x7)
64
c2e5b352
DF		 65#define INT_UNMASK_ALL 0x0007ffff
66#define INT_UNMASK_ALL_EXT 0x0011ffff
67#define INT_MASK_ALL 0x00000000
68#define INT_MASK_ALL_EXT 0x00000000
1da177e4
LT		 69#define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL
70#define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT
1da177e4
LT		 71
72#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
73#define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
74#else
75#define MAX_DESCS_PER_SKB 1
76#endif
77
78#define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */
79#define PHY_WAIT_MICRO_SECONDS 10
80
81/* Static function declarations */
82static int eth_port_link_is_up(unsigned int eth_port_num);
83static void eth_port_uc_addr_get(struct net_device *dev,
84 unsigned char *MacAddr);
16e03018 85static void eth_port_set_multicast_list(struct net_device *);
9f8dd319
DF		 86static void mv643xx_eth_port_enable_tx(unsigned int port_num,
87 unsigned int channels);
88static void mv643xx_eth_port_enable_rx(unsigned int port_num,
89 unsigned int channels);
90static unsigned int mv643xx_eth_port_disable_tx(unsigned int port_num);
91static unsigned int mv643xx_eth_port_disable_rx(unsigned int port_num);
ab4384a6
DF		 92static int mv643xx_eth_open(struct net_device *);
93static int mv643xx_eth_stop(struct net_device *);
1da177e4
LT		 94static int mv643xx_eth_change_mtu(struct net_device *, int);
95static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *);
96static void eth_port_init_mac_tables(unsigned int eth_port_num);
97#ifdef MV643XX_NAPI
98static int mv643xx_poll(struct net_device *dev, int *budget);
99#endif
100static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
101static int ethernet_phy_detect(unsigned int eth_port_num);
102static struct ethtool_ops mv643xx_ethtool_ops;
103
104static char mv643xx_driver_name[] = "mv643xx_eth";
105static char mv643xx_driver_version[] = "1.0";
106
107static void __iomem *mv643xx_eth_shared_base;
108
109/* used to protect MV643XX_ETH_SMI_REG, which is shared across ports */
a9f6a0dd 110static DEFINE_SPINLOCK(mv643xx_eth_phy_lock);
1da177e4
LT		 111
112static inline u32 mv_read(int offset)
113{
dc074a8a 114 void __iomem *reg_base;
1da177e4
LT		 115
116 reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS;
117
118 return readl(reg_base + offset);
119}
120
121static inline void mv_write(int offset, u32 data)
122{
dc074a8a 123 void __iomem *reg_base;
1da177e4
LT		 124
125 reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS;
126 writel(data, reg_base + offset);
127}
128
129/*
130 * Changes MTU (maximum transfer unit) of the gigabit ethenret port
131 *
132 * Input : pointer to ethernet interface network device structure
133 * new mtu size
134 * Output : 0 upon success, -EINVAL upon failure
135 */
136static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
137{
8f518703 138 if ((new_mtu > 9500) || (new_mtu < 64))
1da177e4 139 return -EINVAL;
1da177e4
LT		 140
141 dev->mtu = new_mtu;
142 /*
143 * Stop then re-open the interface. This will allocate RX skb's with
144 * the new MTU.
145 * There is a possible danger that the open will not successed, due
146 * to memory is full, which might fail the open function.
147 */
148 if (netif_running(dev)) {
ab4384a6
DF		 149 mv643xx_eth_stop(dev);
150 if (mv643xx_eth_open(dev))
1da177e4
LT		 151 printk(KERN_ERR
152 "%s: Fatal error on opening device\n",
153 dev->name);
154 }
155
1da177e4
LT		 156 return 0;
157}
158
159/*
160 * mv643xx_eth_rx_task
161 *
162 * Fills / refills RX queue on a certain gigabit ethernet port
163 *
164 * Input : pointer to ethernet interface network device structure
165 * Output : N/A
166 */
167static void mv643xx_eth_rx_task(void *data)
168{
169 struct net_device *dev = (struct net_device *)data;
170 struct mv643xx_private *mp = netdev_priv(dev);
171 struct pkt_info pkt_info;
172 struct sk_buff *skb;
b44cd572 173 int unaligned;
1da177e4
LT		 174
175 if (test_and_set_bit(0, &mp->rx_task_busy))
176 panic("%s: Error in test_set_bit / clear_bit", dev->name);
177
f98e36f1 178 while (mp->rx_desc_count < (mp->rx_ring_size - 5)) {
b44cd572 179 skb = dev_alloc_skb(RX_SKB_SIZE + DMA_ALIGN);
1da177e4
LT		 180 if (!skb)
181 break;
f98e36f1 182 mp->rx_desc_count++;
b44cd572
DF		 183 unaligned = (u32)skb->data & (DMA_ALIGN - 1);
184 if (unaligned)
185 skb_reserve(skb, DMA_ALIGN - unaligned);
1da177e4
LT		 186 pkt_info.cmd_sts = ETH_RX_ENABLE_INTERRUPT;
187 pkt_info.byte_cnt = RX_SKB_SIZE;
188 pkt_info.buf_ptr = dma_map_single(NULL, skb->data, RX_SKB_SIZE,
189 DMA_FROM_DEVICE);
190 pkt_info.return_info = skb;
191 if (eth_rx_return_buff(mp, &pkt_info) != ETH_OK) {
192 printk(KERN_ERR
193 "%s: Error allocating RX Ring\n", dev->name);
194 break;
195 }
b44cd572 196 skb_reserve(skb, HW_IP_ALIGN);
1da177e4
LT		 197 }
198 clear_bit(0, &mp->rx_task_busy);
199 /*
200 * If RX ring is empty of SKB, set a timer to try allocating
201 * again in a later time .
202 */
f98e36f1 203 if ((mp->rx_desc_count == 0) && (mp->rx_timer_flag == 0)) {
1da177e4
LT		 204 printk(KERN_INFO "%s: Rx ring is empty\n", dev->name);
205 /* After 100mSec */
206 mp->timeout.expires = jiffies + (HZ / 10);
207 add_timer(&mp->timeout);
208 mp->rx_timer_flag = 1;
209 }
210#ifdef MV643XX_RX_QUEUE_FILL_ON_TASK
211 else {
212 /* Return interrupts */
213 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(mp->port_num),
c2e5b352 214 INT_UNMASK_ALL);
1da177e4
LT		 215 }
216#endif
217}
218
219/*
220 * mv643xx_eth_rx_task_timer_wrapper
221 *
222 * Timer routine to wake up RX queue filling task. This function is
223 * used only in case the RX queue is empty, and all alloc_skb has
224 * failed (due to out of memory event).
225 *
226 * Input : pointer to ethernet interface network device structure
227 * Output : N/A
228 */
229static void mv643xx_eth_rx_task_timer_wrapper(unsigned long data)
230{
231 struct net_device *dev = (struct net_device *)data;
232 struct mv643xx_private *mp = netdev_priv(dev);
233
234 mp->rx_timer_flag = 0;
235 mv643xx_eth_rx_task((void *)data);
236}
237
238/*
239 * mv643xx_eth_update_mac_address
240 *
241 * Update the MAC address of the port in the address table
242 *
243 * Input : pointer to ethernet interface network device structure
244 * Output : N/A
245 */
246static void mv643xx_eth_update_mac_address(struct net_device *dev)
247{
248 struct mv643xx_private *mp = netdev_priv(dev);
249 unsigned int port_num = mp->port_num;
250
251 eth_port_init_mac_tables(port_num);
ed9b5d45 252 eth_port_uc_addr_set(port_num, dev->dev_addr);
1da177e4
LT		 253}
254
255/*
256 * mv643xx_eth_set_rx_mode
257 *
258 * Change from promiscuos to regular rx mode
259 *
260 * Input : pointer to ethernet interface network device structure
261 * Output : N/A
262 */
263static void mv643xx_eth_set_rx_mode(struct net_device *dev)
264{
265 struct mv643xx_private *mp = netdev_priv(dev);
1da177e4 266
1da177e4 267 if (dev->flags & IFF_PROMISC)
7342cd81 268 mp->port_config |= (u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE;
1da177e4 269 else
7342cd81
DF		 270 mp->port_config &= ~(u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE;
271
272 mv_write(MV643XX_ETH_PORT_CONFIG_REG(mp->port_num), mp->port_config);
16e03018
DF		 273
274 eth_port_set_multicast_list(dev);
1da177e4
LT		 275}
276
277/*
278 * mv643xx_eth_set_mac_address
279 *
280 * Change the interface's mac address.
281 * No special hardware thing should be done because interface is always
282 * put in promiscuous mode.
283 *
284 * Input : pointer to ethernet interface network device structure and
285 * a pointer to the designated entry to be added to the cache.
286 * Output : zero upon success, negative upon failure
287 */
288static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
289{
290 int i;
291
292 for (i = 0; i < 6; i++)
293 /* +2 is for the offset of the HW addr type */
294 dev->dev_addr[i] = ((unsigned char *)addr)[i + 2];
295 mv643xx_eth_update_mac_address(dev);
296 return 0;
297}
298
299/*
300 * mv643xx_eth_tx_timeout
301 *
302 * Called upon a timeout on transmitting a packet
303 *
304 * Input : pointer to ethernet interface network device structure.
305 * Output : N/A
306 */
307static void mv643xx_eth_tx_timeout(struct net_device *dev)
308{
309 struct mv643xx_private *mp = netdev_priv(dev);
310
311 printk(KERN_INFO "%s: TX timeout ", dev->name);
312
313 /* Do the reset outside of interrupt context */
314 schedule_work(&mp->tx_timeout_task);
315}
316
317/*
318 * mv643xx_eth_tx_timeout_task
319 *
320 * Actual routine to reset the adapter when a timeout on Tx has occurred
321 */
322static void mv643xx_eth_tx_timeout_task(struct net_device *dev)
323{
324 struct mv643xx_private *mp = netdev_priv(dev);
325
326 netif_device_detach(dev);
327 eth_port_reset(mp->port_num);
ed9b5d45 328 eth_port_start(dev);
1da177e4
LT		 329 netif_device_attach(dev);
330}
331
332/*
333 * mv643xx_eth_free_tx_queue
334 *
335 * Input : dev - a pointer to the required interface
336 *
337 * Output : 0 if was able to release skb , nonzero otherwise
338 */
339static int mv643xx_eth_free_tx_queue(struct net_device *dev,
340 unsigned int eth_int_cause_ext)
341{
342 struct mv643xx_private *mp = netdev_priv(dev);
343 struct net_device_stats *stats = &mp->stats;
344 struct pkt_info pkt_info;
345 int released = 1;
346
347 if (!(eth_int_cause_ext & (BIT0 | BIT8)))
348 return released;
349
1da177e4
LT		 350 /* Check only queue 0 */
351 while (eth_tx_return_desc(mp, &pkt_info) == ETH_OK) {
352 if (pkt_info.cmd_sts & BIT0) {
353 printk("%s: Error in TX\n", dev->name);
354 stats->tx_errors++;
355 }
356
cb415d30
PG		 357 if (pkt_info.cmd_sts & ETH_TX_FIRST_DESC)
358 dma_unmap_single(NULL, pkt_info.buf_ptr,
359 pkt_info.byte_cnt,
360 DMA_TO_DEVICE);
361 else
362 dma_unmap_page(NULL, pkt_info.buf_ptr,
363 pkt_info.byte_cnt,
364 DMA_TO_DEVICE);
1da177e4 365
cb415d30 366 if (pkt_info.return_info) {
1da177e4
LT		 367 dev_kfree_skb_irq(pkt_info.return_info);
368 released = 0;
cb415d30 369 }
1da177e4
LT		 370 }
371
1da177e4
LT		 372 return released;
373}
374
375/*
376 * mv643xx_eth_receive
377 *
378 * This function is forward packets that are received from the port's
379 * queues toward kernel core or FastRoute them to another interface.
380 *
381 * Input : dev - a pointer to the required interface
382 * max - maximum number to receive (0 means unlimted)
383 *
384 * Output : number of served packets
385 */
386#ifdef MV643XX_NAPI
387static int mv643xx_eth_receive_queue(struct net_device *dev, int budget)
388#else
389static int mv643xx_eth_receive_queue(struct net_device *dev)
390#endif
391{
392 struct mv643xx_private *mp = netdev_priv(dev);
393 struct net_device_stats *stats = &mp->stats;
394 unsigned int received_packets = 0;
395 struct sk_buff *skb;
396 struct pkt_info pkt_info;
397
398#ifdef MV643XX_NAPI
b1dd9ca1 399 while (budget-- > 0 && eth_port_receive(mp, &pkt_info) == ETH_OK) {
1da177e4
LT		 400#else
401 while (eth_port_receive(mp, &pkt_info) == ETH_OK) {
402#endif
f98e36f1 403 mp->rx_desc_count--;
1da177e4 404 received_packets++;
b1dd9ca1 405
1da177e4
LT		 406 /* Update statistics. Note byte count includes 4 byte CRC count */
407 stats->rx_packets++;
408 stats->rx_bytes += pkt_info.byte_cnt;
409 skb = pkt_info.return_info;
410 /*
411 * In case received a packet without first / last bits on OR
412 * the error summary bit is on, the packets needs to be dropeed.
413 */
414 if (((pkt_info.cmd_sts
415 & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
416 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
417 || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
418 stats->rx_dropped++;
419 if ((pkt_info.cmd_sts & (ETH_RX_FIRST_DESC |
420 ETH_RX_LAST_DESC)) !=
421 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) {
422 if (net_ratelimit())
423 printk(KERN_ERR
424 "%s: Received packet spread "
425 "on multiple descriptors\n",
426 dev->name);
427 }
428 if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)
429 stats->rx_errors++;
430
431 dev_kfree_skb_irq(skb);
432 } else {
433 /*
434 * The -4 is for the CRC in the trailer of the
435 * received packet
436 */
437 skb_put(skb, pkt_info.byte_cnt - 4);
438 skb->dev = dev;
439
440 if (pkt_info.cmd_sts & ETH_LAYER_4_CHECKSUM_OK) {
441 skb->ip_summed = CHECKSUM_UNNECESSARY;
442 skb->csum = htons(
443 (pkt_info.cmd_sts & 0x0007fff8) >> 3);
444 }
445 skb->protocol = eth_type_trans(skb, dev);
446#ifdef MV643XX_NAPI
447 netif_receive_skb(skb);
448#else
449 netif_rx(skb);
450#endif
451 }
12ad74f8 452 dev->last_rx = jiffies;
1da177e4
LT		 453 }
454
455 return received_packets;
456}
457
458/*
459 * mv643xx_eth_int_handler
460 *
461 * Main interrupt handler for the gigbit ethernet ports
462 *
463 * Input : irq - irq number (not used)
464 * dev_id - a pointer to the required interface's data structure
465 * regs - not used
466 * Output : N/A
467 */
468
469static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id,
b4de9051 470 struct pt_regs *regs)
1da177e4
LT		 471{
472 struct net_device *dev = (struct net_device *)dev_id;
473 struct mv643xx_private *mp = netdev_priv(dev);
474 u32 eth_int_cause, eth_int_cause_ext = 0;
475 unsigned int port_num = mp->port_num;
476
477 /* Read interrupt cause registers */
478 eth_int_cause = mv_read(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num)) &
c2e5b352 479 INT_UNMASK_ALL;
1da177e4
LT		 480
481 if (eth_int_cause & BIT1)
482 eth_int_cause_ext = mv_read(
483 MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num)) &
c2e5b352 484 INT_UNMASK_ALL_EXT;
1da177e4
LT		 485
486#ifdef MV643XX_NAPI
487 if (!(eth_int_cause & 0x0007fffd)) {
488 /* Dont ack the Rx interrupt */
489#endif
490 /*
491 * Clear specific ethernet port intrerrupt registers by
492 * acknowleding relevant bits.
493 */
494 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num),
495 ~eth_int_cause);
496 if (eth_int_cause_ext != 0x0)
497 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG
498 (port_num), ~eth_int_cause_ext);
499
500 /* UDP change : We may need this */
501 if ((eth_int_cause_ext & 0x0000ffff) &&
502 (mv643xx_eth_free_tx_queue(dev, eth_int_cause_ext) == 0) &&
f98e36f1 503 (mp->tx_ring_size > mp->tx_desc_count + MAX_DESCS_PER_SKB))
1da177e4
LT		 504 netif_wake_queue(dev);
505#ifdef MV643XX_NAPI
506 } else {
507 if (netif_rx_schedule_prep(dev)) {
508 /* Mask all the interrupts */
c2e5b352
DF		 509 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
510 INT_MASK_ALL);
511 /* wait for previous write to complete */
512 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
1da177e4
LT		 513 __netif_rx_schedule(dev);
514 }
515#else
516 if (eth_int_cause & (BIT2 | BIT11))
517 mv643xx_eth_receive_queue(dev, 0);
518
519 /*
520 * After forwarded received packets to upper layer, add a task
521 * in an interrupts enabled context that refills the RX ring
522 * with skb's.
523 */
524#ifdef MV643XX_RX_QUEUE_FILL_ON_TASK
c2e5b352 525 /* Mask all interrupts on ethernet port */
1da177e4 526 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
c2e5b352 527 INT_MASK_ALL);
8f518703
DF		 528 /* wait for previous write to take effect */
529 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
530
1da177e4
LT		 531 queue_task(&mp->rx_task, &tq_immediate);
532 mark_bh(IMMEDIATE_BH);
533#else
534 mp->rx_task.func(dev);
535#endif
536#endif
537 }
538 /* PHY status changed */
539 if (eth_int_cause_ext & (BIT16 | BIT20)) {
540 if (eth_port_link_is_up(port_num)) {
541 netif_carrier_on(dev);
542 netif_wake_queue(dev);
543 /* Start TX queue */
9f8dd319 544 mv643xx_eth_port_enable_tx(port_num, mp->port_tx_queue_command);
1da177e4
LT		 545 } else {
546 netif_carrier_off(dev);
547 netif_stop_queue(dev);
548 }
549 }
550
551 /*
552 * If no real interrupt occured, exit.
553 * This can happen when using gigE interrupt coalescing mechanism.
554 */
555 if ((eth_int_cause == 0x0) && (eth_int_cause_ext == 0x0))
556 return IRQ_NONE;
557
558 return IRQ_HANDLED;
559}
560
561#ifdef MV643XX_COAL
562
563/*
564 * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
565 *
566 * DESCRIPTION:
567 * This routine sets the RX coalescing interrupt mechanism parameter.
568 * This parameter is a timeout counter, that counts in 64 t_clk
569 * chunks ; that when timeout event occurs a maskable interrupt
570 * occurs.
571 * The parameter is calculated using the tClk of the MV-643xx chip
572 * , and the required delay of the interrupt in usec.
573 *
574 * INPUT:
575 * unsigned int eth_port_num Ethernet port number
576 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
577 * unsigned int delay Delay in usec
578 *
579 * OUTPUT:
580 * Interrupt coalescing mechanism value is set in MV-643xx chip.
581 *
582 * RETURN:
583 * The interrupt coalescing value set in the gigE port.
584 *
585 */
586static unsigned int eth_port_set_rx_coal(unsigned int eth_port_num,
587 unsigned int t_clk, unsigned int delay)
588{
589 unsigned int coal = ((t_clk / 1000000) * delay) / 64;
590
591 /* Set RX Coalescing mechanism */
592 mv_write(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num),
593 ((coal & 0x3fff) << 8) |
594 (mv_read(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num))
595 & 0xffc000ff));
596
597 return coal;
598}
599#endif
600
601/*
602 * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
603 *
604 * DESCRIPTION:
605 * This routine sets the TX coalescing interrupt mechanism parameter.
606 * This parameter is a timeout counter, that counts in 64 t_clk
607 * chunks ; that when timeout event occurs a maskable interrupt
608 * occurs.
609 * The parameter is calculated using the t_cLK frequency of the
610 * MV-643xx chip and the required delay in the interrupt in uSec
611 *
612 * INPUT:
613 * unsigned int eth_port_num Ethernet port number
614 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
615 * unsigned int delay Delay in uSeconds
616 *
617 * OUTPUT:
618 * Interrupt coalescing mechanism value is set in MV-643xx chip.
619 *
620 * RETURN:
621 * The interrupt coalescing value set in the gigE port.
622 *
623 */
624static unsigned int eth_port_set_tx_coal(unsigned int eth_port_num,
625 unsigned int t_clk, unsigned int delay)
626{
627 unsigned int coal;
628 coal = ((t_clk / 1000000) * delay) / 64;
629 /* Set TX Coalescing mechanism */
630 mv_write(MV643XX_ETH_TX_FIFO_URGENT_THRESHOLD_REG(eth_port_num),
631 coal << 4);
632 return coal;
633}
634
1da177e4
LT		 635/*
636 * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
637 *
638 * DESCRIPTION:
639 * This function prepares a Rx chained list of descriptors and packet
640 * buffers in a form of a ring. The routine must be called after port
641 * initialization routine and before port start routine.
642 * The Ethernet SDMA engine uses CPU bus addresses to access the various
643 * devices in the system (i.e. DRAM). This function uses the ethernet
644 * struct 'virtual to physical' routine (set by the user) to set the ring
645 * with physical addresses.
646 *
647 * INPUT:
648 * struct mv643xx_private *mp Ethernet Port Control srtuct.
649 *
650 * OUTPUT:
651 * The routine updates the Ethernet port control struct with information
652 * regarding the Rx descriptors and buffers.
653 *
654 * RETURN:
655 * None.
656 */
657static void ether_init_rx_desc_ring(struct mv643xx_private *mp)
658{
659 volatile struct eth_rx_desc *p_rx_desc;
660 int rx_desc_num = mp->rx_ring_size;
661 int i;
662
663 /* initialize the next_desc_ptr links in the Rx descriptors ring */
664 p_rx_desc = (struct eth_rx_desc *)mp->p_rx_desc_area;
665 for (i = 0; i < rx_desc_num; i++) {
666 p_rx_desc[i].next_desc_ptr = mp->rx_desc_dma +
667 ((i + 1) % rx_desc_num) * sizeof(struct eth_rx_desc);
668 }
669
670 /* Save Rx desc pointer to driver struct. */
671 mp->rx_curr_desc_q = 0;
672 mp->rx_used_desc_q = 0;
673
674 mp->rx_desc_area_size = rx_desc_num * sizeof(struct eth_rx_desc);
675
9f8dd319
DF		 676 /* Enable queue 0 for this port */
677 mp->port_rx_queue_command = 1;
1da177e4
LT		 678}
679
680/*
681 * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
682 *
683 * DESCRIPTION:
684 * This function prepares a Tx chained list of descriptors and packet
685 * buffers in a form of a ring. The routine must be called after port
686 * initialization routine and before port start routine.
687 * The Ethernet SDMA engine uses CPU bus addresses to access the various
688 * devices in the system (i.e. DRAM). This function uses the ethernet
689 * struct 'virtual to physical' routine (set by the user) to set the ring
690 * with physical addresses.
691 *
692 * INPUT:
693 * struct mv643xx_private *mp Ethernet Port Control srtuct.
694 *
695 * OUTPUT:
696 * The routine updates the Ethernet port control struct with information
697 * regarding the Tx descriptors and buffers.
698 *
699 * RETURN:
700 * None.
701 */
702static void ether_init_tx_desc_ring(struct mv643xx_private *mp)
703{
704 int tx_desc_num = mp->tx_ring_size;
705 struct eth_tx_desc *p_tx_desc;
706 int i;
707
708 /* Initialize the next_desc_ptr links in the Tx descriptors ring */
709 p_tx_desc = (struct eth_tx_desc *)mp->p_tx_desc_area;
710 for (i = 0; i < tx_desc_num; i++) {
711 p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma +
712 ((i + 1) % tx_desc_num) * sizeof(struct eth_tx_desc);
713 }
714
715 mp->tx_curr_desc_q = 0;
716 mp->tx_used_desc_q = 0;
717#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
718 mp->tx_first_desc_q = 0;
719#endif
720
721 mp->tx_desc_area_size = tx_desc_num * sizeof(struct eth_tx_desc);
722
9f8dd319
DF		 723 /* Enable queue 0 for this port */
724 mp->port_tx_queue_command = 1;
1da177e4
LT		 725}
726
ab4384a6
DF		 727/*
728 * mv643xx_eth_open
729 *
730 * This function is called when openning the network device. The function
731 * should initialize all the hardware, initialize cyclic Rx/Tx
732 * descriptors chain and buffers and allocate an IRQ to the network
733 * device.
734 *
735 * Input : a pointer to the network device structure
736 *
737 * Output : zero of success , nonzero if fails.
738 */
739
740static int mv643xx_eth_open(struct net_device *dev)
1da177e4
LT		 741{
742 struct mv643xx_private *mp = netdev_priv(dev);
743 unsigned int port_num = mp->port_num;
744 unsigned int size;
ab4384a6
DF		 745 int err;
746
747 err = request_irq(dev->irq, mv643xx_eth_int_handler,
748 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
749 if (err) {
750 printk(KERN_ERR "Can not assign IRQ number to MV643XX_eth%d\n",
751 port_num);
752 return -EAGAIN;
753 }
1da177e4 754
1da177e4
LT		 755 eth_port_init(mp);
756
757 INIT_WORK(&mp->rx_task, (void (*)(void *))mv643xx_eth_rx_task, dev);
758
759 memset(&mp->timeout, 0, sizeof(struct timer_list));
760 mp->timeout.function = mv643xx_eth_rx_task_timer_wrapper;
761 mp->timeout.data = (unsigned long)dev;
762
763 mp->rx_task_busy = 0;
764 mp->rx_timer_flag = 0;
765
766 /* Allocate RX and TX skb rings */
767 mp->rx_skb = kmalloc(sizeof(*mp->rx_skb) * mp->rx_ring_size,
768 GFP_KERNEL);
769 if (!mp->rx_skb) {
770 printk(KERN_ERR "%s: Cannot allocate Rx skb ring\n", dev->name);
ab4384a6
DF		 771 err = -ENOMEM;
772 goto out_free_irq;
1da177e4
LT		 773 }
774 mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size,
775 GFP_KERNEL);
776 if (!mp->tx_skb) {
777 printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name);
ab4384a6
DF		 778 err = -ENOMEM;
779 goto out_free_rx_skb;
1da177e4
LT		 780 }
781
782 /* Allocate TX ring */
f98e36f1 783 mp->tx_desc_count = 0;
1da177e4
LT		 784 size = mp->tx_ring_size * sizeof(struct eth_tx_desc);
785 mp->tx_desc_area_size = size;
786
787 if (mp->tx_sram_size) {
788 mp->p_tx_desc_area = ioremap(mp->tx_sram_addr,
789 mp->tx_sram_size);
790 mp->tx_desc_dma = mp->tx_sram_addr;
791 } else
792 mp->p_tx_desc_area = dma_alloc_coherent(NULL, size,
793 &mp->tx_desc_dma,
794 GFP_KERNEL);
795
796 if (!mp->p_tx_desc_area) {
797 printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n",
798 dev->name, size);
ab4384a6
DF		 799 err = -ENOMEM;
800 goto out_free_tx_skb;
1da177e4
LT		 801 }
802 BUG_ON((u32) mp->p_tx_desc_area & 0xf); /* check 16-byte alignment */
803 memset((void *)mp->p_tx_desc_area, 0, mp->tx_desc_area_size);
804
805 ether_init_tx_desc_ring(mp);
806
807 /* Allocate RX ring */
f98e36f1 808 mp->rx_desc_count = 0;
1da177e4
LT		 809 size = mp->rx_ring_size * sizeof(struct eth_rx_desc);
810 mp->rx_desc_area_size = size;
811
812 if (mp->rx_sram_size) {
813 mp->p_rx_desc_area = ioremap(mp->rx_sram_addr,
814 mp->rx_sram_size);
815 mp->rx_desc_dma = mp->rx_sram_addr;
816 } else
817 mp->p_rx_desc_area = dma_alloc_coherent(NULL, size,
818 &mp->rx_desc_dma,
819 GFP_KERNEL);
820
821 if (!mp->p_rx_desc_area) {
822 printk(KERN_ERR "%s: Cannot allocate Rx ring (size %d bytes)\n",
823 dev->name, size);
824 printk(KERN_ERR "%s: Freeing previously allocated TX queues...",
825 dev->name);
826 if (mp->rx_sram_size)
dd09b1de 827 iounmap(mp->p_tx_desc_area);
1da177e4
LT		 828 else
829 dma_free_coherent(NULL, mp->tx_desc_area_size,
830 mp->p_tx_desc_area, mp->tx_desc_dma);
ab4384a6
DF		 831 err = -ENOMEM;
832 goto out_free_tx_skb;
1da177e4
LT		 833 }
834 memset((void *)mp->p_rx_desc_area, 0, size);
835
836 ether_init_rx_desc_ring(mp);
837
838 mv643xx_eth_rx_task(dev); /* Fill RX ring with skb's */
839
ed9b5d45 840 eth_port_start(dev);
1da177e4
LT		 841
842 /* Interrupt Coalescing */
843
844#ifdef MV643XX_COAL
845 mp->rx_int_coal =
846 eth_port_set_rx_coal(port_num, 133000000, MV643XX_RX_COAL);
847#endif
848
849 mp->tx_int_coal =
850 eth_port_set_tx_coal(port_num, 133000000, MV643XX_TX_COAL);
851
8f518703
DF		 852 /* Clear any pending ethernet port interrupts */
853 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
854 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
855
856 /* Unmask phy and link status changes interrupts */
857 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
c2e5b352 858 INT_UNMASK_ALL_EXT);
1da177e4 859
8f518703 860 /* Unmask RX buffer and TX end interrupt */
c2e5b352 861 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), INT_UNMASK_ALL);
1da177e4 862 return 0;
ab4384a6
DF		 863
864out_free_tx_skb:
865 kfree(mp->tx_skb);
866out_free_rx_skb:
867 kfree(mp->rx_skb);
868out_free_irq:
869 free_irq(dev->irq, dev);
870
871 return err;
1da177e4
LT		 872}
873
874static void mv643xx_eth_free_tx_rings(struct net_device *dev)
875{
876 struct mv643xx_private *mp = netdev_priv(dev);
877 unsigned int port_num = mp->port_num;
878 unsigned int curr;
4476e0e4 879 struct sk_buff *skb;
1da177e4
LT		 880
881 /* Stop Tx Queues */
9f8dd319 882 mv643xx_eth_port_disable_tx(port_num);
1da177e4
LT		 883
884 /* Free outstanding skb's on TX rings */
f98e36f1 885 for (curr = 0; mp->tx_desc_count && curr < mp->tx_ring_size; curr++) {
4476e0e4
DF		 886 skb = mp->tx_skb[curr];
887 if (skb) {
f98e36f1 888 mp->tx_desc_count -= skb_shinfo(skb)->nr_frags;
4476e0e4 889 dev_kfree_skb(skb);
f98e36f1 890 mp->tx_desc_count--;
1da177e4
LT		 891 }
892 }
f98e36f1 893 if (mp->tx_desc_count)
1da177e4 894 printk("%s: Error on Tx descriptor free - could not free %d"
f98e36f1 895 " descriptors\n", dev->name, mp->tx_desc_count);
1da177e4
LT		 896
897 /* Free TX ring */
898 if (mp->tx_sram_size)
899 iounmap(mp->p_tx_desc_area);
900 else
901 dma_free_coherent(NULL, mp->tx_desc_area_size,
902 mp->p_tx_desc_area, mp->tx_desc_dma);
903}
904
905static void mv643xx_eth_free_rx_rings(struct net_device *dev)
906{
907 struct mv643xx_private *mp = netdev_priv(dev);
908 unsigned int port_num = mp->port_num;
909 int curr;
910
911 /* Stop RX Queues */
9f8dd319 912 mv643xx_eth_port_disable_rx(port_num);
1da177e4
LT		 913
914 /* Free preallocated skb's on RX rings */
f98e36f1 915 for (curr = 0; mp->rx_desc_count && curr < mp->rx_ring_size; curr++) {
1da177e4
LT		 916 if (mp->rx_skb[curr]) {
917 dev_kfree_skb(mp->rx_skb[curr]);
f98e36f1 918 mp->rx_desc_count--;
1da177e4
LT		 919 }
920 }
921
f98e36f1 922 if (mp->rx_desc_count)
1da177e4
LT		 923 printk(KERN_ERR
924 "%s: Error in freeing Rx Ring. %d skb's still"
925 " stuck in RX Ring - ignoring them\n", dev->name,
f98e36f1 926 mp->rx_desc_count);
1da177e4
LT		 927 /* Free RX ring */
928 if (mp->rx_sram_size)
929 iounmap(mp->p_rx_desc_area);
930 else
931 dma_free_coherent(NULL, mp->rx_desc_area_size,
932 mp->p_rx_desc_area, mp->rx_desc_dma);
933}
934
935/*
936 * mv643xx_eth_stop
937 *
938 * This function is used when closing the network device.
939 * It updates the hardware,
940 * release all memory that holds buffers and descriptors and release the IRQ.
941 * Input : a pointer to the device structure
942 * Output : zero if success , nonzero if fails
943 */
944
ab4384a6 945static int mv643xx_eth_stop(struct net_device *dev)
1da177e4
LT		 946{
947 struct mv643xx_private *mp = netdev_priv(dev);
948 unsigned int port_num = mp->port_num;
949
c2e5b352
DF		 950 /* Mask all interrupts on ethernet port */
951 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), INT_MASK_ALL);
952 /* wait for previous write to complete */
8f518703
DF		 953 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
954
955#ifdef MV643XX_NAPI
956 netif_poll_disable(dev);
957#endif
1da177e4
LT		 958 netif_carrier_off(dev);
959 netif_stop_queue(dev);
960
1da177e4
LT		 961 eth_port_reset(mp->port_num);
962
8f518703
DF		 963 mv643xx_eth_free_tx_rings(dev);
964 mv643xx_eth_free_rx_rings(dev);
1da177e4 965
8f518703
DF		 966#ifdef MV643XX_NAPI
967 netif_poll_enable(dev);
968#endif
1da177e4 969
1da177e4 970 free_irq(dev->irq, dev);
1da177e4
LT		 971
972 return 0;
973}
974
975#ifdef MV643XX_NAPI
976static void mv643xx_tx(struct net_device *dev)
977{
978 struct mv643xx_private *mp = netdev_priv(dev);
979 struct pkt_info pkt_info;
980
981 while (eth_tx_return_desc(mp, &pkt_info) == ETH_OK) {
cb415d30
PG		 982 if (pkt_info.cmd_sts & ETH_TX_FIRST_DESC)
983 dma_unmap_single(NULL, pkt_info.buf_ptr,
984 pkt_info.byte_cnt,
985 DMA_TO_DEVICE);
986 else
987 dma_unmap_page(NULL, pkt_info.buf_ptr,
988 pkt_info.byte_cnt,
989 DMA_TO_DEVICE);
1da177e4 990
cb415d30 991 if (pkt_info.return_info)
1da177e4 992 dev_kfree_skb_irq(pkt_info.return_info);
1da177e4
LT		 993 }
994
995 if (netif_queue_stopped(dev) &&
f98e36f1
DF		 996 mp->tx_ring_size >
997 mp->tx_desc_count + MAX_DESCS_PER_SKB)
1da177e4
LT		 998 netif_wake_queue(dev);
999}
1000
1001/*
1002 * mv643xx_poll
1003 *
1004 * This function is used in case of NAPI
1005 */
1006static int mv643xx_poll(struct net_device *dev, int *budget)
1007{
1008 struct mv643xx_private *mp = netdev_priv(dev);
1009 int done = 1, orig_budget, work_done;
1010 unsigned int port_num = mp->port_num;
1da177e4
LT		 1011
1012#ifdef MV643XX_TX_FAST_REFILL
1013 if (++mp->tx_clean_threshold > 5) {
1da177e4
LT		 1014 mv643xx_tx(dev);
1015 mp->tx_clean_threshold = 0;
1da177e4
LT		 1016 }
1017#endif
1018
1019 if ((mv_read(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num)))
1020 != (u32) mp->rx_used_desc_q) {
1021 orig_budget = *budget;
1022 if (orig_budget > dev->quota)
1023 orig_budget = dev->quota;
1024 work_done = mv643xx_eth_receive_queue(dev, orig_budget);
1025 mp->rx_task.func(dev);
1026 *budget -= work_done;
1027 dev->quota -= work_done;
1028 if (work_done >= orig_budget)
1029 done = 0;
1030 }
1031
1032 if (done) {
8f518703 1033 netif_rx_complete(dev);
1da177e4
LT		 1034 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
1035 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
1036 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
c2e5b352 1037 INT_UNMASK_ALL);
1da177e4
LT		 1038 }
1039
1040 return done ? 0 : 1;
1041}
1042#endif
1043
f7ea3337
PJ		 1044/* Hardware can't handle unaligned fragments smaller than 9 bytes.
1045 * This helper function detects that case.
1046 */
1047
1048static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1049{
b4de9051
DF		 1050 unsigned int frag;
1051 skb_frag_t *fragp;
f7ea3337 1052
b4de9051
DF		 1053 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1054 fragp = &skb_shinfo(skb)->frags[frag];
1055 if (fragp->size <= 8 && fragp->page_offset & 0x7)
1056 return 1;
1057 }
1058 return 0;
f7ea3337
PJ		 1059}
1060
1061
1da177e4
LT		 1062/*
1063 * mv643xx_eth_start_xmit
1064 *
1065 * This function is queues a packet in the Tx descriptor for
1066 * required port.
1067 *
1068 * Input : skb - a pointer to socket buffer
1069 * dev - a pointer to the required port
1070 *
1071 * Output : zero upon success
1072 */
1073static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
1074{
1075 struct mv643xx_private *mp = netdev_priv(dev);
1076 struct net_device_stats *stats = &mp->stats;
1077 ETH_FUNC_RET_STATUS status;
1078 unsigned long flags;
1079 struct pkt_info pkt_info;
1080
1081 if (netif_queue_stopped(dev)) {
1082 printk(KERN_ERR
1083 "%s: Tried sending packet when interface is stopped\n",
1084 dev->name);
1085 return 1;
1086 }
1087
1088 /* This is a hard error, log it. */
f98e36f1 1089 if ((mp->tx_ring_size - mp->tx_desc_count) <=
1da177e4
LT		 1090 (skb_shinfo(skb)->nr_frags + 1)) {
1091 netif_stop_queue(dev);
1092 printk(KERN_ERR
1093 "%s: Bug in mv643xx_eth - Trying to transmit when"
1094 " queue full !\n", dev->name);
1095 return 1;
1096 }
1097
1098 /* Paranoid check - this shouldn't happen */
1099 if (skb == NULL) {
1100 stats->tx_dropped++;
1101 printk(KERN_ERR "mv64320_eth paranoid check failed\n");
1102 return 1;
1103 }
1104
f7ea3337
PJ		 1105#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1106 if (has_tiny_unaligned_frags(skb)) {
1107 if ((skb_linearize(skb, GFP_ATOMIC) != 0)) {
1108 stats->tx_dropped++;
1109 printk(KERN_DEBUG "%s: failed to linearize tiny "
1110 "unaligned fragment\n", dev->name);
1111 return 1;
1112 }
1113 }
1114
1da177e4
LT		 1115 spin_lock_irqsave(&mp->lock, flags);
1116
1da177e4 1117 if (!skb_shinfo(skb)->nr_frags) {
1da177e4 1118 if (skb->ip_summed != CHECKSUM_HW) {
26006360 1119 /* Errata BTS #50, IHL must be 5 if no HW checksum */
1da177e4 1120 pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT |
26006360
DF		 1121 ETH_TX_FIRST_DESC |
1122 ETH_TX_LAST_DESC |
1123 5 << ETH_TX_IHL_SHIFT;
1da177e4
LT		 1124 pkt_info.l4i_chk = 0;
1125 } else {
1da177e4 1126 pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT |
26006360
DF		 1127 ETH_TX_FIRST_DESC |
1128 ETH_TX_LAST_DESC |
1129 ETH_GEN_TCP_UDP_CHECKSUM |
1130 ETH_GEN_IP_V_4_CHECKSUM |
1131 skb->nh.iph->ihl << ETH_TX_IHL_SHIFT;
1da177e4 1132 /* CPU already calculated pseudo header checksum. */
63890576
WJ		 1133 if ((skb->protocol == ETH_P_IP) &&
1134 (skb->nh.iph->protocol == IPPROTO_UDP) ) {
1da177e4
LT		 1135 pkt_info.cmd_sts |= ETH_UDP_FRAME;
1136 pkt_info.l4i_chk = skb->h.uh->check;
63890576
WJ		 1137 } else if ((skb->protocol == ETH_P_IP) &&
1138 (skb->nh.iph->protocol == IPPROTO_TCP))
1da177e4
LT		 1139 pkt_info.l4i_chk = skb->h.th->check;
1140 else {
1141 printk(KERN_ERR
63890576 1142 "%s: chksum proto != IPv4 TCP or UDP\n",
1da177e4
LT		 1143 dev->name);
1144 spin_unlock_irqrestore(&mp->lock, flags);
1145 return 1;
1146 }
1147 }
1148 pkt_info.byte_cnt = skb->len;
1149 pkt_info.buf_ptr = dma_map_single(NULL, skb->data, skb->len,
1150 DMA_TO_DEVICE);
1151 pkt_info.return_info = skb;
1da177e4
LT		 1152 status = eth_port_send(mp, &pkt_info);
1153 if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL))
1154 printk(KERN_ERR "%s: Error on transmitting packet\n",
1155 dev->name);
1156 stats->tx_bytes += pkt_info.byte_cnt;
1157 } else {
1158 unsigned int frag;
1da177e4 1159
1da177e4
LT		 1160 /* first frag which is skb header */
1161 pkt_info.byte_cnt = skb_headlen(skb);
1162 pkt_info.buf_ptr = dma_map_single(NULL, skb->data,
1163 skb_headlen(skb),
1164 DMA_TO_DEVICE);
1165 pkt_info.l4i_chk = 0;
1166 pkt_info.return_info = 0;
1da177e4 1167
26006360
DF		 1168 if (skb->ip_summed != CHECKSUM_HW)
1169 /* Errata BTS #50, IHL must be 5 if no HW checksum */
1170 pkt_info.cmd_sts = ETH_TX_FIRST_DESC |
1171 5 << ETH_TX_IHL_SHIFT;
1172 else {
1173 pkt_info.cmd_sts = ETH_TX_FIRST_DESC |
1174 ETH_GEN_TCP_UDP_CHECKSUM |
1175 ETH_GEN_IP_V_4_CHECKSUM |
1176 skb->nh.iph->ihl << ETH_TX_IHL_SHIFT;
1da177e4 1177 /* CPU already calculated pseudo header checksum. */
63890576
WJ		 1178 if ((skb->protocol == ETH_P_IP) &&
1179 (skb->nh.iph->protocol == IPPROTO_UDP)) {
1da177e4
LT		 1180 pkt_info.cmd_sts |= ETH_UDP_FRAME;
1181 pkt_info.l4i_chk = skb->h.uh->check;
63890576
WJ		 1182 } else if ((skb->protocol == ETH_P_IP) &&
1183 (skb->nh.iph->protocol == IPPROTO_TCP))
1da177e4
LT		 1184 pkt_info.l4i_chk = skb->h.th->check;
1185 else {
1186 printk(KERN_ERR
63890576 1187 "%s: chksum proto != IPv4 TCP or UDP\n",
1da177e4
LT		 1188 dev->name);
1189 spin_unlock_irqrestore(&mp->lock, flags);
1190 return 1;
1191 }
1192 }
1193
1194 status = eth_port_send(mp, &pkt_info);
1195 if (status != ETH_OK) {
1196 if ((status == ETH_ERROR))
1197 printk(KERN_ERR
1198 "%s: Error on transmitting packet\n",
1199 dev->name);
1200 if (status == ETH_QUEUE_FULL)
1201 printk("Error on Queue Full \n");
1202 if (status == ETH_QUEUE_LAST_RESOURCE)
1203 printk("Tx resource error \n");
1204 }
1205 stats->tx_bytes += pkt_info.byte_cnt;
1206
1207 /* Check for the remaining frags */
1208 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1209 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
1210 pkt_info.l4i_chk = 0x0000;
1211 pkt_info.cmd_sts = 0x00000000;
1212
1213 /* Last Frag enables interrupt and frees the skb */
1214 if (frag == (skb_shinfo(skb)->nr_frags - 1)) {
1215 pkt_info.cmd_sts |= ETH_TX_ENABLE_INTERRUPT |
1216 ETH_TX_LAST_DESC;
1217 pkt_info.return_info = skb;
1da177e4
LT		 1218 } else {
1219 pkt_info.return_info = 0;
1220 }
1221 pkt_info.l4i_chk = 0;
1222 pkt_info.byte_cnt = this_frag->size;
1223
1224 pkt_info.buf_ptr = dma_map_page(NULL, this_frag->page,
1225 this_frag->page_offset,
1226 this_frag->size,
1227 DMA_TO_DEVICE);
1228
1229 status = eth_port_send(mp, &pkt_info);
1230
1231 if (status != ETH_OK) {
1232 if ((status == ETH_ERROR))
1233 printk(KERN_ERR "%s: Error on "
1234 "transmitting packet\n",
1235 dev->name);
1236
1237 if (status == ETH_QUEUE_LAST_RESOURCE)
1238 printk("Tx resource error \n");
1239
1240 if (status == ETH_QUEUE_FULL)
1241 printk("Queue is full \n");
1242 }
1243 stats->tx_bytes += pkt_info.byte_cnt;
1244 }
1245 }
1246#else
f7ea3337
PJ		 1247 spin_lock_irqsave(&mp->lock, flags);
1248
1da177e4
LT		 1249 pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT | ETH_TX_FIRST_DESC |
1250 ETH_TX_LAST_DESC;
1251 pkt_info.l4i_chk = 0;
1252 pkt_info.byte_cnt = skb->len;
1253 pkt_info.buf_ptr = dma_map_single(NULL, skb->data, skb->len,
1254 DMA_TO_DEVICE);
1255 pkt_info.return_info = skb;
1da177e4
LT		 1256 status = eth_port_send(mp, &pkt_info);
1257 if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL))
1258 printk(KERN_ERR "%s: Error on transmitting packet\n",
1259 dev->name);
1260 stats->tx_bytes += pkt_info.byte_cnt;
1261#endif
1262
1263 /* Check if TX queue can handle another skb. If not, then
1264 * signal higher layers to stop requesting TX
1265 */
f98e36f1 1266 if (mp->tx_ring_size <= (mp->tx_desc_count + MAX_DESCS_PER_SKB))
1da177e4
LT		 1267 /*
1268 * Stop getting skb's from upper layers.
1269 * Getting skb's from upper layers will be enabled again after
1270 * packets are released.
1271 */
1272 netif_stop_queue(dev);
1273
1274 /* Update statistics and start of transmittion time */
1275 stats->tx_packets++;
1276 dev->trans_start = jiffies;
1277
1278 spin_unlock_irqrestore(&mp->lock, flags);
1279
1280 return 0; /* success */
1281}
1282
1283/*
1284 * mv643xx_eth_get_stats
1285 *
1286 * Returns a pointer to the interface statistics.
1287 *
1288 * Input : dev - a pointer to the required interface
1289 *
1290 * Output : a pointer to the interface's statistics
1291 */
1292
1293static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1294{
1295 struct mv643xx_private *mp = netdev_priv(dev);
1296
1297 return &mp->stats;
1298}
1299
63c9e549 1300#ifdef CONFIG_NET_POLL_CONTROLLER
63c9e549
DF		 1301static void mv643xx_netpoll(struct net_device *netdev)
1302{
1303 struct mv643xx_private *mp = netdev_priv(netdev);
c2e5b352
DF		 1304 int port_num = mp->port_num;
1305
1306 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), INT_MASK_ALL);
1307 /* wait for previous write to complete */
1308 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
63c9e549 1309
63c9e549 1310 mv643xx_eth_int_handler(netdev->irq, netdev, NULL);
c2e5b352
DF		 1311
1312 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), INT_UNMASK_ALL);
63c9e549
DF		 1313}
1314#endif
1315
1da177e4
LT		 1316/*/
1317 * mv643xx_eth_probe
1318 *
1319 * First function called after registering the network device.
1320 * It's purpose is to initialize the device as an ethernet device,
1321 * fill the ethernet device structure with pointers * to functions,
1322 * and set the MAC address of the interface
1323 *
1324 * Input : struct device *
1325 * Output : -ENOMEM if failed , 0 if success
1326 */
3ae5eaec 1327static int mv643xx_eth_probe(struct platform_device *pdev)
1da177e4 1328{
1da177e4
LT		 1329 struct mv643xx_eth_platform_data *pd;
1330 int port_num = pdev->id;
1331 struct mv643xx_private *mp;
1332 struct net_device *dev;
1333 u8 *p;
1334 struct resource *res;
1335 int err;
1336
1337 dev = alloc_etherdev(sizeof(struct mv643xx_private));
1338 if (!dev)
1339 return -ENOMEM;
1340
3ae5eaec 1341 platform_set_drvdata(pdev, dev);
1da177e4
LT		 1342
1343 mp = netdev_priv(dev);
1344
1345 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1346 BUG_ON(!res);
1347 dev->irq = res->start;
1348
1349 mp->port_num = port_num;
1350
1351 dev->open = mv643xx_eth_open;
1352 dev->stop = mv643xx_eth_stop;
1353 dev->hard_start_xmit = mv643xx_eth_start_xmit;
1354 dev->get_stats = mv643xx_eth_get_stats;
1355 dev->set_mac_address = mv643xx_eth_set_mac_address;
1356 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
1357
1358 /* No need to Tx Timeout */
1359 dev->tx_timeout = mv643xx_eth_tx_timeout;
1360#ifdef MV643XX_NAPI
1361 dev->poll = mv643xx_poll;
1362 dev->weight = 64;
1363#endif
1364
63c9e549
DF		 1365#ifdef CONFIG_NET_POLL_CONTROLLER
1366 dev->poll_controller = mv643xx_netpoll;
1367#endif
1368
1da177e4
LT		 1369 dev->watchdog_timeo = 2 * HZ;
1370 dev->tx_queue_len = mp->tx_ring_size;
1371 dev->base_addr = 0;
1372 dev->change_mtu = mv643xx_eth_change_mtu;
1373 SET_ETHTOOL_OPS(dev, &mv643xx_ethtool_ops);
1374
1375#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1376#ifdef MAX_SKB_FRAGS
1377 /*
1378 * Zero copy can only work if we use Discovery II memory. Else, we will
1379 * have to map the buffers to ISA memory which is only 16 MB
1380 */
63890576 1381 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
1da177e4
LT		 1382#endif
1383#endif
1384
1385 /* Configure the timeout task */
1386 INIT_WORK(&mp->tx_timeout_task,
1387 (void (*)(void *))mv643xx_eth_tx_timeout_task, dev);
1388
1389 spin_lock_init(&mp->lock);
1390
1391 /* set default config values */
1392 eth_port_uc_addr_get(dev, dev->dev_addr);
1393 mp->port_config = MV643XX_ETH_PORT_CONFIG_DEFAULT_VALUE;
1394 mp->port_config_extend = MV643XX_ETH_PORT_CONFIG_EXTEND_DEFAULT_VALUE;
1395 mp->port_sdma_config = MV643XX_ETH_PORT_SDMA_CONFIG_DEFAULT_VALUE;
1396 mp->port_serial_control = MV643XX_ETH_PORT_SERIAL_CONTROL_DEFAULT_VALUE;
1397 mp->rx_ring_size = MV643XX_ETH_PORT_DEFAULT_RECEIVE_QUEUE_SIZE;
1398 mp->tx_ring_size = MV643XX_ETH_PORT_DEFAULT_TRANSMIT_QUEUE_SIZE;
1399
1400 pd = pdev->dev.platform_data;
1401 if (pd) {
1402 if (pd->mac_addr != NULL)
1403 memcpy(dev->dev_addr, pd->mac_addr, 6);
1404
1405 if (pd->phy_addr || pd->force_phy_addr)
1406 ethernet_phy_set(port_num, pd->phy_addr);
1407
1408 if (pd->port_config || pd->force_port_config)
1409 mp->port_config = pd->port_config;
1410
1411 if (pd->port_config_extend || pd->force_port_config_extend)
1412 mp->port_config_extend = pd->port_config_extend;
1413
1414 if (pd->port_sdma_config || pd->force_port_sdma_config)
1415 mp->port_sdma_config = pd->port_sdma_config;
1416
1417 if (pd->port_serial_control || pd->force_port_serial_control)
1418 mp->port_serial_control = pd->port_serial_control;
1419
1420 if (pd->rx_queue_size)
1421 mp->rx_ring_size = pd->rx_queue_size;
1422
1423 if (pd->tx_queue_size)
1424 mp->tx_ring_size = pd->tx_queue_size;
1425
1426 if (pd->tx_sram_size) {
1427 mp->tx_sram_size = pd->tx_sram_size;
1428 mp->tx_sram_addr = pd->tx_sram_addr;
1429 }
1430
1431 if (pd->rx_sram_size) {
1432 mp->rx_sram_size = pd->rx_sram_size;
1433 mp->rx_sram_addr = pd->rx_sram_addr;
1434 }
1435 }
1436
1437 err = ethernet_phy_detect(port_num);
1438 if (err) {
1439 pr_debug("MV643xx ethernet port %d: "
1440 "No PHY detected at addr %d\n",
1441 port_num, ethernet_phy_get(port_num));
1442 return err;
1443 }
1444
1445 err = register_netdev(dev);
1446 if (err)
1447 goto out;
1448
1449 p = dev->dev_addr;
1450 printk(KERN_NOTICE
1451 "%s: port %d with MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
1452 dev->name, port_num, p[0], p[1], p[2], p[3], p[4], p[5]);
1453
1454 if (dev->features & NETIF_F_SG)
1455 printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name);
1456
1457 if (dev->features & NETIF_F_IP_CSUM)
1458 printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n",
1459 dev->name);
1460
1461#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1462 printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name);
1463#endif
1464
1465#ifdef MV643XX_COAL
1466 printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n",
1467 dev->name);
1468#endif
1469
1470#ifdef MV643XX_NAPI
1471 printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name);
1472#endif
1473
b1529871
ND		 1474 if (mp->tx_sram_size > 0)
1475 printk(KERN_NOTICE "%s: Using SRAM\n", dev->name);
1476
1da177e4
LT		 1477 return 0;
1478
1479out:
1480 free_netdev(dev);
1481
1482 return err;
1483}
1484
3ae5eaec 1485static int mv643xx_eth_remove(struct platform_device *pdev)
1da177e4 1486{
3ae5eaec 1487 struct net_device *dev = platform_get_drvdata(pdev);
1da177e4
LT		 1488
1489 unregister_netdev(dev);
1490 flush_scheduled_work();
1491
1492 free_netdev(dev);
3ae5eaec 1493 platform_set_drvdata(pdev, NULL);
1da177e4
LT		 1494 return 0;
1495}
1496
3ae5eaec 1497static int mv643xx_eth_shared_probe(struct platform_device *pdev)
1da177e4 1498{
1da177e4
LT		 1499 struct resource *res;
1500
1501 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
1502
1503 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1504 if (res == NULL)
1505 return -ENODEV;
1506
1507 mv643xx_eth_shared_base = ioremap(res->start,
1508 MV643XX_ETH_SHARED_REGS_SIZE);
1509 if (mv643xx_eth_shared_base == NULL)
1510 return -ENOMEM;
1511
1512 return 0;
1513
1514}
1515
3ae5eaec 1516static int mv643xx_eth_shared_remove(struct platform_device *pdev)
1da177e4
LT		 1517{
1518 iounmap(mv643xx_eth_shared_base);
1519 mv643xx_eth_shared_base = NULL;
1520
1521 return 0;
1522}
1523
3ae5eaec 1524static struct platform_driver mv643xx_eth_driver = {
1da177e4
LT		 1525 .probe = mv643xx_eth_probe,
1526 .remove = mv643xx_eth_remove,
3ae5eaec
RK		 1527 .driver = {
1528 .name = MV643XX_ETH_NAME,
1529 },
1da177e4
LT		 1530};
1531
3ae5eaec 1532static struct platform_driver mv643xx_eth_shared_driver = {
1da177e4
LT		 1533 .probe = mv643xx_eth_shared_probe,
1534 .remove = mv643xx_eth_shared_remove,
3ae5eaec
RK		 1535 .driver = {
1536 .name = MV643XX_ETH_SHARED_NAME,
1537 },
1da177e4
LT		 1538};
1539
1540/*
1541 * mv643xx_init_module
1542 *
1543 * Registers the network drivers into the Linux kernel
1544 *
1545 * Input : N/A
1546 *
1547 * Output : N/A
1548 */
1549static int __init mv643xx_init_module(void)
1550{
1551 int rc;
1552
3ae5eaec 1553 rc = platform_driver_register(&mv643xx_eth_shared_driver);
1da177e4 1554 if (!rc) {
3ae5eaec 1555 rc = platform_driver_register(&mv643xx_eth_driver);
1da177e4 1556 if (rc)
3ae5eaec 1557 platform_driver_unregister(&mv643xx_eth_shared_driver);
1da177e4
LT		 1558 }
1559 return rc;
1560}
1561
1562/*
1563 * mv643xx_cleanup_module
1564 *
1565 * Registers the network drivers into the Linux kernel
1566 *
1567 * Input : N/A
1568 *
1569 * Output : N/A
1570 */
1571static void __exit mv643xx_cleanup_module(void)
1572{
3ae5eaec
RK		 1573 platform_driver_unregister(&mv643xx_eth_driver);
1574 platform_driver_unregister(&mv643xx_eth_shared_driver);
1da177e4
LT		 1575}
1576
1577module_init(mv643xx_init_module);
1578module_exit(mv643xx_cleanup_module);
1579
1580MODULE_LICENSE("GPL");
1581MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani"
1582 " and Dale Farnsworth");
1583MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
1584
1585/*
1586 * The second part is the low level driver of the gigE ethernet ports.
1587 */
1588
1589/*
1590 * Marvell's Gigabit Ethernet controller low level driver
1591 *
1592 * DESCRIPTION:
1593 * This file introduce low level API to Marvell's Gigabit Ethernet
1594 * controller. This Gigabit Ethernet Controller driver API controls
1595 * 1) Operations (i.e. port init, start, reset etc').
1596 * 2) Data flow (i.e. port send, receive etc').
1597 * Each Gigabit Ethernet port is controlled via
1598 * struct mv643xx_private.
1599 * This struct includes user configuration information as well as
1600 * driver internal data needed for its operations.
1601 *
1602 * Supported Features:
1603 * - This low level driver is OS independent. Allocating memory for
1604 * the descriptor rings and buffers are not within the scope of
1605 * this driver.
1606 * - The user is free from Rx/Tx queue managing.
1607 * - This low level driver introduce functionality API that enable
1608 * the to operate Marvell's Gigabit Ethernet Controller in a
1609 * convenient way.
1610 * - Simple Gigabit Ethernet port operation API.
1611 * - Simple Gigabit Ethernet port data flow API.
1612 * - Data flow and operation API support per queue functionality.
1613 * - Support cached descriptors for better performance.
1614 * - Enable access to all four DRAM banks and internal SRAM memory
1615 * spaces.
1616 * - PHY access and control API.
1617 * - Port control register configuration API.
1618 * - Full control over Unicast and Multicast MAC configurations.
1619 *
1620 * Operation flow:
1621 *
1622 * Initialization phase
1623 * This phase complete the initialization of the the
1624 * mv643xx_private struct.
1625 * User information regarding port configuration has to be set
1626 * prior to calling the port initialization routine.
1627 *
1628 * In this phase any port Tx/Rx activity is halted, MIB counters
1629 * are cleared, PHY address is set according to user parameter and
1630 * access to DRAM and internal SRAM memory spaces.
1631 *
1632 * Driver ring initialization
1633 * Allocating memory for the descriptor rings and buffers is not
1634 * within the scope of this driver. Thus, the user is required to
1635 * allocate memory for the descriptors ring and buffers. Those
1636 * memory parameters are used by the Rx and Tx ring initialization
1637 * routines in order to curve the descriptor linked list in a form
1638 * of a ring.
1639 * Note: Pay special attention to alignment issues when using
1640 * cached descriptors/buffers. In this phase the driver store
1641 * information in the mv643xx_private struct regarding each queue
1642 * ring.
1643 *
1644 * Driver start
1645 * This phase prepares the Ethernet port for Rx and Tx activity.
1646 * It uses the information stored in the mv643xx_private struct to
1647 * initialize the various port registers.
1648 *
1649 * Data flow:
1650 * All packet references to/from the driver are done using
1651 * struct pkt_info.
1652 * This struct is a unified struct used with Rx and Tx operations.
1653 * This way the user is not required to be familiar with neither
1654 * Tx nor Rx descriptors structures.
1655 * The driver's descriptors rings are management by indexes.
1656 * Those indexes controls the ring resources and used to indicate
1657 * a SW resource error:
1658 * 'current'
1659 * This index points to the current available resource for use. For
1660 * example in Rx process this index will point to the descriptor
1661 * that will be passed to the user upon calling the receive
1662 * routine. In Tx process, this index will point to the descriptor
1663 * that will be assigned with the user packet info and transmitted.
1664 * 'used'
1665 * This index points to the descriptor that need to restore its
1666 * resources. For example in Rx process, using the Rx buffer return
1667 * API will attach the buffer returned in packet info to the
1668 * descriptor pointed by 'used'. In Tx process, using the Tx
1669 * descriptor return will merely return the user packet info with
1670 * the command status of the transmitted buffer pointed by the
1671 * 'used' index. Nevertheless, it is essential to use this routine
1672 * to update the 'used' index.
1673 * 'first'
1674 * This index supports Tx Scatter-Gather. It points to the first
1675 * descriptor of a packet assembled of multiple buffers. For
1676 * example when in middle of Such packet we have a Tx resource
1677 * error the 'curr' index get the value of 'first' to indicate
1678 * that the ring returned to its state before trying to transmit
1679 * this packet.
1680 *
1681 * Receive operation:
1682 * The eth_port_receive API set the packet information struct,
1683 * passed by the caller, with received information from the
1684 * 'current' SDMA descriptor.
1685 * It is the user responsibility to return this resource back
1686 * to the Rx descriptor ring to enable the reuse of this source.
1687 * Return Rx resource is done using the eth_rx_return_buff API.
1688 *
1689 * Transmit operation:
1690 * The eth_port_send API supports Scatter-Gather which enables to
1691 * send a packet spanned over multiple buffers. This means that
1692 * for each packet info structure given by the user and put into
1693 * the Tx descriptors ring, will be transmitted only if the 'LAST'
1694 * bit will be set in the packet info command status field. This
1695 * API also consider restriction regarding buffer alignments and
1696 * sizes.
1697 * The user must return a Tx resource after ensuring the buffer
1698 * has been transmitted to enable the Tx ring indexes to update.
1699 *
1700 * BOARD LAYOUT
1701 * This device is on-board. No jumper diagram is necessary.
1702 *
1703 * EXTERNAL INTERFACE
1704 *
1705 * Prior to calling the initialization routine eth_port_init() the user
1706 * must set the following fields under mv643xx_private struct:
1707 * port_num User Ethernet port number.
1da177e4
LT		 1708 * port_config User port configuration value.
1709 * port_config_extend User port config extend value.
1710 * port_sdma_config User port SDMA config value.
1711 * port_serial_control User port serial control value.
1712 *
1713 * This driver data flow is done using the struct pkt_info which
1714 * is a unified struct for Rx and Tx operations:
1715 *
1716 * byte_cnt Tx/Rx descriptor buffer byte count.
1717 * l4i_chk CPU provided TCP Checksum. For Tx operation
1718 * only.
1719 * cmd_sts Tx/Rx descriptor command status.
1720 * buf_ptr Tx/Rx descriptor buffer pointer.
1721 * return_info Tx/Rx user resource return information.
1722 */
1723
1da177e4
LT		 1724/* PHY routines */
1725static int ethernet_phy_get(unsigned int eth_port_num);
1726static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
1727
1728/* Ethernet Port routines */
cf4086c7 1729static void eth_port_set_filter_table_entry(int table, unsigned char entry);
1da177e4
LT		 1730
1731/*
1732 * eth_port_init - Initialize the Ethernet port driver
1733 *
1734 * DESCRIPTION:
1735 * This function prepares the ethernet port to start its activity:
1736 * 1) Completes the ethernet port driver struct initialization toward port
1737 * start routine.
1738 * 2) Resets the device to a quiescent state in case of warm reboot.
1739 * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
1740 * 4) Clean MAC tables. The reset status of those tables is unknown.
1741 * 5) Set PHY address.
1742 * Note: Call this routine prior to eth_port_start routine and after
1743 * setting user values in the user fields of Ethernet port control
1744 * struct.
1745 *
1746 * INPUT:
1747 * struct mv643xx_private *mp Ethernet port control struct
1748 *
1749 * OUTPUT:
1750 * See description.
1751 *
1752 * RETURN:
1753 * None.
1754 */
1755static void eth_port_init(struct mv643xx_private *mp)
1756{
1da177e4
LT		 1757 mp->rx_resource_err = 0;
1758 mp->tx_resource_err = 0;
1759
1760 eth_port_reset(mp->port_num);
1761
1762 eth_port_init_mac_tables(mp->port_num);
1763
1764 ethernet_phy_reset(mp->port_num);
1765}
1766
1767/*
1768 * eth_port_start - Start the Ethernet port activity.
1769 *
1770 * DESCRIPTION:
1771 * This routine prepares the Ethernet port for Rx and Tx activity:
1772 * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
1773 * has been initialized a descriptor's ring (using
1774 * ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx)
1775 * 2. Initialize and enable the Ethernet configuration port by writing to
1776 * the port's configuration and command registers.
1777 * 3. Initialize and enable the SDMA by writing to the SDMA's
1778 * configuration and command registers. After completing these steps,
1779 * the ethernet port SDMA can starts to perform Rx and Tx activities.
1780 *
1781 * Note: Each Rx and Tx queue descriptor's list must be initialized prior
1782 * to calling this function (use ether_init_tx_desc_ring for Tx queues
1783 * and ether_init_rx_desc_ring for Rx queues).
1784 *
1785 * INPUT:
ed9b5d45 1786 * dev - a pointer to the required interface
1da177e4
LT		 1787 *
1788 * OUTPUT:
1789 * Ethernet port is ready to receive and transmit.
1790 *
1791 * RETURN:
1792 * None.
1793 */
ed9b5d45 1794static void eth_port_start(struct net_device *dev)
1da177e4 1795{
ed9b5d45 1796 struct mv643xx_private *mp = netdev_priv(dev);
1da177e4
LT		 1797 unsigned int port_num = mp->port_num;
1798 int tx_curr_desc, rx_curr_desc;
1799
1800 /* Assignment of Tx CTRP of given queue */
1801 tx_curr_desc = mp->tx_curr_desc_q;
1802 mv_write(MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port_num),
1803 (u32)((struct eth_tx_desc *)mp->tx_desc_dma + tx_curr_desc));
1804
1805 /* Assignment of Rx CRDP of given queue */
1806 rx_curr_desc = mp->rx_curr_desc_q;
1807 mv_write(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num),
1808 (u32)((struct eth_rx_desc *)mp->rx_desc_dma + rx_curr_desc));
1809
1810 /* Add the assigned Ethernet address to the port's address table */
ed9b5d45 1811 eth_port_uc_addr_set(port_num, dev->dev_addr);
1da177e4
LT		 1812
1813 /* Assign port configuration and command. */
1814 mv_write(MV643XX_ETH_PORT_CONFIG_REG(port_num), mp->port_config);
1815
1816 mv_write(MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port_num),
1817 mp->port_config_extend);
1818
1819
1820 /* Increase the Rx side buffer size if supporting GigE */
1821 if (mp->port_serial_control & MV643XX_ETH_SET_GMII_SPEED_TO_1000)
1822 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
1823 (mp->port_serial_control & 0xfff1ffff) | (0x5 << 17));
1824 else
1825 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
1826 mp->port_serial_control);
1827
1828 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
1829 mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num)) |
1830 MV643XX_ETH_SERIAL_PORT_ENABLE);
1831
1832 /* Assign port SDMA configuration */
1833 mv_write(MV643XX_ETH_SDMA_CONFIG_REG(port_num),
1834 mp->port_sdma_config);
1835
1836 /* Enable port Rx. */
9f8dd319 1837 mv643xx_eth_port_enable_rx(port_num, mp->port_rx_queue_command);
8f543718
DF		 1838
1839 /* Disable port bandwidth limits by clearing MTU register */
1840 mv_write(MV643XX_ETH_MAXIMUM_TRANSMIT_UNIT(port_num), 0);
1da177e4
LT		 1841}
1842
1843/*
1844 * eth_port_uc_addr_set - This function Set the port Unicast address.
1845 *
1846 * DESCRIPTION:
1847 * This function Set the port Ethernet MAC address.
1848 *
1849 * INPUT:
1850 * unsigned int eth_port_num Port number.
1851 * char * p_addr Address to be set
1852 *
1853 * OUTPUT:
cf4086c7
DF		 1854 * Set MAC address low and high registers. also calls
1855 * eth_port_set_filter_table_entry() to set the unicast
1856 * table with the proper information.
1da177e4
LT		 1857 *
1858 * RETURN:
1859 * N/A.
1860 *
1861 */
1862static void eth_port_uc_addr_set(unsigned int eth_port_num,
1863 unsigned char *p_addr)
1864{
1865 unsigned int mac_h;
1866 unsigned int mac_l;
cf4086c7 1867 int table;
1da177e4
LT		 1868
1869 mac_l = (p_addr[4] << 8) | (p_addr[5]);
1870 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
1871 (p_addr[3] << 0);
1872
1873 mv_write(MV643XX_ETH_MAC_ADDR_LOW(eth_port_num), mac_l);
1874 mv_write(MV643XX_ETH_MAC_ADDR_HIGH(eth_port_num), mac_h);
1875
1876 /* Accept frames of this address */
cf4086c7
DF		 1877 table = MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE(eth_port_num);
1878 eth_port_set_filter_table_entry(table, p_addr[5] & 0x0f);
1da177e4
LT		 1879}
1880
1881/*
1882 * eth_port_uc_addr_get - This function retrieves the port Unicast address
1883 * (MAC address) from the ethernet hw registers.
1884 *
1885 * DESCRIPTION:
1886 * This function retrieves the port Ethernet MAC address.
1887 *
1888 * INPUT:
1889 * unsigned int eth_port_num Port number.
1890 * char *MacAddr pointer where the MAC address is stored
1891 *
1892 * OUTPUT:
1893 * Copy the MAC address to the location pointed to by MacAddr
1894 *
1895 * RETURN:
1896 * N/A.
1897 *
1898 */
1899static void eth_port_uc_addr_get(struct net_device *dev, unsigned char *p_addr)
1900{
1901 struct mv643xx_private *mp = netdev_priv(dev);
1902 unsigned int mac_h;
1903 unsigned int mac_l;
1904
1905 mac_h = mv_read(MV643XX_ETH_MAC_ADDR_HIGH(mp->port_num));
1906 mac_l = mv_read(MV643XX_ETH_MAC_ADDR_LOW(mp->port_num));
1907
1908 p_addr[0] = (mac_h >> 24) & 0xff;
1909 p_addr[1] = (mac_h >> 16) & 0xff;
1910 p_addr[2] = (mac_h >> 8) & 0xff;
1911 p_addr[3] = mac_h & 0xff;
1912 p_addr[4] = (mac_l >> 8) & 0xff;
1913 p_addr[5] = mac_l & 0xff;
1914}
1915
16e03018
DF		 1916/*
1917 * The entries in each table are indexed by a hash of a packet's MAC
1918 * address. One bit in each entry determines whether the packet is
1919 * accepted. There are 4 entries (each 8 bits wide) in each register
1920 * of the table. The bits in each entry are defined as follows:
1921 * 0 Accept=1, Drop=0
1922 * 3-1 Queue (ETH_Q0=0)
1923 * 7-4 Reserved = 0;
1924 */
1925static void eth_port_set_filter_table_entry(int table, unsigned char entry)
1926{
1927 unsigned int table_reg;
1928 unsigned int tbl_offset;
1929 unsigned int reg_offset;
1930
1931 tbl_offset = (entry / 4) * 4; /* Register offset of DA table entry */
1932 reg_offset = entry % 4; /* Entry offset within the register */
1933
1934 /* Set "accepts frame bit" at specified table entry */
1935 table_reg = mv_read(table + tbl_offset);
1936 table_reg |= 0x01 << (8 * reg_offset);
1937 mv_write(table + tbl_offset, table_reg);
1938}
1939
1940/*
1941 * eth_port_mc_addr - Multicast address settings.
1942 *
1943 * The MV device supports multicast using two tables:
1944 * 1) Special Multicast Table for MAC addresses of the form
1945 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_FF).
1946 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1947 * Table entries in the DA-Filter table.
1948 * 2) Other Multicast Table for multicast of another type. A CRC-8bit
1949 * is used as an index to the Other Multicast Table entries in the
1950 * DA-Filter table. This function calculates the CRC-8bit value.
1951 * In either case, eth_port_set_filter_table_entry() is then called
1952 * to set to set the actual table entry.
1953 */
1954static void eth_port_mc_addr(unsigned int eth_port_num, unsigned char *p_addr)
1955{
1956 unsigned int mac_h;
1957 unsigned int mac_l;
1958 unsigned char crc_result = 0;
1959 int table;
1960 int mac_array[48];
1961 int crc[8];
1962 int i;
1963
1964 if ((p_addr[0] == 0x01) && (p_addr[1] == 0x00) &&
1965 (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) {
1966 table = MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
1967 (eth_port_num);
1968 eth_port_set_filter_table_entry(table, p_addr[5]);
1969 return;
1970 }
1971
1972 /* Calculate CRC-8 out of the given address */
1973 mac_h = (p_addr[0] << 8) | (p_addr[1]);
1974 mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
1975 (p_addr[4] << 8) | (p_addr[5] << 0);
1976
1977 for (i = 0; i < 32; i++)
1978 mac_array[i] = (mac_l >> i) & 0x1;
1979 for (i = 32; i < 48; i++)
1980 mac_array[i] = (mac_h >> (i - 32)) & 0x1;
1981
1982 crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ mac_array[39] ^
1983 mac_array[35] ^ mac_array[34] ^ mac_array[31] ^ mac_array[30] ^
1984 mac_array[28] ^ mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
1985 mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ mac_array[12] ^
1986 mac_array[8] ^ mac_array[7] ^ mac_array[6] ^ mac_array[0];
1987
1988 crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
1989 mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ mac_array[34] ^
1990 mac_array[32] ^ mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
1991 mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ mac_array[21] ^
1992 mac_array[20] ^ mac_array[18] ^ mac_array[17] ^ mac_array[16] ^
1993 mac_array[15] ^ mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
1994 mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ mac_array[0];
1995
1996 crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ mac_array[43] ^
1997 mac_array[42] ^ mac_array[39] ^ mac_array[37] ^ mac_array[34] ^
1998 mac_array[33] ^ mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
1999 mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ mac_array[15] ^
2000 mac_array[13] ^ mac_array[12] ^ mac_array[10] ^ mac_array[8] ^
2001 mac_array[6] ^ mac_array[2] ^ mac_array[1] ^ mac_array[0];
2002
2003 crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
2004 mac_array[40] ^ mac_array[38] ^ mac_array[35] ^ mac_array[34] ^
2005 mac_array[30] ^ mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
2006 mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
2007 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[7] ^
2008 mac_array[3] ^ mac_array[2] ^ mac_array[1];
2009
2010 crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[41] ^
2011 mac_array[39] ^ mac_array[36] ^ mac_array[35] ^ mac_array[31] ^
2012 mac_array[30] ^ mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
2013 mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ mac_array[14] ^
2014 mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ mac_array[4] ^
2015 mac_array[3] ^ mac_array[2];
2016
2017 crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ mac_array[42] ^
2018 mac_array[40] ^ mac_array[37] ^ mac_array[36] ^ mac_array[32] ^
2019 mac_array[31] ^ mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
2020 mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ mac_array[15] ^
2021 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[5] ^
2022 mac_array[4] ^ mac_array[3];
2023
2024 crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ mac_array[41] ^
2025 mac_array[38] ^ mac_array[37] ^ mac_array[33] ^ mac_array[32] ^
2026 mac_array[29] ^ mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
2027 mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ mac_array[14] ^
2028 mac_array[12] ^ mac_array[10] ^ mac_array[6] ^ mac_array[5] ^
2029 mac_array[4];
2030
2031 crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ mac_array[39] ^
2032 mac_array[38] ^ mac_array[34] ^ mac_array[33] ^ mac_array[30] ^
2033 mac_array[29] ^ mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
2034 mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ mac_array[13] ^
2035 mac_array[11] ^ mac_array[7] ^ mac_array[6] ^ mac_array[5];
2036
2037 for (i = 0; i < 8; i++)
2038 crc_result = crc_result | (crc[i] << i);
2039
2040 table = MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num);
2041 eth_port_set_filter_table_entry(table, crc_result);
2042}
2043
2044/*
2045 * Set the entire multicast list based on dev->mc_list.
2046 */
2047static void eth_port_set_multicast_list(struct net_device *dev)
2048{
2049
2050 struct dev_mc_list *mc_list;
2051 int i;
2052 int table_index;
2053 struct mv643xx_private *mp = netdev_priv(dev);
2054 unsigned int eth_port_num = mp->port_num;
2055
2056 /* If the device is in promiscuous mode or in all multicast mode,
2057 * we will fully populate both multicast tables with accept.
2058 * This is guaranteed to yield a match on all multicast addresses...
2059 */
2060 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) {
2061 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
b4de9051
DF		 2062 /* Set all entries in DA filter special multicast
2063 * table (Ex_dFSMT)
2064 * Set for ETH_Q0 for now
2065 * Bits
2066 * 0 Accept=1, Drop=0
2067 * 3-1 Queue ETH_Q0=0
2068 * 7-4 Reserved = 0;
2069 */
2070 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
2071
2072 /* Set all entries in DA filter other multicast
2073 * table (Ex_dFOMT)
2074 * Set for ETH_Q0 for now
2075 * Bits
2076 * 0 Accept=1, Drop=0
2077 * 3-1 Queue ETH_Q0=0
2078 * 7-4 Reserved = 0;
2079 */
2080 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
2081 }
16e03018
DF		 2082 return;
2083 }
2084
2085 /* We will clear out multicast tables every time we get the list.
2086 * Then add the entire new list...
2087 */
2088 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2089 /* Clear DA filter special multicast table (Ex_dFSMT) */
2090 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2091 (eth_port_num) + table_index, 0);
2092
2093 /* Clear DA filter other multicast table (Ex_dFOMT) */
2094 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2095 (eth_port_num) + table_index, 0);
2096 }
2097
2098 /* Get pointer to net_device multicast list and add each one... */
2099 for (i = 0, mc_list = dev->mc_list;
2100 (i < 256) && (mc_list != NULL) && (i < dev->mc_count);
2101 i++, mc_list = mc_list->next)
2102 if (mc_list->dmi_addrlen == 6)
2103 eth_port_mc_addr(eth_port_num, mc_list->dmi_addr);
2104}
2105
1da177e4
LT		 2106/*
2107 * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
2108 *
2109 * DESCRIPTION:
2110 * Go through all the DA filter tables (Unicast, Special Multicast &
2111 * Other Multicast) and set each entry to 0.
2112 *
2113 * INPUT:
2114 * unsigned int eth_port_num Ethernet Port number.
2115 *
2116 * OUTPUT:
2117 * Multicast and Unicast packets are rejected.
2118 *
2119 * RETURN:
2120 * None.
2121 */
2122static void eth_port_init_mac_tables(unsigned int eth_port_num)
2123{
2124 int table_index;
2125
2126 /* Clear DA filter unicast table (Ex_dFUT) */
2127 for (table_index = 0; table_index <= 0xC; table_index += 4)
cf4086c7
DF		 2128 mv_write(MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2129 (eth_port_num) + table_index, 0);
1da177e4
LT		 2130
2131 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2132 /* Clear DA filter special multicast table (Ex_dFSMT) */
16e03018
DF		 2133 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2134 (eth_port_num) + table_index, 0);
1da177e4 2135 /* Clear DA filter other multicast table (Ex_dFOMT) */
16e03018
DF		 2136 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2137 (eth_port_num) + table_index, 0);
1da177e4
LT		 2138 }
2139}
2140
2141/*
2142 * eth_clear_mib_counters - Clear all MIB counters
2143 *
2144 * DESCRIPTION:
2145 * This function clears all MIB counters of a specific ethernet port.
2146 * A read from the MIB counter will reset the counter.
2147 *
2148 * INPUT:
2149 * unsigned int eth_port_num Ethernet Port number.
2150 *
2151 * OUTPUT:
2152 * After reading all MIB counters, the counters resets.
2153 *
2154 * RETURN:
2155 * MIB counter value.
2156 *
2157 */
2158static void eth_clear_mib_counters(unsigned int eth_port_num)
2159{
2160 int i;
2161
2162 /* Perform dummy reads from MIB counters */
2163 for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
2164 i += 4)
2165 mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(eth_port_num) + i);
2166}
2167
2168static inline u32 read_mib(struct mv643xx_private *mp, int offset)
2169{
2170 return mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(mp->port_num) + offset);
2171}
2172
2173static void eth_update_mib_counters(struct mv643xx_private *mp)
2174{
2175 struct mv643xx_mib_counters *p = &mp->mib_counters;
2176 int offset;
2177
2178 p->good_octets_received +=
2179 read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
2180 p->good_octets_received +=
2181 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32;
2182
2183 for (offset = ETH_MIB_BAD_OCTETS_RECEIVED;
2184 offset <= ETH_MIB_FRAMES_1024_TO_MAX_OCTETS;
2185 offset += 4)
2186 *(u32 *)((char *)p + offset) = read_mib(mp, offset);
2187
2188 p->good_octets_sent += read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_LOW);
2189 p->good_octets_sent +=
2190 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_HIGH) << 32;
2191
2192 for (offset = ETH_MIB_GOOD_FRAMES_SENT;
2193 offset <= ETH_MIB_LATE_COLLISION;
2194 offset += 4)
2195 *(u32 *)((char *)p + offset) = read_mib(mp, offset);
2196}
2197
2198/*
2199 * ethernet_phy_detect - Detect whether a phy is present
2200 *
2201 * DESCRIPTION:
2202 * This function tests whether there is a PHY present on
2203 * the specified port.
2204 *
2205 * INPUT:
2206 * unsigned int eth_port_num Ethernet Port number.
2207 *
2208 * OUTPUT:
2209 * None
2210 *
2211 * RETURN:
2212 * 0 on success
2213 * -ENODEV on failure
2214 *
2215 */
2216static int ethernet_phy_detect(unsigned int port_num)
2217{
2218 unsigned int phy_reg_data0;
2219 int auto_neg;
2220
2221 eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
2222 auto_neg = phy_reg_data0 & 0x1000;
2223 phy_reg_data0 ^= 0x1000; /* invert auto_neg */
2224 eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
2225
2226 eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
2227 if ((phy_reg_data0 & 0x1000) == auto_neg)
2228 return -ENODEV; /* change didn't take */
2229
2230 phy_reg_data0 ^= 0x1000;
2231 eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
2232 return 0;
2233}
2234
2235/*
2236 * ethernet_phy_get - Get the ethernet port PHY address.
2237 *
2238 * DESCRIPTION:
2239 * This routine returns the given ethernet port PHY address.
2240 *
2241 * INPUT:
2242 * unsigned int eth_port_num Ethernet Port number.
2243 *
2244 * OUTPUT:
2245 * None.
2246 *
2247 * RETURN:
2248 * PHY address.
2249 *
2250 */
2251static int ethernet_phy_get(unsigned int eth_port_num)
2252{
2253 unsigned int reg_data;
2254
2255 reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG);
2256
2257 return ((reg_data >> (5 * eth_port_num)) & 0x1f);
2258}
2259
2260/*
2261 * ethernet_phy_set - Set the ethernet port PHY address.
2262 *
2263 * DESCRIPTION:
2264 * This routine sets the given ethernet port PHY address.
2265 *
2266 * INPUT:
2267 * unsigned int eth_port_num Ethernet Port number.
2268 * int phy_addr PHY address.
2269 *
2270 * OUTPUT:
2271 * None.
2272 *
2273 * RETURN:
2274 * None.
2275 *
2276 */
2277static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr)
2278{
2279 u32 reg_data;
2280 int addr_shift = 5 * eth_port_num;
2281
2282 reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG);
2283 reg_data &= ~(0x1f << addr_shift);
2284 reg_data |= (phy_addr & 0x1f) << addr_shift;
2285 mv_write(MV643XX_ETH_PHY_ADDR_REG, reg_data);
2286}
2287
2288/*
2289 * ethernet_phy_reset - Reset Ethernet port PHY.
2290 *
2291 * DESCRIPTION:
2292 * This routine utilizes the SMI interface to reset the ethernet port PHY.
2293 *
2294 * INPUT:
2295 * unsigned int eth_port_num Ethernet Port number.
2296 *
2297 * OUTPUT:
2298 * The PHY is reset.
2299 *
2300 * RETURN:
2301 * None.
2302 *
2303 */
2304static void ethernet_phy_reset(unsigned int eth_port_num)
2305{
2306 unsigned int phy_reg_data;
2307
2308 /* Reset the PHY */
2309 eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data);
2310 phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
2311 eth_port_write_smi_reg(eth_port_num, 0, phy_reg_data);
2312}
2313
9f8dd319
DF		 2314static void mv643xx_eth_port_enable_tx(unsigned int port_num,
2315 unsigned int channels)
2316{
2317 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num), channels);
2318}
2319
2320static void mv643xx_eth_port_enable_rx(unsigned int port_num,
2321 unsigned int channels)
2322{
2323 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), channels);
2324}
2325
2326static unsigned int mv643xx_eth_port_disable_tx(unsigned int port_num)
2327{
2328 u32 channels;
2329
2330 /* Stop Tx port activity. Check port Tx activity. */
2331 channels = mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num))
2332 & 0xFF;
2333 if (channels) {
2334 /* Issue stop command for active channels only */
2335 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num),
2336 (channels << 8));
2337
2338 /* Wait for all Tx activity to terminate. */
2339 /* Check port cause register that all Tx queues are stopped */
2340 while (mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num))
2341 & 0xFF)
2342 udelay(PHY_WAIT_MICRO_SECONDS);
2343
2344 /* Wait for Tx FIFO to empty */
2345 while (mv_read(MV643XX_ETH_PORT_STATUS_REG(port_num)) &
2346 ETH_PORT_TX_FIFO_EMPTY)
2347 udelay(PHY_WAIT_MICRO_SECONDS);
2348 }
2349
2350 return channels;
2351}
2352
2353static unsigned int mv643xx_eth_port_disable_rx(unsigned int port_num)
2354{
2355 u32 channels;
2356
2357 /* Stop Rx port activity. Check port Rx activity. */
2358 channels = mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num)
2359 & 0xFF);
2360 if (channels) {
2361 /* Issue stop command for active channels only */
2362 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num),
2363 (channels << 8));
2364
2365 /* Wait for all Rx activity to terminate. */
2366 /* Check port cause register that all Rx queues are stopped */
2367 while (mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num))
2368 & 0xFF)
2369 udelay(PHY_WAIT_MICRO_SECONDS);
2370 }
2371
2372 return channels;
2373}
2374
1da177e4
LT		 2375/*
2376 * eth_port_reset - Reset Ethernet port
2377 *
2378 * DESCRIPTION:
2379 * This routine resets the chip by aborting any SDMA engine activity and
2380 * clearing the MIB counters. The Receiver and the Transmit unit are in
2381 * idle state after this command is performed and the port is disabled.
2382 *
2383 * INPUT:
2384 * unsigned int eth_port_num Ethernet Port number.
2385 *
2386 * OUTPUT:
2387 * Channel activity is halted.
2388 *
2389 * RETURN:
2390 * None.
2391 *
2392 */
2393static void eth_port_reset(unsigned int port_num)
2394{
2395 unsigned int reg_data;
2396
9f8dd319
DF		 2397 mv643xx_eth_port_disable_tx(port_num);
2398 mv643xx_eth_port_disable_rx(port_num);
1da177e4
LT		 2399
2400 /* Clear all MIB counters */
2401 eth_clear_mib_counters(port_num);
2402
2403 /* Reset the Enable bit in the Configuration Register */
2404 reg_data = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
2405 reg_data &= ~MV643XX_ETH_SERIAL_PORT_ENABLE;
2406 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), reg_data);
2407}
2408
1da177e4
LT		 2409
2410static int eth_port_autoneg_supported(unsigned int eth_port_num)
2411{
2412 unsigned int phy_reg_data0;
2413
2414 eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data0);
2415
2416 return phy_reg_data0 & 0x1000;
2417}
2418
2419static int eth_port_link_is_up(unsigned int eth_port_num)
2420{
2421 unsigned int phy_reg_data1;
2422
2423 eth_port_read_smi_reg(eth_port_num, 1, &phy_reg_data1);
2424
2425 if (eth_port_autoneg_supported(eth_port_num)) {
2426 if (phy_reg_data1 & 0x20) /* auto-neg complete */
2427 return 1;
2428 } else if (phy_reg_data1 & 0x4) /* link up */
2429 return 1;
2430
2431 return 0;
2432}
2433
1da177e4
LT		 2434/*
2435 * eth_port_read_smi_reg - Read PHY registers
2436 *
2437 * DESCRIPTION:
2438 * This routine utilize the SMI interface to interact with the PHY in
2439 * order to perform PHY register read.
2440 *
2441 * INPUT:
2442 * unsigned int port_num Ethernet Port number.
2443 * unsigned int phy_reg PHY register address offset.
2444 * unsigned int *value Register value buffer.
2445 *
2446 * OUTPUT:
2447 * Write the value of a specified PHY register into given buffer.
2448 *
2449 * RETURN:
2450 * false if the PHY is busy or read data is not in valid state.
2451 * true otherwise.
2452 *
2453 */
2454static void eth_port_read_smi_reg(unsigned int port_num,
2455 unsigned int phy_reg, unsigned int *value)
2456{
2457 int phy_addr = ethernet_phy_get(port_num);
2458 unsigned long flags;
2459 int i;
2460
2461 /* the SMI register is a shared resource */
2462 spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
2463
2464 /* wait for the SMI register to become available */
2465 for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) {
2466 if (i == PHY_WAIT_ITERATIONS) {
2467 printk("mv643xx PHY busy timeout, port %d\n", port_num);
2468 goto out;
2469 }
2470 udelay(PHY_WAIT_MICRO_SECONDS);
2471 }
2472
2473 mv_write(MV643XX_ETH_SMI_REG,
2474 (phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ);
2475
2476 /* now wait for the data to be valid */
2477 for (i = 0; !(mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_READ_VALID); i++) {
2478 if (i == PHY_WAIT_ITERATIONS) {
2479 printk("mv643xx PHY read timeout, port %d\n", port_num);
2480 goto out;
2481 }
2482 udelay(PHY_WAIT_MICRO_SECONDS);
2483 }
2484
2485 *value = mv_read(MV643XX_ETH_SMI_REG) & 0xffff;
2486out:
2487 spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
2488}
2489
2490/*
2491 * eth_port_write_smi_reg - Write to PHY registers
2492 *
2493 * DESCRIPTION:
2494 * This routine utilize the SMI interface to interact with the PHY in
2495 * order to perform writes to PHY registers.
2496 *
2497 * INPUT:
2498 * unsigned int eth_port_num Ethernet Port number.
2499 * unsigned int phy_reg PHY register address offset.
2500 * unsigned int value Register value.
2501 *
2502 * OUTPUT:
2503 * Write the given value to the specified PHY register.
2504 *
2505 * RETURN:
2506 * false if the PHY is busy.
2507 * true otherwise.
2508 *
2509 */
2510static void eth_port_write_smi_reg(unsigned int eth_port_num,
2511 unsigned int phy_reg, unsigned int value)
2512{
2513 int phy_addr;
2514 int i;
2515 unsigned long flags;
2516
2517 phy_addr = ethernet_phy_get(eth_port_num);
2518
2519 /* the SMI register is a shared resource */
2520 spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
2521
2522 /* wait for the SMI register to become available */
2523 for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) {
2524 if (i == PHY_WAIT_ITERATIONS) {
2525 printk("mv643xx PHY busy timeout, port %d\n",
2526 eth_port_num);
2527 goto out;
2528 }
2529 udelay(PHY_WAIT_MICRO_SECONDS);
2530 }
2531
2532 mv_write(MV643XX_ETH_SMI_REG, (phy_addr << 16) | (phy_reg << 21) |
2533 ETH_SMI_OPCODE_WRITE | (value & 0xffff));
2534out:
2535 spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
2536}
2537
2538/*
2539 * eth_port_send - Send an Ethernet packet
2540 *
2541 * DESCRIPTION:
2542 * This routine send a given packet described by p_pktinfo parameter. It
2543 * supports transmitting of a packet spaned over multiple buffers. The
2544 * routine updates 'curr' and 'first' indexes according to the packet
2545 * segment passed to the routine. In case the packet segment is first,
2546 * the 'first' index is update. In any case, the 'curr' index is updated.
2547 * If the routine get into Tx resource error it assigns 'curr' index as
2548 * 'first'. This way the function can abort Tx process of multiple
2549 * descriptors per packet.
2550 *
2551 * INPUT:
2552 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2553 * struct pkt_info *p_pkt_info User packet buffer.
2554 *
2555 * OUTPUT:
2556 * Tx ring 'curr' and 'first' indexes are updated.
2557 *
2558 * RETURN:
2559 * ETH_QUEUE_FULL in case of Tx resource error.
2560 * ETH_ERROR in case the routine can not access Tx desc ring.
2561 * ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource.
2562 * ETH_OK otherwise.
2563 *
2564 */
2565#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
2566/*
2567 * Modified to include the first descriptor pointer in case of SG
2568 */
2569static ETH_FUNC_RET_STATUS eth_port_send(struct mv643xx_private *mp,
2570 struct pkt_info *p_pkt_info)
2571{
2572 int tx_desc_curr, tx_desc_used, tx_first_desc, tx_next_desc;
2573 struct eth_tx_desc *current_descriptor;
2574 struct eth_tx_desc *first_descriptor;
2575 u32 command;
2576
2577 /* Do not process Tx ring in case of Tx ring resource error */
2578 if (mp->tx_resource_err)
2579 return ETH_QUEUE_FULL;
2580
2581 /*
2582 * The hardware requires that each buffer that is <= 8 bytes
2583 * in length must be aligned on an 8 byte boundary.
2584 */
2585 if (p_pkt_info->byte_cnt <= 8 && p_pkt_info->buf_ptr & 0x7) {
2586 printk(KERN_ERR
2587 "mv643xx_eth port %d: packet size <= 8 problem\n",
2588 mp->port_num);
2589 return ETH_ERROR;
2590 }
2591
f98e36f1
DF		 2592 mp->tx_desc_count++;
2593 BUG_ON(mp->tx_desc_count > mp->tx_ring_size);
b111ceb6 2594
1da177e4
LT		 2595 /* Get the Tx Desc ring indexes */
2596 tx_desc_curr = mp->tx_curr_desc_q;
2597 tx_desc_used = mp->tx_used_desc_q;
2598
2599 current_descriptor = &mp->p_tx_desc_area[tx_desc_curr];
2600
2601 tx_next_desc = (tx_desc_curr + 1) % mp->tx_ring_size;
2602
2603 current_descriptor->buf_ptr = p_pkt_info->buf_ptr;
2604 current_descriptor->byte_cnt = p_pkt_info->byte_cnt;
2605 current_descriptor->l4i_chk = p_pkt_info->l4i_chk;
2606 mp->tx_skb[tx_desc_curr] = p_pkt_info->return_info;
2607
2608 command = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC |
2609 ETH_BUFFER_OWNED_BY_DMA;
2610 if (command & ETH_TX_FIRST_DESC) {
2611 tx_first_desc = tx_desc_curr;
2612 mp->tx_first_desc_q = tx_first_desc;
2613 first_descriptor = current_descriptor;
2614 mp->tx_first_command = command;
2615 } else {
2616 tx_first_desc = mp->tx_first_desc_q;
2617 first_descriptor = &mp->p_tx_desc_area[tx_first_desc];
2618 BUG_ON(first_descriptor == NULL);
2619 current_descriptor->cmd_sts = command;
2620 }
2621
2622 if (command & ETH_TX_LAST_DESC) {
2623 wmb();
2624 first_descriptor->cmd_sts = mp->tx_first_command;
2625
2626 wmb();
9f8dd319 2627 mv643xx_eth_port_enable_tx(mp->port_num, mp->port_tx_queue_command);
1da177e4
LT		 2628
2629 /*
2630 * Finish Tx packet. Update first desc in case of Tx resource
2631 * error */
2632 tx_first_desc = tx_next_desc;
2633 mp->tx_first_desc_q = tx_first_desc;
2634 }
2635
2636 /* Check for ring index overlap in the Tx desc ring */
2637 if (tx_next_desc == tx_desc_used) {
2638 mp->tx_resource_err = 1;
2639 mp->tx_curr_desc_q = tx_first_desc;
2640
2641 return ETH_QUEUE_LAST_RESOURCE;
2642 }
2643
2644 mp->tx_curr_desc_q = tx_next_desc;
2645
2646 return ETH_OK;
2647}
2648#else
2649static ETH_FUNC_RET_STATUS eth_port_send(struct mv643xx_private *mp,
2650 struct pkt_info *p_pkt_info)
2651{
2652 int tx_desc_curr;
2653 int tx_desc_used;
2654 struct eth_tx_desc *current_descriptor;
2655 unsigned int command_status;
2656
2657 /* Do not process Tx ring in case of Tx ring resource error */
2658 if (mp->tx_resource_err)
2659 return ETH_QUEUE_FULL;
2660
f98e36f1
DF		 2661 mp->tx_desc_count++;
2662 BUG_ON(mp->tx_desc_count > mp->tx_ring_size);
b111ceb6 2663
1da177e4
LT		 2664 /* Get the Tx Desc ring indexes */
2665 tx_desc_curr = mp->tx_curr_desc_q;
2666 tx_desc_used = mp->tx_used_desc_q;
2667 current_descriptor = &mp->p_tx_desc_area[tx_desc_curr];
2668
2669 command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC;
2670 current_descriptor->buf_ptr = p_pkt_info->buf_ptr;
2671 current_descriptor->byte_cnt = p_pkt_info->byte_cnt;
2672 mp->tx_skb[tx_desc_curr] = p_pkt_info->return_info;
2673
2674 /* Set last desc with DMA ownership and interrupt enable. */
2675 wmb();
2676 current_descriptor->cmd_sts = command_status |
2677 ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT;
2678
2679 wmb();
9f8dd319 2680 mv643xx_eth_port_enable_tx(mp->port_num, mp->port_tx_queue_command);
1da177e4
LT		 2681
2682 /* Finish Tx packet. Update first desc in case of Tx resource error */
2683 tx_desc_curr = (tx_desc_curr + 1) % mp->tx_ring_size;
2684
2685 /* Update the current descriptor */
2686 mp->tx_curr_desc_q = tx_desc_curr;
2687
2688 /* Check for ring index overlap in the Tx desc ring */
2689 if (tx_desc_curr == tx_desc_used) {
2690 mp->tx_resource_err = 1;
2691 return ETH_QUEUE_LAST_RESOURCE;
2692 }
2693
2694 return ETH_OK;
2695}
2696#endif
2697
2698/*
2699 * eth_tx_return_desc - Free all used Tx descriptors
2700 *
2701 * DESCRIPTION:
2702 * This routine returns the transmitted packet information to the caller.
2703 * It uses the 'first' index to support Tx desc return in case a transmit
2704 * of a packet spanned over multiple buffer still in process.
2705 * In case the Tx queue was in "resource error" condition, where there are
2706 * no available Tx resources, the function resets the resource error flag.
2707 *
2708 * INPUT:
2709 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2710 * struct pkt_info *p_pkt_info User packet buffer.
2711 *
2712 * OUTPUT:
2713 * Tx ring 'first' and 'used' indexes are updated.
2714 *
2715 * RETURN:
8f518703
DF		 2716 * ETH_OK on success
2717 * ETH_ERROR otherwise.
1da177e4
LT		 2718 *
2719 */
2720static ETH_FUNC_RET_STATUS eth_tx_return_desc(struct mv643xx_private *mp,
2721 struct pkt_info *p_pkt_info)
2722{
2723 int tx_desc_used;
8f518703
DF		 2724 int tx_busy_desc;
2725 struct eth_tx_desc *p_tx_desc_used;
2726 unsigned int command_status;
2727 unsigned long flags;
2728 int err = ETH_OK;
2729
2730 spin_lock_irqsave(&mp->lock, flags);
2731
1da177e4 2732#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
8f518703 2733 tx_busy_desc = mp->tx_first_desc_q;
1da177e4 2734#else
8f518703 2735 tx_busy_desc = mp->tx_curr_desc_q;
1da177e4 2736#endif
1da177e4
LT		 2737
2738 /* Get the Tx Desc ring indexes */
2739 tx_desc_used = mp->tx_used_desc_q;
2740
2741 p_tx_desc_used = &mp->p_tx_desc_area[tx_desc_used];
2742
2743 /* Sanity check */
8f518703
DF		 2744 if (p_tx_desc_used == NULL) {
2745 err = ETH_ERROR;
2746 goto out;
2747 }
1da177e4
LT		 2748
2749 /* Stop release. About to overlap the current available Tx descriptor */
8f518703
DF		 2750 if (tx_desc_used == tx_busy_desc && !mp->tx_resource_err) {
2751 err = ETH_ERROR;
2752 goto out;
2753 }
1da177e4
LT		 2754
2755 command_status = p_tx_desc_used->cmd_sts;
2756
2757 /* Still transmitting... */
8f518703
DF		 2758 if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
2759 err = ETH_ERROR;
2760 goto out;
2761 }
1da177e4
LT		 2762
2763 /* Pass the packet information to the caller */
2764 p_pkt_info->cmd_sts = command_status;
2765 p_pkt_info->return_info = mp->tx_skb[tx_desc_used];
4eaa3cb3
PG		 2766 p_pkt_info->buf_ptr = p_tx_desc_used->buf_ptr;
2767 p_pkt_info->byte_cnt = p_tx_desc_used->byte_cnt;
1da177e4
LT		 2768 mp->tx_skb[tx_desc_used] = NULL;
2769
2770 /* Update the next descriptor to release. */
2771 mp->tx_used_desc_q = (tx_desc_used + 1) % mp->tx_ring_size;
2772
2773 /* Any Tx return cancels the Tx resource error status */
2774 mp->tx_resource_err = 0;
2775
f98e36f1
DF		 2776 BUG_ON(mp->tx_desc_count == 0);
2777 mp->tx_desc_count--;
b111ceb6 2778
8f518703
DF		 2779out:
2780 spin_unlock_irqrestore(&mp->lock, flags);
2781
2782 return err;
1da177e4
LT		 2783}
2784
2785/*
2786 * eth_port_receive - Get received information from Rx ring.
2787 *
2788 * DESCRIPTION:
2789 * This routine returns the received data to the caller. There is no
2790 * data copying during routine operation. All information is returned
2791 * using pointer to packet information struct passed from the caller.
2792 * If the routine exhausts Rx ring resources then the resource error flag
2793 * is set.
2794 *
2795 * INPUT:
2796 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2797 * struct pkt_info *p_pkt_info User packet buffer.
2798 *
2799 * OUTPUT:
2800 * Rx ring current and used indexes are updated.
2801 *
2802 * RETURN:
2803 * ETH_ERROR in case the routine can not access Rx desc ring.
2804 * ETH_QUEUE_FULL if Rx ring resources are exhausted.
2805 * ETH_END_OF_JOB if there is no received data.
2806 * ETH_OK otherwise.
2807 */
2808static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
2809 struct pkt_info *p_pkt_info)
2810{
2811 int rx_next_curr_desc, rx_curr_desc, rx_used_desc;
2812 volatile struct eth_rx_desc *p_rx_desc;
2813 unsigned int command_status;
8f518703 2814 unsigned long flags;
1da177e4
LT		 2815
2816 /* Do not process Rx ring in case of Rx ring resource error */
2817 if (mp->rx_resource_err)
2818 return ETH_QUEUE_FULL;
2819
8f518703
DF		 2820 spin_lock_irqsave(&mp->lock, flags);
2821
1da177e4
LT		 2822 /* Get the Rx Desc ring 'curr and 'used' indexes */
2823 rx_curr_desc = mp->rx_curr_desc_q;
2824 rx_used_desc = mp->rx_used_desc_q;
2825
2826 p_rx_desc = &mp->p_rx_desc_area[rx_curr_desc];
2827
2828 /* The following parameters are used to save readings from memory */
2829 command_status = p_rx_desc->cmd_sts;
2830 rmb();
2831
2832 /* Nothing to receive... */
8f518703
DF		 2833 if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
2834 spin_unlock_irqrestore(&mp->lock, flags);
1da177e4 2835 return ETH_END_OF_JOB;
8f518703 2836 }
1da177e4
LT		 2837
2838 p_pkt_info->byte_cnt = (p_rx_desc->byte_cnt) - RX_BUF_OFFSET;
2839 p_pkt_info->cmd_sts = command_status;
2840 p_pkt_info->buf_ptr = (p_rx_desc->buf_ptr) + RX_BUF_OFFSET;
2841 p_pkt_info->return_info = mp->rx_skb[rx_curr_desc];
2842 p_pkt_info->l4i_chk = p_rx_desc->buf_size;
2843
b4de9051
DF		 2844 /*
2845 * Clean the return info field to indicate that the
2846 * packet has been moved to the upper layers
2847 */
1da177e4
LT		 2848 mp->rx_skb[rx_curr_desc] = NULL;
2849
2850 /* Update current index in data structure */
2851 rx_next_curr_desc = (rx_curr_desc + 1) % mp->rx_ring_size;
2852 mp->rx_curr_desc_q = rx_next_curr_desc;
2853
2854 /* Rx descriptors exhausted. Set the Rx ring resource error flag */
2855 if (rx_next_curr_desc == rx_used_desc)
2856 mp->rx_resource_err = 1;
2857
8f518703
DF		 2858 spin_unlock_irqrestore(&mp->lock, flags);
2859
1da177e4
LT		 2860 return ETH_OK;
2861}
2862
2863/*
2864 * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
2865 *
2866 * DESCRIPTION:
2867 * This routine returns a Rx buffer back to the Rx ring. It retrieves the
2868 * next 'used' descriptor and attached the returned buffer to it.
2869 * In case the Rx ring was in "resource error" condition, where there are
2870 * no available Rx resources, the function resets the resource error flag.
2871 *
2872 * INPUT:
2873 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2874 * struct pkt_info *p_pkt_info Information on returned buffer.
2875 *
2876 * OUTPUT:
2877 * New available Rx resource in Rx descriptor ring.
2878 *
2879 * RETURN:
2880 * ETH_ERROR in case the routine can not access Rx desc ring.
2881 * ETH_OK otherwise.
2882 */
2883static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
2884 struct pkt_info *p_pkt_info)
2885{
2886 int used_rx_desc; /* Where to return Rx resource */
2887 volatile struct eth_rx_desc *p_used_rx_desc;
8f518703
DF		 2888 unsigned long flags;
2889
2890 spin_lock_irqsave(&mp->lock, flags);
1da177e4
LT		 2891
2892 /* Get 'used' Rx descriptor */
2893 used_rx_desc = mp->rx_used_desc_q;
2894 p_used_rx_desc = &mp->p_rx_desc_area[used_rx_desc];
2895
2896 p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
2897 p_used_rx_desc->buf_size = p_pkt_info->byte_cnt;
2898 mp->rx_skb[used_rx_desc] = p_pkt_info->return_info;
2899
2900 /* Flush the write pipe */
2901
2902 /* Return the descriptor to DMA ownership */
2903 wmb();
2904 p_used_rx_desc->cmd_sts =
2905 ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
2906 wmb();
2907
2908 /* Move the used descriptor pointer to the next descriptor */
2909 mp->rx_used_desc_q = (used_rx_desc + 1) % mp->rx_ring_size;
2910
2911 /* Any Rx return cancels the Rx resource error status */
2912 mp->rx_resource_err = 0;
2913
8f518703
DF		 2914 spin_unlock_irqrestore(&mp->lock, flags);
2915
1da177e4
LT		 2916 return ETH_OK;
2917}
2918
2919/************* Begin ethtool support *************************/
2920
2921struct mv643xx_stats {
2922 char stat_string[ETH_GSTRING_LEN];
2923 int sizeof_stat;
2924 int stat_offset;
2925};
2926
2927#define MV643XX_STAT(m) sizeof(((struct mv643xx_private *)0)->m), \
b4de9051 2928 offsetof(struct mv643xx_private, m)
1da177e4
LT		 2929
2930static const struct mv643xx_stats mv643xx_gstrings_stats[] = {
2931 { "rx_packets", MV643XX_STAT(stats.rx_packets) },
2932 { "tx_packets", MV643XX_STAT(stats.tx_packets) },
2933 { "rx_bytes", MV643XX_STAT(stats.rx_bytes) },
2934 { "tx_bytes", MV643XX_STAT(stats.tx_bytes) },
2935 { "rx_errors", MV643XX_STAT(stats.rx_errors) },
2936 { "tx_errors", MV643XX_STAT(stats.tx_errors) },
2937 { "rx_dropped", MV643XX_STAT(stats.rx_dropped) },
2938 { "tx_dropped", MV643XX_STAT(stats.tx_dropped) },
2939 { "good_octets_received", MV643XX_STAT(mib_counters.good_octets_received) },
2940 { "bad_octets_received", MV643XX_STAT(mib_counters.bad_octets_received) },
2941 { "internal_mac_transmit_err", MV643XX_STAT(mib_counters.internal_mac_transmit_err) },
2942 { "good_frames_received", MV643XX_STAT(mib_counters.good_frames_received) },
2943 { "bad_frames_received", MV643XX_STAT(mib_counters.bad_frames_received) },
2944 { "broadcast_frames_received", MV643XX_STAT(mib_counters.broadcast_frames_received) },
2945 { "multicast_frames_received", MV643XX_STAT(mib_counters.multicast_frames_received) },
2946 { "frames_64_octets", MV643XX_STAT(mib_counters.frames_64_octets) },
2947 { "frames_65_to_127_octets", MV643XX_STAT(mib_counters.frames_65_to_127_octets) },
2948 { "frames_128_to_255_octets", MV643XX_STAT(mib_counters.frames_128_to_255_octets) },
2949 { "frames_256_to_511_octets", MV643XX_STAT(mib_counters.frames_256_to_511_octets) },
2950 { "frames_512_to_1023_octets", MV643XX_STAT(mib_counters.frames_512_to_1023_octets) },
2951 { "frames_1024_to_max_octets", MV643XX_STAT(mib_counters.frames_1024_to_max_octets) },
2952 { "good_octets_sent", MV643XX_STAT(mib_counters.good_octets_sent) },
2953 { "good_frames_sent", MV643XX_STAT(mib_counters.good_frames_sent) },
2954 { "excessive_collision", MV643XX_STAT(mib_counters.excessive_collision) },
2955 { "multicast_frames_sent", MV643XX_STAT(mib_counters.multicast_frames_sent) },
2956 { "broadcast_frames_sent", MV643XX_STAT(mib_counters.broadcast_frames_sent) },
2957 { "unrec_mac_control_received", MV643XX_STAT(mib_counters.unrec_mac_control_received) },
2958 { "fc_sent", MV643XX_STAT(mib_counters.fc_sent) },
2959 { "good_fc_received", MV643XX_STAT(mib_counters.good_fc_received) },
2960 { "bad_fc_received", MV643XX_STAT(mib_counters.bad_fc_received) },
2961 { "undersize_received", MV643XX_STAT(mib_counters.undersize_received) },
2962 { "fragments_received", MV643XX_STAT(mib_counters.fragments_received) },
2963 { "oversize_received", MV643XX_STAT(mib_counters.oversize_received) },
2964 { "jabber_received", MV643XX_STAT(mib_counters.jabber_received) },
2965 { "mac_receive_error", MV643XX_STAT(mib_counters.mac_receive_error) },
2966 { "bad_crc_event", MV643XX_STAT(mib_counters.bad_crc_event) },
2967 { "collision", MV643XX_STAT(mib_counters.collision) },
2968 { "late_collision", MV643XX_STAT(mib_counters.late_collision) },
2969};
2970
2971#define MV643XX_STATS_LEN \
2972 sizeof(mv643xx_gstrings_stats) / sizeof(struct mv643xx_stats)
2973
2974static int
2975mv643xx_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
2976{
2977 struct mv643xx_private *mp = netdev->priv;
2978 int port_num = mp->port_num;
2979 int autoneg = eth_port_autoneg_supported(port_num);
2980 int mode_10_bit;
2981 int auto_duplex;
2982 int half_duplex = 0;
2983 int full_duplex = 0;
2984 int auto_speed;
2985 int speed_10 = 0;
2986 int speed_100 = 0;
2987 int speed_1000 = 0;
2988
2989 u32 pcs = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
2990 u32 psr = mv_read(MV643XX_ETH_PORT_STATUS_REG(port_num));
2991
2992 mode_10_bit = psr & MV643XX_ETH_PORT_STATUS_MODE_10_BIT;
2993
2994 if (mode_10_bit) {
2995 ecmd->supported = SUPPORTED_10baseT_Half;
2996 } else {
2997 ecmd->supported = (SUPPORTED_10baseT_Half |
2998 SUPPORTED_10baseT_Full |
2999 SUPPORTED_100baseT_Half |
3000 SUPPORTED_100baseT_Full |
3001 SUPPORTED_1000baseT_Full |
3002 (autoneg ? SUPPORTED_Autoneg : 0) |
3003 SUPPORTED_TP);
3004
3005 auto_duplex = !(pcs & MV643XX_ETH_DISABLE_AUTO_NEG_FOR_DUPLX);
3006 auto_speed = !(pcs & MV643XX_ETH_DISABLE_AUTO_NEG_SPEED_GMII);
3007
3008 ecmd->advertising = ADVERTISED_TP;
3009
3010 if (autoneg) {
3011 ecmd->advertising |= ADVERTISED_Autoneg;
3012
3013 if (auto_duplex) {
3014 half_duplex = 1;
3015 full_duplex = 1;
3016 } else {
3017 if (pcs & MV643XX_ETH_SET_FULL_DUPLEX_MODE)
3018 full_duplex = 1;
3019 else
3020 half_duplex = 1;
3021 }
3022
3023 if (auto_speed) {
3024 speed_10 = 1;
3025 speed_100 = 1;
3026 speed_1000 = 1;
3027 } else {
3028 if (pcs & MV643XX_ETH_SET_GMII_SPEED_TO_1000)
3029 speed_1000 = 1;
3030 else if (pcs & MV643XX_ETH_SET_MII_SPEED_TO_100)
3031 speed_100 = 1;
3032 else
3033 speed_10 = 1;
3034 }
3035
3036 if (speed_10 & half_duplex)
3037 ecmd->advertising |= ADVERTISED_10baseT_Half;
3038 if (speed_10 & full_duplex)
3039 ecmd->advertising |= ADVERTISED_10baseT_Full;
3040 if (speed_100 & half_duplex)
3041 ecmd->advertising |= ADVERTISED_100baseT_Half;
3042 if (speed_100 & full_duplex)
3043 ecmd->advertising |= ADVERTISED_100baseT_Full;
3044 if (speed_1000)
3045 ecmd->advertising |= ADVERTISED_1000baseT_Full;
3046 }
3047 }
3048
3049 ecmd->port = PORT_TP;
3050 ecmd->phy_address = ethernet_phy_get(port_num);
3051
3052 ecmd->transceiver = XCVR_EXTERNAL;
3053
3054 if (netif_carrier_ok(netdev)) {
3055 if (mode_10_bit)
3056 ecmd->speed = SPEED_10;
3057 else {
3058 if (psr & MV643XX_ETH_PORT_STATUS_GMII_1000)
3059 ecmd->speed = SPEED_1000;
3060 else if (psr & MV643XX_ETH_PORT_STATUS_MII_100)
3061 ecmd->speed = SPEED_100;
3062 else
3063 ecmd->speed = SPEED_10;
3064 }
3065
3066 if (psr & MV643XX_ETH_PORT_STATUS_FULL_DUPLEX)
3067 ecmd->duplex = DUPLEX_FULL;
3068 else
3069 ecmd->duplex = DUPLEX_HALF;
3070 } else {
3071 ecmd->speed = -1;
3072 ecmd->duplex = -1;
3073 }
3074
3075 ecmd->autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3076 return 0;
3077}
3078
b4de9051
DF		 3079static void mv643xx_get_drvinfo(struct net_device *netdev,
3080 struct ethtool_drvinfo *drvinfo)
1da177e4
LT		 3081{
3082 strncpy(drvinfo->driver, mv643xx_driver_name, 32);
3083 strncpy(drvinfo->version, mv643xx_driver_version, 32);
3084 strncpy(drvinfo->fw_version, "N/A", 32);
3085 strncpy(drvinfo->bus_info, "mv643xx", 32);
3086 drvinfo->n_stats = MV643XX_STATS_LEN;
3087}
3088
b4de9051 3089static int mv643xx_get_stats_count(struct net_device *netdev)
1da177e4
LT		 3090{
3091 return MV643XX_STATS_LEN;
3092}
3093
b4de9051
DF		 3094static void mv643xx_get_ethtool_stats(struct net_device *netdev,
3095 struct ethtool_stats *stats, uint64_t *data)
1da177e4
LT		 3096{
3097 struct mv643xx_private *mp = netdev->priv;
3098 int i;
3099
3100 eth_update_mib_counters(mp);
3101
b4de9051 3102 for (i = 0; i < MV643XX_STATS_LEN; i++) {
1da177e4 3103 char *p = (char *)mp+mv643xx_gstrings_stats[i].stat_offset;
b4de9051 3104 data[i] = (mv643xx_gstrings_stats[i].sizeof_stat ==
1da177e4
LT		 3105 sizeof(uint64_t)) ? *(uint64_t *)p : *(uint32_t *)p;
3106 }
3107}
3108
b4de9051
DF		 3109static void mv643xx_get_strings(struct net_device *netdev, uint32_t stringset,
3110 uint8_t *data)
1da177e4
LT		 3111{
3112 int i;
3113
3114 switch(stringset) {
3115 case ETH_SS_STATS:
3116 for (i=0; i < MV643XX_STATS_LEN; i++) {
b4de9051
DF		 3117 memcpy(data + i * ETH_GSTRING_LEN,
3118 mv643xx_gstrings_stats[i].stat_string,
3119 ETH_GSTRING_LEN);
1da177e4
LT		 3120 }
3121 break;
3122 }
3123}
3124
3125static struct ethtool_ops mv643xx_ethtool_ops = {
3126 .get_settings = mv643xx_get_settings,
3127 .get_drvinfo = mv643xx_get_drvinfo,
3128 .get_link = ethtool_op_get_link,
3129 .get_sg = ethtool_op_get_sg,
3130 .set_sg = ethtool_op_set_sg,
3131 .get_strings = mv643xx_get_strings,
3132 .get_stats_count = mv643xx_get_stats_count,
3133 .get_ethtool_stats = mv643xx_get_ethtool_stats,
3134};
3135
3136/************* End ethtool support *************************/
Linux 6.x block layer and io_uring tree(s)