projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
mv643xx_eth: fix NULL pointer dereference in rxq_process()
[linux-2.6-block.git] / drivers / net / mv643xx_eth.c
CommitLineData
1da177e4 1/*
9c1bbdfe 2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
1da177e4
LT		 3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
4547fa61
LB		 6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
1da177e4
LT		 8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
3bb8a18a 10 * written by Manish Lachwani
1da177e4
LT		 11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
c8aaea25 14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
1da177e4
LT		 15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
4547fa61
LB		 20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
1da177e4
LT		 23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36 */
a779d38c 37
1da177e4
LT		 38#include <linux/init.h>
39#include <linux/dma-mapping.h>
b6298c22 40#include <linux/in.h>
1da177e4
LT		 41#include <linux/tcp.h>
42#include <linux/udp.h>
43#include <linux/etherdevice.h>
1da177e4
LT		 44#include <linux/delay.h>
45#include <linux/ethtool.h>
d052d1be 46#include <linux/platform_device.h>
fbd6a754
LB		 47#include <linux/module.h>
48#include <linux/kernel.h>
49#include <linux/spinlock.h>
50#include <linux/workqueue.h>
51#include <linux/mii.h>
fbd6a754 52#include <linux/mv643xx_eth.h>
1da177e4
LT		 53#include <asm/io.h>
54#include <asm/types.h>
1da177e4 55#include <asm/system.h>
fbd6a754 56
e5371493 57static char mv643xx_eth_driver_name[] = "mv643xx_eth";
ac0a2d0c 58static char mv643xx_eth_driver_version[] = "1.2";
c9df406f 59
e5371493
LB		 60#define MV643XX_ETH_CHECKSUM_OFFLOAD_TX
61#define MV643XX_ETH_NAPI
62#define MV643XX_ETH_TX_FAST_REFILL
fbd6a754 63
e5371493 64#ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
fbd6a754
LB		 65#define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
66#else
67#define MAX_DESCS_PER_SKB 1
68#endif
69
fbd6a754
LB		 70/*
71 * Registers shared between all ports.
72 */
3cb4667c
LB		 73#define PHY_ADDR 0x0000
74#define SMI_REG 0x0004
75#define WINDOW_BASE(w) (0x0200 + ((w) << 3))
76#define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
77#define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
78#define WINDOW_BAR_ENABLE 0x0290
79#define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
fbd6a754
LB		 80
81/*
82 * Per-port registers.
83 */
3cb4667c 84#define PORT_CONFIG(p) (0x0400 + ((p) << 10))
d9a073ea 85#define UNICAST_PROMISCUOUS_MODE 0x00000001
3cb4667c
LB		 86#define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
87#define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
88#define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
89#define SDMA_CONFIG(p) (0x041c + ((p) << 10))
90#define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
91#define PORT_STATUS(p) (0x0444 + ((p) << 10))
a2a41689 92#define TX_FIFO_EMPTY 0x00000400
ae9ae064 93#define TX_IN_PROGRESS 0x00000080
2f7eb47a
LB		 94#define PORT_SPEED_MASK 0x00000030
95#define PORT_SPEED_1000 0x00000010
96#define PORT_SPEED_100 0x00000020
97#define PORT_SPEED_10 0x00000000
98#define FLOW_CONTROL_ENABLED 0x00000008
99#define FULL_DUPLEX 0x00000004
81600eea 100#define LINK_UP 0x00000002
3cb4667c 101#define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
89df5fdc
LB		 102#define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10))
103#define TX_BW_RATE(p) (0x0450 + ((p) << 10))
3cb4667c 104#define TX_BW_MTU(p) (0x0458 + ((p) << 10))
89df5fdc 105#define TX_BW_BURST(p) (0x045c + ((p) << 10))
3cb4667c 106#define INT_CAUSE(p) (0x0460 + ((p) << 10))
8fa89bf5 107#define INT_TX_END_0 0x00080000
226bb6b7 108#define INT_TX_END 0x07f80000
64da80a2 109#define INT_RX 0x0007fbfc
073a345c 110#define INT_EXT 0x00000002
3cb4667c 111#define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
073a345c
LB		 112#define INT_EXT_LINK 0x00100000
113#define INT_EXT_PHY 0x00010000
114#define INT_EXT_TX_ERROR_0 0x00000100
115#define INT_EXT_TX_0 0x00000001
3d6b35bc 116#define INT_EXT_TX 0x0000ffff
3cb4667c
LB		 117#define INT_MASK(p) (0x0468 + ((p) << 10))
118#define INT_MASK_EXT(p) (0x046c + ((p) << 10))
119#define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
1e881592
LB		 120#define TXQ_FIX_PRIO_CONF_MOVED(p) (0x04dc + ((p) << 10))
121#define TX_BW_RATE_MOVED(p) (0x04e0 + ((p) << 10))
122#define TX_BW_MTU_MOVED(p) (0x04e8 + ((p) << 10))
123#define TX_BW_BURST_MOVED(p) (0x04ec + ((p) << 10))
64da80a2 124#define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4))
3cb4667c 125#define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
3d6b35bc
LB		 126#define TXQ_CURRENT_DESC_PTR(p, q) (0x06c0 + ((p) << 10) + ((q) << 2))
127#define TXQ_BW_TOKENS(p, q) (0x0700 + ((p) << 10) + ((q) << 4))
128#define TXQ_BW_CONF(p, q) (0x0704 + ((p) << 10) + ((q) << 4))
129#define TXQ_BW_WRR_CONF(p, q) (0x0708 + ((p) << 10) + ((q) << 4))
3cb4667c
LB		 130#define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
131#define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
132#define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
133#define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
fbd6a754 134
2679a550
LB		 135
136/*
137 * SDMA configuration register.
138 */
cd4ccf76 139#define RX_BURST_SIZE_16_64BIT (4 << 1)
fbd6a754 140#define BLM_RX_NO_SWAP (1 << 4)
fbd6a754 141#define BLM_TX_NO_SWAP (1 << 5)
cd4ccf76 142#define TX_BURST_SIZE_16_64BIT (4 << 22)
fbd6a754
LB		 143
144#if defined(__BIG_ENDIAN)
145#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
cd4ccf76
LB		 146 RX_BURST_SIZE_16_64BIT | \
147 TX_BURST_SIZE_16_64BIT
fbd6a754
LB		 148#elif defined(__LITTLE_ENDIAN)
149#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
cd4ccf76 150 RX_BURST_SIZE_16_64BIT | \
fbd6a754
LB		 151 BLM_RX_NO_SWAP | \
152 BLM_TX_NO_SWAP | \
cd4ccf76 153 TX_BURST_SIZE_16_64BIT
fbd6a754
LB		 154#else
155#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
156#endif
157
2beff77b
LB		 158
159/*
160 * Port serial control register.
161 */
162#define SET_MII_SPEED_TO_100 (1 << 24)
163#define SET_GMII_SPEED_TO_1000 (1 << 23)
164#define SET_FULL_DUPLEX_MODE (1 << 21)
fbd6a754 165#define MAX_RX_PACKET_9700BYTE (5 << 17)
2beff77b
LB		 166#define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
167#define DO_NOT_FORCE_LINK_FAIL (1 << 10)
168#define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
169#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
170#define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
171#define FORCE_LINK_PASS (1 << 1)
172#define SERIAL_PORT_ENABLE (1 << 0)
fbd6a754 173
cc9754b3
LB		 174#define DEFAULT_RX_QUEUE_SIZE 400
175#define DEFAULT_TX_QUEUE_SIZE 800
fbd6a754 176
fbd6a754 177
7ca72a3b
LB		 178/*
179 * RX/TX descriptors.
fbd6a754
LB		 180 */
181#if defined(__BIG_ENDIAN)
cc9754b3 182struct rx_desc {
fbd6a754
LB		 183 u16 byte_cnt; /* Descriptor buffer byte count */
184 u16 buf_size; /* Buffer size */
185 u32 cmd_sts; /* Descriptor command status */
186 u32 next_desc_ptr; /* Next descriptor pointer */
187 u32 buf_ptr; /* Descriptor buffer pointer */
188};
189
cc9754b3 190struct tx_desc {
fbd6a754
LB		 191 u16 byte_cnt; /* buffer byte count */
192 u16 l4i_chk; /* CPU provided TCP checksum */
193 u32 cmd_sts; /* Command/status field */
194 u32 next_desc_ptr; /* Pointer to next descriptor */
195 u32 buf_ptr; /* pointer to buffer for this descriptor*/
196};
197#elif defined(__LITTLE_ENDIAN)
cc9754b3 198struct rx_desc {
fbd6a754
LB		 199 u32 cmd_sts; /* Descriptor command status */
200 u16 buf_size; /* Buffer size */
201 u16 byte_cnt; /* Descriptor buffer byte count */
202 u32 buf_ptr; /* Descriptor buffer pointer */
203 u32 next_desc_ptr; /* Next descriptor pointer */
204};
205
cc9754b3 206struct tx_desc {
fbd6a754
LB		 207 u32 cmd_sts; /* Command/status field */
208 u16 l4i_chk; /* CPU provided TCP checksum */
209 u16 byte_cnt; /* buffer byte count */
210 u32 buf_ptr; /* pointer to buffer for this descriptor*/
211 u32 next_desc_ptr; /* Pointer to next descriptor */
212};
213#else
214#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
215#endif
216
7ca72a3b 217/* RX & TX descriptor command */
cc9754b3 218#define BUFFER_OWNED_BY_DMA 0x80000000
7ca72a3b
LB		 219
220/* RX & TX descriptor status */
cc9754b3 221#define ERROR_SUMMARY 0x00000001
7ca72a3b
LB		 222
223/* RX descriptor status */
cc9754b3
LB		 224#define LAYER_4_CHECKSUM_OK 0x40000000
225#define RX_ENABLE_INTERRUPT 0x20000000
226#define RX_FIRST_DESC 0x08000000
227#define RX_LAST_DESC 0x04000000
7ca72a3b
LB		 228
229/* TX descriptor command */
cc9754b3
LB		 230#define TX_ENABLE_INTERRUPT 0x00800000
231#define GEN_CRC 0x00400000
232#define TX_FIRST_DESC 0x00200000
233#define TX_LAST_DESC 0x00100000
234#define ZERO_PADDING 0x00080000
235#define GEN_IP_V4_CHECKSUM 0x00040000
236#define GEN_TCP_UDP_CHECKSUM 0x00020000
237#define UDP_FRAME 0x00010000
e32b6617
LB		 238#define MAC_HDR_EXTRA_4_BYTES 0x00008000
239#define MAC_HDR_EXTRA_8_BYTES 0x00000200
7ca72a3b 240
cc9754b3 241#define TX_IHL_SHIFT 11
7ca72a3b
LB		 242
243
c9df406f 244/* global *******************************************************************/
e5371493 245struct mv643xx_eth_shared_private {
fc32b0e2
LB		 246 /*
247 * Ethernet controller base address.
248 */
cc9754b3 249 void __iomem *base;
c9df406f 250
fc32b0e2
LB		 251 /*
252 * Protects access to SMI_REG, which is shared between ports.
253 */
c9df406f
LB		 254 spinlock_t phy_lock;
255
fc32b0e2
LB		 256 /*
257 * Per-port MBUS window access register value.
258 */
c9df406f
LB		 259 u32 win_protect;
260
fc32b0e2
LB		 261 /*
262 * Hardware-specific parameters.
263 */
c9df406f 264 unsigned int t_clk;
773fc3ee 265 int extended_rx_coal_limit;
1e881592 266 int tx_bw_control_moved;
c9df406f
LB		 267};
268
269
270/* per-port *****************************************************************/
e5371493 271struct mib_counters {
fbd6a754
LB		 272 u64 good_octets_received;
273 u32 bad_octets_received;
274 u32 internal_mac_transmit_err;
275 u32 good_frames_received;
276 u32 bad_frames_received;
277 u32 broadcast_frames_received;
278 u32 multicast_frames_received;
279 u32 frames_64_octets;
280 u32 frames_65_to_127_octets;
281 u32 frames_128_to_255_octets;
282 u32 frames_256_to_511_octets;
283 u32 frames_512_to_1023_octets;
284 u32 frames_1024_to_max_octets;
285 u64 good_octets_sent;
286 u32 good_frames_sent;
287 u32 excessive_collision;
288 u32 multicast_frames_sent;
289 u32 broadcast_frames_sent;
290 u32 unrec_mac_control_received;
291 u32 fc_sent;
292 u32 good_fc_received;
293 u32 bad_fc_received;
294 u32 undersize_received;
295 u32 fragments_received;
296 u32 oversize_received;
297 u32 jabber_received;
298 u32 mac_receive_error;
299 u32 bad_crc_event;
300 u32 collision;
301 u32 late_collision;
302};
303
8a578111 304struct rx_queue {
64da80a2
LB		 305 int index;
306
8a578111
LB		 307 int rx_ring_size;
308
309 int rx_desc_count;
310 int rx_curr_desc;
311 int rx_used_desc;
312
313 struct rx_desc *rx_desc_area;
314 dma_addr_t rx_desc_dma;
315 int rx_desc_area_size;
316 struct sk_buff **rx_skb;
317
318 struct timer_list rx_oom;
319};
320
13d64285 321struct tx_queue {
3d6b35bc
LB		 322 int index;
323
13d64285 324 int tx_ring_size;
fbd6a754 325
13d64285
LB		 326 int tx_desc_count;
327 int tx_curr_desc;
328 int tx_used_desc;
fbd6a754 329
5daffe94 330 struct tx_desc *tx_desc_area;
fbd6a754
LB		 331 dma_addr_t tx_desc_dma;
332 int tx_desc_area_size;
333 struct sk_buff **tx_skb;
13d64285
LB		 334};
335
336struct mv643xx_eth_private {
337 struct mv643xx_eth_shared_private *shared;
fc32b0e2 338 int port_num;
13d64285 339
fc32b0e2 340 struct net_device *dev;
fbd6a754 341
fc32b0e2
LB		 342 struct mv643xx_eth_shared_private *shared_smi;
343 int phy_addr;
fbd6a754 344
fbd6a754 345 spinlock_t lock;
fbd6a754 346
fc32b0e2
LB		 347 struct mib_counters mib_counters;
348 struct work_struct tx_timeout_task;
fbd6a754 349 struct mii_if_info mii;
8a578111
LB		 350
351 /*
352 * RX state.
353 */
354 int default_rx_ring_size;
355 unsigned long rx_desc_sram_addr;
356 int rx_desc_sram_size;
64da80a2
LB		 357 u8 rxq_mask;
358 int rxq_primary;
8a578111 359 struct napi_struct napi;
64da80a2 360 struct rx_queue rxq[8];
13d64285
LB		 361
362 /*
363 * TX state.
364 */
365 int default_tx_ring_size;
366 unsigned long tx_desc_sram_addr;
367 int tx_desc_sram_size;
3d6b35bc
LB		 368 u8 txq_mask;
369 int txq_primary;
370 struct tx_queue txq[8];
13d64285
LB		 371#ifdef MV643XX_ETH_TX_FAST_REFILL
372 int tx_clean_threshold;
373#endif
fbd6a754 374};
1da177e4 375
fbd6a754 376
c9df406f 377/* port register accessors **************************************************/
e5371493 378static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
c9df406f 379{
cc9754b3 380 return readl(mp->shared->base + offset);
c9df406f 381}
fbd6a754 382
e5371493 383static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
c9df406f 384{
cc9754b3 385 writel(data, mp->shared->base + offset);
c9df406f 386}
fbd6a754 387
fbd6a754 388
c9df406f 389/* rxq/txq helper functions *************************************************/
8a578111 390static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
c9df406f 391{
64da80a2 392 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
c9df406f 393}
fbd6a754 394
13d64285
LB		 395static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
396{
3d6b35bc 397 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
13d64285
LB		 398}
399
8a578111 400static void rxq_enable(struct rx_queue *rxq)
c9df406f 401{
8a578111 402 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
64da80a2 403 wrl(mp, RXQ_COMMAND(mp->port_num), 1 << rxq->index);
8a578111 404}
1da177e4 405
8a578111
LB		 406static void rxq_disable(struct rx_queue *rxq)
407{
408 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
64da80a2 409 u8 mask = 1 << rxq->index;
1da177e4 410
8a578111
LB		 411 wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8);
412 while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask)
413 udelay(10);
c9df406f
LB		 414}
415
6b368f68
LB		 416static void txq_reset_hw_ptr(struct tx_queue *txq)
417{
418 struct mv643xx_eth_private *mp = txq_to_mp(txq);
419 int off = TXQ_CURRENT_DESC_PTR(mp->port_num, txq->index);
420 u32 addr;
421
422 addr = (u32)txq->tx_desc_dma;
423 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
424 wrl(mp, off, addr);
425}
426
13d64285 427static void txq_enable(struct tx_queue *txq)
1da177e4 428{
13d64285 429 struct mv643xx_eth_private *mp = txq_to_mp(txq);
3d6b35bc 430 wrl(mp, TXQ_COMMAND(mp->port_num), 1 << txq->index);
1da177e4
LT		 431}
432
13d64285 433static void txq_disable(struct tx_queue *txq)
1da177e4 434{
13d64285 435 struct mv643xx_eth_private *mp = txq_to_mp(txq);
3d6b35bc 436 u8 mask = 1 << txq->index;
c9df406f 437
13d64285
LB		 438 wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8);
439 while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask)
440 udelay(10);
441}
442
443static void __txq_maybe_wake(struct tx_queue *txq)
444{
445 struct mv643xx_eth_private *mp = txq_to_mp(txq);
446
3d6b35bc
LB		 447 /*
448 * netif_{stop,wake}_queue() flow control only applies to
449 * the primary queue.
450 */
451 BUG_ON(txq->index != mp->txq_primary);
452
13d64285
LB		 453 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_DESCS_PER_SKB)
454 netif_wake_queue(mp->dev);
1da177e4
LT		 455}
456
c9df406f
LB		 457
458/* rx ***********************************************************************/
13d64285 459static void txq_reclaim(struct tx_queue *txq, int force);
c9df406f 460
8a578111 461static void rxq_refill(struct rx_queue *rxq)
1da177e4 462{
8a578111 463 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
c9df406f 464 unsigned long flags;
1da177e4 465
c9df406f 466 spin_lock_irqsave(&mp->lock, flags);
c0d0f2ca 467
8a578111
LB		 468 while (rxq->rx_desc_count < rxq->rx_ring_size) {
469 int skb_size;
de34f225
LB		 470 struct sk_buff *skb;
471 int unaligned;
472 int rx;
473
8a578111
LB		 474 /*
475 * Reserve 2+14 bytes for an ethernet header (the
476 * hardware automatically prepends 2 bytes of dummy
477 * data to each received packet), 4 bytes for a VLAN
478 * header, and 4 bytes for the trailing FCS -- 24
479 * bytes total.
480 */
481 skb_size = mp->dev->mtu + 24;
482
483 skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1);
de34f225 484 if (skb == NULL)
1da177e4 485 break;
de34f225 486
908b637f 487 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
b44cd572 488 if (unaligned)
908b637f 489 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
de34f225 490
8a578111
LB		 491 rxq->rx_desc_count++;
492 rx = rxq->rx_used_desc;
493 rxq->rx_used_desc = (rx + 1) % rxq->rx_ring_size;
de34f225 494
8a578111
LB		 495 rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
496 skb_size, DMA_FROM_DEVICE);
497 rxq->rx_desc_area[rx].buf_size = skb_size;
498 rxq->rx_skb[rx] = skb;
de34f225 499 wmb();
8a578111 500 rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
de34f225
LB		 501 RX_ENABLE_INTERRUPT;
502 wmb();
503
fc32b0e2
LB		 504 /*
505 * The hardware automatically prepends 2 bytes of
506 * dummy data to each received packet, so that the
507 * IP header ends up 16-byte aligned.
508 */
509 skb_reserve(skb, 2);
1da177e4 510 }
de34f225 511
92c70f27
LB		 512 if (rxq->rx_desc_count != rxq->rx_ring_size)
513 mod_timer(&rxq->rx_oom, jiffies + (HZ / 10));
de34f225
LB		 514
515 spin_unlock_irqrestore(&mp->lock, flags);
1da177e4
LT		 516}
517
8a578111 518static inline void rxq_refill_timer_wrapper(unsigned long data)
1da177e4 519{
8a578111 520 rxq_refill((struct rx_queue *)data);
1da177e4
LT		 521}
522
8a578111 523static int rxq_process(struct rx_queue *rxq, int budget)
1da177e4 524{
8a578111
LB		 525 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
526 struct net_device_stats *stats = &mp->dev->stats;
527 int rx;
1da177e4 528
8a578111 529 rx = 0;
9e1f3772 530 while (rx < budget && rxq->rx_desc_count) {
fc32b0e2 531 struct rx_desc *rx_desc;
96587661 532 unsigned int cmd_sts;
fc32b0e2 533 struct sk_buff *skb;
96587661 534 unsigned long flags;
d344bff9 535
96587661 536 spin_lock_irqsave(&mp->lock, flags);
ff561eef 537
8a578111 538 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
1da177e4 539
96587661
LB		 540 cmd_sts = rx_desc->cmd_sts;
541 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
542 spin_unlock_irqrestore(&mp->lock, flags);
543 break;
544 }
545 rmb();
1da177e4 546
8a578111
LB		 547 skb = rxq->rx_skb[rxq->rx_curr_desc];
548 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
ff561eef 549
8a578111 550 rxq->rx_curr_desc = (rxq->rx_curr_desc + 1) % rxq->rx_ring_size;
ff561eef 551
96587661 552 spin_unlock_irqrestore(&mp->lock, flags);
1da177e4 553
fc32b0e2
LB		 554 dma_unmap_single(NULL, rx_desc->buf_ptr + 2,
555 mp->dev->mtu + 24, DMA_FROM_DEVICE);
8a578111
LB		 556 rxq->rx_desc_count--;
557 rx++;
b1dd9ca1 558
468d09f8
DF		 559 /*
560 * Update statistics.
fc32b0e2
LB		 561 *
562 * Note that the descriptor byte count includes 2 dummy
563 * bytes automatically inserted by the hardware at the
564 * start of the packet (which we don't count), and a 4
565 * byte CRC at the end of the packet (which we do count).
468d09f8 566 */
1da177e4 567 stats->rx_packets++;
fc32b0e2 568 stats->rx_bytes += rx_desc->byte_cnt - 2;
96587661 569
1da177e4 570 /*
fc32b0e2
LB		 571 * In case we received a packet without first / last bits
572 * on, or the error summary bit is set, the packet needs
573 * to be dropped.
1da177e4 574 */
96587661 575 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
cc9754b3 576 (RX_FIRST_DESC | RX_LAST_DESC))
96587661 577 || (cmd_sts & ERROR_SUMMARY)) {
1da177e4 578 stats->rx_dropped++;
fc32b0e2 579
96587661 580 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
cc9754b3 581 (RX_FIRST_DESC | RX_LAST_DESC)) {
1da177e4 582 if (net_ratelimit())
fc32b0e2
LB		 583 dev_printk(KERN_ERR, &mp->dev->dev,
584 "received packet spanning "
585 "multiple descriptors\n");
1da177e4 586 }
fc32b0e2 587
96587661 588 if (cmd_sts & ERROR_SUMMARY)
1da177e4
LT		 589 stats->rx_errors++;
590
591 dev_kfree_skb_irq(skb);
592 } else {
593 /*
594 * The -4 is for the CRC in the trailer of the
595 * received packet
596 */
fc32b0e2 597 skb_put(skb, rx_desc->byte_cnt - 2 - 4);
1da177e4 598
96587661 599 if (cmd_sts & LAYER_4_CHECKSUM_OK) {
1da177e4
LT		 600 skb->ip_summed = CHECKSUM_UNNECESSARY;
601 skb->csum = htons(
96587661 602 (cmd_sts & 0x0007fff8) >> 3);
1da177e4 603 }
8a578111 604 skb->protocol = eth_type_trans(skb, mp->dev);
e5371493 605#ifdef MV643XX_ETH_NAPI
1da177e4
LT		 606 netif_receive_skb(skb);
607#else
608 netif_rx(skb);
609#endif
610 }
fc32b0e2 611
8a578111 612 mp->dev->last_rx = jiffies;
1da177e4 613 }
fc32b0e2 614
8a578111 615 rxq_refill(rxq);
1da177e4 616
8a578111 617 return rx;
1da177e4
LT		 618}
619
e5371493 620#ifdef MV643XX_ETH_NAPI
e5371493 621static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
d0412d96 622{
8a578111
LB		 623 struct mv643xx_eth_private *mp;
624 int rx;
64da80a2 625 int i;
8a578111
LB		 626
627 mp = container_of(napi, struct mv643xx_eth_private, napi);
d0412d96 628
e5371493 629#ifdef MV643XX_ETH_TX_FAST_REFILL
c9df406f 630 if (++mp->tx_clean_threshold > 5) {
c9df406f 631 mp->tx_clean_threshold = 0;
3d6b35bc
LB		 632 for (i = 0; i < 8; i++)
633 if (mp->txq_mask & (1 << i))
634 txq_reclaim(mp->txq + i, 0);
4dfc1c87
LB		 635
636 if (netif_carrier_ok(mp->dev)) {
8e0b1bf6 637 spin_lock_irq(&mp->lock);
4dfc1c87 638 __txq_maybe_wake(mp->txq + mp->txq_primary);
8e0b1bf6 639 spin_unlock_irq(&mp->lock);
4dfc1c87 640 }
d0412d96 641 }
c9df406f 642#endif
d0412d96 643
64da80a2
LB		 644 rx = 0;
645 for (i = 7; rx < budget && i >= 0; i--)
646 if (mp->rxq_mask & (1 << i))
647 rx += rxq_process(mp->rxq + i, budget - rx);
d0412d96 648
8a578111
LB		 649 if (rx < budget) {
650 netif_rx_complete(mp->dev, napi);
226bb6b7 651 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
d0412d96 652 }
c9df406f 653
8a578111 654 return rx;
d0412d96 655}
c9df406f 656#endif
d0412d96 657
c9df406f
LB		 658
659/* tx ***********************************************************************/
c9df406f 660static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1da177e4 661{
13d64285 662 int frag;
1da177e4 663
c9df406f 664 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
13d64285
LB		 665 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
666 if (fragp->size <= 8 && fragp->page_offset & 7)
c9df406f 667 return 1;
1da177e4 668 }
13d64285 669
c9df406f
LB		 670 return 0;
671}
7303fde8 672
13d64285 673static int txq_alloc_desc_index(struct tx_queue *txq)
c9df406f
LB		 674{
675 int tx_desc_curr;
d0412d96 676
13d64285 677 BUG_ON(txq->tx_desc_count >= txq->tx_ring_size);
1da177e4 678
13d64285
LB		 679 tx_desc_curr = txq->tx_curr_desc;
680 txq->tx_curr_desc = (tx_desc_curr + 1) % txq->tx_ring_size;
e4d00fa9 681
13d64285 682 BUG_ON(txq->tx_curr_desc == txq->tx_used_desc);
468d09f8 683
c9df406f
LB		 684 return tx_desc_curr;
685}
468d09f8 686
13d64285 687static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
c9df406f 688{
13d64285 689 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 690 int frag;
1da177e4 691
13d64285
LB		 692 for (frag = 0; frag < nr_frags; frag++) {
693 skb_frag_t *this_frag;
694 int tx_index;
695 struct tx_desc *desc;
696
697 this_frag = &skb_shinfo(skb)->frags[frag];
698 tx_index = txq_alloc_desc_index(txq);
699 desc = &txq->tx_desc_area[tx_index];
700
701 /*
702 * The last fragment will generate an interrupt
703 * which will free the skb on TX completion.
704 */
705 if (frag == nr_frags - 1) {
706 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
707 ZERO_PADDING | TX_LAST_DESC |
708 TX_ENABLE_INTERRUPT;
709 txq->tx_skb[tx_index] = skb;
710 } else {
711 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
712 txq->tx_skb[tx_index] = NULL;
713 }
714
c9df406f
LB		 715 desc->l4i_chk = 0;
716 desc->byte_cnt = this_frag->size;
717 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
718 this_frag->page_offset,
719 this_frag->size,
720 DMA_TO_DEVICE);
721 }
1da177e4
LT		 722}
723
c9df406f
LB		 724static inline __be16 sum16_as_be(__sum16 sum)
725{
726 return (__force __be16)sum;
727}
1da177e4 728
13d64285 729static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
1da177e4 730{
8fa89bf5 731 struct mv643xx_eth_private *mp = txq_to_mp(txq);
13d64285 732 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 733 int tx_index;
cc9754b3 734 struct tx_desc *desc;
c9df406f
LB		 735 u32 cmd_sts;
736 int length;
1da177e4 737
cc9754b3 738 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
1da177e4 739
13d64285
LB		 740 tx_index = txq_alloc_desc_index(txq);
741 desc = &txq->tx_desc_area[tx_index];
c9df406f
LB		 742
743 if (nr_frags) {
13d64285 744 txq_submit_frag_skb(txq, skb);
c9df406f
LB		 745
746 length = skb_headlen(skb);
13d64285 747 txq->tx_skb[tx_index] = NULL;
c9df406f 748 } else {
cc9754b3 749 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
c9df406f 750 length = skb->len;
13d64285 751 txq->tx_skb[tx_index] = skb;
c9df406f
LB		 752 }
753
754 desc->byte_cnt = length;
755 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
756
757 if (skb->ip_summed == CHECKSUM_PARTIAL) {
e32b6617
LB		 758 int mac_hdr_len;
759
760 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
761 skb->protocol != htons(ETH_P_8021Q));
c9df406f 762
cc9754b3
LB		 763 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
764 GEN_IP_V4_CHECKSUM |
765 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
c9df406f 766
e32b6617
LB		 767 mac_hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
768 switch (mac_hdr_len - ETH_HLEN) {
769 case 0:
770 break;
771 case 4:
772 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
773 break;
774 case 8:
775 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
776 break;
777 case 12:
778 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
779 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
780 break;
781 default:
782 if (net_ratelimit())
783 dev_printk(KERN_ERR, &txq_to_mp(txq)->dev->dev,
784 "mac header length is %d?!\n", mac_hdr_len);
785 break;
786 }
787
c9df406f
LB		 788 switch (ip_hdr(skb)->protocol) {
789 case IPPROTO_UDP:
cc9754b3 790 cmd_sts |= UDP_FRAME;
c9df406f
LB		 791 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
792 break;
793 case IPPROTO_TCP:
794 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
795 break;
796 default:
797 BUG();
798 }
799 } else {
800 /* Errata BTS #50, IHL must be 5 if no HW checksum */
cc9754b3 801 cmd_sts |= 5 << TX_IHL_SHIFT;
c9df406f
LB		 802 desc->l4i_chk = 0;
803 }
804
805 /* ensure all other descriptors are written before first cmd_sts */
806 wmb();
807 desc->cmd_sts = cmd_sts;
808
8fa89bf5
LB		 809 /* clear TX_END interrupt status */
810 wrl(mp, INT_CAUSE(mp->port_num), ~(INT_TX_END_0 << txq->index));
811 rdl(mp, INT_CAUSE(mp->port_num));
812
c9df406f
LB		 813 /* ensure all descriptors are written before poking hardware */
814 wmb();
13d64285 815 txq_enable(txq);
c9df406f 816
13d64285 817 txq->tx_desc_count += nr_frags + 1;
1da177e4 818}
1da177e4 819
fc32b0e2 820static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 821{
e5371493 822 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 823 struct net_device_stats *stats = &dev->stats;
13d64285 824 struct tx_queue *txq;
c9df406f 825 unsigned long flags;
afdb57a2 826
c9df406f
LB		 827 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
828 stats->tx_dropped++;
fc32b0e2
LB		 829 dev_printk(KERN_DEBUG, &dev->dev,
830 "failed to linearize skb with tiny "
831 "unaligned fragment\n");
c9df406f
LB		 832 return NETDEV_TX_BUSY;
833 }
834
835 spin_lock_irqsave(&mp->lock, flags);
836
3d6b35bc 837 txq = mp->txq + mp->txq_primary;
13d64285
LB		 838
839 if (txq->tx_ring_size - txq->tx_desc_count < MAX_DESCS_PER_SKB) {
c9df406f 840 spin_unlock_irqrestore(&mp->lock, flags);
3d6b35bc
LB		 841 if (txq->index == mp->txq_primary && net_ratelimit())
842 dev_printk(KERN_ERR, &dev->dev,
843 "primary tx queue full?!\n");
844 kfree_skb(skb);
845 return NETDEV_TX_OK;
c9df406f
LB		 846 }
847
13d64285 848 txq_submit_skb(txq, skb);
c9df406f
LB		 849 stats->tx_bytes += skb->len;
850 stats->tx_packets++;
851 dev->trans_start = jiffies;
852
3d6b35bc
LB		 853 if (txq->index == mp->txq_primary) {
854 int entries_left;
855
856 entries_left = txq->tx_ring_size - txq->tx_desc_count;
857 if (entries_left < MAX_DESCS_PER_SKB)
858 netif_stop_queue(dev);
859 }
c9df406f
LB		 860
861 spin_unlock_irqrestore(&mp->lock, flags);
862
863 return NETDEV_TX_OK;
1da177e4
LT		 864}
865
c9df406f 866
89df5fdc
LB		 867/* tx rate control **********************************************************/
868/*
869 * Set total maximum TX rate (shared by all TX queues for this port)
870 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
871 */
872static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
873{
874 int token_rate;
875 int mtu;
876 int bucket_size;
877
878 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
879 if (token_rate > 1023)
880 token_rate = 1023;
881
882 mtu = (mp->dev->mtu + 255) >> 8;
883 if (mtu > 63)
884 mtu = 63;
885
886 bucket_size = (burst + 255) >> 8;
887 if (bucket_size > 65535)
888 bucket_size = 65535;
889
1e881592
LB		 890 if (mp->shared->tx_bw_control_moved) {
891 wrl(mp, TX_BW_RATE_MOVED(mp->port_num), token_rate);
892 wrl(mp, TX_BW_MTU_MOVED(mp->port_num), mtu);
893 wrl(mp, TX_BW_BURST_MOVED(mp->port_num), bucket_size);
894 } else {
895 wrl(mp, TX_BW_RATE(mp->port_num), token_rate);
896 wrl(mp, TX_BW_MTU(mp->port_num), mtu);
897 wrl(mp, TX_BW_BURST(mp->port_num), bucket_size);
898 }
89df5fdc
LB		 899}
900
901static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
902{
903 struct mv643xx_eth_private *mp = txq_to_mp(txq);
904 int token_rate;
905 int bucket_size;
906
907 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
908 if (token_rate > 1023)
909 token_rate = 1023;
910
911 bucket_size = (burst + 255) >> 8;
912 if (bucket_size > 65535)
913 bucket_size = 65535;
914
3d6b35bc
LB		 915 wrl(mp, TXQ_BW_TOKENS(mp->port_num, txq->index), token_rate << 14);
916 wrl(mp, TXQ_BW_CONF(mp->port_num, txq->index),
89df5fdc
LB		 917 (bucket_size << 10) | token_rate);
918}
919
920static void txq_set_fixed_prio_mode(struct tx_queue *txq)
921{
922 struct mv643xx_eth_private *mp = txq_to_mp(txq);
923 int off;
924 u32 val;
925
926 /*
927 * Turn on fixed priority mode.
928 */
1e881592
LB		 929 if (mp->shared->tx_bw_control_moved)
930 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
931 else
932 off = TXQ_FIX_PRIO_CONF(mp->port_num);
89df5fdc
LB		 933
934 val = rdl(mp, off);
3d6b35bc 935 val |= 1 << txq->index;
89df5fdc
LB		 936 wrl(mp, off, val);
937}
938
939static void txq_set_wrr(struct tx_queue *txq, int weight)
940{
941 struct mv643xx_eth_private *mp = txq_to_mp(txq);
942 int off;
943 u32 val;
944
945 /*
946 * Turn off fixed priority mode.
947 */
1e881592
LB		 948 if (mp->shared->tx_bw_control_moved)
949 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
950 else
951 off = TXQ_FIX_PRIO_CONF(mp->port_num);
89df5fdc
LB		 952
953 val = rdl(mp, off);
3d6b35bc 954 val &= ~(1 << txq->index);
89df5fdc
LB		 955 wrl(mp, off, val);
956
957 /*
958 * Configure WRR weight for this queue.
959 */
3d6b35bc 960 off = TXQ_BW_WRR_CONF(mp->port_num, txq->index);
89df5fdc
LB		 961
962 val = rdl(mp, off);
963 val = (val & ~0xff) | (weight & 0xff);
964 wrl(mp, off, val);
965}
966
967
c9df406f 968/* mii management interface *************************************************/
fc32b0e2
LB		 969#define SMI_BUSY 0x10000000
970#define SMI_READ_VALID 0x08000000
971#define SMI_OPCODE_READ 0x04000000
972#define SMI_OPCODE_WRITE 0x00000000
c9df406f 973
fc32b0e2
LB		 974static void smi_reg_read(struct mv643xx_eth_private *mp, unsigned int addr,
975 unsigned int reg, unsigned int *value)
1da177e4 976{
cc9754b3 977 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
c9df406f 978 unsigned long flags;
1da177e4
LT		 979 int i;
980
c9df406f
LB		 981 /* the SMI register is a shared resource */
982 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
983
984 /* wait for the SMI register to become available */
cc9754b3 985 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
e1bea50a 986 if (i == 1000) {
c9df406f
LB		 987 printk("%s: PHY busy timeout\n", mp->dev->name);
988 goto out;
989 }
e1bea50a 990 udelay(10);
1da177e4
LT		 991 }
992
fc32b0e2 993 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1da177e4 994
c9df406f 995 /* now wait for the data to be valid */
cc9754b3 996 for (i = 0; !(readl(smi_reg) & SMI_READ_VALID); i++) {
e1bea50a 997 if (i == 1000) {
c9df406f
LB		 998 printk("%s: PHY read timeout\n", mp->dev->name);
999 goto out;
1000 }
e1bea50a 1001 udelay(10);
c9df406f
LB		 1002 }
1003
1004 *value = readl(smi_reg) & 0xffff;
1005out:
1006 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
1da177e4
LT		 1007}
1008
fc32b0e2
LB		 1009static void smi_reg_write(struct mv643xx_eth_private *mp,
1010 unsigned int addr,
1011 unsigned int reg, unsigned int value)
1da177e4 1012{
cc9754b3 1013 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
c9df406f 1014 unsigned long flags;
1da177e4
LT		 1015 int i;
1016
c9df406f
LB		 1017 /* the SMI register is a shared resource */
1018 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
1019
1020 /* wait for the SMI register to become available */
cc9754b3 1021 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
e1bea50a 1022 if (i == 1000) {
c9df406f
LB		 1023 printk("%s: PHY busy timeout\n", mp->dev->name);
1024 goto out;
1025 }
e1bea50a 1026 udelay(10);
1da177e4
LT		 1027 }
1028
fc32b0e2
LB		 1029 writel(SMI_OPCODE_WRITE | (reg << 21) |
1030 (addr << 16) | (value & 0xffff), smi_reg);
c9df406f
LB		 1031out:
1032 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
1033}
1da177e4 1034
c9df406f
LB		 1035
1036/* mib counters *************************************************************/
fc32b0e2 1037static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
c9df406f 1038{
fc32b0e2 1039 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1da177e4
LT		 1040}
1041
fc32b0e2 1042static void mib_counters_clear(struct mv643xx_eth_private *mp)
d0412d96 1043{
fc32b0e2
LB		 1044 int i;
1045
1046 for (i = 0; i < 0x80; i += 4)
1047 mib_read(mp, i);
c9df406f 1048}
d0412d96 1049
fc32b0e2 1050static void mib_counters_update(struct mv643xx_eth_private *mp)
c9df406f 1051{
e5371493 1052 struct mib_counters *p = &mp->mib_counters;
4b8e3655 1053
fc32b0e2
LB		 1054 p->good_octets_received += mib_read(mp, 0x00);
1055 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
1056 p->bad_octets_received += mib_read(mp, 0x08);
1057 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1058 p->good_frames_received += mib_read(mp, 0x10);
1059 p->bad_frames_received += mib_read(mp, 0x14);
1060 p->broadcast_frames_received += mib_read(mp, 0x18);
1061 p->multicast_frames_received += mib_read(mp, 0x1c);
1062 p->frames_64_octets += mib_read(mp, 0x20);
1063 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1064 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1065 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1066 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1067 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1068 p->good_octets_sent += mib_read(mp, 0x38);
1069 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1070 p->good_frames_sent += mib_read(mp, 0x40);
1071 p->excessive_collision += mib_read(mp, 0x44);
1072 p->multicast_frames_sent += mib_read(mp, 0x48);
1073 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1074 p->unrec_mac_control_received += mib_read(mp, 0x50);
1075 p->fc_sent += mib_read(mp, 0x54);
1076 p->good_fc_received += mib_read(mp, 0x58);
1077 p->bad_fc_received += mib_read(mp, 0x5c);
1078 p->undersize_received += mib_read(mp, 0x60);
1079 p->fragments_received += mib_read(mp, 0x64);
1080 p->oversize_received += mib_read(mp, 0x68);
1081 p->jabber_received += mib_read(mp, 0x6c);
1082 p->mac_receive_error += mib_read(mp, 0x70);
1083 p->bad_crc_event += mib_read(mp, 0x74);
1084 p->collision += mib_read(mp, 0x78);
1085 p->late_collision += mib_read(mp, 0x7c);
d0412d96
JC		 1086}
1087
c9df406f
LB		 1088
1089/* ethtool ******************************************************************/
e5371493 1090struct mv643xx_eth_stats {
c9df406f
LB		 1091 char stat_string[ETH_GSTRING_LEN];
1092 int sizeof_stat;
16820054
LB		 1093 int netdev_off;
1094 int mp_off;
c9df406f
LB		 1095};
1096
16820054
LB		 1097#define SSTAT(m) \
1098 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1099 offsetof(struct net_device, stats.m), -1 }
1100
1101#define MIBSTAT(m) \
1102 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1103 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1104
1105static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1106 SSTAT(rx_packets),
1107 SSTAT(tx_packets),
1108 SSTAT(rx_bytes),
1109 SSTAT(tx_bytes),
1110 SSTAT(rx_errors),
1111 SSTAT(tx_errors),
1112 SSTAT(rx_dropped),
1113 SSTAT(tx_dropped),
1114 MIBSTAT(good_octets_received),
1115 MIBSTAT(bad_octets_received),
1116 MIBSTAT(internal_mac_transmit_err),
1117 MIBSTAT(good_frames_received),
1118 MIBSTAT(bad_frames_received),
1119 MIBSTAT(broadcast_frames_received),
1120 MIBSTAT(multicast_frames_received),
1121 MIBSTAT(frames_64_octets),
1122 MIBSTAT(frames_65_to_127_octets),
1123 MIBSTAT(frames_128_to_255_octets),
1124 MIBSTAT(frames_256_to_511_octets),
1125 MIBSTAT(frames_512_to_1023_octets),
1126 MIBSTAT(frames_1024_to_max_octets),
1127 MIBSTAT(good_octets_sent),
1128 MIBSTAT(good_frames_sent),
1129 MIBSTAT(excessive_collision),
1130 MIBSTAT(multicast_frames_sent),
1131 MIBSTAT(broadcast_frames_sent),
1132 MIBSTAT(unrec_mac_control_received),
1133 MIBSTAT(fc_sent),
1134 MIBSTAT(good_fc_received),
1135 MIBSTAT(bad_fc_received),
1136 MIBSTAT(undersize_received),
1137 MIBSTAT(fragments_received),
1138 MIBSTAT(oversize_received),
1139 MIBSTAT(jabber_received),
1140 MIBSTAT(mac_receive_error),
1141 MIBSTAT(bad_crc_event),
1142 MIBSTAT(collision),
1143 MIBSTAT(late_collision),
c9df406f
LB		 1144};
1145
e5371493 1146static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
d0412d96 1147{
e5371493 1148 struct mv643xx_eth_private *mp = netdev_priv(dev);
d0412d96
JC		 1149 int err;
1150
1151 spin_lock_irq(&mp->lock);
1152 err = mii_ethtool_gset(&mp->mii, cmd);
1153 spin_unlock_irq(&mp->lock);
1154
fc32b0e2
LB		 1155 /*
1156 * The MAC does not support 1000baseT_Half.
1157 */
d0412d96
JC		 1158 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1159 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1160
1161 return err;
1162}
1163
bedfe324
LB		 1164static int mv643xx_eth_get_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1165{
81600eea
LB		 1166 struct mv643xx_eth_private *mp = netdev_priv(dev);
1167 u32 port_status;
1168
1169 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1170
bedfe324
LB		 1171 cmd->supported = SUPPORTED_MII;
1172 cmd->advertising = ADVERTISED_MII;
81600eea
LB		 1173 switch (port_status & PORT_SPEED_MASK) {
1174 case PORT_SPEED_10:
1175 cmd->speed = SPEED_10;
1176 break;
1177 case PORT_SPEED_100:
1178 cmd->speed = SPEED_100;
1179 break;
1180 case PORT_SPEED_1000:
1181 cmd->speed = SPEED_1000;
1182 break;
1183 default:
1184 cmd->speed = -1;
1185 break;
1186 }
1187 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
bedfe324
LB		 1188 cmd->port = PORT_MII;
1189 cmd->phy_address = 0;
1190 cmd->transceiver = XCVR_INTERNAL;
1191 cmd->autoneg = AUTONEG_DISABLE;
1192 cmd->maxtxpkt = 1;
1193 cmd->maxrxpkt = 1;
1194
1195 return 0;
1196}
1197
e5371493 1198static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4 1199{
e5371493 1200 struct mv643xx_eth_private *mp = netdev_priv(dev);
ab4384a6
DF		 1201 int err;
1202
fc32b0e2
LB		 1203 /*
1204 * The MAC does not support 1000baseT_Half.
1205 */
1206 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1207
c9df406f
LB		 1208 spin_lock_irq(&mp->lock);
1209 err = mii_ethtool_sset(&mp->mii, cmd);
1210 spin_unlock_irq(&mp->lock);
85cf572c 1211
c9df406f
LB		 1212 return err;
1213}
1da177e4 1214
bedfe324
LB		 1215static int mv643xx_eth_set_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1216{
1217 return -EINVAL;
1218}
1219
fc32b0e2
LB		 1220static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1221 struct ethtool_drvinfo *drvinfo)
c9df406f 1222{
e5371493
LB		 1223 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1224 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
c9df406f 1225 strncpy(drvinfo->fw_version, "N/A", 32);
fc32b0e2 1226 strncpy(drvinfo->bus_info, "platform", 32);
16820054 1227 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
c9df406f 1228}
1da177e4 1229
fc32b0e2 1230static int mv643xx_eth_nway_reset(struct net_device *dev)
c9df406f 1231{
e5371493 1232 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1233
c9df406f
LB		 1234 return mii_nway_restart(&mp->mii);
1235}
1da177e4 1236
bedfe324
LB		 1237static int mv643xx_eth_nway_reset_phyless(struct net_device *dev)
1238{
1239 return -EINVAL;
1240}
1241
c9df406f
LB		 1242static u32 mv643xx_eth_get_link(struct net_device *dev)
1243{
e5371493 1244 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1245
c9df406f
LB		 1246 return mii_link_ok(&mp->mii);
1247}
1da177e4 1248
bedfe324
LB		 1249static u32 mv643xx_eth_get_link_phyless(struct net_device *dev)
1250{
1251 return 1;
1252}
1253
fc32b0e2
LB		 1254static void mv643xx_eth_get_strings(struct net_device *dev,
1255 uint32_t stringset, uint8_t *data)
c9df406f
LB		 1256{
1257 int i;
1da177e4 1258
fc32b0e2
LB		 1259 if (stringset == ETH_SS_STATS) {
1260 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
c9df406f 1261 memcpy(data + i * ETH_GSTRING_LEN,
16820054 1262 mv643xx_eth_stats[i].stat_string,
e5371493 1263 ETH_GSTRING_LEN);
c9df406f 1264 }
c9df406f
LB		 1265 }
1266}
1da177e4 1267
fc32b0e2
LB		 1268static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1269 struct ethtool_stats *stats,
1270 uint64_t *data)
c9df406f 1271{
fc32b0e2 1272 struct mv643xx_eth_private *mp = dev->priv;
c9df406f 1273 int i;
1da177e4 1274
fc32b0e2 1275 mib_counters_update(mp);
1da177e4 1276
16820054
LB		 1277 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1278 const struct mv643xx_eth_stats *stat;
1279 void *p;
1280
1281 stat = mv643xx_eth_stats + i;
1282
1283 if (stat->netdev_off >= 0)
1284 p = ((void *)mp->dev) + stat->netdev_off;
1285 else
1286 p = ((void *)mp) + stat->mp_off;
1287
1288 data[i] = (stat->sizeof_stat == 8) ?
1289 *(uint64_t *)p : *(uint32_t *)p;
1da177e4 1290 }
c9df406f 1291}
1da177e4 1292
fc32b0e2 1293static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
c9df406f 1294{
fc32b0e2 1295 if (sset == ETH_SS_STATS)
16820054 1296 return ARRAY_SIZE(mv643xx_eth_stats);
fc32b0e2
LB		 1297
1298 return -EOPNOTSUPP;
c9df406f 1299}
1da177e4 1300
e5371493 1301static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
fc32b0e2
LB		 1302 .get_settings = mv643xx_eth_get_settings,
1303 .set_settings = mv643xx_eth_set_settings,
1304 .get_drvinfo = mv643xx_eth_get_drvinfo,
1305 .nway_reset = mv643xx_eth_nway_reset,
1306 .get_link = mv643xx_eth_get_link,
c9df406f 1307 .set_sg = ethtool_op_set_sg,
fc32b0e2
LB		 1308 .get_strings = mv643xx_eth_get_strings,
1309 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
e5371493 1310 .get_sset_count = mv643xx_eth_get_sset_count,
c9df406f 1311};
1da177e4 1312
bedfe324
LB		 1313static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless = {
1314 .get_settings = mv643xx_eth_get_settings_phyless,
1315 .set_settings = mv643xx_eth_set_settings_phyless,
1316 .get_drvinfo = mv643xx_eth_get_drvinfo,
1317 .nway_reset = mv643xx_eth_nway_reset_phyless,
1318 .get_link = mv643xx_eth_get_link_phyless,
1319 .set_sg = ethtool_op_set_sg,
1320 .get_strings = mv643xx_eth_get_strings,
1321 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1322 .get_sset_count = mv643xx_eth_get_sset_count,
1323};
1324
bea3348e 1325
c9df406f 1326/* address handling *********************************************************/
5daffe94 1327static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
c9df406f 1328{
c9df406f
LB		 1329 unsigned int mac_h;
1330 unsigned int mac_l;
1da177e4 1331
fc32b0e2
LB		 1332 mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num));
1333 mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num));
1da177e4 1334
5daffe94
LB		 1335 addr[0] = (mac_h >> 24) & 0xff;
1336 addr[1] = (mac_h >> 16) & 0xff;
1337 addr[2] = (mac_h >> 8) & 0xff;
1338 addr[3] = mac_h & 0xff;
1339 addr[4] = (mac_l >> 8) & 0xff;
1340 addr[5] = mac_l & 0xff;
c9df406f 1341}
1da177e4 1342
e5371493 1343static void init_mac_tables(struct mv643xx_eth_private *mp)
c9df406f 1344{
fc32b0e2 1345 int i;
1da177e4 1346
fc32b0e2
LB		 1347 for (i = 0; i < 0x100; i += 4) {
1348 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1349 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
c9df406f 1350 }
fc32b0e2
LB		 1351
1352 for (i = 0; i < 0x10; i += 4)
1353 wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
c9df406f 1354}
d0412d96 1355
e5371493 1356static void set_filter_table_entry(struct mv643xx_eth_private *mp,
fc32b0e2 1357 int table, unsigned char entry)
c9df406f
LB		 1358{
1359 unsigned int table_reg;
ab4384a6 1360
c9df406f 1361 /* Set "accepts frame bit" at specified table entry */
fc32b0e2
LB		 1362 table_reg = rdl(mp, table + (entry & 0xfc));
1363 table_reg |= 0x01 << (8 * (entry & 3));
1364 wrl(mp, table + (entry & 0xfc), table_reg);
1da177e4
LT		 1365}
1366
5daffe94 1367static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1da177e4 1368{
c9df406f
LB		 1369 unsigned int mac_h;
1370 unsigned int mac_l;
1371 int table;
1da177e4 1372
fc32b0e2
LB		 1373 mac_l = (addr[4] << 8) | addr[5];
1374 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
ff561eef 1375
fc32b0e2
LB		 1376 wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l);
1377 wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h);
1da177e4 1378
fc32b0e2 1379 table = UNICAST_TABLE(mp->port_num);
5daffe94 1380 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1da177e4
LT		 1381}
1382
fc32b0e2 1383static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1da177e4 1384{
e5371493 1385 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1386
fc32b0e2
LB		 1387 /* +2 is for the offset of the HW addr type */
1388 memcpy(dev->dev_addr, addr + 2, 6);
1389
cc9754b3
LB		 1390 init_mac_tables(mp);
1391 uc_addr_set(mp, dev->dev_addr);
1da177e4
LT		 1392
1393 return 0;
1394}
1395
69876569
LB		 1396static int addr_crc(unsigned char *addr)
1397{
1398 int crc = 0;
1399 int i;
1400
1401 for (i = 0; i < 6; i++) {
1402 int j;
1403
1404 crc = (crc ^ addr[i]) << 8;
1405 for (j = 7; j >= 0; j--) {
1406 if (crc & (0x100 << j))
1407 crc ^= 0x107 << j;
1408 }
1409 }
1410
1411 return crc;
1412}
1413
fc32b0e2 1414static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1da177e4 1415{
fc32b0e2
LB		 1416 struct mv643xx_eth_private *mp = netdev_priv(dev);
1417 u32 port_config;
1418 struct dev_addr_list *addr;
1419 int i;
c8aaea25 1420
fc32b0e2
LB		 1421 port_config = rdl(mp, PORT_CONFIG(mp->port_num));
1422 if (dev->flags & IFF_PROMISC)
1423 port_config |= UNICAST_PROMISCUOUS_MODE;
1424 else
1425 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1426 wrl(mp, PORT_CONFIG(mp->port_num), port_config);
1da177e4 1427
fc32b0e2
LB		 1428 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1429 int port_num = mp->port_num;
1430 u32 accept = 0x01010101;
c8aaea25 1431
fc32b0e2
LB		 1432 for (i = 0; i < 0x100; i += 4) {
1433 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1434 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
c9df406f
LB		 1435 }
1436 return;
1437 }
c8aaea25 1438
fc32b0e2
LB		 1439 for (i = 0; i < 0x100; i += 4) {
1440 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1441 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1da177e4
LT		 1442 }
1443
fc32b0e2
LB		 1444 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1445 u8 *a = addr->da_addr;
1446 int table;
324ff2c1 1447
fc32b0e2
LB		 1448 if (addr->da_addrlen != 6)
1449 continue;
1da177e4 1450
fc32b0e2
LB		 1451 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1452 table = SPECIAL_MCAST_TABLE(mp->port_num);
1453 set_filter_table_entry(mp, table, a[5]);
1454 } else {
1455 int crc = addr_crc(a);
1da177e4 1456
fc32b0e2
LB		 1457 table = OTHER_MCAST_TABLE(mp->port_num);
1458 set_filter_table_entry(mp, table, crc);
1459 }
1460 }
c9df406f 1461}
c8aaea25 1462
c8aaea25 1463
c9df406f 1464/* rx/tx queue initialisation ***********************************************/
64da80a2 1465static int rxq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1466{
64da80a2 1467 struct rx_queue *rxq = mp->rxq + index;
8a578111
LB		 1468 struct rx_desc *rx_desc;
1469 int size;
c9df406f
LB		 1470 int i;
1471
64da80a2
LB		 1472 rxq->index = index;
1473
8a578111
LB		 1474 rxq->rx_ring_size = mp->default_rx_ring_size;
1475
1476 rxq->rx_desc_count = 0;
1477 rxq->rx_curr_desc = 0;
1478 rxq->rx_used_desc = 0;
1479
1480 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1481
64da80a2 1482 if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size) {
8a578111
LB		 1483 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1484 mp->rx_desc_sram_size);
1485 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1486 } else {
1487 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1488 &rxq->rx_desc_dma,
1489 GFP_KERNEL);
f7ea3337
PJ		 1490 }
1491
8a578111
LB		 1492 if (rxq->rx_desc_area == NULL) {
1493 dev_printk(KERN_ERR, &mp->dev->dev,
1494 "can't allocate rx ring (%d bytes)\n", size);
1495 goto out;
1496 }
1497 memset(rxq->rx_desc_area, 0, size);
1da177e4 1498
8a578111
LB		 1499 rxq->rx_desc_area_size = size;
1500 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1501 GFP_KERNEL);
1502 if (rxq->rx_skb == NULL) {
1503 dev_printk(KERN_ERR, &mp->dev->dev,
1504 "can't allocate rx skb ring\n");
1505 goto out_free;
1506 }
1507
1508 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1509 for (i = 0; i < rxq->rx_ring_size; i++) {
1510 int nexti = (i + 1) % rxq->rx_ring_size;
1511 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1512 nexti * sizeof(struct rx_desc);
1513 }
1514
1515 init_timer(&rxq->rx_oom);
1516 rxq->rx_oom.data = (unsigned long)rxq;
1517 rxq->rx_oom.function = rxq_refill_timer_wrapper;
1518
1519 return 0;
1520
1521
1522out_free:
64da80a2 1523 if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size)
8a578111
LB		 1524 iounmap(rxq->rx_desc_area);
1525 else
1526 dma_free_coherent(NULL, size,
1527 rxq->rx_desc_area,
1528 rxq->rx_desc_dma);
1529
1530out:
1531 return -ENOMEM;
c9df406f 1532}
c8aaea25 1533
8a578111 1534static void rxq_deinit(struct rx_queue *rxq)
c9df406f 1535{
8a578111
LB		 1536 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1537 int i;
1538
1539 rxq_disable(rxq);
c8aaea25 1540
8a578111 1541 del_timer_sync(&rxq->rx_oom);
c9df406f 1542
8a578111
LB		 1543 for (i = 0; i < rxq->rx_ring_size; i++) {
1544 if (rxq->rx_skb[i]) {
1545 dev_kfree_skb(rxq->rx_skb[i]);
1546 rxq->rx_desc_count--;
1da177e4 1547 }
c8aaea25 1548 }
1da177e4 1549
8a578111
LB		 1550 if (rxq->rx_desc_count) {
1551 dev_printk(KERN_ERR, &mp->dev->dev,
1552 "error freeing rx ring -- %d skbs stuck\n",
1553 rxq->rx_desc_count);
1554 }
1555
64da80a2
LB		 1556 if (rxq->index == mp->rxq_primary &&
1557 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
8a578111 1558 iounmap(rxq->rx_desc_area);
c9df406f 1559 else
8a578111
LB		 1560 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1561 rxq->rx_desc_area, rxq->rx_desc_dma);
1562
1563 kfree(rxq->rx_skb);
c9df406f 1564}
1da177e4 1565
3d6b35bc 1566static int txq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1567{
3d6b35bc 1568 struct tx_queue *txq = mp->txq + index;
13d64285
LB		 1569 struct tx_desc *tx_desc;
1570 int size;
c9df406f 1571 int i;
1da177e4 1572
3d6b35bc
LB		 1573 txq->index = index;
1574
13d64285
LB		 1575 txq->tx_ring_size = mp->default_tx_ring_size;
1576
1577 txq->tx_desc_count = 0;
1578 txq->tx_curr_desc = 0;
1579 txq->tx_used_desc = 0;
1580
1581 size = txq->tx_ring_size * sizeof(struct tx_desc);
1582
3d6b35bc 1583 if (index == mp->txq_primary && size <= mp->tx_desc_sram_size) {
13d64285
LB		 1584 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1585 mp->tx_desc_sram_size);
1586 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1587 } else {
1588 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1589 &txq->tx_desc_dma,
1590 GFP_KERNEL);
1591 }
1592
1593 if (txq->tx_desc_area == NULL) {
1594 dev_printk(KERN_ERR, &mp->dev->dev,
1595 "can't allocate tx ring (%d bytes)\n", size);
1596 goto out;
c9df406f 1597 }
13d64285
LB		 1598 memset(txq->tx_desc_area, 0, size);
1599
1600 txq->tx_desc_area_size = size;
1601 txq->tx_skb = kmalloc(txq->tx_ring_size * sizeof(*txq->tx_skb),
1602 GFP_KERNEL);
1603 if (txq->tx_skb == NULL) {
1604 dev_printk(KERN_ERR, &mp->dev->dev,
1605 "can't allocate tx skb ring\n");
1606 goto out_free;
1607 }
1608
1609 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1610 for (i = 0; i < txq->tx_ring_size; i++) {
6b368f68 1611 struct tx_desc *txd = tx_desc + i;
13d64285 1612 int nexti = (i + 1) % txq->tx_ring_size;
6b368f68
LB		 1613
1614 txd->cmd_sts = 0;
1615 txd->next_desc_ptr = txq->tx_desc_dma +
13d64285
LB		 1616 nexti * sizeof(struct tx_desc);
1617 }
1618
1619 return 0;
1620
c9df406f 1621
13d64285 1622out_free:
3d6b35bc 1623 if (index == mp->txq_primary && size <= mp->tx_desc_sram_size)
13d64285
LB		 1624 iounmap(txq->tx_desc_area);
1625 else
1626 dma_free_coherent(NULL, size,
1627 txq->tx_desc_area,
1628 txq->tx_desc_dma);
c9df406f 1629
13d64285
LB		 1630out:
1631 return -ENOMEM;
c8aaea25 1632}
1da177e4 1633
13d64285 1634static void txq_reclaim(struct tx_queue *txq, int force)
c8aaea25 1635{
13d64285 1636 struct mv643xx_eth_private *mp = txq_to_mp(txq);
c8aaea25 1637 unsigned long flags;
1da177e4 1638
13d64285
LB		 1639 spin_lock_irqsave(&mp->lock, flags);
1640 while (txq->tx_desc_count > 0) {
1641 int tx_index;
1642 struct tx_desc *desc;
1643 u32 cmd_sts;
1644 struct sk_buff *skb;
1645 dma_addr_t addr;
1646 int count;
4d64e718 1647
13d64285
LB		 1648 tx_index = txq->tx_used_desc;
1649 desc = &txq->tx_desc_area[tx_index];
c9df406f 1650 cmd_sts = desc->cmd_sts;
4d64e718 1651
6b368f68
LB		 1652 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
1653 if (!force)
1654 break;
1655 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
1656 }
1da177e4 1657
13d64285
LB		 1658 txq->tx_used_desc = (tx_index + 1) % txq->tx_ring_size;
1659 txq->tx_desc_count--;
1da177e4 1660
c9df406f
LB		 1661 addr = desc->buf_ptr;
1662 count = desc->byte_cnt;
13d64285
LB		 1663 skb = txq->tx_skb[tx_index];
1664 txq->tx_skb[tx_index] = NULL;
c8aaea25 1665
cc9754b3 1666 if (cmd_sts & ERROR_SUMMARY) {
13d64285
LB		 1667 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
1668 mp->dev->stats.tx_errors++;
c9df406f 1669 }
1da177e4 1670
13d64285
LB		 1671 /*
1672 * Drop mp->lock while we free the skb.
1673 */
c9df406f 1674 spin_unlock_irqrestore(&mp->lock, flags);
1da177e4 1675
cc9754b3 1676 if (cmd_sts & TX_FIRST_DESC)
c9df406f
LB		 1677 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
1678 else
1679 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
c2e5b352 1680
c9df406f
LB		 1681 if (skb)
1682 dev_kfree_skb_irq(skb);
63c9e549 1683
13d64285 1684 spin_lock_irqsave(&mp->lock, flags);
c9df406f 1685 }
13d64285 1686 spin_unlock_irqrestore(&mp->lock, flags);
c9df406f 1687}
1da177e4 1688
13d64285 1689static void txq_deinit(struct tx_queue *txq)
c9df406f 1690{
13d64285 1691 struct mv643xx_eth_private *mp = txq_to_mp(txq);
fa3959f4 1692
13d64285
LB		 1693 txq_disable(txq);
1694 txq_reclaim(txq, 1);
1da177e4 1695
13d64285 1696 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1da177e4 1697
3d6b35bc
LB		 1698 if (txq->index == mp->txq_primary &&
1699 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
13d64285 1700 iounmap(txq->tx_desc_area);
c9df406f 1701 else
13d64285
LB		 1702 dma_free_coherent(NULL, txq->tx_desc_area_size,
1703 txq->tx_desc_area, txq->tx_desc_dma);
1704
1705 kfree(txq->tx_skb);
c9df406f 1706}
1da177e4 1707
1da177e4 1708
c9df406f 1709/* netdev ops and related ***************************************************/
2f7eb47a
LB		 1710static void handle_link_event(struct mv643xx_eth_private *mp)
1711{
1712 struct net_device *dev = mp->dev;
1713 u32 port_status;
1714 int speed;
1715 int duplex;
1716 int fc;
1717
1718 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1719 if (!(port_status & LINK_UP)) {
1720 if (netif_carrier_ok(dev)) {
1721 int i;
1722
1723 printk(KERN_INFO "%s: link down\n", dev->name);
1724
1725 netif_carrier_off(dev);
1726 netif_stop_queue(dev);
1727
1728 for (i = 0; i < 8; i++) {
1729 struct tx_queue *txq = mp->txq + i;
1730
1731 if (mp->txq_mask & (1 << i)) {
1732 txq_reclaim(txq, 1);
1733 txq_reset_hw_ptr(txq);
1734 }
1735 }
1736 }
1737 return;
1738 }
1739
1740 switch (port_status & PORT_SPEED_MASK) {
1741 case PORT_SPEED_10:
1742 speed = 10;
1743 break;
1744 case PORT_SPEED_100:
1745 speed = 100;
1746 break;
1747 case PORT_SPEED_1000:
1748 speed = 1000;
1749 break;
1750 default:
1751 speed = -1;
1752 break;
1753 }
1754 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
1755 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
1756
1757 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
1758 "flow control %sabled\n", dev->name,
1759 speed, duplex ? "full" : "half",
1760 fc ? "en" : "dis");
1761
1762 if (!netif_carrier_ok(dev)) {
1763 netif_carrier_on(dev);
1764 netif_wake_queue(dev);
1765 }
1766}
1767
fc32b0e2 1768static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
c9df406f
LB		 1769{
1770 struct net_device *dev = (struct net_device *)dev_id;
e5371493 1771 struct mv643xx_eth_private *mp = netdev_priv(dev);
fc32b0e2
LB		 1772 u32 int_cause;
1773 u32 int_cause_ext;
ce4e2e45 1774
226bb6b7
LB		 1775 int_cause = rdl(mp, INT_CAUSE(mp->port_num)) &
1776 (INT_TX_END | INT_RX | INT_EXT);
fc32b0e2
LB		 1777 if (int_cause == 0)
1778 return IRQ_NONE;
1779
1780 int_cause_ext = 0;
cc9754b3 1781 if (int_cause & INT_EXT) {
13d64285 1782 int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num))
073a345c 1783 & (INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
13d64285 1784 wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext);
c9df406f 1785 }
1da177e4 1786
2f7eb47a
LB		 1787 if (int_cause_ext & (INT_EXT_PHY | INT_EXT_LINK))
1788 handle_link_event(mp);
1da177e4 1789
64da80a2
LB		 1790 /*
1791 * RxBuffer or RxError set for any of the 8 queues?
1792 */
e5371493 1793#ifdef MV643XX_ETH_NAPI
cc9754b3 1794 if (int_cause & INT_RX) {
819ddcaf 1795 wrl(mp, INT_CAUSE(mp->port_num), ~(int_cause & INT_RX));
13d64285 1796 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
13d64285 1797 rdl(mp, INT_MASK(mp->port_num));
1da177e4 1798
c9df406f 1799 netif_rx_schedule(dev, &mp->napi);
84dd619e 1800 }
c9df406f 1801#else
64da80a2
LB		 1802 if (int_cause & INT_RX) {
1803 int i;
1804
1805 for (i = 7; i >= 0; i--)
1806 if (mp->rxq_mask & (1 << i))
1807 rxq_process(mp->rxq + i, INT_MAX);
1808 }
c9df406f 1809#endif
fc32b0e2 1810
3d6b35bc
LB		 1811 /*
1812 * TxBuffer or TxError set for any of the 8 queues?
1813 */
13d64285 1814 if (int_cause_ext & INT_EXT_TX) {
3d6b35bc
LB		 1815 int i;
1816
1817 for (i = 0; i < 8; i++)
1818 if (mp->txq_mask & (1 << i))
1819 txq_reclaim(mp->txq + i, 0);
8fa89bf5
LB		 1820
1821 /*
1822 * Enough space again in the primary TX queue for a
1823 * full packet?
1824 */
6b368f68
LB		 1825 if (netif_carrier_ok(dev)) {
1826 spin_lock(&mp->lock);
1827 __txq_maybe_wake(mp->txq + mp->txq_primary);
1828 spin_unlock(&mp->lock);
1829 }
226bb6b7 1830 }
3d6b35bc 1831
226bb6b7
LB		 1832 /*
1833 * Any TxEnd interrupts?
1834 */
1835 if (int_cause & INT_TX_END) {
1836 int i;
1837
1838 wrl(mp, INT_CAUSE(mp->port_num), ~(int_cause & INT_TX_END));
8fa89bf5
LB		 1839
1840 spin_lock(&mp->lock);
226bb6b7
LB		 1841 for (i = 0; i < 8; i++) {
1842 struct tx_queue *txq = mp->txq + i;
8fa89bf5
LB		 1843 u32 hw_desc_ptr;
1844 u32 expected_ptr;
1845
1846 if ((int_cause & (INT_TX_END_0 << i)) == 0)
1847 continue;
1848
1849 hw_desc_ptr =
1850 rdl(mp, TXQ_CURRENT_DESC_PTR(mp->port_num, i));
1851 expected_ptr = (u32)txq->tx_desc_dma +
1852 txq->tx_curr_desc * sizeof(struct tx_desc);
1853
1854 if (hw_desc_ptr != expected_ptr)
226bb6b7
LB		 1855 txq_enable(txq);
1856 }
8fa89bf5 1857 spin_unlock(&mp->lock);
13d64285 1858 }
1da177e4 1859
c9df406f 1860 return IRQ_HANDLED;
1da177e4
LT		 1861}
1862
e5371493 1863static void phy_reset(struct mv643xx_eth_private *mp)
1da177e4 1864{
fc32b0e2 1865 unsigned int data;
1da177e4 1866
7f106c1d
LB		 1867 smi_reg_read(mp, mp->phy_addr, MII_BMCR, &data);
1868 data |= BMCR_RESET;
1869 smi_reg_write(mp, mp->phy_addr, MII_BMCR, data);
1da177e4 1870
c9df406f
LB		 1871 do {
1872 udelay(1);
7f106c1d
LB		 1873 smi_reg_read(mp, mp->phy_addr, MII_BMCR, &data);
1874 } while (data & BMCR_RESET);
1da177e4
LT		 1875}
1876
fc32b0e2 1877static void port_start(struct mv643xx_eth_private *mp)
1da177e4 1878{
d0412d96 1879 u32 pscr;
8a578111 1880 int i;
1da177e4 1881
bedfe324
LB		 1882 /*
1883 * Perform PHY reset, if there is a PHY.
1884 */
1885 if (mp->phy_addr != -1) {
1886 struct ethtool_cmd cmd;
1887
1888 mv643xx_eth_get_settings(mp->dev, &cmd);
1889 phy_reset(mp);
1890 mv643xx_eth_set_settings(mp->dev, &cmd);
1891 }
1da177e4 1892
81600eea
LB		 1893 /*
1894 * Configure basic link parameters.
1895 */
1896 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1897
1898 pscr |= SERIAL_PORT_ENABLE;
1899 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1900
1901 pscr |= DO_NOT_FORCE_LINK_FAIL;
1902 if (mp->phy_addr == -1)
1903 pscr |= FORCE_LINK_PASS;
1904 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1905
1906 wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1907
13d64285
LB		 1908 /*
1909 * Configure TX path and queues.
1910 */
89df5fdc 1911 tx_set_rate(mp, 1000000000, 16777216);
3d6b35bc
LB		 1912 for (i = 0; i < 8; i++) {
1913 struct tx_queue *txq = mp->txq + i;
13d64285 1914
3d6b35bc
LB		 1915 if ((mp->txq_mask & (1 << i)) == 0)
1916 continue;
1917
6b368f68 1918 txq_reset_hw_ptr(txq);
89df5fdc
LB		 1919 txq_set_rate(txq, 1000000000, 16777216);
1920 txq_set_fixed_prio_mode(txq);
13d64285
LB		 1921 }
1922
fc32b0e2
LB		 1923 /*
1924 * Add configured unicast address to address filter table.
1925 */
1926 uc_addr_set(mp, mp->dev->dev_addr);
1da177e4 1927
d9a073ea
LB		 1928 /*
1929 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
1930 * frames to RX queue #0.
1931 */
8a578111 1932 wrl(mp, PORT_CONFIG(mp->port_num), 0x00000000);
01999873 1933
376489a2
LB		 1934 /*
1935 * Treat BPDUs as normal multicasts, and disable partition mode.
1936 */
8a578111 1937 wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000);
01999873 1938
8a578111 1939 /*
64da80a2 1940 * Enable the receive queues.
8a578111 1941 */
64da80a2
LB		 1942 for (i = 0; i < 8; i++) {
1943 struct rx_queue *rxq = mp->rxq + i;
1944 int off = RXQ_CURRENT_DESC_PTR(mp->port_num, i);
8a578111 1945 u32 addr;
1da177e4 1946
64da80a2
LB		 1947 if ((mp->rxq_mask & (1 << i)) == 0)
1948 continue;
1949
8a578111
LB		 1950 addr = (u32)rxq->rx_desc_dma;
1951 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
1952 wrl(mp, off, addr);
1da177e4 1953
8a578111
LB		 1954 rxq_enable(rxq);
1955 }
1da177e4
LT		 1956}
1957
ffd86bbe 1958static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1da177e4 1959{
c9df406f 1960 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
773fc3ee 1961 u32 val;
1da177e4 1962
773fc3ee
LB		 1963 val = rdl(mp, SDMA_CONFIG(mp->port_num));
1964 if (mp->shared->extended_rx_coal_limit) {
1965 if (coal > 0xffff)
1966 coal = 0xffff;
1967 val &= ~0x023fff80;
1968 val |= (coal & 0x8000) << 10;
1969 val |= (coal & 0x7fff) << 7;
1970 } else {
1971 if (coal > 0x3fff)
1972 coal = 0x3fff;
1973 val &= ~0x003fff00;
1974 val |= (coal & 0x3fff) << 8;
1975 }
1976 wrl(mp, SDMA_CONFIG(mp->port_num), val);
1da177e4
LT		 1977}
1978
ffd86bbe 1979static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1da177e4 1980{
c9df406f 1981 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1da177e4 1982
fc32b0e2
LB		 1983 if (coal > 0x3fff)
1984 coal = 0x3fff;
1985 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4);
16e03018
DF		 1986}
1987
c9df406f 1988static int mv643xx_eth_open(struct net_device *dev)
16e03018 1989{
e5371493 1990 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 1991 int err;
64da80a2 1992 int i;
16e03018 1993
fc32b0e2
LB		 1994 wrl(mp, INT_CAUSE(mp->port_num), 0);
1995 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
1996 rdl(mp, INT_CAUSE_EXT(mp->port_num));
c9df406f 1997
fc32b0e2
LB		 1998 err = request_irq(dev->irq, mv643xx_eth_irq,
1999 IRQF_SHARED | IRQF_SAMPLE_RANDOM,
2000 dev->name, dev);
c9df406f 2001 if (err) {
fc32b0e2 2002 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
c9df406f 2003 return -EAGAIN;
16e03018
DF		 2004 }
2005
fc32b0e2 2006 init_mac_tables(mp);
16e03018 2007
64da80a2
LB		 2008 for (i = 0; i < 8; i++) {
2009 if ((mp->rxq_mask & (1 << i)) == 0)
2010 continue;
2011
2012 err = rxq_init(mp, i);
2013 if (err) {
2014 while (--i >= 0)
2015 if (mp->rxq_mask & (1 << i))
2016 rxq_deinit(mp->rxq + i);
2017 goto out;
2018 }
2019
2020 rxq_refill(mp->rxq + i);
2021 }
8a578111 2022
3d6b35bc
LB		 2023 for (i = 0; i < 8; i++) {
2024 if ((mp->txq_mask & (1 << i)) == 0)
2025 continue;
2026
2027 err = txq_init(mp, i);
2028 if (err) {
2029 while (--i >= 0)
2030 if (mp->txq_mask & (1 << i))
2031 txq_deinit(mp->txq + i);
2032 goto out_free;
2033 }
2034 }
16e03018 2035
e5371493 2036#ifdef MV643XX_ETH_NAPI
c9df406f
LB		 2037 napi_enable(&mp->napi);
2038#endif
16e03018 2039
2f7eb47a
LB		 2040 netif_carrier_off(dev);
2041 netif_stop_queue(dev);
2042
fc32b0e2 2043 port_start(mp);
16e03018 2044
ffd86bbe
LB		 2045 set_rx_coal(mp, 0);
2046 set_tx_coal(mp, 0);
16e03018 2047
fc32b0e2
LB		 2048 wrl(mp, INT_MASK_EXT(mp->port_num),
2049 INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
16e03018 2050
226bb6b7 2051 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
16e03018 2052
c9df406f
LB		 2053 return 0;
2054
13d64285 2055
fc32b0e2 2056out_free:
64da80a2
LB		 2057 for (i = 0; i < 8; i++)
2058 if (mp->rxq_mask & (1 << i))
2059 rxq_deinit(mp->rxq + i);
fc32b0e2 2060out:
c9df406f
LB		 2061 free_irq(dev->irq, dev);
2062
2063 return err;
16e03018
DF		 2064}
2065
e5371493 2066static void port_reset(struct mv643xx_eth_private *mp)
1da177e4 2067{
fc32b0e2 2068 unsigned int data;
64da80a2 2069 int i;
1da177e4 2070
64da80a2
LB		 2071 for (i = 0; i < 8; i++) {
2072 if (mp->rxq_mask & (1 << i))
2073 rxq_disable(mp->rxq + i);
3d6b35bc
LB		 2074 if (mp->txq_mask & (1 << i))
2075 txq_disable(mp->txq + i);
64da80a2 2076 }
ae9ae064
LB		 2077
2078 while (1) {
2079 u32 ps = rdl(mp, PORT_STATUS(mp->port_num));
2080
2081 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2082 break;
13d64285 2083 udelay(10);
ae9ae064 2084 }
1da177e4 2085
c9df406f 2086 /* Reset the Enable bit in the Configuration Register */
fc32b0e2
LB		 2087 data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2088 data &= ~(SERIAL_PORT_ENABLE |
2089 DO_NOT_FORCE_LINK_FAIL |
2090 FORCE_LINK_PASS);
2091 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data);
1da177e4
LT		 2092}
2093
c9df406f 2094static int mv643xx_eth_stop(struct net_device *dev)
1da177e4 2095{
e5371493 2096 struct mv643xx_eth_private *mp = netdev_priv(dev);
64da80a2 2097 int i;
1da177e4 2098
fc32b0e2
LB		 2099 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2100 rdl(mp, INT_MASK(mp->port_num));
1da177e4 2101
e5371493 2102#ifdef MV643XX_ETH_NAPI
c9df406f
LB		 2103 napi_disable(&mp->napi);
2104#endif
2105 netif_carrier_off(dev);
2106 netif_stop_queue(dev);
1da177e4 2107
fc32b0e2
LB		 2108 free_irq(dev->irq, dev);
2109
cc9754b3 2110 port_reset(mp);
fc32b0e2 2111 mib_counters_update(mp);
1da177e4 2112
64da80a2
LB		 2113 for (i = 0; i < 8; i++) {
2114 if (mp->rxq_mask & (1 << i))
2115 rxq_deinit(mp->rxq + i);
3d6b35bc
LB		 2116 if (mp->txq_mask & (1 << i))
2117 txq_deinit(mp->txq + i);
64da80a2 2118 }
1da177e4 2119
c9df406f 2120 return 0;
1da177e4
LT		 2121}
2122
fc32b0e2 2123static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1da177e4 2124{
e5371493 2125 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2126
bedfe324
LB		 2127 if (mp->phy_addr != -1)
2128 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
2129
2130 return -EOPNOTSUPP;
1da177e4
LT		 2131}
2132
c9df406f 2133static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 2134{
89df5fdc
LB		 2135 struct mv643xx_eth_private *mp = netdev_priv(dev);
2136
fc32b0e2 2137 if (new_mtu < 64 || new_mtu > 9500)
c9df406f 2138 return -EINVAL;
1da177e4 2139
c9df406f 2140 dev->mtu = new_mtu;
89df5fdc
LB		 2141 tx_set_rate(mp, 1000000000, 16777216);
2142
c9df406f
LB		 2143 if (!netif_running(dev))
2144 return 0;
1da177e4 2145
c9df406f
LB		 2146 /*
2147 * Stop and then re-open the interface. This will allocate RX
2148 * skbs of the new MTU.
2149 * There is a possible danger that the open will not succeed,
fc32b0e2 2150 * due to memory being full.
c9df406f
LB		 2151 */
2152 mv643xx_eth_stop(dev);
2153 if (mv643xx_eth_open(dev)) {
fc32b0e2
LB		 2154 dev_printk(KERN_ERR, &dev->dev,
2155 "fatal error on re-opening device after "
2156 "MTU change\n");
c9df406f
LB		 2157 }
2158
2159 return 0;
1da177e4
LT		 2160}
2161
fc32b0e2 2162static void tx_timeout_task(struct work_struct *ugly)
1da177e4 2163{
fc32b0e2 2164 struct mv643xx_eth_private *mp;
1da177e4 2165
fc32b0e2
LB		 2166 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2167 if (netif_running(mp->dev)) {
2168 netif_stop_queue(mp->dev);
c9df406f 2169
fc32b0e2
LB		 2170 port_reset(mp);
2171 port_start(mp);
c9df406f 2172
3d6b35bc 2173 __txq_maybe_wake(mp->txq + mp->txq_primary);
fc32b0e2 2174 }
c9df406f
LB		 2175}
2176
c9df406f 2177static void mv643xx_eth_tx_timeout(struct net_device *dev)
1da177e4 2178{
e5371493 2179 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2180
fc32b0e2 2181 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
d0412d96 2182
c9df406f 2183 schedule_work(&mp->tx_timeout_task);
1da177e4
LT		 2184}
2185
c9df406f 2186#ifdef CONFIG_NET_POLL_CONTROLLER
fc32b0e2 2187static void mv643xx_eth_netpoll(struct net_device *dev)
9f8dd319 2188{
fc32b0e2 2189 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2190
fc32b0e2
LB		 2191 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2192 rdl(mp, INT_MASK(mp->port_num));
c9df406f 2193
fc32b0e2 2194 mv643xx_eth_irq(dev->irq, dev);
c9df406f 2195
f2ca60f2 2196 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
9f8dd319 2197}
c9df406f 2198#endif
9f8dd319 2199
fc32b0e2 2200static int mv643xx_eth_mdio_read(struct net_device *dev, int addr, int reg)
9f8dd319 2201{
e5371493 2202 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f
LB		 2203 int val;
2204
fc32b0e2
LB		 2205 smi_reg_read(mp, addr, reg, &val);
2206
c9df406f 2207 return val;
9f8dd319
DF		 2208}
2209
fc32b0e2 2210static void mv643xx_eth_mdio_write(struct net_device *dev, int addr, int reg, int val)
9f8dd319 2211{
e5371493 2212 struct mv643xx_eth_private *mp = netdev_priv(dev);
fc32b0e2 2213 smi_reg_write(mp, addr, reg, val);
c9df406f 2214}
9f8dd319 2215
9f8dd319 2216
c9df406f 2217/* platform glue ************************************************************/
e5371493
LB		 2218static void
2219mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2220 struct mbus_dram_target_info *dram)
c9df406f 2221{
cc9754b3 2222 void __iomem *base = msp->base;
c9df406f
LB		 2223 u32 win_enable;
2224 u32 win_protect;
2225 int i;
9f8dd319 2226
c9df406f
LB		 2227 for (i = 0; i < 6; i++) {
2228 writel(0, base + WINDOW_BASE(i));
2229 writel(0, base + WINDOW_SIZE(i));
2230 if (i < 4)
2231 writel(0, base + WINDOW_REMAP_HIGH(i));
9f8dd319
DF		 2232 }
2233
c9df406f
LB		 2234 win_enable = 0x3f;
2235 win_protect = 0;
2236
2237 for (i = 0; i < dram->num_cs; i++) {
2238 struct mbus_dram_window *cs = dram->cs + i;
2239
2240 writel((cs->base & 0xffff0000) |
2241 (cs->mbus_attr << 8) |
2242 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2243 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2244
2245 win_enable &= ~(1 << i);
2246 win_protect |= 3 << (2 * i);
2247 }
2248
2249 writel(win_enable, base + WINDOW_BAR_ENABLE);
2250 msp->win_protect = win_protect;
9f8dd319
DF		 2251}
2252
773fc3ee
LB		 2253static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2254{
2255 /*
2256 * Check whether we have a 14-bit coal limit field in bits
2257 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2258 * SDMA config register.
2259 */
2260 writel(0x02000000, msp->base + SDMA_CONFIG(0));
2261 if (readl(msp->base + SDMA_CONFIG(0)) & 0x02000000)
2262 msp->extended_rx_coal_limit = 1;
2263 else
2264 msp->extended_rx_coal_limit = 0;
1e881592
LB		 2265
2266 /*
2267 * Check whether the TX rate control registers are in the
2268 * old or the new place.
2269 */
2270 writel(1, msp->base + TX_BW_MTU_MOVED(0));
2271 if (readl(msp->base + TX_BW_MTU_MOVED(0)) & 1)
2272 msp->tx_bw_control_moved = 1;
2273 else
2274 msp->tx_bw_control_moved = 0;
773fc3ee
LB		 2275}
2276
c9df406f 2277static int mv643xx_eth_shared_probe(struct platform_device *pdev)
9f8dd319 2278{
e5371493 2279 static int mv643xx_eth_version_printed = 0;
c9df406f 2280 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
e5371493 2281 struct mv643xx_eth_shared_private *msp;
c9df406f
LB		 2282 struct resource *res;
2283 int ret;
9f8dd319 2284
e5371493 2285 if (!mv643xx_eth_version_printed++)
7dde154d
LB		 2286 printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet "
2287 "driver version %s\n", mv643xx_eth_driver_version);
9f8dd319 2288
c9df406f
LB		 2289 ret = -EINVAL;
2290 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2291 if (res == NULL)
2292 goto out;
9f8dd319 2293
c9df406f
LB		 2294 ret = -ENOMEM;
2295 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2296 if (msp == NULL)
2297 goto out;
2298 memset(msp, 0, sizeof(*msp));
2299
cc9754b3
LB		 2300 msp->base = ioremap(res->start, res->end - res->start + 1);
2301 if (msp->base == NULL)
c9df406f
LB		 2302 goto out_free;
2303
2304 spin_lock_init(&msp->phy_lock);
c9df406f
LB		 2305
2306 /*
2307 * (Re-)program MBUS remapping windows if we are asked to.
2308 */
2309 if (pd != NULL && pd->dram != NULL)
2310 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2311
fc32b0e2
LB		 2312 /*
2313 * Detect hardware parameters.
2314 */
2315 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
773fc3ee 2316 infer_hw_params(msp);
fc32b0e2
LB		 2317
2318 platform_set_drvdata(pdev, msp);
2319
c9df406f
LB		 2320 return 0;
2321
2322out_free:
2323 kfree(msp);
2324out:
2325 return ret;
2326}
2327
2328static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2329{
e5371493 2330 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
c9df406f 2331
cc9754b3 2332 iounmap(msp->base);
c9df406f
LB		 2333 kfree(msp);
2334
2335 return 0;
9f8dd319
DF		 2336}
2337
c9df406f 2338static struct platform_driver mv643xx_eth_shared_driver = {
fc32b0e2
LB		 2339 .probe = mv643xx_eth_shared_probe,
2340 .remove = mv643xx_eth_shared_remove,
c9df406f 2341 .driver = {
fc32b0e2 2342 .name = MV643XX_ETH_SHARED_NAME,
c9df406f
LB		 2343 .owner = THIS_MODULE,
2344 },
2345};
2346
e5371493 2347static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
1da177e4 2348{
c9df406f 2349 int addr_shift = 5 * mp->port_num;
fc32b0e2 2350 u32 data;
1da177e4 2351
fc32b0e2
LB		 2352 data = rdl(mp, PHY_ADDR);
2353 data &= ~(0x1f << addr_shift);
2354 data |= (phy_addr & 0x1f) << addr_shift;
2355 wrl(mp, PHY_ADDR, data);
1da177e4
LT		 2356}
2357
e5371493 2358static int phy_addr_get(struct mv643xx_eth_private *mp)
1da177e4 2359{
fc32b0e2
LB		 2360 unsigned int data;
2361
2362 data = rdl(mp, PHY_ADDR);
2363
2364 return (data >> (5 * mp->port_num)) & 0x1f;
2365}
2366
2367static void set_params(struct mv643xx_eth_private *mp,
2368 struct mv643xx_eth_platform_data *pd)
2369{
2370 struct net_device *dev = mp->dev;
2371
2372 if (is_valid_ether_addr(pd->mac_addr))
2373 memcpy(dev->dev_addr, pd->mac_addr, 6);
2374 else
2375 uc_addr_get(mp, dev->dev_addr);
2376
2377 if (pd->phy_addr == -1) {
2378 mp->shared_smi = NULL;
2379 mp->phy_addr = -1;
2380 } else {
2381 mp->shared_smi = mp->shared;
2382 if (pd->shared_smi != NULL)
2383 mp->shared_smi = platform_get_drvdata(pd->shared_smi);
2384
2385 if (pd->force_phy_addr || pd->phy_addr) {
2386 mp->phy_addr = pd->phy_addr & 0x3f;
2387 phy_addr_set(mp, mp->phy_addr);
2388 } else {
2389 mp->phy_addr = phy_addr_get(mp);
2390 }
2391 }
1da177e4 2392
fc32b0e2
LB		 2393 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2394 if (pd->rx_queue_size)
2395 mp->default_rx_ring_size = pd->rx_queue_size;
2396 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2397 mp->rx_desc_sram_size = pd->rx_sram_size;
1da177e4 2398
64da80a2
LB		 2399 if (pd->rx_queue_mask)
2400 mp->rxq_mask = pd->rx_queue_mask;
2401 else
2402 mp->rxq_mask = 0x01;
2403 mp->rxq_primary = fls(mp->rxq_mask) - 1;
2404
fc32b0e2
LB		 2405 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2406 if (pd->tx_queue_size)
2407 mp->default_tx_ring_size = pd->tx_queue_size;
2408 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2409 mp->tx_desc_sram_size = pd->tx_sram_size;
3d6b35bc
LB		 2410
2411 if (pd->tx_queue_mask)
2412 mp->txq_mask = pd->tx_queue_mask;
2413 else
2414 mp->txq_mask = 0x01;
2415 mp->txq_primary = fls(mp->txq_mask) - 1;
1da177e4
LT		 2416}
2417
e5371493 2418static int phy_detect(struct mv643xx_eth_private *mp)
1da177e4 2419{
fc32b0e2
LB		 2420 unsigned int data;
2421 unsigned int data2;
2422
7f106c1d
LB		 2423 smi_reg_read(mp, mp->phy_addr, MII_BMCR, &data);
2424 smi_reg_write(mp, mp->phy_addr, MII_BMCR, data ^ BMCR_ANENABLE);
1da177e4 2425
7f106c1d
LB		 2426 smi_reg_read(mp, mp->phy_addr, MII_BMCR, &data2);
2427 if (((data ^ data2) & BMCR_ANENABLE) == 0)
fc32b0e2 2428 return -ENODEV;
1da177e4 2429
7f106c1d 2430 smi_reg_write(mp, mp->phy_addr, MII_BMCR, data);
1da177e4 2431
c9df406f 2432 return 0;
1da177e4
LT		 2433}
2434
fc32b0e2
LB		 2435static int phy_init(struct mv643xx_eth_private *mp,
2436 struct mv643xx_eth_platform_data *pd)
c28a4f89 2437{
fc32b0e2
LB		 2438 struct ethtool_cmd cmd;
2439 int err;
c28a4f89 2440
fc32b0e2
LB		 2441 err = phy_detect(mp);
2442 if (err) {
2443 dev_printk(KERN_INFO, &mp->dev->dev,
2444 "no PHY detected at addr %d\n", mp->phy_addr);
2445 return err;
2446 }
2447 phy_reset(mp);
2448
2449 mp->mii.phy_id = mp->phy_addr;
2450 mp->mii.phy_id_mask = 0x3f;
2451 mp->mii.reg_num_mask = 0x1f;
2452 mp->mii.dev = mp->dev;
2453 mp->mii.mdio_read = mv643xx_eth_mdio_read;
2454 mp->mii.mdio_write = mv643xx_eth_mdio_write;
c28a4f89 2455
fc32b0e2 2456 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
c9df406f 2457
fc32b0e2
LB		 2458 memset(&cmd, 0, sizeof(cmd));
2459
2460 cmd.port = PORT_MII;
2461 cmd.transceiver = XCVR_INTERNAL;
2462 cmd.phy_address = mp->phy_addr;
2463 if (pd->speed == 0) {
2464 cmd.autoneg = AUTONEG_ENABLE;
2465 cmd.speed = SPEED_100;
2466 cmd.advertising = ADVERTISED_10baseT_Half |
2467 ADVERTISED_10baseT_Full |
2468 ADVERTISED_100baseT_Half |
2469 ADVERTISED_100baseT_Full;
c9df406f 2470 if (mp->mii.supports_gmii)
fc32b0e2 2471 cmd.advertising |= ADVERTISED_1000baseT_Full;
c9df406f 2472 } else {
fc32b0e2
LB		 2473 cmd.autoneg = AUTONEG_DISABLE;
2474 cmd.speed = pd->speed;
2475 cmd.duplex = pd->duplex;
c9df406f 2476 }
fc32b0e2 2477
fc32b0e2
LB		 2478 mv643xx_eth_set_settings(mp->dev, &cmd);
2479
2480 return 0;
c28a4f89
JC		 2481}
2482
81600eea
LB		 2483static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2484{
2485 u32 pscr;
2486
2487 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2488 if (pscr & SERIAL_PORT_ENABLE) {
2489 pscr &= ~SERIAL_PORT_ENABLE;
2490 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2491 }
2492
2493 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
2494 if (mp->phy_addr == -1) {
2495 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2496 if (speed == SPEED_1000)
2497 pscr |= SET_GMII_SPEED_TO_1000;
2498 else if (speed == SPEED_100)
2499 pscr |= SET_MII_SPEED_TO_100;
2500
2501 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2502
2503 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2504 if (duplex == DUPLEX_FULL)
2505 pscr |= SET_FULL_DUPLEX_MODE;
2506 }
2507
2508 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2509}
2510
c9df406f 2511static int mv643xx_eth_probe(struct platform_device *pdev)
1da177e4 2512{
c9df406f 2513 struct mv643xx_eth_platform_data *pd;
e5371493 2514 struct mv643xx_eth_private *mp;
c9df406f 2515 struct net_device *dev;
c9df406f 2516 struct resource *res;
c9df406f 2517 DECLARE_MAC_BUF(mac);
fc32b0e2 2518 int err;
1da177e4 2519
c9df406f
LB		 2520 pd = pdev->dev.platform_data;
2521 if (pd == NULL) {
fc32b0e2
LB		 2522 dev_printk(KERN_ERR, &pdev->dev,
2523 "no mv643xx_eth_platform_data\n");
c9df406f
LB		 2524 return -ENODEV;
2525 }
1da177e4 2526
c9df406f 2527 if (pd->shared == NULL) {
fc32b0e2
LB		 2528 dev_printk(KERN_ERR, &pdev->dev,
2529 "no mv643xx_eth_platform_data->shared\n");
c9df406f
LB		 2530 return -ENODEV;
2531 }
8f518703 2532
e5371493 2533 dev = alloc_etherdev(sizeof(struct mv643xx_eth_private));
c9df406f
LB		 2534 if (!dev)
2535 return -ENOMEM;
1da177e4 2536
c9df406f 2537 mp = netdev_priv(dev);
fc32b0e2
LB		 2538 platform_set_drvdata(pdev, mp);
2539
2540 mp->shared = platform_get_drvdata(pd->shared);
2541 mp->port_num = pd->port_number;
2542
c9df406f 2543 mp->dev = dev;
e5371493
LB		 2544#ifdef MV643XX_ETH_NAPI
2545 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 64);
c9df406f 2546#endif
1da177e4 2547
fc32b0e2
LB		 2548 set_params(mp, pd);
2549
2550 spin_lock_init(&mp->lock);
2551
2552 mib_counters_clear(mp);
2553 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2554
bedfe324
LB		 2555 if (mp->phy_addr != -1) {
2556 err = phy_init(mp, pd);
2557 if (err)
2558 goto out;
2559
2560 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2561 } else {
2562 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless);
2563 }
81600eea 2564 init_pscr(mp, pd->speed, pd->duplex);
fc32b0e2
LB		 2565
2566
c9df406f
LB		 2567 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2568 BUG_ON(!res);
2569 dev->irq = res->start;
1da177e4 2570
fc32b0e2 2571 dev->hard_start_xmit = mv643xx_eth_xmit;
c9df406f
LB		 2572 dev->open = mv643xx_eth_open;
2573 dev->stop = mv643xx_eth_stop;
c9df406f 2574 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
fc32b0e2
LB		 2575 dev->set_mac_address = mv643xx_eth_set_mac_address;
2576 dev->do_ioctl = mv643xx_eth_ioctl;
2577 dev->change_mtu = mv643xx_eth_change_mtu;
c9df406f 2578 dev->tx_timeout = mv643xx_eth_tx_timeout;
c9df406f 2579#ifdef CONFIG_NET_POLL_CONTROLLER
e5371493 2580 dev->poll_controller = mv643xx_eth_netpoll;
c9df406f 2581#endif
c9df406f
LB		 2582 dev->watchdog_timeo = 2 * HZ;
2583 dev->base_addr = 0;
1da177e4 2584
e5371493 2585#ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
b4de9051 2586 /*
c9df406f
LB		 2587 * Zero copy can only work if we use Discovery II memory. Else, we will
2588 * have to map the buffers to ISA memory which is only 16 MB
b4de9051 2589 */
c9df406f 2590 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
e32b6617 2591 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
c9df406f 2592#endif
1da177e4 2593
fc32b0e2 2594 SET_NETDEV_DEV(dev, &pdev->dev);
8f518703 2595
c9df406f 2596 if (mp->shared->win_protect)
fc32b0e2 2597 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
1da177e4 2598
c9df406f
LB		 2599 err = register_netdev(dev);
2600 if (err)
2601 goto out;
1da177e4 2602
fc32b0e2
LB		 2603 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %s\n",
2604 mp->port_num, print_mac(mac, dev->dev_addr));
1da177e4 2605
c9df406f 2606 if (dev->features & NETIF_F_SG)
fc32b0e2 2607 dev_printk(KERN_NOTICE, &dev->dev, "scatter/gather enabled\n");
1da177e4 2608
c9df406f 2609 if (dev->features & NETIF_F_IP_CSUM)
fc32b0e2 2610 dev_printk(KERN_NOTICE, &dev->dev, "tx checksum offload\n");
1da177e4 2611
e5371493 2612#ifdef MV643XX_ETH_NAPI
fc32b0e2 2613 dev_printk(KERN_NOTICE, &dev->dev, "napi enabled\n");
c9df406f 2614#endif
1da177e4 2615
13d64285 2616 if (mp->tx_desc_sram_size > 0)
fc32b0e2 2617 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
1da177e4 2618
c9df406f 2619 return 0;
1da177e4 2620
c9df406f
LB		 2621out:
2622 free_netdev(dev);
1da177e4 2623
c9df406f 2624 return err;
1da177e4
LT		 2625}
2626
c9df406f 2627static int mv643xx_eth_remove(struct platform_device *pdev)
1da177e4 2628{
fc32b0e2 2629 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
1da177e4 2630
fc32b0e2 2631 unregister_netdev(mp->dev);
c9df406f 2632 flush_scheduled_work();
fc32b0e2 2633 free_netdev(mp->dev);
c9df406f 2634
c9df406f 2635 platform_set_drvdata(pdev, NULL);
fc32b0e2 2636
c9df406f 2637 return 0;
1da177e4
LT		 2638}
2639
c9df406f 2640static void mv643xx_eth_shutdown(struct platform_device *pdev)
d0412d96 2641{
fc32b0e2 2642 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
d0412d96 2643
c9df406f 2644 /* Mask all interrupts on ethernet port */
fc32b0e2
LB		 2645 wrl(mp, INT_MASK(mp->port_num), 0);
2646 rdl(mp, INT_MASK(mp->port_num));
c9df406f 2647
fc32b0e2
LB		 2648 if (netif_running(mp->dev))
2649 port_reset(mp);
d0412d96
JC		 2650}
2651
c9df406f 2652static struct platform_driver mv643xx_eth_driver = {
fc32b0e2
LB		 2653 .probe = mv643xx_eth_probe,
2654 .remove = mv643xx_eth_remove,
2655 .shutdown = mv643xx_eth_shutdown,
c9df406f 2656 .driver = {
fc32b0e2 2657 .name = MV643XX_ETH_NAME,
c9df406f
LB		 2658 .owner = THIS_MODULE,
2659 },
2660};
2661
e5371493 2662static int __init mv643xx_eth_init_module(void)
d0412d96 2663{
c9df406f 2664 int rc;
d0412d96 2665
c9df406f
LB		 2666 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2667 if (!rc) {
2668 rc = platform_driver_register(&mv643xx_eth_driver);
2669 if (rc)
2670 platform_driver_unregister(&mv643xx_eth_shared_driver);
2671 }
fc32b0e2 2672
c9df406f 2673 return rc;
d0412d96 2674}
fc32b0e2 2675module_init(mv643xx_eth_init_module);
d0412d96 2676
e5371493 2677static void __exit mv643xx_eth_cleanup_module(void)
d0412d96 2678{
c9df406f
LB		 2679 platform_driver_unregister(&mv643xx_eth_driver);
2680 platform_driver_unregister(&mv643xx_eth_shared_driver);
d0412d96 2681}
e5371493 2682module_exit(mv643xx_eth_cleanup_module);
1da177e4 2683
45675bc6
LB		 2684MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2685 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
c9df406f 2686MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
fc32b0e2 2687MODULE_LICENSE("GPL");
c9df406f 2688MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
fc32b0e2 2689MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
Linux 6.x block layer and io_uring tree(s)