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mv643xx_eth: use symbolic MII register addresses and values
[linux-2.6-block.git] / drivers / net / mv643xx_eth.c
CommitLineData
1da177e4 1/*
9c1bbdfe 2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
1da177e4
LT		 3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
4547fa61
LB		 6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
1da177e4
LT		 8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
3bb8a18a 10 * written by Manish Lachwani
1da177e4
LT		 11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
c8aaea25 14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
1da177e4
LT		 15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
4547fa61
LB		 20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
1da177e4
LT		 23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36 */
a779d38c 37
1da177e4
LT		 38#include <linux/init.h>
39#include <linux/dma-mapping.h>
b6298c22 40#include <linux/in.h>
1da177e4
LT		 41#include <linux/tcp.h>
42#include <linux/udp.h>
43#include <linux/etherdevice.h>
1da177e4
LT		 44#include <linux/delay.h>
45#include <linux/ethtool.h>
d052d1be 46#include <linux/platform_device.h>
fbd6a754
LB		 47#include <linux/module.h>
48#include <linux/kernel.h>
49#include <linux/spinlock.h>
50#include <linux/workqueue.h>
51#include <linux/mii.h>
fbd6a754 52#include <linux/mv643xx_eth.h>
1da177e4
LT		 53#include <asm/io.h>
54#include <asm/types.h>
1da177e4 55#include <asm/system.h>
fbd6a754 56
e5371493 57static char mv643xx_eth_driver_name[] = "mv643xx_eth";
45675bc6 58static char mv643xx_eth_driver_version[] = "1.1";
c9df406f 59
e5371493
LB		 60#define MV643XX_ETH_CHECKSUM_OFFLOAD_TX
61#define MV643XX_ETH_NAPI
62#define MV643XX_ETH_TX_FAST_REFILL
fbd6a754 63
e5371493 64#ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
fbd6a754
LB		 65#define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
66#else
67#define MAX_DESCS_PER_SKB 1
68#endif
69
fbd6a754
LB		 70/*
71 * Registers shared between all ports.
72 */
3cb4667c
LB		 73#define PHY_ADDR 0x0000
74#define SMI_REG 0x0004
75#define WINDOW_BASE(w) (0x0200 + ((w) << 3))
76#define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
77#define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
78#define WINDOW_BAR_ENABLE 0x0290
79#define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
fbd6a754
LB		 80
81/*
82 * Per-port registers.
83 */
3cb4667c 84#define PORT_CONFIG(p) (0x0400 + ((p) << 10))
d9a073ea 85#define UNICAST_PROMISCUOUS_MODE 0x00000001
3cb4667c
LB		 86#define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
87#define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
88#define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
89#define SDMA_CONFIG(p) (0x041c + ((p) << 10))
90#define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
91#define PORT_STATUS(p) (0x0444 + ((p) << 10))
a2a41689 92#define TX_FIFO_EMPTY 0x00000400
ae9ae064 93#define TX_IN_PROGRESS 0x00000080
3cb4667c 94#define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
89df5fdc
LB		 95#define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10))
96#define TX_BW_RATE(p) (0x0450 + ((p) << 10))
3cb4667c 97#define TX_BW_MTU(p) (0x0458 + ((p) << 10))
89df5fdc 98#define TX_BW_BURST(p) (0x045c + ((p) << 10))
3cb4667c 99#define INT_CAUSE(p) (0x0460 + ((p) << 10))
8fa89bf5 100#define INT_TX_END_0 0x00080000
226bb6b7 101#define INT_TX_END 0x07f80000
64da80a2 102#define INT_RX 0x0007fbfc
073a345c 103#define INT_EXT 0x00000002
3cb4667c 104#define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
073a345c
LB		 105#define INT_EXT_LINK 0x00100000
106#define INT_EXT_PHY 0x00010000
107#define INT_EXT_TX_ERROR_0 0x00000100
108#define INT_EXT_TX_0 0x00000001
3d6b35bc 109#define INT_EXT_TX 0x0000ffff
3cb4667c
LB		 110#define INT_MASK(p) (0x0468 + ((p) << 10))
111#define INT_MASK_EXT(p) (0x046c + ((p) << 10))
112#define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
1e881592
LB		 113#define TXQ_FIX_PRIO_CONF_MOVED(p) (0x04dc + ((p) << 10))
114#define TX_BW_RATE_MOVED(p) (0x04e0 + ((p) << 10))
115#define TX_BW_MTU_MOVED(p) (0x04e8 + ((p) << 10))
116#define TX_BW_BURST_MOVED(p) (0x04ec + ((p) << 10))
64da80a2 117#define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4))
3cb4667c 118#define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
3d6b35bc
LB		 119#define TXQ_CURRENT_DESC_PTR(p, q) (0x06c0 + ((p) << 10) + ((q) << 2))
120#define TXQ_BW_TOKENS(p, q) (0x0700 + ((p) << 10) + ((q) << 4))
121#define TXQ_BW_CONF(p, q) (0x0704 + ((p) << 10) + ((q) << 4))
122#define TXQ_BW_WRR_CONF(p, q) (0x0708 + ((p) << 10) + ((q) << 4))
3cb4667c
LB		 123#define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
124#define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
125#define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
126#define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
fbd6a754 127
2679a550
LB		 128
129/*
130 * SDMA configuration register.
131 */
cd4ccf76 132#define RX_BURST_SIZE_16_64BIT (4 << 1)
fbd6a754 133#define BLM_RX_NO_SWAP (1 << 4)
fbd6a754 134#define BLM_TX_NO_SWAP (1 << 5)
cd4ccf76 135#define TX_BURST_SIZE_16_64BIT (4 << 22)
fbd6a754
LB		 136
137#if defined(__BIG_ENDIAN)
138#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
cd4ccf76
LB		 139 RX_BURST_SIZE_16_64BIT | \
140 TX_BURST_SIZE_16_64BIT
fbd6a754
LB		 141#elif defined(__LITTLE_ENDIAN)
142#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
cd4ccf76 143 RX_BURST_SIZE_16_64BIT | \
fbd6a754
LB		 144 BLM_RX_NO_SWAP | \
145 BLM_TX_NO_SWAP | \
cd4ccf76 146 TX_BURST_SIZE_16_64BIT
fbd6a754
LB		 147#else
148#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
149#endif
150
2beff77b
LB		 151
152/*
153 * Port serial control register.
154 */
155#define SET_MII_SPEED_TO_100 (1 << 24)
156#define SET_GMII_SPEED_TO_1000 (1 << 23)
157#define SET_FULL_DUPLEX_MODE (1 << 21)
fbd6a754
LB		 158#define MAX_RX_PACKET_9700BYTE (5 << 17)
159#define MAX_RX_PACKET_MASK (7 << 17)
2beff77b
LB		 160#define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
161#define DO_NOT_FORCE_LINK_FAIL (1 << 10)
162#define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
163#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
164#define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
165#define FORCE_LINK_PASS (1 << 1)
166#define SERIAL_PORT_ENABLE (1 << 0)
fbd6a754 167
cc9754b3
LB		 168#define DEFAULT_RX_QUEUE_SIZE 400
169#define DEFAULT_TX_QUEUE_SIZE 800
fbd6a754 170
fbd6a754 171
7ca72a3b
LB		 172/*
173 * RX/TX descriptors.
fbd6a754
LB		 174 */
175#if defined(__BIG_ENDIAN)
cc9754b3 176struct rx_desc {
fbd6a754
LB		 177 u16 byte_cnt; /* Descriptor buffer byte count */
178 u16 buf_size; /* Buffer size */
179 u32 cmd_sts; /* Descriptor command status */
180 u32 next_desc_ptr; /* Next descriptor pointer */
181 u32 buf_ptr; /* Descriptor buffer pointer */
182};
183
cc9754b3 184struct tx_desc {
fbd6a754
LB		 185 u16 byte_cnt; /* buffer byte count */
186 u16 l4i_chk; /* CPU provided TCP checksum */
187 u32 cmd_sts; /* Command/status field */
188 u32 next_desc_ptr; /* Pointer to next descriptor */
189 u32 buf_ptr; /* pointer to buffer for this descriptor*/
190};
191#elif defined(__LITTLE_ENDIAN)
cc9754b3 192struct rx_desc {
fbd6a754
LB		 193 u32 cmd_sts; /* Descriptor command status */
194 u16 buf_size; /* Buffer size */
195 u16 byte_cnt; /* Descriptor buffer byte count */
196 u32 buf_ptr; /* Descriptor buffer pointer */
197 u32 next_desc_ptr; /* Next descriptor pointer */
198};
199
cc9754b3 200struct tx_desc {
fbd6a754
LB		 201 u32 cmd_sts; /* Command/status field */
202 u16 l4i_chk; /* CPU provided TCP checksum */
203 u16 byte_cnt; /* buffer byte count */
204 u32 buf_ptr; /* pointer to buffer for this descriptor*/
205 u32 next_desc_ptr; /* Pointer to next descriptor */
206};
207#else
208#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
209#endif
210
7ca72a3b 211/* RX & TX descriptor command */
cc9754b3 212#define BUFFER_OWNED_BY_DMA 0x80000000
7ca72a3b
LB		 213
214/* RX & TX descriptor status */
cc9754b3 215#define ERROR_SUMMARY 0x00000001
7ca72a3b
LB		 216
217/* RX descriptor status */
cc9754b3
LB		 218#define LAYER_4_CHECKSUM_OK 0x40000000
219#define RX_ENABLE_INTERRUPT 0x20000000
220#define RX_FIRST_DESC 0x08000000
221#define RX_LAST_DESC 0x04000000
7ca72a3b
LB		 222
223/* TX descriptor command */
cc9754b3
LB		 224#define TX_ENABLE_INTERRUPT 0x00800000
225#define GEN_CRC 0x00400000
226#define TX_FIRST_DESC 0x00200000
227#define TX_LAST_DESC 0x00100000
228#define ZERO_PADDING 0x00080000
229#define GEN_IP_V4_CHECKSUM 0x00040000
230#define GEN_TCP_UDP_CHECKSUM 0x00020000
231#define UDP_FRAME 0x00010000
7ca72a3b 232
cc9754b3 233#define TX_IHL_SHIFT 11
7ca72a3b
LB		 234
235
c9df406f 236/* global *******************************************************************/
e5371493 237struct mv643xx_eth_shared_private {
fc32b0e2
LB		 238 /*
239 * Ethernet controller base address.
240 */
cc9754b3 241 void __iomem *base;
c9df406f 242
fc32b0e2
LB		 243 /*
244 * Protects access to SMI_REG, which is shared between ports.
245 */
c9df406f
LB		 246 spinlock_t phy_lock;
247
fc32b0e2
LB		 248 /*
249 * Per-port MBUS window access register value.
250 */
c9df406f
LB		 251 u32 win_protect;
252
fc32b0e2
LB		 253 /*
254 * Hardware-specific parameters.
255 */
c9df406f 256 unsigned int t_clk;
773fc3ee 257 int extended_rx_coal_limit;
1e881592 258 int tx_bw_control_moved;
c9df406f
LB		 259};
260
261
262/* per-port *****************************************************************/
e5371493 263struct mib_counters {
fbd6a754
LB		 264 u64 good_octets_received;
265 u32 bad_octets_received;
266 u32 internal_mac_transmit_err;
267 u32 good_frames_received;
268 u32 bad_frames_received;
269 u32 broadcast_frames_received;
270 u32 multicast_frames_received;
271 u32 frames_64_octets;
272 u32 frames_65_to_127_octets;
273 u32 frames_128_to_255_octets;
274 u32 frames_256_to_511_octets;
275 u32 frames_512_to_1023_octets;
276 u32 frames_1024_to_max_octets;
277 u64 good_octets_sent;
278 u32 good_frames_sent;
279 u32 excessive_collision;
280 u32 multicast_frames_sent;
281 u32 broadcast_frames_sent;
282 u32 unrec_mac_control_received;
283 u32 fc_sent;
284 u32 good_fc_received;
285 u32 bad_fc_received;
286 u32 undersize_received;
287 u32 fragments_received;
288 u32 oversize_received;
289 u32 jabber_received;
290 u32 mac_receive_error;
291 u32 bad_crc_event;
292 u32 collision;
293 u32 late_collision;
294};
295
8a578111 296struct rx_queue {
64da80a2
LB		 297 int index;
298
8a578111
LB		 299 int rx_ring_size;
300
301 int rx_desc_count;
302 int rx_curr_desc;
303 int rx_used_desc;
304
305 struct rx_desc *rx_desc_area;
306 dma_addr_t rx_desc_dma;
307 int rx_desc_area_size;
308 struct sk_buff **rx_skb;
309
310 struct timer_list rx_oom;
311};
312
13d64285 313struct tx_queue {
3d6b35bc
LB		 314 int index;
315
13d64285 316 int tx_ring_size;
fbd6a754 317
13d64285
LB		 318 int tx_desc_count;
319 int tx_curr_desc;
320 int tx_used_desc;
fbd6a754 321
5daffe94 322 struct tx_desc *tx_desc_area;
fbd6a754
LB		 323 dma_addr_t tx_desc_dma;
324 int tx_desc_area_size;
325 struct sk_buff **tx_skb;
13d64285
LB		 326};
327
328struct mv643xx_eth_private {
329 struct mv643xx_eth_shared_private *shared;
fc32b0e2 330 int port_num;
13d64285 331
fc32b0e2 332 struct net_device *dev;
fbd6a754 333
fc32b0e2
LB		 334 struct mv643xx_eth_shared_private *shared_smi;
335 int phy_addr;
fbd6a754 336
fbd6a754 337 spinlock_t lock;
fbd6a754 338
fc32b0e2
LB		 339 struct mib_counters mib_counters;
340 struct work_struct tx_timeout_task;
fbd6a754 341 struct mii_if_info mii;
8a578111
LB		 342
343 /*
344 * RX state.
345 */
346 int default_rx_ring_size;
347 unsigned long rx_desc_sram_addr;
348 int rx_desc_sram_size;
64da80a2
LB		 349 u8 rxq_mask;
350 int rxq_primary;
8a578111 351 struct napi_struct napi;
64da80a2 352 struct rx_queue rxq[8];
13d64285
LB		 353
354 /*
355 * TX state.
356 */
357 int default_tx_ring_size;
358 unsigned long tx_desc_sram_addr;
359 int tx_desc_sram_size;
3d6b35bc
LB		 360 u8 txq_mask;
361 int txq_primary;
362 struct tx_queue txq[8];
13d64285
LB		 363#ifdef MV643XX_ETH_TX_FAST_REFILL
364 int tx_clean_threshold;
365#endif
fbd6a754 366};
1da177e4 367
fbd6a754 368
c9df406f 369/* port register accessors **************************************************/
e5371493 370static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
c9df406f 371{
cc9754b3 372 return readl(mp->shared->base + offset);
c9df406f 373}
fbd6a754 374
e5371493 375static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
c9df406f 376{
cc9754b3 377 writel(data, mp->shared->base + offset);
c9df406f 378}
fbd6a754 379
fbd6a754 380
c9df406f 381/* rxq/txq helper functions *************************************************/
8a578111 382static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
c9df406f 383{
64da80a2 384 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
c9df406f 385}
fbd6a754 386
13d64285
LB		 387static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
388{
3d6b35bc 389 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
13d64285
LB		 390}
391
8a578111 392static void rxq_enable(struct rx_queue *rxq)
c9df406f 393{
8a578111 394 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
64da80a2 395 wrl(mp, RXQ_COMMAND(mp->port_num), 1 << rxq->index);
8a578111 396}
1da177e4 397
8a578111
LB		 398static void rxq_disable(struct rx_queue *rxq)
399{
400 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
64da80a2 401 u8 mask = 1 << rxq->index;
1da177e4 402
8a578111
LB		 403 wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8);
404 while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask)
405 udelay(10);
c9df406f
LB		 406}
407
6b368f68
LB		 408static void txq_reset_hw_ptr(struct tx_queue *txq)
409{
410 struct mv643xx_eth_private *mp = txq_to_mp(txq);
411 int off = TXQ_CURRENT_DESC_PTR(mp->port_num, txq->index);
412 u32 addr;
413
414 addr = (u32)txq->tx_desc_dma;
415 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
416 wrl(mp, off, addr);
417}
418
13d64285 419static void txq_enable(struct tx_queue *txq)
1da177e4 420{
13d64285 421 struct mv643xx_eth_private *mp = txq_to_mp(txq);
3d6b35bc 422 wrl(mp, TXQ_COMMAND(mp->port_num), 1 << txq->index);
1da177e4
LT		 423}
424
13d64285 425static void txq_disable(struct tx_queue *txq)
1da177e4 426{
13d64285 427 struct mv643xx_eth_private *mp = txq_to_mp(txq);
3d6b35bc 428 u8 mask = 1 << txq->index;
c9df406f 429
13d64285
LB		 430 wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8);
431 while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask)
432 udelay(10);
433}
434
435static void __txq_maybe_wake(struct tx_queue *txq)
436{
437 struct mv643xx_eth_private *mp = txq_to_mp(txq);
438
3d6b35bc
LB		 439 /*
440 * netif_{stop,wake}_queue() flow control only applies to
441 * the primary queue.
442 */
443 BUG_ON(txq->index != mp->txq_primary);
444
13d64285
LB		 445 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_DESCS_PER_SKB)
446 netif_wake_queue(mp->dev);
1da177e4
LT		 447}
448
c9df406f
LB		 449
450/* rx ***********************************************************************/
13d64285 451static void txq_reclaim(struct tx_queue *txq, int force);
c9df406f 452
8a578111 453static void rxq_refill(struct rx_queue *rxq)
1da177e4 454{
8a578111 455 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
c9df406f 456 unsigned long flags;
1da177e4 457
c9df406f 458 spin_lock_irqsave(&mp->lock, flags);
c0d0f2ca 459
8a578111
LB		 460 while (rxq->rx_desc_count < rxq->rx_ring_size) {
461 int skb_size;
de34f225
LB		 462 struct sk_buff *skb;
463 int unaligned;
464 int rx;
465
8a578111
LB		 466 /*
467 * Reserve 2+14 bytes for an ethernet header (the
468 * hardware automatically prepends 2 bytes of dummy
469 * data to each received packet), 4 bytes for a VLAN
470 * header, and 4 bytes for the trailing FCS -- 24
471 * bytes total.
472 */
473 skb_size = mp->dev->mtu + 24;
474
475 skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1);
de34f225 476 if (skb == NULL)
1da177e4 477 break;
de34f225 478
908b637f 479 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
b44cd572 480 if (unaligned)
908b637f 481 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
de34f225 482
8a578111
LB		 483 rxq->rx_desc_count++;
484 rx = rxq->rx_used_desc;
485 rxq->rx_used_desc = (rx + 1) % rxq->rx_ring_size;
de34f225 486
8a578111
LB		 487 rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
488 skb_size, DMA_FROM_DEVICE);
489 rxq->rx_desc_area[rx].buf_size = skb_size;
490 rxq->rx_skb[rx] = skb;
de34f225 491 wmb();
8a578111 492 rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
de34f225
LB		 493 RX_ENABLE_INTERRUPT;
494 wmb();
495
fc32b0e2
LB		 496 /*
497 * The hardware automatically prepends 2 bytes of
498 * dummy data to each received packet, so that the
499 * IP header ends up 16-byte aligned.
500 */
501 skb_reserve(skb, 2);
1da177e4 502 }
de34f225 503
12e4ab79 504 if (rxq->rx_desc_count != rxq->rx_ring_size) {
8a578111
LB		 505 rxq->rx_oom.expires = jiffies + (HZ / 10);
506 add_timer(&rxq->rx_oom);
1da177e4 507 }
de34f225
LB		 508
509 spin_unlock_irqrestore(&mp->lock, flags);
1da177e4
LT		 510}
511
8a578111 512static inline void rxq_refill_timer_wrapper(unsigned long data)
1da177e4 513{
8a578111 514 rxq_refill((struct rx_queue *)data);
1da177e4
LT		 515}
516
8a578111 517static int rxq_process(struct rx_queue *rxq, int budget)
1da177e4 518{
8a578111
LB		 519 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
520 struct net_device_stats *stats = &mp->dev->stats;
521 int rx;
1da177e4 522
8a578111
LB		 523 rx = 0;
524 while (rx < budget) {
fc32b0e2 525 struct rx_desc *rx_desc;
96587661 526 unsigned int cmd_sts;
fc32b0e2 527 struct sk_buff *skb;
96587661 528 unsigned long flags;
d344bff9 529
96587661 530 spin_lock_irqsave(&mp->lock, flags);
ff561eef 531
8a578111 532 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
1da177e4 533
96587661
LB		 534 cmd_sts = rx_desc->cmd_sts;
535 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
536 spin_unlock_irqrestore(&mp->lock, flags);
537 break;
538 }
539 rmb();
1da177e4 540
8a578111
LB		 541 skb = rxq->rx_skb[rxq->rx_curr_desc];
542 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
ff561eef 543
8a578111 544 rxq->rx_curr_desc = (rxq->rx_curr_desc + 1) % rxq->rx_ring_size;
ff561eef 545
96587661 546 spin_unlock_irqrestore(&mp->lock, flags);
1da177e4 547
fc32b0e2
LB		 548 dma_unmap_single(NULL, rx_desc->buf_ptr + 2,
549 mp->dev->mtu + 24, DMA_FROM_DEVICE);
8a578111
LB		 550 rxq->rx_desc_count--;
551 rx++;
b1dd9ca1 552
468d09f8
DF		 553 /*
554 * Update statistics.
fc32b0e2
LB		 555 *
556 * Note that the descriptor byte count includes 2 dummy
557 * bytes automatically inserted by the hardware at the
558 * start of the packet (which we don't count), and a 4
559 * byte CRC at the end of the packet (which we do count).
468d09f8 560 */
1da177e4 561 stats->rx_packets++;
fc32b0e2 562 stats->rx_bytes += rx_desc->byte_cnt - 2;
96587661 563
1da177e4 564 /*
fc32b0e2
LB		 565 * In case we received a packet without first / last bits
566 * on, or the error summary bit is set, the packet needs
567 * to be dropped.
1da177e4 568 */
96587661 569 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
cc9754b3 570 (RX_FIRST_DESC | RX_LAST_DESC))
96587661 571 || (cmd_sts & ERROR_SUMMARY)) {
1da177e4 572 stats->rx_dropped++;
fc32b0e2 573
96587661 574 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
cc9754b3 575 (RX_FIRST_DESC | RX_LAST_DESC)) {
1da177e4 576 if (net_ratelimit())
fc32b0e2
LB		 577 dev_printk(KERN_ERR, &mp->dev->dev,
578 "received packet spanning "
579 "multiple descriptors\n");
1da177e4 580 }
fc32b0e2 581
96587661 582 if (cmd_sts & ERROR_SUMMARY)
1da177e4
LT		 583 stats->rx_errors++;
584
585 dev_kfree_skb_irq(skb);
586 } else {
587 /*
588 * The -4 is for the CRC in the trailer of the
589 * received packet
590 */
fc32b0e2 591 skb_put(skb, rx_desc->byte_cnt - 2 - 4);
1da177e4 592
96587661 593 if (cmd_sts & LAYER_4_CHECKSUM_OK) {
1da177e4
LT		 594 skb->ip_summed = CHECKSUM_UNNECESSARY;
595 skb->csum = htons(
96587661 596 (cmd_sts & 0x0007fff8) >> 3);
1da177e4 597 }
8a578111 598 skb->protocol = eth_type_trans(skb, mp->dev);
e5371493 599#ifdef MV643XX_ETH_NAPI
1da177e4
LT		 600 netif_receive_skb(skb);
601#else
602 netif_rx(skb);
603#endif
604 }
fc32b0e2 605
8a578111 606 mp->dev->last_rx = jiffies;
1da177e4 607 }
fc32b0e2 608
8a578111 609 rxq_refill(rxq);
1da177e4 610
8a578111 611 return rx;
1da177e4
LT		 612}
613
e5371493 614#ifdef MV643XX_ETH_NAPI
e5371493 615static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
d0412d96 616{
8a578111
LB		 617 struct mv643xx_eth_private *mp;
618 int rx;
64da80a2 619 int i;
8a578111
LB		 620
621 mp = container_of(napi, struct mv643xx_eth_private, napi);
d0412d96 622
e5371493 623#ifdef MV643XX_ETH_TX_FAST_REFILL
c9df406f 624 if (++mp->tx_clean_threshold > 5) {
c9df406f 625 mp->tx_clean_threshold = 0;
3d6b35bc
LB		 626 for (i = 0; i < 8; i++)
627 if (mp->txq_mask & (1 << i))
628 txq_reclaim(mp->txq + i, 0);
4dfc1c87
LB		 629
630 if (netif_carrier_ok(mp->dev)) {
631 spin_lock(&mp->lock);
632 __txq_maybe_wake(mp->txq + mp->txq_primary);
633 spin_unlock(&mp->lock);
634 }
d0412d96 635 }
c9df406f 636#endif
d0412d96 637
64da80a2
LB		 638 rx = 0;
639 for (i = 7; rx < budget && i >= 0; i--)
640 if (mp->rxq_mask & (1 << i))
641 rx += rxq_process(mp->rxq + i, budget - rx);
d0412d96 642
8a578111
LB		 643 if (rx < budget) {
644 netif_rx_complete(mp->dev, napi);
645 wrl(mp, INT_CAUSE(mp->port_num), 0);
646 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
226bb6b7 647 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
d0412d96 648 }
c9df406f 649
8a578111 650 return rx;
d0412d96 651}
c9df406f 652#endif
d0412d96 653
c9df406f
LB		 654
655/* tx ***********************************************************************/
c9df406f 656static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1da177e4 657{
13d64285 658 int frag;
1da177e4 659
c9df406f 660 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
13d64285
LB		 661 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
662 if (fragp->size <= 8 && fragp->page_offset & 7)
c9df406f 663 return 1;
1da177e4 664 }
13d64285 665
c9df406f
LB		 666 return 0;
667}
7303fde8 668
13d64285 669static int txq_alloc_desc_index(struct tx_queue *txq)
c9df406f
LB		 670{
671 int tx_desc_curr;
d0412d96 672
13d64285 673 BUG_ON(txq->tx_desc_count >= txq->tx_ring_size);
1da177e4 674
13d64285
LB		 675 tx_desc_curr = txq->tx_curr_desc;
676 txq->tx_curr_desc = (tx_desc_curr + 1) % txq->tx_ring_size;
e4d00fa9 677
13d64285 678 BUG_ON(txq->tx_curr_desc == txq->tx_used_desc);
468d09f8 679
c9df406f
LB		 680 return tx_desc_curr;
681}
468d09f8 682
13d64285 683static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
c9df406f 684{
13d64285 685 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 686 int frag;
1da177e4 687
13d64285
LB		 688 for (frag = 0; frag < nr_frags; frag++) {
689 skb_frag_t *this_frag;
690 int tx_index;
691 struct tx_desc *desc;
692
693 this_frag = &skb_shinfo(skb)->frags[frag];
694 tx_index = txq_alloc_desc_index(txq);
695 desc = &txq->tx_desc_area[tx_index];
696
697 /*
698 * The last fragment will generate an interrupt
699 * which will free the skb on TX completion.
700 */
701 if (frag == nr_frags - 1) {
702 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
703 ZERO_PADDING | TX_LAST_DESC |
704 TX_ENABLE_INTERRUPT;
705 txq->tx_skb[tx_index] = skb;
706 } else {
707 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
708 txq->tx_skb[tx_index] = NULL;
709 }
710
c9df406f
LB		 711 desc->l4i_chk = 0;
712 desc->byte_cnt = this_frag->size;
713 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
714 this_frag->page_offset,
715 this_frag->size,
716 DMA_TO_DEVICE);
717 }
1da177e4
LT		 718}
719
c9df406f
LB		 720static inline __be16 sum16_as_be(__sum16 sum)
721{
722 return (__force __be16)sum;
723}
1da177e4 724
13d64285 725static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
1da177e4 726{
8fa89bf5 727 struct mv643xx_eth_private *mp = txq_to_mp(txq);
13d64285 728 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 729 int tx_index;
cc9754b3 730 struct tx_desc *desc;
c9df406f
LB		 731 u32 cmd_sts;
732 int length;
1da177e4 733
cc9754b3 734 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
1da177e4 735
13d64285
LB		 736 tx_index = txq_alloc_desc_index(txq);
737 desc = &txq->tx_desc_area[tx_index];
c9df406f
LB		 738
739 if (nr_frags) {
13d64285 740 txq_submit_frag_skb(txq, skb);
c9df406f
LB		 741
742 length = skb_headlen(skb);
13d64285 743 txq->tx_skb[tx_index] = NULL;
c9df406f 744 } else {
cc9754b3 745 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
c9df406f 746 length = skb->len;
13d64285 747 txq->tx_skb[tx_index] = skb;
c9df406f
LB		 748 }
749
750 desc->byte_cnt = length;
751 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
752
753 if (skb->ip_summed == CHECKSUM_PARTIAL) {
754 BUG_ON(skb->protocol != htons(ETH_P_IP));
755
cc9754b3
LB		 756 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
757 GEN_IP_V4_CHECKSUM |
758 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
c9df406f
LB		 759
760 switch (ip_hdr(skb)->protocol) {
761 case IPPROTO_UDP:
cc9754b3 762 cmd_sts |= UDP_FRAME;
c9df406f
LB		 763 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
764 break;
765 case IPPROTO_TCP:
766 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
767 break;
768 default:
769 BUG();
770 }
771 } else {
772 /* Errata BTS #50, IHL must be 5 if no HW checksum */
cc9754b3 773 cmd_sts |= 5 << TX_IHL_SHIFT;
c9df406f
LB		 774 desc->l4i_chk = 0;
775 }
776
777 /* ensure all other descriptors are written before first cmd_sts */
778 wmb();
779 desc->cmd_sts = cmd_sts;
780
8fa89bf5
LB		 781 /* clear TX_END interrupt status */
782 wrl(mp, INT_CAUSE(mp->port_num), ~(INT_TX_END_0 << txq->index));
783 rdl(mp, INT_CAUSE(mp->port_num));
784
c9df406f
LB		 785 /* ensure all descriptors are written before poking hardware */
786 wmb();
13d64285 787 txq_enable(txq);
c9df406f 788
13d64285 789 txq->tx_desc_count += nr_frags + 1;
1da177e4 790}
1da177e4 791
fc32b0e2 792static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 793{
e5371493 794 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 795 struct net_device_stats *stats = &dev->stats;
13d64285 796 struct tx_queue *txq;
c9df406f 797 unsigned long flags;
afdb57a2 798
c9df406f
LB		 799 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
800 stats->tx_dropped++;
fc32b0e2
LB		 801 dev_printk(KERN_DEBUG, &dev->dev,
802 "failed to linearize skb with tiny "
803 "unaligned fragment\n");
c9df406f
LB		 804 return NETDEV_TX_BUSY;
805 }
806
807 spin_lock_irqsave(&mp->lock, flags);
808
3d6b35bc 809 txq = mp->txq + mp->txq_primary;
13d64285
LB		 810
811 if (txq->tx_ring_size - txq->tx_desc_count < MAX_DESCS_PER_SKB) {
c9df406f 812 spin_unlock_irqrestore(&mp->lock, flags);
3d6b35bc
LB		 813 if (txq->index == mp->txq_primary && net_ratelimit())
814 dev_printk(KERN_ERR, &dev->dev,
815 "primary tx queue full?!\n");
816 kfree_skb(skb);
817 return NETDEV_TX_OK;
c9df406f
LB		 818 }
819
13d64285 820 txq_submit_skb(txq, skb);
c9df406f
LB		 821 stats->tx_bytes += skb->len;
822 stats->tx_packets++;
823 dev->trans_start = jiffies;
824
3d6b35bc
LB		 825 if (txq->index == mp->txq_primary) {
826 int entries_left;
827
828 entries_left = txq->tx_ring_size - txq->tx_desc_count;
829 if (entries_left < MAX_DESCS_PER_SKB)
830 netif_stop_queue(dev);
831 }
c9df406f
LB		 832
833 spin_unlock_irqrestore(&mp->lock, flags);
834
835 return NETDEV_TX_OK;
1da177e4
LT		 836}
837
c9df406f 838
89df5fdc
LB		 839/* tx rate control **********************************************************/
840/*
841 * Set total maximum TX rate (shared by all TX queues for this port)
842 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
843 */
844static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
845{
846 int token_rate;
847 int mtu;
848 int bucket_size;
849
850 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
851 if (token_rate > 1023)
852 token_rate = 1023;
853
854 mtu = (mp->dev->mtu + 255) >> 8;
855 if (mtu > 63)
856 mtu = 63;
857
858 bucket_size = (burst + 255) >> 8;
859 if (bucket_size > 65535)
860 bucket_size = 65535;
861
1e881592
LB		 862 if (mp->shared->tx_bw_control_moved) {
863 wrl(mp, TX_BW_RATE_MOVED(mp->port_num), token_rate);
864 wrl(mp, TX_BW_MTU_MOVED(mp->port_num), mtu);
865 wrl(mp, TX_BW_BURST_MOVED(mp->port_num), bucket_size);
866 } else {
867 wrl(mp, TX_BW_RATE(mp->port_num), token_rate);
868 wrl(mp, TX_BW_MTU(mp->port_num), mtu);
869 wrl(mp, TX_BW_BURST(mp->port_num), bucket_size);
870 }
89df5fdc
LB		 871}
872
873static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
874{
875 struct mv643xx_eth_private *mp = txq_to_mp(txq);
876 int token_rate;
877 int bucket_size;
878
879 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
880 if (token_rate > 1023)
881 token_rate = 1023;
882
883 bucket_size = (burst + 255) >> 8;
884 if (bucket_size > 65535)
885 bucket_size = 65535;
886
3d6b35bc
LB		 887 wrl(mp, TXQ_BW_TOKENS(mp->port_num, txq->index), token_rate << 14);
888 wrl(mp, TXQ_BW_CONF(mp->port_num, txq->index),
89df5fdc
LB		 889 (bucket_size << 10) | token_rate);
890}
891
892static void txq_set_fixed_prio_mode(struct tx_queue *txq)
893{
894 struct mv643xx_eth_private *mp = txq_to_mp(txq);
895 int off;
896 u32 val;
897
898 /*
899 * Turn on fixed priority mode.
900 */
1e881592
LB		 901 if (mp->shared->tx_bw_control_moved)
902 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
903 else
904 off = TXQ_FIX_PRIO_CONF(mp->port_num);
89df5fdc
LB		 905
906 val = rdl(mp, off);
3d6b35bc 907 val |= 1 << txq->index;
89df5fdc
LB		 908 wrl(mp, off, val);
909}
910
911static void txq_set_wrr(struct tx_queue *txq, int weight)
912{
913 struct mv643xx_eth_private *mp = txq_to_mp(txq);
914 int off;
915 u32 val;
916
917 /*
918 * Turn off fixed priority mode.
919 */
1e881592
LB		 920 if (mp->shared->tx_bw_control_moved)
921 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
922 else
923 off = TXQ_FIX_PRIO_CONF(mp->port_num);
89df5fdc
LB		 924
925 val = rdl(mp, off);
3d6b35bc 926 val &= ~(1 << txq->index);
89df5fdc
LB		 927 wrl(mp, off, val);
928
929 /*
930 * Configure WRR weight for this queue.
931 */
3d6b35bc 932 off = TXQ_BW_WRR_CONF(mp->port_num, txq->index);
89df5fdc
LB		 933
934 val = rdl(mp, off);
935 val = (val & ~0xff) | (weight & 0xff);
936 wrl(mp, off, val);
937}
938
939
c9df406f 940/* mii management interface *************************************************/
fc32b0e2
LB		 941#define SMI_BUSY 0x10000000
942#define SMI_READ_VALID 0x08000000
943#define SMI_OPCODE_READ 0x04000000
944#define SMI_OPCODE_WRITE 0x00000000
c9df406f 945
fc32b0e2
LB		 946static void smi_reg_read(struct mv643xx_eth_private *mp, unsigned int addr,
947 unsigned int reg, unsigned int *value)
1da177e4 948{
cc9754b3 949 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
c9df406f 950 unsigned long flags;
1da177e4
LT		 951 int i;
952
c9df406f
LB		 953 /* the SMI register is a shared resource */
954 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
955
956 /* wait for the SMI register to become available */
cc9754b3 957 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
e1bea50a 958 if (i == 1000) {
c9df406f
LB		 959 printk("%s: PHY busy timeout\n", mp->dev->name);
960 goto out;
961 }
e1bea50a 962 udelay(10);
1da177e4
LT		 963 }
964
fc32b0e2 965 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1da177e4 966
c9df406f 967 /* now wait for the data to be valid */
cc9754b3 968 for (i = 0; !(readl(smi_reg) & SMI_READ_VALID); i++) {
e1bea50a 969 if (i == 1000) {
c9df406f
LB		 970 printk("%s: PHY read timeout\n", mp->dev->name);
971 goto out;
972 }
e1bea50a 973 udelay(10);
c9df406f
LB		 974 }
975
976 *value = readl(smi_reg) & 0xffff;
977out:
978 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
1da177e4
LT		 979}
980
fc32b0e2
LB		 981static void smi_reg_write(struct mv643xx_eth_private *mp,
982 unsigned int addr,
983 unsigned int reg, unsigned int value)
1da177e4 984{
cc9754b3 985 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
c9df406f 986 unsigned long flags;
1da177e4
LT		 987 int i;
988
c9df406f
LB		 989 /* the SMI register is a shared resource */
990 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
991
992 /* wait for the SMI register to become available */
cc9754b3 993 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
e1bea50a 994 if (i == 1000) {
c9df406f
LB		 995 printk("%s: PHY busy timeout\n", mp->dev->name);
996 goto out;
997 }
e1bea50a 998 udelay(10);
1da177e4
LT		 999 }
1000
fc32b0e2
LB		 1001 writel(SMI_OPCODE_WRITE | (reg << 21) |
1002 (addr << 16) | (value & 0xffff), smi_reg);
c9df406f
LB		 1003out:
1004 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
1005}
1da177e4 1006
c9df406f
LB		 1007
1008/* mib counters *************************************************************/
fc32b0e2 1009static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
c9df406f 1010{
fc32b0e2 1011 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1da177e4
LT		 1012}
1013
fc32b0e2 1014static void mib_counters_clear(struct mv643xx_eth_private *mp)
d0412d96 1015{
fc32b0e2
LB		 1016 int i;
1017
1018 for (i = 0; i < 0x80; i += 4)
1019 mib_read(mp, i);
c9df406f 1020}
d0412d96 1021
fc32b0e2 1022static void mib_counters_update(struct mv643xx_eth_private *mp)
c9df406f 1023{
e5371493 1024 struct mib_counters *p = &mp->mib_counters;
4b8e3655 1025
fc32b0e2
LB		 1026 p->good_octets_received += mib_read(mp, 0x00);
1027 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
1028 p->bad_octets_received += mib_read(mp, 0x08);
1029 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1030 p->good_frames_received += mib_read(mp, 0x10);
1031 p->bad_frames_received += mib_read(mp, 0x14);
1032 p->broadcast_frames_received += mib_read(mp, 0x18);
1033 p->multicast_frames_received += mib_read(mp, 0x1c);
1034 p->frames_64_octets += mib_read(mp, 0x20);
1035 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1036 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1037 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1038 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1039 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1040 p->good_octets_sent += mib_read(mp, 0x38);
1041 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1042 p->good_frames_sent += mib_read(mp, 0x40);
1043 p->excessive_collision += mib_read(mp, 0x44);
1044 p->multicast_frames_sent += mib_read(mp, 0x48);
1045 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1046 p->unrec_mac_control_received += mib_read(mp, 0x50);
1047 p->fc_sent += mib_read(mp, 0x54);
1048 p->good_fc_received += mib_read(mp, 0x58);
1049 p->bad_fc_received += mib_read(mp, 0x5c);
1050 p->undersize_received += mib_read(mp, 0x60);
1051 p->fragments_received += mib_read(mp, 0x64);
1052 p->oversize_received += mib_read(mp, 0x68);
1053 p->jabber_received += mib_read(mp, 0x6c);
1054 p->mac_receive_error += mib_read(mp, 0x70);
1055 p->bad_crc_event += mib_read(mp, 0x74);
1056 p->collision += mib_read(mp, 0x78);
1057 p->late_collision += mib_read(mp, 0x7c);
d0412d96
JC		 1058}
1059
c9df406f
LB		 1060
1061/* ethtool ******************************************************************/
e5371493 1062struct mv643xx_eth_stats {
c9df406f
LB		 1063 char stat_string[ETH_GSTRING_LEN];
1064 int sizeof_stat;
16820054
LB		 1065 int netdev_off;
1066 int mp_off;
c9df406f
LB		 1067};
1068
16820054
LB		 1069#define SSTAT(m) \
1070 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1071 offsetof(struct net_device, stats.m), -1 }
1072
1073#define MIBSTAT(m) \
1074 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1075 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1076
1077static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1078 SSTAT(rx_packets),
1079 SSTAT(tx_packets),
1080 SSTAT(rx_bytes),
1081 SSTAT(tx_bytes),
1082 SSTAT(rx_errors),
1083 SSTAT(tx_errors),
1084 SSTAT(rx_dropped),
1085 SSTAT(tx_dropped),
1086 MIBSTAT(good_octets_received),
1087 MIBSTAT(bad_octets_received),
1088 MIBSTAT(internal_mac_transmit_err),
1089 MIBSTAT(good_frames_received),
1090 MIBSTAT(bad_frames_received),
1091 MIBSTAT(broadcast_frames_received),
1092 MIBSTAT(multicast_frames_received),
1093 MIBSTAT(frames_64_octets),
1094 MIBSTAT(frames_65_to_127_octets),
1095 MIBSTAT(frames_128_to_255_octets),
1096 MIBSTAT(frames_256_to_511_octets),
1097 MIBSTAT(frames_512_to_1023_octets),
1098 MIBSTAT(frames_1024_to_max_octets),
1099 MIBSTAT(good_octets_sent),
1100 MIBSTAT(good_frames_sent),
1101 MIBSTAT(excessive_collision),
1102 MIBSTAT(multicast_frames_sent),
1103 MIBSTAT(broadcast_frames_sent),
1104 MIBSTAT(unrec_mac_control_received),
1105 MIBSTAT(fc_sent),
1106 MIBSTAT(good_fc_received),
1107 MIBSTAT(bad_fc_received),
1108 MIBSTAT(undersize_received),
1109 MIBSTAT(fragments_received),
1110 MIBSTAT(oversize_received),
1111 MIBSTAT(jabber_received),
1112 MIBSTAT(mac_receive_error),
1113 MIBSTAT(bad_crc_event),
1114 MIBSTAT(collision),
1115 MIBSTAT(late_collision),
c9df406f
LB		 1116};
1117
e5371493 1118static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
d0412d96 1119{
e5371493 1120 struct mv643xx_eth_private *mp = netdev_priv(dev);
d0412d96
JC		 1121 int err;
1122
1123 spin_lock_irq(&mp->lock);
1124 err = mii_ethtool_gset(&mp->mii, cmd);
1125 spin_unlock_irq(&mp->lock);
1126
fc32b0e2
LB		 1127 /*
1128 * The MAC does not support 1000baseT_Half.
1129 */
d0412d96
JC		 1130 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1131 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1132
1133 return err;
1134}
1135
bedfe324
LB		 1136static int mv643xx_eth_get_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1137{
1138 cmd->supported = SUPPORTED_MII;
1139 cmd->advertising = ADVERTISED_MII;
1140 cmd->speed = SPEED_1000;
1141 cmd->duplex = DUPLEX_FULL;
1142 cmd->port = PORT_MII;
1143 cmd->phy_address = 0;
1144 cmd->transceiver = XCVR_INTERNAL;
1145 cmd->autoneg = AUTONEG_DISABLE;
1146 cmd->maxtxpkt = 1;
1147 cmd->maxrxpkt = 1;
1148
1149 return 0;
1150}
1151
e5371493 1152static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4 1153{
e5371493 1154 struct mv643xx_eth_private *mp = netdev_priv(dev);
ab4384a6
DF		 1155 int err;
1156
fc32b0e2
LB		 1157 /*
1158 * The MAC does not support 1000baseT_Half.
1159 */
1160 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1161
c9df406f
LB		 1162 spin_lock_irq(&mp->lock);
1163 err = mii_ethtool_sset(&mp->mii, cmd);
1164 spin_unlock_irq(&mp->lock);
85cf572c 1165
c9df406f
LB		 1166 return err;
1167}
1da177e4 1168
bedfe324
LB		 1169static int mv643xx_eth_set_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1170{
1171 return -EINVAL;
1172}
1173
fc32b0e2
LB		 1174static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1175 struct ethtool_drvinfo *drvinfo)
c9df406f 1176{
e5371493
LB		 1177 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1178 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
c9df406f 1179 strncpy(drvinfo->fw_version, "N/A", 32);
fc32b0e2 1180 strncpy(drvinfo->bus_info, "platform", 32);
16820054 1181 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
c9df406f 1182}
1da177e4 1183
fc32b0e2 1184static int mv643xx_eth_nway_reset(struct net_device *dev)
c9df406f 1185{
e5371493 1186 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1187
c9df406f
LB		 1188 return mii_nway_restart(&mp->mii);
1189}
1da177e4 1190
bedfe324
LB		 1191static int mv643xx_eth_nway_reset_phyless(struct net_device *dev)
1192{
1193 return -EINVAL;
1194}
1195
c9df406f
LB		 1196static u32 mv643xx_eth_get_link(struct net_device *dev)
1197{
e5371493 1198 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1199
c9df406f
LB		 1200 return mii_link_ok(&mp->mii);
1201}
1da177e4 1202
bedfe324
LB		 1203static u32 mv643xx_eth_get_link_phyless(struct net_device *dev)
1204{
1205 return 1;
1206}
1207
fc32b0e2
LB		 1208static void mv643xx_eth_get_strings(struct net_device *dev,
1209 uint32_t stringset, uint8_t *data)
c9df406f
LB		 1210{
1211 int i;
1da177e4 1212
fc32b0e2
LB		 1213 if (stringset == ETH_SS_STATS) {
1214 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
c9df406f 1215 memcpy(data + i * ETH_GSTRING_LEN,
16820054 1216 mv643xx_eth_stats[i].stat_string,
e5371493 1217 ETH_GSTRING_LEN);
c9df406f 1218 }
c9df406f
LB		 1219 }
1220}
1da177e4 1221
fc32b0e2
LB		 1222static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1223 struct ethtool_stats *stats,
1224 uint64_t *data)
c9df406f 1225{
fc32b0e2 1226 struct mv643xx_eth_private *mp = dev->priv;
c9df406f 1227 int i;
1da177e4 1228
fc32b0e2 1229 mib_counters_update(mp);
1da177e4 1230
16820054
LB		 1231 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1232 const struct mv643xx_eth_stats *stat;
1233 void *p;
1234
1235 stat = mv643xx_eth_stats + i;
1236
1237 if (stat->netdev_off >= 0)
1238 p = ((void *)mp->dev) + stat->netdev_off;
1239 else
1240 p = ((void *)mp) + stat->mp_off;
1241
1242 data[i] = (stat->sizeof_stat == 8) ?
1243 *(uint64_t *)p : *(uint32_t *)p;
1da177e4 1244 }
c9df406f 1245}
1da177e4 1246
fc32b0e2 1247static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
c9df406f 1248{
fc32b0e2 1249 if (sset == ETH_SS_STATS)
16820054 1250 return ARRAY_SIZE(mv643xx_eth_stats);
fc32b0e2
LB		 1251
1252 return -EOPNOTSUPP;
c9df406f 1253}
1da177e4 1254
e5371493 1255static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
fc32b0e2
LB		 1256 .get_settings = mv643xx_eth_get_settings,
1257 .set_settings = mv643xx_eth_set_settings,
1258 .get_drvinfo = mv643xx_eth_get_drvinfo,
1259 .nway_reset = mv643xx_eth_nway_reset,
1260 .get_link = mv643xx_eth_get_link,
c9df406f 1261 .set_sg = ethtool_op_set_sg,
fc32b0e2
LB		 1262 .get_strings = mv643xx_eth_get_strings,
1263 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
e5371493 1264 .get_sset_count = mv643xx_eth_get_sset_count,
c9df406f 1265};
1da177e4 1266
bedfe324
LB		 1267static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless = {
1268 .get_settings = mv643xx_eth_get_settings_phyless,
1269 .set_settings = mv643xx_eth_set_settings_phyless,
1270 .get_drvinfo = mv643xx_eth_get_drvinfo,
1271 .nway_reset = mv643xx_eth_nway_reset_phyless,
1272 .get_link = mv643xx_eth_get_link_phyless,
1273 .set_sg = ethtool_op_set_sg,
1274 .get_strings = mv643xx_eth_get_strings,
1275 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1276 .get_sset_count = mv643xx_eth_get_sset_count,
1277};
1278
bea3348e 1279
c9df406f 1280/* address handling *********************************************************/
5daffe94 1281static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
c9df406f 1282{
c9df406f
LB		 1283 unsigned int mac_h;
1284 unsigned int mac_l;
1da177e4 1285
fc32b0e2
LB		 1286 mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num));
1287 mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num));
1da177e4 1288
5daffe94
LB		 1289 addr[0] = (mac_h >> 24) & 0xff;
1290 addr[1] = (mac_h >> 16) & 0xff;
1291 addr[2] = (mac_h >> 8) & 0xff;
1292 addr[3] = mac_h & 0xff;
1293 addr[4] = (mac_l >> 8) & 0xff;
1294 addr[5] = mac_l & 0xff;
c9df406f 1295}
1da177e4 1296
e5371493 1297static void init_mac_tables(struct mv643xx_eth_private *mp)
c9df406f 1298{
fc32b0e2 1299 int i;
1da177e4 1300
fc32b0e2
LB		 1301 for (i = 0; i < 0x100; i += 4) {
1302 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1303 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
c9df406f 1304 }
fc32b0e2
LB		 1305
1306 for (i = 0; i < 0x10; i += 4)
1307 wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
c9df406f 1308}
d0412d96 1309
e5371493 1310static void set_filter_table_entry(struct mv643xx_eth_private *mp,
fc32b0e2 1311 int table, unsigned char entry)
c9df406f
LB		 1312{
1313 unsigned int table_reg;
ab4384a6 1314
c9df406f 1315 /* Set "accepts frame bit" at specified table entry */
fc32b0e2
LB		 1316 table_reg = rdl(mp, table + (entry & 0xfc));
1317 table_reg |= 0x01 << (8 * (entry & 3));
1318 wrl(mp, table + (entry & 0xfc), table_reg);
1da177e4
LT		 1319}
1320
5daffe94 1321static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1da177e4 1322{
c9df406f
LB		 1323 unsigned int mac_h;
1324 unsigned int mac_l;
1325 int table;
1da177e4 1326
fc32b0e2
LB		 1327 mac_l = (addr[4] << 8) | addr[5];
1328 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
ff561eef 1329
fc32b0e2
LB		 1330 wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l);
1331 wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h);
1da177e4 1332
fc32b0e2 1333 table = UNICAST_TABLE(mp->port_num);
5daffe94 1334 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1da177e4
LT		 1335}
1336
fc32b0e2 1337static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1da177e4 1338{
e5371493 1339 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1340
fc32b0e2
LB		 1341 /* +2 is for the offset of the HW addr type */
1342 memcpy(dev->dev_addr, addr + 2, 6);
1343
cc9754b3
LB		 1344 init_mac_tables(mp);
1345 uc_addr_set(mp, dev->dev_addr);
1da177e4
LT		 1346
1347 return 0;
1348}
1349
69876569
LB		 1350static int addr_crc(unsigned char *addr)
1351{
1352 int crc = 0;
1353 int i;
1354
1355 for (i = 0; i < 6; i++) {
1356 int j;
1357
1358 crc = (crc ^ addr[i]) << 8;
1359 for (j = 7; j >= 0; j--) {
1360 if (crc & (0x100 << j))
1361 crc ^= 0x107 << j;
1362 }
1363 }
1364
1365 return crc;
1366}
1367
fc32b0e2 1368static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1da177e4 1369{
fc32b0e2
LB		 1370 struct mv643xx_eth_private *mp = netdev_priv(dev);
1371 u32 port_config;
1372 struct dev_addr_list *addr;
1373 int i;
c8aaea25 1374
fc32b0e2
LB		 1375 port_config = rdl(mp, PORT_CONFIG(mp->port_num));
1376 if (dev->flags & IFF_PROMISC)
1377 port_config |= UNICAST_PROMISCUOUS_MODE;
1378 else
1379 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1380 wrl(mp, PORT_CONFIG(mp->port_num), port_config);
1da177e4 1381
fc32b0e2
LB		 1382 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1383 int port_num = mp->port_num;
1384 u32 accept = 0x01010101;
c8aaea25 1385
fc32b0e2
LB		 1386 for (i = 0; i < 0x100; i += 4) {
1387 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1388 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
c9df406f
LB		 1389 }
1390 return;
1391 }
c8aaea25 1392
fc32b0e2
LB		 1393 for (i = 0; i < 0x100; i += 4) {
1394 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1395 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1da177e4
LT		 1396 }
1397
fc32b0e2
LB		 1398 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1399 u8 *a = addr->da_addr;
1400 int table;
324ff2c1 1401
fc32b0e2
LB		 1402 if (addr->da_addrlen != 6)
1403 continue;
1da177e4 1404
fc32b0e2
LB		 1405 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1406 table = SPECIAL_MCAST_TABLE(mp->port_num);
1407 set_filter_table_entry(mp, table, a[5]);
1408 } else {
1409 int crc = addr_crc(a);
1da177e4 1410
fc32b0e2
LB		 1411 table = OTHER_MCAST_TABLE(mp->port_num);
1412 set_filter_table_entry(mp, table, crc);
1413 }
1414 }
c9df406f 1415}
c8aaea25 1416
c8aaea25 1417
c9df406f 1418/* rx/tx queue initialisation ***********************************************/
64da80a2 1419static int rxq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1420{
64da80a2 1421 struct rx_queue *rxq = mp->rxq + index;
8a578111
LB		 1422 struct rx_desc *rx_desc;
1423 int size;
c9df406f
LB		 1424 int i;
1425
64da80a2
LB		 1426 rxq->index = index;
1427
8a578111
LB		 1428 rxq->rx_ring_size = mp->default_rx_ring_size;
1429
1430 rxq->rx_desc_count = 0;
1431 rxq->rx_curr_desc = 0;
1432 rxq->rx_used_desc = 0;
1433
1434 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1435
64da80a2 1436 if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size) {
8a578111
LB		 1437 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1438 mp->rx_desc_sram_size);
1439 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1440 } else {
1441 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1442 &rxq->rx_desc_dma,
1443 GFP_KERNEL);
f7ea3337
PJ		 1444 }
1445
8a578111
LB		 1446 if (rxq->rx_desc_area == NULL) {
1447 dev_printk(KERN_ERR, &mp->dev->dev,
1448 "can't allocate rx ring (%d bytes)\n", size);
1449 goto out;
1450 }
1451 memset(rxq->rx_desc_area, 0, size);
1da177e4 1452
8a578111
LB		 1453 rxq->rx_desc_area_size = size;
1454 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1455 GFP_KERNEL);
1456 if (rxq->rx_skb == NULL) {
1457 dev_printk(KERN_ERR, &mp->dev->dev,
1458 "can't allocate rx skb ring\n");
1459 goto out_free;
1460 }
1461
1462 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1463 for (i = 0; i < rxq->rx_ring_size; i++) {
1464 int nexti = (i + 1) % rxq->rx_ring_size;
1465 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1466 nexti * sizeof(struct rx_desc);
1467 }
1468
1469 init_timer(&rxq->rx_oom);
1470 rxq->rx_oom.data = (unsigned long)rxq;
1471 rxq->rx_oom.function = rxq_refill_timer_wrapper;
1472
1473 return 0;
1474
1475
1476out_free:
64da80a2 1477 if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size)
8a578111
LB		 1478 iounmap(rxq->rx_desc_area);
1479 else
1480 dma_free_coherent(NULL, size,
1481 rxq->rx_desc_area,
1482 rxq->rx_desc_dma);
1483
1484out:
1485 return -ENOMEM;
c9df406f 1486}
c8aaea25 1487
8a578111 1488static void rxq_deinit(struct rx_queue *rxq)
c9df406f 1489{
8a578111
LB		 1490 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1491 int i;
1492
1493 rxq_disable(rxq);
c8aaea25 1494
8a578111 1495 del_timer_sync(&rxq->rx_oom);
c9df406f 1496
8a578111
LB		 1497 for (i = 0; i < rxq->rx_ring_size; i++) {
1498 if (rxq->rx_skb[i]) {
1499 dev_kfree_skb(rxq->rx_skb[i]);
1500 rxq->rx_desc_count--;
1da177e4 1501 }
c8aaea25 1502 }
1da177e4 1503
8a578111
LB		 1504 if (rxq->rx_desc_count) {
1505 dev_printk(KERN_ERR, &mp->dev->dev,
1506 "error freeing rx ring -- %d skbs stuck\n",
1507 rxq->rx_desc_count);
1508 }
1509
64da80a2
LB		 1510 if (rxq->index == mp->rxq_primary &&
1511 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
8a578111 1512 iounmap(rxq->rx_desc_area);
c9df406f 1513 else
8a578111
LB		 1514 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1515 rxq->rx_desc_area, rxq->rx_desc_dma);
1516
1517 kfree(rxq->rx_skb);
c9df406f 1518}
1da177e4 1519
3d6b35bc 1520static int txq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1521{
3d6b35bc 1522 struct tx_queue *txq = mp->txq + index;
13d64285
LB		 1523 struct tx_desc *tx_desc;
1524 int size;
c9df406f 1525 int i;
1da177e4 1526
3d6b35bc
LB		 1527 txq->index = index;
1528
13d64285
LB		 1529 txq->tx_ring_size = mp->default_tx_ring_size;
1530
1531 txq->tx_desc_count = 0;
1532 txq->tx_curr_desc = 0;
1533 txq->tx_used_desc = 0;
1534
1535 size = txq->tx_ring_size * sizeof(struct tx_desc);
1536
3d6b35bc 1537 if (index == mp->txq_primary && size <= mp->tx_desc_sram_size) {
13d64285
LB		 1538 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1539 mp->tx_desc_sram_size);
1540 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1541 } else {
1542 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1543 &txq->tx_desc_dma,
1544 GFP_KERNEL);
1545 }
1546
1547 if (txq->tx_desc_area == NULL) {
1548 dev_printk(KERN_ERR, &mp->dev->dev,
1549 "can't allocate tx ring (%d bytes)\n", size);
1550 goto out;
c9df406f 1551 }
13d64285
LB		 1552 memset(txq->tx_desc_area, 0, size);
1553
1554 txq->tx_desc_area_size = size;
1555 txq->tx_skb = kmalloc(txq->tx_ring_size * sizeof(*txq->tx_skb),
1556 GFP_KERNEL);
1557 if (txq->tx_skb == NULL) {
1558 dev_printk(KERN_ERR, &mp->dev->dev,
1559 "can't allocate tx skb ring\n");
1560 goto out_free;
1561 }
1562
1563 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1564 for (i = 0; i < txq->tx_ring_size; i++) {
6b368f68 1565 struct tx_desc *txd = tx_desc + i;
13d64285 1566 int nexti = (i + 1) % txq->tx_ring_size;
6b368f68
LB		 1567
1568 txd->cmd_sts = 0;
1569 txd->next_desc_ptr = txq->tx_desc_dma +
13d64285
LB		 1570 nexti * sizeof(struct tx_desc);
1571 }
1572
1573 return 0;
1574
c9df406f 1575
13d64285 1576out_free:
3d6b35bc 1577 if (index == mp->txq_primary && size <= mp->tx_desc_sram_size)
13d64285
LB		 1578 iounmap(txq->tx_desc_area);
1579 else
1580 dma_free_coherent(NULL, size,
1581 txq->tx_desc_area,
1582 txq->tx_desc_dma);
c9df406f 1583
13d64285
LB		 1584out:
1585 return -ENOMEM;
c8aaea25 1586}
1da177e4 1587
13d64285 1588static void txq_reclaim(struct tx_queue *txq, int force)
c8aaea25 1589{
13d64285 1590 struct mv643xx_eth_private *mp = txq_to_mp(txq);
c8aaea25 1591 unsigned long flags;
1da177e4 1592
13d64285
LB		 1593 spin_lock_irqsave(&mp->lock, flags);
1594 while (txq->tx_desc_count > 0) {
1595 int tx_index;
1596 struct tx_desc *desc;
1597 u32 cmd_sts;
1598 struct sk_buff *skb;
1599 dma_addr_t addr;
1600 int count;
4d64e718 1601
13d64285
LB		 1602 tx_index = txq->tx_used_desc;
1603 desc = &txq->tx_desc_area[tx_index];
c9df406f 1604 cmd_sts = desc->cmd_sts;
4d64e718 1605
6b368f68
LB		 1606 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
1607 if (!force)
1608 break;
1609 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
1610 }
1da177e4 1611
13d64285
LB		 1612 txq->tx_used_desc = (tx_index + 1) % txq->tx_ring_size;
1613 txq->tx_desc_count--;
1da177e4 1614
c9df406f
LB		 1615 addr = desc->buf_ptr;
1616 count = desc->byte_cnt;
13d64285
LB		 1617 skb = txq->tx_skb[tx_index];
1618 txq->tx_skb[tx_index] = NULL;
c8aaea25 1619
cc9754b3 1620 if (cmd_sts & ERROR_SUMMARY) {
13d64285
LB		 1621 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
1622 mp->dev->stats.tx_errors++;
c9df406f 1623 }
1da177e4 1624
13d64285
LB		 1625 /*
1626 * Drop mp->lock while we free the skb.
1627 */
c9df406f 1628 spin_unlock_irqrestore(&mp->lock, flags);
1da177e4 1629
cc9754b3 1630 if (cmd_sts & TX_FIRST_DESC)
c9df406f
LB		 1631 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
1632 else
1633 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
c2e5b352 1634
c9df406f
LB		 1635 if (skb)
1636 dev_kfree_skb_irq(skb);
63c9e549 1637
13d64285 1638 spin_lock_irqsave(&mp->lock, flags);
c9df406f 1639 }
13d64285 1640 spin_unlock_irqrestore(&mp->lock, flags);
c9df406f 1641}
1da177e4 1642
13d64285 1643static void txq_deinit(struct tx_queue *txq)
c9df406f 1644{
13d64285 1645 struct mv643xx_eth_private *mp = txq_to_mp(txq);
fa3959f4 1646
13d64285
LB		 1647 txq_disable(txq);
1648 txq_reclaim(txq, 1);
1da177e4 1649
13d64285 1650 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1da177e4 1651
3d6b35bc
LB		 1652 if (txq->index == mp->txq_primary &&
1653 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
13d64285 1654 iounmap(txq->tx_desc_area);
c9df406f 1655 else
13d64285
LB		 1656 dma_free_coherent(NULL, txq->tx_desc_area_size,
1657 txq->tx_desc_area, txq->tx_desc_dma);
1658
1659 kfree(txq->tx_skb);
c9df406f 1660}
1da177e4 1661
1da177e4 1662
c9df406f 1663/* netdev ops and related ***************************************************/
fc32b0e2 1664static void update_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
c9df406f 1665{
13d64285
LB		 1666 u32 pscr_o;
1667 u32 pscr_n;
1da177e4 1668
13d64285 1669 pscr_o = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
63c9e549 1670
c9df406f 1671 /* clear speed, duplex and rx buffer size fields */
13d64285
LB		 1672 pscr_n = pscr_o & ~(SET_MII_SPEED_TO_100 |
1673 SET_GMII_SPEED_TO_1000 |
1674 SET_FULL_DUPLEX_MODE |
1675 MAX_RX_PACKET_MASK);
1da177e4 1676
65193a91
LB		 1677 pscr_n |= MAX_RX_PACKET_9700BYTE;
1678
1679 if (speed == SPEED_1000)
1680 pscr_n |= SET_GMII_SPEED_TO_1000;
1681 else if (speed == SPEED_100)
1682 pscr_n |= SET_MII_SPEED_TO_100;
1da177e4 1683
fc32b0e2 1684 if (duplex == DUPLEX_FULL)
13d64285
LB		 1685 pscr_n |= SET_FULL_DUPLEX_MODE;
1686
1687 if (pscr_n != pscr_o) {
1688 if ((pscr_o & SERIAL_PORT_ENABLE) == 0)
1689 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
c9df406f 1690 else {
3d6b35bc
LB		 1691 int i;
1692
1693 for (i = 0; i < 8; i++)
1694 if (mp->txq_mask & (1 << i))
1695 txq_disable(mp->txq + i);
1696
13d64285
LB		 1697 pscr_o &= ~SERIAL_PORT_ENABLE;
1698 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_o);
1699 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
1700 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
3d6b35bc
LB		 1701
1702 for (i = 0; i < 8; i++)
1703 if (mp->txq_mask & (1 << i))
1704 txq_enable(mp->txq + i);
c9df406f
LB		 1705 }
1706 }
1707}
84dd619e 1708
fc32b0e2 1709static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
c9df406f
LB		 1710{
1711 struct net_device *dev = (struct net_device *)dev_id;
e5371493 1712 struct mv643xx_eth_private *mp = netdev_priv(dev);
fc32b0e2
LB		 1713 u32 int_cause;
1714 u32 int_cause_ext;
ce4e2e45 1715
226bb6b7
LB		 1716 int_cause = rdl(mp, INT_CAUSE(mp->port_num)) &
1717 (INT_TX_END | INT_RX | INT_EXT);
fc32b0e2
LB		 1718 if (int_cause == 0)
1719 return IRQ_NONE;
1720
1721 int_cause_ext = 0;
cc9754b3 1722 if (int_cause & INT_EXT) {
13d64285 1723 int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num))
073a345c 1724 & (INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
13d64285 1725 wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext);
c9df406f 1726 }
1da177e4 1727
fc32b0e2 1728 if (int_cause_ext & (INT_EXT_PHY | INT_EXT_LINK)) {
bedfe324 1729 if (mp->phy_addr == -1 || mii_link_ok(&mp->mii)) {
bedfe324
LB		 1730 if (mp->phy_addr != -1) {
1731 struct ethtool_cmd cmd;
1732
1733 mii_ethtool_gset(&mp->mii, &cmd);
1734 update_pscr(mp, cmd.speed, cmd.duplex);
1735 }
1736
c9df406f
LB		 1737 if (!netif_carrier_ok(dev)) {
1738 netif_carrier_on(dev);
6b368f68 1739 netif_wake_queue(dev);
c9df406f
LB		 1740 }
1741 } else if (netif_carrier_ok(dev)) {
6b368f68
LB		 1742 int i;
1743
c9df406f
LB		 1744 netif_stop_queue(dev);
1745 netif_carrier_off(dev);
6b368f68
LB		 1746
1747 for (i = 0; i < 8; i++) {
1748 struct tx_queue *txq = mp->txq + i;
1749
1750 if (mp->txq_mask & (1 << i)) {
1751 txq_reclaim(txq, 1);
1752 txq_reset_hw_ptr(txq);
1753 }
1754 }
c9df406f
LB		 1755 }
1756 }
1da177e4 1757
64da80a2
LB		 1758 /*
1759 * RxBuffer or RxError set for any of the 8 queues?
1760 */
e5371493 1761#ifdef MV643XX_ETH_NAPI
cc9754b3 1762 if (int_cause & INT_RX) {
13d64285 1763 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
13d64285 1764 rdl(mp, INT_MASK(mp->port_num));
1da177e4 1765
c9df406f 1766 netif_rx_schedule(dev, &mp->napi);
84dd619e 1767 }
c9df406f 1768#else
64da80a2
LB		 1769 if (int_cause & INT_RX) {
1770 int i;
1771
1772 for (i = 7; i >= 0; i--)
1773 if (mp->rxq_mask & (1 << i))
1774 rxq_process(mp->rxq + i, INT_MAX);
1775 }
c9df406f 1776#endif
fc32b0e2 1777
3d6b35bc
LB		 1778 /*
1779 * TxBuffer or TxError set for any of the 8 queues?
1780 */
13d64285 1781 if (int_cause_ext & INT_EXT_TX) {
3d6b35bc
LB		 1782 int i;
1783
1784 for (i = 0; i < 8; i++)
1785 if (mp->txq_mask & (1 << i))
1786 txq_reclaim(mp->txq + i, 0);
8fa89bf5
LB		 1787
1788 /*
1789 * Enough space again in the primary TX queue for a
1790 * full packet?
1791 */
6b368f68
LB		 1792 if (netif_carrier_ok(dev)) {
1793 spin_lock(&mp->lock);
1794 __txq_maybe_wake(mp->txq + mp->txq_primary);
1795 spin_unlock(&mp->lock);
1796 }
226bb6b7 1797 }
3d6b35bc 1798
226bb6b7
LB		 1799 /*
1800 * Any TxEnd interrupts?
1801 */
1802 if (int_cause & INT_TX_END) {
1803 int i;
1804
1805 wrl(mp, INT_CAUSE(mp->port_num), ~(int_cause & INT_TX_END));
8fa89bf5
LB		 1806
1807 spin_lock(&mp->lock);
226bb6b7
LB		 1808 for (i = 0; i < 8; i++) {
1809 struct tx_queue *txq = mp->txq + i;
8fa89bf5
LB		 1810 u32 hw_desc_ptr;
1811 u32 expected_ptr;
1812
1813 if ((int_cause & (INT_TX_END_0 << i)) == 0)
1814 continue;
1815
1816 hw_desc_ptr =
1817 rdl(mp, TXQ_CURRENT_DESC_PTR(mp->port_num, i));
1818 expected_ptr = (u32)txq->tx_desc_dma +
1819 txq->tx_curr_desc * sizeof(struct tx_desc);
1820
1821 if (hw_desc_ptr != expected_ptr)
226bb6b7
LB		 1822 txq_enable(txq);
1823 }
8fa89bf5 1824 spin_unlock(&mp->lock);
13d64285 1825 }
1da177e4 1826
c9df406f 1827 return IRQ_HANDLED;
1da177e4
LT		 1828}
1829
e5371493 1830static void phy_reset(struct mv643xx_eth_private *mp)
1da177e4 1831{
fc32b0e2 1832 unsigned int data;
1da177e4 1833
7f106c1d
LB		 1834 smi_reg_read(mp, mp->phy_addr, MII_BMCR, &data);
1835 data |= BMCR_RESET;
1836 smi_reg_write(mp, mp->phy_addr, MII_BMCR, data);
1da177e4 1837
c9df406f
LB		 1838 do {
1839 udelay(1);
7f106c1d
LB		 1840 smi_reg_read(mp, mp->phy_addr, MII_BMCR, &data);
1841 } while (data & BMCR_RESET);
1da177e4
LT		 1842}
1843
fc32b0e2 1844static void port_start(struct mv643xx_eth_private *mp)
1da177e4 1845{
d0412d96 1846 u32 pscr;
8a578111 1847 int i;
1da177e4 1848
8a578111
LB		 1849 /*
1850 * Configure basic link parameters.
1851 */
1852 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1853 pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS);
1854 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1855 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1856 DISABLE_AUTO_NEG_SPEED_GMII |
1857 DISABLE_AUTO_NEG_FOR_DUPLEX |
1858 DO_NOT_FORCE_LINK_FAIL |
1859 SERIAL_PORT_CONTROL_RESERVED;
1860 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1861 pscr |= SERIAL_PORT_ENABLE;
1862 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1da177e4 1863
8a578111
LB		 1864 wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1865
bedfe324
LB		 1866 /*
1867 * Perform PHY reset, if there is a PHY.
1868 */
1869 if (mp->phy_addr != -1) {
1870 struct ethtool_cmd cmd;
1871
1872 mv643xx_eth_get_settings(mp->dev, &cmd);
1873 phy_reset(mp);
1874 mv643xx_eth_set_settings(mp->dev, &cmd);
1875 }
1da177e4 1876
13d64285
LB		 1877 /*
1878 * Configure TX path and queues.
1879 */
89df5fdc 1880 tx_set_rate(mp, 1000000000, 16777216);
3d6b35bc
LB		 1881 for (i = 0; i < 8; i++) {
1882 struct tx_queue *txq = mp->txq + i;
13d64285 1883
3d6b35bc
LB		 1884 if ((mp->txq_mask & (1 << i)) == 0)
1885 continue;
1886
6b368f68 1887 txq_reset_hw_ptr(txq);
89df5fdc
LB		 1888 txq_set_rate(txq, 1000000000, 16777216);
1889 txq_set_fixed_prio_mode(txq);
13d64285
LB		 1890 }
1891
fc32b0e2
LB		 1892 /*
1893 * Add configured unicast address to address filter table.
1894 */
1895 uc_addr_set(mp, mp->dev->dev_addr);
1da177e4 1896
d9a073ea
LB		 1897 /*
1898 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
1899 * frames to RX queue #0.
1900 */
8a578111 1901 wrl(mp, PORT_CONFIG(mp->port_num), 0x00000000);
01999873 1902
376489a2
LB		 1903 /*
1904 * Treat BPDUs as normal multicasts, and disable partition mode.
1905 */
8a578111 1906 wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000);
01999873 1907
8a578111 1908 /*
64da80a2 1909 * Enable the receive queues.
8a578111 1910 */
64da80a2
LB		 1911 for (i = 0; i < 8; i++) {
1912 struct rx_queue *rxq = mp->rxq + i;
1913 int off = RXQ_CURRENT_DESC_PTR(mp->port_num, i);
8a578111 1914 u32 addr;
1da177e4 1915
64da80a2
LB		 1916 if ((mp->rxq_mask & (1 << i)) == 0)
1917 continue;
1918
8a578111
LB		 1919 addr = (u32)rxq->rx_desc_dma;
1920 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
1921 wrl(mp, off, addr);
1da177e4 1922
8a578111
LB		 1923 rxq_enable(rxq);
1924 }
1da177e4
LT		 1925}
1926
ffd86bbe 1927static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1da177e4 1928{
c9df406f 1929 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
773fc3ee 1930 u32 val;
1da177e4 1931
773fc3ee
LB		 1932 val = rdl(mp, SDMA_CONFIG(mp->port_num));
1933 if (mp->shared->extended_rx_coal_limit) {
1934 if (coal > 0xffff)
1935 coal = 0xffff;
1936 val &= ~0x023fff80;
1937 val |= (coal & 0x8000) << 10;
1938 val |= (coal & 0x7fff) << 7;
1939 } else {
1940 if (coal > 0x3fff)
1941 coal = 0x3fff;
1942 val &= ~0x003fff00;
1943 val |= (coal & 0x3fff) << 8;
1944 }
1945 wrl(mp, SDMA_CONFIG(mp->port_num), val);
1da177e4
LT		 1946}
1947
ffd86bbe 1948static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1da177e4 1949{
c9df406f 1950 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1da177e4 1951
fc32b0e2
LB		 1952 if (coal > 0x3fff)
1953 coal = 0x3fff;
1954 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4);
16e03018
DF		 1955}
1956
c9df406f 1957static int mv643xx_eth_open(struct net_device *dev)
16e03018 1958{
e5371493 1959 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 1960 int err;
64da80a2 1961 int i;
16e03018 1962
fc32b0e2
LB		 1963 wrl(mp, INT_CAUSE(mp->port_num), 0);
1964 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
1965 rdl(mp, INT_CAUSE_EXT(mp->port_num));
c9df406f 1966
fc32b0e2
LB		 1967 err = request_irq(dev->irq, mv643xx_eth_irq,
1968 IRQF_SHARED | IRQF_SAMPLE_RANDOM,
1969 dev->name, dev);
c9df406f 1970 if (err) {
fc32b0e2 1971 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
c9df406f 1972 return -EAGAIN;
16e03018
DF		 1973 }
1974
fc32b0e2 1975 init_mac_tables(mp);
16e03018 1976
64da80a2
LB		 1977 for (i = 0; i < 8; i++) {
1978 if ((mp->rxq_mask & (1 << i)) == 0)
1979 continue;
1980
1981 err = rxq_init(mp, i);
1982 if (err) {
1983 while (--i >= 0)
1984 if (mp->rxq_mask & (1 << i))
1985 rxq_deinit(mp->rxq + i);
1986 goto out;
1987 }
1988
1989 rxq_refill(mp->rxq + i);
1990 }
8a578111 1991
3d6b35bc
LB		 1992 for (i = 0; i < 8; i++) {
1993 if ((mp->txq_mask & (1 << i)) == 0)
1994 continue;
1995
1996 err = txq_init(mp, i);
1997 if (err) {
1998 while (--i >= 0)
1999 if (mp->txq_mask & (1 << i))
2000 txq_deinit(mp->txq + i);
2001 goto out_free;
2002 }
2003 }
16e03018 2004
e5371493 2005#ifdef MV643XX_ETH_NAPI
c9df406f
LB		 2006 napi_enable(&mp->napi);
2007#endif
16e03018 2008
fc32b0e2 2009 port_start(mp);
16e03018 2010
ffd86bbe
LB		 2011 set_rx_coal(mp, 0);
2012 set_tx_coal(mp, 0);
16e03018 2013
fc32b0e2
LB		 2014 wrl(mp, INT_MASK_EXT(mp->port_num),
2015 INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
16e03018 2016
226bb6b7 2017 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
16e03018 2018
c9df406f
LB		 2019 return 0;
2020
13d64285 2021
fc32b0e2 2022out_free:
64da80a2
LB		 2023 for (i = 0; i < 8; i++)
2024 if (mp->rxq_mask & (1 << i))
2025 rxq_deinit(mp->rxq + i);
fc32b0e2 2026out:
c9df406f
LB		 2027 free_irq(dev->irq, dev);
2028
2029 return err;
16e03018
DF		 2030}
2031
e5371493 2032static void port_reset(struct mv643xx_eth_private *mp)
1da177e4 2033{
fc32b0e2 2034 unsigned int data;
64da80a2 2035 int i;
1da177e4 2036
64da80a2
LB		 2037 for (i = 0; i < 8; i++) {
2038 if (mp->rxq_mask & (1 << i))
2039 rxq_disable(mp->rxq + i);
3d6b35bc
LB		 2040 if (mp->txq_mask & (1 << i))
2041 txq_disable(mp->txq + i);
64da80a2 2042 }
ae9ae064
LB		 2043
2044 while (1) {
2045 u32 ps = rdl(mp, PORT_STATUS(mp->port_num));
2046
2047 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2048 break;
13d64285 2049 udelay(10);
ae9ae064 2050 }
1da177e4 2051
c9df406f 2052 /* Reset the Enable bit in the Configuration Register */
fc32b0e2
LB		 2053 data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2054 data &= ~(SERIAL_PORT_ENABLE |
2055 DO_NOT_FORCE_LINK_FAIL |
2056 FORCE_LINK_PASS);
2057 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data);
1da177e4
LT		 2058}
2059
c9df406f 2060static int mv643xx_eth_stop(struct net_device *dev)
1da177e4 2061{
e5371493 2062 struct mv643xx_eth_private *mp = netdev_priv(dev);
64da80a2 2063 int i;
1da177e4 2064
fc32b0e2
LB		 2065 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2066 rdl(mp, INT_MASK(mp->port_num));
1da177e4 2067
e5371493 2068#ifdef MV643XX_ETH_NAPI
c9df406f
LB		 2069 napi_disable(&mp->napi);
2070#endif
2071 netif_carrier_off(dev);
2072 netif_stop_queue(dev);
1da177e4 2073
fc32b0e2
LB		 2074 free_irq(dev->irq, dev);
2075
cc9754b3 2076 port_reset(mp);
fc32b0e2 2077 mib_counters_update(mp);
1da177e4 2078
64da80a2
LB		 2079 for (i = 0; i < 8; i++) {
2080 if (mp->rxq_mask & (1 << i))
2081 rxq_deinit(mp->rxq + i);
3d6b35bc
LB		 2082 if (mp->txq_mask & (1 << i))
2083 txq_deinit(mp->txq + i);
64da80a2 2084 }
1da177e4 2085
c9df406f 2086 return 0;
1da177e4
LT		 2087}
2088
fc32b0e2 2089static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1da177e4 2090{
e5371493 2091 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2092
bedfe324
LB		 2093 if (mp->phy_addr != -1)
2094 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
2095
2096 return -EOPNOTSUPP;
1da177e4
LT		 2097}
2098
c9df406f 2099static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 2100{
89df5fdc
LB		 2101 struct mv643xx_eth_private *mp = netdev_priv(dev);
2102
fc32b0e2 2103 if (new_mtu < 64 || new_mtu > 9500)
c9df406f 2104 return -EINVAL;
1da177e4 2105
c9df406f 2106 dev->mtu = new_mtu;
89df5fdc
LB		 2107 tx_set_rate(mp, 1000000000, 16777216);
2108
c9df406f
LB		 2109 if (!netif_running(dev))
2110 return 0;
1da177e4 2111
c9df406f
LB		 2112 /*
2113 * Stop and then re-open the interface. This will allocate RX
2114 * skbs of the new MTU.
2115 * There is a possible danger that the open will not succeed,
fc32b0e2 2116 * due to memory being full.
c9df406f
LB		 2117 */
2118 mv643xx_eth_stop(dev);
2119 if (mv643xx_eth_open(dev)) {
fc32b0e2
LB		 2120 dev_printk(KERN_ERR, &dev->dev,
2121 "fatal error on re-opening device after "
2122 "MTU change\n");
c9df406f
LB		 2123 }
2124
2125 return 0;
1da177e4
LT		 2126}
2127
fc32b0e2 2128static void tx_timeout_task(struct work_struct *ugly)
1da177e4 2129{
fc32b0e2 2130 struct mv643xx_eth_private *mp;
1da177e4 2131
fc32b0e2
LB		 2132 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2133 if (netif_running(mp->dev)) {
2134 netif_stop_queue(mp->dev);
c9df406f 2135
fc32b0e2
LB		 2136 port_reset(mp);
2137 port_start(mp);
c9df406f 2138
3d6b35bc 2139 __txq_maybe_wake(mp->txq + mp->txq_primary);
fc32b0e2 2140 }
c9df406f
LB		 2141}
2142
c9df406f 2143static void mv643xx_eth_tx_timeout(struct net_device *dev)
1da177e4 2144{
e5371493 2145 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2146
fc32b0e2 2147 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
d0412d96 2148
c9df406f 2149 schedule_work(&mp->tx_timeout_task);
1da177e4
LT		 2150}
2151
c9df406f 2152#ifdef CONFIG_NET_POLL_CONTROLLER
fc32b0e2 2153static void mv643xx_eth_netpoll(struct net_device *dev)
9f8dd319 2154{
fc32b0e2 2155 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2156
fc32b0e2
LB		 2157 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2158 rdl(mp, INT_MASK(mp->port_num));
c9df406f 2159
fc32b0e2 2160 mv643xx_eth_irq(dev->irq, dev);
c9df406f 2161
f2ca60f2 2162 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
9f8dd319 2163}
c9df406f 2164#endif
9f8dd319 2165
fc32b0e2 2166static int mv643xx_eth_mdio_read(struct net_device *dev, int addr, int reg)
9f8dd319 2167{
e5371493 2168 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f
LB		 2169 int val;
2170
fc32b0e2
LB		 2171 smi_reg_read(mp, addr, reg, &val);
2172
c9df406f 2173 return val;
9f8dd319
DF		 2174}
2175
fc32b0e2 2176static void mv643xx_eth_mdio_write(struct net_device *dev, int addr, int reg, int val)
9f8dd319 2177{
e5371493 2178 struct mv643xx_eth_private *mp = netdev_priv(dev);
fc32b0e2 2179 smi_reg_write(mp, addr, reg, val);
c9df406f 2180}
9f8dd319 2181
9f8dd319 2182
c9df406f 2183/* platform glue ************************************************************/
e5371493
LB		 2184static void
2185mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2186 struct mbus_dram_target_info *dram)
c9df406f 2187{
cc9754b3 2188 void __iomem *base = msp->base;
c9df406f
LB		 2189 u32 win_enable;
2190 u32 win_protect;
2191 int i;
9f8dd319 2192
c9df406f
LB		 2193 for (i = 0; i < 6; i++) {
2194 writel(0, base + WINDOW_BASE(i));
2195 writel(0, base + WINDOW_SIZE(i));
2196 if (i < 4)
2197 writel(0, base + WINDOW_REMAP_HIGH(i));
9f8dd319
DF		 2198 }
2199
c9df406f
LB		 2200 win_enable = 0x3f;
2201 win_protect = 0;
2202
2203 for (i = 0; i < dram->num_cs; i++) {
2204 struct mbus_dram_window *cs = dram->cs + i;
2205
2206 writel((cs->base & 0xffff0000) |
2207 (cs->mbus_attr << 8) |
2208 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2209 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2210
2211 win_enable &= ~(1 << i);
2212 win_protect |= 3 << (2 * i);
2213 }
2214
2215 writel(win_enable, base + WINDOW_BAR_ENABLE);
2216 msp->win_protect = win_protect;
9f8dd319
DF		 2217}
2218
773fc3ee
LB		 2219static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2220{
2221 /*
2222 * Check whether we have a 14-bit coal limit field in bits
2223 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2224 * SDMA config register.
2225 */
2226 writel(0x02000000, msp->base + SDMA_CONFIG(0));
2227 if (readl(msp->base + SDMA_CONFIG(0)) & 0x02000000)
2228 msp->extended_rx_coal_limit = 1;
2229 else
2230 msp->extended_rx_coal_limit = 0;
1e881592
LB		 2231
2232 /*
2233 * Check whether the TX rate control registers are in the
2234 * old or the new place.
2235 */
2236 writel(1, msp->base + TX_BW_MTU_MOVED(0));
2237 if (readl(msp->base + TX_BW_MTU_MOVED(0)) & 1)
2238 msp->tx_bw_control_moved = 1;
2239 else
2240 msp->tx_bw_control_moved = 0;
773fc3ee
LB		 2241}
2242
c9df406f 2243static int mv643xx_eth_shared_probe(struct platform_device *pdev)
9f8dd319 2244{
e5371493 2245 static int mv643xx_eth_version_printed = 0;
c9df406f 2246 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
e5371493 2247 struct mv643xx_eth_shared_private *msp;
c9df406f
LB		 2248 struct resource *res;
2249 int ret;
9f8dd319 2250
e5371493 2251 if (!mv643xx_eth_version_printed++)
c9df406f 2252 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
9f8dd319 2253
c9df406f
LB		 2254 ret = -EINVAL;
2255 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2256 if (res == NULL)
2257 goto out;
9f8dd319 2258
c9df406f
LB		 2259 ret = -ENOMEM;
2260 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2261 if (msp == NULL)
2262 goto out;
2263 memset(msp, 0, sizeof(*msp));
2264
cc9754b3
LB		 2265 msp->base = ioremap(res->start, res->end - res->start + 1);
2266 if (msp->base == NULL)
c9df406f
LB		 2267 goto out_free;
2268
2269 spin_lock_init(&msp->phy_lock);
c9df406f
LB		 2270
2271 /*
2272 * (Re-)program MBUS remapping windows if we are asked to.
2273 */
2274 if (pd != NULL && pd->dram != NULL)
2275 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2276
fc32b0e2
LB		 2277 /*
2278 * Detect hardware parameters.
2279 */
2280 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
773fc3ee 2281 infer_hw_params(msp);
fc32b0e2
LB		 2282
2283 platform_set_drvdata(pdev, msp);
2284
c9df406f
LB		 2285 return 0;
2286
2287out_free:
2288 kfree(msp);
2289out:
2290 return ret;
2291}
2292
2293static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2294{
e5371493 2295 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
c9df406f 2296
cc9754b3 2297 iounmap(msp->base);
c9df406f
LB		 2298 kfree(msp);
2299
2300 return 0;
9f8dd319
DF		 2301}
2302
c9df406f 2303static struct platform_driver mv643xx_eth_shared_driver = {
fc32b0e2
LB		 2304 .probe = mv643xx_eth_shared_probe,
2305 .remove = mv643xx_eth_shared_remove,
c9df406f 2306 .driver = {
fc32b0e2 2307 .name = MV643XX_ETH_SHARED_NAME,
c9df406f
LB		 2308 .owner = THIS_MODULE,
2309 },
2310};
2311
e5371493 2312static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
1da177e4 2313{
c9df406f 2314 int addr_shift = 5 * mp->port_num;
fc32b0e2 2315 u32 data;
1da177e4 2316
fc32b0e2
LB		 2317 data = rdl(mp, PHY_ADDR);
2318 data &= ~(0x1f << addr_shift);
2319 data |= (phy_addr & 0x1f) << addr_shift;
2320 wrl(mp, PHY_ADDR, data);
1da177e4
LT		 2321}
2322
e5371493 2323static int phy_addr_get(struct mv643xx_eth_private *mp)
1da177e4 2324{
fc32b0e2
LB		 2325 unsigned int data;
2326
2327 data = rdl(mp, PHY_ADDR);
2328
2329 return (data >> (5 * mp->port_num)) & 0x1f;
2330}
2331
2332static void set_params(struct mv643xx_eth_private *mp,
2333 struct mv643xx_eth_platform_data *pd)
2334{
2335 struct net_device *dev = mp->dev;
2336
2337 if (is_valid_ether_addr(pd->mac_addr))
2338 memcpy(dev->dev_addr, pd->mac_addr, 6);
2339 else
2340 uc_addr_get(mp, dev->dev_addr);
2341
2342 if (pd->phy_addr == -1) {
2343 mp->shared_smi = NULL;
2344 mp->phy_addr = -1;
2345 } else {
2346 mp->shared_smi = mp->shared;
2347 if (pd->shared_smi != NULL)
2348 mp->shared_smi = platform_get_drvdata(pd->shared_smi);
2349
2350 if (pd->force_phy_addr || pd->phy_addr) {
2351 mp->phy_addr = pd->phy_addr & 0x3f;
2352 phy_addr_set(mp, mp->phy_addr);
2353 } else {
2354 mp->phy_addr = phy_addr_get(mp);
2355 }
2356 }
1da177e4 2357
fc32b0e2
LB		 2358 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2359 if (pd->rx_queue_size)
2360 mp->default_rx_ring_size = pd->rx_queue_size;
2361 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2362 mp->rx_desc_sram_size = pd->rx_sram_size;
1da177e4 2363
64da80a2
LB		 2364 if (pd->rx_queue_mask)
2365 mp->rxq_mask = pd->rx_queue_mask;
2366 else
2367 mp->rxq_mask = 0x01;
2368 mp->rxq_primary = fls(mp->rxq_mask) - 1;
2369
fc32b0e2
LB		 2370 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2371 if (pd->tx_queue_size)
2372 mp->default_tx_ring_size = pd->tx_queue_size;
2373 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2374 mp->tx_desc_sram_size = pd->tx_sram_size;
3d6b35bc
LB		 2375
2376 if (pd->tx_queue_mask)
2377 mp->txq_mask = pd->tx_queue_mask;
2378 else
2379 mp->txq_mask = 0x01;
2380 mp->txq_primary = fls(mp->txq_mask) - 1;
1da177e4
LT		 2381}
2382
e5371493 2383static int phy_detect(struct mv643xx_eth_private *mp)
1da177e4 2384{
fc32b0e2
LB		 2385 unsigned int data;
2386 unsigned int data2;
2387
7f106c1d
LB		 2388 smi_reg_read(mp, mp->phy_addr, MII_BMCR, &data);
2389 smi_reg_write(mp, mp->phy_addr, MII_BMCR, data ^ BMCR_ANENABLE);
1da177e4 2390
7f106c1d
LB		 2391 smi_reg_read(mp, mp->phy_addr, MII_BMCR, &data2);
2392 if (((data ^ data2) & BMCR_ANENABLE) == 0)
fc32b0e2 2393 return -ENODEV;
1da177e4 2394
7f106c1d 2395 smi_reg_write(mp, mp->phy_addr, MII_BMCR, data);
1da177e4 2396
c9df406f 2397 return 0;
1da177e4
LT		 2398}
2399
fc32b0e2
LB		 2400static int phy_init(struct mv643xx_eth_private *mp,
2401 struct mv643xx_eth_platform_data *pd)
c28a4f89 2402{
fc32b0e2
LB		 2403 struct ethtool_cmd cmd;
2404 int err;
c28a4f89 2405
fc32b0e2
LB		 2406 err = phy_detect(mp);
2407 if (err) {
2408 dev_printk(KERN_INFO, &mp->dev->dev,
2409 "no PHY detected at addr %d\n", mp->phy_addr);
2410 return err;
2411 }
2412 phy_reset(mp);
2413
2414 mp->mii.phy_id = mp->phy_addr;
2415 mp->mii.phy_id_mask = 0x3f;
2416 mp->mii.reg_num_mask = 0x1f;
2417 mp->mii.dev = mp->dev;
2418 mp->mii.mdio_read = mv643xx_eth_mdio_read;
2419 mp->mii.mdio_write = mv643xx_eth_mdio_write;
c28a4f89 2420
fc32b0e2 2421 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
c9df406f 2422
fc32b0e2
LB		 2423 memset(&cmd, 0, sizeof(cmd));
2424
2425 cmd.port = PORT_MII;
2426 cmd.transceiver = XCVR_INTERNAL;
2427 cmd.phy_address = mp->phy_addr;
2428 if (pd->speed == 0) {
2429 cmd.autoneg = AUTONEG_ENABLE;
2430 cmd.speed = SPEED_100;
2431 cmd.advertising = ADVERTISED_10baseT_Half |
2432 ADVERTISED_10baseT_Full |
2433 ADVERTISED_100baseT_Half |
2434 ADVERTISED_100baseT_Full;
c9df406f 2435 if (mp->mii.supports_gmii)
fc32b0e2 2436 cmd.advertising |= ADVERTISED_1000baseT_Full;
c9df406f 2437 } else {
fc32b0e2
LB		 2438 cmd.autoneg = AUTONEG_DISABLE;
2439 cmd.speed = pd->speed;
2440 cmd.duplex = pd->duplex;
c9df406f 2441 }
fc32b0e2
LB		 2442
2443 update_pscr(mp, cmd.speed, cmd.duplex);
2444 mv643xx_eth_set_settings(mp->dev, &cmd);
2445
2446 return 0;
c28a4f89
JC		 2447}
2448
c9df406f 2449static int mv643xx_eth_probe(struct platform_device *pdev)
1da177e4 2450{
c9df406f 2451 struct mv643xx_eth_platform_data *pd;
e5371493 2452 struct mv643xx_eth_private *mp;
c9df406f 2453 struct net_device *dev;
c9df406f 2454 struct resource *res;
c9df406f 2455 DECLARE_MAC_BUF(mac);
fc32b0e2 2456 int err;
1da177e4 2457
c9df406f
LB		 2458 pd = pdev->dev.platform_data;
2459 if (pd == NULL) {
fc32b0e2
LB		 2460 dev_printk(KERN_ERR, &pdev->dev,
2461 "no mv643xx_eth_platform_data\n");
c9df406f
LB		 2462 return -ENODEV;
2463 }
1da177e4 2464
c9df406f 2465 if (pd->shared == NULL) {
fc32b0e2
LB		 2466 dev_printk(KERN_ERR, &pdev->dev,
2467 "no mv643xx_eth_platform_data->shared\n");
c9df406f
LB		 2468 return -ENODEV;
2469 }
8f518703 2470
e5371493 2471 dev = alloc_etherdev(sizeof(struct mv643xx_eth_private));
c9df406f
LB		 2472 if (!dev)
2473 return -ENOMEM;
1da177e4 2474
c9df406f 2475 mp = netdev_priv(dev);
fc32b0e2
LB		 2476 platform_set_drvdata(pdev, mp);
2477
2478 mp->shared = platform_get_drvdata(pd->shared);
2479 mp->port_num = pd->port_number;
2480
c9df406f 2481 mp->dev = dev;
e5371493
LB		 2482#ifdef MV643XX_ETH_NAPI
2483 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 64);
c9df406f 2484#endif
1da177e4 2485
fc32b0e2
LB		 2486 set_params(mp, pd);
2487
2488 spin_lock_init(&mp->lock);
2489
2490 mib_counters_clear(mp);
2491 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2492
bedfe324
LB		 2493 if (mp->phy_addr != -1) {
2494 err = phy_init(mp, pd);
2495 if (err)
2496 goto out;
2497
2498 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2499 } else {
2500 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless);
2501 }
fc32b0e2
LB		 2502
2503
c9df406f
LB		 2504 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2505 BUG_ON(!res);
2506 dev->irq = res->start;
1da177e4 2507
fc32b0e2 2508 dev->hard_start_xmit = mv643xx_eth_xmit;
c9df406f
LB		 2509 dev->open = mv643xx_eth_open;
2510 dev->stop = mv643xx_eth_stop;
c9df406f 2511 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
fc32b0e2
LB		 2512 dev->set_mac_address = mv643xx_eth_set_mac_address;
2513 dev->do_ioctl = mv643xx_eth_ioctl;
2514 dev->change_mtu = mv643xx_eth_change_mtu;
c9df406f 2515 dev->tx_timeout = mv643xx_eth_tx_timeout;
c9df406f 2516#ifdef CONFIG_NET_POLL_CONTROLLER
e5371493 2517 dev->poll_controller = mv643xx_eth_netpoll;
c9df406f 2518#endif
c9df406f
LB		 2519 dev->watchdog_timeo = 2 * HZ;
2520 dev->base_addr = 0;
1da177e4 2521
e5371493 2522#ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
b4de9051 2523 /*
c9df406f
LB		 2524 * Zero copy can only work if we use Discovery II memory. Else, we will
2525 * have to map the buffers to ISA memory which is only 16 MB
b4de9051 2526 */
c9df406f 2527 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
c9df406f 2528#endif
1da177e4 2529
fc32b0e2 2530 SET_NETDEV_DEV(dev, &pdev->dev);
8f518703 2531
c9df406f 2532 if (mp->shared->win_protect)
fc32b0e2 2533 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
1da177e4 2534
c9df406f
LB		 2535 err = register_netdev(dev);
2536 if (err)
2537 goto out;
1da177e4 2538
fc32b0e2
LB		 2539 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %s\n",
2540 mp->port_num, print_mac(mac, dev->dev_addr));
1da177e4 2541
c9df406f 2542 if (dev->features & NETIF_F_SG)
fc32b0e2 2543 dev_printk(KERN_NOTICE, &dev->dev, "scatter/gather enabled\n");
1da177e4 2544
c9df406f 2545 if (dev->features & NETIF_F_IP_CSUM)
fc32b0e2 2546 dev_printk(KERN_NOTICE, &dev->dev, "tx checksum offload\n");
1da177e4 2547
e5371493 2548#ifdef MV643XX_ETH_NAPI
fc32b0e2 2549 dev_printk(KERN_NOTICE, &dev->dev, "napi enabled\n");
c9df406f 2550#endif
1da177e4 2551
13d64285 2552 if (mp->tx_desc_sram_size > 0)
fc32b0e2 2553 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
1da177e4 2554
c9df406f 2555 return 0;
1da177e4 2556
c9df406f
LB		 2557out:
2558 free_netdev(dev);
1da177e4 2559
c9df406f 2560 return err;
1da177e4
LT		 2561}
2562
c9df406f 2563static int mv643xx_eth_remove(struct platform_device *pdev)
1da177e4 2564{
fc32b0e2 2565 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
1da177e4 2566
fc32b0e2 2567 unregister_netdev(mp->dev);
c9df406f 2568 flush_scheduled_work();
fc32b0e2 2569 free_netdev(mp->dev);
c9df406f 2570
c9df406f 2571 platform_set_drvdata(pdev, NULL);
fc32b0e2 2572
c9df406f 2573 return 0;
1da177e4
LT		 2574}
2575
c9df406f 2576static void mv643xx_eth_shutdown(struct platform_device *pdev)
d0412d96 2577{
fc32b0e2 2578 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
d0412d96 2579
c9df406f 2580 /* Mask all interrupts on ethernet port */
fc32b0e2
LB		 2581 wrl(mp, INT_MASK(mp->port_num), 0);
2582 rdl(mp, INT_MASK(mp->port_num));
c9df406f 2583
fc32b0e2
LB		 2584 if (netif_running(mp->dev))
2585 port_reset(mp);
d0412d96
JC		 2586}
2587
c9df406f 2588static struct platform_driver mv643xx_eth_driver = {
fc32b0e2
LB		 2589 .probe = mv643xx_eth_probe,
2590 .remove = mv643xx_eth_remove,
2591 .shutdown = mv643xx_eth_shutdown,
c9df406f 2592 .driver = {
fc32b0e2 2593 .name = MV643XX_ETH_NAME,
c9df406f
LB		 2594 .owner = THIS_MODULE,
2595 },
2596};
2597
e5371493 2598static int __init mv643xx_eth_init_module(void)
d0412d96 2599{
c9df406f 2600 int rc;
d0412d96 2601
c9df406f
LB		 2602 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2603 if (!rc) {
2604 rc = platform_driver_register(&mv643xx_eth_driver);
2605 if (rc)
2606 platform_driver_unregister(&mv643xx_eth_shared_driver);
2607 }
fc32b0e2 2608
c9df406f 2609 return rc;
d0412d96 2610}
fc32b0e2 2611module_init(mv643xx_eth_init_module);
d0412d96 2612
e5371493 2613static void __exit mv643xx_eth_cleanup_module(void)
d0412d96 2614{
c9df406f
LB		 2615 platform_driver_unregister(&mv643xx_eth_driver);
2616 platform_driver_unregister(&mv643xx_eth_shared_driver);
d0412d96 2617}
e5371493 2618module_exit(mv643xx_eth_cleanup_module);
1da177e4 2619
45675bc6
LB		 2620MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2621 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
c9df406f 2622MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
fc32b0e2 2623MODULE_LICENSE("GPL");
c9df406f 2624MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
fc32b0e2 2625MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
Linux 6.x block layer and io_uring tree(s)