Commit | Line | Data |
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1da177e4 | 1 | /* |
9c1bbdfe | 2 | * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports |
1da177e4 LT |
3 | * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com> |
4 | * | |
5 | * Based on the 64360 driver from: | |
4547fa61 LB |
6 | * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il> |
7 | * Rabeeh Khoury <rabeeh@marvell.com> | |
1da177e4 LT |
8 | * |
9 | * Copyright (C) 2003 PMC-Sierra, Inc., | |
3bb8a18a | 10 | * written by Manish Lachwani |
1da177e4 LT |
11 | * |
12 | * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org> | |
13 | * | |
c8aaea25 | 14 | * Copyright (C) 2004-2006 MontaVista Software, Inc. |
1da177e4 LT |
15 | * Dale Farnsworth <dale@farnsworth.org> |
16 | * | |
17 | * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com> | |
18 | * <sjhill@realitydiluted.com> | |
19 | * | |
4547fa61 LB |
20 | * Copyright (C) 2007-2008 Marvell Semiconductor |
21 | * Lennert Buytenhek <buytenh@marvell.com> | |
22 | * | |
1da177e4 LT |
23 | * This program is free software; you can redistribute it and/or |
24 | * modify it under the terms of the GNU General Public License | |
25 | * as published by the Free Software Foundation; either version 2 | |
26 | * of the License, or (at your option) any later version. | |
27 | * | |
28 | * This program is distributed in the hope that it will be useful, | |
29 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
30 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
31 | * GNU General Public License for more details. | |
32 | * | |
33 | * You should have received a copy of the GNU General Public License | |
34 | * along with this program; if not, write to the Free Software | |
35 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
36 | */ | |
a779d38c | 37 | |
1da177e4 LT |
38 | #include <linux/init.h> |
39 | #include <linux/dma-mapping.h> | |
b6298c22 | 40 | #include <linux/in.h> |
1da177e4 LT |
41 | #include <linux/tcp.h> |
42 | #include <linux/udp.h> | |
43 | #include <linux/etherdevice.h> | |
1da177e4 LT |
44 | #include <linux/delay.h> |
45 | #include <linux/ethtool.h> | |
d052d1be | 46 | #include <linux/platform_device.h> |
fbd6a754 LB |
47 | #include <linux/module.h> |
48 | #include <linux/kernel.h> | |
49 | #include <linux/spinlock.h> | |
50 | #include <linux/workqueue.h> | |
51 | #include <linux/mii.h> | |
fbd6a754 | 52 | #include <linux/mv643xx_eth.h> |
1da177e4 LT |
53 | #include <asm/io.h> |
54 | #include <asm/types.h> | |
1da177e4 | 55 | #include <asm/system.h> |
fbd6a754 | 56 | |
c9df406f LB |
57 | static char mv643xx_driver_name[] = "mv643xx_eth"; |
58 | static char mv643xx_driver_version[] = "1.0"; | |
59 | ||
fbd6a754 LB |
60 | #define MV643XX_CHECKSUM_OFFLOAD_TX |
61 | #define MV643XX_NAPI | |
62 | #define MV643XX_TX_FAST_REFILL | |
63 | #undef MV643XX_COAL | |
64 | ||
fbd6a754 LB |
65 | #define MV643XX_TX_COAL 100 |
66 | #ifdef MV643XX_COAL | |
67 | #define MV643XX_RX_COAL 100 | |
68 | #endif | |
69 | ||
70 | #ifdef MV643XX_CHECKSUM_OFFLOAD_TX | |
71 | #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1) | |
72 | #else | |
73 | #define MAX_DESCS_PER_SKB 1 | |
74 | #endif | |
75 | ||
76 | #define ETH_VLAN_HLEN 4 | |
77 | #define ETH_FCS_LEN 4 | |
78 | #define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */ | |
79 | #define ETH_WRAPPER_LEN (ETH_HW_IP_ALIGN + ETH_HLEN + \ | |
80 | ETH_VLAN_HLEN + ETH_FCS_LEN) | |
81 | #define ETH_RX_SKB_SIZE (dev->mtu + ETH_WRAPPER_LEN + \ | |
82 | dma_get_cache_alignment()) | |
83 | ||
84 | /* | |
85 | * Registers shared between all ports. | |
86 | */ | |
3cb4667c LB |
87 | #define PHY_ADDR 0x0000 |
88 | #define SMI_REG 0x0004 | |
89 | #define WINDOW_BASE(w) (0x0200 + ((w) << 3)) | |
90 | #define WINDOW_SIZE(w) (0x0204 + ((w) << 3)) | |
91 | #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2)) | |
92 | #define WINDOW_BAR_ENABLE 0x0290 | |
93 | #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4)) | |
fbd6a754 LB |
94 | |
95 | /* | |
96 | * Per-port registers. | |
97 | */ | |
3cb4667c | 98 | #define PORT_CONFIG(p) (0x0400 + ((p) << 10)) |
d9a073ea | 99 | #define UNICAST_PROMISCUOUS_MODE 0x00000001 |
3cb4667c LB |
100 | #define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10)) |
101 | #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10)) | |
102 | #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10)) | |
103 | #define SDMA_CONFIG(p) (0x041c + ((p) << 10)) | |
104 | #define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10)) | |
105 | #define PORT_STATUS(p) (0x0444 + ((p) << 10)) | |
a2a41689 | 106 | #define TX_FIFO_EMPTY 0x00000400 |
3cb4667c LB |
107 | #define TXQ_COMMAND(p) (0x0448 + ((p) << 10)) |
108 | #define TX_BW_MTU(p) (0x0458 + ((p) << 10)) | |
109 | #define INT_CAUSE(p) (0x0460 + ((p) << 10)) | |
073a345c LB |
110 | #define INT_RX 0x00000804 |
111 | #define INT_EXT 0x00000002 | |
3cb4667c | 112 | #define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10)) |
073a345c LB |
113 | #define INT_EXT_LINK 0x00100000 |
114 | #define INT_EXT_PHY 0x00010000 | |
115 | #define INT_EXT_TX_ERROR_0 0x00000100 | |
116 | #define INT_EXT_TX_0 0x00000001 | |
117 | #define INT_EXT_TX 0x00000101 | |
3cb4667c LB |
118 | #define INT_MASK(p) (0x0468 + ((p) << 10)) |
119 | #define INT_MASK_EXT(p) (0x046c + ((p) << 10)) | |
120 | #define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10)) | |
121 | #define RXQ_CURRENT_DESC_PTR(p) (0x060c + ((p) << 10)) | |
122 | #define RXQ_COMMAND(p) (0x0680 + ((p) << 10)) | |
123 | #define TXQ_CURRENT_DESC_PTR(p) (0x06c0 + ((p) << 10)) | |
124 | #define MIB_COUNTERS(p) (0x1000 + ((p) << 7)) | |
125 | #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10)) | |
126 | #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10)) | |
127 | #define UNICAST_TABLE(p) (0x1600 + ((p) << 10)) | |
fbd6a754 | 128 | |
2679a550 LB |
129 | |
130 | /* | |
131 | * SDMA configuration register. | |
132 | */ | |
fbd6a754 | 133 | #define RX_BURST_SIZE_4_64BIT (2 << 1) |
fbd6a754 | 134 | #define BLM_RX_NO_SWAP (1 << 4) |
fbd6a754 | 135 | #define BLM_TX_NO_SWAP (1 << 5) |
fbd6a754 | 136 | #define TX_BURST_SIZE_4_64BIT (2 << 22) |
fbd6a754 LB |
137 | |
138 | #if defined(__BIG_ENDIAN) | |
139 | #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ | |
140 | RX_BURST_SIZE_4_64BIT | \ | |
fbd6a754 LB |
141 | TX_BURST_SIZE_4_64BIT |
142 | #elif defined(__LITTLE_ENDIAN) | |
143 | #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ | |
144 | RX_BURST_SIZE_4_64BIT | \ | |
145 | BLM_RX_NO_SWAP | \ | |
146 | BLM_TX_NO_SWAP | \ | |
fbd6a754 LB |
147 | TX_BURST_SIZE_4_64BIT |
148 | #else | |
149 | #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined | |
150 | #endif | |
151 | ||
2beff77b LB |
152 | |
153 | /* | |
154 | * Port serial control register. | |
155 | */ | |
156 | #define SET_MII_SPEED_TO_100 (1 << 24) | |
157 | #define SET_GMII_SPEED_TO_1000 (1 << 23) | |
158 | #define SET_FULL_DUPLEX_MODE (1 << 21) | |
fbd6a754 | 159 | #define MAX_RX_PACKET_1522BYTE (1 << 17) |
fbd6a754 LB |
160 | #define MAX_RX_PACKET_9700BYTE (5 << 17) |
161 | #define MAX_RX_PACKET_MASK (7 << 17) | |
2beff77b LB |
162 | #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13) |
163 | #define DO_NOT_FORCE_LINK_FAIL (1 << 10) | |
164 | #define SERIAL_PORT_CONTROL_RESERVED (1 << 9) | |
165 | #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3) | |
166 | #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2) | |
167 | #define FORCE_LINK_PASS (1 << 1) | |
168 | #define SERIAL_PORT_ENABLE (1 << 0) | |
fbd6a754 | 169 | |
fbd6a754 LB |
170 | #define PORT_DEFAULT_TRANSMIT_QUEUE_SIZE 800 |
171 | #define PORT_DEFAULT_RECEIVE_QUEUE_SIZE 400 | |
172 | ||
fbd6a754 LB |
173 | /* SMI reg */ |
174 | #define ETH_SMI_BUSY 0x10000000 /* 0 - Write, 1 - Read */ | |
175 | #define ETH_SMI_READ_VALID 0x08000000 /* 0 - Write, 1 - Read */ | |
176 | #define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read */ | |
177 | #define ETH_SMI_OPCODE_READ 0x04000000 /* Operation is in progress */ | |
178 | ||
fbd6a754 LB |
179 | /* typedefs */ |
180 | ||
181 | typedef enum _eth_func_ret_status { | |
182 | ETH_OK, /* Returned as expected. */ | |
183 | ETH_ERROR, /* Fundamental error. */ | |
184 | ETH_RETRY, /* Could not process request. Try later.*/ | |
185 | ETH_END_OF_JOB, /* Ring has nothing to process. */ | |
186 | ETH_QUEUE_FULL, /* Ring resource error. */ | |
187 | ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */ | |
188 | } ETH_FUNC_RET_STATUS; | |
189 | ||
7ca72a3b LB |
190 | /* |
191 | * RX/TX descriptors. | |
fbd6a754 LB |
192 | */ |
193 | #if defined(__BIG_ENDIAN) | |
194 | struct eth_rx_desc { | |
195 | u16 byte_cnt; /* Descriptor buffer byte count */ | |
196 | u16 buf_size; /* Buffer size */ | |
197 | u32 cmd_sts; /* Descriptor command status */ | |
198 | u32 next_desc_ptr; /* Next descriptor pointer */ | |
199 | u32 buf_ptr; /* Descriptor buffer pointer */ | |
200 | }; | |
201 | ||
202 | struct eth_tx_desc { | |
203 | u16 byte_cnt; /* buffer byte count */ | |
204 | u16 l4i_chk; /* CPU provided TCP checksum */ | |
205 | u32 cmd_sts; /* Command/status field */ | |
206 | u32 next_desc_ptr; /* Pointer to next descriptor */ | |
207 | u32 buf_ptr; /* pointer to buffer for this descriptor*/ | |
208 | }; | |
209 | #elif defined(__LITTLE_ENDIAN) | |
210 | struct eth_rx_desc { | |
211 | u32 cmd_sts; /* Descriptor command status */ | |
212 | u16 buf_size; /* Buffer size */ | |
213 | u16 byte_cnt; /* Descriptor buffer byte count */ | |
214 | u32 buf_ptr; /* Descriptor buffer pointer */ | |
215 | u32 next_desc_ptr; /* Next descriptor pointer */ | |
216 | }; | |
217 | ||
218 | struct eth_tx_desc { | |
219 | u32 cmd_sts; /* Command/status field */ | |
220 | u16 l4i_chk; /* CPU provided TCP checksum */ | |
221 | u16 byte_cnt; /* buffer byte count */ | |
222 | u32 buf_ptr; /* pointer to buffer for this descriptor*/ | |
223 | u32 next_desc_ptr; /* Pointer to next descriptor */ | |
224 | }; | |
225 | #else | |
226 | #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined | |
227 | #endif | |
228 | ||
7ca72a3b LB |
229 | /* RX & TX descriptor command */ |
230 | #define ETH_BUFFER_OWNED_BY_DMA 0x80000000 | |
231 | ||
232 | /* RX & TX descriptor status */ | |
233 | #define ETH_ERROR_SUMMARY 0x00000001 | |
234 | ||
235 | /* RX descriptor status */ | |
236 | #define ETH_LAYER_4_CHECKSUM_OK 0x40000000 | |
237 | #define ETH_RX_ENABLE_INTERRUPT 0x20000000 | |
238 | #define ETH_RX_FIRST_DESC 0x08000000 | |
239 | #define ETH_RX_LAST_DESC 0x04000000 | |
240 | ||
241 | /* TX descriptor command */ | |
242 | #define ETH_TX_ENABLE_INTERRUPT 0x00800000 | |
243 | #define ETH_GEN_CRC 0x00400000 | |
244 | #define ETH_TX_FIRST_DESC 0x00200000 | |
245 | #define ETH_TX_LAST_DESC 0x00100000 | |
246 | #define ETH_ZERO_PADDING 0x00080000 | |
247 | #define ETH_GEN_IP_V4_CHECKSUM 0x00040000 | |
248 | #define ETH_GEN_TCP_UDP_CHECKSUM 0x00020000 | |
249 | #define ETH_UDP_FRAME 0x00010000 | |
250 | ||
251 | #define ETH_TX_IHL_SHIFT 11 | |
252 | ||
253 | ||
fbd6a754 LB |
254 | /* Unified struct for Rx and Tx operations. The user is not required to */ |
255 | /* be familier with neither Tx nor Rx descriptors. */ | |
256 | struct pkt_info { | |
257 | unsigned short byte_cnt; /* Descriptor buffer byte count */ | |
258 | unsigned short l4i_chk; /* Tx CPU provided TCP Checksum */ | |
259 | unsigned int cmd_sts; /* Descriptor command status */ | |
260 | dma_addr_t buf_ptr; /* Descriptor buffer pointer */ | |
261 | struct sk_buff *return_info; /* User resource return information */ | |
262 | }; | |
263 | ||
c9df406f LB |
264 | |
265 | /* global *******************************************************************/ | |
266 | struct mv643xx_shared_private { | |
267 | void __iomem *eth_base; | |
268 | ||
269 | /* used to protect SMI_REG, which is shared across ports */ | |
270 | spinlock_t phy_lock; | |
271 | ||
272 | u32 win_protect; | |
273 | ||
274 | unsigned int t_clk; | |
275 | }; | |
276 | ||
277 | ||
278 | /* per-port *****************************************************************/ | |
fbd6a754 LB |
279 | struct mv643xx_mib_counters { |
280 | u64 good_octets_received; | |
281 | u32 bad_octets_received; | |
282 | u32 internal_mac_transmit_err; | |
283 | u32 good_frames_received; | |
284 | u32 bad_frames_received; | |
285 | u32 broadcast_frames_received; | |
286 | u32 multicast_frames_received; | |
287 | u32 frames_64_octets; | |
288 | u32 frames_65_to_127_octets; | |
289 | u32 frames_128_to_255_octets; | |
290 | u32 frames_256_to_511_octets; | |
291 | u32 frames_512_to_1023_octets; | |
292 | u32 frames_1024_to_max_octets; | |
293 | u64 good_octets_sent; | |
294 | u32 good_frames_sent; | |
295 | u32 excessive_collision; | |
296 | u32 multicast_frames_sent; | |
297 | u32 broadcast_frames_sent; | |
298 | u32 unrec_mac_control_received; | |
299 | u32 fc_sent; | |
300 | u32 good_fc_received; | |
301 | u32 bad_fc_received; | |
302 | u32 undersize_received; | |
303 | u32 fragments_received; | |
304 | u32 oversize_received; | |
305 | u32 jabber_received; | |
306 | u32 mac_receive_error; | |
307 | u32 bad_crc_event; | |
308 | u32 collision; | |
309 | u32 late_collision; | |
310 | }; | |
311 | ||
312 | struct mv643xx_private { | |
fa3959f4 | 313 | struct mv643xx_shared_private *shared; |
fbd6a754 LB |
314 | int port_num; /* User Ethernet port number */ |
315 | ||
ce4e2e45 LB |
316 | struct mv643xx_shared_private *shared_smi; |
317 | ||
fbd6a754 LB |
318 | u32 rx_sram_addr; /* Base address of rx sram area */ |
319 | u32 rx_sram_size; /* Size of rx sram area */ | |
320 | u32 tx_sram_addr; /* Base address of tx sram area */ | |
321 | u32 tx_sram_size; /* Size of tx sram area */ | |
322 | ||
323 | int rx_resource_err; /* Rx ring resource error flag */ | |
324 | ||
325 | /* Tx/Rx rings managment indexes fields. For driver use */ | |
326 | ||
327 | /* Next available and first returning Rx resource */ | |
328 | int rx_curr_desc_q, rx_used_desc_q; | |
329 | ||
330 | /* Next available and first returning Tx resource */ | |
331 | int tx_curr_desc_q, tx_used_desc_q; | |
332 | ||
333 | #ifdef MV643XX_TX_FAST_REFILL | |
334 | u32 tx_clean_threshold; | |
335 | #endif | |
336 | ||
337 | struct eth_rx_desc *p_rx_desc_area; | |
338 | dma_addr_t rx_desc_dma; | |
339 | int rx_desc_area_size; | |
340 | struct sk_buff **rx_skb; | |
341 | ||
342 | struct eth_tx_desc *p_tx_desc_area; | |
343 | dma_addr_t tx_desc_dma; | |
344 | int tx_desc_area_size; | |
345 | struct sk_buff **tx_skb; | |
346 | ||
347 | struct work_struct tx_timeout_task; | |
348 | ||
349 | struct net_device *dev; | |
350 | struct napi_struct napi; | |
351 | struct net_device_stats stats; | |
352 | struct mv643xx_mib_counters mib_counters; | |
353 | spinlock_t lock; | |
354 | /* Size of Tx Ring per queue */ | |
355 | int tx_ring_size; | |
356 | /* Number of tx descriptors in use */ | |
357 | int tx_desc_count; | |
358 | /* Size of Rx Ring per queue */ | |
359 | int rx_ring_size; | |
360 | /* Number of rx descriptors in use */ | |
361 | int rx_desc_count; | |
362 | ||
363 | /* | |
364 | * Used in case RX Ring is empty, which can be caused when | |
365 | * system does not have resources (skb's) | |
366 | */ | |
367 | struct timer_list timeout; | |
368 | ||
369 | u32 rx_int_coal; | |
370 | u32 tx_int_coal; | |
371 | struct mii_if_info mii; | |
372 | }; | |
1da177e4 | 373 | |
fbd6a754 | 374 | |
c9df406f LB |
375 | /* port register accessors **************************************************/ |
376 | static inline u32 rdl(struct mv643xx_private *mp, int offset) | |
377 | { | |
378 | return readl(mp->shared->eth_base + offset); | |
379 | } | |
fbd6a754 | 380 | |
c9df406f LB |
381 | static inline void wrl(struct mv643xx_private *mp, int offset, u32 data) |
382 | { | |
383 | writel(data, mp->shared->eth_base + offset); | |
384 | } | |
fbd6a754 | 385 | |
fbd6a754 | 386 | |
c9df406f LB |
387 | /* rxq/txq helper functions *************************************************/ |
388 | static void mv643xx_eth_port_enable_rx(struct mv643xx_private *mp, | |
389 | unsigned int queues) | |
390 | { | |
3cb4667c | 391 | wrl(mp, RXQ_COMMAND(mp->port_num), queues); |
c9df406f | 392 | } |
fbd6a754 | 393 | |
c9df406f LB |
394 | static unsigned int mv643xx_eth_port_disable_rx(struct mv643xx_private *mp) |
395 | { | |
396 | unsigned int port_num = mp->port_num; | |
397 | u32 queues; | |
fbd6a754 | 398 | |
c9df406f | 399 | /* Stop Rx port activity. Check port Rx activity. */ |
3cb4667c | 400 | queues = rdl(mp, RXQ_COMMAND(port_num)) & 0xFF; |
c9df406f LB |
401 | if (queues) { |
402 | /* Issue stop command for active queues only */ | |
3cb4667c | 403 | wrl(mp, RXQ_COMMAND(port_num), (queues << 8)); |
1da177e4 | 404 | |
c9df406f LB |
405 | /* Wait for all Rx activity to terminate. */ |
406 | /* Check port cause register that all Rx queues are stopped */ | |
3cb4667c | 407 | while (rdl(mp, RXQ_COMMAND(port_num)) & 0xFF) |
e1bea50a | 408 | udelay(10); |
c9df406f | 409 | } |
1da177e4 | 410 | |
c9df406f LB |
411 | return queues; |
412 | } | |
413 | ||
414 | static void mv643xx_eth_port_enable_tx(struct mv643xx_private *mp, | |
415 | unsigned int queues) | |
1da177e4 | 416 | { |
3cb4667c | 417 | wrl(mp, TXQ_COMMAND(mp->port_num), queues); |
1da177e4 LT |
418 | } |
419 | ||
c9df406f | 420 | static unsigned int mv643xx_eth_port_disable_tx(struct mv643xx_private *mp) |
1da177e4 | 421 | { |
c9df406f LB |
422 | unsigned int port_num = mp->port_num; |
423 | u32 queues; | |
424 | ||
425 | /* Stop Tx port activity. Check port Tx activity. */ | |
3cb4667c | 426 | queues = rdl(mp, TXQ_COMMAND(port_num)) & 0xFF; |
c9df406f LB |
427 | if (queues) { |
428 | /* Issue stop command for active queues only */ | |
3cb4667c | 429 | wrl(mp, TXQ_COMMAND(port_num), (queues << 8)); |
c9df406f LB |
430 | |
431 | /* Wait for all Tx activity to terminate. */ | |
432 | /* Check port cause register that all Tx queues are stopped */ | |
3cb4667c | 433 | while (rdl(mp, TXQ_COMMAND(port_num)) & 0xFF) |
e1bea50a | 434 | udelay(10); |
c9df406f LB |
435 | |
436 | /* Wait for Tx FIFO to empty */ | |
a2a41689 | 437 | while (rdl(mp, PORT_STATUS(port_num)) & TX_FIFO_EMPTY) |
e1bea50a | 438 | udelay(10); |
c9df406f LB |
439 | } |
440 | ||
441 | return queues; | |
1da177e4 LT |
442 | } |
443 | ||
c9df406f LB |
444 | |
445 | /* rx ***********************************************************************/ | |
446 | static void mv643xx_eth_free_completed_tx_descs(struct net_device *dev); | |
447 | ||
1da177e4 | 448 | /* |
c9df406f | 449 | * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring. |
1da177e4 | 450 | * |
c9df406f LB |
451 | * DESCRIPTION: |
452 | * This routine returns a Rx buffer back to the Rx ring. It retrieves the | |
453 | * next 'used' descriptor and attached the returned buffer to it. | |
454 | * In case the Rx ring was in "resource error" condition, where there are | |
455 | * no available Rx resources, the function resets the resource error flag. | |
456 | * | |
457 | * INPUT: | |
458 | * struct mv643xx_private *mp Ethernet Port Control srtuct. | |
459 | * struct pkt_info *p_pkt_info Information on returned buffer. | |
460 | * | |
461 | * OUTPUT: | |
462 | * New available Rx resource in Rx descriptor ring. | |
463 | * | |
464 | * RETURN: | |
465 | * ETH_ERROR in case the routine can not access Rx desc ring. | |
466 | * ETH_OK otherwise. | |
1da177e4 | 467 | */ |
c9df406f LB |
468 | static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp, |
469 | struct pkt_info *p_pkt_info) | |
1da177e4 | 470 | { |
c9df406f LB |
471 | int used_rx_desc; /* Where to return Rx resource */ |
472 | volatile struct eth_rx_desc *p_used_rx_desc; | |
473 | unsigned long flags; | |
1da177e4 | 474 | |
c9df406f | 475 | spin_lock_irqsave(&mp->lock, flags); |
c0d0f2ca | 476 | |
c9df406f LB |
477 | /* Get 'used' Rx descriptor */ |
478 | used_rx_desc = mp->rx_used_desc_q; | |
479 | p_used_rx_desc = &mp->p_rx_desc_area[used_rx_desc]; | |
1da177e4 | 480 | |
c9df406f LB |
481 | p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr; |
482 | p_used_rx_desc->buf_size = p_pkt_info->byte_cnt; | |
483 | mp->rx_skb[used_rx_desc] = p_pkt_info->return_info; | |
484 | ||
485 | /* Flush the write pipe */ | |
486 | ||
487 | /* Return the descriptor to DMA ownership */ | |
488 | wmb(); | |
489 | p_used_rx_desc->cmd_sts = | |
490 | ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT; | |
491 | wmb(); | |
492 | ||
493 | /* Move the used descriptor pointer to the next descriptor */ | |
494 | mp->rx_used_desc_q = (used_rx_desc + 1) % mp->rx_ring_size; | |
495 | ||
496 | /* Any Rx return cancels the Rx resource error status */ | |
497 | mp->rx_resource_err = 0; | |
498 | ||
499 | spin_unlock_irqrestore(&mp->lock, flags); | |
500 | ||
501 | return ETH_OK; | |
1da177e4 LT |
502 | } |
503 | ||
504 | /* | |
f78fb474 | 505 | * mv643xx_eth_rx_refill_descs |
1da177e4 LT |
506 | * |
507 | * Fills / refills RX queue on a certain gigabit ethernet port | |
508 | * | |
509 | * Input : pointer to ethernet interface network device structure | |
510 | * Output : N/A | |
511 | */ | |
f78fb474 | 512 | static void mv643xx_eth_rx_refill_descs(struct net_device *dev) |
1da177e4 | 513 | { |
1da177e4 LT |
514 | struct mv643xx_private *mp = netdev_priv(dev); |
515 | struct pkt_info pkt_info; | |
516 | struct sk_buff *skb; | |
b44cd572 | 517 | int unaligned; |
1da177e4 | 518 | |
f78fb474 | 519 | while (mp->rx_desc_count < mp->rx_ring_size) { |
908b637f | 520 | skb = dev_alloc_skb(ETH_RX_SKB_SIZE + dma_get_cache_alignment()); |
1da177e4 LT |
521 | if (!skb) |
522 | break; | |
f98e36f1 | 523 | mp->rx_desc_count++; |
908b637f | 524 | unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1); |
b44cd572 | 525 | if (unaligned) |
908b637f | 526 | skb_reserve(skb, dma_get_cache_alignment() - unaligned); |
1da177e4 | 527 | pkt_info.cmd_sts = ETH_RX_ENABLE_INTERRUPT; |
7303fde8 DF |
528 | pkt_info.byte_cnt = ETH_RX_SKB_SIZE; |
529 | pkt_info.buf_ptr = dma_map_single(NULL, skb->data, | |
530 | ETH_RX_SKB_SIZE, DMA_FROM_DEVICE); | |
1da177e4 LT |
531 | pkt_info.return_info = skb; |
532 | if (eth_rx_return_buff(mp, &pkt_info) != ETH_OK) { | |
533 | printk(KERN_ERR | |
534 | "%s: Error allocating RX Ring\n", dev->name); | |
535 | break; | |
536 | } | |
7303fde8 | 537 | skb_reserve(skb, ETH_HW_IP_ALIGN); |
1da177e4 | 538 | } |
1da177e4 LT |
539 | /* |
540 | * If RX ring is empty of SKB, set a timer to try allocating | |
f78fb474 | 541 | * again at a later time. |
1da177e4 | 542 | */ |
f78fb474 | 543 | if (mp->rx_desc_count == 0) { |
1da177e4 | 544 | printk(KERN_INFO "%s: Rx ring is empty\n", dev->name); |
f78fb474 | 545 | mp->timeout.expires = jiffies + (HZ / 10); /* 100 mSec */ |
1da177e4 | 546 | add_timer(&mp->timeout); |
1da177e4 | 547 | } |
1da177e4 LT |
548 | } |
549 | ||
550 | /* | |
f78fb474 | 551 | * mv643xx_eth_rx_refill_descs_timer_wrapper |
1da177e4 LT |
552 | * |
553 | * Timer routine to wake up RX queue filling task. This function is | |
554 | * used only in case the RX queue is empty, and all alloc_skb has | |
555 | * failed (due to out of memory event). | |
556 | * | |
557 | * Input : pointer to ethernet interface network device structure | |
558 | * Output : N/A | |
559 | */ | |
f78fb474 | 560 | static inline void mv643xx_eth_rx_refill_descs_timer_wrapper(unsigned long data) |
1da177e4 | 561 | { |
f78fb474 | 562 | mv643xx_eth_rx_refill_descs((struct net_device *)data); |
1da177e4 LT |
563 | } |
564 | ||
565 | /* | |
c9df406f | 566 | * eth_port_receive - Get received information from Rx ring. |
1da177e4 | 567 | * |
c9df406f LB |
568 | * DESCRIPTION: |
569 | * This routine returns the received data to the caller. There is no | |
570 | * data copying during routine operation. All information is returned | |
571 | * using pointer to packet information struct passed from the caller. | |
572 | * If the routine exhausts Rx ring resources then the resource error flag | |
573 | * is set. | |
1da177e4 | 574 | * |
c9df406f LB |
575 | * INPUT: |
576 | * struct mv643xx_private *mp Ethernet Port Control srtuct. | |
577 | * struct pkt_info *p_pkt_info User packet buffer. | |
1da177e4 | 578 | * |
c9df406f LB |
579 | * OUTPUT: |
580 | * Rx ring current and used indexes are updated. | |
1da177e4 | 581 | * |
c9df406f LB |
582 | * RETURN: |
583 | * ETH_ERROR in case the routine can not access Rx desc ring. | |
584 | * ETH_QUEUE_FULL if Rx ring resources are exhausted. | |
585 | * ETH_END_OF_JOB if there is no received data. | |
586 | * ETH_OK otherwise. | |
1da177e4 | 587 | */ |
c9df406f LB |
588 | static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp, |
589 | struct pkt_info *p_pkt_info) | |
1da177e4 | 590 | { |
c9df406f LB |
591 | int rx_next_curr_desc, rx_curr_desc, rx_used_desc; |
592 | volatile struct eth_rx_desc *p_rx_desc; | |
593 | unsigned int command_status; | |
594 | unsigned long flags; | |
1da177e4 | 595 | |
c9df406f LB |
596 | /* Do not process Rx ring in case of Rx ring resource error */ |
597 | if (mp->rx_resource_err) | |
598 | return ETH_QUEUE_FULL; | |
16e03018 | 599 | |
c9df406f | 600 | spin_lock_irqsave(&mp->lock, flags); |
1da177e4 | 601 | |
c9df406f LB |
602 | /* Get the Rx Desc ring 'curr and 'used' indexes */ |
603 | rx_curr_desc = mp->rx_curr_desc_q; | |
604 | rx_used_desc = mp->rx_used_desc_q; | |
1da177e4 | 605 | |
c9df406f | 606 | p_rx_desc = &mp->p_rx_desc_area[rx_curr_desc]; |
1da177e4 | 607 | |
c9df406f LB |
608 | /* The following parameters are used to save readings from memory */ |
609 | command_status = p_rx_desc->cmd_sts; | |
610 | rmb(); | |
1da177e4 | 611 | |
c9df406f LB |
612 | /* Nothing to receive... */ |
613 | if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { | |
d344bff9 | 614 | spin_unlock_irqrestore(&mp->lock, flags); |
c9df406f LB |
615 | return ETH_END_OF_JOB; |
616 | } | |
d344bff9 | 617 | |
0a6cf74d | 618 | p_pkt_info->byte_cnt = p_rx_desc->byte_cnt - ETH_HW_IP_ALIGN; |
c9df406f | 619 | p_pkt_info->cmd_sts = command_status; |
0a6cf74d | 620 | p_pkt_info->buf_ptr = p_rx_desc->buf_ptr + ETH_HW_IP_ALIGN; |
c9df406f LB |
621 | p_pkt_info->return_info = mp->rx_skb[rx_curr_desc]; |
622 | p_pkt_info->l4i_chk = p_rx_desc->buf_size; | |
ff561eef | 623 | |
c9df406f LB |
624 | /* |
625 | * Clean the return info field to indicate that the | |
626 | * packet has been moved to the upper layers | |
627 | */ | |
628 | mp->rx_skb[rx_curr_desc] = NULL; | |
1da177e4 | 629 | |
c9df406f LB |
630 | /* Update current index in data structure */ |
631 | rx_next_curr_desc = (rx_curr_desc + 1) % mp->rx_ring_size; | |
632 | mp->rx_curr_desc_q = rx_next_curr_desc; | |
1da177e4 | 633 | |
c9df406f LB |
634 | /* Rx descriptors exhausted. Set the Rx ring resource error flag */ |
635 | if (rx_next_curr_desc == rx_used_desc) | |
636 | mp->rx_resource_err = 1; | |
ff561eef | 637 | |
c9df406f | 638 | spin_unlock_irqrestore(&mp->lock, flags); |
ff561eef | 639 | |
c9df406f | 640 | return ETH_OK; |
ff561eef DF |
641 | } |
642 | ||
1da177e4 LT |
643 | /* |
644 | * mv643xx_eth_receive | |
645 | * | |
646 | * This function is forward packets that are received from the port's | |
647 | * queues toward kernel core or FastRoute them to another interface. | |
648 | * | |
649 | * Input : dev - a pointer to the required interface | |
650 | * max - maximum number to receive (0 means unlimted) | |
651 | * | |
652 | * Output : number of served packets | |
653 | */ | |
1da177e4 | 654 | static int mv643xx_eth_receive_queue(struct net_device *dev, int budget) |
1da177e4 LT |
655 | { |
656 | struct mv643xx_private *mp = netdev_priv(dev); | |
09f75cd7 | 657 | struct net_device_stats *stats = &dev->stats; |
1da177e4 LT |
658 | unsigned int received_packets = 0; |
659 | struct sk_buff *skb; | |
660 | struct pkt_info pkt_info; | |
661 | ||
b1dd9ca1 | 662 | while (budget-- > 0 && eth_port_receive(mp, &pkt_info) == ETH_OK) { |
54caf44d | 663 | dma_unmap_single(NULL, pkt_info.buf_ptr, ETH_RX_SKB_SIZE, |
71d28725 | 664 | DMA_FROM_DEVICE); |
f98e36f1 | 665 | mp->rx_desc_count--; |
1da177e4 | 666 | received_packets++; |
b1dd9ca1 | 667 | |
468d09f8 DF |
668 | /* |
669 | * Update statistics. | |
670 | * Note byte count includes 4 byte CRC count | |
671 | */ | |
1da177e4 LT |
672 | stats->rx_packets++; |
673 | stats->rx_bytes += pkt_info.byte_cnt; | |
674 | skb = pkt_info.return_info; | |
675 | /* | |
676 | * In case received a packet without first / last bits on OR | |
677 | * the error summary bit is on, the packets needs to be dropeed. | |
678 | */ | |
679 | if (((pkt_info.cmd_sts | |
680 | & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) != | |
681 | (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) | |
682 | || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) { | |
683 | stats->rx_dropped++; | |
684 | if ((pkt_info.cmd_sts & (ETH_RX_FIRST_DESC | | |
685 | ETH_RX_LAST_DESC)) != | |
686 | (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) { | |
687 | if (net_ratelimit()) | |
688 | printk(KERN_ERR | |
689 | "%s: Received packet spread " | |
690 | "on multiple descriptors\n", | |
691 | dev->name); | |
692 | } | |
693 | if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) | |
694 | stats->rx_errors++; | |
695 | ||
696 | dev_kfree_skb_irq(skb); | |
697 | } else { | |
698 | /* | |
699 | * The -4 is for the CRC in the trailer of the | |
700 | * received packet | |
701 | */ | |
702 | skb_put(skb, pkt_info.byte_cnt - 4); | |
1da177e4 LT |
703 | |
704 | if (pkt_info.cmd_sts & ETH_LAYER_4_CHECKSUM_OK) { | |
705 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
706 | skb->csum = htons( | |
707 | (pkt_info.cmd_sts & 0x0007fff8) >> 3); | |
708 | } | |
709 | skb->protocol = eth_type_trans(skb, dev); | |
710 | #ifdef MV643XX_NAPI | |
711 | netif_receive_skb(skb); | |
712 | #else | |
713 | netif_rx(skb); | |
714 | #endif | |
715 | } | |
12ad74f8 | 716 | dev->last_rx = jiffies; |
1da177e4 | 717 | } |
f78fb474 | 718 | mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */ |
1da177e4 LT |
719 | |
720 | return received_packets; | |
721 | } | |
722 | ||
c9df406f LB |
723 | #ifdef MV643XX_NAPI |
724 | /* | |
725 | * mv643xx_poll | |
726 | * | |
727 | * This function is used in case of NAPI | |
728 | */ | |
729 | static int mv643xx_poll(struct napi_struct *napi, int budget) | |
d0412d96 | 730 | { |
c9df406f LB |
731 | struct mv643xx_private *mp = container_of(napi, struct mv643xx_private, napi); |
732 | struct net_device *dev = mp->dev; | |
733 | unsigned int port_num = mp->port_num; | |
734 | int work_done; | |
d0412d96 | 735 | |
c9df406f LB |
736 | #ifdef MV643XX_TX_FAST_REFILL |
737 | if (++mp->tx_clean_threshold > 5) { | |
738 | mv643xx_eth_free_completed_tx_descs(dev); | |
739 | mp->tx_clean_threshold = 0; | |
d0412d96 | 740 | } |
c9df406f | 741 | #endif |
d0412d96 | 742 | |
c9df406f | 743 | work_done = 0; |
3cb4667c | 744 | if ((rdl(mp, RXQ_CURRENT_DESC_PTR(port_num))) |
c9df406f LB |
745 | != (u32) mp->rx_used_desc_q) |
746 | work_done = mv643xx_eth_receive_queue(dev, budget); | |
d0412d96 | 747 | |
c9df406f LB |
748 | if (work_done < budget) { |
749 | netif_rx_complete(dev, napi); | |
3cb4667c LB |
750 | wrl(mp, INT_CAUSE(port_num), 0); |
751 | wrl(mp, INT_CAUSE_EXT(port_num), 0); | |
073a345c | 752 | wrl(mp, INT_MASK(port_num), INT_RX | INT_EXT); |
d0412d96 | 753 | } |
c9df406f LB |
754 | |
755 | return work_done; | |
d0412d96 | 756 | } |
c9df406f | 757 | #endif |
d0412d96 | 758 | |
c9df406f LB |
759 | |
760 | /* tx ***********************************************************************/ | |
761 | /** | |
762 | * has_tiny_unaligned_frags - check if skb has any small, unaligned fragments | |
1da177e4 | 763 | * |
c9df406f LB |
764 | * Hardware can't handle unaligned fragments smaller than 9 bytes. |
765 | * This helper function detects that case. | |
1da177e4 LT |
766 | */ |
767 | ||
c9df406f | 768 | static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb) |
1da177e4 | 769 | { |
c9df406f LB |
770 | unsigned int frag; |
771 | skb_frag_t *fragp; | |
1da177e4 | 772 | |
c9df406f LB |
773 | for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { |
774 | fragp = &skb_shinfo(skb)->frags[frag]; | |
775 | if (fragp->size <= 8 && fragp->page_offset & 0x7) | |
776 | return 1; | |
1da177e4 | 777 | } |
c9df406f LB |
778 | return 0; |
779 | } | |
7303fde8 | 780 | |
c9df406f LB |
781 | /** |
782 | * eth_alloc_tx_desc_index - return the index of the next available tx desc | |
783 | */ | |
784 | static int eth_alloc_tx_desc_index(struct mv643xx_private *mp) | |
785 | { | |
786 | int tx_desc_curr; | |
d0412d96 | 787 | |
c9df406f | 788 | BUG_ON(mp->tx_desc_count >= mp->tx_ring_size); |
1da177e4 | 789 | |
c9df406f LB |
790 | tx_desc_curr = mp->tx_curr_desc_q; |
791 | mp->tx_curr_desc_q = (tx_desc_curr + 1) % mp->tx_ring_size; | |
e4d00fa9 | 792 | |
c9df406f | 793 | BUG_ON(mp->tx_curr_desc_q == mp->tx_used_desc_q); |
468d09f8 | 794 | |
c9df406f LB |
795 | return tx_desc_curr; |
796 | } | |
468d09f8 | 797 | |
c9df406f LB |
798 | /** |
799 | * eth_tx_fill_frag_descs - fill tx hw descriptors for an skb's fragments. | |
800 | * | |
801 | * Ensure the data for each fragment to be transmitted is mapped properly, | |
802 | * then fill in descriptors in the tx hw queue. | |
803 | */ | |
804 | static void eth_tx_fill_frag_descs(struct mv643xx_private *mp, | |
805 | struct sk_buff *skb) | |
806 | { | |
807 | int frag; | |
808 | int tx_index; | |
809 | struct eth_tx_desc *desc; | |
1da177e4 | 810 | |
c9df406f LB |
811 | for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { |
812 | skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag]; | |
813 | ||
814 | tx_index = eth_alloc_tx_desc_index(mp); | |
815 | desc = &mp->p_tx_desc_area[tx_index]; | |
816 | ||
817 | desc->cmd_sts = ETH_BUFFER_OWNED_BY_DMA; | |
818 | /* Last Frag enables interrupt and frees the skb */ | |
819 | if (frag == (skb_shinfo(skb)->nr_frags - 1)) { | |
820 | desc->cmd_sts |= ETH_ZERO_PADDING | | |
821 | ETH_TX_LAST_DESC | | |
822 | ETH_TX_ENABLE_INTERRUPT; | |
823 | mp->tx_skb[tx_index] = skb; | |
824 | } else | |
825 | mp->tx_skb[tx_index] = NULL; | |
826 | ||
827 | desc = &mp->p_tx_desc_area[tx_index]; | |
828 | desc->l4i_chk = 0; | |
829 | desc->byte_cnt = this_frag->size; | |
830 | desc->buf_ptr = dma_map_page(NULL, this_frag->page, | |
831 | this_frag->page_offset, | |
832 | this_frag->size, | |
833 | DMA_TO_DEVICE); | |
834 | } | |
1da177e4 LT |
835 | } |
836 | ||
c9df406f LB |
837 | static inline __be16 sum16_as_be(__sum16 sum) |
838 | { | |
839 | return (__force __be16)sum; | |
840 | } | |
1da177e4 | 841 | |
c9df406f LB |
842 | /** |
843 | * eth_tx_submit_descs_for_skb - submit data from an skb to the tx hw | |
1da177e4 | 844 | * |
c9df406f LB |
845 | * Ensure the data for an skb to be transmitted is mapped properly, |
846 | * then fill in descriptors in the tx hw queue and start the hardware. | |
1da177e4 | 847 | */ |
c9df406f LB |
848 | static void eth_tx_submit_descs_for_skb(struct mv643xx_private *mp, |
849 | struct sk_buff *skb) | |
1da177e4 | 850 | { |
c9df406f LB |
851 | int tx_index; |
852 | struct eth_tx_desc *desc; | |
853 | u32 cmd_sts; | |
854 | int length; | |
855 | int nr_frags = skb_shinfo(skb)->nr_frags; | |
1da177e4 | 856 | |
c9df406f | 857 | cmd_sts = ETH_TX_FIRST_DESC | ETH_GEN_CRC | ETH_BUFFER_OWNED_BY_DMA; |
1da177e4 | 858 | |
c9df406f LB |
859 | tx_index = eth_alloc_tx_desc_index(mp); |
860 | desc = &mp->p_tx_desc_area[tx_index]; | |
861 | ||
862 | if (nr_frags) { | |
863 | eth_tx_fill_frag_descs(mp, skb); | |
864 | ||
865 | length = skb_headlen(skb); | |
866 | mp->tx_skb[tx_index] = NULL; | |
867 | } else { | |
868 | cmd_sts |= ETH_ZERO_PADDING | | |
869 | ETH_TX_LAST_DESC | | |
870 | ETH_TX_ENABLE_INTERRUPT; | |
871 | length = skb->len; | |
872 | mp->tx_skb[tx_index] = skb; | |
873 | } | |
874 | ||
875 | desc->byte_cnt = length; | |
876 | desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE); | |
877 | ||
878 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
879 | BUG_ON(skb->protocol != htons(ETH_P_IP)); | |
880 | ||
881 | cmd_sts |= ETH_GEN_TCP_UDP_CHECKSUM | | |
7ca72a3b | 882 | ETH_GEN_IP_V4_CHECKSUM | |
c9df406f LB |
883 | ip_hdr(skb)->ihl << ETH_TX_IHL_SHIFT; |
884 | ||
885 | switch (ip_hdr(skb)->protocol) { | |
886 | case IPPROTO_UDP: | |
887 | cmd_sts |= ETH_UDP_FRAME; | |
888 | desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check)); | |
889 | break; | |
890 | case IPPROTO_TCP: | |
891 | desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check)); | |
892 | break; | |
893 | default: | |
894 | BUG(); | |
895 | } | |
896 | } else { | |
897 | /* Errata BTS #50, IHL must be 5 if no HW checksum */ | |
898 | cmd_sts |= 5 << ETH_TX_IHL_SHIFT; | |
899 | desc->l4i_chk = 0; | |
900 | } | |
901 | ||
902 | /* ensure all other descriptors are written before first cmd_sts */ | |
903 | wmb(); | |
904 | desc->cmd_sts = cmd_sts; | |
905 | ||
906 | /* ensure all descriptors are written before poking hardware */ | |
907 | wmb(); | |
073a345c | 908 | mv643xx_eth_port_enable_tx(mp, 1); |
c9df406f LB |
909 | |
910 | mp->tx_desc_count += nr_frags + 1; | |
1da177e4 | 911 | } |
1da177e4 | 912 | |
c9df406f LB |
913 | /** |
914 | * mv643xx_eth_start_xmit - queue an skb to the hardware for transmission | |
1da177e4 LT |
915 | * |
916 | */ | |
c9df406f | 917 | static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev) |
1da177e4 | 918 | { |
c9df406f LB |
919 | struct mv643xx_private *mp = netdev_priv(dev); |
920 | struct net_device_stats *stats = &dev->stats; | |
921 | unsigned long flags; | |
afdb57a2 | 922 | |
c9df406f | 923 | BUG_ON(netif_queue_stopped(dev)); |
afdb57a2 | 924 | |
c9df406f LB |
925 | if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) { |
926 | stats->tx_dropped++; | |
927 | printk(KERN_DEBUG "%s: failed to linearize tiny " | |
928 | "unaligned fragment\n", dev->name); | |
929 | return NETDEV_TX_BUSY; | |
930 | } | |
931 | ||
932 | spin_lock_irqsave(&mp->lock, flags); | |
933 | ||
934 | if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB) { | |
935 | printk(KERN_ERR "%s: transmit with queue full\n", dev->name); | |
936 | netif_stop_queue(dev); | |
937 | spin_unlock_irqrestore(&mp->lock, flags); | |
938 | return NETDEV_TX_BUSY; | |
939 | } | |
940 | ||
941 | eth_tx_submit_descs_for_skb(mp, skb); | |
942 | stats->tx_bytes += skb->len; | |
943 | stats->tx_packets++; | |
944 | dev->trans_start = jiffies; | |
945 | ||
946 | if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB) | |
947 | netif_stop_queue(dev); | |
948 | ||
949 | spin_unlock_irqrestore(&mp->lock, flags); | |
950 | ||
951 | return NETDEV_TX_OK; | |
1da177e4 LT |
952 | } |
953 | ||
c9df406f LB |
954 | |
955 | /* mii management interface *************************************************/ | |
956 | static int ethernet_phy_get(struct mv643xx_private *mp); | |
957 | ||
1da177e4 | 958 | /* |
c9df406f | 959 | * eth_port_read_smi_reg - Read PHY registers |
1da177e4 LT |
960 | * |
961 | * DESCRIPTION: | |
c9df406f LB |
962 | * This routine utilize the SMI interface to interact with the PHY in |
963 | * order to perform PHY register read. | |
1da177e4 LT |
964 | * |
965 | * INPUT: | |
c9df406f LB |
966 | * struct mv643xx_private *mp Ethernet Port. |
967 | * unsigned int phy_reg PHY register address offset. | |
968 | * unsigned int *value Register value buffer. | |
1da177e4 LT |
969 | * |
970 | * OUTPUT: | |
c9df406f | 971 | * Write the value of a specified PHY register into given buffer. |
1da177e4 LT |
972 | * |
973 | * RETURN: | |
c9df406f LB |
974 | * false if the PHY is busy or read data is not in valid state. |
975 | * true otherwise. | |
976 | * | |
1da177e4 | 977 | */ |
c9df406f LB |
978 | static void eth_port_read_smi_reg(struct mv643xx_private *mp, |
979 | unsigned int phy_reg, unsigned int *value) | |
1da177e4 | 980 | { |
c9df406f LB |
981 | void __iomem *smi_reg = mp->shared_smi->eth_base + SMI_REG; |
982 | int phy_addr = ethernet_phy_get(mp); | |
983 | unsigned long flags; | |
1da177e4 LT |
984 | int i; |
985 | ||
c9df406f LB |
986 | /* the SMI register is a shared resource */ |
987 | spin_lock_irqsave(&mp->shared_smi->phy_lock, flags); | |
988 | ||
989 | /* wait for the SMI register to become available */ | |
990 | for (i = 0; readl(smi_reg) & ETH_SMI_BUSY; i++) { | |
e1bea50a | 991 | if (i == 1000) { |
c9df406f LB |
992 | printk("%s: PHY busy timeout\n", mp->dev->name); |
993 | goto out; | |
994 | } | |
e1bea50a | 995 | udelay(10); |
1da177e4 LT |
996 | } |
997 | ||
c9df406f LB |
998 | writel((phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ, |
999 | smi_reg); | |
1da177e4 | 1000 | |
c9df406f LB |
1001 | /* now wait for the data to be valid */ |
1002 | for (i = 0; !(readl(smi_reg) & ETH_SMI_READ_VALID); i++) { | |
e1bea50a | 1003 | if (i == 1000) { |
c9df406f LB |
1004 | printk("%s: PHY read timeout\n", mp->dev->name); |
1005 | goto out; | |
1006 | } | |
e1bea50a | 1007 | udelay(10); |
c9df406f LB |
1008 | } |
1009 | ||
1010 | *value = readl(smi_reg) & 0xffff; | |
1011 | out: | |
1012 | spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags); | |
1da177e4 LT |
1013 | } |
1014 | ||
1015 | /* | |
c9df406f | 1016 | * eth_port_write_smi_reg - Write to PHY registers |
1da177e4 LT |
1017 | * |
1018 | * DESCRIPTION: | |
c9df406f LB |
1019 | * This routine utilize the SMI interface to interact with the PHY in |
1020 | * order to perform writes to PHY registers. | |
1da177e4 LT |
1021 | * |
1022 | * INPUT: | |
c9df406f LB |
1023 | * struct mv643xx_private *mp Ethernet Port. |
1024 | * unsigned int phy_reg PHY register address offset. | |
1025 | * unsigned int value Register value. | |
1da177e4 LT |
1026 | * |
1027 | * OUTPUT: | |
c9df406f | 1028 | * Write the given value to the specified PHY register. |
1da177e4 LT |
1029 | * |
1030 | * RETURN: | |
c9df406f LB |
1031 | * false if the PHY is busy. |
1032 | * true otherwise. | |
1033 | * | |
1da177e4 | 1034 | */ |
c9df406f LB |
1035 | static void eth_port_write_smi_reg(struct mv643xx_private *mp, |
1036 | unsigned int phy_reg, unsigned int value) | |
1da177e4 | 1037 | { |
c9df406f LB |
1038 | void __iomem *smi_reg = mp->shared_smi->eth_base + SMI_REG; |
1039 | int phy_addr = ethernet_phy_get(mp); | |
1040 | unsigned long flags; | |
1da177e4 LT |
1041 | int i; |
1042 | ||
c9df406f LB |
1043 | /* the SMI register is a shared resource */ |
1044 | spin_lock_irqsave(&mp->shared_smi->phy_lock, flags); | |
1045 | ||
1046 | /* wait for the SMI register to become available */ | |
1047 | for (i = 0; readl(smi_reg) & ETH_SMI_BUSY; i++) { | |
e1bea50a | 1048 | if (i == 1000) { |
c9df406f LB |
1049 | printk("%s: PHY busy timeout\n", mp->dev->name); |
1050 | goto out; | |
1051 | } | |
e1bea50a | 1052 | udelay(10); |
1da177e4 LT |
1053 | } |
1054 | ||
c9df406f LB |
1055 | writel((phy_addr << 16) | (phy_reg << 21) | |
1056 | ETH_SMI_OPCODE_WRITE | (value & 0xffff), smi_reg); | |
1057 | out: | |
1058 | spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags); | |
1059 | } | |
1da177e4 | 1060 | |
c9df406f LB |
1061 | |
1062 | /* mib counters *************************************************************/ | |
1063 | /* | |
1064 | * eth_clear_mib_counters - Clear all MIB counters | |
1065 | * | |
1066 | * DESCRIPTION: | |
1067 | * This function clears all MIB counters of a specific ethernet port. | |
1068 | * A read from the MIB counter will reset the counter. | |
1069 | * | |
1070 | * INPUT: | |
1071 | * struct mv643xx_private *mp Ethernet Port. | |
1072 | * | |
1073 | * OUTPUT: | |
1074 | * After reading all MIB counters, the counters resets. | |
1075 | * | |
1076 | * RETURN: | |
1077 | * MIB counter value. | |
1078 | * | |
1079 | */ | |
1080 | static void eth_clear_mib_counters(struct mv643xx_private *mp) | |
1081 | { | |
1082 | unsigned int port_num = mp->port_num; | |
1083 | int i; | |
1084 | ||
1085 | /* Perform dummy reads from MIB counters */ | |
4b8e3655 | 1086 | for (i = 0; i < 0x80; i += 4) |
3cb4667c | 1087 | rdl(mp, MIB_COUNTERS(port_num) + i); |
1da177e4 LT |
1088 | } |
1089 | ||
c9df406f | 1090 | static inline u32 read_mib(struct mv643xx_private *mp, int offset) |
d0412d96 | 1091 | { |
3cb4667c | 1092 | return rdl(mp, MIB_COUNTERS(mp->port_num) + offset); |
c9df406f | 1093 | } |
d0412d96 | 1094 | |
c9df406f LB |
1095 | static void eth_update_mib_counters(struct mv643xx_private *mp) |
1096 | { | |
1097 | struct mv643xx_mib_counters *p = &mp->mib_counters; | |
4b8e3655 LB |
1098 | |
1099 | p->good_octets_received += read_mib(mp, 0x00); | |
1100 | p->good_octets_received += (u64)read_mib(mp, 0x04) << 32; | |
1101 | p->bad_octets_received += read_mib(mp, 0x08); | |
1102 | p->internal_mac_transmit_err += read_mib(mp, 0x0c); | |
1103 | p->good_frames_received += read_mib(mp, 0x10); | |
1104 | p->bad_frames_received += read_mib(mp, 0x14); | |
1105 | p->broadcast_frames_received += read_mib(mp, 0x18); | |
1106 | p->multicast_frames_received += read_mib(mp, 0x1c); | |
1107 | p->frames_64_octets += read_mib(mp, 0x20); | |
1108 | p->frames_65_to_127_octets += read_mib(mp, 0x24); | |
1109 | p->frames_128_to_255_octets += read_mib(mp, 0x28); | |
1110 | p->frames_256_to_511_octets += read_mib(mp, 0x2c); | |
1111 | p->frames_512_to_1023_octets += read_mib(mp, 0x30); | |
1112 | p->frames_1024_to_max_octets += read_mib(mp, 0x34); | |
1113 | p->good_octets_sent += read_mib(mp, 0x38); | |
1114 | p->good_octets_sent += (u64)read_mib(mp, 0x3c) << 32; | |
1115 | p->good_frames_sent += read_mib(mp, 0x40); | |
1116 | p->excessive_collision += read_mib(mp, 0x44); | |
1117 | p->multicast_frames_sent += read_mib(mp, 0x48); | |
1118 | p->broadcast_frames_sent += read_mib(mp, 0x4c); | |
1119 | p->unrec_mac_control_received += read_mib(mp, 0x50); | |
1120 | p->fc_sent += read_mib(mp, 0x54); | |
1121 | p->good_fc_received += read_mib(mp, 0x58); | |
1122 | p->bad_fc_received += read_mib(mp, 0x5c); | |
1123 | p->undersize_received += read_mib(mp, 0x60); | |
1124 | p->fragments_received += read_mib(mp, 0x64); | |
1125 | p->oversize_received += read_mib(mp, 0x68); | |
1126 | p->jabber_received += read_mib(mp, 0x6c); | |
1127 | p->mac_receive_error += read_mib(mp, 0x70); | |
1128 | p->bad_crc_event += read_mib(mp, 0x74); | |
1129 | p->collision += read_mib(mp, 0x78); | |
1130 | p->late_collision += read_mib(mp, 0x7c); | |
d0412d96 JC |
1131 | } |
1132 | ||
c9df406f LB |
1133 | |
1134 | /* ethtool ******************************************************************/ | |
1135 | struct mv643xx_stats { | |
1136 | char stat_string[ETH_GSTRING_LEN]; | |
1137 | int sizeof_stat; | |
1138 | int stat_offset; | |
1139 | }; | |
1140 | ||
1141 | #define MV643XX_STAT(m) FIELD_SIZEOF(struct mv643xx_private, m), \ | |
1142 | offsetof(struct mv643xx_private, m) | |
1143 | ||
1144 | static const struct mv643xx_stats mv643xx_gstrings_stats[] = { | |
1145 | { "rx_packets", MV643XX_STAT(stats.rx_packets) }, | |
1146 | { "tx_packets", MV643XX_STAT(stats.tx_packets) }, | |
1147 | { "rx_bytes", MV643XX_STAT(stats.rx_bytes) }, | |
1148 | { "tx_bytes", MV643XX_STAT(stats.tx_bytes) }, | |
1149 | { "rx_errors", MV643XX_STAT(stats.rx_errors) }, | |
1150 | { "tx_errors", MV643XX_STAT(stats.tx_errors) }, | |
1151 | { "rx_dropped", MV643XX_STAT(stats.rx_dropped) }, | |
1152 | { "tx_dropped", MV643XX_STAT(stats.tx_dropped) }, | |
1153 | { "good_octets_received", MV643XX_STAT(mib_counters.good_octets_received) }, | |
1154 | { "bad_octets_received", MV643XX_STAT(mib_counters.bad_octets_received) }, | |
1155 | { "internal_mac_transmit_err", MV643XX_STAT(mib_counters.internal_mac_transmit_err) }, | |
1156 | { "good_frames_received", MV643XX_STAT(mib_counters.good_frames_received) }, | |
1157 | { "bad_frames_received", MV643XX_STAT(mib_counters.bad_frames_received) }, | |
1158 | { "broadcast_frames_received", MV643XX_STAT(mib_counters.broadcast_frames_received) }, | |
1159 | { "multicast_frames_received", MV643XX_STAT(mib_counters.multicast_frames_received) }, | |
1160 | { "frames_64_octets", MV643XX_STAT(mib_counters.frames_64_octets) }, | |
1161 | { "frames_65_to_127_octets", MV643XX_STAT(mib_counters.frames_65_to_127_octets) }, | |
1162 | { "frames_128_to_255_octets", MV643XX_STAT(mib_counters.frames_128_to_255_octets) }, | |
1163 | { "frames_256_to_511_octets", MV643XX_STAT(mib_counters.frames_256_to_511_octets) }, | |
1164 | { "frames_512_to_1023_octets", MV643XX_STAT(mib_counters.frames_512_to_1023_octets) }, | |
1165 | { "frames_1024_to_max_octets", MV643XX_STAT(mib_counters.frames_1024_to_max_octets) }, | |
1166 | { "good_octets_sent", MV643XX_STAT(mib_counters.good_octets_sent) }, | |
1167 | { "good_frames_sent", MV643XX_STAT(mib_counters.good_frames_sent) }, | |
1168 | { "excessive_collision", MV643XX_STAT(mib_counters.excessive_collision) }, | |
1169 | { "multicast_frames_sent", MV643XX_STAT(mib_counters.multicast_frames_sent) }, | |
1170 | { "broadcast_frames_sent", MV643XX_STAT(mib_counters.broadcast_frames_sent) }, | |
1171 | { "unrec_mac_control_received", MV643XX_STAT(mib_counters.unrec_mac_control_received) }, | |
1172 | { "fc_sent", MV643XX_STAT(mib_counters.fc_sent) }, | |
1173 | { "good_fc_received", MV643XX_STAT(mib_counters.good_fc_received) }, | |
1174 | { "bad_fc_received", MV643XX_STAT(mib_counters.bad_fc_received) }, | |
1175 | { "undersize_received", MV643XX_STAT(mib_counters.undersize_received) }, | |
1176 | { "fragments_received", MV643XX_STAT(mib_counters.fragments_received) }, | |
1177 | { "oversize_received", MV643XX_STAT(mib_counters.oversize_received) }, | |
1178 | { "jabber_received", MV643XX_STAT(mib_counters.jabber_received) }, | |
1179 | { "mac_receive_error", MV643XX_STAT(mib_counters.mac_receive_error) }, | |
1180 | { "bad_crc_event", MV643XX_STAT(mib_counters.bad_crc_event) }, | |
1181 | { "collision", MV643XX_STAT(mib_counters.collision) }, | |
1182 | { "late_collision", MV643XX_STAT(mib_counters.late_collision) }, | |
1183 | }; | |
1184 | ||
1185 | #define MV643XX_STATS_LEN ARRAY_SIZE(mv643xx_gstrings_stats) | |
1186 | ||
d0412d96 JC |
1187 | static int mv643xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
1188 | { | |
1189 | struct mv643xx_private *mp = netdev_priv(dev); | |
1190 | int err; | |
1191 | ||
1192 | spin_lock_irq(&mp->lock); | |
1193 | err = mii_ethtool_gset(&mp->mii, cmd); | |
1194 | spin_unlock_irq(&mp->lock); | |
1195 | ||
1196 | /* The PHY may support 1000baseT_Half, but the mv643xx does not */ | |
1197 | cmd->supported &= ~SUPPORTED_1000baseT_Half; | |
1198 | cmd->advertising &= ~ADVERTISED_1000baseT_Half; | |
1199 | ||
1200 | return err; | |
1201 | } | |
1202 | ||
c9df406f | 1203 | static int mv643xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
1da177e4 LT |
1204 | { |
1205 | struct mv643xx_private *mp = netdev_priv(dev); | |
ab4384a6 DF |
1206 | int err; |
1207 | ||
c9df406f LB |
1208 | spin_lock_irq(&mp->lock); |
1209 | err = mii_ethtool_sset(&mp->mii, cmd); | |
1210 | spin_unlock_irq(&mp->lock); | |
85cf572c | 1211 | |
c9df406f LB |
1212 | return err; |
1213 | } | |
1da177e4 | 1214 | |
c9df406f LB |
1215 | static void mv643xx_get_drvinfo(struct net_device *netdev, |
1216 | struct ethtool_drvinfo *drvinfo) | |
1217 | { | |
1218 | strncpy(drvinfo->driver, mv643xx_driver_name, 32); | |
1219 | strncpy(drvinfo->version, mv643xx_driver_version, 32); | |
1220 | strncpy(drvinfo->fw_version, "N/A", 32); | |
1221 | strncpy(drvinfo->bus_info, "mv643xx", 32); | |
1222 | drvinfo->n_stats = MV643XX_STATS_LEN; | |
1223 | } | |
1da177e4 | 1224 | |
c9df406f LB |
1225 | static int mv643xx_eth_nway_restart(struct net_device *dev) |
1226 | { | |
1227 | struct mv643xx_private *mp = netdev_priv(dev); | |
1da177e4 | 1228 | |
c9df406f LB |
1229 | return mii_nway_restart(&mp->mii); |
1230 | } | |
1da177e4 | 1231 | |
c9df406f LB |
1232 | static u32 mv643xx_eth_get_link(struct net_device *dev) |
1233 | { | |
1234 | struct mv643xx_private *mp = netdev_priv(dev); | |
1da177e4 | 1235 | |
c9df406f LB |
1236 | return mii_link_ok(&mp->mii); |
1237 | } | |
1da177e4 | 1238 | |
c9df406f LB |
1239 | static void mv643xx_get_strings(struct net_device *netdev, uint32_t stringset, |
1240 | uint8_t *data) | |
1241 | { | |
1242 | int i; | |
1da177e4 | 1243 | |
c9df406f LB |
1244 | switch(stringset) { |
1245 | case ETH_SS_STATS: | |
1246 | for (i=0; i < MV643XX_STATS_LEN; i++) { | |
1247 | memcpy(data + i * ETH_GSTRING_LEN, | |
1248 | mv643xx_gstrings_stats[i].stat_string, | |
1249 | ETH_GSTRING_LEN); | |
1250 | } | |
1251 | break; | |
1252 | } | |
1253 | } | |
1da177e4 | 1254 | |
c9df406f LB |
1255 | static void mv643xx_get_ethtool_stats(struct net_device *netdev, |
1256 | struct ethtool_stats *stats, uint64_t *data) | |
1257 | { | |
1258 | struct mv643xx_private *mp = netdev->priv; | |
1259 | int i; | |
1da177e4 | 1260 | |
c9df406f | 1261 | eth_update_mib_counters(mp); |
1da177e4 | 1262 | |
c9df406f LB |
1263 | for (i = 0; i < MV643XX_STATS_LEN; i++) { |
1264 | char *p = (char *)mp+mv643xx_gstrings_stats[i].stat_offset; | |
1265 | data[i] = (mv643xx_gstrings_stats[i].sizeof_stat == | |
1266 | sizeof(uint64_t)) ? *(uint64_t *)p : *(uint32_t *)p; | |
1da177e4 | 1267 | } |
c9df406f | 1268 | } |
1da177e4 | 1269 | |
c9df406f LB |
1270 | static int mv643xx_get_sset_count(struct net_device *netdev, int sset) |
1271 | { | |
1272 | switch (sset) { | |
1273 | case ETH_SS_STATS: | |
1274 | return MV643XX_STATS_LEN; | |
1275 | default: | |
1276 | return -EOPNOTSUPP; | |
1277 | } | |
1278 | } | |
1da177e4 | 1279 | |
c9df406f LB |
1280 | static const struct ethtool_ops mv643xx_ethtool_ops = { |
1281 | .get_settings = mv643xx_get_settings, | |
1282 | .set_settings = mv643xx_set_settings, | |
1283 | .get_drvinfo = mv643xx_get_drvinfo, | |
1284 | .get_link = mv643xx_eth_get_link, | |
1285 | .set_sg = ethtool_op_set_sg, | |
1286 | .get_sset_count = mv643xx_get_sset_count, | |
1287 | .get_ethtool_stats = mv643xx_get_ethtool_stats, | |
1288 | .get_strings = mv643xx_get_strings, | |
1289 | .nway_reset = mv643xx_eth_nway_restart, | |
1290 | }; | |
1da177e4 | 1291 | |
bea3348e | 1292 | |
c9df406f LB |
1293 | /* address handling *********************************************************/ |
1294 | /* | |
1295 | * eth_port_uc_addr_get - Read the MAC address from the port's hw registers | |
1296 | */ | |
1297 | static void eth_port_uc_addr_get(struct mv643xx_private *mp, | |
1298 | unsigned char *p_addr) | |
1299 | { | |
1300 | unsigned int port_num = mp->port_num; | |
1301 | unsigned int mac_h; | |
1302 | unsigned int mac_l; | |
1da177e4 | 1303 | |
c9df406f LB |
1304 | mac_h = rdl(mp, MAC_ADDR_HIGH(port_num)); |
1305 | mac_l = rdl(mp, MAC_ADDR_LOW(port_num)); | |
1da177e4 | 1306 | |
c9df406f LB |
1307 | p_addr[0] = (mac_h >> 24) & 0xff; |
1308 | p_addr[1] = (mac_h >> 16) & 0xff; | |
1309 | p_addr[2] = (mac_h >> 8) & 0xff; | |
1310 | p_addr[3] = mac_h & 0xff; | |
1311 | p_addr[4] = (mac_l >> 8) & 0xff; | |
1312 | p_addr[5] = mac_l & 0xff; | |
1313 | } | |
1da177e4 | 1314 | |
c9df406f LB |
1315 | /* |
1316 | * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables | |
1317 | * | |
1318 | * DESCRIPTION: | |
1319 | * Go through all the DA filter tables (Unicast, Special Multicast & | |
1320 | * Other Multicast) and set each entry to 0. | |
1321 | * | |
1322 | * INPUT: | |
1323 | * struct mv643xx_private *mp Ethernet Port. | |
1324 | * | |
1325 | * OUTPUT: | |
1326 | * Multicast and Unicast packets are rejected. | |
1327 | * | |
1328 | * RETURN: | |
1329 | * None. | |
1330 | */ | |
1331 | static void eth_port_init_mac_tables(struct mv643xx_private *mp) | |
1332 | { | |
1333 | unsigned int port_num = mp->port_num; | |
1334 | int table_index; | |
1da177e4 | 1335 | |
c9df406f LB |
1336 | /* Clear DA filter unicast table (Ex_dFUT) */ |
1337 | for (table_index = 0; table_index <= 0xC; table_index += 4) | |
3cb4667c | 1338 | wrl(mp, UNICAST_TABLE(port_num) + table_index, 0); |
1da177e4 | 1339 | |
c9df406f LB |
1340 | for (table_index = 0; table_index <= 0xFC; table_index += 4) { |
1341 | /* Clear DA filter special multicast table (Ex_dFSMT) */ | |
3cb4667c | 1342 | wrl(mp, SPECIAL_MCAST_TABLE(port_num) + table_index, 0); |
c9df406f | 1343 | /* Clear DA filter other multicast table (Ex_dFOMT) */ |
3cb4667c | 1344 | wrl(mp, OTHER_MCAST_TABLE(port_num) + table_index, 0); |
c9df406f LB |
1345 | } |
1346 | } | |
d0412d96 | 1347 | |
c9df406f LB |
1348 | /* |
1349 | * The entries in each table are indexed by a hash of a packet's MAC | |
1350 | * address. One bit in each entry determines whether the packet is | |
1351 | * accepted. There are 4 entries (each 8 bits wide) in each register | |
1352 | * of the table. The bits in each entry are defined as follows: | |
1353 | * 0 Accept=1, Drop=0 | |
1354 | * 3-1 Queue (ETH_Q0=0) | |
1355 | * 7-4 Reserved = 0; | |
1356 | */ | |
1357 | static void eth_port_set_filter_table_entry(struct mv643xx_private *mp, | |
1358 | int table, unsigned char entry) | |
1359 | { | |
1360 | unsigned int table_reg; | |
1361 | unsigned int tbl_offset; | |
1362 | unsigned int reg_offset; | |
ab4384a6 | 1363 | |
c9df406f LB |
1364 | tbl_offset = (entry / 4) * 4; /* Register offset of DA table entry */ |
1365 | reg_offset = entry % 4; /* Entry offset within the register */ | |
ab4384a6 | 1366 | |
c9df406f LB |
1367 | /* Set "accepts frame bit" at specified table entry */ |
1368 | table_reg = rdl(mp, table + tbl_offset); | |
1369 | table_reg |= 0x01 << (8 * reg_offset); | |
1370 | wrl(mp, table + tbl_offset, table_reg); | |
1da177e4 LT |
1371 | } |
1372 | ||
c9df406f LB |
1373 | /* |
1374 | * eth_port_uc_addr_set - Write a MAC address into the port's hw registers | |
1375 | */ | |
1376 | static void eth_port_uc_addr_set(struct mv643xx_private *mp, | |
1377 | unsigned char *p_addr) | |
1da177e4 | 1378 | { |
c9df406f LB |
1379 | unsigned int port_num = mp->port_num; |
1380 | unsigned int mac_h; | |
1381 | unsigned int mac_l; | |
1382 | int table; | |
1da177e4 | 1383 | |
c9df406f LB |
1384 | mac_l = (p_addr[4] << 8) | (p_addr[5]); |
1385 | mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) | | |
1386 | (p_addr[3] << 0); | |
ff561eef | 1387 | |
c9df406f LB |
1388 | wrl(mp, MAC_ADDR_LOW(port_num), mac_l); |
1389 | wrl(mp, MAC_ADDR_HIGH(port_num), mac_h); | |
1da177e4 | 1390 | |
c9df406f | 1391 | /* Accept frames with this address */ |
3cb4667c | 1392 | table = UNICAST_TABLE(port_num); |
c9df406f | 1393 | eth_port_set_filter_table_entry(mp, table, p_addr[5] & 0x0f); |
1da177e4 LT |
1394 | } |
1395 | ||
c9df406f LB |
1396 | /* |
1397 | * mv643xx_eth_update_mac_address | |
1398 | * | |
1399 | * Update the MAC address of the port in the address table | |
1400 | * | |
1401 | * Input : pointer to ethernet interface network device structure | |
1402 | * Output : N/A | |
1403 | */ | |
1404 | static void mv643xx_eth_update_mac_address(struct net_device *dev) | |
1da177e4 LT |
1405 | { |
1406 | struct mv643xx_private *mp = netdev_priv(dev); | |
1da177e4 | 1407 | |
c9df406f LB |
1408 | eth_port_init_mac_tables(mp); |
1409 | eth_port_uc_addr_set(mp, dev->dev_addr); | |
1410 | } | |
1da177e4 LT |
1411 | |
1412 | /* | |
c9df406f | 1413 | * mv643xx_eth_set_mac_address |
1da177e4 | 1414 | * |
c9df406f LB |
1415 | * Change the interface's mac address. |
1416 | * No special hardware thing should be done because interface is always | |
1417 | * put in promiscuous mode. | |
1418 | * | |
1419 | * Input : pointer to ethernet interface network device structure and | |
1420 | * a pointer to the designated entry to be added to the cache. | |
1421 | * Output : zero upon success, negative upon failure | |
1da177e4 | 1422 | */ |
c9df406f | 1423 | static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr) |
1da177e4 | 1424 | { |
c9df406f | 1425 | int i; |
1da177e4 | 1426 | |
c9df406f LB |
1427 | for (i = 0; i < 6; i++) |
1428 | /* +2 is for the offset of the HW addr type */ | |
1429 | dev->dev_addr[i] = ((unsigned char *)addr)[i + 2]; | |
1430 | mv643xx_eth_update_mac_address(dev); | |
1da177e4 LT |
1431 | return 0; |
1432 | } | |
1433 | ||
1da177e4 | 1434 | /* |
c9df406f | 1435 | * eth_port_mc_addr - Multicast address settings. |
1da177e4 | 1436 | * |
c9df406f LB |
1437 | * The MV device supports multicast using two tables: |
1438 | * 1) Special Multicast Table for MAC addresses of the form | |
1439 | * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_FF). | |
1440 | * The MAC DA[7:0] bits are used as a pointer to the Special Multicast | |
1441 | * Table entries in the DA-Filter table. | |
1442 | * 2) Other Multicast Table for multicast of another type. A CRC-8bit | |
1443 | * is used as an index to the Other Multicast Table entries in the | |
1444 | * DA-Filter table. This function calculates the CRC-8bit value. | |
1445 | * In either case, eth_port_set_filter_table_entry() is then called | |
1446 | * to set to set the actual table entry. | |
1da177e4 | 1447 | */ |
c9df406f | 1448 | static void eth_port_mc_addr(struct mv643xx_private *mp, unsigned char *p_addr) |
1da177e4 | 1449 | { |
1da177e4 | 1450 | unsigned int port_num = mp->port_num; |
c9df406f LB |
1451 | unsigned int mac_h; |
1452 | unsigned int mac_l; | |
1453 | unsigned char crc_result = 0; | |
1454 | int table; | |
1455 | int mac_array[48]; | |
1456 | int crc[8]; | |
1457 | int i; | |
1da177e4 | 1458 | |
c9df406f LB |
1459 | if ((p_addr[0] == 0x01) && (p_addr[1] == 0x00) && |
1460 | (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) { | |
3cb4667c | 1461 | table = SPECIAL_MCAST_TABLE(port_num); |
c9df406f LB |
1462 | eth_port_set_filter_table_entry(mp, table, p_addr[5]); |
1463 | return; | |
1da177e4 | 1464 | } |
1da177e4 | 1465 | |
c9df406f LB |
1466 | /* Calculate CRC-8 out of the given address */ |
1467 | mac_h = (p_addr[0] << 8) | (p_addr[1]); | |
1468 | mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) | | |
1469 | (p_addr[4] << 8) | (p_addr[5] << 0); | |
1da177e4 | 1470 | |
c9df406f LB |
1471 | for (i = 0; i < 32; i++) |
1472 | mac_array[i] = (mac_l >> i) & 0x1; | |
1473 | for (i = 32; i < 48; i++) | |
1474 | mac_array[i] = (mac_h >> (i - 32)) & 0x1; | |
1da177e4 | 1475 | |
c9df406f LB |
1476 | crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ mac_array[39] ^ |
1477 | mac_array[35] ^ mac_array[34] ^ mac_array[31] ^ mac_array[30] ^ | |
1478 | mac_array[28] ^ mac_array[23] ^ mac_array[21] ^ mac_array[19] ^ | |
1479 | mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ mac_array[12] ^ | |
1480 | mac_array[8] ^ mac_array[7] ^ mac_array[6] ^ mac_array[0]; | |
1da177e4 | 1481 | |
c9df406f LB |
1482 | crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^ |
1483 | mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ mac_array[34] ^ | |
1484 | mac_array[32] ^ mac_array[30] ^ mac_array[29] ^ mac_array[28] ^ | |
1485 | mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ mac_array[21] ^ | |
1486 | mac_array[20] ^ mac_array[18] ^ mac_array[17] ^ mac_array[16] ^ | |
1487 | mac_array[15] ^ mac_array[14] ^ mac_array[13] ^ mac_array[12] ^ | |
1488 | mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ mac_array[0]; | |
f7ea3337 | 1489 | |
c9df406f LB |
1490 | crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ mac_array[43] ^ |
1491 | mac_array[42] ^ mac_array[39] ^ mac_array[37] ^ mac_array[34] ^ | |
1492 | mac_array[33] ^ mac_array[29] ^ mac_array[28] ^ mac_array[25] ^ | |
1493 | mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ mac_array[15] ^ | |
1494 | mac_array[13] ^ mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ | |
1495 | mac_array[6] ^ mac_array[2] ^ mac_array[1] ^ mac_array[0]; | |
f7ea3337 | 1496 | |
c9df406f LB |
1497 | crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^ |
1498 | mac_array[40] ^ mac_array[38] ^ mac_array[35] ^ mac_array[34] ^ | |
1499 | mac_array[30] ^ mac_array[29] ^ mac_array[26] ^ mac_array[25] ^ | |
1500 | mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ | |
1501 | mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[7] ^ | |
1502 | mac_array[3] ^ mac_array[2] ^ mac_array[1]; | |
f7ea3337 | 1503 | |
c9df406f LB |
1504 | crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[41] ^ |
1505 | mac_array[39] ^ mac_array[36] ^ mac_array[35] ^ mac_array[31] ^ | |
1506 | mac_array[30] ^ mac_array[27] ^ mac_array[26] ^ mac_array[24] ^ | |
1507 | mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ mac_array[14] ^ | |
1508 | mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ mac_array[4] ^ | |
1509 | mac_array[3] ^ mac_array[2]; | |
c8aaea25 | 1510 | |
c9df406f LB |
1511 | crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ mac_array[42] ^ |
1512 | mac_array[40] ^ mac_array[37] ^ mac_array[36] ^ mac_array[32] ^ | |
1513 | mac_array[31] ^ mac_array[28] ^ mac_array[27] ^ mac_array[25] ^ | |
1514 | mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ mac_array[15] ^ | |
1515 | mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[5] ^ | |
1516 | mac_array[4] ^ mac_array[3]; | |
c8aaea25 | 1517 | |
c9df406f LB |
1518 | crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ mac_array[41] ^ |
1519 | mac_array[38] ^ mac_array[37] ^ mac_array[33] ^ mac_array[32] ^ | |
1520 | mac_array[29] ^ mac_array[28] ^ mac_array[26] ^ mac_array[21] ^ | |
1521 | mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ mac_array[14] ^ | |
1522 | mac_array[12] ^ mac_array[10] ^ mac_array[6] ^ mac_array[5] ^ | |
1523 | mac_array[4]; | |
c8aaea25 | 1524 | |
c9df406f LB |
1525 | crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ mac_array[39] ^ |
1526 | mac_array[38] ^ mac_array[34] ^ mac_array[33] ^ mac_array[30] ^ | |
1527 | mac_array[29] ^ mac_array[27] ^ mac_array[22] ^ mac_array[20] ^ | |
1528 | mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ mac_array[13] ^ | |
1529 | mac_array[11] ^ mac_array[7] ^ mac_array[6] ^ mac_array[5]; | |
c8aaea25 | 1530 | |
c9df406f LB |
1531 | for (i = 0; i < 8; i++) |
1532 | crc_result = crc_result | (crc[i] << i); | |
1533 | ||
3cb4667c | 1534 | table = OTHER_MCAST_TABLE(port_num); |
c9df406f | 1535 | eth_port_set_filter_table_entry(mp, table, crc_result); |
c8aaea25 DF |
1536 | } |
1537 | ||
c9df406f LB |
1538 | /* |
1539 | * Set the entire multicast list based on dev->mc_list. | |
1da177e4 | 1540 | */ |
c9df406f | 1541 | static void eth_port_set_multicast_list(struct net_device *dev) |
1da177e4 | 1542 | { |
1da177e4 | 1543 | |
c9df406f LB |
1544 | struct dev_mc_list *mc_list; |
1545 | int i; | |
1546 | int table_index; | |
1547 | struct mv643xx_private *mp = netdev_priv(dev); | |
1548 | unsigned int eth_port_num = mp->port_num; | |
c8aaea25 | 1549 | |
c9df406f LB |
1550 | /* If the device is in promiscuous mode or in all multicast mode, |
1551 | * we will fully populate both multicast tables with accept. | |
1552 | * This is guaranteed to yield a match on all multicast addresses... | |
1553 | */ | |
1554 | if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) { | |
1555 | for (table_index = 0; table_index <= 0xFC; table_index += 4) { | |
1556 | /* Set all entries in DA filter special multicast | |
1557 | * table (Ex_dFSMT) | |
1558 | * Set for ETH_Q0 for now | |
1559 | * Bits | |
1560 | * 0 Accept=1, Drop=0 | |
1561 | * 3-1 Queue ETH_Q0=0 | |
1562 | * 7-4 Reserved = 0; | |
1563 | */ | |
3cb4667c | 1564 | wrl(mp, SPECIAL_MCAST_TABLE(eth_port_num) + table_index, 0x01010101); |
c8aaea25 | 1565 | |
c9df406f LB |
1566 | /* Set all entries in DA filter other multicast |
1567 | * table (Ex_dFOMT) | |
1568 | * Set for ETH_Q0 for now | |
1569 | * Bits | |
1570 | * 0 Accept=1, Drop=0 | |
1571 | * 3-1 Queue ETH_Q0=0 | |
1572 | * 7-4 Reserved = 0; | |
1573 | */ | |
3cb4667c | 1574 | wrl(mp, OTHER_MCAST_TABLE(eth_port_num) + table_index, 0x01010101); |
c9df406f LB |
1575 | } |
1576 | return; | |
1577 | } | |
c8aaea25 | 1578 | |
c9df406f LB |
1579 | /* We will clear out multicast tables every time we get the list. |
1580 | * Then add the entire new list... | |
1581 | */ | |
1582 | for (table_index = 0; table_index <= 0xFC; table_index += 4) { | |
1583 | /* Clear DA filter special multicast table (Ex_dFSMT) */ | |
3cb4667c | 1584 | wrl(mp, SPECIAL_MCAST_TABLE(eth_port_num) + table_index, 0); |
c9df406f LB |
1585 | |
1586 | /* Clear DA filter other multicast table (Ex_dFOMT) */ | |
3cb4667c | 1587 | wrl(mp, OTHER_MCAST_TABLE(eth_port_num) + table_index, 0); |
1da177e4 LT |
1588 | } |
1589 | ||
c9df406f LB |
1590 | /* Get pointer to net_device multicast list and add each one... */ |
1591 | for (i = 0, mc_list = dev->mc_list; | |
1592 | (i < 256) && (mc_list != NULL) && (i < dev->mc_count); | |
1593 | i++, mc_list = mc_list->next) | |
1594 | if (mc_list->dmi_addrlen == 6) | |
1595 | eth_port_mc_addr(mp, mc_list->dmi_addr); | |
324ff2c1 BB |
1596 | } |
1597 | ||
c9df406f LB |
1598 | /* |
1599 | * mv643xx_eth_set_rx_mode | |
c8aaea25 | 1600 | * |
c9df406f LB |
1601 | * Change from promiscuos to regular rx mode |
1602 | * | |
1603 | * Input : pointer to ethernet interface network device structure | |
1604 | * Output : N/A | |
c8aaea25 | 1605 | */ |
c9df406f | 1606 | static void mv643xx_eth_set_rx_mode(struct net_device *dev) |
c8aaea25 | 1607 | { |
c9df406f LB |
1608 | struct mv643xx_private *mp = netdev_priv(dev); |
1609 | u32 config_reg; | |
1da177e4 | 1610 | |
3cb4667c | 1611 | config_reg = rdl(mp, PORT_CONFIG(mp->port_num)); |
c9df406f | 1612 | if (dev->flags & IFF_PROMISC) |
d9a073ea | 1613 | config_reg |= UNICAST_PROMISCUOUS_MODE; |
c9df406f | 1614 | else |
d9a073ea | 1615 | config_reg &= ~UNICAST_PROMISCUOUS_MODE; |
3cb4667c | 1616 | wrl(mp, PORT_CONFIG(mp->port_num), config_reg); |
1da177e4 | 1617 | |
c9df406f LB |
1618 | eth_port_set_multicast_list(dev); |
1619 | } | |
c8aaea25 | 1620 | |
c8aaea25 | 1621 | |
c9df406f LB |
1622 | /* rx/tx queue initialisation ***********************************************/ |
1623 | /* | |
1624 | * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory. | |
1625 | * | |
1626 | * DESCRIPTION: | |
1627 | * This function prepares a Rx chained list of descriptors and packet | |
1628 | * buffers in a form of a ring. The routine must be called after port | |
1629 | * initialization routine and before port start routine. | |
1630 | * The Ethernet SDMA engine uses CPU bus addresses to access the various | |
1631 | * devices in the system (i.e. DRAM). This function uses the ethernet | |
1632 | * struct 'virtual to physical' routine (set by the user) to set the ring | |
1633 | * with physical addresses. | |
1634 | * | |
1635 | * INPUT: | |
1636 | * struct mv643xx_private *mp Ethernet Port Control srtuct. | |
1637 | * | |
1638 | * OUTPUT: | |
1639 | * The routine updates the Ethernet port control struct with information | |
1640 | * regarding the Rx descriptors and buffers. | |
1641 | * | |
1642 | * RETURN: | |
1643 | * None. | |
1644 | */ | |
1645 | static void ether_init_rx_desc_ring(struct mv643xx_private *mp) | |
1646 | { | |
1647 | volatile struct eth_rx_desc *p_rx_desc; | |
1648 | int rx_desc_num = mp->rx_ring_size; | |
1649 | int i; | |
1650 | ||
1651 | /* initialize the next_desc_ptr links in the Rx descriptors ring */ | |
1652 | p_rx_desc = (struct eth_rx_desc *)mp->p_rx_desc_area; | |
1653 | for (i = 0; i < rx_desc_num; i++) { | |
1654 | p_rx_desc[i].next_desc_ptr = mp->rx_desc_dma + | |
1655 | ((i + 1) % rx_desc_num) * sizeof(struct eth_rx_desc); | |
f7ea3337 PJ |
1656 | } |
1657 | ||
c9df406f LB |
1658 | /* Save Rx desc pointer to driver struct. */ |
1659 | mp->rx_curr_desc_q = 0; | |
1660 | mp->rx_used_desc_q = 0; | |
1da177e4 | 1661 | |
c9df406f LB |
1662 | mp->rx_desc_area_size = rx_desc_num * sizeof(struct eth_rx_desc); |
1663 | } | |
c8aaea25 | 1664 | |
c9df406f LB |
1665 | static void mv643xx_eth_free_rx_rings(struct net_device *dev) |
1666 | { | |
1667 | struct mv643xx_private *mp = netdev_priv(dev); | |
1668 | int curr; | |
c8aaea25 | 1669 | |
c9df406f LB |
1670 | /* Stop RX Queues */ |
1671 | mv643xx_eth_port_disable_rx(mp); | |
1672 | ||
1673 | /* Free preallocated skb's on RX rings */ | |
1674 | for (curr = 0; mp->rx_desc_count && curr < mp->rx_ring_size; curr++) { | |
1675 | if (mp->rx_skb[curr]) { | |
1676 | dev_kfree_skb(mp->rx_skb[curr]); | |
1677 | mp->rx_desc_count--; | |
1da177e4 | 1678 | } |
c8aaea25 | 1679 | } |
1da177e4 | 1680 | |
c9df406f LB |
1681 | if (mp->rx_desc_count) |
1682 | printk(KERN_ERR | |
1683 | "%s: Error in freeing Rx Ring. %d skb's still" | |
1684 | " stuck in RX Ring - ignoring them\n", dev->name, | |
1685 | mp->rx_desc_count); | |
1686 | /* Free RX ring */ | |
1687 | if (mp->rx_sram_size) | |
1688 | iounmap(mp->p_rx_desc_area); | |
1689 | else | |
1690 | dma_free_coherent(NULL, mp->rx_desc_area_size, | |
1691 | mp->p_rx_desc_area, mp->rx_desc_dma); | |
1692 | } | |
1da177e4 | 1693 | |
c9df406f LB |
1694 | /* |
1695 | * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory. | |
1696 | * | |
1697 | * DESCRIPTION: | |
1698 | * This function prepares a Tx chained list of descriptors and packet | |
1699 | * buffers in a form of a ring. The routine must be called after port | |
1700 | * initialization routine and before port start routine. | |
1701 | * The Ethernet SDMA engine uses CPU bus addresses to access the various | |
1702 | * devices in the system (i.e. DRAM). This function uses the ethernet | |
1703 | * struct 'virtual to physical' routine (set by the user) to set the ring | |
1704 | * with physical addresses. | |
1705 | * | |
1706 | * INPUT: | |
1707 | * struct mv643xx_private *mp Ethernet Port Control srtuct. | |
1708 | * | |
1709 | * OUTPUT: | |
1710 | * The routine updates the Ethernet port control struct with information | |
1711 | * regarding the Tx descriptors and buffers. | |
1712 | * | |
1713 | * RETURN: | |
1714 | * None. | |
1715 | */ | |
1716 | static void ether_init_tx_desc_ring(struct mv643xx_private *mp) | |
1717 | { | |
1718 | int tx_desc_num = mp->tx_ring_size; | |
1719 | struct eth_tx_desc *p_tx_desc; | |
1720 | int i; | |
1da177e4 | 1721 | |
c9df406f LB |
1722 | /* Initialize the next_desc_ptr links in the Tx descriptors ring */ |
1723 | p_tx_desc = (struct eth_tx_desc *)mp->p_tx_desc_area; | |
1724 | for (i = 0; i < tx_desc_num; i++) { | |
1725 | p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma + | |
1726 | ((i + 1) % tx_desc_num) * sizeof(struct eth_tx_desc); | |
1727 | } | |
1728 | ||
1729 | mp->tx_curr_desc_q = 0; | |
1730 | mp->tx_used_desc_q = 0; | |
1731 | ||
1732 | mp->tx_desc_area_size = tx_desc_num * sizeof(struct eth_tx_desc); | |
c8aaea25 | 1733 | } |
1da177e4 | 1734 | |
c8aaea25 | 1735 | /** |
c9df406f | 1736 | * mv643xx_eth_free_tx_descs - Free the tx desc data for completed descriptors |
c8aaea25 | 1737 | * |
c9df406f | 1738 | * If force is non-zero, frees uncompleted descriptors as well |
c8aaea25 | 1739 | */ |
c9df406f | 1740 | static int mv643xx_eth_free_tx_descs(struct net_device *dev, int force) |
c8aaea25 DF |
1741 | { |
1742 | struct mv643xx_private *mp = netdev_priv(dev); | |
c9df406f LB |
1743 | struct eth_tx_desc *desc; |
1744 | u32 cmd_sts; | |
1745 | struct sk_buff *skb; | |
c8aaea25 | 1746 | unsigned long flags; |
c9df406f LB |
1747 | int tx_index; |
1748 | dma_addr_t addr; | |
1749 | int count; | |
1750 | int released = 0; | |
1da177e4 | 1751 | |
c9df406f LB |
1752 | while (mp->tx_desc_count > 0) { |
1753 | spin_lock_irqsave(&mp->lock, flags); | |
94843566 | 1754 | |
c9df406f LB |
1755 | /* tx_desc_count might have changed before acquiring the lock */ |
1756 | if (mp->tx_desc_count <= 0) { | |
1757 | spin_unlock_irqrestore(&mp->lock, flags); | |
1758 | return released; | |
1759 | } | |
4d64e718 | 1760 | |
c9df406f LB |
1761 | tx_index = mp->tx_used_desc_q; |
1762 | desc = &mp->p_tx_desc_area[tx_index]; | |
1763 | cmd_sts = desc->cmd_sts; | |
4d64e718 | 1764 | |
c9df406f LB |
1765 | if (!force && (cmd_sts & ETH_BUFFER_OWNED_BY_DMA)) { |
1766 | spin_unlock_irqrestore(&mp->lock, flags); | |
1767 | return released; | |
1768 | } | |
1da177e4 | 1769 | |
c9df406f LB |
1770 | mp->tx_used_desc_q = (tx_index + 1) % mp->tx_ring_size; |
1771 | mp->tx_desc_count--; | |
1da177e4 | 1772 | |
c9df406f LB |
1773 | addr = desc->buf_ptr; |
1774 | count = desc->byte_cnt; | |
1775 | skb = mp->tx_skb[tx_index]; | |
1776 | if (skb) | |
1777 | mp->tx_skb[tx_index] = NULL; | |
c8aaea25 | 1778 | |
c9df406f LB |
1779 | if (cmd_sts & ETH_ERROR_SUMMARY) { |
1780 | printk("%s: Error in TX\n", dev->name); | |
1781 | dev->stats.tx_errors++; | |
1782 | } | |
1da177e4 | 1783 | |
c9df406f | 1784 | spin_unlock_irqrestore(&mp->lock, flags); |
1da177e4 | 1785 | |
c9df406f LB |
1786 | if (cmd_sts & ETH_TX_FIRST_DESC) |
1787 | dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE); | |
1788 | else | |
1789 | dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE); | |
c2e5b352 | 1790 | |
c9df406f LB |
1791 | if (skb) |
1792 | dev_kfree_skb_irq(skb); | |
63c9e549 | 1793 | |
c9df406f LB |
1794 | released = 1; |
1795 | } | |
c2e5b352 | 1796 | |
c9df406f | 1797 | return released; |
63c9e549 | 1798 | } |
63c9e549 | 1799 | |
c9df406f | 1800 | static void mv643xx_eth_free_completed_tx_descs(struct net_device *dev) |
d0412d96 JC |
1801 | { |
1802 | struct mv643xx_private *mp = netdev_priv(dev); | |
1803 | ||
c9df406f LB |
1804 | if (mv643xx_eth_free_tx_descs(dev, 0) && |
1805 | mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB) | |
1806 | netif_wake_queue(dev); | |
d0412d96 JC |
1807 | } |
1808 | ||
c9df406f | 1809 | static void mv643xx_eth_free_all_tx_descs(struct net_device *dev) |
1da177e4 | 1810 | { |
c9df406f LB |
1811 | mv643xx_eth_free_tx_descs(dev, 1); |
1812 | } | |
1da177e4 | 1813 | |
c9df406f LB |
1814 | static void mv643xx_eth_free_tx_rings(struct net_device *dev) |
1815 | { | |
1816 | struct mv643xx_private *mp = netdev_priv(dev); | |
84dd619e | 1817 | |
c9df406f LB |
1818 | /* Stop Tx Queues */ |
1819 | mv643xx_eth_port_disable_tx(mp); | |
fa3959f4 | 1820 | |
c9df406f LB |
1821 | /* Free outstanding skb's on TX ring */ |
1822 | mv643xx_eth_free_all_tx_descs(dev); | |
1da177e4 | 1823 | |
c9df406f | 1824 | BUG_ON(mp->tx_used_desc_q != mp->tx_curr_desc_q); |
1da177e4 | 1825 | |
c9df406f LB |
1826 | /* Free TX ring */ |
1827 | if (mp->tx_sram_size) | |
1828 | iounmap(mp->p_tx_desc_area); | |
1829 | else | |
1830 | dma_free_coherent(NULL, mp->tx_desc_area_size, | |
1831 | mp->p_tx_desc_area, mp->tx_desc_dma); | |
1832 | } | |
1da177e4 | 1833 | |
1da177e4 | 1834 | |
c9df406f LB |
1835 | /* netdev ops and related ***************************************************/ |
1836 | static void eth_port_reset(struct mv643xx_private *mp); | |
1da177e4 | 1837 | |
c9df406f LB |
1838 | /* Set the mv643xx port configuration register for the speed/duplex mode. */ |
1839 | static void mv643xx_eth_update_pscr(struct net_device *dev, | |
1840 | struct ethtool_cmd *ecmd) | |
1841 | { | |
1842 | struct mv643xx_private *mp = netdev_priv(dev); | |
1843 | int port_num = mp->port_num; | |
1844 | u32 o_pscr, n_pscr; | |
1845 | unsigned int queues; | |
1da177e4 | 1846 | |
3cb4667c | 1847 | o_pscr = rdl(mp, PORT_SERIAL_CONTROL(port_num)); |
c9df406f | 1848 | n_pscr = o_pscr; |
63c9e549 | 1849 | |
c9df406f LB |
1850 | /* clear speed, duplex and rx buffer size fields */ |
1851 | n_pscr &= ~(SET_MII_SPEED_TO_100 | | |
1852 | SET_GMII_SPEED_TO_1000 | | |
1853 | SET_FULL_DUPLEX_MODE | | |
1854 | MAX_RX_PACKET_MASK); | |
1da177e4 | 1855 | |
c9df406f LB |
1856 | if (ecmd->duplex == DUPLEX_FULL) |
1857 | n_pscr |= SET_FULL_DUPLEX_MODE; | |
1da177e4 | 1858 | |
c9df406f LB |
1859 | if (ecmd->speed == SPEED_1000) |
1860 | n_pscr |= SET_GMII_SPEED_TO_1000 | | |
1861 | MAX_RX_PACKET_9700BYTE; | |
1862 | else { | |
1863 | if (ecmd->speed == SPEED_100) | |
1864 | n_pscr |= SET_MII_SPEED_TO_100; | |
1865 | n_pscr |= MAX_RX_PACKET_1522BYTE; | |
1866 | } | |
1da177e4 | 1867 | |
c9df406f LB |
1868 | if (n_pscr != o_pscr) { |
1869 | if ((o_pscr & SERIAL_PORT_ENABLE) == 0) | |
3cb4667c | 1870 | wrl(mp, PORT_SERIAL_CONTROL(port_num), n_pscr); |
c9df406f LB |
1871 | else { |
1872 | queues = mv643xx_eth_port_disable_tx(mp); | |
1da177e4 | 1873 | |
c9df406f | 1874 | o_pscr &= ~SERIAL_PORT_ENABLE; |
3cb4667c LB |
1875 | wrl(mp, PORT_SERIAL_CONTROL(port_num), o_pscr); |
1876 | wrl(mp, PORT_SERIAL_CONTROL(port_num), n_pscr); | |
1877 | wrl(mp, PORT_SERIAL_CONTROL(port_num), n_pscr); | |
c9df406f LB |
1878 | if (queues) |
1879 | mv643xx_eth_port_enable_tx(mp, queues); | |
1880 | } | |
1881 | } | |
1882 | } | |
84dd619e | 1883 | |
c9df406f LB |
1884 | /* |
1885 | * mv643xx_eth_int_handler | |
1886 | * | |
1887 | * Main interrupt handler for the gigbit ethernet ports | |
1888 | * | |
1889 | * Input : irq - irq number (not used) | |
1890 | * dev_id - a pointer to the required interface's data structure | |
1891 | * regs - not used | |
1892 | * Output : N/A | |
1893 | */ | |
f2ce825d | 1894 | |
c9df406f LB |
1895 | static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id) |
1896 | { | |
1897 | struct net_device *dev = (struct net_device *)dev_id; | |
1898 | struct mv643xx_private *mp = netdev_priv(dev); | |
1899 | u32 eth_int_cause, eth_int_cause_ext = 0; | |
1900 | unsigned int port_num = mp->port_num; | |
ce4e2e45 | 1901 | |
c9df406f | 1902 | /* Read interrupt cause registers */ |
073a345c LB |
1903 | eth_int_cause = rdl(mp, INT_CAUSE(port_num)) & (INT_RX | INT_EXT); |
1904 | if (eth_int_cause & INT_EXT) { | |
3cb4667c | 1905 | eth_int_cause_ext = rdl(mp, INT_CAUSE_EXT(port_num)) |
073a345c | 1906 | & (INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX); |
3cb4667c | 1907 | wrl(mp, INT_CAUSE_EXT(port_num), ~eth_int_cause_ext); |
c9df406f | 1908 | } |
1da177e4 | 1909 | |
c9df406f | 1910 | /* PHY status changed */ |
073a345c | 1911 | if (eth_int_cause_ext & (INT_EXT_LINK | INT_EXT_PHY)) { |
c9df406f | 1912 | struct ethtool_cmd cmd; |
1da177e4 | 1913 | |
c9df406f LB |
1914 | if (mii_link_ok(&mp->mii)) { |
1915 | mii_ethtool_gset(&mp->mii, &cmd); | |
1916 | mv643xx_eth_update_pscr(dev, &cmd); | |
073a345c | 1917 | mv643xx_eth_port_enable_tx(mp, 1); |
c9df406f LB |
1918 | if (!netif_carrier_ok(dev)) { |
1919 | netif_carrier_on(dev); | |
1920 | if (mp->tx_ring_size - mp->tx_desc_count >= | |
1921 | MAX_DESCS_PER_SKB) | |
1922 | netif_wake_queue(dev); | |
1923 | } | |
1924 | } else if (netif_carrier_ok(dev)) { | |
1925 | netif_stop_queue(dev); | |
1926 | netif_carrier_off(dev); | |
1927 | } | |
1928 | } | |
1da177e4 | 1929 | |
c9df406f | 1930 | #ifdef MV643XX_NAPI |
073a345c | 1931 | if (eth_int_cause & INT_RX) { |
c9df406f | 1932 | /* schedule the NAPI poll routine to maintain port */ |
073a345c | 1933 | wrl(mp, INT_MASK(port_num), 0x00000000); |
1da177e4 | 1934 | |
c9df406f | 1935 | /* wait for previous write to complete */ |
3cb4667c | 1936 | rdl(mp, INT_MASK(port_num)); |
1da177e4 | 1937 | |
c9df406f | 1938 | netif_rx_schedule(dev, &mp->napi); |
84dd619e | 1939 | } |
c9df406f | 1940 | #else |
073a345c | 1941 | if (eth_int_cause & INT_RX) |
c9df406f LB |
1942 | mv643xx_eth_receive_queue(dev, INT_MAX); |
1943 | #endif | |
073a345c | 1944 | if (eth_int_cause_ext & INT_EXT_TX) |
c9df406f | 1945 | mv643xx_eth_free_completed_tx_descs(dev); |
1da177e4 | 1946 | |
f2ce825d | 1947 | /* |
c9df406f LB |
1948 | * If no real interrupt occured, exit. |
1949 | * This can happen when using gigE interrupt coalescing mechanism. | |
f2ce825d | 1950 | */ |
c9df406f LB |
1951 | if ((eth_int_cause == 0x0) && (eth_int_cause_ext == 0x0)) |
1952 | return IRQ_NONE; | |
1da177e4 | 1953 | |
c9df406f | 1954 | return IRQ_HANDLED; |
1da177e4 LT |
1955 | } |
1956 | ||
1da177e4 | 1957 | /* |
c9df406f | 1958 | * ethernet_phy_reset - Reset Ethernet port PHY. |
1da177e4 LT |
1959 | * |
1960 | * DESCRIPTION: | |
c9df406f | 1961 | * This routine utilizes the SMI interface to reset the ethernet port PHY. |
1da177e4 LT |
1962 | * |
1963 | * INPUT: | |
c9df406f | 1964 | * struct mv643xx_private *mp Ethernet Port. |
1da177e4 LT |
1965 | * |
1966 | * OUTPUT: | |
c9df406f | 1967 | * The PHY is reset. |
1da177e4 LT |
1968 | * |
1969 | * RETURN: | |
1970 | * None. | |
c9df406f | 1971 | * |
1da177e4 | 1972 | */ |
c9df406f | 1973 | static void ethernet_phy_reset(struct mv643xx_private *mp) |
1da177e4 | 1974 | { |
c9df406f | 1975 | unsigned int phy_reg_data; |
1da177e4 | 1976 | |
c9df406f LB |
1977 | /* Reset the PHY */ |
1978 | eth_port_read_smi_reg(mp, 0, &phy_reg_data); | |
1979 | phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */ | |
1980 | eth_port_write_smi_reg(mp, 0, phy_reg_data); | |
1da177e4 | 1981 | |
c9df406f LB |
1982 | /* wait for PHY to come out of reset */ |
1983 | do { | |
1984 | udelay(1); | |
1985 | eth_port_read_smi_reg(mp, 0, &phy_reg_data); | |
1986 | } while (phy_reg_data & 0x8000); | |
1da177e4 LT |
1987 | } |
1988 | ||
1989 | /* | |
1990 | * eth_port_start - Start the Ethernet port activity. | |
1991 | * | |
1992 | * DESCRIPTION: | |
1993 | * This routine prepares the Ethernet port for Rx and Tx activity: | |
1994 | * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that | |
1995 | * has been initialized a descriptor's ring (using | |
1996 | * ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx) | |
1997 | * 2. Initialize and enable the Ethernet configuration port by writing to | |
1998 | * the port's configuration and command registers. | |
1999 | * 3. Initialize and enable the SDMA by writing to the SDMA's | |
2000 | * configuration and command registers. After completing these steps, | |
2001 | * the ethernet port SDMA can starts to perform Rx and Tx activities. | |
2002 | * | |
2003 | * Note: Each Rx and Tx queue descriptor's list must be initialized prior | |
2004 | * to calling this function (use ether_init_tx_desc_ring for Tx queues | |
2005 | * and ether_init_rx_desc_ring for Rx queues). | |
2006 | * | |
2007 | * INPUT: | |
ed9b5d45 | 2008 | * dev - a pointer to the required interface |
1da177e4 LT |
2009 | * |
2010 | * OUTPUT: | |
2011 | * Ethernet port is ready to receive and transmit. | |
2012 | * | |
2013 | * RETURN: | |
2014 | * None. | |
2015 | */ | |
ed9b5d45 | 2016 | static void eth_port_start(struct net_device *dev) |
1da177e4 | 2017 | { |
ed9b5d45 | 2018 | struct mv643xx_private *mp = netdev_priv(dev); |
1da177e4 LT |
2019 | unsigned int port_num = mp->port_num; |
2020 | int tx_curr_desc, rx_curr_desc; | |
d0412d96 JC |
2021 | u32 pscr; |
2022 | struct ethtool_cmd ethtool_cmd; | |
1da177e4 LT |
2023 | |
2024 | /* Assignment of Tx CTRP of given queue */ | |
2025 | tx_curr_desc = mp->tx_curr_desc_q; | |
3cb4667c | 2026 | wrl(mp, TXQ_CURRENT_DESC_PTR(port_num), |
1da177e4 LT |
2027 | (u32)((struct eth_tx_desc *)mp->tx_desc_dma + tx_curr_desc)); |
2028 | ||
2029 | /* Assignment of Rx CRDP of given queue */ | |
2030 | rx_curr_desc = mp->rx_curr_desc_q; | |
3cb4667c | 2031 | wrl(mp, RXQ_CURRENT_DESC_PTR(port_num), |
1da177e4 LT |
2032 | (u32)((struct eth_rx_desc *)mp->rx_desc_dma + rx_curr_desc)); |
2033 | ||
2034 | /* Add the assigned Ethernet address to the port's address table */ | |
afdb57a2 | 2035 | eth_port_uc_addr_set(mp, dev->dev_addr); |
1da177e4 | 2036 | |
d9a073ea LB |
2037 | /* |
2038 | * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast | |
2039 | * frames to RX queue #0. | |
2040 | */ | |
2041 | wrl(mp, PORT_CONFIG(port_num), 0x00000000); | |
01999873 | 2042 | |
376489a2 LB |
2043 | /* |
2044 | * Treat BPDUs as normal multicasts, and disable partition mode. | |
2045 | */ | |
2046 | wrl(mp, PORT_CONFIG_EXT(port_num), 0x00000000); | |
1da177e4 | 2047 | |
3cb4667c | 2048 | pscr = rdl(mp, PORT_SERIAL_CONTROL(port_num)); |
01999873 | 2049 | |
e4d00fa9 | 2050 | pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS); |
3cb4667c | 2051 | wrl(mp, PORT_SERIAL_CONTROL(port_num), pscr); |
1da177e4 | 2052 | |
e4d00fa9 LB |
2053 | pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL | |
2054 | DISABLE_AUTO_NEG_SPEED_GMII | | |
2beff77b | 2055 | DISABLE_AUTO_NEG_FOR_DUPLEX | |
e4d00fa9 LB |
2056 | DO_NOT_FORCE_LINK_FAIL | |
2057 | SERIAL_PORT_CONTROL_RESERVED; | |
1da177e4 | 2058 | |
3cb4667c | 2059 | wrl(mp, PORT_SERIAL_CONTROL(port_num), pscr); |
1da177e4 | 2060 | |
e4d00fa9 | 2061 | pscr |= SERIAL_PORT_ENABLE; |
3cb4667c | 2062 | wrl(mp, PORT_SERIAL_CONTROL(port_num), pscr); |
1da177e4 LT |
2063 | |
2064 | /* Assign port SDMA configuration */ | |
3cb4667c | 2065 | wrl(mp, SDMA_CONFIG(port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE); |
1da177e4 LT |
2066 | |
2067 | /* Enable port Rx. */ | |
073a345c | 2068 | mv643xx_eth_port_enable_rx(mp, 1); |
8f543718 DF |
2069 | |
2070 | /* Disable port bandwidth limits by clearing MTU register */ | |
3cb4667c | 2071 | wrl(mp, TX_BW_MTU(port_num), 0); |
d0412d96 JC |
2072 | |
2073 | /* save phy settings across reset */ | |
2074 | mv643xx_get_settings(dev, ðtool_cmd); | |
afdb57a2 | 2075 | ethernet_phy_reset(mp); |
d0412d96 | 2076 | mv643xx_set_settings(dev, ðtool_cmd); |
1da177e4 LT |
2077 | } |
2078 | ||
c9df406f LB |
2079 | #ifdef MV643XX_COAL |
2080 | ||
1da177e4 | 2081 | /* |
c9df406f LB |
2082 | * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path |
2083 | * | |
2084 | * DESCRIPTION: | |
2085 | * This routine sets the RX coalescing interrupt mechanism parameter. | |
2086 | * This parameter is a timeout counter, that counts in 64 t_clk | |
2087 | * chunks ; that when timeout event occurs a maskable interrupt | |
2088 | * occurs. | |
2089 | * The parameter is calculated using the tClk of the MV-643xx chip | |
2090 | * , and the required delay of the interrupt in usec. | |
2091 | * | |
2092 | * INPUT: | |
2093 | * struct mv643xx_private *mp Ethernet port | |
2094 | * unsigned int delay Delay in usec | |
2095 | * | |
2096 | * OUTPUT: | |
2097 | * Interrupt coalescing mechanism value is set in MV-643xx chip. | |
2098 | * | |
2099 | * RETURN: | |
2100 | * The interrupt coalescing value set in the gigE port. | |
2101 | * | |
1da177e4 | 2102 | */ |
c9df406f LB |
2103 | static unsigned int eth_port_set_rx_coal(struct mv643xx_private *mp, |
2104 | unsigned int delay) | |
1da177e4 | 2105 | { |
afdb57a2 | 2106 | unsigned int port_num = mp->port_num; |
c9df406f | 2107 | unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64; |
1da177e4 | 2108 | |
c9df406f | 2109 | /* Set RX Coalescing mechanism */ |
3cb4667c | 2110 | wrl(mp, SDMA_CONFIG(port_num), |
c9df406f | 2111 | ((coal & 0x3fff) << 8) | |
3cb4667c | 2112 | (rdl(mp, SDMA_CONFIG(port_num)) |
c9df406f | 2113 | & 0xffc000ff)); |
1da177e4 | 2114 | |
c9df406f | 2115 | return coal; |
1da177e4 | 2116 | } |
c9df406f | 2117 | #endif |
1da177e4 LT |
2118 | |
2119 | /* | |
c9df406f LB |
2120 | * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path |
2121 | * | |
2122 | * DESCRIPTION: | |
2123 | * This routine sets the TX coalescing interrupt mechanism parameter. | |
2124 | * This parameter is a timeout counter, that counts in 64 t_clk | |
2125 | * chunks ; that when timeout event occurs a maskable interrupt | |
2126 | * occurs. | |
2127 | * The parameter is calculated using the t_cLK frequency of the | |
2128 | * MV-643xx chip and the required delay in the interrupt in uSec | |
2129 | * | |
2130 | * INPUT: | |
2131 | * struct mv643xx_private *mp Ethernet port | |
2132 | * unsigned int delay Delay in uSeconds | |
2133 | * | |
2134 | * OUTPUT: | |
2135 | * Interrupt coalescing mechanism value is set in MV-643xx chip. | |
2136 | * | |
2137 | * RETURN: | |
2138 | * The interrupt coalescing value set in the gigE port. | |
2139 | * | |
1da177e4 | 2140 | */ |
c9df406f LB |
2141 | static unsigned int eth_port_set_tx_coal(struct mv643xx_private *mp, |
2142 | unsigned int delay) | |
1da177e4 | 2143 | { |
c9df406f | 2144 | unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64; |
1da177e4 | 2145 | |
c9df406f | 2146 | /* Set TX Coalescing mechanism */ |
3cb4667c | 2147 | wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), coal << 4); |
1da177e4 | 2148 | |
c9df406f | 2149 | return coal; |
1da177e4 LT |
2150 | } |
2151 | ||
16e03018 | 2152 | /* |
c9df406f LB |
2153 | * eth_port_init - Initialize the Ethernet port driver |
2154 | * | |
2155 | * DESCRIPTION: | |
2156 | * This function prepares the ethernet port to start its activity: | |
2157 | * 1) Completes the ethernet port driver struct initialization toward port | |
2158 | * start routine. | |
2159 | * 2) Resets the device to a quiescent state in case of warm reboot. | |
2160 | * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM. | |
2161 | * 4) Clean MAC tables. The reset status of those tables is unknown. | |
2162 | * 5) Set PHY address. | |
2163 | * Note: Call this routine prior to eth_port_start routine and after | |
2164 | * setting user values in the user fields of Ethernet port control | |
2165 | * struct. | |
2166 | * | |
2167 | * INPUT: | |
2168 | * struct mv643xx_private *mp Ethernet port control struct | |
2169 | * | |
2170 | * OUTPUT: | |
2171 | * See description. | |
2172 | * | |
2173 | * RETURN: | |
2174 | * None. | |
16e03018 | 2175 | */ |
c9df406f | 2176 | static void eth_port_init(struct mv643xx_private *mp) |
16e03018 | 2177 | { |
c9df406f | 2178 | mp->rx_resource_err = 0; |
16e03018 | 2179 | |
c9df406f | 2180 | eth_port_reset(mp); |
16e03018 | 2181 | |
c9df406f | 2182 | eth_port_init_mac_tables(mp); |
16e03018 DF |
2183 | } |
2184 | ||
2185 | /* | |
c9df406f | 2186 | * mv643xx_eth_open |
16e03018 | 2187 | * |
c9df406f LB |
2188 | * This function is called when openning the network device. The function |
2189 | * should initialize all the hardware, initialize cyclic Rx/Tx | |
2190 | * descriptors chain and buffers and allocate an IRQ to the network | |
2191 | * device. | |
2192 | * | |
2193 | * Input : a pointer to the network device structure | |
2194 | * | |
2195 | * Output : zero of success , nonzero if fails. | |
16e03018 | 2196 | */ |
c9df406f LB |
2197 | |
2198 | static int mv643xx_eth_open(struct net_device *dev) | |
16e03018 | 2199 | { |
c9df406f | 2200 | struct mv643xx_private *mp = netdev_priv(dev); |
afdb57a2 | 2201 | unsigned int port_num = mp->port_num; |
c9df406f LB |
2202 | unsigned int size; |
2203 | int err; | |
16e03018 | 2204 | |
c9df406f | 2205 | /* Clear any pending ethernet port interrupts */ |
3cb4667c LB |
2206 | wrl(mp, INT_CAUSE(port_num), 0); |
2207 | wrl(mp, INT_CAUSE_EXT(port_num), 0); | |
c9df406f | 2208 | /* wait for previous write to complete */ |
3cb4667c | 2209 | rdl(mp, INT_CAUSE_EXT(port_num)); |
c9df406f LB |
2210 | |
2211 | err = request_irq(dev->irq, mv643xx_eth_int_handler, | |
2212 | IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev); | |
2213 | if (err) { | |
2214 | printk(KERN_ERR "%s: Can not assign IRQ\n", dev->name); | |
2215 | return -EAGAIN; | |
16e03018 DF |
2216 | } |
2217 | ||
c9df406f | 2218 | eth_port_init(mp); |
16e03018 | 2219 | |
c9df406f LB |
2220 | memset(&mp->timeout, 0, sizeof(struct timer_list)); |
2221 | mp->timeout.function = mv643xx_eth_rx_refill_descs_timer_wrapper; | |
2222 | mp->timeout.data = (unsigned long)dev; | |
16e03018 | 2223 | |
c9df406f LB |
2224 | /* Allocate RX and TX skb rings */ |
2225 | mp->rx_skb = kmalloc(sizeof(*mp->rx_skb) * mp->rx_ring_size, | |
2226 | GFP_KERNEL); | |
2227 | if (!mp->rx_skb) { | |
2228 | printk(KERN_ERR "%s: Cannot allocate Rx skb ring\n", dev->name); | |
2229 | err = -ENOMEM; | |
2230 | goto out_free_irq; | |
2231 | } | |
2232 | mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size, | |
2233 | GFP_KERNEL); | |
2234 | if (!mp->tx_skb) { | |
2235 | printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name); | |
2236 | err = -ENOMEM; | |
2237 | goto out_free_rx_skb; | |
2238 | } | |
16e03018 | 2239 | |
c9df406f LB |
2240 | /* Allocate TX ring */ |
2241 | mp->tx_desc_count = 0; | |
2242 | size = mp->tx_ring_size * sizeof(struct eth_tx_desc); | |
2243 | mp->tx_desc_area_size = size; | |
16e03018 | 2244 | |
c9df406f LB |
2245 | if (mp->tx_sram_size) { |
2246 | mp->p_tx_desc_area = ioremap(mp->tx_sram_addr, | |
2247 | mp->tx_sram_size); | |
2248 | mp->tx_desc_dma = mp->tx_sram_addr; | |
2249 | } else | |
2250 | mp->p_tx_desc_area = dma_alloc_coherent(NULL, size, | |
2251 | &mp->tx_desc_dma, | |
2252 | GFP_KERNEL); | |
16e03018 | 2253 | |
c9df406f LB |
2254 | if (!mp->p_tx_desc_area) { |
2255 | printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n", | |
2256 | dev->name, size); | |
2257 | err = -ENOMEM; | |
2258 | goto out_free_tx_skb; | |
2259 | } | |
2260 | BUG_ON((u32) mp->p_tx_desc_area & 0xf); /* check 16-byte alignment */ | |
2261 | memset((void *)mp->p_tx_desc_area, 0, mp->tx_desc_area_size); | |
16e03018 | 2262 | |
c9df406f | 2263 | ether_init_tx_desc_ring(mp); |
16e03018 | 2264 | |
c9df406f LB |
2265 | /* Allocate RX ring */ |
2266 | mp->rx_desc_count = 0; | |
2267 | size = mp->rx_ring_size * sizeof(struct eth_rx_desc); | |
2268 | mp->rx_desc_area_size = size; | |
16e03018 | 2269 | |
c9df406f LB |
2270 | if (mp->rx_sram_size) { |
2271 | mp->p_rx_desc_area = ioremap(mp->rx_sram_addr, | |
2272 | mp->rx_sram_size); | |
2273 | mp->rx_desc_dma = mp->rx_sram_addr; | |
2274 | } else | |
2275 | mp->p_rx_desc_area = dma_alloc_coherent(NULL, size, | |
2276 | &mp->rx_desc_dma, | |
2277 | GFP_KERNEL); | |
16e03018 | 2278 | |
c9df406f LB |
2279 | if (!mp->p_rx_desc_area) { |
2280 | printk(KERN_ERR "%s: Cannot allocate Rx ring (size %d bytes)\n", | |
2281 | dev->name, size); | |
2282 | printk(KERN_ERR "%s: Freeing previously allocated TX queues...", | |
2283 | dev->name); | |
2284 | if (mp->rx_sram_size) | |
2285 | iounmap(mp->p_tx_desc_area); | |
2286 | else | |
2287 | dma_free_coherent(NULL, mp->tx_desc_area_size, | |
2288 | mp->p_tx_desc_area, mp->tx_desc_dma); | |
2289 | err = -ENOMEM; | |
2290 | goto out_free_tx_skb; | |
2291 | } | |
2292 | memset((void *)mp->p_rx_desc_area, 0, size); | |
16e03018 | 2293 | |
c9df406f | 2294 | ether_init_rx_desc_ring(mp); |
16e03018 | 2295 | |
c9df406f | 2296 | mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */ |
16e03018 | 2297 | |
c9df406f LB |
2298 | #ifdef MV643XX_NAPI |
2299 | napi_enable(&mp->napi); | |
2300 | #endif | |
16e03018 | 2301 | |
c9df406f | 2302 | eth_port_start(dev); |
16e03018 | 2303 | |
c9df406f | 2304 | /* Interrupt Coalescing */ |
b4de9051 | 2305 | |
c9df406f LB |
2306 | #ifdef MV643XX_COAL |
2307 | mp->rx_int_coal = | |
2308 | eth_port_set_rx_coal(mp, MV643XX_RX_COAL); | |
2309 | #endif | |
2310 | ||
2311 | mp->tx_int_coal = | |
2312 | eth_port_set_tx_coal(mp, MV643XX_TX_COAL); | |
16e03018 | 2313 | |
c9df406f | 2314 | /* Unmask phy and link status changes interrupts */ |
073a345c | 2315 | wrl(mp, INT_MASK_EXT(port_num), INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX); |
16e03018 | 2316 | |
c9df406f | 2317 | /* Unmask RX buffer and TX end interrupt */ |
073a345c | 2318 | wrl(mp, INT_MASK(port_num), INT_RX | INT_EXT); |
16e03018 | 2319 | |
c9df406f LB |
2320 | return 0; |
2321 | ||
2322 | out_free_tx_skb: | |
2323 | kfree(mp->tx_skb); | |
2324 | out_free_rx_skb: | |
2325 | kfree(mp->rx_skb); | |
2326 | out_free_irq: | |
2327 | free_irq(dev->irq, dev); | |
2328 | ||
2329 | return err; | |
16e03018 DF |
2330 | } |
2331 | ||
1da177e4 | 2332 | /* |
c9df406f | 2333 | * eth_port_reset - Reset Ethernet port |
1da177e4 LT |
2334 | * |
2335 | * DESCRIPTION: | |
c9df406f LB |
2336 | * This routine resets the chip by aborting any SDMA engine activity and |
2337 | * clearing the MIB counters. The Receiver and the Transmit unit are in | |
2338 | * idle state after this command is performed and the port is disabled. | |
1da177e4 LT |
2339 | * |
2340 | * INPUT: | |
afdb57a2 | 2341 | * struct mv643xx_private *mp Ethernet Port. |
1da177e4 LT |
2342 | * |
2343 | * OUTPUT: | |
c9df406f | 2344 | * Channel activity is halted. |
1da177e4 LT |
2345 | * |
2346 | * RETURN: | |
2347 | * None. | |
c9df406f | 2348 | * |
1da177e4 | 2349 | */ |
c9df406f | 2350 | static void eth_port_reset(struct mv643xx_private *mp) |
1da177e4 | 2351 | { |
afdb57a2 | 2352 | unsigned int port_num = mp->port_num; |
c9df406f | 2353 | unsigned int reg_data; |
1da177e4 | 2354 | |
c9df406f LB |
2355 | mv643xx_eth_port_disable_tx(mp); |
2356 | mv643xx_eth_port_disable_rx(mp); | |
1da177e4 | 2357 | |
c9df406f LB |
2358 | /* Clear all MIB counters */ |
2359 | eth_clear_mib_counters(mp); | |
2360 | ||
2361 | /* Reset the Enable bit in the Configuration Register */ | |
3cb4667c | 2362 | reg_data = rdl(mp, PORT_SERIAL_CONTROL(port_num)); |
c9df406f LB |
2363 | reg_data &= ~(SERIAL_PORT_ENABLE | |
2364 | DO_NOT_FORCE_LINK_FAIL | | |
2365 | FORCE_LINK_PASS); | |
3cb4667c | 2366 | wrl(mp, PORT_SERIAL_CONTROL(port_num), reg_data); |
1da177e4 LT |
2367 | } |
2368 | ||
2369 | /* | |
c9df406f | 2370 | * mv643xx_eth_stop |
1da177e4 | 2371 | * |
c9df406f LB |
2372 | * This function is used when closing the network device. |
2373 | * It updates the hardware, | |
2374 | * release all memory that holds buffers and descriptors and release the IRQ. | |
2375 | * Input : a pointer to the device structure | |
2376 | * Output : zero if success , nonzero if fails | |
1da177e4 | 2377 | */ |
c9df406f LB |
2378 | |
2379 | static int mv643xx_eth_stop(struct net_device *dev) | |
1da177e4 | 2380 | { |
c9df406f | 2381 | struct mv643xx_private *mp = netdev_priv(dev); |
afdb57a2 | 2382 | unsigned int port_num = mp->port_num; |
1da177e4 | 2383 | |
c9df406f | 2384 | /* Mask all interrupts on ethernet port */ |
073a345c | 2385 | wrl(mp, INT_MASK(port_num), 0x00000000); |
c9df406f | 2386 | /* wait for previous write to complete */ |
3cb4667c | 2387 | rdl(mp, INT_MASK(port_num)); |
1da177e4 | 2388 | |
c9df406f LB |
2389 | #ifdef MV643XX_NAPI |
2390 | napi_disable(&mp->napi); | |
2391 | #endif | |
2392 | netif_carrier_off(dev); | |
2393 | netif_stop_queue(dev); | |
1da177e4 | 2394 | |
c9df406f | 2395 | eth_port_reset(mp); |
1da177e4 | 2396 | |
c9df406f LB |
2397 | mv643xx_eth_free_tx_rings(dev); |
2398 | mv643xx_eth_free_rx_rings(dev); | |
1da177e4 | 2399 | |
c9df406f | 2400 | free_irq(dev->irq, dev); |
1da177e4 | 2401 | |
c9df406f | 2402 | return 0; |
1da177e4 LT |
2403 | } |
2404 | ||
c9df406f | 2405 | static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
1da177e4 | 2406 | { |
c9df406f | 2407 | struct mv643xx_private *mp = netdev_priv(dev); |
1da177e4 | 2408 | |
c9df406f | 2409 | return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL); |
1da177e4 LT |
2410 | } |
2411 | ||
2412 | /* | |
c9df406f | 2413 | * Changes MTU (maximum transfer unit) of the gigabit ethenret port |
1da177e4 | 2414 | * |
c9df406f LB |
2415 | * Input : pointer to ethernet interface network device structure |
2416 | * new mtu size | |
2417 | * Output : 0 upon success, -EINVAL upon failure | |
1da177e4 | 2418 | */ |
c9df406f | 2419 | static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu) |
1da177e4 | 2420 | { |
c9df406f LB |
2421 | if ((new_mtu > 9500) || (new_mtu < 64)) |
2422 | return -EINVAL; | |
1da177e4 | 2423 | |
c9df406f LB |
2424 | dev->mtu = new_mtu; |
2425 | if (!netif_running(dev)) | |
2426 | return 0; | |
1da177e4 | 2427 | |
c9df406f LB |
2428 | /* |
2429 | * Stop and then re-open the interface. This will allocate RX | |
2430 | * skbs of the new MTU. | |
2431 | * There is a possible danger that the open will not succeed, | |
2432 | * due to memory being full, which might fail the open function. | |
2433 | */ | |
2434 | mv643xx_eth_stop(dev); | |
2435 | if (mv643xx_eth_open(dev)) { | |
2436 | printk(KERN_ERR "%s: Fatal error on opening device\n", | |
2437 | dev->name); | |
2438 | } | |
2439 | ||
2440 | return 0; | |
1da177e4 LT |
2441 | } |
2442 | ||
2443 | /* | |
c9df406f | 2444 | * mv643xx_eth_tx_timeout_task |
1da177e4 | 2445 | * |
c9df406f | 2446 | * Actual routine to reset the adapter when a timeout on Tx has occurred |
1da177e4 | 2447 | */ |
c9df406f | 2448 | static void mv643xx_eth_tx_timeout_task(struct work_struct *ugly) |
1da177e4 | 2449 | { |
c9df406f LB |
2450 | struct mv643xx_private *mp = container_of(ugly, struct mv643xx_private, |
2451 | tx_timeout_task); | |
2452 | struct net_device *dev = mp->dev; | |
1da177e4 | 2453 | |
c9df406f LB |
2454 | if (!netif_running(dev)) |
2455 | return; | |
1da177e4 | 2456 | |
c9df406f LB |
2457 | netif_stop_queue(dev); |
2458 | ||
2459 | eth_port_reset(mp); | |
2460 | eth_port_start(dev); | |
2461 | ||
2462 | if (mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB) | |
2463 | netif_wake_queue(dev); | |
2464 | } | |
2465 | ||
2466 | /* | |
2467 | * mv643xx_eth_tx_timeout | |
1da177e4 | 2468 | * |
c9df406f | 2469 | * Called upon a timeout on transmitting a packet |
1da177e4 | 2470 | * |
c9df406f LB |
2471 | * Input : pointer to ethernet interface network device structure. |
2472 | * Output : N/A | |
1da177e4 | 2473 | */ |
c9df406f | 2474 | static void mv643xx_eth_tx_timeout(struct net_device *dev) |
1da177e4 | 2475 | { |
c9df406f | 2476 | struct mv643xx_private *mp = netdev_priv(dev); |
1da177e4 | 2477 | |
c9df406f | 2478 | printk(KERN_INFO "%s: TX timeout ", dev->name); |
d0412d96 | 2479 | |
c9df406f LB |
2480 | /* Do the reset outside of interrupt context */ |
2481 | schedule_work(&mp->tx_timeout_task); | |
1da177e4 LT |
2482 | } |
2483 | ||
c9df406f LB |
2484 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2485 | static void mv643xx_netpoll(struct net_device *netdev) | |
9f8dd319 | 2486 | { |
c9df406f LB |
2487 | struct mv643xx_private *mp = netdev_priv(netdev); |
2488 | int port_num = mp->port_num; | |
2489 | ||
073a345c | 2490 | wrl(mp, INT_MASK(port_num), 0x00000000); |
c9df406f | 2491 | /* wait for previous write to complete */ |
3cb4667c | 2492 | rdl(mp, INT_MASK(port_num)); |
c9df406f LB |
2493 | |
2494 | mv643xx_eth_int_handler(netdev->irq, netdev); | |
2495 | ||
073a345c | 2496 | wrl(mp, INT_MASK(port_num), INT_RX | INT_CAUSE_EXT); |
9f8dd319 | 2497 | } |
c9df406f | 2498 | #endif |
9f8dd319 | 2499 | |
c9df406f LB |
2500 | /* |
2501 | * Wrappers for MII support library. | |
2502 | */ | |
2503 | static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location) | |
9f8dd319 | 2504 | { |
c9df406f LB |
2505 | struct mv643xx_private *mp = netdev_priv(dev); |
2506 | int val; | |
2507 | ||
2508 | eth_port_read_smi_reg(mp, location, &val); | |
2509 | return val; | |
9f8dd319 DF |
2510 | } |
2511 | ||
c9df406f | 2512 | static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val) |
9f8dd319 | 2513 | { |
c9df406f LB |
2514 | struct mv643xx_private *mp = netdev_priv(dev); |
2515 | eth_port_write_smi_reg(mp, location, val); | |
2516 | } | |
9f8dd319 | 2517 | |
9f8dd319 | 2518 | |
c9df406f LB |
2519 | /* platform glue ************************************************************/ |
2520 | static void mv643xx_eth_conf_mbus_windows(struct mv643xx_shared_private *msp, | |
2521 | struct mbus_dram_target_info *dram) | |
2522 | { | |
2523 | void __iomem *base = msp->eth_base; | |
2524 | u32 win_enable; | |
2525 | u32 win_protect; | |
2526 | int i; | |
9f8dd319 | 2527 | |
c9df406f LB |
2528 | for (i = 0; i < 6; i++) { |
2529 | writel(0, base + WINDOW_BASE(i)); | |
2530 | writel(0, base + WINDOW_SIZE(i)); | |
2531 | if (i < 4) | |
2532 | writel(0, base + WINDOW_REMAP_HIGH(i)); | |
9f8dd319 DF |
2533 | } |
2534 | ||
c9df406f LB |
2535 | win_enable = 0x3f; |
2536 | win_protect = 0; | |
2537 | ||
2538 | for (i = 0; i < dram->num_cs; i++) { | |
2539 | struct mbus_dram_window *cs = dram->cs + i; | |
2540 | ||
2541 | writel((cs->base & 0xffff0000) | | |
2542 | (cs->mbus_attr << 8) | | |
2543 | dram->mbus_dram_target_id, base + WINDOW_BASE(i)); | |
2544 | writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i)); | |
2545 | ||
2546 | win_enable &= ~(1 << i); | |
2547 | win_protect |= 3 << (2 * i); | |
2548 | } | |
2549 | ||
2550 | writel(win_enable, base + WINDOW_BAR_ENABLE); | |
2551 | msp->win_protect = win_protect; | |
9f8dd319 DF |
2552 | } |
2553 | ||
c9df406f | 2554 | static int mv643xx_eth_shared_probe(struct platform_device *pdev) |
9f8dd319 | 2555 | { |
c9df406f LB |
2556 | static int mv643xx_version_printed = 0; |
2557 | struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data; | |
2558 | struct mv643xx_shared_private *msp; | |
2559 | struct resource *res; | |
2560 | int ret; | |
9f8dd319 | 2561 | |
c9df406f LB |
2562 | if (!mv643xx_version_printed++) |
2563 | printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n"); | |
9f8dd319 | 2564 | |
c9df406f LB |
2565 | ret = -EINVAL; |
2566 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2567 | if (res == NULL) | |
2568 | goto out; | |
9f8dd319 | 2569 | |
c9df406f LB |
2570 | ret = -ENOMEM; |
2571 | msp = kmalloc(sizeof(*msp), GFP_KERNEL); | |
2572 | if (msp == NULL) | |
2573 | goto out; | |
2574 | memset(msp, 0, sizeof(*msp)); | |
2575 | ||
2576 | msp->eth_base = ioremap(res->start, res->end - res->start + 1); | |
2577 | if (msp->eth_base == NULL) | |
2578 | goto out_free; | |
2579 | ||
2580 | spin_lock_init(&msp->phy_lock); | |
2581 | msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000; | |
2582 | ||
2583 | platform_set_drvdata(pdev, msp); | |
2584 | ||
2585 | /* | |
2586 | * (Re-)program MBUS remapping windows if we are asked to. | |
2587 | */ | |
2588 | if (pd != NULL && pd->dram != NULL) | |
2589 | mv643xx_eth_conf_mbus_windows(msp, pd->dram); | |
2590 | ||
2591 | return 0; | |
2592 | ||
2593 | out_free: | |
2594 | kfree(msp); | |
2595 | out: | |
2596 | return ret; | |
2597 | } | |
2598 | ||
2599 | static int mv643xx_eth_shared_remove(struct platform_device *pdev) | |
2600 | { | |
2601 | struct mv643xx_shared_private *msp = platform_get_drvdata(pdev); | |
2602 | ||
2603 | iounmap(msp->eth_base); | |
2604 | kfree(msp); | |
2605 | ||
2606 | return 0; | |
9f8dd319 DF |
2607 | } |
2608 | ||
c9df406f LB |
2609 | static struct platform_driver mv643xx_eth_shared_driver = { |
2610 | .probe = mv643xx_eth_shared_probe, | |
2611 | .remove = mv643xx_eth_shared_remove, | |
2612 | .driver = { | |
2613 | .name = MV643XX_ETH_SHARED_NAME, | |
2614 | .owner = THIS_MODULE, | |
2615 | }, | |
2616 | }; | |
2617 | ||
1da177e4 | 2618 | /* |
c9df406f | 2619 | * ethernet_phy_set - Set the ethernet port PHY address. |
1da177e4 LT |
2620 | * |
2621 | * DESCRIPTION: | |
c9df406f | 2622 | * This routine sets the given ethernet port PHY address. |
1da177e4 LT |
2623 | * |
2624 | * INPUT: | |
afdb57a2 | 2625 | * struct mv643xx_private *mp Ethernet Port. |
c9df406f | 2626 | * int phy_addr PHY address. |
1da177e4 LT |
2627 | * |
2628 | * OUTPUT: | |
c9df406f | 2629 | * None. |
1da177e4 LT |
2630 | * |
2631 | * RETURN: | |
2632 | * None. | |
2633 | * | |
2634 | */ | |
c9df406f | 2635 | static void ethernet_phy_set(struct mv643xx_private *mp, int phy_addr) |
1da177e4 | 2636 | { |
c9df406f LB |
2637 | u32 reg_data; |
2638 | int addr_shift = 5 * mp->port_num; | |
1da177e4 | 2639 | |
3cb4667c | 2640 | reg_data = rdl(mp, PHY_ADDR); |
c9df406f LB |
2641 | reg_data &= ~(0x1f << addr_shift); |
2642 | reg_data |= (phy_addr & 0x1f) << addr_shift; | |
3cb4667c | 2643 | wrl(mp, PHY_ADDR, reg_data); |
1da177e4 LT |
2644 | } |
2645 | ||
1da177e4 | 2646 | /* |
c9df406f | 2647 | * ethernet_phy_get - Get the ethernet port PHY address. |
1da177e4 LT |
2648 | * |
2649 | * DESCRIPTION: | |
c9df406f | 2650 | * This routine returns the given ethernet port PHY address. |
1da177e4 LT |
2651 | * |
2652 | * INPUT: | |
afdb57a2 | 2653 | * struct mv643xx_private *mp Ethernet Port. |
1da177e4 LT |
2654 | * |
2655 | * OUTPUT: | |
c9df406f | 2656 | * None. |
1da177e4 LT |
2657 | * |
2658 | * RETURN: | |
c9df406f | 2659 | * PHY address. |
1da177e4 LT |
2660 | * |
2661 | */ | |
c9df406f | 2662 | static int ethernet_phy_get(struct mv643xx_private *mp) |
1da177e4 | 2663 | { |
c9df406f | 2664 | unsigned int reg_data; |
1da177e4 | 2665 | |
3cb4667c | 2666 | reg_data = rdl(mp, PHY_ADDR); |
1da177e4 | 2667 | |
c9df406f | 2668 | return ((reg_data >> (5 * mp->port_num)) & 0x1f); |
1da177e4 LT |
2669 | } |
2670 | ||
2671 | /* | |
c9df406f | 2672 | * ethernet_phy_detect - Detect whether a phy is present |
1da177e4 LT |
2673 | * |
2674 | * DESCRIPTION: | |
c9df406f LB |
2675 | * This function tests whether there is a PHY present on |
2676 | * the specified port. | |
1da177e4 LT |
2677 | * |
2678 | * INPUT: | |
afdb57a2 | 2679 | * struct mv643xx_private *mp Ethernet Port. |
1da177e4 LT |
2680 | * |
2681 | * OUTPUT: | |
c9df406f | 2682 | * None |
1da177e4 LT |
2683 | * |
2684 | * RETURN: | |
c9df406f LB |
2685 | * 0 on success |
2686 | * -ENODEV on failure | |
1da177e4 LT |
2687 | * |
2688 | */ | |
c9df406f | 2689 | static int ethernet_phy_detect(struct mv643xx_private *mp) |
1da177e4 | 2690 | { |
c9df406f LB |
2691 | unsigned int phy_reg_data0; |
2692 | int auto_neg; | |
1da177e4 | 2693 | |
c9df406f LB |
2694 | eth_port_read_smi_reg(mp, 0, &phy_reg_data0); |
2695 | auto_neg = phy_reg_data0 & 0x1000; | |
2696 | phy_reg_data0 ^= 0x1000; /* invert auto_neg */ | |
2697 | eth_port_write_smi_reg(mp, 0, phy_reg_data0); | |
1da177e4 | 2698 | |
c9df406f LB |
2699 | eth_port_read_smi_reg(mp, 0, &phy_reg_data0); |
2700 | if ((phy_reg_data0 & 0x1000) == auto_neg) | |
2701 | return -ENODEV; /* change didn't take */ | |
1da177e4 | 2702 | |
c9df406f LB |
2703 | phy_reg_data0 ^= 0x1000; |
2704 | eth_port_write_smi_reg(mp, 0, phy_reg_data0); | |
2705 | return 0; | |
1da177e4 LT |
2706 | } |
2707 | ||
c9df406f LB |
2708 | static void mv643xx_init_ethtool_cmd(struct net_device *dev, int phy_address, |
2709 | int speed, int duplex, | |
2710 | struct ethtool_cmd *cmd) | |
c28a4f89 | 2711 | { |
c28a4f89 JC |
2712 | struct mv643xx_private *mp = netdev_priv(dev); |
2713 | ||
c9df406f | 2714 | memset(cmd, 0, sizeof(*cmd)); |
c28a4f89 | 2715 | |
c9df406f LB |
2716 | cmd->port = PORT_MII; |
2717 | cmd->transceiver = XCVR_INTERNAL; | |
2718 | cmd->phy_address = phy_address; | |
2719 | ||
2720 | if (speed == 0) { | |
2721 | cmd->autoneg = AUTONEG_ENABLE; | |
2722 | /* mii lib checks, but doesn't use speed on AUTONEG_ENABLE */ | |
2723 | cmd->speed = SPEED_100; | |
2724 | cmd->advertising = ADVERTISED_10baseT_Half | | |
2725 | ADVERTISED_10baseT_Full | | |
2726 | ADVERTISED_100baseT_Half | | |
2727 | ADVERTISED_100baseT_Full; | |
2728 | if (mp->mii.supports_gmii) | |
2729 | cmd->advertising |= ADVERTISED_1000baseT_Full; | |
2730 | } else { | |
2731 | cmd->autoneg = AUTONEG_DISABLE; | |
2732 | cmd->speed = speed; | |
2733 | cmd->duplex = duplex; | |
2734 | } | |
c28a4f89 JC |
2735 | } |
2736 | ||
c9df406f LB |
2737 | /*/ |
2738 | * mv643xx_eth_probe | |
1da177e4 | 2739 | * |
c9df406f LB |
2740 | * First function called after registering the network device. |
2741 | * It's purpose is to initialize the device as an ethernet device, | |
2742 | * fill the ethernet device structure with pointers * to functions, | |
2743 | * and set the MAC address of the interface | |
1da177e4 | 2744 | * |
c9df406f LB |
2745 | * Input : struct device * |
2746 | * Output : -ENOMEM if failed , 0 if success | |
1da177e4 | 2747 | */ |
c9df406f | 2748 | static int mv643xx_eth_probe(struct platform_device *pdev) |
1da177e4 | 2749 | { |
c9df406f LB |
2750 | struct mv643xx_eth_platform_data *pd; |
2751 | int port_num; | |
2752 | struct mv643xx_private *mp; | |
2753 | struct net_device *dev; | |
2754 | u8 *p; | |
2755 | struct resource *res; | |
2756 | int err; | |
2757 | struct ethtool_cmd cmd; | |
2758 | int duplex = DUPLEX_HALF; | |
2759 | int speed = 0; /* default to auto-negotiation */ | |
2760 | DECLARE_MAC_BUF(mac); | |
1da177e4 | 2761 | |
c9df406f LB |
2762 | pd = pdev->dev.platform_data; |
2763 | if (pd == NULL) { | |
2764 | printk(KERN_ERR "No mv643xx_eth_platform_data\n"); | |
2765 | return -ENODEV; | |
2766 | } | |
1da177e4 | 2767 | |
c9df406f LB |
2768 | if (pd->shared == NULL) { |
2769 | printk(KERN_ERR "No mv643xx_eth_platform_data->shared\n"); | |
2770 | return -ENODEV; | |
2771 | } | |
8f518703 | 2772 | |
c9df406f LB |
2773 | dev = alloc_etherdev(sizeof(struct mv643xx_private)); |
2774 | if (!dev) | |
2775 | return -ENOMEM; | |
1da177e4 | 2776 | |
c9df406f | 2777 | platform_set_drvdata(pdev, dev); |
1da177e4 | 2778 | |
c9df406f LB |
2779 | mp = netdev_priv(dev); |
2780 | mp->dev = dev; | |
2781 | #ifdef MV643XX_NAPI | |
2782 | netif_napi_add(dev, &mp->napi, mv643xx_poll, 64); | |
2783 | #endif | |
1da177e4 | 2784 | |
c9df406f LB |
2785 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
2786 | BUG_ON(!res); | |
2787 | dev->irq = res->start; | |
1da177e4 | 2788 | |
c9df406f LB |
2789 | dev->open = mv643xx_eth_open; |
2790 | dev->stop = mv643xx_eth_stop; | |
2791 | dev->hard_start_xmit = mv643xx_eth_start_xmit; | |
2792 | dev->set_mac_address = mv643xx_eth_set_mac_address; | |
2793 | dev->set_multicast_list = mv643xx_eth_set_rx_mode; | |
2794 | ||
2795 | /* No need to Tx Timeout */ | |
2796 | dev->tx_timeout = mv643xx_eth_tx_timeout; | |
2797 | ||
2798 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2799 | dev->poll_controller = mv643xx_netpoll; | |
2800 | #endif | |
2801 | ||
2802 | dev->watchdog_timeo = 2 * HZ; | |
2803 | dev->base_addr = 0; | |
2804 | dev->change_mtu = mv643xx_eth_change_mtu; | |
2805 | dev->do_ioctl = mv643xx_eth_do_ioctl; | |
2806 | SET_ETHTOOL_OPS(dev, &mv643xx_ethtool_ops); | |
1da177e4 | 2807 | |
c9df406f LB |
2808 | #ifdef MV643XX_CHECKSUM_OFFLOAD_TX |
2809 | #ifdef MAX_SKB_FRAGS | |
b4de9051 | 2810 | /* |
c9df406f LB |
2811 | * Zero copy can only work if we use Discovery II memory. Else, we will |
2812 | * have to map the buffers to ISA memory which is only 16 MB | |
b4de9051 | 2813 | */ |
c9df406f LB |
2814 | dev->features = NETIF_F_SG | NETIF_F_IP_CSUM; |
2815 | #endif | |
2816 | #endif | |
1da177e4 | 2817 | |
c9df406f LB |
2818 | /* Configure the timeout task */ |
2819 | INIT_WORK(&mp->tx_timeout_task, mv643xx_eth_tx_timeout_task); | |
1da177e4 | 2820 | |
c9df406f | 2821 | spin_lock_init(&mp->lock); |
1da177e4 | 2822 | |
c9df406f LB |
2823 | mp->shared = platform_get_drvdata(pd->shared); |
2824 | port_num = mp->port_num = pd->port_number; | |
8f518703 | 2825 | |
c9df406f LB |
2826 | if (mp->shared->win_protect) |
2827 | wrl(mp, WINDOW_PROTECT(port_num), mp->shared->win_protect); | |
1da177e4 | 2828 | |
c9df406f LB |
2829 | mp->shared_smi = mp->shared; |
2830 | if (pd->shared_smi != NULL) | |
2831 | mp->shared_smi = platform_get_drvdata(pd->shared_smi); | |
2832 | ||
2833 | /* set default config values */ | |
2834 | eth_port_uc_addr_get(mp, dev->dev_addr); | |
2835 | mp->rx_ring_size = PORT_DEFAULT_RECEIVE_QUEUE_SIZE; | |
2836 | mp->tx_ring_size = PORT_DEFAULT_TRANSMIT_QUEUE_SIZE; | |
2837 | ||
2838 | if (is_valid_ether_addr(pd->mac_addr)) | |
2839 | memcpy(dev->dev_addr, pd->mac_addr, 6); | |
2840 | ||
2841 | if (pd->phy_addr || pd->force_phy_addr) | |
2842 | ethernet_phy_set(mp, pd->phy_addr); | |
8f518703 | 2843 | |
c9df406f LB |
2844 | if (pd->rx_queue_size) |
2845 | mp->rx_ring_size = pd->rx_queue_size; | |
1da177e4 | 2846 | |
c9df406f LB |
2847 | if (pd->tx_queue_size) |
2848 | mp->tx_ring_size = pd->tx_queue_size; | |
1da177e4 | 2849 | |
c9df406f LB |
2850 | if (pd->tx_sram_size) { |
2851 | mp->tx_sram_size = pd->tx_sram_size; | |
2852 | mp->tx_sram_addr = pd->tx_sram_addr; | |
2853 | } | |
1da177e4 | 2854 | |
c9df406f LB |
2855 | if (pd->rx_sram_size) { |
2856 | mp->rx_sram_size = pd->rx_sram_size; | |
2857 | mp->rx_sram_addr = pd->rx_sram_addr; | |
2858 | } | |
1da177e4 | 2859 | |
c9df406f LB |
2860 | duplex = pd->duplex; |
2861 | speed = pd->speed; | |
1da177e4 | 2862 | |
c9df406f LB |
2863 | /* Hook up MII support for ethtool */ |
2864 | mp->mii.dev = dev; | |
2865 | mp->mii.mdio_read = mv643xx_mdio_read; | |
2866 | mp->mii.mdio_write = mv643xx_mdio_write; | |
2867 | mp->mii.phy_id = ethernet_phy_get(mp); | |
2868 | mp->mii.phy_id_mask = 0x3f; | |
2869 | mp->mii.reg_num_mask = 0x1f; | |
1da177e4 | 2870 | |
c9df406f LB |
2871 | err = ethernet_phy_detect(mp); |
2872 | if (err) { | |
2873 | pr_debug("%s: No PHY detected at addr %d\n", | |
2874 | dev->name, ethernet_phy_get(mp)); | |
2875 | goto out; | |
2876 | } | |
1da177e4 | 2877 | |
c9df406f LB |
2878 | ethernet_phy_reset(mp); |
2879 | mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii); | |
2880 | mv643xx_init_ethtool_cmd(dev, mp->mii.phy_id, speed, duplex, &cmd); | |
2881 | mv643xx_eth_update_pscr(dev, &cmd); | |
2882 | mv643xx_set_settings(dev, &cmd); | |
8f518703 | 2883 | |
c9df406f LB |
2884 | SET_NETDEV_DEV(dev, &pdev->dev); |
2885 | err = register_netdev(dev); | |
2886 | if (err) | |
2887 | goto out; | |
1da177e4 | 2888 | |
c9df406f LB |
2889 | p = dev->dev_addr; |
2890 | printk(KERN_NOTICE | |
2891 | "%s: port %d with MAC address %s\n", | |
2892 | dev->name, port_num, print_mac(mac, p)); | |
1da177e4 | 2893 | |
c9df406f LB |
2894 | if (dev->features & NETIF_F_SG) |
2895 | printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name); | |
1da177e4 | 2896 | |
c9df406f LB |
2897 | if (dev->features & NETIF_F_IP_CSUM) |
2898 | printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n", | |
2899 | dev->name); | |
1da177e4 | 2900 | |
c9df406f LB |
2901 | #ifdef MV643XX_CHECKSUM_OFFLOAD_TX |
2902 | printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name); | |
2903 | #endif | |
1da177e4 | 2904 | |
c9df406f LB |
2905 | #ifdef MV643XX_COAL |
2906 | printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n", | |
2907 | dev->name); | |
2908 | #endif | |
1da177e4 | 2909 | |
c9df406f LB |
2910 | #ifdef MV643XX_NAPI |
2911 | printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name); | |
2912 | #endif | |
1da177e4 | 2913 | |
c9df406f LB |
2914 | if (mp->tx_sram_size > 0) |
2915 | printk(KERN_NOTICE "%s: Using SRAM\n", dev->name); | |
1da177e4 | 2916 | |
c9df406f | 2917 | return 0; |
1da177e4 | 2918 | |
c9df406f LB |
2919 | out: |
2920 | free_netdev(dev); | |
1da177e4 | 2921 | |
c9df406f | 2922 | return err; |
1da177e4 LT |
2923 | } |
2924 | ||
c9df406f | 2925 | static int mv643xx_eth_remove(struct platform_device *pdev) |
1da177e4 | 2926 | { |
c9df406f | 2927 | struct net_device *dev = platform_get_drvdata(pdev); |
1da177e4 | 2928 | |
c9df406f LB |
2929 | unregister_netdev(dev); |
2930 | flush_scheduled_work(); | |
2931 | ||
2932 | free_netdev(dev); | |
2933 | platform_set_drvdata(pdev, NULL); | |
2934 | return 0; | |
1da177e4 LT |
2935 | } |
2936 | ||
c9df406f | 2937 | static void mv643xx_eth_shutdown(struct platform_device *pdev) |
d0412d96 | 2938 | { |
c9df406f | 2939 | struct net_device *dev = platform_get_drvdata(pdev); |
d0412d96 | 2940 | struct mv643xx_private *mp = netdev_priv(dev); |
c9df406f | 2941 | unsigned int port_num = mp->port_num; |
d0412d96 | 2942 | |
c9df406f | 2943 | /* Mask all interrupts on ethernet port */ |
3cb4667c LB |
2944 | wrl(mp, INT_MASK(port_num), 0); |
2945 | rdl(mp, INT_MASK(port_num)); | |
c9df406f LB |
2946 | |
2947 | eth_port_reset(mp); | |
d0412d96 JC |
2948 | } |
2949 | ||
c9df406f LB |
2950 | static struct platform_driver mv643xx_eth_driver = { |
2951 | .probe = mv643xx_eth_probe, | |
2952 | .remove = mv643xx_eth_remove, | |
2953 | .shutdown = mv643xx_eth_shutdown, | |
2954 | .driver = { | |
2955 | .name = MV643XX_ETH_NAME, | |
2956 | .owner = THIS_MODULE, | |
2957 | }, | |
2958 | }; | |
2959 | ||
2960 | /* | |
2961 | * mv643xx_init_module | |
2962 | * | |
2963 | * Registers the network drivers into the Linux kernel | |
2964 | * | |
2965 | * Input : N/A | |
2966 | * | |
2967 | * Output : N/A | |
2968 | */ | |
2969 | static int __init mv643xx_init_module(void) | |
d0412d96 | 2970 | { |
c9df406f | 2971 | int rc; |
d0412d96 | 2972 | |
c9df406f LB |
2973 | rc = platform_driver_register(&mv643xx_eth_shared_driver); |
2974 | if (!rc) { | |
2975 | rc = platform_driver_register(&mv643xx_eth_driver); | |
2976 | if (rc) | |
2977 | platform_driver_unregister(&mv643xx_eth_shared_driver); | |
2978 | } | |
2979 | return rc; | |
d0412d96 JC |
2980 | } |
2981 | ||
c9df406f LB |
2982 | /* |
2983 | * mv643xx_cleanup_module | |
2984 | * | |
2985 | * Registers the network drivers into the Linux kernel | |
2986 | * | |
2987 | * Input : N/A | |
2988 | * | |
2989 | * Output : N/A | |
2990 | */ | |
2991 | static void __exit mv643xx_cleanup_module(void) | |
d0412d96 | 2992 | { |
c9df406f LB |
2993 | platform_driver_unregister(&mv643xx_eth_driver); |
2994 | platform_driver_unregister(&mv643xx_eth_shared_driver); | |
d0412d96 JC |
2995 | } |
2996 | ||
c9df406f LB |
2997 | module_init(mv643xx_init_module); |
2998 | module_exit(mv643xx_cleanup_module); | |
1da177e4 | 2999 | |
c9df406f LB |
3000 | MODULE_LICENSE("GPL"); |
3001 | MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani" | |
3002 | " and Dale Farnsworth"); | |
3003 | MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX"); | |
3004 | MODULE_ALIAS("platform:" MV643XX_ETH_NAME); | |
3005 | MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME); |