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mv643xx_eth: inline txq_alloc_desc_index()
[linux-2.6-block.git] / drivers / net / mv643xx_eth.c
CommitLineData
1da177e4 1/*
9c1bbdfe 2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
1da177e4
LT		 3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
4547fa61
LB		 6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
1da177e4
LT		 8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
3bb8a18a 10 * written by Manish Lachwani
1da177e4
LT		 11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
c8aaea25 14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
1da177e4
LT		 15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
4547fa61
LB		 20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
1da177e4
LT		 23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36 */
a779d38c 37
1da177e4
LT		 38#include <linux/init.h>
39#include <linux/dma-mapping.h>
b6298c22 40#include <linux/in.h>
c3efab8e 41#include <linux/ip.h>
1da177e4
LT		 42#include <linux/tcp.h>
43#include <linux/udp.h>
44#include <linux/etherdevice.h>
1da177e4
LT		 45#include <linux/delay.h>
46#include <linux/ethtool.h>
d052d1be 47#include <linux/platform_device.h>
fbd6a754
LB		 48#include <linux/module.h>
49#include <linux/kernel.h>
50#include <linux/spinlock.h>
51#include <linux/workqueue.h>
ed94493f 52#include <linux/phy.h>
fbd6a754 53#include <linux/mv643xx_eth.h>
10a9948d
LB		 54#include <linux/io.h>
55#include <linux/types.h>
1da177e4 56#include <asm/system.h>
fbd6a754 57
e5371493 58static char mv643xx_eth_driver_name[] = "mv643xx_eth";
042af53c 59static char mv643xx_eth_driver_version[] = "1.4";
c9df406f 60
fbd6a754 61
fbd6a754
LB		 62/*
63 * Registers shared between all ports.
64 */
3cb4667c
LB		 65#define PHY_ADDR 0x0000
66#define SMI_REG 0x0004
45c5d3bc
LB		 67#define SMI_BUSY 0x10000000
68#define SMI_READ_VALID 0x08000000
69#define SMI_OPCODE_READ 0x04000000
70#define SMI_OPCODE_WRITE 0x00000000
71#define ERR_INT_CAUSE 0x0080
72#define ERR_INT_SMI_DONE 0x00000010
73#define ERR_INT_MASK 0x0084
3cb4667c
LB		 74#define WINDOW_BASE(w) (0x0200 + ((w) << 3))
75#define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
76#define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
77#define WINDOW_BAR_ENABLE 0x0290
78#define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
fbd6a754
LB		 79
80/*
37a6084f
LB		 81 * Main per-port registers. These live at offset 0x0400 for
82 * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
fbd6a754 83 */
37a6084f 84#define PORT_CONFIG 0x0000
d9a073ea 85#define UNICAST_PROMISCUOUS_MODE 0x00000001
37a6084f
LB		 86#define PORT_CONFIG_EXT 0x0004
87#define MAC_ADDR_LOW 0x0014
88#define MAC_ADDR_HIGH 0x0018
89#define SDMA_CONFIG 0x001c
90#define PORT_SERIAL_CONTROL 0x003c
91#define PORT_STATUS 0x0044
a2a41689 92#define TX_FIFO_EMPTY 0x00000400
ae9ae064 93#define TX_IN_PROGRESS 0x00000080
2f7eb47a
LB		 94#define PORT_SPEED_MASK 0x00000030
95#define PORT_SPEED_1000 0x00000010
96#define PORT_SPEED_100 0x00000020
97#define PORT_SPEED_10 0x00000000
98#define FLOW_CONTROL_ENABLED 0x00000008
99#define FULL_DUPLEX 0x00000004
81600eea 100#define LINK_UP 0x00000002
37a6084f
LB		 101#define TXQ_COMMAND 0x0048
102#define TXQ_FIX_PRIO_CONF 0x004c
103#define TX_BW_RATE 0x0050
104#define TX_BW_MTU 0x0058
105#define TX_BW_BURST 0x005c
106#define INT_CAUSE 0x0060
226bb6b7 107#define INT_TX_END 0x07f80000
befefe21 108#define INT_RX 0x000003fc
073a345c 109#define INT_EXT 0x00000002
37a6084f 110#define INT_CAUSE_EXT 0x0064
befefe21
LB		 111#define INT_EXT_LINK_PHY 0x00110000
112#define INT_EXT_TX 0x000000ff
37a6084f
LB		 113#define INT_MASK 0x0068
114#define INT_MASK_EXT 0x006c
115#define TX_FIFO_URGENT_THRESHOLD 0x0074
116#define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
117#define TX_BW_RATE_MOVED 0x00e0
118#define TX_BW_MTU_MOVED 0x00e8
119#define TX_BW_BURST_MOVED 0x00ec
120#define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4))
121#define RXQ_COMMAND 0x0280
122#define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2))
123#define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4))
124#define TXQ_BW_CONF(q) (0x0304 + ((q) << 4))
125#define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4))
126
127/*
128 * Misc per-port registers.
129 */
3cb4667c
LB		 130#define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
131#define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
132#define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
133#define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
fbd6a754 134
2679a550
LB		 135
136/*
137 * SDMA configuration register.
138 */
cd4ccf76 139#define RX_BURST_SIZE_16_64BIT (4 << 1)
fbd6a754 140#define BLM_RX_NO_SWAP (1 << 4)
fbd6a754 141#define BLM_TX_NO_SWAP (1 << 5)
cd4ccf76 142#define TX_BURST_SIZE_16_64BIT (4 << 22)
fbd6a754
LB		 143
144#if defined(__BIG_ENDIAN)
145#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
10a9948d
LB		 146 (RX_BURST_SIZE_16_64BIT | \
147 TX_BURST_SIZE_16_64BIT)
fbd6a754
LB		 148#elif defined(__LITTLE_ENDIAN)
149#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
10a9948d 150 (RX_BURST_SIZE_16_64BIT | \
fbd6a754
LB		 151 BLM_RX_NO_SWAP | \
152 BLM_TX_NO_SWAP | \
10a9948d 153 TX_BURST_SIZE_16_64BIT)
fbd6a754
LB		 154#else
155#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
156#endif
157
2beff77b
LB		 158
159/*
160 * Port serial control register.
161 */
162#define SET_MII_SPEED_TO_100 (1 << 24)
163#define SET_GMII_SPEED_TO_1000 (1 << 23)
164#define SET_FULL_DUPLEX_MODE (1 << 21)
fbd6a754 165#define MAX_RX_PACKET_9700BYTE (5 << 17)
2beff77b
LB		 166#define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
167#define DO_NOT_FORCE_LINK_FAIL (1 << 10)
168#define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
169#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
170#define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
171#define FORCE_LINK_PASS (1 << 1)
172#define SERIAL_PORT_ENABLE (1 << 0)
fbd6a754 173
2b4a624d
LB		 174#define DEFAULT_RX_QUEUE_SIZE 128
175#define DEFAULT_TX_QUEUE_SIZE 256
fbd6a754 176
fbd6a754 177
7ca72a3b
LB		 178/*
179 * RX/TX descriptors.
fbd6a754
LB		 180 */
181#if defined(__BIG_ENDIAN)
cc9754b3 182struct rx_desc {
fbd6a754
LB		 183 u16 byte_cnt; /* Descriptor buffer byte count */
184 u16 buf_size; /* Buffer size */
185 u32 cmd_sts; /* Descriptor command status */
186 u32 next_desc_ptr; /* Next descriptor pointer */
187 u32 buf_ptr; /* Descriptor buffer pointer */
188};
189
cc9754b3 190struct tx_desc {
fbd6a754
LB		 191 u16 byte_cnt; /* buffer byte count */
192 u16 l4i_chk; /* CPU provided TCP checksum */
193 u32 cmd_sts; /* Command/status field */
194 u32 next_desc_ptr; /* Pointer to next descriptor */
195 u32 buf_ptr; /* pointer to buffer for this descriptor*/
196};
197#elif defined(__LITTLE_ENDIAN)
cc9754b3 198struct rx_desc {
fbd6a754
LB		 199 u32 cmd_sts; /* Descriptor command status */
200 u16 buf_size; /* Buffer size */
201 u16 byte_cnt; /* Descriptor buffer byte count */
202 u32 buf_ptr; /* Descriptor buffer pointer */
203 u32 next_desc_ptr; /* Next descriptor pointer */
204};
205
cc9754b3 206struct tx_desc {
fbd6a754
LB		 207 u32 cmd_sts; /* Command/status field */
208 u16 l4i_chk; /* CPU provided TCP checksum */
209 u16 byte_cnt; /* buffer byte count */
210 u32 buf_ptr; /* pointer to buffer for this descriptor*/
211 u32 next_desc_ptr; /* Pointer to next descriptor */
212};
213#else
214#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
215#endif
216
7ca72a3b 217/* RX & TX descriptor command */
cc9754b3 218#define BUFFER_OWNED_BY_DMA 0x80000000
7ca72a3b
LB		 219
220/* RX & TX descriptor status */
cc9754b3 221#define ERROR_SUMMARY 0x00000001
7ca72a3b
LB		 222
223/* RX descriptor status */
cc9754b3
LB		 224#define LAYER_4_CHECKSUM_OK 0x40000000
225#define RX_ENABLE_INTERRUPT 0x20000000
226#define RX_FIRST_DESC 0x08000000
227#define RX_LAST_DESC 0x04000000
7ca72a3b
LB		 228
229/* TX descriptor command */
cc9754b3
LB		 230#define TX_ENABLE_INTERRUPT 0x00800000
231#define GEN_CRC 0x00400000
232#define TX_FIRST_DESC 0x00200000
233#define TX_LAST_DESC 0x00100000
234#define ZERO_PADDING 0x00080000
235#define GEN_IP_V4_CHECKSUM 0x00040000
236#define GEN_TCP_UDP_CHECKSUM 0x00020000
237#define UDP_FRAME 0x00010000
e32b6617
LB		 238#define MAC_HDR_EXTRA_4_BYTES 0x00008000
239#define MAC_HDR_EXTRA_8_BYTES 0x00000200
7ca72a3b 240
cc9754b3 241#define TX_IHL_SHIFT 11
7ca72a3b
LB		 242
243
c9df406f 244/* global *******************************************************************/
e5371493 245struct mv643xx_eth_shared_private {
fc32b0e2
LB		 246 /*
247 * Ethernet controller base address.
248 */
cc9754b3 249 void __iomem *base;
c9df406f 250
fc0eb9f2
LB		 251 /*
252 * Points at the right SMI instance to use.
253 */
254 struct mv643xx_eth_shared_private *smi;
255
fc32b0e2 256 /*
ed94493f 257 * Provides access to local SMI interface.
fc32b0e2 258 */
298cf9be 259 struct mii_bus *smi_bus;
c9df406f 260
45c5d3bc
LB		 261 /*
262 * If we have access to the error interrupt pin (which is
263 * somewhat misnamed as it not only reflects internal errors
264 * but also reflects SMI completion), use that to wait for
265 * SMI access completion instead of polling the SMI busy bit.
266 */
267 int err_interrupt;
268 wait_queue_head_t smi_busy_wait;
269
fc32b0e2
LB		 270 /*
271 * Per-port MBUS window access register value.
272 */
c9df406f
LB		 273 u32 win_protect;
274
fc32b0e2
LB		 275 /*
276 * Hardware-specific parameters.
277 */
c9df406f 278 unsigned int t_clk;
773fc3ee 279 int extended_rx_coal_limit;
457b1d5a 280 int tx_bw_control;
c9df406f
LB		 281};
282
457b1d5a
LB		 283#define TX_BW_CONTROL_ABSENT 0
284#define TX_BW_CONTROL_OLD_LAYOUT 1
285#define TX_BW_CONTROL_NEW_LAYOUT 2
286
c9df406f
LB		 287
288/* per-port *****************************************************************/
e5371493 289struct mib_counters {
fbd6a754
LB		 290 u64 good_octets_received;
291 u32 bad_octets_received;
292 u32 internal_mac_transmit_err;
293 u32 good_frames_received;
294 u32 bad_frames_received;
295 u32 broadcast_frames_received;
296 u32 multicast_frames_received;
297 u32 frames_64_octets;
298 u32 frames_65_to_127_octets;
299 u32 frames_128_to_255_octets;
300 u32 frames_256_to_511_octets;
301 u32 frames_512_to_1023_octets;
302 u32 frames_1024_to_max_octets;
303 u64 good_octets_sent;
304 u32 good_frames_sent;
305 u32 excessive_collision;
306 u32 multicast_frames_sent;
307 u32 broadcast_frames_sent;
308 u32 unrec_mac_control_received;
309 u32 fc_sent;
310 u32 good_fc_received;
311 u32 bad_fc_received;
312 u32 undersize_received;
313 u32 fragments_received;
314 u32 oversize_received;
315 u32 jabber_received;
316 u32 mac_receive_error;
317 u32 bad_crc_event;
318 u32 collision;
319 u32 late_collision;
320};
321
8a578111 322struct rx_queue {
64da80a2
LB		 323 int index;
324
8a578111
LB		 325 int rx_ring_size;
326
327 int rx_desc_count;
328 int rx_curr_desc;
329 int rx_used_desc;
330
331 struct rx_desc *rx_desc_area;
332 dma_addr_t rx_desc_dma;
333 int rx_desc_area_size;
334 struct sk_buff **rx_skb;
8a578111
LB		 335};
336
13d64285 337struct tx_queue {
3d6b35bc
LB		 338 int index;
339
13d64285 340 int tx_ring_size;
fbd6a754 341
13d64285
LB		 342 int tx_desc_count;
343 int tx_curr_desc;
344 int tx_used_desc;
fbd6a754 345
5daffe94 346 struct tx_desc *tx_desc_area;
fbd6a754
LB		 347 dma_addr_t tx_desc_dma;
348 int tx_desc_area_size;
99ab08e0
LB		 349
350 struct sk_buff_head tx_skb;
8fd89211
LB		 351
352 unsigned long tx_packets;
353 unsigned long tx_bytes;
354 unsigned long tx_dropped;
13d64285
LB		 355};
356
357struct mv643xx_eth_private {
358 struct mv643xx_eth_shared_private *shared;
37a6084f 359 void __iomem *base;
fc32b0e2 360 int port_num;
13d64285 361
fc32b0e2 362 struct net_device *dev;
fbd6a754 363
ed94493f 364 struct phy_device *phy;
fbd6a754 365
4ff3495a
LB		 366 struct timer_list mib_counters_timer;
367 spinlock_t mib_counters_lock;
fc32b0e2 368 struct mib_counters mib_counters;
4ff3495a 369
fc32b0e2 370 struct work_struct tx_timeout_task;
8a578111 371
1fa38c58
LB		 372 struct napi_struct napi;
373 u8 work_link;
374 u8 work_tx;
375 u8 work_tx_end;
376 u8 work_rx;
377 u8 work_rx_refill;
378 u8 work_rx_oom;
379
2bcb4b0f
LB		 380 int skb_size;
381 struct sk_buff_head rx_recycle;
382
8a578111
LB		 383 /*
384 * RX state.
385 */
386 int default_rx_ring_size;
387 unsigned long rx_desc_sram_addr;
388 int rx_desc_sram_size;
f7981c1c 389 int rxq_count;
2257e05c 390 struct timer_list rx_oom;
64da80a2 391 struct rx_queue rxq[8];
13d64285
LB		 392
393 /*
394 * TX state.
395 */
396 int default_tx_ring_size;
397 unsigned long tx_desc_sram_addr;
398 int tx_desc_sram_size;
f7981c1c 399 int txq_count;
3d6b35bc 400 struct tx_queue txq[8];
fbd6a754 401};
1da177e4 402
fbd6a754 403
c9df406f 404/* port register accessors **************************************************/
e5371493 405static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
c9df406f 406{
cc9754b3 407 return readl(mp->shared->base + offset);
c9df406f 408}
fbd6a754 409
37a6084f
LB		 410static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset)
411{
412 return readl(mp->base + offset);
413}
414
e5371493 415static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
c9df406f 416{
cc9754b3 417 writel(data, mp->shared->base + offset);
c9df406f 418}
fbd6a754 419
37a6084f
LB		 420static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)
421{
422 writel(data, mp->base + offset);
423}
424
fbd6a754 425
c9df406f 426/* rxq/txq helper functions *************************************************/
8a578111 427static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
c9df406f 428{
64da80a2 429 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
c9df406f 430}
fbd6a754 431
13d64285
LB		 432static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
433{
3d6b35bc 434 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
13d64285
LB		 435}
436
8a578111 437static void rxq_enable(struct rx_queue *rxq)
c9df406f 438{
8a578111 439 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
37a6084f 440 wrlp(mp, RXQ_COMMAND, 1 << rxq->index);
8a578111 441}
1da177e4 442
8a578111
LB		 443static void rxq_disable(struct rx_queue *rxq)
444{
445 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
64da80a2 446 u8 mask = 1 << rxq->index;
1da177e4 447
37a6084f
LB		 448 wrlp(mp, RXQ_COMMAND, mask << 8);
449 while (rdlp(mp, RXQ_COMMAND) & mask)
8a578111 450 udelay(10);
c9df406f
LB		 451}
452
6b368f68
LB		 453static void txq_reset_hw_ptr(struct tx_queue *txq)
454{
455 struct mv643xx_eth_private *mp = txq_to_mp(txq);
6b368f68
LB		 456 u32 addr;
457
458 addr = (u32)txq->tx_desc_dma;
459 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
37a6084f 460 wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);
6b368f68
LB		 461}
462
13d64285 463static void txq_enable(struct tx_queue *txq)
1da177e4 464{
13d64285 465 struct mv643xx_eth_private *mp = txq_to_mp(txq);
37a6084f 466 wrlp(mp, TXQ_COMMAND, 1 << txq->index);
1da177e4
LT		 467}
468
13d64285 469static void txq_disable(struct tx_queue *txq)
1da177e4 470{
13d64285 471 struct mv643xx_eth_private *mp = txq_to_mp(txq);
3d6b35bc 472 u8 mask = 1 << txq->index;
c9df406f 473
37a6084f
LB		 474 wrlp(mp, TXQ_COMMAND, mask << 8);
475 while (rdlp(mp, TXQ_COMMAND) & mask)
13d64285
LB		 476 udelay(10);
477}
478
1fa38c58 479static void txq_maybe_wake(struct tx_queue *txq)
13d64285
LB		 480{
481 struct mv643xx_eth_private *mp = txq_to_mp(txq);
e5ef1de1 482 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
3d6b35bc 483
8fd89211
LB		 484 if (netif_tx_queue_stopped(nq)) {
485 __netif_tx_lock(nq, smp_processor_id());
486 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
487 netif_tx_wake_queue(nq);
488 __netif_tx_unlock(nq);
489 }
1da177e4
LT		 490}
491
c9df406f 492
1fa38c58 493/* rx napi ******************************************************************/
8a578111 494static int rxq_process(struct rx_queue *rxq, int budget)
1da177e4 495{
8a578111
LB		 496 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
497 struct net_device_stats *stats = &mp->dev->stats;
498 int rx;
1da177e4 499
8a578111 500 rx = 0;
9e1f3772 501 while (rx < budget && rxq->rx_desc_count) {
fc32b0e2 502 struct rx_desc *rx_desc;
96587661 503 unsigned int cmd_sts;
fc32b0e2 504 struct sk_buff *skb;
6b8f90c2 505 u16 byte_cnt;
ff561eef 506
8a578111 507 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
1da177e4 508
96587661 509 cmd_sts = rx_desc->cmd_sts;
2257e05c 510 if (cmd_sts & BUFFER_OWNED_BY_DMA)
96587661 511 break;
96587661 512 rmb();
1da177e4 513
8a578111
LB		 514 skb = rxq->rx_skb[rxq->rx_curr_desc];
515 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
ff561eef 516
9da78745
LB		 517 rxq->rx_curr_desc++;
518 if (rxq->rx_curr_desc == rxq->rx_ring_size)
519 rxq->rx_curr_desc = 0;
ff561eef 520
3a499481 521 dma_unmap_single(NULL, rx_desc->buf_ptr,
abe78717 522 rx_desc->buf_size, DMA_FROM_DEVICE);
8a578111
LB		 523 rxq->rx_desc_count--;
524 rx++;
b1dd9ca1 525
1fa38c58
LB		 526 mp->work_rx_refill |= 1 << rxq->index;
527
6b8f90c2
LB		 528 byte_cnt = rx_desc->byte_cnt;
529
468d09f8
DF		 530 /*
531 * Update statistics.
fc32b0e2
LB		 532 *
533 * Note that the descriptor byte count includes 2 dummy
534 * bytes automatically inserted by the hardware at the
535 * start of the packet (which we don't count), and a 4
536 * byte CRC at the end of the packet (which we do count).
468d09f8 537 */
1da177e4 538 stats->rx_packets++;
6b8f90c2 539 stats->rx_bytes += byte_cnt - 2;
96587661 540
1da177e4 541 /*
fc32b0e2
LB		 542 * In case we received a packet without first / last bits
543 * on, or the error summary bit is set, the packet needs
544 * to be dropped.
1da177e4 545 */
96587661 546 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
cc9754b3 547 (RX_FIRST_DESC | RX_LAST_DESC))
96587661 548 || (cmd_sts & ERROR_SUMMARY)) {
1da177e4 549 stats->rx_dropped++;
fc32b0e2 550
96587661 551 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
cc9754b3 552 (RX_FIRST_DESC | RX_LAST_DESC)) {
1da177e4 553 if (net_ratelimit())
fc32b0e2
LB		 554 dev_printk(KERN_ERR, &mp->dev->dev,
555 "received packet spanning "
556 "multiple descriptors\n");
1da177e4 557 }
fc32b0e2 558
96587661 559 if (cmd_sts & ERROR_SUMMARY)
1da177e4
LT		 560 stats->rx_errors++;
561
78fff83b 562 dev_kfree_skb(skb);
1da177e4
LT		 563 } else {
564 /*
565 * The -4 is for the CRC in the trailer of the
566 * received packet
567 */
6b8f90c2 568 skb_put(skb, byte_cnt - 2 - 4);
1da177e4 569
170e7108 570 if (cmd_sts & LAYER_4_CHECKSUM_OK)
1da177e4 571 skb->ip_summed = CHECKSUM_UNNECESSARY;
8a578111 572 skb->protocol = eth_type_trans(skb, mp->dev);
1da177e4 573 netif_receive_skb(skb);
1da177e4
LT		 574 }
575 }
fc32b0e2 576
1fa38c58
LB		 577 if (rx < budget)
578 mp->work_rx &= ~(1 << rxq->index);
579
8a578111 580 return rx;
1da177e4
LT		 581}
582
1fa38c58 583static int rxq_refill(struct rx_queue *rxq, int budget)
d0412d96 584{
1fa38c58 585 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1fa38c58 586 int refilled;
8a578111 587
1fa38c58
LB		 588 refilled = 0;
589 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
590 struct sk_buff *skb;
591 int unaligned;
592 int rx;
d0412d96 593
2bcb4b0f
LB		 594 skb = __skb_dequeue(&mp->rx_recycle);
595 if (skb == NULL)
596 skb = dev_alloc_skb(mp->skb_size +
597 dma_get_cache_alignment() - 1);
598
1fa38c58
LB		 599 if (skb == NULL) {
600 mp->work_rx_oom |= 1 << rxq->index;
601 goto oom;
602 }
d0412d96 603
1fa38c58
LB		 604 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
605 if (unaligned)
606 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
2257e05c 607
1fa38c58
LB		 608 refilled++;
609 rxq->rx_desc_count++;
c9df406f 610
1fa38c58
LB		 611 rx = rxq->rx_used_desc++;
612 if (rxq->rx_used_desc == rxq->rx_ring_size)
613 rxq->rx_used_desc = 0;
2257e05c 614
1fa38c58 615 rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
2bcb4b0f
LB		 616 mp->skb_size, DMA_FROM_DEVICE);
617 rxq->rx_desc_area[rx].buf_size = mp->skb_size;
1fa38c58
LB		 618 rxq->rx_skb[rx] = skb;
619 wmb();
620 rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
621 RX_ENABLE_INTERRUPT;
622 wmb();
2257e05c 623
1fa38c58
LB		 624 /*
625 * The hardware automatically prepends 2 bytes of
626 * dummy data to each received packet, so that the
627 * IP header ends up 16-byte aligned.
628 */
629 skb_reserve(skb, 2);
630 }
631
632 if (refilled < budget)
633 mp->work_rx_refill &= ~(1 << rxq->index);
634
635oom:
636 return refilled;
d0412d96
JC		 637}
638
c9df406f
LB		 639
640/* tx ***********************************************************************/
c9df406f 641static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1da177e4 642{
13d64285 643 int frag;
1da177e4 644
c9df406f 645 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
13d64285
LB		 646 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
647 if (fragp->size <= 8 && fragp->page_offset & 7)
c9df406f 648 return 1;
1da177e4 649 }
13d64285 650
c9df406f
LB		 651 return 0;
652}
7303fde8 653
13d64285 654static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
c9df406f 655{
13d64285 656 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 657 int frag;
1da177e4 658
13d64285
LB		 659 for (frag = 0; frag < nr_frags; frag++) {
660 skb_frag_t *this_frag;
661 int tx_index;
662 struct tx_desc *desc;
663
664 this_frag = &skb_shinfo(skb)->frags[frag];
66823b92
LB		 665 tx_index = txq->tx_curr_desc++;
666 if (txq->tx_curr_desc == txq->tx_ring_size)
667 txq->tx_curr_desc = 0;
13d64285
LB		 668 desc = &txq->tx_desc_area[tx_index];
669
670 /*
671 * The last fragment will generate an interrupt
672 * which will free the skb on TX completion.
673 */
674 if (frag == nr_frags - 1) {
675 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
676 ZERO_PADDING | TX_LAST_DESC |
677 TX_ENABLE_INTERRUPT;
13d64285
LB		 678 } else {
679 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
13d64285
LB		 680 }
681
c9df406f
LB		 682 desc->l4i_chk = 0;
683 desc->byte_cnt = this_frag->size;
684 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
685 this_frag->page_offset,
686 this_frag->size,
687 DMA_TO_DEVICE);
688 }
1da177e4
LT		 689}
690
c9df406f
LB		 691static inline __be16 sum16_as_be(__sum16 sum)
692{
693 return (__force __be16)sum;
694}
1da177e4 695
4df89bd5 696static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
1da177e4 697{
8fa89bf5 698 struct mv643xx_eth_private *mp = txq_to_mp(txq);
13d64285 699 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 700 int tx_index;
cc9754b3 701 struct tx_desc *desc;
c9df406f 702 u32 cmd_sts;
4df89bd5 703 u16 l4i_chk;
c9df406f 704 int length;
1da177e4 705
cc9754b3 706 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
4df89bd5 707 l4i_chk = 0;
c9df406f
LB		 708
709 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4df89bd5 710 int tag_bytes;
e32b6617
LB		 711
712 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
713 skb->protocol != htons(ETH_P_8021Q));
c9df406f 714
4df89bd5
LB		 715 tag_bytes = (void *)ip_hdr(skb) - (void *)skb->data - ETH_HLEN;
716 if (unlikely(tag_bytes & ~12)) {
717 if (skb_checksum_help(skb) == 0)
718 goto no_csum;
719 kfree_skb(skb);
720 return 1;
721 }
c9df406f 722
4df89bd5 723 if (tag_bytes & 4)
e32b6617 724 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
4df89bd5 725 if (tag_bytes & 8)
e32b6617 726 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
4df89bd5
LB		 727
728 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
729 GEN_IP_V4_CHECKSUM |
730 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
e32b6617 731
c9df406f
LB		 732 switch (ip_hdr(skb)->protocol) {
733 case IPPROTO_UDP:
cc9754b3 734 cmd_sts |= UDP_FRAME;
4df89bd5 735 l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
c9df406f
LB		 736 break;
737 case IPPROTO_TCP:
4df89bd5 738 l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
c9df406f
LB		 739 break;
740 default:
741 BUG();
742 }
743 } else {
4df89bd5 744no_csum:
c9df406f 745 /* Errata BTS #50, IHL must be 5 if no HW checksum */
cc9754b3 746 cmd_sts |= 5 << TX_IHL_SHIFT;
c9df406f
LB		 747 }
748
66823b92
LB		 749 tx_index = txq->tx_curr_desc++;
750 if (txq->tx_curr_desc == txq->tx_ring_size)
751 txq->tx_curr_desc = 0;
4df89bd5
LB		 752 desc = &txq->tx_desc_area[tx_index];
753
754 if (nr_frags) {
755 txq_submit_frag_skb(txq, skb);
756 length = skb_headlen(skb);
757 } else {
758 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
759 length = skb->len;
760 }
761
762 desc->l4i_chk = l4i_chk;
763 desc->byte_cnt = length;
764 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
765
99ab08e0
LB		 766 __skb_queue_tail(&txq->tx_skb, skb);
767
c9df406f
LB		 768 /* ensure all other descriptors are written before first cmd_sts */
769 wmb();
770 desc->cmd_sts = cmd_sts;
771
1fa38c58
LB		 772 /* clear TX_END status */
773 mp->work_tx_end &= ~(1 << txq->index);
8fa89bf5 774
c9df406f
LB		 775 /* ensure all descriptors are written before poking hardware */
776 wmb();
13d64285 777 txq_enable(txq);
c9df406f 778
13d64285 779 txq->tx_desc_count += nr_frags + 1;
4df89bd5
LB		 780
781 return 0;
1da177e4 782}
1da177e4 783
fc32b0e2 784static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 785{
e5371493 786 struct mv643xx_eth_private *mp = netdev_priv(dev);
e5ef1de1 787 int queue;
13d64285 788 struct tx_queue *txq;
e5ef1de1 789 struct netdev_queue *nq;
afdb57a2 790
8fd89211
LB		 791 queue = skb_get_queue_mapping(skb);
792 txq = mp->txq + queue;
793 nq = netdev_get_tx_queue(dev, queue);
794
c9df406f 795 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
8fd89211 796 txq->tx_dropped++;
fc32b0e2
LB		 797 dev_printk(KERN_DEBUG, &dev->dev,
798 "failed to linearize skb with tiny "
799 "unaligned fragment\n");
c9df406f
LB		 800 return NETDEV_TX_BUSY;
801 }
802
17cd0a59 803 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
e5ef1de1
LB		 804 if (net_ratelimit())
805 dev_printk(KERN_ERR, &dev->dev, "tx queue full?!\n");
3d6b35bc
LB		 806 kfree_skb(skb);
807 return NETDEV_TX_OK;
c9df406f
LB		 808 }
809
4df89bd5
LB		 810 if (!txq_submit_skb(txq, skb)) {
811 int entries_left;
812
813 txq->tx_bytes += skb->len;
814 txq->tx_packets++;
815 dev->trans_start = jiffies;
c9df406f 816
4df89bd5
LB		 817 entries_left = txq->tx_ring_size - txq->tx_desc_count;
818 if (entries_left < MAX_SKB_FRAGS + 1)
819 netif_tx_stop_queue(nq);
820 }
c9df406f 821
c9df406f 822 return NETDEV_TX_OK;
1da177e4
LT		 823}
824
c9df406f 825
1fa38c58
LB		 826/* tx napi ******************************************************************/
827static void txq_kick(struct tx_queue *txq)
828{
829 struct mv643xx_eth_private *mp = txq_to_mp(txq);
8fd89211 830 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1fa38c58
LB		 831 u32 hw_desc_ptr;
832 u32 expected_ptr;
833
8fd89211 834 __netif_tx_lock(nq, smp_processor_id());
1fa38c58 835
37a6084f 836 if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
1fa38c58
LB		 837 goto out;
838
37a6084f 839 hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
1fa38c58
LB		 840 expected_ptr = (u32)txq->tx_desc_dma +
841 txq->tx_curr_desc * sizeof(struct tx_desc);
842
843 if (hw_desc_ptr != expected_ptr)
844 txq_enable(txq);
845
846out:
8fd89211 847 __netif_tx_unlock(nq);
1fa38c58
LB		 848
849 mp->work_tx_end &= ~(1 << txq->index);
850}
851
852static int txq_reclaim(struct tx_queue *txq, int budget, int force)
853{
854 struct mv643xx_eth_private *mp = txq_to_mp(txq);
8fd89211 855 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1fa38c58
LB		 856 int reclaimed;
857
8fd89211 858 __netif_tx_lock(nq, smp_processor_id());
1fa38c58
LB		 859
860 reclaimed = 0;
861 while (reclaimed < budget && txq->tx_desc_count > 0) {
862 int tx_index;
863 struct tx_desc *desc;
864 u32 cmd_sts;
865 struct sk_buff *skb;
1fa38c58
LB		 866
867 tx_index = txq->tx_used_desc;
868 desc = &txq->tx_desc_area[tx_index];
869 cmd_sts = desc->cmd_sts;
870
871 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
872 if (!force)
873 break;
874 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
875 }
876
877 txq->tx_used_desc = tx_index + 1;
878 if (txq->tx_used_desc == txq->tx_ring_size)
879 txq->tx_used_desc = 0;
880
881 reclaimed++;
882 txq->tx_desc_count--;
883
99ab08e0
LB		 884 skb = NULL;
885 if (cmd_sts & TX_LAST_DESC)
886 skb = __skb_dequeue(&txq->tx_skb);
1fa38c58
LB		 887
888 if (cmd_sts & ERROR_SUMMARY) {
889 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
890 mp->dev->stats.tx_errors++;
891 }
892
a418950c
LB		 893 if (cmd_sts & TX_FIRST_DESC) {
894 dma_unmap_single(NULL, desc->buf_ptr,
895 desc->byte_cnt, DMA_TO_DEVICE);
896 } else {
897 dma_unmap_page(NULL, desc->buf_ptr,
898 desc->byte_cnt, DMA_TO_DEVICE);
899 }
1fa38c58 900
2bcb4b0f
LB		 901 if (skb != NULL) {
902 if (skb_queue_len(&mp->rx_recycle) <
903 mp->default_rx_ring_size &&
904 skb_recycle_check(skb, mp->skb_size))
905 __skb_queue_head(&mp->rx_recycle, skb);
906 else
907 dev_kfree_skb(skb);
908 }
1fa38c58
LB		 909 }
910
8fd89211
LB		 911 __netif_tx_unlock(nq);
912
1fa38c58
LB		 913 if (reclaimed < budget)
914 mp->work_tx &= ~(1 << txq->index);
915
1fa38c58
LB		 916 return reclaimed;
917}
918
919
89df5fdc
LB		 920/* tx rate control **********************************************************/
921/*
922 * Set total maximum TX rate (shared by all TX queues for this port)
923 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
924 */
925static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
926{
927 int token_rate;
928 int mtu;
929 int bucket_size;
930
931 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
932 if (token_rate > 1023)
933 token_rate = 1023;
934
935 mtu = (mp->dev->mtu + 255) >> 8;
936 if (mtu > 63)
937 mtu = 63;
938
939 bucket_size = (burst + 255) >> 8;
940 if (bucket_size > 65535)
941 bucket_size = 65535;
942
457b1d5a
LB		 943 switch (mp->shared->tx_bw_control) {
944 case TX_BW_CONTROL_OLD_LAYOUT:
37a6084f
LB		 945 wrlp(mp, TX_BW_RATE, token_rate);
946 wrlp(mp, TX_BW_MTU, mtu);
947 wrlp(mp, TX_BW_BURST, bucket_size);
457b1d5a
LB		 948 break;
949 case TX_BW_CONTROL_NEW_LAYOUT:
37a6084f
LB		 950 wrlp(mp, TX_BW_RATE_MOVED, token_rate);
951 wrlp(mp, TX_BW_MTU_MOVED, mtu);
952 wrlp(mp, TX_BW_BURST_MOVED, bucket_size);
457b1d5a 953 break;
1e881592 954 }
89df5fdc
LB		 955}
956
957static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
958{
959 struct mv643xx_eth_private *mp = txq_to_mp(txq);
960 int token_rate;
961 int bucket_size;
962
963 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
964 if (token_rate > 1023)
965 token_rate = 1023;
966
967 bucket_size = (burst + 255) >> 8;
968 if (bucket_size > 65535)
969 bucket_size = 65535;
970
37a6084f
LB		 971 wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);
972 wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);
89df5fdc
LB		 973}
974
975static void txq_set_fixed_prio_mode(struct tx_queue *txq)
976{
977 struct mv643xx_eth_private *mp = txq_to_mp(txq);
978 int off;
979 u32 val;
980
981 /*
982 * Turn on fixed priority mode.
983 */
457b1d5a
LB		 984 off = 0;
985 switch (mp->shared->tx_bw_control) {
986 case TX_BW_CONTROL_OLD_LAYOUT:
37a6084f 987 off = TXQ_FIX_PRIO_CONF;
457b1d5a
LB		 988 break;
989 case TX_BW_CONTROL_NEW_LAYOUT:
37a6084f 990 off = TXQ_FIX_PRIO_CONF_MOVED;
457b1d5a
LB		 991 break;
992 }
89df5fdc 993
457b1d5a 994 if (off) {
37a6084f 995 val = rdlp(mp, off);
457b1d5a 996 val |= 1 << txq->index;
37a6084f 997 wrlp(mp, off, val);
457b1d5a 998 }
89df5fdc
LB		 999}
1000
1001static void txq_set_wrr(struct tx_queue *txq, int weight)
1002{
1003 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1004 int off;
1005 u32 val;
1006
1007 /*
1008 * Turn off fixed priority mode.
1009 */
457b1d5a
LB		 1010 off = 0;
1011 switch (mp->shared->tx_bw_control) {
1012 case TX_BW_CONTROL_OLD_LAYOUT:
37a6084f 1013 off = TXQ_FIX_PRIO_CONF;
457b1d5a
LB		 1014 break;
1015 case TX_BW_CONTROL_NEW_LAYOUT:
37a6084f 1016 off = TXQ_FIX_PRIO_CONF_MOVED;
457b1d5a
LB		 1017 break;
1018 }
89df5fdc 1019
457b1d5a 1020 if (off) {
37a6084f 1021 val = rdlp(mp, off);
457b1d5a 1022 val &= ~(1 << txq->index);
37a6084f 1023 wrlp(mp, off, val);
89df5fdc 1024
457b1d5a
LB		 1025 /*
1026 * Configure WRR weight for this queue.
1027 */
89df5fdc 1028
37a6084f 1029 val = rdlp(mp, off);
457b1d5a 1030 val = (val & ~0xff) | (weight & 0xff);
37a6084f 1031 wrlp(mp, TXQ_BW_WRR_CONF(txq->index), val);
457b1d5a 1032 }
89df5fdc
LB		 1033}
1034
1035
c9df406f 1036/* mii management interface *************************************************/
45c5d3bc
LB		 1037static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id)
1038{
1039 struct mv643xx_eth_shared_private *msp = dev_id;
1040
1041 if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) {
1042 writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE);
1043 wake_up(&msp->smi_busy_wait);
1044 return IRQ_HANDLED;
1045 }
1046
1047 return IRQ_NONE;
1048}
c9df406f 1049
45c5d3bc 1050static int smi_is_done(struct mv643xx_eth_shared_private *msp)
1da177e4 1051{
45c5d3bc
LB		 1052 return !(readl(msp->base + SMI_REG) & SMI_BUSY);
1053}
1da177e4 1054
45c5d3bc
LB		 1055static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
1056{
1057 if (msp->err_interrupt == NO_IRQ) {
1058 int i;
c9df406f 1059
45c5d3bc
LB		 1060 for (i = 0; !smi_is_done(msp); i++) {
1061 if (i == 10)
1062 return -ETIMEDOUT;
1063 msleep(10);
c9df406f 1064 }
45c5d3bc
LB		 1065
1066 return 0;
1067 }
1068
ee04448d
LB		 1069 if (!smi_is_done(msp)) {
1070 wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
1071 msecs_to_jiffies(100));
1072 if (!smi_is_done(msp))
1073 return -ETIMEDOUT;
1074 }
45c5d3bc
LB		 1075
1076 return 0;
1077}
1078
ed94493f 1079static int smi_bus_read(struct mii_bus *bus, int addr, int reg)
45c5d3bc 1080{
ed94493f 1081 struct mv643xx_eth_shared_private *msp = bus->priv;
45c5d3bc
LB		 1082 void __iomem *smi_reg = msp->base + SMI_REG;
1083 int ret;
1084
45c5d3bc 1085 if (smi_wait_ready(msp)) {
10a9948d 1086 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
ed94493f 1087 return -ETIMEDOUT;
1da177e4
LT		 1088 }
1089
fc32b0e2 1090 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1da177e4 1091
45c5d3bc 1092 if (smi_wait_ready(msp)) {
10a9948d 1093 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
ed94493f 1094 return -ETIMEDOUT;
45c5d3bc
LB		 1095 }
1096
1097 ret = readl(smi_reg);
1098 if (!(ret & SMI_READ_VALID)) {
10a9948d 1099 printk(KERN_WARNING "mv643xx_eth: SMI bus read not valid\n");
ed94493f 1100 return -ENODEV;
c9df406f
LB		 1101 }
1102
ed94493f 1103 return ret & 0xffff;
1da177e4
LT		 1104}
1105
ed94493f 1106static int smi_bus_write(struct mii_bus *bus, int addr, int reg, u16 val)
1da177e4 1107{
ed94493f 1108 struct mv643xx_eth_shared_private *msp = bus->priv;
45c5d3bc 1109 void __iomem *smi_reg = msp->base + SMI_REG;
1da177e4 1110
45c5d3bc 1111 if (smi_wait_ready(msp)) {
10a9948d 1112 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
45c5d3bc 1113 return -ETIMEDOUT;
1da177e4
LT		 1114 }
1115
fc32b0e2 1116 writel(SMI_OPCODE_WRITE | (reg << 21) |
ed94493f 1117 (addr << 16) | (val & 0xffff), smi_reg);
45c5d3bc 1118
ed94493f 1119 if (smi_wait_ready(msp)) {
10a9948d 1120 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
ed94493f
LB		 1121 return -ETIMEDOUT;
1122 }
45c5d3bc
LB		 1123
1124 return 0;
c9df406f 1125}
1da177e4 1126
c9df406f 1127
8fd89211
LB		 1128/* statistics ***************************************************************/
1129static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1130{
1131 struct mv643xx_eth_private *mp = netdev_priv(dev);
1132 struct net_device_stats *stats = &dev->stats;
1133 unsigned long tx_packets = 0;
1134 unsigned long tx_bytes = 0;
1135 unsigned long tx_dropped = 0;
1136 int i;
1137
1138 for (i = 0; i < mp->txq_count; i++) {
1139 struct tx_queue *txq = mp->txq + i;
1140
1141 tx_packets += txq->tx_packets;
1142 tx_bytes += txq->tx_bytes;
1143 tx_dropped += txq->tx_dropped;
1144 }
1145
1146 stats->tx_packets = tx_packets;
1147 stats->tx_bytes = tx_bytes;
1148 stats->tx_dropped = tx_dropped;
1149
1150 return stats;
1151}
1152
fc32b0e2 1153static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
c9df406f 1154{
fc32b0e2 1155 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1da177e4
LT		 1156}
1157
fc32b0e2 1158static void mib_counters_clear(struct mv643xx_eth_private *mp)
d0412d96 1159{
fc32b0e2
LB		 1160 int i;
1161
1162 for (i = 0; i < 0x80; i += 4)
1163 mib_read(mp, i);
c9df406f 1164}
d0412d96 1165
fc32b0e2 1166static void mib_counters_update(struct mv643xx_eth_private *mp)
c9df406f 1167{
e5371493 1168 struct mib_counters *p = &mp->mib_counters;
4b8e3655 1169
4ff3495a 1170 spin_lock(&mp->mib_counters_lock);
fc32b0e2
LB		 1171 p->good_octets_received += mib_read(mp, 0x00);
1172 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
1173 p->bad_octets_received += mib_read(mp, 0x08);
1174 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1175 p->good_frames_received += mib_read(mp, 0x10);
1176 p->bad_frames_received += mib_read(mp, 0x14);
1177 p->broadcast_frames_received += mib_read(mp, 0x18);
1178 p->multicast_frames_received += mib_read(mp, 0x1c);
1179 p->frames_64_octets += mib_read(mp, 0x20);
1180 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1181 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1182 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1183 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1184 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1185 p->good_octets_sent += mib_read(mp, 0x38);
1186 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1187 p->good_frames_sent += mib_read(mp, 0x40);
1188 p->excessive_collision += mib_read(mp, 0x44);
1189 p->multicast_frames_sent += mib_read(mp, 0x48);
1190 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1191 p->unrec_mac_control_received += mib_read(mp, 0x50);
1192 p->fc_sent += mib_read(mp, 0x54);
1193 p->good_fc_received += mib_read(mp, 0x58);
1194 p->bad_fc_received += mib_read(mp, 0x5c);
1195 p->undersize_received += mib_read(mp, 0x60);
1196 p->fragments_received += mib_read(mp, 0x64);
1197 p->oversize_received += mib_read(mp, 0x68);
1198 p->jabber_received += mib_read(mp, 0x6c);
1199 p->mac_receive_error += mib_read(mp, 0x70);
1200 p->bad_crc_event += mib_read(mp, 0x74);
1201 p->collision += mib_read(mp, 0x78);
1202 p->late_collision += mib_read(mp, 0x7c);
4ff3495a
LB		 1203 spin_unlock(&mp->mib_counters_lock);
1204
1205 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1206}
1207
1208static void mib_counters_timer_wrapper(unsigned long _mp)
1209{
1210 struct mv643xx_eth_private *mp = (void *)_mp;
1211
1212 mib_counters_update(mp);
d0412d96
JC		 1213}
1214
c9df406f
LB		 1215
1216/* ethtool ******************************************************************/
e5371493 1217struct mv643xx_eth_stats {
c9df406f
LB		 1218 char stat_string[ETH_GSTRING_LEN];
1219 int sizeof_stat;
16820054
LB		 1220 int netdev_off;
1221 int mp_off;
c9df406f
LB		 1222};
1223
16820054
LB		 1224#define SSTAT(m) \
1225 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1226 offsetof(struct net_device, stats.m), -1 }
1227
1228#define MIBSTAT(m) \
1229 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1230 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1231
1232static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1233 SSTAT(rx_packets),
1234 SSTAT(tx_packets),
1235 SSTAT(rx_bytes),
1236 SSTAT(tx_bytes),
1237 SSTAT(rx_errors),
1238 SSTAT(tx_errors),
1239 SSTAT(rx_dropped),
1240 SSTAT(tx_dropped),
1241 MIBSTAT(good_octets_received),
1242 MIBSTAT(bad_octets_received),
1243 MIBSTAT(internal_mac_transmit_err),
1244 MIBSTAT(good_frames_received),
1245 MIBSTAT(bad_frames_received),
1246 MIBSTAT(broadcast_frames_received),
1247 MIBSTAT(multicast_frames_received),
1248 MIBSTAT(frames_64_octets),
1249 MIBSTAT(frames_65_to_127_octets),
1250 MIBSTAT(frames_128_to_255_octets),
1251 MIBSTAT(frames_256_to_511_octets),
1252 MIBSTAT(frames_512_to_1023_octets),
1253 MIBSTAT(frames_1024_to_max_octets),
1254 MIBSTAT(good_octets_sent),
1255 MIBSTAT(good_frames_sent),
1256 MIBSTAT(excessive_collision),
1257 MIBSTAT(multicast_frames_sent),
1258 MIBSTAT(broadcast_frames_sent),
1259 MIBSTAT(unrec_mac_control_received),
1260 MIBSTAT(fc_sent),
1261 MIBSTAT(good_fc_received),
1262 MIBSTAT(bad_fc_received),
1263 MIBSTAT(undersize_received),
1264 MIBSTAT(fragments_received),
1265 MIBSTAT(oversize_received),
1266 MIBSTAT(jabber_received),
1267 MIBSTAT(mac_receive_error),
1268 MIBSTAT(bad_crc_event),
1269 MIBSTAT(collision),
1270 MIBSTAT(late_collision),
c9df406f
LB		 1271};
1272
10a9948d
LB		 1273static int
1274mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
d0412d96 1275{
e5371493 1276 struct mv643xx_eth_private *mp = netdev_priv(dev);
d0412d96
JC		 1277 int err;
1278
ed94493f
LB		 1279 err = phy_read_status(mp->phy);
1280 if (err == 0)
1281 err = phy_ethtool_gset(mp->phy, cmd);
d0412d96 1282
fc32b0e2
LB		 1283 /*
1284 * The MAC does not support 1000baseT_Half.
1285 */
d0412d96
JC		 1286 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1287 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1288
1289 return err;
1290}
1291
10a9948d
LB		 1292static int
1293mv643xx_eth_get_settings_phyless(struct net_device *dev,
1294 struct ethtool_cmd *cmd)
bedfe324 1295{
81600eea
LB		 1296 struct mv643xx_eth_private *mp = netdev_priv(dev);
1297 u32 port_status;
1298
37a6084f 1299 port_status = rdlp(mp, PORT_STATUS);
81600eea 1300
bedfe324
LB		 1301 cmd->supported = SUPPORTED_MII;
1302 cmd->advertising = ADVERTISED_MII;
81600eea
LB		 1303 switch (port_status & PORT_SPEED_MASK) {
1304 case PORT_SPEED_10:
1305 cmd->speed = SPEED_10;
1306 break;
1307 case PORT_SPEED_100:
1308 cmd->speed = SPEED_100;
1309 break;
1310 case PORT_SPEED_1000:
1311 cmd->speed = SPEED_1000;
1312 break;
1313 default:
1314 cmd->speed = -1;
1315 break;
1316 }
1317 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
bedfe324
LB		 1318 cmd->port = PORT_MII;
1319 cmd->phy_address = 0;
1320 cmd->transceiver = XCVR_INTERNAL;
1321 cmd->autoneg = AUTONEG_DISABLE;
1322 cmd->maxtxpkt = 1;
1323 cmd->maxrxpkt = 1;
1324
1325 return 0;
1326}
1327
10a9948d
LB		 1328static int
1329mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4 1330{
e5371493 1331 struct mv643xx_eth_private *mp = netdev_priv(dev);
ab4384a6 1332
fc32b0e2
LB		 1333 /*
1334 * The MAC does not support 1000baseT_Half.
1335 */
1336 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1337
ed94493f 1338 return phy_ethtool_sset(mp->phy, cmd);
c9df406f 1339}
1da177e4 1340
10a9948d
LB		 1341static int
1342mv643xx_eth_set_settings_phyless(struct net_device *dev,
1343 struct ethtool_cmd *cmd)
bedfe324
LB		 1344{
1345 return -EINVAL;
1346}
1347
fc32b0e2
LB		 1348static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1349 struct ethtool_drvinfo *drvinfo)
c9df406f 1350{
e5371493
LB		 1351 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1352 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
c9df406f 1353 strncpy(drvinfo->fw_version, "N/A", 32);
fc32b0e2 1354 strncpy(drvinfo->bus_info, "platform", 32);
16820054 1355 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
c9df406f 1356}
1da177e4 1357
fc32b0e2 1358static int mv643xx_eth_nway_reset(struct net_device *dev)
c9df406f 1359{
e5371493 1360 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1361
ed94493f 1362 return genphy_restart_aneg(mp->phy);
c9df406f 1363}
1da177e4 1364
bedfe324
LB		 1365static int mv643xx_eth_nway_reset_phyless(struct net_device *dev)
1366{
1367 return -EINVAL;
1368}
1369
c9df406f
LB		 1370static u32 mv643xx_eth_get_link(struct net_device *dev)
1371{
ed94493f 1372 return !!netif_carrier_ok(dev);
bedfe324
LB		 1373}
1374
fc32b0e2
LB		 1375static void mv643xx_eth_get_strings(struct net_device *dev,
1376 uint32_t stringset, uint8_t *data)
c9df406f
LB		 1377{
1378 int i;
1da177e4 1379
fc32b0e2
LB		 1380 if (stringset == ETH_SS_STATS) {
1381 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
c9df406f 1382 memcpy(data + i * ETH_GSTRING_LEN,
16820054 1383 mv643xx_eth_stats[i].stat_string,
e5371493 1384 ETH_GSTRING_LEN);
c9df406f 1385 }
c9df406f
LB		 1386 }
1387}
1da177e4 1388
fc32b0e2
LB		 1389static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1390 struct ethtool_stats *stats,
1391 uint64_t *data)
c9df406f 1392{
b9873841 1393 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 1394 int i;
1da177e4 1395
8fd89211 1396 mv643xx_eth_get_stats(dev);
fc32b0e2 1397 mib_counters_update(mp);
1da177e4 1398
16820054
LB		 1399 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1400 const struct mv643xx_eth_stats *stat;
1401 void *p;
1402
1403 stat = mv643xx_eth_stats + i;
1404
1405 if (stat->netdev_off >= 0)
1406 p = ((void *)mp->dev) + stat->netdev_off;
1407 else
1408 p = ((void *)mp) + stat->mp_off;
1409
1410 data[i] = (stat->sizeof_stat == 8) ?
1411 *(uint64_t *)p : *(uint32_t *)p;
1da177e4 1412 }
c9df406f 1413}
1da177e4 1414
fc32b0e2 1415static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
c9df406f 1416{
fc32b0e2 1417 if (sset == ETH_SS_STATS)
16820054 1418 return ARRAY_SIZE(mv643xx_eth_stats);
fc32b0e2
LB		 1419
1420 return -EOPNOTSUPP;
c9df406f 1421}
1da177e4 1422
e5371493 1423static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
fc32b0e2
LB		 1424 .get_settings = mv643xx_eth_get_settings,
1425 .set_settings = mv643xx_eth_set_settings,
1426 .get_drvinfo = mv643xx_eth_get_drvinfo,
1427 .nway_reset = mv643xx_eth_nway_reset,
1428 .get_link = mv643xx_eth_get_link,
c9df406f 1429 .set_sg = ethtool_op_set_sg,
fc32b0e2
LB		 1430 .get_strings = mv643xx_eth_get_strings,
1431 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
e5371493 1432 .get_sset_count = mv643xx_eth_get_sset_count,
c9df406f 1433};
1da177e4 1434
bedfe324
LB		 1435static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless = {
1436 .get_settings = mv643xx_eth_get_settings_phyless,
1437 .set_settings = mv643xx_eth_set_settings_phyless,
1438 .get_drvinfo = mv643xx_eth_get_drvinfo,
1439 .nway_reset = mv643xx_eth_nway_reset_phyless,
ed94493f 1440 .get_link = mv643xx_eth_get_link,
bedfe324
LB		 1441 .set_sg = ethtool_op_set_sg,
1442 .get_strings = mv643xx_eth_get_strings,
1443 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1444 .get_sset_count = mv643xx_eth_get_sset_count,
1445};
1446
bea3348e 1447
c9df406f 1448/* address handling *********************************************************/
5daffe94 1449static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
c9df406f 1450{
c9df406f
LB		 1451 unsigned int mac_h;
1452 unsigned int mac_l;
1da177e4 1453
37a6084f
LB		 1454 mac_h = rdlp(mp, MAC_ADDR_HIGH);
1455 mac_l = rdlp(mp, MAC_ADDR_LOW);
1da177e4 1456
5daffe94
LB		 1457 addr[0] = (mac_h >> 24) & 0xff;
1458 addr[1] = (mac_h >> 16) & 0xff;
1459 addr[2] = (mac_h >> 8) & 0xff;
1460 addr[3] = mac_h & 0xff;
1461 addr[4] = (mac_l >> 8) & 0xff;
1462 addr[5] = mac_l & 0xff;
c9df406f 1463}
1da177e4 1464
e5371493 1465static void init_mac_tables(struct mv643xx_eth_private *mp)
c9df406f 1466{
fc32b0e2 1467 int i;
1da177e4 1468
fc32b0e2
LB		 1469 for (i = 0; i < 0x100; i += 4) {
1470 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1471 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
c9df406f 1472 }
fc32b0e2
LB		 1473
1474 for (i = 0; i < 0x10; i += 4)
1475 wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
c9df406f 1476}
d0412d96 1477
e5371493 1478static void set_filter_table_entry(struct mv643xx_eth_private *mp,
fc32b0e2 1479 int table, unsigned char entry)
c9df406f
LB		 1480{
1481 unsigned int table_reg;
ab4384a6 1482
c9df406f 1483 /* Set "accepts frame bit" at specified table entry */
fc32b0e2
LB		 1484 table_reg = rdl(mp, table + (entry & 0xfc));
1485 table_reg |= 0x01 << (8 * (entry & 3));
1486 wrl(mp, table + (entry & 0xfc), table_reg);
1da177e4
LT		 1487}
1488
5daffe94 1489static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1da177e4 1490{
c9df406f
LB		 1491 unsigned int mac_h;
1492 unsigned int mac_l;
1493 int table;
1da177e4 1494
fc32b0e2
LB		 1495 mac_l = (addr[4] << 8) | addr[5];
1496 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
ff561eef 1497
37a6084f
LB		 1498 wrlp(mp, MAC_ADDR_LOW, mac_l);
1499 wrlp(mp, MAC_ADDR_HIGH, mac_h);
1da177e4 1500
fc32b0e2 1501 table = UNICAST_TABLE(mp->port_num);
5daffe94 1502 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1da177e4
LT		 1503}
1504
fc32b0e2 1505static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1da177e4 1506{
e5371493 1507 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1508
fc32b0e2
LB		 1509 /* +2 is for the offset of the HW addr type */
1510 memcpy(dev->dev_addr, addr + 2, 6);
1511
cc9754b3
LB		 1512 init_mac_tables(mp);
1513 uc_addr_set(mp, dev->dev_addr);
1da177e4
LT		 1514
1515 return 0;
1516}
1517
69876569
LB		 1518static int addr_crc(unsigned char *addr)
1519{
1520 int crc = 0;
1521 int i;
1522
1523 for (i = 0; i < 6; i++) {
1524 int j;
1525
1526 crc = (crc ^ addr[i]) << 8;
1527 for (j = 7; j >= 0; j--) {
1528 if (crc & (0x100 << j))
1529 crc ^= 0x107 << j;
1530 }
1531 }
1532
1533 return crc;
1534}
1535
fc32b0e2 1536static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1da177e4 1537{
fc32b0e2
LB		 1538 struct mv643xx_eth_private *mp = netdev_priv(dev);
1539 u32 port_config;
1540 struct dev_addr_list *addr;
1541 int i;
c8aaea25 1542
37a6084f 1543 port_config = rdlp(mp, PORT_CONFIG);
fc32b0e2
LB		 1544 if (dev->flags & IFF_PROMISC)
1545 port_config |= UNICAST_PROMISCUOUS_MODE;
1546 else
1547 port_config &= ~UNICAST_PROMISCUOUS_MODE;
37a6084f 1548 wrlp(mp, PORT_CONFIG, port_config);
1da177e4 1549
fc32b0e2
LB		 1550 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1551 int port_num = mp->port_num;
1552 u32 accept = 0x01010101;
c8aaea25 1553
fc32b0e2
LB		 1554 for (i = 0; i < 0x100; i += 4) {
1555 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1556 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
c9df406f
LB		 1557 }
1558 return;
1559 }
c8aaea25 1560
fc32b0e2
LB		 1561 for (i = 0; i < 0x100; i += 4) {
1562 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1563 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1da177e4
LT		 1564 }
1565
fc32b0e2
LB		 1566 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1567 u8 *a = addr->da_addr;
1568 int table;
324ff2c1 1569
fc32b0e2
LB		 1570 if (addr->da_addrlen != 6)
1571 continue;
1da177e4 1572
fc32b0e2
LB		 1573 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1574 table = SPECIAL_MCAST_TABLE(mp->port_num);
1575 set_filter_table_entry(mp, table, a[5]);
1576 } else {
1577 int crc = addr_crc(a);
1da177e4 1578
fc32b0e2
LB		 1579 table = OTHER_MCAST_TABLE(mp->port_num);
1580 set_filter_table_entry(mp, table, crc);
1581 }
1582 }
c9df406f 1583}
c8aaea25 1584
c8aaea25 1585
c9df406f 1586/* rx/tx queue initialisation ***********************************************/
64da80a2 1587static int rxq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1588{
64da80a2 1589 struct rx_queue *rxq = mp->rxq + index;
8a578111
LB		 1590 struct rx_desc *rx_desc;
1591 int size;
c9df406f
LB		 1592 int i;
1593
64da80a2
LB		 1594 rxq->index = index;
1595
8a578111
LB		 1596 rxq->rx_ring_size = mp->default_rx_ring_size;
1597
1598 rxq->rx_desc_count = 0;
1599 rxq->rx_curr_desc = 0;
1600 rxq->rx_used_desc = 0;
1601
1602 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1603
f7981c1c 1604 if (index == 0 && size <= mp->rx_desc_sram_size) {
8a578111
LB		 1605 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1606 mp->rx_desc_sram_size);
1607 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1608 } else {
1609 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1610 &rxq->rx_desc_dma,
1611 GFP_KERNEL);
f7ea3337
PJ		 1612 }
1613
8a578111
LB		 1614 if (rxq->rx_desc_area == NULL) {
1615 dev_printk(KERN_ERR, &mp->dev->dev,
1616 "can't allocate rx ring (%d bytes)\n", size);
1617 goto out;
1618 }
1619 memset(rxq->rx_desc_area, 0, size);
1da177e4 1620
8a578111
LB		 1621 rxq->rx_desc_area_size = size;
1622 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1623 GFP_KERNEL);
1624 if (rxq->rx_skb == NULL) {
1625 dev_printk(KERN_ERR, &mp->dev->dev,
1626 "can't allocate rx skb ring\n");
1627 goto out_free;
1628 }
1629
1630 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1631 for (i = 0; i < rxq->rx_ring_size; i++) {
9da78745
LB		 1632 int nexti;
1633
1634 nexti = i + 1;
1635 if (nexti == rxq->rx_ring_size)
1636 nexti = 0;
1637
8a578111
LB		 1638 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1639 nexti * sizeof(struct rx_desc);
1640 }
1641
8a578111
LB		 1642 return 0;
1643
1644
1645out_free:
f7981c1c 1646 if (index == 0 && size <= mp->rx_desc_sram_size)
8a578111
LB		 1647 iounmap(rxq->rx_desc_area);
1648 else
1649 dma_free_coherent(NULL, size,
1650 rxq->rx_desc_area,
1651 rxq->rx_desc_dma);
1652
1653out:
1654 return -ENOMEM;
c9df406f 1655}
c8aaea25 1656
8a578111 1657static void rxq_deinit(struct rx_queue *rxq)
c9df406f 1658{
8a578111
LB		 1659 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1660 int i;
1661
1662 rxq_disable(rxq);
c8aaea25 1663
8a578111
LB		 1664 for (i = 0; i < rxq->rx_ring_size; i++) {
1665 if (rxq->rx_skb[i]) {
1666 dev_kfree_skb(rxq->rx_skb[i]);
1667 rxq->rx_desc_count--;
1da177e4 1668 }
c8aaea25 1669 }
1da177e4 1670
8a578111
LB		 1671 if (rxq->rx_desc_count) {
1672 dev_printk(KERN_ERR, &mp->dev->dev,
1673 "error freeing rx ring -- %d skbs stuck\n",
1674 rxq->rx_desc_count);
1675 }
1676
f7981c1c 1677 if (rxq->index == 0 &&
64da80a2 1678 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
8a578111 1679 iounmap(rxq->rx_desc_area);
c9df406f 1680 else
8a578111
LB		 1681 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1682 rxq->rx_desc_area, rxq->rx_desc_dma);
1683
1684 kfree(rxq->rx_skb);
c9df406f 1685}
1da177e4 1686
3d6b35bc 1687static int txq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1688{
3d6b35bc 1689 struct tx_queue *txq = mp->txq + index;
13d64285
LB		 1690 struct tx_desc *tx_desc;
1691 int size;
c9df406f 1692 int i;
1da177e4 1693
3d6b35bc
LB		 1694 txq->index = index;
1695
13d64285
LB		 1696 txq->tx_ring_size = mp->default_tx_ring_size;
1697
1698 txq->tx_desc_count = 0;
1699 txq->tx_curr_desc = 0;
1700 txq->tx_used_desc = 0;
1701
1702 size = txq->tx_ring_size * sizeof(struct tx_desc);
1703
f7981c1c 1704 if (index == 0 && size <= mp->tx_desc_sram_size) {
13d64285
LB		 1705 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1706 mp->tx_desc_sram_size);
1707 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1708 } else {
1709 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1710 &txq->tx_desc_dma,
1711 GFP_KERNEL);
1712 }
1713
1714 if (txq->tx_desc_area == NULL) {
1715 dev_printk(KERN_ERR, &mp->dev->dev,
1716 "can't allocate tx ring (%d bytes)\n", size);
99ab08e0 1717 return -ENOMEM;
c9df406f 1718 }
13d64285
LB		 1719 memset(txq->tx_desc_area, 0, size);
1720
1721 txq->tx_desc_area_size = size;
13d64285
LB		 1722
1723 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1724 for (i = 0; i < txq->tx_ring_size; i++) {
6b368f68 1725 struct tx_desc *txd = tx_desc + i;
9da78745
LB		 1726 int nexti;
1727
1728 nexti = i + 1;
1729 if (nexti == txq->tx_ring_size)
1730 nexti = 0;
6b368f68
LB		 1731
1732 txd->cmd_sts = 0;
1733 txd->next_desc_ptr = txq->tx_desc_dma +
13d64285
LB		 1734 nexti * sizeof(struct tx_desc);
1735 }
1736
99ab08e0 1737 skb_queue_head_init(&txq->tx_skb);
c9df406f 1738
99ab08e0 1739 return 0;
c8aaea25 1740}
1da177e4 1741
13d64285 1742static void txq_deinit(struct tx_queue *txq)
c9df406f 1743{
13d64285 1744 struct mv643xx_eth_private *mp = txq_to_mp(txq);
fa3959f4 1745
13d64285 1746 txq_disable(txq);
1fa38c58 1747 txq_reclaim(txq, txq->tx_ring_size, 1);
1da177e4 1748
13d64285 1749 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1da177e4 1750
f7981c1c 1751 if (txq->index == 0 &&
3d6b35bc 1752 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
13d64285 1753 iounmap(txq->tx_desc_area);
c9df406f 1754 else
13d64285
LB		 1755 dma_free_coherent(NULL, txq->tx_desc_area_size,
1756 txq->tx_desc_area, txq->tx_desc_dma);
c9df406f 1757}
1da177e4 1758
1da177e4 1759
c9df406f 1760/* netdev ops and related ***************************************************/
1fa38c58
LB		 1761static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
1762{
1763 u32 int_cause;
1764 u32 int_cause_ext;
1765
37a6084f 1766 int_cause = rdlp(mp, INT_CAUSE) & (INT_TX_END | INT_RX | INT_EXT);
1fa38c58
LB		 1767 if (int_cause == 0)
1768 return 0;
1769
1770 int_cause_ext = 0;
1771 if (int_cause & INT_EXT)
37a6084f 1772 int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
1fa38c58
LB		 1773
1774 int_cause &= INT_TX_END | INT_RX;
1775 if (int_cause) {
37a6084f 1776 wrlp(mp, INT_CAUSE, ~int_cause);
1fa38c58 1777 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
37a6084f 1778 ~(rdlp(mp, TXQ_COMMAND) & 0xff);
1fa38c58
LB		 1779 mp->work_rx |= (int_cause & INT_RX) >> 2;
1780 }
1781
1782 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
1783 if (int_cause_ext) {
37a6084f 1784 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);
1fa38c58
LB		 1785 if (int_cause_ext & INT_EXT_LINK_PHY)
1786 mp->work_link = 1;
1787 mp->work_tx |= int_cause_ext & INT_EXT_TX;
1788 }
1789
1790 return 1;
1791}
1792
1793static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1794{
1795 struct net_device *dev = (struct net_device *)dev_id;
1796 struct mv643xx_eth_private *mp = netdev_priv(dev);
1797
1798 if (unlikely(!mv643xx_eth_collect_events(mp)))
1799 return IRQ_NONE;
1800
37a6084f 1801 wrlp(mp, INT_MASK, 0);
1fa38c58
LB		 1802 napi_schedule(&mp->napi);
1803
1804 return IRQ_HANDLED;
1805}
1806
2f7eb47a
LB		 1807static void handle_link_event(struct mv643xx_eth_private *mp)
1808{
1809 struct net_device *dev = mp->dev;
1810 u32 port_status;
1811 int speed;
1812 int duplex;
1813 int fc;
1814
37a6084f 1815 port_status = rdlp(mp, PORT_STATUS);
2f7eb47a
LB		 1816 if (!(port_status & LINK_UP)) {
1817 if (netif_carrier_ok(dev)) {
1818 int i;
1819
1820 printk(KERN_INFO "%s: link down\n", dev->name);
1821
1822 netif_carrier_off(dev);
2f7eb47a 1823
f7981c1c 1824 for (i = 0; i < mp->txq_count; i++) {
2f7eb47a
LB		 1825 struct tx_queue *txq = mp->txq + i;
1826
1fa38c58 1827 txq_reclaim(txq, txq->tx_ring_size, 1);
f7981c1c 1828 txq_reset_hw_ptr(txq);
2f7eb47a
LB		 1829 }
1830 }
1831 return;
1832 }
1833
1834 switch (port_status & PORT_SPEED_MASK) {
1835 case PORT_SPEED_10:
1836 speed = 10;
1837 break;
1838 case PORT_SPEED_100:
1839 speed = 100;
1840 break;
1841 case PORT_SPEED_1000:
1842 speed = 1000;
1843 break;
1844 default:
1845 speed = -1;
1846 break;
1847 }
1848 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
1849 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
1850
1851 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
1852 "flow control %sabled\n", dev->name,
1853 speed, duplex ? "full" : "half",
1854 fc ? "en" : "dis");
1855
4fdeca3f 1856 if (!netif_carrier_ok(dev))
2f7eb47a 1857 netif_carrier_on(dev);
2f7eb47a
LB		 1858}
1859
1fa38c58 1860static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
c9df406f 1861{
1fa38c58
LB		 1862 struct mv643xx_eth_private *mp;
1863 int work_done;
ce4e2e45 1864
1fa38c58 1865 mp = container_of(napi, struct mv643xx_eth_private, napi);
fc32b0e2 1866
1fa38c58
LB		 1867 mp->work_rx_refill |= mp->work_rx_oom;
1868 mp->work_rx_oom = 0;
1da177e4 1869
1fa38c58
LB		 1870 work_done = 0;
1871 while (work_done < budget) {
1872 u8 queue_mask;
1873 int queue;
1874 int work_tbd;
1875
1876 if (mp->work_link) {
1877 mp->work_link = 0;
1878 handle_link_event(mp);
1879 continue;
1880 }
1da177e4 1881
1fa38c58
LB		 1882 queue_mask = mp->work_tx | mp->work_tx_end |
1883 mp->work_rx | mp->work_rx_refill;
1884 if (!queue_mask) {
1885 if (mv643xx_eth_collect_events(mp))
1886 continue;
1887 break;
1888 }
1da177e4 1889
1fa38c58
LB		 1890 queue = fls(queue_mask) - 1;
1891 queue_mask = 1 << queue;
1892
1893 work_tbd = budget - work_done;
1894 if (work_tbd > 16)
1895 work_tbd = 16;
1896
1897 if (mp->work_tx_end & queue_mask) {
1898 txq_kick(mp->txq + queue);
1899 } else if (mp->work_tx & queue_mask) {
1900 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
1901 txq_maybe_wake(mp->txq + queue);
1902 } else if (mp->work_rx & queue_mask) {
1903 work_done += rxq_process(mp->rxq + queue, work_tbd);
1904 } else if (mp->work_rx_refill & queue_mask) {
1905 work_done += rxq_refill(mp->rxq + queue, work_tbd);
1906 } else {
1907 BUG();
1908 }
84dd619e 1909 }
fc32b0e2 1910
1fa38c58
LB		 1911 if (work_done < budget) {
1912 if (mp->work_rx_oom)
1913 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
1914 napi_complete(napi);
37a6084f 1915 wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT);
226bb6b7 1916 }
3d6b35bc 1917
1fa38c58
LB		 1918 return work_done;
1919}
8fa89bf5 1920
1fa38c58
LB		 1921static inline void oom_timer_wrapper(unsigned long data)
1922{
1923 struct mv643xx_eth_private *mp = (void *)data;
1da177e4 1924
1fa38c58 1925 napi_schedule(&mp->napi);
1da177e4
LT		 1926}
1927
e5371493 1928static void phy_reset(struct mv643xx_eth_private *mp)
1da177e4 1929{
45c5d3bc
LB		 1930 int data;
1931
ed94493f 1932 data = phy_read(mp->phy, MII_BMCR);
45c5d3bc
LB		 1933 if (data < 0)
1934 return;
1da177e4 1935
7f106c1d 1936 data |= BMCR_RESET;
ed94493f 1937 if (phy_write(mp->phy, MII_BMCR, data) < 0)
45c5d3bc 1938 return;
1da177e4 1939
c9df406f 1940 do {
ed94493f 1941 data = phy_read(mp->phy, MII_BMCR);
45c5d3bc 1942 } while (data >= 0 && data & BMCR_RESET);
1da177e4
LT		 1943}
1944
fc32b0e2 1945static void port_start(struct mv643xx_eth_private *mp)
1da177e4 1946{
d0412d96 1947 u32 pscr;
8a578111 1948 int i;
1da177e4 1949
bedfe324
LB		 1950 /*
1951 * Perform PHY reset, if there is a PHY.
1952 */
ed94493f 1953 if (mp->phy != NULL) {
bedfe324
LB		 1954 struct ethtool_cmd cmd;
1955
1956 mv643xx_eth_get_settings(mp->dev, &cmd);
1957 phy_reset(mp);
1958 mv643xx_eth_set_settings(mp->dev, &cmd);
1959 }
1da177e4 1960
81600eea
LB		 1961 /*
1962 * Configure basic link parameters.
1963 */
37a6084f 1964 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
81600eea
LB		 1965
1966 pscr |= SERIAL_PORT_ENABLE;
37a6084f 1967 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea
LB		 1968
1969 pscr |= DO_NOT_FORCE_LINK_FAIL;
ed94493f 1970 if (mp->phy == NULL)
81600eea 1971 pscr |= FORCE_LINK_PASS;
37a6084f 1972 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea 1973
37a6084f 1974 wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);
81600eea 1975
13d64285
LB		 1976 /*
1977 * Configure TX path and queues.
1978 */
89df5fdc 1979 tx_set_rate(mp, 1000000000, 16777216);
f7981c1c 1980 for (i = 0; i < mp->txq_count; i++) {
3d6b35bc 1981 struct tx_queue *txq = mp->txq + i;
13d64285 1982
6b368f68 1983 txq_reset_hw_ptr(txq);
89df5fdc
LB		 1984 txq_set_rate(txq, 1000000000, 16777216);
1985 txq_set_fixed_prio_mode(txq);
13d64285
LB		 1986 }
1987
fc32b0e2
LB		 1988 /*
1989 * Add configured unicast address to address filter table.
1990 */
1991 uc_addr_set(mp, mp->dev->dev_addr);
1da177e4 1992
d9a073ea
LB		 1993 /*
1994 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
170e7108
LB		 1995 * frames to RX queue #0, and include the pseudo-header when
1996 * calculating receive checksums.
d9a073ea 1997 */
37a6084f 1998 wrlp(mp, PORT_CONFIG, 0x02000000);
01999873 1999
376489a2
LB		 2000 /*
2001 * Treat BPDUs as normal multicasts, and disable partition mode.
2002 */
37a6084f 2003 wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
01999873 2004
8a578111 2005 /*
64da80a2 2006 * Enable the receive queues.
8a578111 2007 */
f7981c1c 2008 for (i = 0; i < mp->rxq_count; i++) {
64da80a2 2009 struct rx_queue *rxq = mp->rxq + i;
8a578111 2010 u32 addr;
1da177e4 2011
8a578111
LB		 2012 addr = (u32)rxq->rx_desc_dma;
2013 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
37a6084f 2014 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);
1da177e4 2015
8a578111
LB		 2016 rxq_enable(rxq);
2017 }
1da177e4
LT		 2018}
2019
ffd86bbe 2020static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1da177e4 2021{
c9df406f 2022 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
773fc3ee 2023 u32 val;
1da177e4 2024
37a6084f 2025 val = rdlp(mp, SDMA_CONFIG);
773fc3ee
LB		 2026 if (mp->shared->extended_rx_coal_limit) {
2027 if (coal > 0xffff)
2028 coal = 0xffff;
2029 val &= ~0x023fff80;
2030 val |= (coal & 0x8000) << 10;
2031 val |= (coal & 0x7fff) << 7;
2032 } else {
2033 if (coal > 0x3fff)
2034 coal = 0x3fff;
2035 val &= ~0x003fff00;
2036 val |= (coal & 0x3fff) << 8;
2037 }
37a6084f 2038 wrlp(mp, SDMA_CONFIG, val);
1da177e4
LT		 2039}
2040
ffd86bbe 2041static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1da177e4 2042{
c9df406f 2043 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1da177e4 2044
fc32b0e2
LB		 2045 if (coal > 0x3fff)
2046 coal = 0x3fff;
37a6084f 2047 wrlp(mp, TX_FIFO_URGENT_THRESHOLD, (coal & 0x3fff) << 4);
16e03018
DF		 2048}
2049
2bcb4b0f
LB		 2050static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
2051{
2052 int skb_size;
2053
2054 /*
2055 * Reserve 2+14 bytes for an ethernet header (the hardware
2056 * automatically prepends 2 bytes of dummy data to each
2057 * received packet), 16 bytes for up to four VLAN tags, and
2058 * 4 bytes for the trailing FCS -- 36 bytes total.
2059 */
2060 skb_size = mp->dev->mtu + 36;
2061
2062 /*
2063 * Make sure that the skb size is a multiple of 8 bytes, as
2064 * the lower three bits of the receive descriptor's buffer
2065 * size field are ignored by the hardware.
2066 */
2067 mp->skb_size = (skb_size + 7) & ~7;
2068}
2069
c9df406f 2070static int mv643xx_eth_open(struct net_device *dev)
16e03018 2071{
e5371493 2072 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2073 int err;
64da80a2 2074 int i;
16e03018 2075
37a6084f
LB		 2076 wrlp(mp, INT_CAUSE, 0);
2077 wrlp(mp, INT_CAUSE_EXT, 0);
2078 rdlp(mp, INT_CAUSE_EXT);
c9df406f 2079
fc32b0e2 2080 err = request_irq(dev->irq, mv643xx_eth_irq,
2a1867a7 2081 IRQF_SHARED, dev->name, dev);
c9df406f 2082 if (err) {
fc32b0e2 2083 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
c9df406f 2084 return -EAGAIN;
16e03018
DF		 2085 }
2086
fc32b0e2 2087 init_mac_tables(mp);
16e03018 2088
2bcb4b0f
LB		 2089 mv643xx_eth_recalc_skb_size(mp);
2090
2257e05c
LB		 2091 napi_enable(&mp->napi);
2092
2bcb4b0f
LB		 2093 skb_queue_head_init(&mp->rx_recycle);
2094
f7981c1c 2095 for (i = 0; i < mp->rxq_count; i++) {
64da80a2
LB		 2096 err = rxq_init(mp, i);
2097 if (err) {
2098 while (--i >= 0)
f7981c1c 2099 rxq_deinit(mp->rxq + i);
64da80a2
LB		 2100 goto out;
2101 }
2102
1fa38c58 2103 rxq_refill(mp->rxq + i, INT_MAX);
2257e05c
LB		 2104 }
2105
1fa38c58 2106 if (mp->work_rx_oom) {
2257e05c
LB		 2107 mp->rx_oom.expires = jiffies + (HZ / 10);
2108 add_timer(&mp->rx_oom);
64da80a2 2109 }
8a578111 2110
f7981c1c 2111 for (i = 0; i < mp->txq_count; i++) {
3d6b35bc
LB		 2112 err = txq_init(mp, i);
2113 if (err) {
2114 while (--i >= 0)
f7981c1c 2115 txq_deinit(mp->txq + i);
3d6b35bc
LB		 2116 goto out_free;
2117 }
2118 }
16e03018 2119
2f7eb47a 2120 netif_carrier_off(dev);
2f7eb47a 2121
fc32b0e2 2122 port_start(mp);
16e03018 2123
ffd86bbe
LB		 2124 set_rx_coal(mp, 0);
2125 set_tx_coal(mp, 0);
16e03018 2126
37a6084f
LB		 2127 wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);
2128 wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT);
16e03018 2129
c9df406f
LB		 2130 return 0;
2131
13d64285 2132
fc32b0e2 2133out_free:
f7981c1c
LB		 2134 for (i = 0; i < mp->rxq_count; i++)
2135 rxq_deinit(mp->rxq + i);
fc32b0e2 2136out:
c9df406f
LB		 2137 free_irq(dev->irq, dev);
2138
2139 return err;
16e03018
DF		 2140}
2141
e5371493 2142static void port_reset(struct mv643xx_eth_private *mp)
1da177e4 2143{
fc32b0e2 2144 unsigned int data;
64da80a2 2145 int i;
1da177e4 2146
f7981c1c
LB		 2147 for (i = 0; i < mp->rxq_count; i++)
2148 rxq_disable(mp->rxq + i);
2149 for (i = 0; i < mp->txq_count; i++)
2150 txq_disable(mp->txq + i);
ae9ae064
LB		 2151
2152 while (1) {
37a6084f 2153 u32 ps = rdlp(mp, PORT_STATUS);
ae9ae064
LB		 2154
2155 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2156 break;
13d64285 2157 udelay(10);
ae9ae064 2158 }
1da177e4 2159
c9df406f 2160 /* Reset the Enable bit in the Configuration Register */
37a6084f 2161 data = rdlp(mp, PORT_SERIAL_CONTROL);
fc32b0e2
LB		 2162 data &= ~(SERIAL_PORT_ENABLE |
2163 DO_NOT_FORCE_LINK_FAIL |
2164 FORCE_LINK_PASS);
37a6084f 2165 wrlp(mp, PORT_SERIAL_CONTROL, data);
1da177e4
LT		 2166}
2167
c9df406f 2168static int mv643xx_eth_stop(struct net_device *dev)
1da177e4 2169{
e5371493 2170 struct mv643xx_eth_private *mp = netdev_priv(dev);
64da80a2 2171 int i;
1da177e4 2172
37a6084f
LB		 2173 wrlp(mp, INT_MASK, 0x00000000);
2174 rdlp(mp, INT_MASK);
1da177e4 2175
4ff3495a
LB		 2176 del_timer_sync(&mp->mib_counters_timer);
2177
c9df406f 2178 napi_disable(&mp->napi);
78fff83b 2179
2257e05c
LB		 2180 del_timer_sync(&mp->rx_oom);
2181
c9df406f 2182 netif_carrier_off(dev);
1da177e4 2183
fc32b0e2
LB		 2184 free_irq(dev->irq, dev);
2185
cc9754b3 2186 port_reset(mp);
8fd89211 2187 mv643xx_eth_get_stats(dev);
fc32b0e2 2188 mib_counters_update(mp);
1da177e4 2189
2bcb4b0f
LB		 2190 skb_queue_purge(&mp->rx_recycle);
2191
f7981c1c
LB		 2192 for (i = 0; i < mp->rxq_count; i++)
2193 rxq_deinit(mp->rxq + i);
2194 for (i = 0; i < mp->txq_count; i++)
2195 txq_deinit(mp->txq + i);
1da177e4 2196
c9df406f 2197 return 0;
1da177e4
LT		 2198}
2199
fc32b0e2 2200static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1da177e4 2201{
e5371493 2202 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2203
ed94493f
LB		 2204 if (mp->phy != NULL)
2205 return phy_mii_ioctl(mp->phy, if_mii(ifr), cmd);
bedfe324
LB		 2206
2207 return -EOPNOTSUPP;
1da177e4
LT		 2208}
2209
c9df406f 2210static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 2211{
89df5fdc
LB		 2212 struct mv643xx_eth_private *mp = netdev_priv(dev);
2213
fc32b0e2 2214 if (new_mtu < 64 || new_mtu > 9500)
c9df406f 2215 return -EINVAL;
1da177e4 2216
c9df406f 2217 dev->mtu = new_mtu;
2bcb4b0f 2218 mv643xx_eth_recalc_skb_size(mp);
89df5fdc
LB		 2219 tx_set_rate(mp, 1000000000, 16777216);
2220
c9df406f
LB		 2221 if (!netif_running(dev))
2222 return 0;
1da177e4 2223
c9df406f
LB		 2224 /*
2225 * Stop and then re-open the interface. This will allocate RX
2226 * skbs of the new MTU.
2227 * There is a possible danger that the open will not succeed,
fc32b0e2 2228 * due to memory being full.
c9df406f
LB		 2229 */
2230 mv643xx_eth_stop(dev);
2231 if (mv643xx_eth_open(dev)) {
fc32b0e2
LB		 2232 dev_printk(KERN_ERR, &dev->dev,
2233 "fatal error on re-opening device after "
2234 "MTU change\n");
c9df406f
LB		 2235 }
2236
2237 return 0;
1da177e4
LT		 2238}
2239
fc32b0e2 2240static void tx_timeout_task(struct work_struct *ugly)
1da177e4 2241{
fc32b0e2 2242 struct mv643xx_eth_private *mp;
1da177e4 2243
fc32b0e2
LB		 2244 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2245 if (netif_running(mp->dev)) {
e5ef1de1 2246 netif_tx_stop_all_queues(mp->dev);
fc32b0e2
LB		 2247 port_reset(mp);
2248 port_start(mp);
e5ef1de1 2249 netif_tx_wake_all_queues(mp->dev);
fc32b0e2 2250 }
c9df406f
LB		 2251}
2252
c9df406f 2253static void mv643xx_eth_tx_timeout(struct net_device *dev)
1da177e4 2254{
e5371493 2255 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2256
fc32b0e2 2257 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
d0412d96 2258
c9df406f 2259 schedule_work(&mp->tx_timeout_task);
1da177e4
LT		 2260}
2261
c9df406f 2262#ifdef CONFIG_NET_POLL_CONTROLLER
fc32b0e2 2263static void mv643xx_eth_netpoll(struct net_device *dev)
9f8dd319 2264{
fc32b0e2 2265 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2266
37a6084f
LB		 2267 wrlp(mp, INT_MASK, 0x00000000);
2268 rdlp(mp, INT_MASK);
c9df406f 2269
fc32b0e2 2270 mv643xx_eth_irq(dev->irq, dev);
c9df406f 2271
37a6084f 2272 wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT);
9f8dd319 2273}
c9df406f 2274#endif
9f8dd319 2275
9f8dd319 2276
c9df406f 2277/* platform glue ************************************************************/
e5371493
LB		 2278static void
2279mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2280 struct mbus_dram_target_info *dram)
c9df406f 2281{
cc9754b3 2282 void __iomem *base = msp->base;
c9df406f
LB		 2283 u32 win_enable;
2284 u32 win_protect;
2285 int i;
9f8dd319 2286
c9df406f
LB		 2287 for (i = 0; i < 6; i++) {
2288 writel(0, base + WINDOW_BASE(i));
2289 writel(0, base + WINDOW_SIZE(i));
2290 if (i < 4)
2291 writel(0, base + WINDOW_REMAP_HIGH(i));
9f8dd319
DF		 2292 }
2293
c9df406f
LB		 2294 win_enable = 0x3f;
2295 win_protect = 0;
2296
2297 for (i = 0; i < dram->num_cs; i++) {
2298 struct mbus_dram_window *cs = dram->cs + i;
2299
2300 writel((cs->base & 0xffff0000) |
2301 (cs->mbus_attr << 8) |
2302 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2303 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2304
2305 win_enable &= ~(1 << i);
2306 win_protect |= 3 << (2 * i);
2307 }
2308
2309 writel(win_enable, base + WINDOW_BAR_ENABLE);
2310 msp->win_protect = win_protect;
9f8dd319
DF		 2311}
2312
773fc3ee
LB		 2313static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2314{
2315 /*
2316 * Check whether we have a 14-bit coal limit field in bits
2317 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2318 * SDMA config register.
2319 */
37a6084f
LB		 2320 writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
2321 if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000)
773fc3ee
LB		 2322 msp->extended_rx_coal_limit = 1;
2323 else
2324 msp->extended_rx_coal_limit = 0;
1e881592
LB		 2325
2326 /*
457b1d5a
LB		 2327 * Check whether the MAC supports TX rate control, and if
2328 * yes, whether its associated registers are in the old or
2329 * the new place.
1e881592 2330 */
37a6084f
LB		 2331 writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
2332 if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) {
457b1d5a
LB		 2333 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2334 } else {
37a6084f
LB		 2335 writel(7, msp->base + 0x0400 + TX_BW_RATE);
2336 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7)
457b1d5a
LB		 2337 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2338 else
2339 msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2340 }
773fc3ee
LB		 2341}
2342
c9df406f 2343static int mv643xx_eth_shared_probe(struct platform_device *pdev)
9f8dd319 2344{
10a9948d 2345 static int mv643xx_eth_version_printed;
c9df406f 2346 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
e5371493 2347 struct mv643xx_eth_shared_private *msp;
c9df406f
LB		 2348 struct resource *res;
2349 int ret;
9f8dd319 2350
e5371493 2351 if (!mv643xx_eth_version_printed++)
7dde154d
LB		 2352 printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet "
2353 "driver version %s\n", mv643xx_eth_driver_version);
9f8dd319 2354
c9df406f
LB		 2355 ret = -EINVAL;
2356 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2357 if (res == NULL)
2358 goto out;
9f8dd319 2359
c9df406f
LB		 2360 ret = -ENOMEM;
2361 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2362 if (msp == NULL)
2363 goto out;
2364 memset(msp, 0, sizeof(*msp));
2365
cc9754b3
LB		 2366 msp->base = ioremap(res->start, res->end - res->start + 1);
2367 if (msp->base == NULL)
c9df406f
LB		 2368 goto out_free;
2369
ed94493f
LB		 2370 /*
2371 * Set up and register SMI bus.
2372 */
2373 if (pd == NULL || pd->shared_smi == NULL) {
298cf9be
LB		 2374 msp->smi_bus = mdiobus_alloc();
2375 if (msp->smi_bus == NULL)
ed94493f 2376 goto out_unmap;
298cf9be
LB		 2377
2378 msp->smi_bus->priv = msp;
2379 msp->smi_bus->name = "mv643xx_eth smi";
2380 msp->smi_bus->read = smi_bus_read;
2381 msp->smi_bus->write = smi_bus_write,
2382 snprintf(msp->smi_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id);
2383 msp->smi_bus->parent = &pdev->dev;
2384 msp->smi_bus->phy_mask = 0xffffffff;
2385 if (mdiobus_register(msp->smi_bus) < 0)
2386 goto out_free_mii_bus;
ed94493f
LB		 2387 msp->smi = msp;
2388 } else {
fc0eb9f2 2389 msp->smi = platform_get_drvdata(pd->shared_smi);
ed94493f 2390 }
c9df406f 2391
45c5d3bc
LB		 2392 msp->err_interrupt = NO_IRQ;
2393 init_waitqueue_head(&msp->smi_busy_wait);
2394
2395 /*
2396 * Check whether the error interrupt is hooked up.
2397 */
2398 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2399 if (res != NULL) {
2400 int err;
2401
2402 err = request_irq(res->start, mv643xx_eth_err_irq,
2403 IRQF_SHARED, "mv643xx_eth", msp);
2404 if (!err) {
2405 writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK);
2406 msp->err_interrupt = res->start;
2407 }
2408 }
2409
c9df406f
LB		 2410 /*
2411 * (Re-)program MBUS remapping windows if we are asked to.
2412 */
2413 if (pd != NULL && pd->dram != NULL)
2414 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2415
fc32b0e2
LB		 2416 /*
2417 * Detect hardware parameters.
2418 */
2419 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
773fc3ee 2420 infer_hw_params(msp);
fc32b0e2
LB		 2421
2422 platform_set_drvdata(pdev, msp);
2423
c9df406f
LB		 2424 return 0;
2425
298cf9be
LB		 2426out_free_mii_bus:
2427 mdiobus_free(msp->smi_bus);
ed94493f
LB		 2428out_unmap:
2429 iounmap(msp->base);
c9df406f
LB		 2430out_free:
2431 kfree(msp);
2432out:
2433 return ret;
2434}
2435
2436static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2437{
e5371493 2438 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
ed94493f 2439 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
c9df406f 2440
298cf9be
LB		 2441 if (pd == NULL || pd->shared_smi == NULL) {
2442 mdiobus_free(msp->smi_bus);
2443 mdiobus_unregister(msp->smi_bus);
2444 }
45c5d3bc
LB		 2445 if (msp->err_interrupt != NO_IRQ)
2446 free_irq(msp->err_interrupt, msp);
cc9754b3 2447 iounmap(msp->base);
c9df406f
LB		 2448 kfree(msp);
2449
2450 return 0;
9f8dd319
DF		 2451}
2452
c9df406f 2453static struct platform_driver mv643xx_eth_shared_driver = {
fc32b0e2
LB		 2454 .probe = mv643xx_eth_shared_probe,
2455 .remove = mv643xx_eth_shared_remove,
c9df406f 2456 .driver = {
fc32b0e2 2457 .name = MV643XX_ETH_SHARED_NAME,
c9df406f
LB		 2458 .owner = THIS_MODULE,
2459 },
2460};
2461
e5371493 2462static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
1da177e4 2463{
c9df406f 2464 int addr_shift = 5 * mp->port_num;
fc32b0e2 2465 u32 data;
1da177e4 2466
fc32b0e2
LB		 2467 data = rdl(mp, PHY_ADDR);
2468 data &= ~(0x1f << addr_shift);
2469 data |= (phy_addr & 0x1f) << addr_shift;
2470 wrl(mp, PHY_ADDR, data);
1da177e4
LT		 2471}
2472
e5371493 2473static int phy_addr_get(struct mv643xx_eth_private *mp)
1da177e4 2474{
fc32b0e2
LB		 2475 unsigned int data;
2476
2477 data = rdl(mp, PHY_ADDR);
2478
2479 return (data >> (5 * mp->port_num)) & 0x1f;
2480}
2481
2482static void set_params(struct mv643xx_eth_private *mp,
2483 struct mv643xx_eth_platform_data *pd)
2484{
2485 struct net_device *dev = mp->dev;
2486
2487 if (is_valid_ether_addr(pd->mac_addr))
2488 memcpy(dev->dev_addr, pd->mac_addr, 6);
2489 else
2490 uc_addr_get(mp, dev->dev_addr);
2491
fc32b0e2
LB		 2492 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2493 if (pd->rx_queue_size)
2494 mp->default_rx_ring_size = pd->rx_queue_size;
2495 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2496 mp->rx_desc_sram_size = pd->rx_sram_size;
1da177e4 2497
f7981c1c 2498 mp->rxq_count = pd->rx_queue_count ? : 1;
64da80a2 2499
fc32b0e2
LB		 2500 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2501 if (pd->tx_queue_size)
2502 mp->default_tx_ring_size = pd->tx_queue_size;
2503 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2504 mp->tx_desc_sram_size = pd->tx_sram_size;
3d6b35bc 2505
f7981c1c 2506 mp->txq_count = pd->tx_queue_count ? : 1;
1da177e4
LT		 2507}
2508
ed94493f
LB		 2509static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
2510 int phy_addr)
1da177e4 2511{
298cf9be 2512 struct mii_bus *bus = mp->shared->smi->smi_bus;
ed94493f
LB		 2513 struct phy_device *phydev;
2514 int start;
2515 int num;
2516 int i;
45c5d3bc 2517
ed94493f
LB		 2518 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
2519 start = phy_addr_get(mp) & 0x1f;
2520 num = 32;
2521 } else {
2522 start = phy_addr & 0x1f;
2523 num = 1;
2524 }
45c5d3bc 2525
ed94493f
LB		 2526 phydev = NULL;
2527 for (i = 0; i < num; i++) {
2528 int addr = (start + i) & 0x1f;
fc32b0e2 2529
ed94493f
LB		 2530 if (bus->phy_map[addr] == NULL)
2531 mdiobus_scan(bus, addr);
1da177e4 2532
ed94493f
LB		 2533 if (phydev == NULL) {
2534 phydev = bus->phy_map[addr];
2535 if (phydev != NULL)
2536 phy_addr_set(mp, addr);
2537 }
2538 }
1da177e4 2539
ed94493f 2540 return phydev;
1da177e4
LT		 2541}
2542
ed94493f 2543static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
c28a4f89 2544{
ed94493f 2545 struct phy_device *phy = mp->phy;
c28a4f89 2546
fc32b0e2
LB		 2547 phy_reset(mp);
2548
ed94493f
LB		 2549 phy_attach(mp->dev, phy->dev.bus_id, 0, PHY_INTERFACE_MODE_GMII);
2550
2551 if (speed == 0) {
2552 phy->autoneg = AUTONEG_ENABLE;
2553 phy->speed = 0;
2554 phy->duplex = 0;
2555 phy->advertising = phy->supported | ADVERTISED_Autoneg;
c9df406f 2556 } else {
ed94493f
LB		 2557 phy->autoneg = AUTONEG_DISABLE;
2558 phy->advertising = 0;
2559 phy->speed = speed;
2560 phy->duplex = duplex;
c9df406f 2561 }
ed94493f 2562 phy_start_aneg(phy);
c28a4f89
JC		 2563}
2564
81600eea
LB		 2565static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2566{
2567 u32 pscr;
2568
37a6084f 2569 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
81600eea
LB		 2570 if (pscr & SERIAL_PORT_ENABLE) {
2571 pscr &= ~SERIAL_PORT_ENABLE;
37a6084f 2572 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea
LB		 2573 }
2574
2575 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
ed94493f 2576 if (mp->phy == NULL) {
81600eea
LB		 2577 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2578 if (speed == SPEED_1000)
2579 pscr |= SET_GMII_SPEED_TO_1000;
2580 else if (speed == SPEED_100)
2581 pscr |= SET_MII_SPEED_TO_100;
2582
2583 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2584
2585 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2586 if (duplex == DUPLEX_FULL)
2587 pscr |= SET_FULL_DUPLEX_MODE;
2588 }
2589
37a6084f 2590 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea
LB		 2591}
2592
c9df406f 2593static int mv643xx_eth_probe(struct platform_device *pdev)
1da177e4 2594{
c9df406f 2595 struct mv643xx_eth_platform_data *pd;
e5371493 2596 struct mv643xx_eth_private *mp;
c9df406f 2597 struct net_device *dev;
c9df406f 2598 struct resource *res;
fc32b0e2 2599 int err;
1da177e4 2600
c9df406f
LB		 2601 pd = pdev->dev.platform_data;
2602 if (pd == NULL) {
fc32b0e2
LB		 2603 dev_printk(KERN_ERR, &pdev->dev,
2604 "no mv643xx_eth_platform_data\n");
c9df406f
LB		 2605 return -ENODEV;
2606 }
1da177e4 2607
c9df406f 2608 if (pd->shared == NULL) {
fc32b0e2
LB		 2609 dev_printk(KERN_ERR, &pdev->dev,
2610 "no mv643xx_eth_platform_data->shared\n");
c9df406f
LB		 2611 return -ENODEV;
2612 }
8f518703 2613
e5ef1de1 2614 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
c9df406f
LB		 2615 if (!dev)
2616 return -ENOMEM;
1da177e4 2617
c9df406f 2618 mp = netdev_priv(dev);
fc32b0e2
LB		 2619 platform_set_drvdata(pdev, mp);
2620
2621 mp->shared = platform_get_drvdata(pd->shared);
37a6084f 2622 mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10);
fc32b0e2
LB		 2623 mp->port_num = pd->port_number;
2624
c9df406f 2625 mp->dev = dev;
78fff83b 2626
fc32b0e2 2627 set_params(mp, pd);
e5ef1de1 2628 dev->real_num_tx_queues = mp->txq_count;
fc32b0e2 2629
ed94493f
LB		 2630 if (pd->phy_addr != MV643XX_ETH_PHY_NONE)
2631 mp->phy = phy_scan(mp, pd->phy_addr);
bedfe324 2632
ed94493f
LB		 2633 if (mp->phy != NULL) {
2634 phy_init(mp, pd->speed, pd->duplex);
bedfe324
LB		 2635 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2636 } else {
2637 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless);
2638 }
ed94493f 2639
81600eea 2640 init_pscr(mp, pd->speed, pd->duplex);
fc32b0e2 2641
4ff3495a
LB		 2642
2643 mib_counters_clear(mp);
2644
2645 init_timer(&mp->mib_counters_timer);
2646 mp->mib_counters_timer.data = (unsigned long)mp;
2647 mp->mib_counters_timer.function = mib_counters_timer_wrapper;
2648 mp->mib_counters_timer.expires = jiffies + 30 * HZ;
2649 add_timer(&mp->mib_counters_timer);
2650
2651 spin_lock_init(&mp->mib_counters_lock);
2652
2653 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2654
2257e05c
LB		 2655 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
2656
2657 init_timer(&mp->rx_oom);
2658 mp->rx_oom.data = (unsigned long)mp;
2659 mp->rx_oom.function = oom_timer_wrapper;
2660
fc32b0e2 2661
c9df406f
LB		 2662 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2663 BUG_ON(!res);
2664 dev->irq = res->start;
1da177e4 2665
8fd89211 2666 dev->get_stats = mv643xx_eth_get_stats;
fc32b0e2 2667 dev->hard_start_xmit = mv643xx_eth_xmit;
c9df406f
LB		 2668 dev->open = mv643xx_eth_open;
2669 dev->stop = mv643xx_eth_stop;
c9df406f 2670 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
fc32b0e2
LB		 2671 dev->set_mac_address = mv643xx_eth_set_mac_address;
2672 dev->do_ioctl = mv643xx_eth_ioctl;
2673 dev->change_mtu = mv643xx_eth_change_mtu;
c9df406f 2674 dev->tx_timeout = mv643xx_eth_tx_timeout;
c9df406f 2675#ifdef CONFIG_NET_POLL_CONTROLLER
e5371493 2676 dev->poll_controller = mv643xx_eth_netpoll;
c9df406f 2677#endif
c9df406f
LB		 2678 dev->watchdog_timeo = 2 * HZ;
2679 dev->base_addr = 0;
1da177e4 2680
c9df406f 2681 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
e32b6617 2682 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
1da177e4 2683
fc32b0e2 2684 SET_NETDEV_DEV(dev, &pdev->dev);
8f518703 2685
c9df406f 2686 if (mp->shared->win_protect)
fc32b0e2 2687 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
1da177e4 2688
c9df406f
LB		 2689 err = register_netdev(dev);
2690 if (err)
2691 goto out;
1da177e4 2692
e174961c
JB		 2693 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %pM\n",
2694 mp->port_num, dev->dev_addr);
1da177e4 2695
13d64285 2696 if (mp->tx_desc_sram_size > 0)
fc32b0e2 2697 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
1da177e4 2698
c9df406f 2699 return 0;
1da177e4 2700
c9df406f
LB		 2701out:
2702 free_netdev(dev);
1da177e4 2703
c9df406f 2704 return err;
1da177e4
LT		 2705}
2706
c9df406f 2707static int mv643xx_eth_remove(struct platform_device *pdev)
1da177e4 2708{
fc32b0e2 2709 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
1da177e4 2710
fc32b0e2 2711 unregister_netdev(mp->dev);
ed94493f
LB		 2712 if (mp->phy != NULL)
2713 phy_detach(mp->phy);
c9df406f 2714 flush_scheduled_work();
fc32b0e2 2715 free_netdev(mp->dev);
c9df406f 2716
c9df406f 2717 platform_set_drvdata(pdev, NULL);
fc32b0e2 2718
c9df406f 2719 return 0;
1da177e4
LT		 2720}
2721
c9df406f 2722static void mv643xx_eth_shutdown(struct platform_device *pdev)
d0412d96 2723{
fc32b0e2 2724 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
d0412d96 2725
c9df406f 2726 /* Mask all interrupts on ethernet port */
37a6084f
LB		 2727 wrlp(mp, INT_MASK, 0);
2728 rdlp(mp, INT_MASK);
c9df406f 2729
fc32b0e2
LB		 2730 if (netif_running(mp->dev))
2731 port_reset(mp);
d0412d96
JC		 2732}
2733
c9df406f 2734static struct platform_driver mv643xx_eth_driver = {
fc32b0e2
LB		 2735 .probe = mv643xx_eth_probe,
2736 .remove = mv643xx_eth_remove,
2737 .shutdown = mv643xx_eth_shutdown,
c9df406f 2738 .driver = {
fc32b0e2 2739 .name = MV643XX_ETH_NAME,
c9df406f
LB		 2740 .owner = THIS_MODULE,
2741 },
2742};
2743
e5371493 2744static int __init mv643xx_eth_init_module(void)
d0412d96 2745{
c9df406f 2746 int rc;
d0412d96 2747
c9df406f
LB		 2748 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2749 if (!rc) {
2750 rc = platform_driver_register(&mv643xx_eth_driver);
2751 if (rc)
2752 platform_driver_unregister(&mv643xx_eth_shared_driver);
2753 }
fc32b0e2 2754
c9df406f 2755 return rc;
d0412d96 2756}
fc32b0e2 2757module_init(mv643xx_eth_init_module);
d0412d96 2758
e5371493 2759static void __exit mv643xx_eth_cleanup_module(void)
d0412d96 2760{
c9df406f
LB		 2761 platform_driver_unregister(&mv643xx_eth_driver);
2762 platform_driver_unregister(&mv643xx_eth_shared_driver);
d0412d96 2763}
e5371493 2764module_exit(mv643xx_eth_cleanup_module);
1da177e4 2765
45675bc6
LB		 2766MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2767 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
c9df406f 2768MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
fc32b0e2 2769MODULE_LICENSE("GPL");
c9df406f 2770MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
fc32b0e2 2771MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
Linux 6.x block layer and io_uring tree(s)