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[PATCH] mv643xx_eth: Fix a NULL pointer dereference
[linux-2.6-block.git] / drivers / net / mv643xx_eth.c
CommitLineData
1da177e4
LT		 1/*
2 * drivers/net/mv643xx_eth.c - Driver for MV643XX ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 rabeeh@galileo.co.il
7 *
8 * Copyright (C) 2003 PMC-Sierra, Inc.,
3bb8a18a 9 * written by Manish Lachwani
1da177e4
LT		 10 *
11 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
12 *
13 * Copyright (C) 2004-2005 MontaVista Software, Inc.
14 * Dale Farnsworth <dale@farnsworth.org>
15 *
16 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
17 * <sjhill@realitydiluted.com>
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version 2
22 * of the License, or (at your option) any later version.
23 *
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
28 *
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
32 */
33#include <linux/init.h>
34#include <linux/dma-mapping.h>
35#include <linux/tcp.h>
36#include <linux/udp.h>
37#include <linux/etherdevice.h>
78a5e534
OH		 38#include <linux/in.h>
39#include <linux/ip.h>
1da177e4
LT		 40
41#include <linux/bitops.h>
42#include <linux/delay.h>
43#include <linux/ethtool.h>
d052d1be
RK		 44#include <linux/platform_device.h>
45
1da177e4
LT		 46#include <asm/io.h>
47#include <asm/types.h>
48#include <asm/pgtable.h>
49#include <asm/system.h>
50#include <asm/delay.h>
51#include "mv643xx_eth.h"
52
53/*
54 * The first part is the high level driver of the gigE ethernet ports.
55 */
56
57/* Constants */
58#define VLAN_HLEN 4
59#define FCS_LEN 4
60#define WRAP NET_IP_ALIGN + ETH_HLEN + VLAN_HLEN + FCS_LEN
61#define RX_SKB_SIZE ((dev->mtu + WRAP + 7) & ~0x7)
62
63#define INT_CAUSE_UNMASK_ALL 0x0007ffff
64#define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff
1da177e4 65#define INT_CAUSE_MASK_ALL 0x00000000
63c9e549 66#define INT_CAUSE_MASK_ALL_EXT 0x00000000
1da177e4
LT		 67#define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL
68#define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT
1da177e4
LT		 69
70#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
71#define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
72#else
73#define MAX_DESCS_PER_SKB 1
74#endif
75
76#define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */
77#define PHY_WAIT_MICRO_SECONDS 10
78
79/* Static function declarations */
80static int eth_port_link_is_up(unsigned int eth_port_num);
81static void eth_port_uc_addr_get(struct net_device *dev,
82 unsigned char *MacAddr);
83static int mv643xx_eth_real_open(struct net_device *);
84static int mv643xx_eth_real_stop(struct net_device *);
85static int mv643xx_eth_change_mtu(struct net_device *, int);
86static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *);
87static void eth_port_init_mac_tables(unsigned int eth_port_num);
88#ifdef MV643XX_NAPI
89static int mv643xx_poll(struct net_device *dev, int *budget);
90#endif
91static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
92static int ethernet_phy_detect(unsigned int eth_port_num);
93static struct ethtool_ops mv643xx_ethtool_ops;
94
95static char mv643xx_driver_name[] = "mv643xx_eth";
96static char mv643xx_driver_version[] = "1.0";
97
98static void __iomem *mv643xx_eth_shared_base;
99
100/* used to protect MV643XX_ETH_SMI_REG, which is shared across ports */
a9f6a0dd 101static DEFINE_SPINLOCK(mv643xx_eth_phy_lock);
1da177e4
LT		 102
103static inline u32 mv_read(int offset)
104{
dc074a8a 105 void __iomem *reg_base;
1da177e4
LT		 106
107 reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS;
108
109 return readl(reg_base + offset);
110}
111
112static inline void mv_write(int offset, u32 data)
113{
dc074a8a 114 void __iomem *reg_base;
1da177e4
LT		 115
116 reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS;
117 writel(data, reg_base + offset);
118}
119
120/*
121 * Changes MTU (maximum transfer unit) of the gigabit ethenret port
122 *
123 * Input : pointer to ethernet interface network device structure
124 * new mtu size
125 * Output : 0 upon success, -EINVAL upon failure
126 */
127static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
128{
129 struct mv643xx_private *mp = netdev_priv(dev);
130 unsigned long flags;
131
132 spin_lock_irqsave(&mp->lock, flags);
133
134 if ((new_mtu > 9500) || (new_mtu < 64)) {
135 spin_unlock_irqrestore(&mp->lock, flags);
136 return -EINVAL;
137 }
138
139 dev->mtu = new_mtu;
140 /*
141 * Stop then re-open the interface. This will allocate RX skb's with
142 * the new MTU.
143 * There is a possible danger that the open will not successed, due
144 * to memory is full, which might fail the open function.
145 */
146 if (netif_running(dev)) {
147 if (mv643xx_eth_real_stop(dev))
148 printk(KERN_ERR
149 "%s: Fatal error on stopping device\n",
150 dev->name);
151 if (mv643xx_eth_real_open(dev))
152 printk(KERN_ERR
153 "%s: Fatal error on opening device\n",
154 dev->name);
155 }
156
157 spin_unlock_irqrestore(&mp->lock, flags);
158 return 0;
159}
160
161/*
162 * mv643xx_eth_rx_task
163 *
164 * Fills / refills RX queue on a certain gigabit ethernet port
165 *
166 * Input : pointer to ethernet interface network device structure
167 * Output : N/A
168 */
169static void mv643xx_eth_rx_task(void *data)
170{
171 struct net_device *dev = (struct net_device *)data;
172 struct mv643xx_private *mp = netdev_priv(dev);
173 struct pkt_info pkt_info;
174 struct sk_buff *skb;
175
176 if (test_and_set_bit(0, &mp->rx_task_busy))
177 panic("%s: Error in test_set_bit / clear_bit", dev->name);
178
179 while (mp->rx_ring_skbs < (mp->rx_ring_size - 5)) {
180 skb = dev_alloc_skb(RX_SKB_SIZE);
181 if (!skb)
182 break;
183 mp->rx_ring_skbs++;
184 pkt_info.cmd_sts = ETH_RX_ENABLE_INTERRUPT;
185 pkt_info.byte_cnt = RX_SKB_SIZE;
186 pkt_info.buf_ptr = dma_map_single(NULL, skb->data, RX_SKB_SIZE,
187 DMA_FROM_DEVICE);
188 pkt_info.return_info = skb;
189 if (eth_rx_return_buff(mp, &pkt_info) != ETH_OK) {
190 printk(KERN_ERR
191 "%s: Error allocating RX Ring\n", dev->name);
192 break;
193 }
194 skb_reserve(skb, 2);
195 }
196 clear_bit(0, &mp->rx_task_busy);
197 /*
198 * If RX ring is empty of SKB, set a timer to try allocating
199 * again in a later time .
200 */
201 if ((mp->rx_ring_skbs == 0) && (mp->rx_timer_flag == 0)) {
202 printk(KERN_INFO "%s: Rx ring is empty\n", dev->name);
203 /* After 100mSec */
204 mp->timeout.expires = jiffies + (HZ / 10);
205 add_timer(&mp->timeout);
206 mp->rx_timer_flag = 1;
207 }
208#ifdef MV643XX_RX_QUEUE_FILL_ON_TASK
209 else {
210 /* Return interrupts */
211 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(mp->port_num),
212 INT_CAUSE_UNMASK_ALL);
213 }
214#endif
215}
216
217/*
218 * mv643xx_eth_rx_task_timer_wrapper
219 *
220 * Timer routine to wake up RX queue filling task. This function is
221 * used only in case the RX queue is empty, and all alloc_skb has
222 * failed (due to out of memory event).
223 *
224 * Input : pointer to ethernet interface network device structure
225 * Output : N/A
226 */
227static void mv643xx_eth_rx_task_timer_wrapper(unsigned long data)
228{
229 struct net_device *dev = (struct net_device *)data;
230 struct mv643xx_private *mp = netdev_priv(dev);
231
232 mp->rx_timer_flag = 0;
233 mv643xx_eth_rx_task((void *)data);
234}
235
236/*
237 * mv643xx_eth_update_mac_address
238 *
239 * Update the MAC address of the port in the address table
240 *
241 * Input : pointer to ethernet interface network device structure
242 * Output : N/A
243 */
244static void mv643xx_eth_update_mac_address(struct net_device *dev)
245{
246 struct mv643xx_private *mp = netdev_priv(dev);
247 unsigned int port_num = mp->port_num;
248
249 eth_port_init_mac_tables(port_num);
250 memcpy(mp->port_mac_addr, dev->dev_addr, 6);
251 eth_port_uc_addr_set(port_num, mp->port_mac_addr);
252}
253
254/*
255 * mv643xx_eth_set_rx_mode
256 *
257 * Change from promiscuos to regular rx mode
258 *
259 * Input : pointer to ethernet interface network device structure
260 * Output : N/A
261 */
262static void mv643xx_eth_set_rx_mode(struct net_device *dev)
263{
264 struct mv643xx_private *mp = netdev_priv(dev);
1da177e4 265
1da177e4 266 if (dev->flags & IFF_PROMISC)
7342cd81 267 mp->port_config |= (u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE;
1da177e4 268 else
7342cd81
DF		 269 mp->port_config &= ~(u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE;
270
271 mv_write(MV643XX_ETH_PORT_CONFIG_REG(mp->port_num), mp->port_config);
1da177e4
LT		 272}
273
274/*
275 * mv643xx_eth_set_mac_address
276 *
277 * Change the interface's mac address.
278 * No special hardware thing should be done because interface is always
279 * put in promiscuous mode.
280 *
281 * Input : pointer to ethernet interface network device structure and
282 * a pointer to the designated entry to be added to the cache.
283 * Output : zero upon success, negative upon failure
284 */
285static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
286{
287 int i;
288
289 for (i = 0; i < 6; i++)
290 /* +2 is for the offset of the HW addr type */
291 dev->dev_addr[i] = ((unsigned char *)addr)[i + 2];
292 mv643xx_eth_update_mac_address(dev);
293 return 0;
294}
295
296/*
297 * mv643xx_eth_tx_timeout
298 *
299 * Called upon a timeout on transmitting a packet
300 *
301 * Input : pointer to ethernet interface network device structure.
302 * Output : N/A
303 */
304static void mv643xx_eth_tx_timeout(struct net_device *dev)
305{
306 struct mv643xx_private *mp = netdev_priv(dev);
307
308 printk(KERN_INFO "%s: TX timeout ", dev->name);
309
310 /* Do the reset outside of interrupt context */
311 schedule_work(&mp->tx_timeout_task);
312}
313
314/*
315 * mv643xx_eth_tx_timeout_task
316 *
317 * Actual routine to reset the adapter when a timeout on Tx has occurred
318 */
319static void mv643xx_eth_tx_timeout_task(struct net_device *dev)
320{
321 struct mv643xx_private *mp = netdev_priv(dev);
322
323 netif_device_detach(dev);
324 eth_port_reset(mp->port_num);
325 eth_port_start(mp);
326 netif_device_attach(dev);
327}
328
329/*
330 * mv643xx_eth_free_tx_queue
331 *
332 * Input : dev - a pointer to the required interface
333 *
334 * Output : 0 if was able to release skb , nonzero otherwise
335 */
336static int mv643xx_eth_free_tx_queue(struct net_device *dev,
337 unsigned int eth_int_cause_ext)
338{
339 struct mv643xx_private *mp = netdev_priv(dev);
340 struct net_device_stats *stats = &mp->stats;
341 struct pkt_info pkt_info;
342 int released = 1;
343
344 if (!(eth_int_cause_ext & (BIT0 | BIT8)))
345 return released;
346
347 spin_lock(&mp->lock);
348
349 /* Check only queue 0 */
350 while (eth_tx_return_desc(mp, &pkt_info) == ETH_OK) {
351 if (pkt_info.cmd_sts & BIT0) {
352 printk("%s: Error in TX\n", dev->name);
353 stats->tx_errors++;
354 }
355
cb415d30
PG		 356 if (pkt_info.cmd_sts & ETH_TX_FIRST_DESC)
357 dma_unmap_single(NULL, pkt_info.buf_ptr,
358 pkt_info.byte_cnt,
359 DMA_TO_DEVICE);
360 else
361 dma_unmap_page(NULL, pkt_info.buf_ptr,
362 pkt_info.byte_cnt,
363 DMA_TO_DEVICE);
1da177e4 364
cb415d30 365 if (pkt_info.return_info) {
1da177e4
LT		 366 dev_kfree_skb_irq(pkt_info.return_info);
367 released = 0;
cb415d30 368 }
1da177e4
LT		 369 }
370
371 spin_unlock(&mp->lock);
372
373 return released;
374}
375
376/*
377 * mv643xx_eth_receive
378 *
379 * This function is forward packets that are received from the port's
380 * queues toward kernel core or FastRoute them to another interface.
381 *
382 * Input : dev - a pointer to the required interface
383 * max - maximum number to receive (0 means unlimted)
384 *
385 * Output : number of served packets
386 */
387#ifdef MV643XX_NAPI
388static int mv643xx_eth_receive_queue(struct net_device *dev, int budget)
389#else
390static int mv643xx_eth_receive_queue(struct net_device *dev)
391#endif
392{
393 struct mv643xx_private *mp = netdev_priv(dev);
394 struct net_device_stats *stats = &mp->stats;
395 unsigned int received_packets = 0;
396 struct sk_buff *skb;
397 struct pkt_info pkt_info;
398
399#ifdef MV643XX_NAPI
b1dd9ca1 400 while (budget-- > 0 && eth_port_receive(mp, &pkt_info) == ETH_OK) {
1da177e4
LT		 401#else
402 while (eth_port_receive(mp, &pkt_info) == ETH_OK) {
403#endif
404 mp->rx_ring_skbs--;
405 received_packets++;
b1dd9ca1 406
1da177e4
LT		 407 /* Update statistics. Note byte count includes 4 byte CRC count */
408 stats->rx_packets++;
409 stats->rx_bytes += pkt_info.byte_cnt;
410 skb = pkt_info.return_info;
411 /*
412 * In case received a packet without first / last bits on OR
413 * the error summary bit is on, the packets needs to be dropeed.
414 */
415 if (((pkt_info.cmd_sts
416 & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
417 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
418 || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
419 stats->rx_dropped++;
420 if ((pkt_info.cmd_sts & (ETH_RX_FIRST_DESC |
421 ETH_RX_LAST_DESC)) !=
422 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) {
423 if (net_ratelimit())
424 printk(KERN_ERR
425 "%s: Received packet spread "
426 "on multiple descriptors\n",
427 dev->name);
428 }
429 if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)
430 stats->rx_errors++;
431
432 dev_kfree_skb_irq(skb);
433 } else {
434 /*
435 * The -4 is for the CRC in the trailer of the
436 * received packet
437 */
438 skb_put(skb, pkt_info.byte_cnt - 4);
439 skb->dev = dev;
440
441 if (pkt_info.cmd_sts & ETH_LAYER_4_CHECKSUM_OK) {
442 skb->ip_summed = CHECKSUM_UNNECESSARY;
443 skb->csum = htons(
444 (pkt_info.cmd_sts & 0x0007fff8) >> 3);
445 }
446 skb->protocol = eth_type_trans(skb, dev);
447#ifdef MV643XX_NAPI
448 netif_receive_skb(skb);
449#else
450 netif_rx(skb);
451#endif
452 }
453 }
454
455 return received_packets;
456}
457
458/*
459 * mv643xx_eth_int_handler
460 *
461 * Main interrupt handler for the gigbit ethernet ports
462 *
463 * Input : irq - irq number (not used)
464 * dev_id - a pointer to the required interface's data structure
465 * regs - not used
466 * Output : N/A
467 */
468
469static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id,
470 struct pt_regs *regs)
471{
472 struct net_device *dev = (struct net_device *)dev_id;
473 struct mv643xx_private *mp = netdev_priv(dev);
474 u32 eth_int_cause, eth_int_cause_ext = 0;
475 unsigned int port_num = mp->port_num;
476
477 /* Read interrupt cause registers */
478 eth_int_cause = mv_read(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num)) &
479 INT_CAUSE_UNMASK_ALL;
480
481 if (eth_int_cause & BIT1)
482 eth_int_cause_ext = mv_read(
483 MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num)) &
484 INT_CAUSE_UNMASK_ALL_EXT;
485
486#ifdef MV643XX_NAPI
487 if (!(eth_int_cause & 0x0007fffd)) {
488 /* Dont ack the Rx interrupt */
489#endif
490 /*
491 * Clear specific ethernet port intrerrupt registers by
492 * acknowleding relevant bits.
493 */
494 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num),
495 ~eth_int_cause);
496 if (eth_int_cause_ext != 0x0)
497 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG
498 (port_num), ~eth_int_cause_ext);
499
500 /* UDP change : We may need this */
501 if ((eth_int_cause_ext & 0x0000ffff) &&
502 (mv643xx_eth_free_tx_queue(dev, eth_int_cause_ext) == 0) &&
503 (mp->tx_ring_size > mp->tx_ring_skbs + MAX_DESCS_PER_SKB))
504 netif_wake_queue(dev);
505#ifdef MV643XX_NAPI
506 } else {
507 if (netif_rx_schedule_prep(dev)) {
508 /* Mask all the interrupts */
509 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), 0);
510 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG
511 (port_num), 0);
512 __netif_rx_schedule(dev);
513 }
514#else
515 if (eth_int_cause & (BIT2 | BIT11))
516 mv643xx_eth_receive_queue(dev, 0);
517
518 /*
519 * After forwarded received packets to upper layer, add a task
520 * in an interrupts enabled context that refills the RX ring
521 * with skb's.
522 */
523#ifdef MV643XX_RX_QUEUE_FILL_ON_TASK
524 /* Unmask all interrupts on ethernet port */
525 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
526 INT_CAUSE_MASK_ALL);
527 queue_task(&mp->rx_task, &tq_immediate);
528 mark_bh(IMMEDIATE_BH);
529#else
530 mp->rx_task.func(dev);
531#endif
532#endif
533 }
534 /* PHY status changed */
535 if (eth_int_cause_ext & (BIT16 | BIT20)) {
536 if (eth_port_link_is_up(port_num)) {
537 netif_carrier_on(dev);
538 netif_wake_queue(dev);
539 /* Start TX queue */
540 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG
541 (port_num), 1);
542 } else {
543 netif_carrier_off(dev);
544 netif_stop_queue(dev);
545 }
546 }
547
548 /*
549 * If no real interrupt occured, exit.
550 * This can happen when using gigE interrupt coalescing mechanism.
551 */
552 if ((eth_int_cause == 0x0) && (eth_int_cause_ext == 0x0))
553 return IRQ_NONE;
554
555 return IRQ_HANDLED;
556}
557
558#ifdef MV643XX_COAL
559
560/*
561 * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
562 *
563 * DESCRIPTION:
564 * This routine sets the RX coalescing interrupt mechanism parameter.
565 * This parameter is a timeout counter, that counts in 64 t_clk
566 * chunks ; that when timeout event occurs a maskable interrupt
567 * occurs.
568 * The parameter is calculated using the tClk of the MV-643xx chip
569 * , and the required delay of the interrupt in usec.
570 *
571 * INPUT:
572 * unsigned int eth_port_num Ethernet port number
573 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
574 * unsigned int delay Delay in usec
575 *
576 * OUTPUT:
577 * Interrupt coalescing mechanism value is set in MV-643xx chip.
578 *
579 * RETURN:
580 * The interrupt coalescing value set in the gigE port.
581 *
582 */
583static unsigned int eth_port_set_rx_coal(unsigned int eth_port_num,
584 unsigned int t_clk, unsigned int delay)
585{
586 unsigned int coal = ((t_clk / 1000000) * delay) / 64;
587
588 /* Set RX Coalescing mechanism */
589 mv_write(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num),
590 ((coal & 0x3fff) << 8) |
591 (mv_read(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num))
592 & 0xffc000ff));
593
594 return coal;
595}
596#endif
597
598/*
599 * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
600 *
601 * DESCRIPTION:
602 * This routine sets the TX coalescing interrupt mechanism parameter.
603 * This parameter is a timeout counter, that counts in 64 t_clk
604 * chunks ; that when timeout event occurs a maskable interrupt
605 * occurs.
606 * The parameter is calculated using the t_cLK frequency of the
607 * MV-643xx chip and the required delay in the interrupt in uSec
608 *
609 * INPUT:
610 * unsigned int eth_port_num Ethernet port number
611 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
612 * unsigned int delay Delay in uSeconds
613 *
614 * OUTPUT:
615 * Interrupt coalescing mechanism value is set in MV-643xx chip.
616 *
617 * RETURN:
618 * The interrupt coalescing value set in the gigE port.
619 *
620 */
621static unsigned int eth_port_set_tx_coal(unsigned int eth_port_num,
622 unsigned int t_clk, unsigned int delay)
623{
624 unsigned int coal;
625 coal = ((t_clk / 1000000) * delay) / 64;
626 /* Set TX Coalescing mechanism */
627 mv_write(MV643XX_ETH_TX_FIFO_URGENT_THRESHOLD_REG(eth_port_num),
628 coal << 4);
629 return coal;
630}
631
632/*
633 * mv643xx_eth_open
634 *
635 * This function is called when openning the network device. The function
636 * should initialize all the hardware, initialize cyclic Rx/Tx
637 * descriptors chain and buffers and allocate an IRQ to the network
638 * device.
639 *
640 * Input : a pointer to the network device structure
641 *
642 * Output : zero of success , nonzero if fails.
643 */
644
645static int mv643xx_eth_open(struct net_device *dev)
646{
647 struct mv643xx_private *mp = netdev_priv(dev);
648 unsigned int port_num = mp->port_num;
649 int err;
650
651 spin_lock_irq(&mp->lock);
652
653 err = request_irq(dev->irq, mv643xx_eth_int_handler,
16b81757 654 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
1da177e4
LT		 655
656 if (err) {
657 printk(KERN_ERR "Can not assign IRQ number to MV643XX_eth%d\n",
658 port_num);
659 err = -EAGAIN;
660 goto out;
661 }
662
663 if (mv643xx_eth_real_open(dev)) {
664 printk("%s: Error opening interface\n", dev->name);
665 err = -EBUSY;
666 goto out_free;
667 }
668
669 spin_unlock_irq(&mp->lock);
670
671 return 0;
672
673out_free:
674 free_irq(dev->irq, dev);
675
676out:
677 spin_unlock_irq(&mp->lock);
678
679 return err;
680}
681
682/*
683 * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
684 *
685 * DESCRIPTION:
686 * This function prepares a Rx chained list of descriptors and packet
687 * buffers in a form of a ring. The routine must be called after port
688 * initialization routine and before port start routine.
689 * The Ethernet SDMA engine uses CPU bus addresses to access the various
690 * devices in the system (i.e. DRAM). This function uses the ethernet
691 * struct 'virtual to physical' routine (set by the user) to set the ring
692 * with physical addresses.
693 *
694 * INPUT:
695 * struct mv643xx_private *mp Ethernet Port Control srtuct.
696 *
697 * OUTPUT:
698 * The routine updates the Ethernet port control struct with information
699 * regarding the Rx descriptors and buffers.
700 *
701 * RETURN:
702 * None.
703 */
704static void ether_init_rx_desc_ring(struct mv643xx_private *mp)
705{
706 volatile struct eth_rx_desc *p_rx_desc;
707 int rx_desc_num = mp->rx_ring_size;
708 int i;
709
710 /* initialize the next_desc_ptr links in the Rx descriptors ring */
711 p_rx_desc = (struct eth_rx_desc *)mp->p_rx_desc_area;
712 for (i = 0; i < rx_desc_num; i++) {
713 p_rx_desc[i].next_desc_ptr = mp->rx_desc_dma +
714 ((i + 1) % rx_desc_num) * sizeof(struct eth_rx_desc);
715 }
716
717 /* Save Rx desc pointer to driver struct. */
718 mp->rx_curr_desc_q = 0;
719 mp->rx_used_desc_q = 0;
720
721 mp->rx_desc_area_size = rx_desc_num * sizeof(struct eth_rx_desc);
722
723 /* Add the queue to the list of RX queues of this port */
724 mp->port_rx_queue_command |= 1;
725}
726
727/*
728 * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
729 *
730 * DESCRIPTION:
731 * This function prepares a Tx chained list of descriptors and packet
732 * buffers in a form of a ring. The routine must be called after port
733 * initialization routine and before port start routine.
734 * The Ethernet SDMA engine uses CPU bus addresses to access the various
735 * devices in the system (i.e. DRAM). This function uses the ethernet
736 * struct 'virtual to physical' routine (set by the user) to set the ring
737 * with physical addresses.
738 *
739 * INPUT:
740 * struct mv643xx_private *mp Ethernet Port Control srtuct.
741 *
742 * OUTPUT:
743 * The routine updates the Ethernet port control struct with information
744 * regarding the Tx descriptors and buffers.
745 *
746 * RETURN:
747 * None.
748 */
749static void ether_init_tx_desc_ring(struct mv643xx_private *mp)
750{
751 int tx_desc_num = mp->tx_ring_size;
752 struct eth_tx_desc *p_tx_desc;
753 int i;
754
755 /* Initialize the next_desc_ptr links in the Tx descriptors ring */
756 p_tx_desc = (struct eth_tx_desc *)mp->p_tx_desc_area;
757 for (i = 0; i < tx_desc_num; i++) {
758 p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma +
759 ((i + 1) % tx_desc_num) * sizeof(struct eth_tx_desc);
760 }
761
762 mp->tx_curr_desc_q = 0;
763 mp->tx_used_desc_q = 0;
764#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
765 mp->tx_first_desc_q = 0;
766#endif
767
768 mp->tx_desc_area_size = tx_desc_num * sizeof(struct eth_tx_desc);
769
770 /* Add the queue to the list of Tx queues of this port */
771 mp->port_tx_queue_command |= 1;
772}
773
774/* Helper function for mv643xx_eth_open */
775static int mv643xx_eth_real_open(struct net_device *dev)
776{
777 struct mv643xx_private *mp = netdev_priv(dev);
778 unsigned int port_num = mp->port_num;
779 unsigned int size;
780
781 /* Stop RX Queues */
782 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), 0x0000ff00);
783
784 /* Clear the ethernet port interrupts */
785 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
786 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
787
788 /* Unmask RX buffer and TX end interrupt */
789 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
790 INT_CAUSE_UNMASK_ALL);
791
792 /* Unmask phy and link status changes interrupts */
793 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
794 INT_CAUSE_UNMASK_ALL_EXT);
795
796 /* Set the MAC Address */
797 memcpy(mp->port_mac_addr, dev->dev_addr, 6);
798
799 eth_port_init(mp);
800
801 INIT_WORK(&mp->rx_task, (void (*)(void *))mv643xx_eth_rx_task, dev);
802
803 memset(&mp->timeout, 0, sizeof(struct timer_list));
804 mp->timeout.function = mv643xx_eth_rx_task_timer_wrapper;
805 mp->timeout.data = (unsigned long)dev;
806
807 mp->rx_task_busy = 0;
808 mp->rx_timer_flag = 0;
809
810 /* Allocate RX and TX skb rings */
811 mp->rx_skb = kmalloc(sizeof(*mp->rx_skb) * mp->rx_ring_size,
812 GFP_KERNEL);
813 if (!mp->rx_skb) {
814 printk(KERN_ERR "%s: Cannot allocate Rx skb ring\n", dev->name);
815 return -ENOMEM;
816 }
817 mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size,
818 GFP_KERNEL);
819 if (!mp->tx_skb) {
820 printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name);
821 kfree(mp->rx_skb);
822 return -ENOMEM;
823 }
824
825 /* Allocate TX ring */
826 mp->tx_ring_skbs = 0;
827 size = mp->tx_ring_size * sizeof(struct eth_tx_desc);
828 mp->tx_desc_area_size = size;
829
830 if (mp->tx_sram_size) {
831 mp->p_tx_desc_area = ioremap(mp->tx_sram_addr,
832 mp->tx_sram_size);
833 mp->tx_desc_dma = mp->tx_sram_addr;
834 } else
835 mp->p_tx_desc_area = dma_alloc_coherent(NULL, size,
836 &mp->tx_desc_dma,
837 GFP_KERNEL);
838
839 if (!mp->p_tx_desc_area) {
840 printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n",
841 dev->name, size);
842 kfree(mp->rx_skb);
843 kfree(mp->tx_skb);
844 return -ENOMEM;
845 }
846 BUG_ON((u32) mp->p_tx_desc_area & 0xf); /* check 16-byte alignment */
847 memset((void *)mp->p_tx_desc_area, 0, mp->tx_desc_area_size);
848
849 ether_init_tx_desc_ring(mp);
850
851 /* Allocate RX ring */
852 mp->rx_ring_skbs = 0;
853 size = mp->rx_ring_size * sizeof(struct eth_rx_desc);
854 mp->rx_desc_area_size = size;
855
856 if (mp->rx_sram_size) {
857 mp->p_rx_desc_area = ioremap(mp->rx_sram_addr,
858 mp->rx_sram_size);
859 mp->rx_desc_dma = mp->rx_sram_addr;
860 } else
861 mp->p_rx_desc_area = dma_alloc_coherent(NULL, size,
862 &mp->rx_desc_dma,
863 GFP_KERNEL);
864
865 if (!mp->p_rx_desc_area) {
866 printk(KERN_ERR "%s: Cannot allocate Rx ring (size %d bytes)\n",
867 dev->name, size);
868 printk(KERN_ERR "%s: Freeing previously allocated TX queues...",
869 dev->name);
870 if (mp->rx_sram_size)
871 iounmap(mp->p_rx_desc_area);
872 else
873 dma_free_coherent(NULL, mp->tx_desc_area_size,
874 mp->p_tx_desc_area, mp->tx_desc_dma);
875 kfree(mp->rx_skb);
876 kfree(mp->tx_skb);
877 return -ENOMEM;
878 }
879 memset((void *)mp->p_rx_desc_area, 0, size);
880
881 ether_init_rx_desc_ring(mp);
882
883 mv643xx_eth_rx_task(dev); /* Fill RX ring with skb's */
884
885 eth_port_start(mp);
886
887 /* Interrupt Coalescing */
888
889#ifdef MV643XX_COAL
890 mp->rx_int_coal =
891 eth_port_set_rx_coal(port_num, 133000000, MV643XX_RX_COAL);
892#endif
893
894 mp->tx_int_coal =
895 eth_port_set_tx_coal(port_num, 133000000, MV643XX_TX_COAL);
896
897 netif_start_queue(dev);
898
899 return 0;
900}
901
902static void mv643xx_eth_free_tx_rings(struct net_device *dev)
903{
904 struct mv643xx_private *mp = netdev_priv(dev);
905 unsigned int port_num = mp->port_num;
906 unsigned int curr;
907
908 /* Stop Tx Queues */
909 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num), 0x0000ff00);
910
911 /* Free outstanding skb's on TX rings */
912 for (curr = 0; mp->tx_ring_skbs && curr < mp->tx_ring_size; curr++) {
913 if (mp->tx_skb[curr]) {
914 dev_kfree_skb(mp->tx_skb[curr]);
915 mp->tx_ring_skbs--;
916 }
917 }
918 if (mp->tx_ring_skbs)
919 printk("%s: Error on Tx descriptor free - could not free %d"
920 " descriptors\n", dev->name, mp->tx_ring_skbs);
921
922 /* Free TX ring */
923 if (mp->tx_sram_size)
924 iounmap(mp->p_tx_desc_area);
925 else
926 dma_free_coherent(NULL, mp->tx_desc_area_size,
927 mp->p_tx_desc_area, mp->tx_desc_dma);
928}
929
930static void mv643xx_eth_free_rx_rings(struct net_device *dev)
931{
932 struct mv643xx_private *mp = netdev_priv(dev);
933 unsigned int port_num = mp->port_num;
934 int curr;
935
936 /* Stop RX Queues */
937 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), 0x0000ff00);
938
939 /* Free preallocated skb's on RX rings */
940 for (curr = 0; mp->rx_ring_skbs && curr < mp->rx_ring_size; curr++) {
941 if (mp->rx_skb[curr]) {
942 dev_kfree_skb(mp->rx_skb[curr]);
943 mp->rx_ring_skbs--;
944 }
945 }
946
947 if (mp->rx_ring_skbs)
948 printk(KERN_ERR
949 "%s: Error in freeing Rx Ring. %d skb's still"
950 " stuck in RX Ring - ignoring them\n", dev->name,
951 mp->rx_ring_skbs);
952 /* Free RX ring */
953 if (mp->rx_sram_size)
954 iounmap(mp->p_rx_desc_area);
955 else
956 dma_free_coherent(NULL, mp->rx_desc_area_size,
957 mp->p_rx_desc_area, mp->rx_desc_dma);
958}
959
960/*
961 * mv643xx_eth_stop
962 *
963 * This function is used when closing the network device.
964 * It updates the hardware,
965 * release all memory that holds buffers and descriptors and release the IRQ.
966 * Input : a pointer to the device structure
967 * Output : zero if success , nonzero if fails
968 */
969
970/* Helper function for mv643xx_eth_stop */
971
972static int mv643xx_eth_real_stop(struct net_device *dev)
973{
974 struct mv643xx_private *mp = netdev_priv(dev);
975 unsigned int port_num = mp->port_num;
976
977 netif_carrier_off(dev);
978 netif_stop_queue(dev);
979
980 mv643xx_eth_free_tx_rings(dev);
981 mv643xx_eth_free_rx_rings(dev);
982
983 eth_port_reset(mp->port_num);
984
985 /* Disable ethernet port interrupts */
986 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
987 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
988
989 /* Mask RX buffer and TX end interrupt */
990 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), 0);
991
992 /* Mask phy and link status changes interrupts */
993 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num), 0);
994
995 return 0;
996}
997
998static int mv643xx_eth_stop(struct net_device *dev)
999{
1000 struct mv643xx_private *mp = netdev_priv(dev);
1001
1002 spin_lock_irq(&mp->lock);
1003
1004 mv643xx_eth_real_stop(dev);
1005
1006 free_irq(dev->irq, dev);
1007 spin_unlock_irq(&mp->lock);
1008
1009 return 0;
1010}
1011
1012#ifdef MV643XX_NAPI
1013static void mv643xx_tx(struct net_device *dev)
1014{
1015 struct mv643xx_private *mp = netdev_priv(dev);
1016 struct pkt_info pkt_info;
1017
1018 while (eth_tx_return_desc(mp, &pkt_info) == ETH_OK) {
cb415d30
PG		 1019 if (pkt_info.cmd_sts & ETH_TX_FIRST_DESC)
1020 dma_unmap_single(NULL, pkt_info.buf_ptr,
1021 pkt_info.byte_cnt,
1022 DMA_TO_DEVICE);
1023 else
1024 dma_unmap_page(NULL, pkt_info.buf_ptr,
1025 pkt_info.byte_cnt,
1026 DMA_TO_DEVICE);
1da177e4 1027
cb415d30 1028 if (pkt_info.return_info)
1da177e4 1029 dev_kfree_skb_irq(pkt_info.return_info);
1da177e4
LT		 1030 }
1031
1032 if (netif_queue_stopped(dev) &&
1033 mp->tx_ring_size > mp->tx_ring_skbs + MAX_DESCS_PER_SKB)
1034 netif_wake_queue(dev);
1035}
1036
1037/*
1038 * mv643xx_poll
1039 *
1040 * This function is used in case of NAPI
1041 */
1042static int mv643xx_poll(struct net_device *dev, int *budget)
1043{
1044 struct mv643xx_private *mp = netdev_priv(dev);
1045 int done = 1, orig_budget, work_done;
1046 unsigned int port_num = mp->port_num;
1047 unsigned long flags;
1048
1049#ifdef MV643XX_TX_FAST_REFILL
1050 if (++mp->tx_clean_threshold > 5) {
1051 spin_lock_irqsave(&mp->lock, flags);
1052 mv643xx_tx(dev);
1053 mp->tx_clean_threshold = 0;
1054 spin_unlock_irqrestore(&mp->lock, flags);
1055 }
1056#endif
1057
1058 if ((mv_read(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num)))
1059 != (u32) mp->rx_used_desc_q) {
1060 orig_budget = *budget;
1061 if (orig_budget > dev->quota)
1062 orig_budget = dev->quota;
1063 work_done = mv643xx_eth_receive_queue(dev, orig_budget);
1064 mp->rx_task.func(dev);
1065 *budget -= work_done;
1066 dev->quota -= work_done;
1067 if (work_done >= orig_budget)
1068 done = 0;
1069 }
1070
1071 if (done) {
1072 spin_lock_irqsave(&mp->lock, flags);
1073 __netif_rx_complete(dev);
1074 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
1075 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
1076 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
1077 INT_CAUSE_UNMASK_ALL);
1078 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
1079 INT_CAUSE_UNMASK_ALL_EXT);
1080 spin_unlock_irqrestore(&mp->lock, flags);
1081 }
1082
1083 return done ? 0 : 1;
1084}
1085#endif
1086
1087/*
1088 * mv643xx_eth_start_xmit
1089 *
1090 * This function is queues a packet in the Tx descriptor for
1091 * required port.
1092 *
1093 * Input : skb - a pointer to socket buffer
1094 * dev - a pointer to the required port
1095 *
1096 * Output : zero upon success
1097 */
1098static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
1099{
1100 struct mv643xx_private *mp = netdev_priv(dev);
1101 struct net_device_stats *stats = &mp->stats;
1102 ETH_FUNC_RET_STATUS status;
1103 unsigned long flags;
1104 struct pkt_info pkt_info;
1105
1106 if (netif_queue_stopped(dev)) {
1107 printk(KERN_ERR
1108 "%s: Tried sending packet when interface is stopped\n",
1109 dev->name);
1110 return 1;
1111 }
1112
1113 /* This is a hard error, log it. */
1114 if ((mp->tx_ring_size - mp->tx_ring_skbs) <=
1115 (skb_shinfo(skb)->nr_frags + 1)) {
1116 netif_stop_queue(dev);
1117 printk(KERN_ERR
1118 "%s: Bug in mv643xx_eth - Trying to transmit when"
1119 " queue full !\n", dev->name);
1120 return 1;
1121 }
1122
1123 /* Paranoid check - this shouldn't happen */
1124 if (skb == NULL) {
1125 stats->tx_dropped++;
1126 printk(KERN_ERR "mv64320_eth paranoid check failed\n");
1127 return 1;
1128 }
1129
1130 spin_lock_irqsave(&mp->lock, flags);
1131
1132 /* Update packet info data structure -- DMA owned, first last */
1133#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1134 if (!skb_shinfo(skb)->nr_frags) {
1135linear:
1136 if (skb->ip_summed != CHECKSUM_HW) {
26006360 1137 /* Errata BTS #50, IHL must be 5 if no HW checksum */
1da177e4 1138 pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT |
26006360
DF		 1139 ETH_TX_FIRST_DESC |
1140 ETH_TX_LAST_DESC |
1141 5 << ETH_TX_IHL_SHIFT;
1da177e4
LT		 1142 pkt_info.l4i_chk = 0;
1143 } else {
1da177e4
LT		 1144
1145 pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT |
26006360
DF		 1146 ETH_TX_FIRST_DESC |
1147 ETH_TX_LAST_DESC |
1148 ETH_GEN_TCP_UDP_CHECKSUM |
1149 ETH_GEN_IP_V_4_CHECKSUM |
1150 skb->nh.iph->ihl << ETH_TX_IHL_SHIFT;
1da177e4
LT		 1151 /* CPU already calculated pseudo header checksum. */
1152 if (skb->nh.iph->protocol == IPPROTO_UDP) {
1153 pkt_info.cmd_sts |= ETH_UDP_FRAME;
1154 pkt_info.l4i_chk = skb->h.uh->check;
1155 } else if (skb->nh.iph->protocol == IPPROTO_TCP)
1156 pkt_info.l4i_chk = skb->h.th->check;
1157 else {
1158 printk(KERN_ERR
1159 "%s: chksum proto != TCP or UDP\n",
1160 dev->name);
1161 spin_unlock_irqrestore(&mp->lock, flags);
1162 return 1;
1163 }
1164 }
1165 pkt_info.byte_cnt = skb->len;
1166 pkt_info.buf_ptr = dma_map_single(NULL, skb->data, skb->len,
1167 DMA_TO_DEVICE);
1168 pkt_info.return_info = skb;
1da177e4
LT		 1169 status = eth_port_send(mp, &pkt_info);
1170 if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL))
1171 printk(KERN_ERR "%s: Error on transmitting packet\n",
1172 dev->name);
1173 stats->tx_bytes += pkt_info.byte_cnt;
1174 } else {
1175 unsigned int frag;
1da177e4
LT		 1176
1177 /* Since hardware can't handle unaligned fragments smaller
1178 * than 9 bytes, if we find any, we linearize the skb
1179 * and start again. When I've seen it, it's always been
1180 * the first frag (probably near the end of the page),
1181 * but we check all frags to be safe.
1182 */
1183 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1184 skb_frag_t *fragp;
1185
1186 fragp = &skb_shinfo(skb)->frags[frag];
1187 if (fragp->size <= 8 && fragp->page_offset & 0x7) {
1188 skb_linearize(skb, GFP_ATOMIC);
1189 printk(KERN_DEBUG "%s: unaligned tiny fragment"
1190 "%d of %d, fixed\n",
1191 dev->name, frag,
1192 skb_shinfo(skb)->nr_frags);
1193 goto linear;
1194 }
1195 }
1196
1197 /* first frag which is skb header */
1198 pkt_info.byte_cnt = skb_headlen(skb);
1199 pkt_info.buf_ptr = dma_map_single(NULL, skb->data,
1200 skb_headlen(skb),
1201 DMA_TO_DEVICE);
1202 pkt_info.l4i_chk = 0;
1203 pkt_info.return_info = 0;
1da177e4 1204
26006360
DF		 1205 if (skb->ip_summed != CHECKSUM_HW)
1206 /* Errata BTS #50, IHL must be 5 if no HW checksum */
1207 pkt_info.cmd_sts = ETH_TX_FIRST_DESC |
1208 5 << ETH_TX_IHL_SHIFT;
1209 else {
1210 pkt_info.cmd_sts = ETH_TX_FIRST_DESC |
1211 ETH_GEN_TCP_UDP_CHECKSUM |
1212 ETH_GEN_IP_V_4_CHECKSUM |
1213 skb->nh.iph->ihl << ETH_TX_IHL_SHIFT;
1da177e4
LT		 1214 /* CPU already calculated pseudo header checksum. */
1215 if (skb->nh.iph->protocol == IPPROTO_UDP) {
1216 pkt_info.cmd_sts |= ETH_UDP_FRAME;
1217 pkt_info.l4i_chk = skb->h.uh->check;
1218 } else if (skb->nh.iph->protocol == IPPROTO_TCP)
1219 pkt_info.l4i_chk = skb->h.th->check;
1220 else {
1221 printk(KERN_ERR
1222 "%s: chksum proto != TCP or UDP\n",
1223 dev->name);
1224 spin_unlock_irqrestore(&mp->lock, flags);
1225 return 1;
1226 }
1227 }
1228
1229 status = eth_port_send(mp, &pkt_info);
1230 if (status != ETH_OK) {
1231 if ((status == ETH_ERROR))
1232 printk(KERN_ERR
1233 "%s: Error on transmitting packet\n",
1234 dev->name);
1235 if (status == ETH_QUEUE_FULL)
1236 printk("Error on Queue Full \n");
1237 if (status == ETH_QUEUE_LAST_RESOURCE)
1238 printk("Tx resource error \n");
1239 }
1240 stats->tx_bytes += pkt_info.byte_cnt;
1241
1242 /* Check for the remaining frags */
1243 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1244 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
1245 pkt_info.l4i_chk = 0x0000;
1246 pkt_info.cmd_sts = 0x00000000;
1247
1248 /* Last Frag enables interrupt and frees the skb */
1249 if (frag == (skb_shinfo(skb)->nr_frags - 1)) {
1250 pkt_info.cmd_sts |= ETH_TX_ENABLE_INTERRUPT |
1251 ETH_TX_LAST_DESC;
1252 pkt_info.return_info = skb;
1da177e4
LT		 1253 } else {
1254 pkt_info.return_info = 0;
1255 }
1256 pkt_info.l4i_chk = 0;
1257 pkt_info.byte_cnt = this_frag->size;
1258
1259 pkt_info.buf_ptr = dma_map_page(NULL, this_frag->page,
1260 this_frag->page_offset,
1261 this_frag->size,
1262 DMA_TO_DEVICE);
1263
1264 status = eth_port_send(mp, &pkt_info);
1265
1266 if (status != ETH_OK) {
1267 if ((status == ETH_ERROR))
1268 printk(KERN_ERR "%s: Error on "
1269 "transmitting packet\n",
1270 dev->name);
1271
1272 if (status == ETH_QUEUE_LAST_RESOURCE)
1273 printk("Tx resource error \n");
1274
1275 if (status == ETH_QUEUE_FULL)
1276 printk("Queue is full \n");
1277 }
1278 stats->tx_bytes += pkt_info.byte_cnt;
1279 }
1280 }
1281#else
1282 pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT | ETH_TX_FIRST_DESC |
1283 ETH_TX_LAST_DESC;
1284 pkt_info.l4i_chk = 0;
1285 pkt_info.byte_cnt = skb->len;
1286 pkt_info.buf_ptr = dma_map_single(NULL, skb->data, skb->len,
1287 DMA_TO_DEVICE);
1288 pkt_info.return_info = skb;
1da177e4
LT		 1289 status = eth_port_send(mp, &pkt_info);
1290 if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL))
1291 printk(KERN_ERR "%s: Error on transmitting packet\n",
1292 dev->name);
1293 stats->tx_bytes += pkt_info.byte_cnt;
1294#endif
1295
1296 /* Check if TX queue can handle another skb. If not, then
1297 * signal higher layers to stop requesting TX
1298 */
1299 if (mp->tx_ring_size <= (mp->tx_ring_skbs + MAX_DESCS_PER_SKB))
1300 /*
1301 * Stop getting skb's from upper layers.
1302 * Getting skb's from upper layers will be enabled again after
1303 * packets are released.
1304 */
1305 netif_stop_queue(dev);
1306
1307 /* Update statistics and start of transmittion time */
1308 stats->tx_packets++;
1309 dev->trans_start = jiffies;
1310
1311 spin_unlock_irqrestore(&mp->lock, flags);
1312
1313 return 0; /* success */
1314}
1315
1316/*
1317 * mv643xx_eth_get_stats
1318 *
1319 * Returns a pointer to the interface statistics.
1320 *
1321 * Input : dev - a pointer to the required interface
1322 *
1323 * Output : a pointer to the interface's statistics
1324 */
1325
1326static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1327{
1328 struct mv643xx_private *mp = netdev_priv(dev);
1329
1330 return &mp->stats;
1331}
1332
63c9e549
DF		 1333#ifdef CONFIG_NET_POLL_CONTROLLER
1334static inline void mv643xx_enable_irq(struct mv643xx_private *mp)
1335{
1336 int port_num = mp->port_num;
1337 unsigned long flags;
1338
1339 spin_lock_irqsave(&mp->lock, flags);
1340 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
1341 INT_CAUSE_UNMASK_ALL);
1342 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
1343 INT_CAUSE_UNMASK_ALL_EXT);
1344 spin_unlock_irqrestore(&mp->lock, flags);
1345}
1346
1347static inline void mv643xx_disable_irq(struct mv643xx_private *mp)
1348{
1349 int port_num = mp->port_num;
1350 unsigned long flags;
1351
1352 spin_lock_irqsave(&mp->lock, flags);
1353 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
1354 INT_CAUSE_MASK_ALL);
1355 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
1356 INT_CAUSE_MASK_ALL_EXT);
1357 spin_unlock_irqrestore(&mp->lock, flags);
1358}
1359
1360static void mv643xx_netpoll(struct net_device *netdev)
1361{
1362 struct mv643xx_private *mp = netdev_priv(netdev);
1363
1364 mv643xx_disable_irq(mp);
1365 mv643xx_eth_int_handler(netdev->irq, netdev, NULL);
1366 mv643xx_enable_irq(mp);
1367}
1368#endif
1369
1da177e4
LT		 1370/*/
1371 * mv643xx_eth_probe
1372 *
1373 * First function called after registering the network device.
1374 * It's purpose is to initialize the device as an ethernet device,
1375 * fill the ethernet device structure with pointers * to functions,
1376 * and set the MAC address of the interface
1377 *
1378 * Input : struct device *
1379 * Output : -ENOMEM if failed , 0 if success
1380 */
3ae5eaec 1381static int mv643xx_eth_probe(struct platform_device *pdev)
1da177e4 1382{
1da177e4
LT		 1383 struct mv643xx_eth_platform_data *pd;
1384 int port_num = pdev->id;
1385 struct mv643xx_private *mp;
1386 struct net_device *dev;
1387 u8 *p;
1388 struct resource *res;
1389 int err;
1390
1391 dev = alloc_etherdev(sizeof(struct mv643xx_private));
1392 if (!dev)
1393 return -ENOMEM;
1394
3ae5eaec 1395 platform_set_drvdata(pdev, dev);
1da177e4
LT		 1396
1397 mp = netdev_priv(dev);
1398
1399 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1400 BUG_ON(!res);
1401 dev->irq = res->start;
1402
1403 mp->port_num = port_num;
1404
1405 dev->open = mv643xx_eth_open;
1406 dev->stop = mv643xx_eth_stop;
1407 dev->hard_start_xmit = mv643xx_eth_start_xmit;
1408 dev->get_stats = mv643xx_eth_get_stats;
1409 dev->set_mac_address = mv643xx_eth_set_mac_address;
1410 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
1411
1412 /* No need to Tx Timeout */
1413 dev->tx_timeout = mv643xx_eth_tx_timeout;
1414#ifdef MV643XX_NAPI
1415 dev->poll = mv643xx_poll;
1416 dev->weight = 64;
1417#endif
1418
63c9e549
DF		 1419#ifdef CONFIG_NET_POLL_CONTROLLER
1420 dev->poll_controller = mv643xx_netpoll;
1421#endif
1422
1da177e4
LT		 1423 dev->watchdog_timeo = 2 * HZ;
1424 dev->tx_queue_len = mp->tx_ring_size;
1425 dev->base_addr = 0;
1426 dev->change_mtu = mv643xx_eth_change_mtu;
1427 SET_ETHTOOL_OPS(dev, &mv643xx_ethtool_ops);
1428
1429#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1430#ifdef MAX_SKB_FRAGS
1431 /*
1432 * Zero copy can only work if we use Discovery II memory. Else, we will
1433 * have to map the buffers to ISA memory which is only 16 MB
1434 */
1435 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_HW_CSUM;
1436#endif
1437#endif
1438
1439 /* Configure the timeout task */
1440 INIT_WORK(&mp->tx_timeout_task,
1441 (void (*)(void *))mv643xx_eth_tx_timeout_task, dev);
1442
1443 spin_lock_init(&mp->lock);
1444
1445 /* set default config values */
1446 eth_port_uc_addr_get(dev, dev->dev_addr);
1447 mp->port_config = MV643XX_ETH_PORT_CONFIG_DEFAULT_VALUE;
1448 mp->port_config_extend = MV643XX_ETH_PORT_CONFIG_EXTEND_DEFAULT_VALUE;
1449 mp->port_sdma_config = MV643XX_ETH_PORT_SDMA_CONFIG_DEFAULT_VALUE;
1450 mp->port_serial_control = MV643XX_ETH_PORT_SERIAL_CONTROL_DEFAULT_VALUE;
1451 mp->rx_ring_size = MV643XX_ETH_PORT_DEFAULT_RECEIVE_QUEUE_SIZE;
1452 mp->tx_ring_size = MV643XX_ETH_PORT_DEFAULT_TRANSMIT_QUEUE_SIZE;
1453
1454 pd = pdev->dev.platform_data;
1455 if (pd) {
1456 if (pd->mac_addr != NULL)
1457 memcpy(dev->dev_addr, pd->mac_addr, 6);
1458
1459 if (pd->phy_addr || pd->force_phy_addr)
1460 ethernet_phy_set(port_num, pd->phy_addr);
1461
1462 if (pd->port_config || pd->force_port_config)
1463 mp->port_config = pd->port_config;
1464
1465 if (pd->port_config_extend || pd->force_port_config_extend)
1466 mp->port_config_extend = pd->port_config_extend;
1467
1468 if (pd->port_sdma_config || pd->force_port_sdma_config)
1469 mp->port_sdma_config = pd->port_sdma_config;
1470
1471 if (pd->port_serial_control || pd->force_port_serial_control)
1472 mp->port_serial_control = pd->port_serial_control;
1473
1474 if (pd->rx_queue_size)
1475 mp->rx_ring_size = pd->rx_queue_size;
1476
1477 if (pd->tx_queue_size)
1478 mp->tx_ring_size = pd->tx_queue_size;
1479
1480 if (pd->tx_sram_size) {
1481 mp->tx_sram_size = pd->tx_sram_size;
1482 mp->tx_sram_addr = pd->tx_sram_addr;
1483 }
1484
1485 if (pd->rx_sram_size) {
1486 mp->rx_sram_size = pd->rx_sram_size;
1487 mp->rx_sram_addr = pd->rx_sram_addr;
1488 }
1489 }
1490
1491 err = ethernet_phy_detect(port_num);
1492 if (err) {
1493 pr_debug("MV643xx ethernet port %d: "
1494 "No PHY detected at addr %d\n",
1495 port_num, ethernet_phy_get(port_num));
1496 return err;
1497 }
1498
1499 err = register_netdev(dev);
1500 if (err)
1501 goto out;
1502
1503 p = dev->dev_addr;
1504 printk(KERN_NOTICE
1505 "%s: port %d with MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
1506 dev->name, port_num, p[0], p[1], p[2], p[3], p[4], p[5]);
1507
1508 if (dev->features & NETIF_F_SG)
1509 printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name);
1510
1511 if (dev->features & NETIF_F_IP_CSUM)
1512 printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n",
1513 dev->name);
1514
1515#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1516 printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name);
1517#endif
1518
1519#ifdef MV643XX_COAL
1520 printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n",
1521 dev->name);
1522#endif
1523
1524#ifdef MV643XX_NAPI
1525 printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name);
1526#endif
1527
b1529871
ND		 1528 if (mp->tx_sram_size > 0)
1529 printk(KERN_NOTICE "%s: Using SRAM\n", dev->name);
1530
1da177e4
LT		 1531 return 0;
1532
1533out:
1534 free_netdev(dev);
1535
1536 return err;
1537}
1538
3ae5eaec 1539static int mv643xx_eth_remove(struct platform_device *pdev)
1da177e4 1540{
3ae5eaec 1541 struct net_device *dev = platform_get_drvdata(pdev);
1da177e4
LT		 1542
1543 unregister_netdev(dev);
1544 flush_scheduled_work();
1545
1546 free_netdev(dev);
3ae5eaec 1547 platform_set_drvdata(pdev, NULL);
1da177e4
LT		 1548 return 0;
1549}
1550
3ae5eaec 1551static int mv643xx_eth_shared_probe(struct platform_device *pdev)
1da177e4 1552{
1da177e4
LT		 1553 struct resource *res;
1554
1555 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
1556
1557 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1558 if (res == NULL)
1559 return -ENODEV;
1560
1561 mv643xx_eth_shared_base = ioremap(res->start,
1562 MV643XX_ETH_SHARED_REGS_SIZE);
1563 if (mv643xx_eth_shared_base == NULL)
1564 return -ENOMEM;
1565
1566 return 0;
1567
1568}
1569
3ae5eaec 1570static int mv643xx_eth_shared_remove(struct platform_device *pdev)
1da177e4
LT		 1571{
1572 iounmap(mv643xx_eth_shared_base);
1573 mv643xx_eth_shared_base = NULL;
1574
1575 return 0;
1576}
1577
3ae5eaec 1578static struct platform_driver mv643xx_eth_driver = {
1da177e4
LT		 1579 .probe = mv643xx_eth_probe,
1580 .remove = mv643xx_eth_remove,
3ae5eaec
RK		 1581 .driver = {
1582 .name = MV643XX_ETH_NAME,
1583 },
1da177e4
LT		 1584};
1585
3ae5eaec 1586static struct platform_driver mv643xx_eth_shared_driver = {
1da177e4
LT		 1587 .probe = mv643xx_eth_shared_probe,
1588 .remove = mv643xx_eth_shared_remove,
3ae5eaec
RK		 1589 .driver = {
1590 .name = MV643XX_ETH_SHARED_NAME,
1591 },
1da177e4
LT		 1592};
1593
1594/*
1595 * mv643xx_init_module
1596 *
1597 * Registers the network drivers into the Linux kernel
1598 *
1599 * Input : N/A
1600 *
1601 * Output : N/A
1602 */
1603static int __init mv643xx_init_module(void)
1604{
1605 int rc;
1606
3ae5eaec 1607 rc = platform_driver_register(&mv643xx_eth_shared_driver);
1da177e4 1608 if (!rc) {
3ae5eaec 1609 rc = platform_driver_register(&mv643xx_eth_driver);
1da177e4 1610 if (rc)
3ae5eaec 1611 platform_driver_unregister(&mv643xx_eth_shared_driver);
1da177e4
LT		 1612 }
1613 return rc;
1614}
1615
1616/*
1617 * mv643xx_cleanup_module
1618 *
1619 * Registers the network drivers into the Linux kernel
1620 *
1621 * Input : N/A
1622 *
1623 * Output : N/A
1624 */
1625static void __exit mv643xx_cleanup_module(void)
1626{
3ae5eaec
RK		 1627 platform_driver_unregister(&mv643xx_eth_driver);
1628 platform_driver_unregister(&mv643xx_eth_shared_driver);
1da177e4
LT		 1629}
1630
1631module_init(mv643xx_init_module);
1632module_exit(mv643xx_cleanup_module);
1633
1634MODULE_LICENSE("GPL");
1635MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani"
1636 " and Dale Farnsworth");
1637MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
1638
1639/*
1640 * The second part is the low level driver of the gigE ethernet ports.
1641 */
1642
1643/*
1644 * Marvell's Gigabit Ethernet controller low level driver
1645 *
1646 * DESCRIPTION:
1647 * This file introduce low level API to Marvell's Gigabit Ethernet
1648 * controller. This Gigabit Ethernet Controller driver API controls
1649 * 1) Operations (i.e. port init, start, reset etc').
1650 * 2) Data flow (i.e. port send, receive etc').
1651 * Each Gigabit Ethernet port is controlled via
1652 * struct mv643xx_private.
1653 * This struct includes user configuration information as well as
1654 * driver internal data needed for its operations.
1655 *
1656 * Supported Features:
1657 * - This low level driver is OS independent. Allocating memory for
1658 * the descriptor rings and buffers are not within the scope of
1659 * this driver.
1660 * - The user is free from Rx/Tx queue managing.
1661 * - This low level driver introduce functionality API that enable
1662 * the to operate Marvell's Gigabit Ethernet Controller in a
1663 * convenient way.
1664 * - Simple Gigabit Ethernet port operation API.
1665 * - Simple Gigabit Ethernet port data flow API.
1666 * - Data flow and operation API support per queue functionality.
1667 * - Support cached descriptors for better performance.
1668 * - Enable access to all four DRAM banks and internal SRAM memory
1669 * spaces.
1670 * - PHY access and control API.
1671 * - Port control register configuration API.
1672 * - Full control over Unicast and Multicast MAC configurations.
1673 *
1674 * Operation flow:
1675 *
1676 * Initialization phase
1677 * This phase complete the initialization of the the
1678 * mv643xx_private struct.
1679 * User information regarding port configuration has to be set
1680 * prior to calling the port initialization routine.
1681 *
1682 * In this phase any port Tx/Rx activity is halted, MIB counters
1683 * are cleared, PHY address is set according to user parameter and
1684 * access to DRAM and internal SRAM memory spaces.
1685 *
1686 * Driver ring initialization
1687 * Allocating memory for the descriptor rings and buffers is not
1688 * within the scope of this driver. Thus, the user is required to
1689 * allocate memory for the descriptors ring and buffers. Those
1690 * memory parameters are used by the Rx and Tx ring initialization
1691 * routines in order to curve the descriptor linked list in a form
1692 * of a ring.
1693 * Note: Pay special attention to alignment issues when using
1694 * cached descriptors/buffers. In this phase the driver store
1695 * information in the mv643xx_private struct regarding each queue
1696 * ring.
1697 *
1698 * Driver start
1699 * This phase prepares the Ethernet port for Rx and Tx activity.
1700 * It uses the information stored in the mv643xx_private struct to
1701 * initialize the various port registers.
1702 *
1703 * Data flow:
1704 * All packet references to/from the driver are done using
1705 * struct pkt_info.
1706 * This struct is a unified struct used with Rx and Tx operations.
1707 * This way the user is not required to be familiar with neither
1708 * Tx nor Rx descriptors structures.
1709 * The driver's descriptors rings are management by indexes.
1710 * Those indexes controls the ring resources and used to indicate
1711 * a SW resource error:
1712 * 'current'
1713 * This index points to the current available resource for use. For
1714 * example in Rx process this index will point to the descriptor
1715 * that will be passed to the user upon calling the receive
1716 * routine. In Tx process, this index will point to the descriptor
1717 * that will be assigned with the user packet info and transmitted.
1718 * 'used'
1719 * This index points to the descriptor that need to restore its
1720 * resources. For example in Rx process, using the Rx buffer return
1721 * API will attach the buffer returned in packet info to the
1722 * descriptor pointed by 'used'. In Tx process, using the Tx
1723 * descriptor return will merely return the user packet info with
1724 * the command status of the transmitted buffer pointed by the
1725 * 'used' index. Nevertheless, it is essential to use this routine
1726 * to update the 'used' index.
1727 * 'first'
1728 * This index supports Tx Scatter-Gather. It points to the first
1729 * descriptor of a packet assembled of multiple buffers. For
1730 * example when in middle of Such packet we have a Tx resource
1731 * error the 'curr' index get the value of 'first' to indicate
1732 * that the ring returned to its state before trying to transmit
1733 * this packet.
1734 *
1735 * Receive operation:
1736 * The eth_port_receive API set the packet information struct,
1737 * passed by the caller, with received information from the
1738 * 'current' SDMA descriptor.
1739 * It is the user responsibility to return this resource back
1740 * to the Rx descriptor ring to enable the reuse of this source.
1741 * Return Rx resource is done using the eth_rx_return_buff API.
1742 *
1743 * Transmit operation:
1744 * The eth_port_send API supports Scatter-Gather which enables to
1745 * send a packet spanned over multiple buffers. This means that
1746 * for each packet info structure given by the user and put into
1747 * the Tx descriptors ring, will be transmitted only if the 'LAST'
1748 * bit will be set in the packet info command status field. This
1749 * API also consider restriction regarding buffer alignments and
1750 * sizes.
1751 * The user must return a Tx resource after ensuring the buffer
1752 * has been transmitted to enable the Tx ring indexes to update.
1753 *
1754 * BOARD LAYOUT
1755 * This device is on-board. No jumper diagram is necessary.
1756 *
1757 * EXTERNAL INTERFACE
1758 *
1759 * Prior to calling the initialization routine eth_port_init() the user
1760 * must set the following fields under mv643xx_private struct:
1761 * port_num User Ethernet port number.
1762 * port_mac_addr[6] User defined port MAC address.
1763 * port_config User port configuration value.
1764 * port_config_extend User port config extend value.
1765 * port_sdma_config User port SDMA config value.
1766 * port_serial_control User port serial control value.
1767 *
1768 * This driver data flow is done using the struct pkt_info which
1769 * is a unified struct for Rx and Tx operations:
1770 *
1771 * byte_cnt Tx/Rx descriptor buffer byte count.
1772 * l4i_chk CPU provided TCP Checksum. For Tx operation
1773 * only.
1774 * cmd_sts Tx/Rx descriptor command status.
1775 * buf_ptr Tx/Rx descriptor buffer pointer.
1776 * return_info Tx/Rx user resource return information.
1777 */
1778
1779/* defines */
1780/* SDMA command macros */
1781#define ETH_ENABLE_TX_QUEUE(eth_port) \
1782 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), 1)
1783
1784/* locals */
1785
1786/* PHY routines */
1787static int ethernet_phy_get(unsigned int eth_port_num);
1788static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
1789
1790/* Ethernet Port routines */
1791static int eth_port_uc_addr(unsigned int eth_port_num, unsigned char uc_nibble,
1792 int option);
1793
1794/*
1795 * eth_port_init - Initialize the Ethernet port driver
1796 *
1797 * DESCRIPTION:
1798 * This function prepares the ethernet port to start its activity:
1799 * 1) Completes the ethernet port driver struct initialization toward port
1800 * start routine.
1801 * 2) Resets the device to a quiescent state in case of warm reboot.
1802 * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
1803 * 4) Clean MAC tables. The reset status of those tables is unknown.
1804 * 5) Set PHY address.
1805 * Note: Call this routine prior to eth_port_start routine and after
1806 * setting user values in the user fields of Ethernet port control
1807 * struct.
1808 *
1809 * INPUT:
1810 * struct mv643xx_private *mp Ethernet port control struct
1811 *
1812 * OUTPUT:
1813 * See description.
1814 *
1815 * RETURN:
1816 * None.
1817 */
1818static void eth_port_init(struct mv643xx_private *mp)
1819{
1820 mp->port_rx_queue_command = 0;
1821 mp->port_tx_queue_command = 0;
1822
1823 mp->rx_resource_err = 0;
1824 mp->tx_resource_err = 0;
1825
1826 eth_port_reset(mp->port_num);
1827
1828 eth_port_init_mac_tables(mp->port_num);
1829
1830 ethernet_phy_reset(mp->port_num);
1831}
1832
1833/*
1834 * eth_port_start - Start the Ethernet port activity.
1835 *
1836 * DESCRIPTION:
1837 * This routine prepares the Ethernet port for Rx and Tx activity:
1838 * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
1839 * has been initialized a descriptor's ring (using
1840 * ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx)
1841 * 2. Initialize and enable the Ethernet configuration port by writing to
1842 * the port's configuration and command registers.
1843 * 3. Initialize and enable the SDMA by writing to the SDMA's
1844 * configuration and command registers. After completing these steps,
1845 * the ethernet port SDMA can starts to perform Rx and Tx activities.
1846 *
1847 * Note: Each Rx and Tx queue descriptor's list must be initialized prior
1848 * to calling this function (use ether_init_tx_desc_ring for Tx queues
1849 * and ether_init_rx_desc_ring for Rx queues).
1850 *
1851 * INPUT:
1852 * struct mv643xx_private *mp Ethernet port control struct
1853 *
1854 * OUTPUT:
1855 * Ethernet port is ready to receive and transmit.
1856 *
1857 * RETURN:
1858 * None.
1859 */
1860static void eth_port_start(struct mv643xx_private *mp)
1861{
1862 unsigned int port_num = mp->port_num;
1863 int tx_curr_desc, rx_curr_desc;
1864
1865 /* Assignment of Tx CTRP of given queue */
1866 tx_curr_desc = mp->tx_curr_desc_q;
1867 mv_write(MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port_num),
1868 (u32)((struct eth_tx_desc *)mp->tx_desc_dma + tx_curr_desc));
1869
1870 /* Assignment of Rx CRDP of given queue */
1871 rx_curr_desc = mp->rx_curr_desc_q;
1872 mv_write(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num),
1873 (u32)((struct eth_rx_desc *)mp->rx_desc_dma + rx_curr_desc));
1874
1875 /* Add the assigned Ethernet address to the port's address table */
1876 eth_port_uc_addr_set(port_num, mp->port_mac_addr);
1877
1878 /* Assign port configuration and command. */
1879 mv_write(MV643XX_ETH_PORT_CONFIG_REG(port_num), mp->port_config);
1880
1881 mv_write(MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port_num),
1882 mp->port_config_extend);
1883
1884
1885 /* Increase the Rx side buffer size if supporting GigE */
1886 if (mp->port_serial_control & MV643XX_ETH_SET_GMII_SPEED_TO_1000)
1887 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
1888 (mp->port_serial_control & 0xfff1ffff) | (0x5 << 17));
1889 else
1890 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
1891 mp->port_serial_control);
1892
1893 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
1894 mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num)) |
1895 MV643XX_ETH_SERIAL_PORT_ENABLE);
1896
1897 /* Assign port SDMA configuration */
1898 mv_write(MV643XX_ETH_SDMA_CONFIG_REG(port_num),
1899 mp->port_sdma_config);
1900
1901 /* Enable port Rx. */
1902 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num),
1903 mp->port_rx_queue_command);
8f543718
DF		 1904
1905 /* Disable port bandwidth limits by clearing MTU register */
1906 mv_write(MV643XX_ETH_MAXIMUM_TRANSMIT_UNIT(port_num), 0);
1da177e4
LT		 1907}
1908
1909/*
1910 * eth_port_uc_addr_set - This function Set the port Unicast address.
1911 *
1912 * DESCRIPTION:
1913 * This function Set the port Ethernet MAC address.
1914 *
1915 * INPUT:
1916 * unsigned int eth_port_num Port number.
1917 * char * p_addr Address to be set
1918 *
1919 * OUTPUT:
1920 * Set MAC address low and high registers. also calls eth_port_uc_addr()
1921 * To set the unicast table with the proper information.
1922 *
1923 * RETURN:
1924 * N/A.
1925 *
1926 */
1927static void eth_port_uc_addr_set(unsigned int eth_port_num,
1928 unsigned char *p_addr)
1929{
1930 unsigned int mac_h;
1931 unsigned int mac_l;
1932
1933 mac_l = (p_addr[4] << 8) | (p_addr[5]);
1934 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
1935 (p_addr[3] << 0);
1936
1937 mv_write(MV643XX_ETH_MAC_ADDR_LOW(eth_port_num), mac_l);
1938 mv_write(MV643XX_ETH_MAC_ADDR_HIGH(eth_port_num), mac_h);
1939
1940 /* Accept frames of this address */
1941 eth_port_uc_addr(eth_port_num, p_addr[5], ACCEPT_MAC_ADDR);
1942
1943 return;
1944}
1945
1946/*
1947 * eth_port_uc_addr_get - This function retrieves the port Unicast address
1948 * (MAC address) from the ethernet hw registers.
1949 *
1950 * DESCRIPTION:
1951 * This function retrieves the port Ethernet MAC address.
1952 *
1953 * INPUT:
1954 * unsigned int eth_port_num Port number.
1955 * char *MacAddr pointer where the MAC address is stored
1956 *
1957 * OUTPUT:
1958 * Copy the MAC address to the location pointed to by MacAddr
1959 *
1960 * RETURN:
1961 * N/A.
1962 *
1963 */
1964static void eth_port_uc_addr_get(struct net_device *dev, unsigned char *p_addr)
1965{
1966 struct mv643xx_private *mp = netdev_priv(dev);
1967 unsigned int mac_h;
1968 unsigned int mac_l;
1969
1970 mac_h = mv_read(MV643XX_ETH_MAC_ADDR_HIGH(mp->port_num));
1971 mac_l = mv_read(MV643XX_ETH_MAC_ADDR_LOW(mp->port_num));
1972
1973 p_addr[0] = (mac_h >> 24) & 0xff;
1974 p_addr[1] = (mac_h >> 16) & 0xff;
1975 p_addr[2] = (mac_h >> 8) & 0xff;
1976 p_addr[3] = mac_h & 0xff;
1977 p_addr[4] = (mac_l >> 8) & 0xff;
1978 p_addr[5] = mac_l & 0xff;
1979}
1980
1981/*
1982 * eth_port_uc_addr - This function Set the port unicast address table
1983 *
1984 * DESCRIPTION:
1985 * This function locates the proper entry in the Unicast table for the
1986 * specified MAC nibble and sets its properties according to function
1987 * parameters.
1988 *
1989 * INPUT:
1990 * unsigned int eth_port_num Port number.
1991 * unsigned char uc_nibble Unicast MAC Address last nibble.
1992 * int option 0 = Add, 1 = remove address.
1993 *
1994 * OUTPUT:
1995 * This function add/removes MAC addresses from the port unicast address
1996 * table.
1997 *
1998 * RETURN:
1999 * true is output succeeded.
2000 * false if option parameter is invalid.
2001 *
2002 */
2003static int eth_port_uc_addr(unsigned int eth_port_num, unsigned char uc_nibble,
2004 int option)
2005{
2006 unsigned int unicast_reg;
2007 unsigned int tbl_offset;
2008 unsigned int reg_offset;
2009
2010 /* Locate the Unicast table entry */
2011 uc_nibble = (0xf & uc_nibble);
2012 tbl_offset = (uc_nibble / 4) * 4; /* Register offset from unicast table base */
2013 reg_offset = uc_nibble % 4; /* Entry offset within the above register */
2014
2015 switch (option) {
2016 case REJECT_MAC_ADDR:
2017 /* Clear accepts frame bit at given unicast DA table entry */
2018 unicast_reg = mv_read((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2019 (eth_port_num) + tbl_offset));
2020
2021 unicast_reg &= (0x0E << (8 * reg_offset));
2022
2023 mv_write((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2024 (eth_port_num) + tbl_offset), unicast_reg);
2025 break;
2026
2027 case ACCEPT_MAC_ADDR:
2028 /* Set accepts frame bit at unicast DA filter table entry */
2029 unicast_reg =
2030 mv_read((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2031 (eth_port_num) + tbl_offset));
2032
2033 unicast_reg |= (0x01 << (8 * reg_offset));
2034
2035 mv_write((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2036 (eth_port_num) + tbl_offset), unicast_reg);
2037
2038 break;
2039
2040 default:
2041 return 0;
2042 }
2043
2044 return 1;
2045}
2046
2047/*
2048 * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
2049 *
2050 * DESCRIPTION:
2051 * Go through all the DA filter tables (Unicast, Special Multicast &
2052 * Other Multicast) and set each entry to 0.
2053 *
2054 * INPUT:
2055 * unsigned int eth_port_num Ethernet Port number.
2056 *
2057 * OUTPUT:
2058 * Multicast and Unicast packets are rejected.
2059 *
2060 * RETURN:
2061 * None.
2062 */
2063static void eth_port_init_mac_tables(unsigned int eth_port_num)
2064{
2065 int table_index;
2066
2067 /* Clear DA filter unicast table (Ex_dFUT) */
2068 for (table_index = 0; table_index <= 0xC; table_index += 4)
2069 mv_write((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2070 (eth_port_num) + table_index), 0);
2071
2072 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2073 /* Clear DA filter special multicast table (Ex_dFSMT) */
2074 mv_write((MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2075 (eth_port_num) + table_index), 0);
2076 /* Clear DA filter other multicast table (Ex_dFOMT) */
2077 mv_write((MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2078 (eth_port_num) + table_index), 0);
2079 }
2080}
2081
2082/*
2083 * eth_clear_mib_counters - Clear all MIB counters
2084 *
2085 * DESCRIPTION:
2086 * This function clears all MIB counters of a specific ethernet port.
2087 * A read from the MIB counter will reset the counter.
2088 *
2089 * INPUT:
2090 * unsigned int eth_port_num Ethernet Port number.
2091 *
2092 * OUTPUT:
2093 * After reading all MIB counters, the counters resets.
2094 *
2095 * RETURN:
2096 * MIB counter value.
2097 *
2098 */
2099static void eth_clear_mib_counters(unsigned int eth_port_num)
2100{
2101 int i;
2102
2103 /* Perform dummy reads from MIB counters */
2104 for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
2105 i += 4)
2106 mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(eth_port_num) + i);
2107}
2108
2109static inline u32 read_mib(struct mv643xx_private *mp, int offset)
2110{
2111 return mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(mp->port_num) + offset);
2112}
2113
2114static void eth_update_mib_counters(struct mv643xx_private *mp)
2115{
2116 struct mv643xx_mib_counters *p = &mp->mib_counters;
2117 int offset;
2118
2119 p->good_octets_received +=
2120 read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
2121 p->good_octets_received +=
2122 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32;
2123
2124 for (offset = ETH_MIB_BAD_OCTETS_RECEIVED;
2125 offset <= ETH_MIB_FRAMES_1024_TO_MAX_OCTETS;
2126 offset += 4)
2127 *(u32 *)((char *)p + offset) = read_mib(mp, offset);
2128
2129 p->good_octets_sent += read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_LOW);
2130 p->good_octets_sent +=
2131 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_HIGH) << 32;
2132
2133 for (offset = ETH_MIB_GOOD_FRAMES_SENT;
2134 offset <= ETH_MIB_LATE_COLLISION;
2135 offset += 4)
2136 *(u32 *)((char *)p + offset) = read_mib(mp, offset);
2137}
2138
2139/*
2140 * ethernet_phy_detect - Detect whether a phy is present
2141 *
2142 * DESCRIPTION:
2143 * This function tests whether there is a PHY present on
2144 * the specified port.
2145 *
2146 * INPUT:
2147 * unsigned int eth_port_num Ethernet Port number.
2148 *
2149 * OUTPUT:
2150 * None
2151 *
2152 * RETURN:
2153 * 0 on success
2154 * -ENODEV on failure
2155 *
2156 */
2157static int ethernet_phy_detect(unsigned int port_num)
2158{
2159 unsigned int phy_reg_data0;
2160 int auto_neg;
2161
2162 eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
2163 auto_neg = phy_reg_data0 & 0x1000;
2164 phy_reg_data0 ^= 0x1000; /* invert auto_neg */
2165 eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
2166
2167 eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
2168 if ((phy_reg_data0 & 0x1000) == auto_neg)
2169 return -ENODEV; /* change didn't take */
2170
2171 phy_reg_data0 ^= 0x1000;
2172 eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
2173 return 0;
2174}
2175
2176/*
2177 * ethernet_phy_get - Get the ethernet port PHY address.
2178 *
2179 * DESCRIPTION:
2180 * This routine returns the given ethernet port PHY address.
2181 *
2182 * INPUT:
2183 * unsigned int eth_port_num Ethernet Port number.
2184 *
2185 * OUTPUT:
2186 * None.
2187 *
2188 * RETURN:
2189 * PHY address.
2190 *
2191 */
2192static int ethernet_phy_get(unsigned int eth_port_num)
2193{
2194 unsigned int reg_data;
2195
2196 reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG);
2197
2198 return ((reg_data >> (5 * eth_port_num)) & 0x1f);
2199}
2200
2201/*
2202 * ethernet_phy_set - Set the ethernet port PHY address.
2203 *
2204 * DESCRIPTION:
2205 * This routine sets the given ethernet port PHY address.
2206 *
2207 * INPUT:
2208 * unsigned int eth_port_num Ethernet Port number.
2209 * int phy_addr PHY address.
2210 *
2211 * OUTPUT:
2212 * None.
2213 *
2214 * RETURN:
2215 * None.
2216 *
2217 */
2218static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr)
2219{
2220 u32 reg_data;
2221 int addr_shift = 5 * eth_port_num;
2222
2223 reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG);
2224 reg_data &= ~(0x1f << addr_shift);
2225 reg_data |= (phy_addr & 0x1f) << addr_shift;
2226 mv_write(MV643XX_ETH_PHY_ADDR_REG, reg_data);
2227}
2228
2229/*
2230 * ethernet_phy_reset - Reset Ethernet port PHY.
2231 *
2232 * DESCRIPTION:
2233 * This routine utilizes the SMI interface to reset the ethernet port PHY.
2234 *
2235 * INPUT:
2236 * unsigned int eth_port_num Ethernet Port number.
2237 *
2238 * OUTPUT:
2239 * The PHY is reset.
2240 *
2241 * RETURN:
2242 * None.
2243 *
2244 */
2245static void ethernet_phy_reset(unsigned int eth_port_num)
2246{
2247 unsigned int phy_reg_data;
2248
2249 /* Reset the PHY */
2250 eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data);
2251 phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
2252 eth_port_write_smi_reg(eth_port_num, 0, phy_reg_data);
2253}
2254
2255/*
2256 * eth_port_reset - Reset Ethernet port
2257 *
2258 * DESCRIPTION:
2259 * This routine resets the chip by aborting any SDMA engine activity and
2260 * clearing the MIB counters. The Receiver and the Transmit unit are in
2261 * idle state after this command is performed and the port is disabled.
2262 *
2263 * INPUT:
2264 * unsigned int eth_port_num Ethernet Port number.
2265 *
2266 * OUTPUT:
2267 * Channel activity is halted.
2268 *
2269 * RETURN:
2270 * None.
2271 *
2272 */
2273static void eth_port_reset(unsigned int port_num)
2274{
2275 unsigned int reg_data;
2276
2277 /* Stop Tx port activity. Check port Tx activity. */
2278 reg_data = mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num));
2279
2280 if (reg_data & 0xFF) {
2281 /* Issue stop command for active channels only */
2282 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num),
2283 (reg_data << 8));
2284
2285 /* Wait for all Tx activity to terminate. */
2286 /* Check port cause register that all Tx queues are stopped */
2287 while (mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num))
2288 & 0xFF)
2289 udelay(10);
2290 }
2291
2292 /* Stop Rx port activity. Check port Rx activity. */
2293 reg_data = mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num));
2294
2295 if (reg_data & 0xFF) {
2296 /* Issue stop command for active channels only */
2297 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num),
2298 (reg_data << 8));
2299
2300 /* Wait for all Rx activity to terminate. */
2301 /* Check port cause register that all Rx queues are stopped */
2302 while (mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num))
2303 & 0xFF)
2304 udelay(10);
2305 }
2306
2307 /* Clear all MIB counters */
2308 eth_clear_mib_counters(port_num);
2309
2310 /* Reset the Enable bit in the Configuration Register */
2311 reg_data = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
2312 reg_data &= ~MV643XX_ETH_SERIAL_PORT_ENABLE;
2313 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), reg_data);
2314}
2315
1da177e4
LT		 2316
2317static int eth_port_autoneg_supported(unsigned int eth_port_num)
2318{
2319 unsigned int phy_reg_data0;
2320
2321 eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data0);
2322
2323 return phy_reg_data0 & 0x1000;
2324}
2325
2326static int eth_port_link_is_up(unsigned int eth_port_num)
2327{
2328 unsigned int phy_reg_data1;
2329
2330 eth_port_read_smi_reg(eth_port_num, 1, &phy_reg_data1);
2331
2332 if (eth_port_autoneg_supported(eth_port_num)) {
2333 if (phy_reg_data1 & 0x20) /* auto-neg complete */
2334 return 1;
2335 } else if (phy_reg_data1 & 0x4) /* link up */
2336 return 1;
2337
2338 return 0;
2339}
2340
1da177e4
LT		 2341/*
2342 * eth_port_read_smi_reg - Read PHY registers
2343 *
2344 * DESCRIPTION:
2345 * This routine utilize the SMI interface to interact with the PHY in
2346 * order to perform PHY register read.
2347 *
2348 * INPUT:
2349 * unsigned int port_num Ethernet Port number.
2350 * unsigned int phy_reg PHY register address offset.
2351 * unsigned int *value Register value buffer.
2352 *
2353 * OUTPUT:
2354 * Write the value of a specified PHY register into given buffer.
2355 *
2356 * RETURN:
2357 * false if the PHY is busy or read data is not in valid state.
2358 * true otherwise.
2359 *
2360 */
2361static void eth_port_read_smi_reg(unsigned int port_num,
2362 unsigned int phy_reg, unsigned int *value)
2363{
2364 int phy_addr = ethernet_phy_get(port_num);
2365 unsigned long flags;
2366 int i;
2367
2368 /* the SMI register is a shared resource */
2369 spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
2370
2371 /* wait for the SMI register to become available */
2372 for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) {
2373 if (i == PHY_WAIT_ITERATIONS) {
2374 printk("mv643xx PHY busy timeout, port %d\n", port_num);
2375 goto out;
2376 }
2377 udelay(PHY_WAIT_MICRO_SECONDS);
2378 }
2379
2380 mv_write(MV643XX_ETH_SMI_REG,
2381 (phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ);
2382
2383 /* now wait for the data to be valid */
2384 for (i = 0; !(mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_READ_VALID); i++) {
2385 if (i == PHY_WAIT_ITERATIONS) {
2386 printk("mv643xx PHY read timeout, port %d\n", port_num);
2387 goto out;
2388 }
2389 udelay(PHY_WAIT_MICRO_SECONDS);
2390 }
2391
2392 *value = mv_read(MV643XX_ETH_SMI_REG) & 0xffff;
2393out:
2394 spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
2395}
2396
2397/*
2398 * eth_port_write_smi_reg - Write to PHY registers
2399 *
2400 * DESCRIPTION:
2401 * This routine utilize the SMI interface to interact with the PHY in
2402 * order to perform writes to PHY registers.
2403 *
2404 * INPUT:
2405 * unsigned int eth_port_num Ethernet Port number.
2406 * unsigned int phy_reg PHY register address offset.
2407 * unsigned int value Register value.
2408 *
2409 * OUTPUT:
2410 * Write the given value to the specified PHY register.
2411 *
2412 * RETURN:
2413 * false if the PHY is busy.
2414 * true otherwise.
2415 *
2416 */
2417static void eth_port_write_smi_reg(unsigned int eth_port_num,
2418 unsigned int phy_reg, unsigned int value)
2419{
2420 int phy_addr;
2421 int i;
2422 unsigned long flags;
2423
2424 phy_addr = ethernet_phy_get(eth_port_num);
2425
2426 /* the SMI register is a shared resource */
2427 spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
2428
2429 /* wait for the SMI register to become available */
2430 for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) {
2431 if (i == PHY_WAIT_ITERATIONS) {
2432 printk("mv643xx PHY busy timeout, port %d\n",
2433 eth_port_num);
2434 goto out;
2435 }
2436 udelay(PHY_WAIT_MICRO_SECONDS);
2437 }
2438
2439 mv_write(MV643XX_ETH_SMI_REG, (phy_addr << 16) | (phy_reg << 21) |
2440 ETH_SMI_OPCODE_WRITE | (value & 0xffff));
2441out:
2442 spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
2443}
2444
2445/*
2446 * eth_port_send - Send an Ethernet packet
2447 *
2448 * DESCRIPTION:
2449 * This routine send a given packet described by p_pktinfo parameter. It
2450 * supports transmitting of a packet spaned over multiple buffers. The
2451 * routine updates 'curr' and 'first' indexes according to the packet
2452 * segment passed to the routine. In case the packet segment is first,
2453 * the 'first' index is update. In any case, the 'curr' index is updated.
2454 * If the routine get into Tx resource error it assigns 'curr' index as
2455 * 'first'. This way the function can abort Tx process of multiple
2456 * descriptors per packet.
2457 *
2458 * INPUT:
2459 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2460 * struct pkt_info *p_pkt_info User packet buffer.
2461 *
2462 * OUTPUT:
2463 * Tx ring 'curr' and 'first' indexes are updated.
2464 *
2465 * RETURN:
2466 * ETH_QUEUE_FULL in case of Tx resource error.
2467 * ETH_ERROR in case the routine can not access Tx desc ring.
2468 * ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource.
2469 * ETH_OK otherwise.
2470 *
2471 */
2472#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
2473/*
2474 * Modified to include the first descriptor pointer in case of SG
2475 */
2476static ETH_FUNC_RET_STATUS eth_port_send(struct mv643xx_private *mp,
2477 struct pkt_info *p_pkt_info)
2478{
2479 int tx_desc_curr, tx_desc_used, tx_first_desc, tx_next_desc;
2480 struct eth_tx_desc *current_descriptor;
2481 struct eth_tx_desc *first_descriptor;
2482 u32 command;
2483
2484 /* Do not process Tx ring in case of Tx ring resource error */
2485 if (mp->tx_resource_err)
2486 return ETH_QUEUE_FULL;
2487
2488 /*
2489 * The hardware requires that each buffer that is <= 8 bytes
2490 * in length must be aligned on an 8 byte boundary.
2491 */
2492 if (p_pkt_info->byte_cnt <= 8 && p_pkt_info->buf_ptr & 0x7) {
2493 printk(KERN_ERR
2494 "mv643xx_eth port %d: packet size <= 8 problem\n",
2495 mp->port_num);
2496 return ETH_ERROR;
2497 }
2498
b111ceb6
DF		 2499 mp->tx_ring_skbs++;
2500 BUG_ON(mp->tx_ring_skbs > mp->tx_ring_size);
2501
1da177e4
LT		 2502 /* Get the Tx Desc ring indexes */
2503 tx_desc_curr = mp->tx_curr_desc_q;
2504 tx_desc_used = mp->tx_used_desc_q;
2505
2506 current_descriptor = &mp->p_tx_desc_area[tx_desc_curr];
2507
2508 tx_next_desc = (tx_desc_curr + 1) % mp->tx_ring_size;
2509
2510 current_descriptor->buf_ptr = p_pkt_info->buf_ptr;
2511 current_descriptor->byte_cnt = p_pkt_info->byte_cnt;
2512 current_descriptor->l4i_chk = p_pkt_info->l4i_chk;
2513 mp->tx_skb[tx_desc_curr] = p_pkt_info->return_info;
2514
2515 command = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC |
2516 ETH_BUFFER_OWNED_BY_DMA;
2517 if (command & ETH_TX_FIRST_DESC) {
2518 tx_first_desc = tx_desc_curr;
2519 mp->tx_first_desc_q = tx_first_desc;
2520 first_descriptor = current_descriptor;
2521 mp->tx_first_command = command;
2522 } else {
2523 tx_first_desc = mp->tx_first_desc_q;
2524 first_descriptor = &mp->p_tx_desc_area[tx_first_desc];
2525 BUG_ON(first_descriptor == NULL);
2526 current_descriptor->cmd_sts = command;
2527 }
2528
2529 if (command & ETH_TX_LAST_DESC) {
2530 wmb();
2531 first_descriptor->cmd_sts = mp->tx_first_command;
2532
2533 wmb();
2534 ETH_ENABLE_TX_QUEUE(mp->port_num);
2535
2536 /*
2537 * Finish Tx packet. Update first desc in case of Tx resource
2538 * error */
2539 tx_first_desc = tx_next_desc;
2540 mp->tx_first_desc_q = tx_first_desc;
2541 }
2542
2543 /* Check for ring index overlap in the Tx desc ring */
2544 if (tx_next_desc == tx_desc_used) {
2545 mp->tx_resource_err = 1;
2546 mp->tx_curr_desc_q = tx_first_desc;
2547
2548 return ETH_QUEUE_LAST_RESOURCE;
2549 }
2550
2551 mp->tx_curr_desc_q = tx_next_desc;
2552
2553 return ETH_OK;
2554}
2555#else
2556static ETH_FUNC_RET_STATUS eth_port_send(struct mv643xx_private *mp,
2557 struct pkt_info *p_pkt_info)
2558{
2559 int tx_desc_curr;
2560 int tx_desc_used;
2561 struct eth_tx_desc *current_descriptor;
2562 unsigned int command_status;
2563
2564 /* Do not process Tx ring in case of Tx ring resource error */
2565 if (mp->tx_resource_err)
2566 return ETH_QUEUE_FULL;
2567
b111ceb6
DF		 2568 mp->tx_ring_skbs++;
2569 BUG_ON(mp->tx_ring_skbs > mp->tx_ring_size);
2570
1da177e4
LT		 2571 /* Get the Tx Desc ring indexes */
2572 tx_desc_curr = mp->tx_curr_desc_q;
2573 tx_desc_used = mp->tx_used_desc_q;
2574 current_descriptor = &mp->p_tx_desc_area[tx_desc_curr];
2575
2576 command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC;
2577 current_descriptor->buf_ptr = p_pkt_info->buf_ptr;
2578 current_descriptor->byte_cnt = p_pkt_info->byte_cnt;
2579 mp->tx_skb[tx_desc_curr] = p_pkt_info->return_info;
2580
2581 /* Set last desc with DMA ownership and interrupt enable. */
2582 wmb();
2583 current_descriptor->cmd_sts = command_status |
2584 ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT;
2585
2586 wmb();
2587 ETH_ENABLE_TX_QUEUE(mp->port_num);
2588
2589 /* Finish Tx packet. Update first desc in case of Tx resource error */
2590 tx_desc_curr = (tx_desc_curr + 1) % mp->tx_ring_size;
2591
2592 /* Update the current descriptor */
2593 mp->tx_curr_desc_q = tx_desc_curr;
2594
2595 /* Check for ring index overlap in the Tx desc ring */
2596 if (tx_desc_curr == tx_desc_used) {
2597 mp->tx_resource_err = 1;
2598 return ETH_QUEUE_LAST_RESOURCE;
2599 }
2600
2601 return ETH_OK;
2602}
2603#endif
2604
2605/*
2606 * eth_tx_return_desc - Free all used Tx descriptors
2607 *
2608 * DESCRIPTION:
2609 * This routine returns the transmitted packet information to the caller.
2610 * It uses the 'first' index to support Tx desc return in case a transmit
2611 * of a packet spanned over multiple buffer still in process.
2612 * In case the Tx queue was in "resource error" condition, where there are
2613 * no available Tx resources, the function resets the resource error flag.
2614 *
2615 * INPUT:
2616 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2617 * struct pkt_info *p_pkt_info User packet buffer.
2618 *
2619 * OUTPUT:
2620 * Tx ring 'first' and 'used' indexes are updated.
2621 *
2622 * RETURN:
2623 * ETH_ERROR in case the routine can not access Tx desc ring.
2624 * ETH_RETRY in case there is transmission in process.
2625 * ETH_END_OF_JOB if the routine has nothing to release.
2626 * ETH_OK otherwise.
2627 *
2628 */
2629static ETH_FUNC_RET_STATUS eth_tx_return_desc(struct mv643xx_private *mp,
2630 struct pkt_info *p_pkt_info)
2631{
2632 int tx_desc_used;
2633#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
2634 int tx_busy_desc = mp->tx_first_desc_q;
2635#else
2636 int tx_busy_desc = mp->tx_curr_desc_q;
2637#endif
2638 struct eth_tx_desc *p_tx_desc_used;
2639 unsigned int command_status;
2640
2641 /* Get the Tx Desc ring indexes */
2642 tx_desc_used = mp->tx_used_desc_q;
2643
2644 p_tx_desc_used = &mp->p_tx_desc_area[tx_desc_used];
2645
2646 /* Sanity check */
2647 if (p_tx_desc_used == NULL)
2648 return ETH_ERROR;
2649
2650 /* Stop release. About to overlap the current available Tx descriptor */
2651 if (tx_desc_used == tx_busy_desc && !mp->tx_resource_err)
2652 return ETH_END_OF_JOB;
2653
2654 command_status = p_tx_desc_used->cmd_sts;
2655
2656 /* Still transmitting... */
2657 if (command_status & (ETH_BUFFER_OWNED_BY_DMA))
2658 return ETH_RETRY;
2659
2660 /* Pass the packet information to the caller */
2661 p_pkt_info->cmd_sts = command_status;
2662 p_pkt_info->return_info = mp->tx_skb[tx_desc_used];
4eaa3cb3
PG		 2663 p_pkt_info->buf_ptr = p_tx_desc_used->buf_ptr;
2664 p_pkt_info->byte_cnt = p_tx_desc_used->byte_cnt;
1da177e4
LT		 2665 mp->tx_skb[tx_desc_used] = NULL;
2666
2667 /* Update the next descriptor to release. */
2668 mp->tx_used_desc_q = (tx_desc_used + 1) % mp->tx_ring_size;
2669
2670 /* Any Tx return cancels the Tx resource error status */
2671 mp->tx_resource_err = 0;
2672
b111ceb6
DF		 2673 BUG_ON(mp->tx_ring_skbs == 0);
2674 mp->tx_ring_skbs--;
2675
1da177e4
LT		 2676 return ETH_OK;
2677}
2678
2679/*
2680 * eth_port_receive - Get received information from Rx ring.
2681 *
2682 * DESCRIPTION:
2683 * This routine returns the received data to the caller. There is no
2684 * data copying during routine operation. All information is returned
2685 * using pointer to packet information struct passed from the caller.
2686 * If the routine exhausts Rx ring resources then the resource error flag
2687 * is set.
2688 *
2689 * INPUT:
2690 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2691 * struct pkt_info *p_pkt_info User packet buffer.
2692 *
2693 * OUTPUT:
2694 * Rx ring current and used indexes are updated.
2695 *
2696 * RETURN:
2697 * ETH_ERROR in case the routine can not access Rx desc ring.
2698 * ETH_QUEUE_FULL if Rx ring resources are exhausted.
2699 * ETH_END_OF_JOB if there is no received data.
2700 * ETH_OK otherwise.
2701 */
2702static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
2703 struct pkt_info *p_pkt_info)
2704{
2705 int rx_next_curr_desc, rx_curr_desc, rx_used_desc;
2706 volatile struct eth_rx_desc *p_rx_desc;
2707 unsigned int command_status;
2708
2709 /* Do not process Rx ring in case of Rx ring resource error */
2710 if (mp->rx_resource_err)
2711 return ETH_QUEUE_FULL;
2712
2713 /* Get the Rx Desc ring 'curr and 'used' indexes */
2714 rx_curr_desc = mp->rx_curr_desc_q;
2715 rx_used_desc = mp->rx_used_desc_q;
2716
2717 p_rx_desc = &mp->p_rx_desc_area[rx_curr_desc];
2718
2719 /* The following parameters are used to save readings from memory */
2720 command_status = p_rx_desc->cmd_sts;
2721 rmb();
2722
2723 /* Nothing to receive... */
2724 if (command_status & (ETH_BUFFER_OWNED_BY_DMA))
2725 return ETH_END_OF_JOB;
2726
2727 p_pkt_info->byte_cnt = (p_rx_desc->byte_cnt) - RX_BUF_OFFSET;
2728 p_pkt_info->cmd_sts = command_status;
2729 p_pkt_info->buf_ptr = (p_rx_desc->buf_ptr) + RX_BUF_OFFSET;
2730 p_pkt_info->return_info = mp->rx_skb[rx_curr_desc];
2731 p_pkt_info->l4i_chk = p_rx_desc->buf_size;
2732
2733 /* Clean the return info field to indicate that the packet has been */
2734 /* moved to the upper layers */
2735 mp->rx_skb[rx_curr_desc] = NULL;
2736
2737 /* Update current index in data structure */
2738 rx_next_curr_desc = (rx_curr_desc + 1) % mp->rx_ring_size;
2739 mp->rx_curr_desc_q = rx_next_curr_desc;
2740
2741 /* Rx descriptors exhausted. Set the Rx ring resource error flag */
2742 if (rx_next_curr_desc == rx_used_desc)
2743 mp->rx_resource_err = 1;
2744
2745 return ETH_OK;
2746}
2747
2748/*
2749 * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
2750 *
2751 * DESCRIPTION:
2752 * This routine returns a Rx buffer back to the Rx ring. It retrieves the
2753 * next 'used' descriptor and attached the returned buffer to it.
2754 * In case the Rx ring was in "resource error" condition, where there are
2755 * no available Rx resources, the function resets the resource error flag.
2756 *
2757 * INPUT:
2758 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2759 * struct pkt_info *p_pkt_info Information on returned buffer.
2760 *
2761 * OUTPUT:
2762 * New available Rx resource in Rx descriptor ring.
2763 *
2764 * RETURN:
2765 * ETH_ERROR in case the routine can not access Rx desc ring.
2766 * ETH_OK otherwise.
2767 */
2768static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
2769 struct pkt_info *p_pkt_info)
2770{
2771 int used_rx_desc; /* Where to return Rx resource */
2772 volatile struct eth_rx_desc *p_used_rx_desc;
2773
2774 /* Get 'used' Rx descriptor */
2775 used_rx_desc = mp->rx_used_desc_q;
2776 p_used_rx_desc = &mp->p_rx_desc_area[used_rx_desc];
2777
2778 p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
2779 p_used_rx_desc->buf_size = p_pkt_info->byte_cnt;
2780 mp->rx_skb[used_rx_desc] = p_pkt_info->return_info;
2781
2782 /* Flush the write pipe */
2783
2784 /* Return the descriptor to DMA ownership */
2785 wmb();
2786 p_used_rx_desc->cmd_sts =
2787 ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
2788 wmb();
2789
2790 /* Move the used descriptor pointer to the next descriptor */
2791 mp->rx_used_desc_q = (used_rx_desc + 1) % mp->rx_ring_size;
2792
2793 /* Any Rx return cancels the Rx resource error status */
2794 mp->rx_resource_err = 0;
2795
2796 return ETH_OK;
2797}
2798
2799/************* Begin ethtool support *************************/
2800
2801struct mv643xx_stats {
2802 char stat_string[ETH_GSTRING_LEN];
2803 int sizeof_stat;
2804 int stat_offset;
2805};
2806
2807#define MV643XX_STAT(m) sizeof(((struct mv643xx_private *)0)->m), \
2808 offsetof(struct mv643xx_private, m)
2809
2810static const struct mv643xx_stats mv643xx_gstrings_stats[] = {
2811 { "rx_packets", MV643XX_STAT(stats.rx_packets) },
2812 { "tx_packets", MV643XX_STAT(stats.tx_packets) },
2813 { "rx_bytes", MV643XX_STAT(stats.rx_bytes) },
2814 { "tx_bytes", MV643XX_STAT(stats.tx_bytes) },
2815 { "rx_errors", MV643XX_STAT(stats.rx_errors) },
2816 { "tx_errors", MV643XX_STAT(stats.tx_errors) },
2817 { "rx_dropped", MV643XX_STAT(stats.rx_dropped) },
2818 { "tx_dropped", MV643XX_STAT(stats.tx_dropped) },
2819 { "good_octets_received", MV643XX_STAT(mib_counters.good_octets_received) },
2820 { "bad_octets_received", MV643XX_STAT(mib_counters.bad_octets_received) },
2821 { "internal_mac_transmit_err", MV643XX_STAT(mib_counters.internal_mac_transmit_err) },
2822 { "good_frames_received", MV643XX_STAT(mib_counters.good_frames_received) },
2823 { "bad_frames_received", MV643XX_STAT(mib_counters.bad_frames_received) },
2824 { "broadcast_frames_received", MV643XX_STAT(mib_counters.broadcast_frames_received) },
2825 { "multicast_frames_received", MV643XX_STAT(mib_counters.multicast_frames_received) },
2826 { "frames_64_octets", MV643XX_STAT(mib_counters.frames_64_octets) },
2827 { "frames_65_to_127_octets", MV643XX_STAT(mib_counters.frames_65_to_127_octets) },
2828 { "frames_128_to_255_octets", MV643XX_STAT(mib_counters.frames_128_to_255_octets) },
2829 { "frames_256_to_511_octets", MV643XX_STAT(mib_counters.frames_256_to_511_octets) },
2830 { "frames_512_to_1023_octets", MV643XX_STAT(mib_counters.frames_512_to_1023_octets) },
2831 { "frames_1024_to_max_octets", MV643XX_STAT(mib_counters.frames_1024_to_max_octets) },
2832 { "good_octets_sent", MV643XX_STAT(mib_counters.good_octets_sent) },
2833 { "good_frames_sent", MV643XX_STAT(mib_counters.good_frames_sent) },
2834 { "excessive_collision", MV643XX_STAT(mib_counters.excessive_collision) },
2835 { "multicast_frames_sent", MV643XX_STAT(mib_counters.multicast_frames_sent) },
2836 { "broadcast_frames_sent", MV643XX_STAT(mib_counters.broadcast_frames_sent) },
2837 { "unrec_mac_control_received", MV643XX_STAT(mib_counters.unrec_mac_control_received) },
2838 { "fc_sent", MV643XX_STAT(mib_counters.fc_sent) },
2839 { "good_fc_received", MV643XX_STAT(mib_counters.good_fc_received) },
2840 { "bad_fc_received", MV643XX_STAT(mib_counters.bad_fc_received) },
2841 { "undersize_received", MV643XX_STAT(mib_counters.undersize_received) },
2842 { "fragments_received", MV643XX_STAT(mib_counters.fragments_received) },
2843 { "oversize_received", MV643XX_STAT(mib_counters.oversize_received) },
2844 { "jabber_received", MV643XX_STAT(mib_counters.jabber_received) },
2845 { "mac_receive_error", MV643XX_STAT(mib_counters.mac_receive_error) },
2846 { "bad_crc_event", MV643XX_STAT(mib_counters.bad_crc_event) },
2847 { "collision", MV643XX_STAT(mib_counters.collision) },
2848 { "late_collision", MV643XX_STAT(mib_counters.late_collision) },
2849};
2850
2851#define MV643XX_STATS_LEN \
2852 sizeof(mv643xx_gstrings_stats) / sizeof(struct mv643xx_stats)
2853
2854static int
2855mv643xx_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
2856{
2857 struct mv643xx_private *mp = netdev->priv;
2858 int port_num = mp->port_num;
2859 int autoneg = eth_port_autoneg_supported(port_num);
2860 int mode_10_bit;
2861 int auto_duplex;
2862 int half_duplex = 0;
2863 int full_duplex = 0;
2864 int auto_speed;
2865 int speed_10 = 0;
2866 int speed_100 = 0;
2867 int speed_1000 = 0;
2868
2869 u32 pcs = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
2870 u32 psr = mv_read(MV643XX_ETH_PORT_STATUS_REG(port_num));
2871
2872 mode_10_bit = psr & MV643XX_ETH_PORT_STATUS_MODE_10_BIT;
2873
2874 if (mode_10_bit) {
2875 ecmd->supported = SUPPORTED_10baseT_Half;
2876 } else {
2877 ecmd->supported = (SUPPORTED_10baseT_Half |
2878 SUPPORTED_10baseT_Full |
2879 SUPPORTED_100baseT_Half |
2880 SUPPORTED_100baseT_Full |
2881 SUPPORTED_1000baseT_Full |
2882 (autoneg ? SUPPORTED_Autoneg : 0) |
2883 SUPPORTED_TP);
2884
2885 auto_duplex = !(pcs & MV643XX_ETH_DISABLE_AUTO_NEG_FOR_DUPLX);
2886 auto_speed = !(pcs & MV643XX_ETH_DISABLE_AUTO_NEG_SPEED_GMII);
2887
2888 ecmd->advertising = ADVERTISED_TP;
2889
2890 if (autoneg) {
2891 ecmd->advertising |= ADVERTISED_Autoneg;
2892
2893 if (auto_duplex) {
2894 half_duplex = 1;
2895 full_duplex = 1;
2896 } else {
2897 if (pcs & MV643XX_ETH_SET_FULL_DUPLEX_MODE)
2898 full_duplex = 1;
2899 else
2900 half_duplex = 1;
2901 }
2902
2903 if (auto_speed) {
2904 speed_10 = 1;
2905 speed_100 = 1;
2906 speed_1000 = 1;
2907 } else {
2908 if (pcs & MV643XX_ETH_SET_GMII_SPEED_TO_1000)
2909 speed_1000 = 1;
2910 else if (pcs & MV643XX_ETH_SET_MII_SPEED_TO_100)
2911 speed_100 = 1;
2912 else
2913 speed_10 = 1;
2914 }
2915
2916 if (speed_10 & half_duplex)
2917 ecmd->advertising |= ADVERTISED_10baseT_Half;
2918 if (speed_10 & full_duplex)
2919 ecmd->advertising |= ADVERTISED_10baseT_Full;
2920 if (speed_100 & half_duplex)
2921 ecmd->advertising |= ADVERTISED_100baseT_Half;
2922 if (speed_100 & full_duplex)
2923 ecmd->advertising |= ADVERTISED_100baseT_Full;
2924 if (speed_1000)
2925 ecmd->advertising |= ADVERTISED_1000baseT_Full;
2926 }
2927 }
2928
2929 ecmd->port = PORT_TP;
2930 ecmd->phy_address = ethernet_phy_get(port_num);
2931
2932 ecmd->transceiver = XCVR_EXTERNAL;
2933
2934 if (netif_carrier_ok(netdev)) {
2935 if (mode_10_bit)
2936 ecmd->speed = SPEED_10;
2937 else {
2938 if (psr & MV643XX_ETH_PORT_STATUS_GMII_1000)
2939 ecmd->speed = SPEED_1000;
2940 else if (psr & MV643XX_ETH_PORT_STATUS_MII_100)
2941 ecmd->speed = SPEED_100;
2942 else
2943 ecmd->speed = SPEED_10;
2944 }
2945
2946 if (psr & MV643XX_ETH_PORT_STATUS_FULL_DUPLEX)
2947 ecmd->duplex = DUPLEX_FULL;
2948 else
2949 ecmd->duplex = DUPLEX_HALF;
2950 } else {
2951 ecmd->speed = -1;
2952 ecmd->duplex = -1;
2953 }
2954
2955 ecmd->autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
2956 return 0;
2957}
2958
2959static void
2960mv643xx_get_drvinfo(struct net_device *netdev,
2961 struct ethtool_drvinfo *drvinfo)
2962{
2963 strncpy(drvinfo->driver, mv643xx_driver_name, 32);
2964 strncpy(drvinfo->version, mv643xx_driver_version, 32);
2965 strncpy(drvinfo->fw_version, "N/A", 32);
2966 strncpy(drvinfo->bus_info, "mv643xx", 32);
2967 drvinfo->n_stats = MV643XX_STATS_LEN;
2968}
2969
2970static int
2971mv643xx_get_stats_count(struct net_device *netdev)
2972{
2973 return MV643XX_STATS_LEN;
2974}
2975
2976static void
2977mv643xx_get_ethtool_stats(struct net_device *netdev,
2978 struct ethtool_stats *stats, uint64_t *data)
2979{
2980 struct mv643xx_private *mp = netdev->priv;
2981 int i;
2982
2983 eth_update_mib_counters(mp);
2984
2985 for(i = 0; i < MV643XX_STATS_LEN; i++) {
2986 char *p = (char *)mp+mv643xx_gstrings_stats[i].stat_offset;
2987 data[i] = (mv643xx_gstrings_stats[i].sizeof_stat ==
2988 sizeof(uint64_t)) ? *(uint64_t *)p : *(uint32_t *)p;
2989 }
2990}
2991
2992static void
2993mv643xx_get_strings(struct net_device *netdev, uint32_t stringset, uint8_t *data)
2994{
2995 int i;
2996
2997 switch(stringset) {
2998 case ETH_SS_STATS:
2999 for (i=0; i < MV643XX_STATS_LEN; i++) {
3000 memcpy(data + i * ETH_GSTRING_LEN,
3001 mv643xx_gstrings_stats[i].stat_string,
3002 ETH_GSTRING_LEN);
3003 }
3004 break;
3005 }
3006}
3007
3008static struct ethtool_ops mv643xx_ethtool_ops = {
3009 .get_settings = mv643xx_get_settings,
3010 .get_drvinfo = mv643xx_get_drvinfo,
3011 .get_link = ethtool_op_get_link,
3012 .get_sg = ethtool_op_get_sg,
3013 .set_sg = ethtool_op_set_sg,
3014 .get_strings = mv643xx_get_strings,
3015 .get_stats_count = mv643xx_get_stats_count,
3016 .get_ethtool_stats = mv643xx_get_ethtool_stats,
3017};
3018
3019/************* End ethtool support *************************/
Linux 6.x block layer and io_uring tree(s)