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[PATCH] mv643xx_eth: Fix transmit skb accounting
[linux-2.6-block.git] / drivers / net / mv643xx_eth.c
CommitLineData
1da177e4
LT		 1/*
2 * drivers/net/mv643xx_eth.c - Driver for MV643XX ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 rabeeh@galileo.co.il
7 *
8 * Copyright (C) 2003 PMC-Sierra, Inc.,
3bb8a18a 9 * written by Manish Lachwani
1da177e4
LT		 10 *
11 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
12 *
13 * Copyright (C) 2004-2005 MontaVista Software, Inc.
14 * Dale Farnsworth <dale@farnsworth.org>
15 *
16 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
17 * <sjhill@realitydiluted.com>
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version 2
22 * of the License, or (at your option) any later version.
23 *
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
28 *
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
32 */
33#include <linux/init.h>
34#include <linux/dma-mapping.h>
35#include <linux/tcp.h>
36#include <linux/udp.h>
37#include <linux/etherdevice.h>
78a5e534
OH		 38#include <linux/in.h>
39#include <linux/ip.h>
1da177e4
LT		 40
41#include <linux/bitops.h>
42#include <linux/delay.h>
43#include <linux/ethtool.h>
d052d1be
RK		 44#include <linux/platform_device.h>
45
1da177e4
LT		 46#include <asm/io.h>
47#include <asm/types.h>
48#include <asm/pgtable.h>
49#include <asm/system.h>
50#include <asm/delay.h>
51#include "mv643xx_eth.h"
52
53/*
54 * The first part is the high level driver of the gigE ethernet ports.
55 */
56
57/* Constants */
58#define VLAN_HLEN 4
59#define FCS_LEN 4
b44cd572
DF		 60#define DMA_ALIGN 8 /* hw requires 8-byte alignment */
61#define HW_IP_ALIGN 2 /* hw aligns IP header */
62#define WRAP HW_IP_ALIGN + ETH_HLEN + VLAN_HLEN + FCS_LEN
1da177e4
LT		 63#define RX_SKB_SIZE ((dev->mtu + WRAP + 7) & ~0x7)
64
65#define INT_CAUSE_UNMASK_ALL 0x0007ffff
66#define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff
1da177e4 67#define INT_CAUSE_MASK_ALL 0x00000000
63c9e549 68#define INT_CAUSE_MASK_ALL_EXT 0x00000000
1da177e4
LT		 69#define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL
70#define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT
1da177e4
LT		 71
72#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
73#define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
74#else
75#define MAX_DESCS_PER_SKB 1
76#endif
77
78#define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */
79#define PHY_WAIT_MICRO_SECONDS 10
80
81/* Static function declarations */
82static int eth_port_link_is_up(unsigned int eth_port_num);
83static void eth_port_uc_addr_get(struct net_device *dev,
84 unsigned char *MacAddr);
16e03018 85static void eth_port_set_multicast_list(struct net_device *);
1da177e4
LT		 86static int mv643xx_eth_real_open(struct net_device *);
87static int mv643xx_eth_real_stop(struct net_device *);
88static int mv643xx_eth_change_mtu(struct net_device *, int);
89static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *);
90static void eth_port_init_mac_tables(unsigned int eth_port_num);
91#ifdef MV643XX_NAPI
92static int mv643xx_poll(struct net_device *dev, int *budget);
93#endif
94static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
95static int ethernet_phy_detect(unsigned int eth_port_num);
96static struct ethtool_ops mv643xx_ethtool_ops;
97
98static char mv643xx_driver_name[] = "mv643xx_eth";
99static char mv643xx_driver_version[] = "1.0";
100
101static void __iomem *mv643xx_eth_shared_base;
102
103/* used to protect MV643XX_ETH_SMI_REG, which is shared across ports */
a9f6a0dd 104static DEFINE_SPINLOCK(mv643xx_eth_phy_lock);
1da177e4
LT		 105
106static inline u32 mv_read(int offset)
107{
dc074a8a 108 void __iomem *reg_base;
1da177e4
LT		 109
110 reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS;
111
112 return readl(reg_base + offset);
113}
114
115static inline void mv_write(int offset, u32 data)
116{
dc074a8a 117 void __iomem *reg_base;
1da177e4
LT		 118
119 reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS;
120 writel(data, reg_base + offset);
121}
122
123/*
124 * Changes MTU (maximum transfer unit) of the gigabit ethenret port
125 *
126 * Input : pointer to ethernet interface network device structure
127 * new mtu size
128 * Output : 0 upon success, -EINVAL upon failure
129 */
130static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
131{
8f518703 132 if ((new_mtu > 9500) || (new_mtu < 64))
1da177e4 133 return -EINVAL;
1da177e4
LT		 134
135 dev->mtu = new_mtu;
136 /*
137 * Stop then re-open the interface. This will allocate RX skb's with
138 * the new MTU.
139 * There is a possible danger that the open will not successed, due
140 * to memory is full, which might fail the open function.
141 */
142 if (netif_running(dev)) {
143 if (mv643xx_eth_real_stop(dev))
144 printk(KERN_ERR
145 "%s: Fatal error on stopping device\n",
146 dev->name);
147 if (mv643xx_eth_real_open(dev))
148 printk(KERN_ERR
149 "%s: Fatal error on opening device\n",
150 dev->name);
151 }
152
1da177e4
LT		 153 return 0;
154}
155
156/*
157 * mv643xx_eth_rx_task
158 *
159 * Fills / refills RX queue on a certain gigabit ethernet port
160 *
161 * Input : pointer to ethernet interface network device structure
162 * Output : N/A
163 */
164static void mv643xx_eth_rx_task(void *data)
165{
166 struct net_device *dev = (struct net_device *)data;
167 struct mv643xx_private *mp = netdev_priv(dev);
168 struct pkt_info pkt_info;
169 struct sk_buff *skb;
b44cd572 170 int unaligned;
1da177e4
LT		 171
172 if (test_and_set_bit(0, &mp->rx_task_busy))
173 panic("%s: Error in test_set_bit / clear_bit", dev->name);
174
175 while (mp->rx_ring_skbs < (mp->rx_ring_size - 5)) {
b44cd572 176 skb = dev_alloc_skb(RX_SKB_SIZE + DMA_ALIGN);
1da177e4
LT		 177 if (!skb)
178 break;
179 mp->rx_ring_skbs++;
b44cd572
DF		 180 unaligned = (u32)skb->data & (DMA_ALIGN - 1);
181 if (unaligned)
182 skb_reserve(skb, DMA_ALIGN - unaligned);
1da177e4
LT		 183 pkt_info.cmd_sts = ETH_RX_ENABLE_INTERRUPT;
184 pkt_info.byte_cnt = RX_SKB_SIZE;
185 pkt_info.buf_ptr = dma_map_single(NULL, skb->data, RX_SKB_SIZE,
186 DMA_FROM_DEVICE);
187 pkt_info.return_info = skb;
188 if (eth_rx_return_buff(mp, &pkt_info) != ETH_OK) {
189 printk(KERN_ERR
190 "%s: Error allocating RX Ring\n", dev->name);
191 break;
192 }
b44cd572 193 skb_reserve(skb, HW_IP_ALIGN);
1da177e4
LT		 194 }
195 clear_bit(0, &mp->rx_task_busy);
196 /*
197 * If RX ring is empty of SKB, set a timer to try allocating
198 * again in a later time .
199 */
200 if ((mp->rx_ring_skbs == 0) && (mp->rx_timer_flag == 0)) {
201 printk(KERN_INFO "%s: Rx ring is empty\n", dev->name);
202 /* After 100mSec */
203 mp->timeout.expires = jiffies + (HZ / 10);
204 add_timer(&mp->timeout);
205 mp->rx_timer_flag = 1;
206 }
207#ifdef MV643XX_RX_QUEUE_FILL_ON_TASK
208 else {
209 /* Return interrupts */
210 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(mp->port_num),
211 INT_CAUSE_UNMASK_ALL);
212 }
213#endif
214}
215
216/*
217 * mv643xx_eth_rx_task_timer_wrapper
218 *
219 * Timer routine to wake up RX queue filling task. This function is
220 * used only in case the RX queue is empty, and all alloc_skb has
221 * failed (due to out of memory event).
222 *
223 * Input : pointer to ethernet interface network device structure
224 * Output : N/A
225 */
226static void mv643xx_eth_rx_task_timer_wrapper(unsigned long data)
227{
228 struct net_device *dev = (struct net_device *)data;
229 struct mv643xx_private *mp = netdev_priv(dev);
230
231 mp->rx_timer_flag = 0;
232 mv643xx_eth_rx_task((void *)data);
233}
234
235/*
236 * mv643xx_eth_update_mac_address
237 *
238 * Update the MAC address of the port in the address table
239 *
240 * Input : pointer to ethernet interface network device structure
241 * Output : N/A
242 */
243static void mv643xx_eth_update_mac_address(struct net_device *dev)
244{
245 struct mv643xx_private *mp = netdev_priv(dev);
246 unsigned int port_num = mp->port_num;
247
248 eth_port_init_mac_tables(port_num);
249 memcpy(mp->port_mac_addr, dev->dev_addr, 6);
250 eth_port_uc_addr_set(port_num, mp->port_mac_addr);
251}
252
253/*
254 * mv643xx_eth_set_rx_mode
255 *
256 * Change from promiscuos to regular rx mode
257 *
258 * Input : pointer to ethernet interface network device structure
259 * Output : N/A
260 */
261static void mv643xx_eth_set_rx_mode(struct net_device *dev)
262{
263 struct mv643xx_private *mp = netdev_priv(dev);
1da177e4 264
1da177e4 265 if (dev->flags & IFF_PROMISC)
7342cd81 266 mp->port_config |= (u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE;
1da177e4 267 else
7342cd81
DF		 268 mp->port_config &= ~(u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE;
269
270 mv_write(MV643XX_ETH_PORT_CONFIG_REG(mp->port_num), mp->port_config);
16e03018
DF		 271
272 eth_port_set_multicast_list(dev);
1da177e4
LT		 273}
274
275/*
276 * mv643xx_eth_set_mac_address
277 *
278 * Change the interface's mac address.
279 * No special hardware thing should be done because interface is always
280 * put in promiscuous mode.
281 *
282 * Input : pointer to ethernet interface network device structure and
283 * a pointer to the designated entry to be added to the cache.
284 * Output : zero upon success, negative upon failure
285 */
286static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
287{
288 int i;
289
290 for (i = 0; i < 6; i++)
291 /* +2 is for the offset of the HW addr type */
292 dev->dev_addr[i] = ((unsigned char *)addr)[i + 2];
293 mv643xx_eth_update_mac_address(dev);
294 return 0;
295}
296
297/*
298 * mv643xx_eth_tx_timeout
299 *
300 * Called upon a timeout on transmitting a packet
301 *
302 * Input : pointer to ethernet interface network device structure.
303 * Output : N/A
304 */
305static void mv643xx_eth_tx_timeout(struct net_device *dev)
306{
307 struct mv643xx_private *mp = netdev_priv(dev);
308
309 printk(KERN_INFO "%s: TX timeout ", dev->name);
310
311 /* Do the reset outside of interrupt context */
312 schedule_work(&mp->tx_timeout_task);
313}
314
315/*
316 * mv643xx_eth_tx_timeout_task
317 *
318 * Actual routine to reset the adapter when a timeout on Tx has occurred
319 */
320static void mv643xx_eth_tx_timeout_task(struct net_device *dev)
321{
322 struct mv643xx_private *mp = netdev_priv(dev);
323
324 netif_device_detach(dev);
325 eth_port_reset(mp->port_num);
326 eth_port_start(mp);
327 netif_device_attach(dev);
328}
329
330/*
331 * mv643xx_eth_free_tx_queue
332 *
333 * Input : dev - a pointer to the required interface
334 *
335 * Output : 0 if was able to release skb , nonzero otherwise
336 */
337static int mv643xx_eth_free_tx_queue(struct net_device *dev,
338 unsigned int eth_int_cause_ext)
339{
340 struct mv643xx_private *mp = netdev_priv(dev);
341 struct net_device_stats *stats = &mp->stats;
342 struct pkt_info pkt_info;
343 int released = 1;
344
345 if (!(eth_int_cause_ext & (BIT0 | BIT8)))
346 return released;
347
1da177e4
LT		 348 /* Check only queue 0 */
349 while (eth_tx_return_desc(mp, &pkt_info) == ETH_OK) {
350 if (pkt_info.cmd_sts & BIT0) {
351 printk("%s: Error in TX\n", dev->name);
352 stats->tx_errors++;
353 }
354
cb415d30
PG		 355 if (pkt_info.cmd_sts & ETH_TX_FIRST_DESC)
356 dma_unmap_single(NULL, pkt_info.buf_ptr,
357 pkt_info.byte_cnt,
358 DMA_TO_DEVICE);
359 else
360 dma_unmap_page(NULL, pkt_info.buf_ptr,
361 pkt_info.byte_cnt,
362 DMA_TO_DEVICE);
1da177e4 363
cb415d30 364 if (pkt_info.return_info) {
1da177e4
LT		 365 dev_kfree_skb_irq(pkt_info.return_info);
366 released = 0;
cb415d30 367 }
1da177e4
LT		 368 }
369
1da177e4
LT		 370 return released;
371}
372
373/*
374 * mv643xx_eth_receive
375 *
376 * This function is forward packets that are received from the port's
377 * queues toward kernel core or FastRoute them to another interface.
378 *
379 * Input : dev - a pointer to the required interface
380 * max - maximum number to receive (0 means unlimted)
381 *
382 * Output : number of served packets
383 */
384#ifdef MV643XX_NAPI
385static int mv643xx_eth_receive_queue(struct net_device *dev, int budget)
386#else
387static int mv643xx_eth_receive_queue(struct net_device *dev)
388#endif
389{
390 struct mv643xx_private *mp = netdev_priv(dev);
391 struct net_device_stats *stats = &mp->stats;
392 unsigned int received_packets = 0;
393 struct sk_buff *skb;
394 struct pkt_info pkt_info;
395
396#ifdef MV643XX_NAPI
b1dd9ca1 397 while (budget-- > 0 && eth_port_receive(mp, &pkt_info) == ETH_OK) {
1da177e4
LT		 398#else
399 while (eth_port_receive(mp, &pkt_info) == ETH_OK) {
400#endif
401 mp->rx_ring_skbs--;
402 received_packets++;
b1dd9ca1 403
1da177e4
LT		 404 /* Update statistics. Note byte count includes 4 byte CRC count */
405 stats->rx_packets++;
406 stats->rx_bytes += pkt_info.byte_cnt;
407 skb = pkt_info.return_info;
408 /*
409 * In case received a packet without first / last bits on OR
410 * the error summary bit is on, the packets needs to be dropeed.
411 */
412 if (((pkt_info.cmd_sts
413 & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
414 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
415 || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
416 stats->rx_dropped++;
417 if ((pkt_info.cmd_sts & (ETH_RX_FIRST_DESC |
418 ETH_RX_LAST_DESC)) !=
419 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) {
420 if (net_ratelimit())
421 printk(KERN_ERR
422 "%s: Received packet spread "
423 "on multiple descriptors\n",
424 dev->name);
425 }
426 if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)
427 stats->rx_errors++;
428
429 dev_kfree_skb_irq(skb);
430 } else {
431 /*
432 * The -4 is for the CRC in the trailer of the
433 * received packet
434 */
435 skb_put(skb, pkt_info.byte_cnt - 4);
436 skb->dev = dev;
437
438 if (pkt_info.cmd_sts & ETH_LAYER_4_CHECKSUM_OK) {
439 skb->ip_summed = CHECKSUM_UNNECESSARY;
440 skb->csum = htons(
441 (pkt_info.cmd_sts & 0x0007fff8) >> 3);
442 }
443 skb->protocol = eth_type_trans(skb, dev);
444#ifdef MV643XX_NAPI
445 netif_receive_skb(skb);
446#else
447 netif_rx(skb);
448#endif
449 }
450 }
451
452 return received_packets;
453}
454
455/*
456 * mv643xx_eth_int_handler
457 *
458 * Main interrupt handler for the gigbit ethernet ports
459 *
460 * Input : irq - irq number (not used)
461 * dev_id - a pointer to the required interface's data structure
462 * regs - not used
463 * Output : N/A
464 */
465
466static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id,
467 struct pt_regs *regs)
468{
469 struct net_device *dev = (struct net_device *)dev_id;
470 struct mv643xx_private *mp = netdev_priv(dev);
471 u32 eth_int_cause, eth_int_cause_ext = 0;
472 unsigned int port_num = mp->port_num;
473
474 /* Read interrupt cause registers */
475 eth_int_cause = mv_read(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num)) &
476 INT_CAUSE_UNMASK_ALL;
477
478 if (eth_int_cause & BIT1)
479 eth_int_cause_ext = mv_read(
480 MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num)) &
481 INT_CAUSE_UNMASK_ALL_EXT;
482
483#ifdef MV643XX_NAPI
484 if (!(eth_int_cause & 0x0007fffd)) {
485 /* Dont ack the Rx interrupt */
486#endif
487 /*
488 * Clear specific ethernet port intrerrupt registers by
489 * acknowleding relevant bits.
490 */
491 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num),
492 ~eth_int_cause);
493 if (eth_int_cause_ext != 0x0)
494 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG
495 (port_num), ~eth_int_cause_ext);
496
497 /* UDP change : We may need this */
498 if ((eth_int_cause_ext & 0x0000ffff) &&
499 (mv643xx_eth_free_tx_queue(dev, eth_int_cause_ext) == 0) &&
500 (mp->tx_ring_size > mp->tx_ring_skbs + MAX_DESCS_PER_SKB))
501 netif_wake_queue(dev);
502#ifdef MV643XX_NAPI
503 } else {
504 if (netif_rx_schedule_prep(dev)) {
505 /* Mask all the interrupts */
506 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), 0);
507 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG
508 (port_num), 0);
8f518703
DF		 509 /* ensure previous writes have taken effect */
510 mv_read(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num));
1da177e4
LT		 511 __netif_rx_schedule(dev);
512 }
513#else
514 if (eth_int_cause & (BIT2 | BIT11))
515 mv643xx_eth_receive_queue(dev, 0);
516
517 /*
518 * After forwarded received packets to upper layer, add a task
519 * in an interrupts enabled context that refills the RX ring
520 * with skb's.
521 */
522#ifdef MV643XX_RX_QUEUE_FILL_ON_TASK
523 /* Unmask all interrupts on ethernet port */
524 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
525 INT_CAUSE_MASK_ALL);
8f518703
DF		 526 /* wait for previous write to take effect */
527 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
528
1da177e4
LT		 529 queue_task(&mp->rx_task, &tq_immediate);
530 mark_bh(IMMEDIATE_BH);
531#else
532 mp->rx_task.func(dev);
533#endif
534#endif
535 }
536 /* PHY status changed */
537 if (eth_int_cause_ext & (BIT16 | BIT20)) {
538 if (eth_port_link_is_up(port_num)) {
539 netif_carrier_on(dev);
540 netif_wake_queue(dev);
541 /* Start TX queue */
542 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG
543 (port_num), 1);
544 } else {
545 netif_carrier_off(dev);
546 netif_stop_queue(dev);
547 }
548 }
549
550 /*
551 * If no real interrupt occured, exit.
552 * This can happen when using gigE interrupt coalescing mechanism.
553 */
554 if ((eth_int_cause == 0x0) && (eth_int_cause_ext == 0x0))
555 return IRQ_NONE;
556
557 return IRQ_HANDLED;
558}
559
560#ifdef MV643XX_COAL
561
562/*
563 * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
564 *
565 * DESCRIPTION:
566 * This routine sets the RX coalescing interrupt mechanism parameter.
567 * This parameter is a timeout counter, that counts in 64 t_clk
568 * chunks ; that when timeout event occurs a maskable interrupt
569 * occurs.
570 * The parameter is calculated using the tClk of the MV-643xx chip
571 * , and the required delay of the interrupt in usec.
572 *
573 * INPUT:
574 * unsigned int eth_port_num Ethernet port number
575 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
576 * unsigned int delay Delay in usec
577 *
578 * OUTPUT:
579 * Interrupt coalescing mechanism value is set in MV-643xx chip.
580 *
581 * RETURN:
582 * The interrupt coalescing value set in the gigE port.
583 *
584 */
585static unsigned int eth_port_set_rx_coal(unsigned int eth_port_num,
586 unsigned int t_clk, unsigned int delay)
587{
588 unsigned int coal = ((t_clk / 1000000) * delay) / 64;
589
590 /* Set RX Coalescing mechanism */
591 mv_write(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num),
592 ((coal & 0x3fff) << 8) |
593 (mv_read(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num))
594 & 0xffc000ff));
595
596 return coal;
597}
598#endif
599
600/*
601 * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
602 *
603 * DESCRIPTION:
604 * This routine sets the TX coalescing interrupt mechanism parameter.
605 * This parameter is a timeout counter, that counts in 64 t_clk
606 * chunks ; that when timeout event occurs a maskable interrupt
607 * occurs.
608 * The parameter is calculated using the t_cLK frequency of the
609 * MV-643xx chip and the required delay in the interrupt in uSec
610 *
611 * INPUT:
612 * unsigned int eth_port_num Ethernet port number
613 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
614 * unsigned int delay Delay in uSeconds
615 *
616 * OUTPUT:
617 * Interrupt coalescing mechanism value is set in MV-643xx chip.
618 *
619 * RETURN:
620 * The interrupt coalescing value set in the gigE port.
621 *
622 */
623static unsigned int eth_port_set_tx_coal(unsigned int eth_port_num,
624 unsigned int t_clk, unsigned int delay)
625{
626 unsigned int coal;
627 coal = ((t_clk / 1000000) * delay) / 64;
628 /* Set TX Coalescing mechanism */
629 mv_write(MV643XX_ETH_TX_FIFO_URGENT_THRESHOLD_REG(eth_port_num),
630 coal << 4);
631 return coal;
632}
633
634/*
635 * mv643xx_eth_open
636 *
637 * This function is called when openning the network device. The function
638 * should initialize all the hardware, initialize cyclic Rx/Tx
639 * descriptors chain and buffers and allocate an IRQ to the network
640 * device.
641 *
642 * Input : a pointer to the network device structure
643 *
644 * Output : zero of success , nonzero if fails.
645 */
646
647static int mv643xx_eth_open(struct net_device *dev)
648{
649 struct mv643xx_private *mp = netdev_priv(dev);
650 unsigned int port_num = mp->port_num;
651 int err;
652
1da177e4 653 err = request_irq(dev->irq, mv643xx_eth_int_handler,
16b81757 654 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
1da177e4
LT		 655 if (err) {
656 printk(KERN_ERR "Can not assign IRQ number to MV643XX_eth%d\n",
657 port_num);
8f518703 658 return -EAGAIN;
1da177e4
LT		 659 }
660
661 if (mv643xx_eth_real_open(dev)) {
662 printk("%s: Error opening interface\n", dev->name);
8f518703 663 free_irq(dev->irq, dev);
1da177e4 664 err = -EBUSY;
1da177e4
LT		 665 }
666
1da177e4
LT		 667 return err;
668}
669
670/*
671 * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
672 *
673 * DESCRIPTION:
674 * This function prepares a Rx chained list of descriptors and packet
675 * buffers in a form of a ring. The routine must be called after port
676 * initialization routine and before port start routine.
677 * The Ethernet SDMA engine uses CPU bus addresses to access the various
678 * devices in the system (i.e. DRAM). This function uses the ethernet
679 * struct 'virtual to physical' routine (set by the user) to set the ring
680 * with physical addresses.
681 *
682 * INPUT:
683 * struct mv643xx_private *mp Ethernet Port Control srtuct.
684 *
685 * OUTPUT:
686 * The routine updates the Ethernet port control struct with information
687 * regarding the Rx descriptors and buffers.
688 *
689 * RETURN:
690 * None.
691 */
692static void ether_init_rx_desc_ring(struct mv643xx_private *mp)
693{
694 volatile struct eth_rx_desc *p_rx_desc;
695 int rx_desc_num = mp->rx_ring_size;
696 int i;
697
698 /* initialize the next_desc_ptr links in the Rx descriptors ring */
699 p_rx_desc = (struct eth_rx_desc *)mp->p_rx_desc_area;
700 for (i = 0; i < rx_desc_num; i++) {
701 p_rx_desc[i].next_desc_ptr = mp->rx_desc_dma +
702 ((i + 1) % rx_desc_num) * sizeof(struct eth_rx_desc);
703 }
704
705 /* Save Rx desc pointer to driver struct. */
706 mp->rx_curr_desc_q = 0;
707 mp->rx_used_desc_q = 0;
708
709 mp->rx_desc_area_size = rx_desc_num * sizeof(struct eth_rx_desc);
710
711 /* Add the queue to the list of RX queues of this port */
712 mp->port_rx_queue_command |= 1;
713}
714
715/*
716 * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
717 *
718 * DESCRIPTION:
719 * This function prepares a Tx chained list of descriptors and packet
720 * buffers in a form of a ring. The routine must be called after port
721 * initialization routine and before port start routine.
722 * The Ethernet SDMA engine uses CPU bus addresses to access the various
723 * devices in the system (i.e. DRAM). This function uses the ethernet
724 * struct 'virtual to physical' routine (set by the user) to set the ring
725 * with physical addresses.
726 *
727 * INPUT:
728 * struct mv643xx_private *mp Ethernet Port Control srtuct.
729 *
730 * OUTPUT:
731 * The routine updates the Ethernet port control struct with information
732 * regarding the Tx descriptors and buffers.
733 *
734 * RETURN:
735 * None.
736 */
737static void ether_init_tx_desc_ring(struct mv643xx_private *mp)
738{
739 int tx_desc_num = mp->tx_ring_size;
740 struct eth_tx_desc *p_tx_desc;
741 int i;
742
743 /* Initialize the next_desc_ptr links in the Tx descriptors ring */
744 p_tx_desc = (struct eth_tx_desc *)mp->p_tx_desc_area;
745 for (i = 0; i < tx_desc_num; i++) {
746 p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma +
747 ((i + 1) % tx_desc_num) * sizeof(struct eth_tx_desc);
748 }
749
750 mp->tx_curr_desc_q = 0;
751 mp->tx_used_desc_q = 0;
752#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
753 mp->tx_first_desc_q = 0;
754#endif
755
756 mp->tx_desc_area_size = tx_desc_num * sizeof(struct eth_tx_desc);
757
758 /* Add the queue to the list of Tx queues of this port */
759 mp->port_tx_queue_command |= 1;
760}
761
762/* Helper function for mv643xx_eth_open */
763static int mv643xx_eth_real_open(struct net_device *dev)
764{
765 struct mv643xx_private *mp = netdev_priv(dev);
766 unsigned int port_num = mp->port_num;
767 unsigned int size;
768
769 /* Stop RX Queues */
770 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), 0x0000ff00);
771
1da177e4
LT		 772 /* Set the MAC Address */
773 memcpy(mp->port_mac_addr, dev->dev_addr, 6);
774
775 eth_port_init(mp);
776
777 INIT_WORK(&mp->rx_task, (void (*)(void *))mv643xx_eth_rx_task, dev);
778
779 memset(&mp->timeout, 0, sizeof(struct timer_list));
780 mp->timeout.function = mv643xx_eth_rx_task_timer_wrapper;
781 mp->timeout.data = (unsigned long)dev;
782
783 mp->rx_task_busy = 0;
784 mp->rx_timer_flag = 0;
785
786 /* Allocate RX and TX skb rings */
787 mp->rx_skb = kmalloc(sizeof(*mp->rx_skb) * mp->rx_ring_size,
788 GFP_KERNEL);
789 if (!mp->rx_skb) {
790 printk(KERN_ERR "%s: Cannot allocate Rx skb ring\n", dev->name);
791 return -ENOMEM;
792 }
793 mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size,
794 GFP_KERNEL);
795 if (!mp->tx_skb) {
796 printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name);
797 kfree(mp->rx_skb);
798 return -ENOMEM;
799 }
800
801 /* Allocate TX ring */
802 mp->tx_ring_skbs = 0;
803 size = mp->tx_ring_size * sizeof(struct eth_tx_desc);
804 mp->tx_desc_area_size = size;
805
806 if (mp->tx_sram_size) {
807 mp->p_tx_desc_area = ioremap(mp->tx_sram_addr,
808 mp->tx_sram_size);
809 mp->tx_desc_dma = mp->tx_sram_addr;
810 } else
811 mp->p_tx_desc_area = dma_alloc_coherent(NULL, size,
812 &mp->tx_desc_dma,
813 GFP_KERNEL);
814
815 if (!mp->p_tx_desc_area) {
816 printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n",
817 dev->name, size);
818 kfree(mp->rx_skb);
819 kfree(mp->tx_skb);
820 return -ENOMEM;
821 }
822 BUG_ON((u32) mp->p_tx_desc_area & 0xf); /* check 16-byte alignment */
823 memset((void *)mp->p_tx_desc_area, 0, mp->tx_desc_area_size);
824
825 ether_init_tx_desc_ring(mp);
826
827 /* Allocate RX ring */
828 mp->rx_ring_skbs = 0;
829 size = mp->rx_ring_size * sizeof(struct eth_rx_desc);
830 mp->rx_desc_area_size = size;
831
832 if (mp->rx_sram_size) {
833 mp->p_rx_desc_area = ioremap(mp->rx_sram_addr,
834 mp->rx_sram_size);
835 mp->rx_desc_dma = mp->rx_sram_addr;
836 } else
837 mp->p_rx_desc_area = dma_alloc_coherent(NULL, size,
838 &mp->rx_desc_dma,
839 GFP_KERNEL);
840
841 if (!mp->p_rx_desc_area) {
842 printk(KERN_ERR "%s: Cannot allocate Rx ring (size %d bytes)\n",
843 dev->name, size);
844 printk(KERN_ERR "%s: Freeing previously allocated TX queues...",
845 dev->name);
846 if (mp->rx_sram_size)
dd09b1de 847 iounmap(mp->p_tx_desc_area);
1da177e4
LT		 848 else
849 dma_free_coherent(NULL, mp->tx_desc_area_size,
850 mp->p_tx_desc_area, mp->tx_desc_dma);
851 kfree(mp->rx_skb);
852 kfree(mp->tx_skb);
853 return -ENOMEM;
854 }
855 memset((void *)mp->p_rx_desc_area, 0, size);
856
857 ether_init_rx_desc_ring(mp);
858
859 mv643xx_eth_rx_task(dev); /* Fill RX ring with skb's */
860
861 eth_port_start(mp);
862
863 /* Interrupt Coalescing */
864
865#ifdef MV643XX_COAL
866 mp->rx_int_coal =
867 eth_port_set_rx_coal(port_num, 133000000, MV643XX_RX_COAL);
868#endif
869
870 mp->tx_int_coal =
871 eth_port_set_tx_coal(port_num, 133000000, MV643XX_TX_COAL);
872
8f518703
DF		 873 /* Clear any pending ethernet port interrupts */
874 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
875 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
876
877 /* Unmask phy and link status changes interrupts */
878 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
879 INT_CAUSE_UNMASK_ALL_EXT);
1da177e4 880
8f518703
DF		 881 /* Unmask RX buffer and TX end interrupt */
882 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
883 INT_CAUSE_UNMASK_ALL);
1da177e4
LT		 884 return 0;
885}
886
887static void mv643xx_eth_free_tx_rings(struct net_device *dev)
888{
889 struct mv643xx_private *mp = netdev_priv(dev);
890 unsigned int port_num = mp->port_num;
891 unsigned int curr;
4476e0e4 892 struct sk_buff *skb;
1da177e4
LT		 893
894 /* Stop Tx Queues */
895 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num), 0x0000ff00);
896
897 /* Free outstanding skb's on TX rings */
898 for (curr = 0; mp->tx_ring_skbs && curr < mp->tx_ring_size; curr++) {
4476e0e4
DF		 899 skb = mp->tx_skb[curr];
900 if (skb) {
901 mp->tx_ring_skbs -= skb_shinfo(skb)->nr_frags;
902 dev_kfree_skb(skb);
1da177e4
LT		 903 mp->tx_ring_skbs--;
904 }
905 }
906 if (mp->tx_ring_skbs)
907 printk("%s: Error on Tx descriptor free - could not free %d"
908 " descriptors\n", dev->name, mp->tx_ring_skbs);
909
910 /* Free TX ring */
911 if (mp->tx_sram_size)
912 iounmap(mp->p_tx_desc_area);
913 else
914 dma_free_coherent(NULL, mp->tx_desc_area_size,
915 mp->p_tx_desc_area, mp->tx_desc_dma);
916}
917
918static void mv643xx_eth_free_rx_rings(struct net_device *dev)
919{
920 struct mv643xx_private *mp = netdev_priv(dev);
921 unsigned int port_num = mp->port_num;
922 int curr;
923
924 /* Stop RX Queues */
925 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), 0x0000ff00);
926
927 /* Free preallocated skb's on RX rings */
928 for (curr = 0; mp->rx_ring_skbs && curr < mp->rx_ring_size; curr++) {
929 if (mp->rx_skb[curr]) {
930 dev_kfree_skb(mp->rx_skb[curr]);
931 mp->rx_ring_skbs--;
932 }
933 }
934
935 if (mp->rx_ring_skbs)
936 printk(KERN_ERR
937 "%s: Error in freeing Rx Ring. %d skb's still"
938 " stuck in RX Ring - ignoring them\n", dev->name,
939 mp->rx_ring_skbs);
940 /* Free RX ring */
941 if (mp->rx_sram_size)
942 iounmap(mp->p_rx_desc_area);
943 else
944 dma_free_coherent(NULL, mp->rx_desc_area_size,
945 mp->p_rx_desc_area, mp->rx_desc_dma);
946}
947
948/*
949 * mv643xx_eth_stop
950 *
951 * This function is used when closing the network device.
952 * It updates the hardware,
953 * release all memory that holds buffers and descriptors and release the IRQ.
954 * Input : a pointer to the device structure
955 * Output : zero if success , nonzero if fails
956 */
957
958/* Helper function for mv643xx_eth_stop */
959
960static int mv643xx_eth_real_stop(struct net_device *dev)
961{
962 struct mv643xx_private *mp = netdev_priv(dev);
963 unsigned int port_num = mp->port_num;
964
8f518703
DF		 965 /* Mask RX buffer and TX end interrupt */
966 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), 0);
967
968 /* Mask phy and link status changes interrupts */
969 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num), 0);
970
971 /* ensure previous writes have taken effect */
972 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
973
974#ifdef MV643XX_NAPI
975 netif_poll_disable(dev);
976#endif
1da177e4
LT		 977 netif_carrier_off(dev);
978 netif_stop_queue(dev);
979
1da177e4
LT		 980 eth_port_reset(mp->port_num);
981
8f518703
DF		 982 mv643xx_eth_free_tx_rings(dev);
983 mv643xx_eth_free_rx_rings(dev);
1da177e4 984
8f518703
DF		 985#ifdef MV643XX_NAPI
986 netif_poll_enable(dev);
987#endif
1da177e4
LT		 988
989 return 0;
990}
991
992static int mv643xx_eth_stop(struct net_device *dev)
993{
1da177e4
LT		 994 mv643xx_eth_real_stop(dev);
995
996 free_irq(dev->irq, dev);
1da177e4
LT		 997
998 return 0;
999}
1000
1001#ifdef MV643XX_NAPI
1002static void mv643xx_tx(struct net_device *dev)
1003{
1004 struct mv643xx_private *mp = netdev_priv(dev);
1005 struct pkt_info pkt_info;
1006
1007 while (eth_tx_return_desc(mp, &pkt_info) == ETH_OK) {
cb415d30
PG		 1008 if (pkt_info.cmd_sts & ETH_TX_FIRST_DESC)
1009 dma_unmap_single(NULL, pkt_info.buf_ptr,
1010 pkt_info.byte_cnt,
1011 DMA_TO_DEVICE);
1012 else
1013 dma_unmap_page(NULL, pkt_info.buf_ptr,
1014 pkt_info.byte_cnt,
1015 DMA_TO_DEVICE);
1da177e4 1016
cb415d30 1017 if (pkt_info.return_info)
1da177e4 1018 dev_kfree_skb_irq(pkt_info.return_info);
1da177e4
LT		 1019 }
1020
1021 if (netif_queue_stopped(dev) &&
1022 mp->tx_ring_size > mp->tx_ring_skbs + MAX_DESCS_PER_SKB)
1023 netif_wake_queue(dev);
1024}
1025
1026/*
1027 * mv643xx_poll
1028 *
1029 * This function is used in case of NAPI
1030 */
1031static int mv643xx_poll(struct net_device *dev, int *budget)
1032{
1033 struct mv643xx_private *mp = netdev_priv(dev);
1034 int done = 1, orig_budget, work_done;
1035 unsigned int port_num = mp->port_num;
1da177e4
LT		 1036
1037#ifdef MV643XX_TX_FAST_REFILL
1038 if (++mp->tx_clean_threshold > 5) {
1da177e4
LT		 1039 mv643xx_tx(dev);
1040 mp->tx_clean_threshold = 0;
1da177e4
LT		 1041 }
1042#endif
1043
1044 if ((mv_read(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num)))
1045 != (u32) mp->rx_used_desc_q) {
1046 orig_budget = *budget;
1047 if (orig_budget > dev->quota)
1048 orig_budget = dev->quota;
1049 work_done = mv643xx_eth_receive_queue(dev, orig_budget);
1050 mp->rx_task.func(dev);
1051 *budget -= work_done;
1052 dev->quota -= work_done;
1053 if (work_done >= orig_budget)
1054 done = 0;
1055 }
1056
1057 if (done) {
8f518703 1058 netif_rx_complete(dev);
1da177e4
LT		 1059 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
1060 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
1061 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
1062 INT_CAUSE_UNMASK_ALL);
1063 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
1064 INT_CAUSE_UNMASK_ALL_EXT);
1da177e4
LT		 1065 }
1066
1067 return done ? 0 : 1;
1068}
1069#endif
1070
f7ea3337
PJ		 1071/* Hardware can't handle unaligned fragments smaller than 9 bytes.
1072 * This helper function detects that case.
1073 */
1074
1075static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1076{
1077 unsigned int frag;
1078 skb_frag_t *fragp;
1079
1080 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1081 fragp = &skb_shinfo(skb)->frags[frag];
1082 if (fragp->size <= 8 && fragp->page_offset & 0x7)
1083 return 1;
1084
1085 }
1086 return 0;
1087}
1088
1089
1da177e4
LT		 1090/*
1091 * mv643xx_eth_start_xmit
1092 *
1093 * This function is queues a packet in the Tx descriptor for
1094 * required port.
1095 *
1096 * Input : skb - a pointer to socket buffer
1097 * dev - a pointer to the required port
1098 *
1099 * Output : zero upon success
1100 */
1101static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
1102{
1103 struct mv643xx_private *mp = netdev_priv(dev);
1104 struct net_device_stats *stats = &mp->stats;
1105 ETH_FUNC_RET_STATUS status;
1106 unsigned long flags;
1107 struct pkt_info pkt_info;
1108
1109 if (netif_queue_stopped(dev)) {
1110 printk(KERN_ERR
1111 "%s: Tried sending packet when interface is stopped\n",
1112 dev->name);
1113 return 1;
1114 }
1115
1116 /* This is a hard error, log it. */
1117 if ((mp->tx_ring_size - mp->tx_ring_skbs) <=
1118 (skb_shinfo(skb)->nr_frags + 1)) {
1119 netif_stop_queue(dev);
1120 printk(KERN_ERR
1121 "%s: Bug in mv643xx_eth - Trying to transmit when"
1122 " queue full !\n", dev->name);
1123 return 1;
1124 }
1125
1126 /* Paranoid check - this shouldn't happen */
1127 if (skb == NULL) {
1128 stats->tx_dropped++;
1129 printk(KERN_ERR "mv64320_eth paranoid check failed\n");
1130 return 1;
1131 }
1132
f7ea3337
PJ		 1133#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1134 if (has_tiny_unaligned_frags(skb)) {
1135 if ((skb_linearize(skb, GFP_ATOMIC) != 0)) {
1136 stats->tx_dropped++;
1137 printk(KERN_DEBUG "%s: failed to linearize tiny "
1138 "unaligned fragment\n", dev->name);
1139 return 1;
1140 }
1141 }
1142
1da177e4
LT		 1143 spin_lock_irqsave(&mp->lock, flags);
1144
1da177e4 1145 if (!skb_shinfo(skb)->nr_frags) {
1da177e4 1146 if (skb->ip_summed != CHECKSUM_HW) {
26006360 1147 /* Errata BTS #50, IHL must be 5 if no HW checksum */
1da177e4 1148 pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT |
26006360
DF		 1149 ETH_TX_FIRST_DESC |
1150 ETH_TX_LAST_DESC |
1151 5 << ETH_TX_IHL_SHIFT;
1da177e4
LT		 1152 pkt_info.l4i_chk = 0;
1153 } else {
1da177e4 1154 pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT |
26006360
DF		 1155 ETH_TX_FIRST_DESC |
1156 ETH_TX_LAST_DESC |
1157 ETH_GEN_TCP_UDP_CHECKSUM |
1158 ETH_GEN_IP_V_4_CHECKSUM |
1159 skb->nh.iph->ihl << ETH_TX_IHL_SHIFT;
1da177e4 1160 /* CPU already calculated pseudo header checksum. */
63890576
WJ		 1161 if ((skb->protocol == ETH_P_IP) &&
1162 (skb->nh.iph->protocol == IPPROTO_UDP) ) {
1da177e4
LT		 1163 pkt_info.cmd_sts |= ETH_UDP_FRAME;
1164 pkt_info.l4i_chk = skb->h.uh->check;
63890576
WJ		 1165 } else if ((skb->protocol == ETH_P_IP) &&
1166 (skb->nh.iph->protocol == IPPROTO_TCP))
1da177e4
LT		 1167 pkt_info.l4i_chk = skb->h.th->check;
1168 else {
1169 printk(KERN_ERR
63890576 1170 "%s: chksum proto != IPv4 TCP or UDP\n",
1da177e4
LT		 1171 dev->name);
1172 spin_unlock_irqrestore(&mp->lock, flags);
1173 return 1;
1174 }
1175 }
1176 pkt_info.byte_cnt = skb->len;
1177 pkt_info.buf_ptr = dma_map_single(NULL, skb->data, skb->len,
1178 DMA_TO_DEVICE);
1179 pkt_info.return_info = skb;
1da177e4
LT		 1180 status = eth_port_send(mp, &pkt_info);
1181 if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL))
1182 printk(KERN_ERR "%s: Error on transmitting packet\n",
1183 dev->name);
1184 stats->tx_bytes += pkt_info.byte_cnt;
1185 } else {
1186 unsigned int frag;
1da177e4 1187
1da177e4
LT		 1188 /* first frag which is skb header */
1189 pkt_info.byte_cnt = skb_headlen(skb);
1190 pkt_info.buf_ptr = dma_map_single(NULL, skb->data,
1191 skb_headlen(skb),
1192 DMA_TO_DEVICE);
1193 pkt_info.l4i_chk = 0;
1194 pkt_info.return_info = 0;
1da177e4 1195
26006360
DF		 1196 if (skb->ip_summed != CHECKSUM_HW)
1197 /* Errata BTS #50, IHL must be 5 if no HW checksum */
1198 pkt_info.cmd_sts = ETH_TX_FIRST_DESC |
1199 5 << ETH_TX_IHL_SHIFT;
1200 else {
1201 pkt_info.cmd_sts = ETH_TX_FIRST_DESC |
1202 ETH_GEN_TCP_UDP_CHECKSUM |
1203 ETH_GEN_IP_V_4_CHECKSUM |
1204 skb->nh.iph->ihl << ETH_TX_IHL_SHIFT;
1da177e4 1205 /* CPU already calculated pseudo header checksum. */
63890576
WJ		 1206 if ((skb->protocol == ETH_P_IP) &&
1207 (skb->nh.iph->protocol == IPPROTO_UDP)) {
1da177e4
LT		 1208 pkt_info.cmd_sts |= ETH_UDP_FRAME;
1209 pkt_info.l4i_chk = skb->h.uh->check;
63890576
WJ		 1210 } else if ((skb->protocol == ETH_P_IP) &&
1211 (skb->nh.iph->protocol == IPPROTO_TCP))
1da177e4
LT		 1212 pkt_info.l4i_chk = skb->h.th->check;
1213 else {
1214 printk(KERN_ERR
63890576 1215 "%s: chksum proto != IPv4 TCP or UDP\n",
1da177e4
LT		 1216 dev->name);
1217 spin_unlock_irqrestore(&mp->lock, flags);
1218 return 1;
1219 }
1220 }
1221
1222 status = eth_port_send(mp, &pkt_info);
1223 if (status != ETH_OK) {
1224 if ((status == ETH_ERROR))
1225 printk(KERN_ERR
1226 "%s: Error on transmitting packet\n",
1227 dev->name);
1228 if (status == ETH_QUEUE_FULL)
1229 printk("Error on Queue Full \n");
1230 if (status == ETH_QUEUE_LAST_RESOURCE)
1231 printk("Tx resource error \n");
1232 }
1233 stats->tx_bytes += pkt_info.byte_cnt;
1234
1235 /* Check for the remaining frags */
1236 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1237 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
1238 pkt_info.l4i_chk = 0x0000;
1239 pkt_info.cmd_sts = 0x00000000;
1240
1241 /* Last Frag enables interrupt and frees the skb */
1242 if (frag == (skb_shinfo(skb)->nr_frags - 1)) {
1243 pkt_info.cmd_sts |= ETH_TX_ENABLE_INTERRUPT |
1244 ETH_TX_LAST_DESC;
1245 pkt_info.return_info = skb;
1da177e4
LT		 1246 } else {
1247 pkt_info.return_info = 0;
1248 }
1249 pkt_info.l4i_chk = 0;
1250 pkt_info.byte_cnt = this_frag->size;
1251
1252 pkt_info.buf_ptr = dma_map_page(NULL, this_frag->page,
1253 this_frag->page_offset,
1254 this_frag->size,
1255 DMA_TO_DEVICE);
1256
1257 status = eth_port_send(mp, &pkt_info);
1258
1259 if (status != ETH_OK) {
1260 if ((status == ETH_ERROR))
1261 printk(KERN_ERR "%s: Error on "
1262 "transmitting packet\n",
1263 dev->name);
1264
1265 if (status == ETH_QUEUE_LAST_RESOURCE)
1266 printk("Tx resource error \n");
1267
1268 if (status == ETH_QUEUE_FULL)
1269 printk("Queue is full \n");
1270 }
1271 stats->tx_bytes += pkt_info.byte_cnt;
1272 }
1273 }
1274#else
f7ea3337
PJ		 1275 spin_lock_irqsave(&mp->lock, flags);
1276
1da177e4
LT		 1277 pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT | ETH_TX_FIRST_DESC |
1278 ETH_TX_LAST_DESC;
1279 pkt_info.l4i_chk = 0;
1280 pkt_info.byte_cnt = skb->len;
1281 pkt_info.buf_ptr = dma_map_single(NULL, skb->data, skb->len,
1282 DMA_TO_DEVICE);
1283 pkt_info.return_info = skb;
1da177e4
LT		 1284 status = eth_port_send(mp, &pkt_info);
1285 if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL))
1286 printk(KERN_ERR "%s: Error on transmitting packet\n",
1287 dev->name);
1288 stats->tx_bytes += pkt_info.byte_cnt;
1289#endif
1290
1291 /* Check if TX queue can handle another skb. If not, then
1292 * signal higher layers to stop requesting TX
1293 */
1294 if (mp->tx_ring_size <= (mp->tx_ring_skbs + MAX_DESCS_PER_SKB))
1295 /*
1296 * Stop getting skb's from upper layers.
1297 * Getting skb's from upper layers will be enabled again after
1298 * packets are released.
1299 */
1300 netif_stop_queue(dev);
1301
1302 /* Update statistics and start of transmittion time */
1303 stats->tx_packets++;
1304 dev->trans_start = jiffies;
1305
1306 spin_unlock_irqrestore(&mp->lock, flags);
1307
1308 return 0; /* success */
1309}
1310
1311/*
1312 * mv643xx_eth_get_stats
1313 *
1314 * Returns a pointer to the interface statistics.
1315 *
1316 * Input : dev - a pointer to the required interface
1317 *
1318 * Output : a pointer to the interface's statistics
1319 */
1320
1321static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1322{
1323 struct mv643xx_private *mp = netdev_priv(dev);
1324
1325 return &mp->stats;
1326}
1327
63c9e549
DF		 1328#ifdef CONFIG_NET_POLL_CONTROLLER
1329static inline void mv643xx_enable_irq(struct mv643xx_private *mp)
1330{
1331 int port_num = mp->port_num;
1332 unsigned long flags;
1333
1334 spin_lock_irqsave(&mp->lock, flags);
1335 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
1336 INT_CAUSE_UNMASK_ALL);
1337 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
1338 INT_CAUSE_UNMASK_ALL_EXT);
1339 spin_unlock_irqrestore(&mp->lock, flags);
1340}
1341
1342static inline void mv643xx_disable_irq(struct mv643xx_private *mp)
1343{
1344 int port_num = mp->port_num;
1345 unsigned long flags;
1346
1347 spin_lock_irqsave(&mp->lock, flags);
1348 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
1349 INT_CAUSE_MASK_ALL);
1350 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
1351 INT_CAUSE_MASK_ALL_EXT);
1352 spin_unlock_irqrestore(&mp->lock, flags);
1353}
1354
1355static void mv643xx_netpoll(struct net_device *netdev)
1356{
1357 struct mv643xx_private *mp = netdev_priv(netdev);
1358
1359 mv643xx_disable_irq(mp);
1360 mv643xx_eth_int_handler(netdev->irq, netdev, NULL);
1361 mv643xx_enable_irq(mp);
1362}
1363#endif
1364
1da177e4
LT		 1365/*/
1366 * mv643xx_eth_probe
1367 *
1368 * First function called after registering the network device.
1369 * It's purpose is to initialize the device as an ethernet device,
1370 * fill the ethernet device structure with pointers * to functions,
1371 * and set the MAC address of the interface
1372 *
1373 * Input : struct device *
1374 * Output : -ENOMEM if failed , 0 if success
1375 */
3ae5eaec 1376static int mv643xx_eth_probe(struct platform_device *pdev)
1da177e4 1377{
1da177e4
LT		 1378 struct mv643xx_eth_platform_data *pd;
1379 int port_num = pdev->id;
1380 struct mv643xx_private *mp;
1381 struct net_device *dev;
1382 u8 *p;
1383 struct resource *res;
1384 int err;
1385
1386 dev = alloc_etherdev(sizeof(struct mv643xx_private));
1387 if (!dev)
1388 return -ENOMEM;
1389
3ae5eaec 1390 platform_set_drvdata(pdev, dev);
1da177e4
LT		 1391
1392 mp = netdev_priv(dev);
1393
1394 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1395 BUG_ON(!res);
1396 dev->irq = res->start;
1397
1398 mp->port_num = port_num;
1399
1400 dev->open = mv643xx_eth_open;
1401 dev->stop = mv643xx_eth_stop;
1402 dev->hard_start_xmit = mv643xx_eth_start_xmit;
1403 dev->get_stats = mv643xx_eth_get_stats;
1404 dev->set_mac_address = mv643xx_eth_set_mac_address;
1405 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
1406
1407 /* No need to Tx Timeout */
1408 dev->tx_timeout = mv643xx_eth_tx_timeout;
1409#ifdef MV643XX_NAPI
1410 dev->poll = mv643xx_poll;
1411 dev->weight = 64;
1412#endif
1413
63c9e549
DF		 1414#ifdef CONFIG_NET_POLL_CONTROLLER
1415 dev->poll_controller = mv643xx_netpoll;
1416#endif
1417
1da177e4
LT		 1418 dev->watchdog_timeo = 2 * HZ;
1419 dev->tx_queue_len = mp->tx_ring_size;
1420 dev->base_addr = 0;
1421 dev->change_mtu = mv643xx_eth_change_mtu;
1422 SET_ETHTOOL_OPS(dev, &mv643xx_ethtool_ops);
1423
1424#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1425#ifdef MAX_SKB_FRAGS
1426 /*
1427 * Zero copy can only work if we use Discovery II memory. Else, we will
1428 * have to map the buffers to ISA memory which is only 16 MB
1429 */
63890576 1430 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
1da177e4
LT		 1431#endif
1432#endif
1433
1434 /* Configure the timeout task */
1435 INIT_WORK(&mp->tx_timeout_task,
1436 (void (*)(void *))mv643xx_eth_tx_timeout_task, dev);
1437
1438 spin_lock_init(&mp->lock);
1439
1440 /* set default config values */
1441 eth_port_uc_addr_get(dev, dev->dev_addr);
1442 mp->port_config = MV643XX_ETH_PORT_CONFIG_DEFAULT_VALUE;
1443 mp->port_config_extend = MV643XX_ETH_PORT_CONFIG_EXTEND_DEFAULT_VALUE;
1444 mp->port_sdma_config = MV643XX_ETH_PORT_SDMA_CONFIG_DEFAULT_VALUE;
1445 mp->port_serial_control = MV643XX_ETH_PORT_SERIAL_CONTROL_DEFAULT_VALUE;
1446 mp->rx_ring_size = MV643XX_ETH_PORT_DEFAULT_RECEIVE_QUEUE_SIZE;
1447 mp->tx_ring_size = MV643XX_ETH_PORT_DEFAULT_TRANSMIT_QUEUE_SIZE;
1448
1449 pd = pdev->dev.platform_data;
1450 if (pd) {
1451 if (pd->mac_addr != NULL)
1452 memcpy(dev->dev_addr, pd->mac_addr, 6);
1453
1454 if (pd->phy_addr || pd->force_phy_addr)
1455 ethernet_phy_set(port_num, pd->phy_addr);
1456
1457 if (pd->port_config || pd->force_port_config)
1458 mp->port_config = pd->port_config;
1459
1460 if (pd->port_config_extend || pd->force_port_config_extend)
1461 mp->port_config_extend = pd->port_config_extend;
1462
1463 if (pd->port_sdma_config || pd->force_port_sdma_config)
1464 mp->port_sdma_config = pd->port_sdma_config;
1465
1466 if (pd->port_serial_control || pd->force_port_serial_control)
1467 mp->port_serial_control = pd->port_serial_control;
1468
1469 if (pd->rx_queue_size)
1470 mp->rx_ring_size = pd->rx_queue_size;
1471
1472 if (pd->tx_queue_size)
1473 mp->tx_ring_size = pd->tx_queue_size;
1474
1475 if (pd->tx_sram_size) {
1476 mp->tx_sram_size = pd->tx_sram_size;
1477 mp->tx_sram_addr = pd->tx_sram_addr;
1478 }
1479
1480 if (pd->rx_sram_size) {
1481 mp->rx_sram_size = pd->rx_sram_size;
1482 mp->rx_sram_addr = pd->rx_sram_addr;
1483 }
1484 }
1485
1486 err = ethernet_phy_detect(port_num);
1487 if (err) {
1488 pr_debug("MV643xx ethernet port %d: "
1489 "No PHY detected at addr %d\n",
1490 port_num, ethernet_phy_get(port_num));
1491 return err;
1492 }
1493
1494 err = register_netdev(dev);
1495 if (err)
1496 goto out;
1497
1498 p = dev->dev_addr;
1499 printk(KERN_NOTICE
1500 "%s: port %d with MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
1501 dev->name, port_num, p[0], p[1], p[2], p[3], p[4], p[5]);
1502
1503 if (dev->features & NETIF_F_SG)
1504 printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name);
1505
1506 if (dev->features & NETIF_F_IP_CSUM)
1507 printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n",
1508 dev->name);
1509
1510#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1511 printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name);
1512#endif
1513
1514#ifdef MV643XX_COAL
1515 printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n",
1516 dev->name);
1517#endif
1518
1519#ifdef MV643XX_NAPI
1520 printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name);
1521#endif
1522
b1529871
ND		 1523 if (mp->tx_sram_size > 0)
1524 printk(KERN_NOTICE "%s: Using SRAM\n", dev->name);
1525
1da177e4
LT		 1526 return 0;
1527
1528out:
1529 free_netdev(dev);
1530
1531 return err;
1532}
1533
3ae5eaec 1534static int mv643xx_eth_remove(struct platform_device *pdev)
1da177e4 1535{
3ae5eaec 1536 struct net_device *dev = platform_get_drvdata(pdev);
1da177e4
LT		 1537
1538 unregister_netdev(dev);
1539 flush_scheduled_work();
1540
1541 free_netdev(dev);
3ae5eaec 1542 platform_set_drvdata(pdev, NULL);
1da177e4
LT		 1543 return 0;
1544}
1545
3ae5eaec 1546static int mv643xx_eth_shared_probe(struct platform_device *pdev)
1da177e4 1547{
1da177e4
LT		 1548 struct resource *res;
1549
1550 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
1551
1552 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1553 if (res == NULL)
1554 return -ENODEV;
1555
1556 mv643xx_eth_shared_base = ioremap(res->start,
1557 MV643XX_ETH_SHARED_REGS_SIZE);
1558 if (mv643xx_eth_shared_base == NULL)
1559 return -ENOMEM;
1560
1561 return 0;
1562
1563}
1564
3ae5eaec 1565static int mv643xx_eth_shared_remove(struct platform_device *pdev)
1da177e4
LT		 1566{
1567 iounmap(mv643xx_eth_shared_base);
1568 mv643xx_eth_shared_base = NULL;
1569
1570 return 0;
1571}
1572
3ae5eaec 1573static struct platform_driver mv643xx_eth_driver = {
1da177e4
LT		 1574 .probe = mv643xx_eth_probe,
1575 .remove = mv643xx_eth_remove,
3ae5eaec
RK		 1576 .driver = {
1577 .name = MV643XX_ETH_NAME,
1578 },
1da177e4
LT		 1579};
1580
3ae5eaec 1581static struct platform_driver mv643xx_eth_shared_driver = {
1da177e4
LT		 1582 .probe = mv643xx_eth_shared_probe,
1583 .remove = mv643xx_eth_shared_remove,
3ae5eaec
RK		 1584 .driver = {
1585 .name = MV643XX_ETH_SHARED_NAME,
1586 },
1da177e4
LT		 1587};
1588
1589/*
1590 * mv643xx_init_module
1591 *
1592 * Registers the network drivers into the Linux kernel
1593 *
1594 * Input : N/A
1595 *
1596 * Output : N/A
1597 */
1598static int __init mv643xx_init_module(void)
1599{
1600 int rc;
1601
3ae5eaec 1602 rc = platform_driver_register(&mv643xx_eth_shared_driver);
1da177e4 1603 if (!rc) {
3ae5eaec 1604 rc = platform_driver_register(&mv643xx_eth_driver);
1da177e4 1605 if (rc)
3ae5eaec 1606 platform_driver_unregister(&mv643xx_eth_shared_driver);
1da177e4
LT		 1607 }
1608 return rc;
1609}
1610
1611/*
1612 * mv643xx_cleanup_module
1613 *
1614 * Registers the network drivers into the Linux kernel
1615 *
1616 * Input : N/A
1617 *
1618 * Output : N/A
1619 */
1620static void __exit mv643xx_cleanup_module(void)
1621{
3ae5eaec
RK		 1622 platform_driver_unregister(&mv643xx_eth_driver);
1623 platform_driver_unregister(&mv643xx_eth_shared_driver);
1da177e4
LT		 1624}
1625
1626module_init(mv643xx_init_module);
1627module_exit(mv643xx_cleanup_module);
1628
1629MODULE_LICENSE("GPL");
1630MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani"
1631 " and Dale Farnsworth");
1632MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
1633
1634/*
1635 * The second part is the low level driver of the gigE ethernet ports.
1636 */
1637
1638/*
1639 * Marvell's Gigabit Ethernet controller low level driver
1640 *
1641 * DESCRIPTION:
1642 * This file introduce low level API to Marvell's Gigabit Ethernet
1643 * controller. This Gigabit Ethernet Controller driver API controls
1644 * 1) Operations (i.e. port init, start, reset etc').
1645 * 2) Data flow (i.e. port send, receive etc').
1646 * Each Gigabit Ethernet port is controlled via
1647 * struct mv643xx_private.
1648 * This struct includes user configuration information as well as
1649 * driver internal data needed for its operations.
1650 *
1651 * Supported Features:
1652 * - This low level driver is OS independent. Allocating memory for
1653 * the descriptor rings and buffers are not within the scope of
1654 * this driver.
1655 * - The user is free from Rx/Tx queue managing.
1656 * - This low level driver introduce functionality API that enable
1657 * the to operate Marvell's Gigabit Ethernet Controller in a
1658 * convenient way.
1659 * - Simple Gigabit Ethernet port operation API.
1660 * - Simple Gigabit Ethernet port data flow API.
1661 * - Data flow and operation API support per queue functionality.
1662 * - Support cached descriptors for better performance.
1663 * - Enable access to all four DRAM banks and internal SRAM memory
1664 * spaces.
1665 * - PHY access and control API.
1666 * - Port control register configuration API.
1667 * - Full control over Unicast and Multicast MAC configurations.
1668 *
1669 * Operation flow:
1670 *
1671 * Initialization phase
1672 * This phase complete the initialization of the the
1673 * mv643xx_private struct.
1674 * User information regarding port configuration has to be set
1675 * prior to calling the port initialization routine.
1676 *
1677 * In this phase any port Tx/Rx activity is halted, MIB counters
1678 * are cleared, PHY address is set according to user parameter and
1679 * access to DRAM and internal SRAM memory spaces.
1680 *
1681 * Driver ring initialization
1682 * Allocating memory for the descriptor rings and buffers is not
1683 * within the scope of this driver. Thus, the user is required to
1684 * allocate memory for the descriptors ring and buffers. Those
1685 * memory parameters are used by the Rx and Tx ring initialization
1686 * routines in order to curve the descriptor linked list in a form
1687 * of a ring.
1688 * Note: Pay special attention to alignment issues when using
1689 * cached descriptors/buffers. In this phase the driver store
1690 * information in the mv643xx_private struct regarding each queue
1691 * ring.
1692 *
1693 * Driver start
1694 * This phase prepares the Ethernet port for Rx and Tx activity.
1695 * It uses the information stored in the mv643xx_private struct to
1696 * initialize the various port registers.
1697 *
1698 * Data flow:
1699 * All packet references to/from the driver are done using
1700 * struct pkt_info.
1701 * This struct is a unified struct used with Rx and Tx operations.
1702 * This way the user is not required to be familiar with neither
1703 * Tx nor Rx descriptors structures.
1704 * The driver's descriptors rings are management by indexes.
1705 * Those indexes controls the ring resources and used to indicate
1706 * a SW resource error:
1707 * 'current'
1708 * This index points to the current available resource for use. For
1709 * example in Rx process this index will point to the descriptor
1710 * that will be passed to the user upon calling the receive
1711 * routine. In Tx process, this index will point to the descriptor
1712 * that will be assigned with the user packet info and transmitted.
1713 * 'used'
1714 * This index points to the descriptor that need to restore its
1715 * resources. For example in Rx process, using the Rx buffer return
1716 * API will attach the buffer returned in packet info to the
1717 * descriptor pointed by 'used'. In Tx process, using the Tx
1718 * descriptor return will merely return the user packet info with
1719 * the command status of the transmitted buffer pointed by the
1720 * 'used' index. Nevertheless, it is essential to use this routine
1721 * to update the 'used' index.
1722 * 'first'
1723 * This index supports Tx Scatter-Gather. It points to the first
1724 * descriptor of a packet assembled of multiple buffers. For
1725 * example when in middle of Such packet we have a Tx resource
1726 * error the 'curr' index get the value of 'first' to indicate
1727 * that the ring returned to its state before trying to transmit
1728 * this packet.
1729 *
1730 * Receive operation:
1731 * The eth_port_receive API set the packet information struct,
1732 * passed by the caller, with received information from the
1733 * 'current' SDMA descriptor.
1734 * It is the user responsibility to return this resource back
1735 * to the Rx descriptor ring to enable the reuse of this source.
1736 * Return Rx resource is done using the eth_rx_return_buff API.
1737 *
1738 * Transmit operation:
1739 * The eth_port_send API supports Scatter-Gather which enables to
1740 * send a packet spanned over multiple buffers. This means that
1741 * for each packet info structure given by the user and put into
1742 * the Tx descriptors ring, will be transmitted only if the 'LAST'
1743 * bit will be set in the packet info command status field. This
1744 * API also consider restriction regarding buffer alignments and
1745 * sizes.
1746 * The user must return a Tx resource after ensuring the buffer
1747 * has been transmitted to enable the Tx ring indexes to update.
1748 *
1749 * BOARD LAYOUT
1750 * This device is on-board. No jumper diagram is necessary.
1751 *
1752 * EXTERNAL INTERFACE
1753 *
1754 * Prior to calling the initialization routine eth_port_init() the user
1755 * must set the following fields under mv643xx_private struct:
1756 * port_num User Ethernet port number.
1757 * port_mac_addr[6] User defined port MAC address.
1758 * port_config User port configuration value.
1759 * port_config_extend User port config extend value.
1760 * port_sdma_config User port SDMA config value.
1761 * port_serial_control User port serial control value.
1762 *
1763 * This driver data flow is done using the struct pkt_info which
1764 * is a unified struct for Rx and Tx operations:
1765 *
1766 * byte_cnt Tx/Rx descriptor buffer byte count.
1767 * l4i_chk CPU provided TCP Checksum. For Tx operation
1768 * only.
1769 * cmd_sts Tx/Rx descriptor command status.
1770 * buf_ptr Tx/Rx descriptor buffer pointer.
1771 * return_info Tx/Rx user resource return information.
1772 */
1773
1774/* defines */
1775/* SDMA command macros */
1776#define ETH_ENABLE_TX_QUEUE(eth_port) \
1777 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), 1)
1778
1779/* locals */
1780
1781/* PHY routines */
1782static int ethernet_phy_get(unsigned int eth_port_num);
1783static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
1784
1785/* Ethernet Port routines */
1786static int eth_port_uc_addr(unsigned int eth_port_num, unsigned char uc_nibble,
1787 int option);
1788
1789/*
1790 * eth_port_init - Initialize the Ethernet port driver
1791 *
1792 * DESCRIPTION:
1793 * This function prepares the ethernet port to start its activity:
1794 * 1) Completes the ethernet port driver struct initialization toward port
1795 * start routine.
1796 * 2) Resets the device to a quiescent state in case of warm reboot.
1797 * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
1798 * 4) Clean MAC tables. The reset status of those tables is unknown.
1799 * 5) Set PHY address.
1800 * Note: Call this routine prior to eth_port_start routine and after
1801 * setting user values in the user fields of Ethernet port control
1802 * struct.
1803 *
1804 * INPUT:
1805 * struct mv643xx_private *mp Ethernet port control struct
1806 *
1807 * OUTPUT:
1808 * See description.
1809 *
1810 * RETURN:
1811 * None.
1812 */
1813static void eth_port_init(struct mv643xx_private *mp)
1814{
1815 mp->port_rx_queue_command = 0;
1816 mp->port_tx_queue_command = 0;
1817
1818 mp->rx_resource_err = 0;
1819 mp->tx_resource_err = 0;
1820
1821 eth_port_reset(mp->port_num);
1822
1823 eth_port_init_mac_tables(mp->port_num);
1824
1825 ethernet_phy_reset(mp->port_num);
1826}
1827
1828/*
1829 * eth_port_start - Start the Ethernet port activity.
1830 *
1831 * DESCRIPTION:
1832 * This routine prepares the Ethernet port for Rx and Tx activity:
1833 * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
1834 * has been initialized a descriptor's ring (using
1835 * ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx)
1836 * 2. Initialize and enable the Ethernet configuration port by writing to
1837 * the port's configuration and command registers.
1838 * 3. Initialize and enable the SDMA by writing to the SDMA's
1839 * configuration and command registers. After completing these steps,
1840 * the ethernet port SDMA can starts to perform Rx and Tx activities.
1841 *
1842 * Note: Each Rx and Tx queue descriptor's list must be initialized prior
1843 * to calling this function (use ether_init_tx_desc_ring for Tx queues
1844 * and ether_init_rx_desc_ring for Rx queues).
1845 *
1846 * INPUT:
1847 * struct mv643xx_private *mp Ethernet port control struct
1848 *
1849 * OUTPUT:
1850 * Ethernet port is ready to receive and transmit.
1851 *
1852 * RETURN:
1853 * None.
1854 */
1855static void eth_port_start(struct mv643xx_private *mp)
1856{
1857 unsigned int port_num = mp->port_num;
1858 int tx_curr_desc, rx_curr_desc;
1859
1860 /* Assignment of Tx CTRP of given queue */
1861 tx_curr_desc = mp->tx_curr_desc_q;
1862 mv_write(MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port_num),
1863 (u32)((struct eth_tx_desc *)mp->tx_desc_dma + tx_curr_desc));
1864
1865 /* Assignment of Rx CRDP of given queue */
1866 rx_curr_desc = mp->rx_curr_desc_q;
1867 mv_write(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num),
1868 (u32)((struct eth_rx_desc *)mp->rx_desc_dma + rx_curr_desc));
1869
1870 /* Add the assigned Ethernet address to the port's address table */
1871 eth_port_uc_addr_set(port_num, mp->port_mac_addr);
1872
1873 /* Assign port configuration and command. */
1874 mv_write(MV643XX_ETH_PORT_CONFIG_REG(port_num), mp->port_config);
1875
1876 mv_write(MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port_num),
1877 mp->port_config_extend);
1878
1879
1880 /* Increase the Rx side buffer size if supporting GigE */
1881 if (mp->port_serial_control & MV643XX_ETH_SET_GMII_SPEED_TO_1000)
1882 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
1883 (mp->port_serial_control & 0xfff1ffff) | (0x5 << 17));
1884 else
1885 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
1886 mp->port_serial_control);
1887
1888 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
1889 mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num)) |
1890 MV643XX_ETH_SERIAL_PORT_ENABLE);
1891
1892 /* Assign port SDMA configuration */
1893 mv_write(MV643XX_ETH_SDMA_CONFIG_REG(port_num),
1894 mp->port_sdma_config);
1895
1896 /* Enable port Rx. */
1897 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num),
1898 mp->port_rx_queue_command);
8f543718
DF		 1899
1900 /* Disable port bandwidth limits by clearing MTU register */
1901 mv_write(MV643XX_ETH_MAXIMUM_TRANSMIT_UNIT(port_num), 0);
1da177e4
LT		 1902}
1903
1904/*
1905 * eth_port_uc_addr_set - This function Set the port Unicast address.
1906 *
1907 * DESCRIPTION:
1908 * This function Set the port Ethernet MAC address.
1909 *
1910 * INPUT:
1911 * unsigned int eth_port_num Port number.
1912 * char * p_addr Address to be set
1913 *
1914 * OUTPUT:
1915 * Set MAC address low and high registers. also calls eth_port_uc_addr()
1916 * To set the unicast table with the proper information.
1917 *
1918 * RETURN:
1919 * N/A.
1920 *
1921 */
1922static void eth_port_uc_addr_set(unsigned int eth_port_num,
1923 unsigned char *p_addr)
1924{
1925 unsigned int mac_h;
1926 unsigned int mac_l;
1927
1928 mac_l = (p_addr[4] << 8) | (p_addr[5]);
1929 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
1930 (p_addr[3] << 0);
1931
1932 mv_write(MV643XX_ETH_MAC_ADDR_LOW(eth_port_num), mac_l);
1933 mv_write(MV643XX_ETH_MAC_ADDR_HIGH(eth_port_num), mac_h);
1934
1935 /* Accept frames of this address */
1936 eth_port_uc_addr(eth_port_num, p_addr[5], ACCEPT_MAC_ADDR);
1937
1938 return;
1939}
1940
1941/*
1942 * eth_port_uc_addr_get - This function retrieves the port Unicast address
1943 * (MAC address) from the ethernet hw registers.
1944 *
1945 * DESCRIPTION:
1946 * This function retrieves the port Ethernet MAC address.
1947 *
1948 * INPUT:
1949 * unsigned int eth_port_num Port number.
1950 * char *MacAddr pointer where the MAC address is stored
1951 *
1952 * OUTPUT:
1953 * Copy the MAC address to the location pointed to by MacAddr
1954 *
1955 * RETURN:
1956 * N/A.
1957 *
1958 */
1959static void eth_port_uc_addr_get(struct net_device *dev, unsigned char *p_addr)
1960{
1961 struct mv643xx_private *mp = netdev_priv(dev);
1962 unsigned int mac_h;
1963 unsigned int mac_l;
1964
1965 mac_h = mv_read(MV643XX_ETH_MAC_ADDR_HIGH(mp->port_num));
1966 mac_l = mv_read(MV643XX_ETH_MAC_ADDR_LOW(mp->port_num));
1967
1968 p_addr[0] = (mac_h >> 24) & 0xff;
1969 p_addr[1] = (mac_h >> 16) & 0xff;
1970 p_addr[2] = (mac_h >> 8) & 0xff;
1971 p_addr[3] = mac_h & 0xff;
1972 p_addr[4] = (mac_l >> 8) & 0xff;
1973 p_addr[5] = mac_l & 0xff;
1974}
1975
1976/*
1977 * eth_port_uc_addr - This function Set the port unicast address table
1978 *
1979 * DESCRIPTION:
1980 * This function locates the proper entry in the Unicast table for the
1981 * specified MAC nibble and sets its properties according to function
1982 * parameters.
1983 *
1984 * INPUT:
1985 * unsigned int eth_port_num Port number.
1986 * unsigned char uc_nibble Unicast MAC Address last nibble.
1987 * int option 0 = Add, 1 = remove address.
1988 *
1989 * OUTPUT:
1990 * This function add/removes MAC addresses from the port unicast address
1991 * table.
1992 *
1993 * RETURN:
1994 * true is output succeeded.
1995 * false if option parameter is invalid.
1996 *
1997 */
1998static int eth_port_uc_addr(unsigned int eth_port_num, unsigned char uc_nibble,
1999 int option)
2000{
2001 unsigned int unicast_reg;
2002 unsigned int tbl_offset;
2003 unsigned int reg_offset;
2004
2005 /* Locate the Unicast table entry */
2006 uc_nibble = (0xf & uc_nibble);
2007 tbl_offset = (uc_nibble / 4) * 4; /* Register offset from unicast table base */
2008 reg_offset = uc_nibble % 4; /* Entry offset within the above register */
2009
2010 switch (option) {
2011 case REJECT_MAC_ADDR:
2012 /* Clear accepts frame bit at given unicast DA table entry */
2013 unicast_reg = mv_read((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2014 (eth_port_num) + tbl_offset));
2015
2016 unicast_reg &= (0x0E << (8 * reg_offset));
2017
2018 mv_write((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2019 (eth_port_num) + tbl_offset), unicast_reg);
2020 break;
2021
2022 case ACCEPT_MAC_ADDR:
2023 /* Set accepts frame bit at unicast DA filter table entry */
2024 unicast_reg =
2025 mv_read((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2026 (eth_port_num) + tbl_offset));
2027
2028 unicast_reg |= (0x01 << (8 * reg_offset));
2029
2030 mv_write((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2031 (eth_port_num) + tbl_offset), unicast_reg);
2032
2033 break;
2034
2035 default:
2036 return 0;
2037 }
2038
2039 return 1;
2040}
2041
16e03018
DF		 2042/*
2043 * The entries in each table are indexed by a hash of a packet's MAC
2044 * address. One bit in each entry determines whether the packet is
2045 * accepted. There are 4 entries (each 8 bits wide) in each register
2046 * of the table. The bits in each entry are defined as follows:
2047 * 0 Accept=1, Drop=0
2048 * 3-1 Queue (ETH_Q0=0)
2049 * 7-4 Reserved = 0;
2050 */
2051static void eth_port_set_filter_table_entry(int table, unsigned char entry)
2052{
2053 unsigned int table_reg;
2054 unsigned int tbl_offset;
2055 unsigned int reg_offset;
2056
2057 tbl_offset = (entry / 4) * 4; /* Register offset of DA table entry */
2058 reg_offset = entry % 4; /* Entry offset within the register */
2059
2060 /* Set "accepts frame bit" at specified table entry */
2061 table_reg = mv_read(table + tbl_offset);
2062 table_reg |= 0x01 << (8 * reg_offset);
2063 mv_write(table + tbl_offset, table_reg);
2064}
2065
2066/*
2067 * eth_port_mc_addr - Multicast address settings.
2068 *
2069 * The MV device supports multicast using two tables:
2070 * 1) Special Multicast Table for MAC addresses of the form
2071 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_FF).
2072 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
2073 * Table entries in the DA-Filter table.
2074 * 2) Other Multicast Table for multicast of another type. A CRC-8bit
2075 * is used as an index to the Other Multicast Table entries in the
2076 * DA-Filter table. This function calculates the CRC-8bit value.
2077 * In either case, eth_port_set_filter_table_entry() is then called
2078 * to set to set the actual table entry.
2079 */
2080static void eth_port_mc_addr(unsigned int eth_port_num, unsigned char *p_addr)
2081{
2082 unsigned int mac_h;
2083 unsigned int mac_l;
2084 unsigned char crc_result = 0;
2085 int table;
2086 int mac_array[48];
2087 int crc[8];
2088 int i;
2089
2090 if ((p_addr[0] == 0x01) && (p_addr[1] == 0x00) &&
2091 (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) {
2092 table = MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2093 (eth_port_num);
2094 eth_port_set_filter_table_entry(table, p_addr[5]);
2095 return;
2096 }
2097
2098 /* Calculate CRC-8 out of the given address */
2099 mac_h = (p_addr[0] << 8) | (p_addr[1]);
2100 mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
2101 (p_addr[4] << 8) | (p_addr[5] << 0);
2102
2103 for (i = 0; i < 32; i++)
2104 mac_array[i] = (mac_l >> i) & 0x1;
2105 for (i = 32; i < 48; i++)
2106 mac_array[i] = (mac_h >> (i - 32)) & 0x1;
2107
2108 crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ mac_array[39] ^
2109 mac_array[35] ^ mac_array[34] ^ mac_array[31] ^ mac_array[30] ^
2110 mac_array[28] ^ mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
2111 mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ mac_array[12] ^
2112 mac_array[8] ^ mac_array[7] ^ mac_array[6] ^ mac_array[0];
2113
2114 crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
2115 mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ mac_array[34] ^
2116 mac_array[32] ^ mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
2117 mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ mac_array[21] ^
2118 mac_array[20] ^ mac_array[18] ^ mac_array[17] ^ mac_array[16] ^
2119 mac_array[15] ^ mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
2120 mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ mac_array[0];
2121
2122 crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ mac_array[43] ^
2123 mac_array[42] ^ mac_array[39] ^ mac_array[37] ^ mac_array[34] ^
2124 mac_array[33] ^ mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
2125 mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ mac_array[15] ^
2126 mac_array[13] ^ mac_array[12] ^ mac_array[10] ^ mac_array[8] ^
2127 mac_array[6] ^ mac_array[2] ^ mac_array[1] ^ mac_array[0];
2128
2129 crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
2130 mac_array[40] ^ mac_array[38] ^ mac_array[35] ^ mac_array[34] ^
2131 mac_array[30] ^ mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
2132 mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
2133 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[7] ^
2134 mac_array[3] ^ mac_array[2] ^ mac_array[1];
2135
2136 crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[41] ^
2137 mac_array[39] ^ mac_array[36] ^ mac_array[35] ^ mac_array[31] ^
2138 mac_array[30] ^ mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
2139 mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ mac_array[14] ^
2140 mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ mac_array[4] ^
2141 mac_array[3] ^ mac_array[2];
2142
2143 crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ mac_array[42] ^
2144 mac_array[40] ^ mac_array[37] ^ mac_array[36] ^ mac_array[32] ^
2145 mac_array[31] ^ mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
2146 mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ mac_array[15] ^
2147 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[5] ^
2148 mac_array[4] ^ mac_array[3];
2149
2150 crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ mac_array[41] ^
2151 mac_array[38] ^ mac_array[37] ^ mac_array[33] ^ mac_array[32] ^
2152 mac_array[29] ^ mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
2153 mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ mac_array[14] ^
2154 mac_array[12] ^ mac_array[10] ^ mac_array[6] ^ mac_array[5] ^
2155 mac_array[4];
2156
2157 crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ mac_array[39] ^
2158 mac_array[38] ^ mac_array[34] ^ mac_array[33] ^ mac_array[30] ^
2159 mac_array[29] ^ mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
2160 mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ mac_array[13] ^
2161 mac_array[11] ^ mac_array[7] ^ mac_array[6] ^ mac_array[5];
2162
2163 for (i = 0; i < 8; i++)
2164 crc_result = crc_result | (crc[i] << i);
2165
2166 table = MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num);
2167 eth_port_set_filter_table_entry(table, crc_result);
2168}
2169
2170/*
2171 * Set the entire multicast list based on dev->mc_list.
2172 */
2173static void eth_port_set_multicast_list(struct net_device *dev)
2174{
2175
2176 struct dev_mc_list *mc_list;
2177 int i;
2178 int table_index;
2179 struct mv643xx_private *mp = netdev_priv(dev);
2180 unsigned int eth_port_num = mp->port_num;
2181
2182 /* If the device is in promiscuous mode or in all multicast mode,
2183 * we will fully populate both multicast tables with accept.
2184 * This is guaranteed to yield a match on all multicast addresses...
2185 */
2186 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) {
2187 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2188 /* Set all entries in DA filter special multicast
2189 * table (Ex_dFSMT)
2190 * Set for ETH_Q0 for now
2191 * Bits
2192 * 0 Accept=1, Drop=0
2193 * 3-1 Queue ETH_Q0=0
2194 * 7-4 Reserved = 0;
2195 */
2196 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
2197
2198 /* Set all entries in DA filter other multicast
2199 * table (Ex_dFOMT)
2200 * Set for ETH_Q0 for now
2201 * Bits
2202 * 0 Accept=1, Drop=0
2203 * 3-1 Queue ETH_Q0=0
2204 * 7-4 Reserved = 0;
2205 */
2206 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
2207 }
2208 return;
2209 }
2210
2211 /* We will clear out multicast tables every time we get the list.
2212 * Then add the entire new list...
2213 */
2214 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2215 /* Clear DA filter special multicast table (Ex_dFSMT) */
2216 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2217 (eth_port_num) + table_index, 0);
2218
2219 /* Clear DA filter other multicast table (Ex_dFOMT) */
2220 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2221 (eth_port_num) + table_index, 0);
2222 }
2223
2224 /* Get pointer to net_device multicast list and add each one... */
2225 for (i = 0, mc_list = dev->mc_list;
2226 (i < 256) && (mc_list != NULL) && (i < dev->mc_count);
2227 i++, mc_list = mc_list->next)
2228 if (mc_list->dmi_addrlen == 6)
2229 eth_port_mc_addr(eth_port_num, mc_list->dmi_addr);
2230}
2231
1da177e4
LT		 2232/*
2233 * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
2234 *
2235 * DESCRIPTION:
2236 * Go through all the DA filter tables (Unicast, Special Multicast &
2237 * Other Multicast) and set each entry to 0.
2238 *
2239 * INPUT:
2240 * unsigned int eth_port_num Ethernet Port number.
2241 *
2242 * OUTPUT:
2243 * Multicast and Unicast packets are rejected.
2244 *
2245 * RETURN:
2246 * None.
2247 */
2248static void eth_port_init_mac_tables(unsigned int eth_port_num)
2249{
2250 int table_index;
2251
2252 /* Clear DA filter unicast table (Ex_dFUT) */
2253 for (table_index = 0; table_index <= 0xC; table_index += 4)
2254 mv_write((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2255 (eth_port_num) + table_index), 0);
2256
2257 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2258 /* Clear DA filter special multicast table (Ex_dFSMT) */
16e03018
DF		 2259 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2260 (eth_port_num) + table_index, 0);
1da177e4 2261 /* Clear DA filter other multicast table (Ex_dFOMT) */
16e03018
DF		 2262 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2263 (eth_port_num) + table_index, 0);
1da177e4
LT		 2264 }
2265}
2266
2267/*
2268 * eth_clear_mib_counters - Clear all MIB counters
2269 *
2270 * DESCRIPTION:
2271 * This function clears all MIB counters of a specific ethernet port.
2272 * A read from the MIB counter will reset the counter.
2273 *
2274 * INPUT:
2275 * unsigned int eth_port_num Ethernet Port number.
2276 *
2277 * OUTPUT:
2278 * After reading all MIB counters, the counters resets.
2279 *
2280 * RETURN:
2281 * MIB counter value.
2282 *
2283 */
2284static void eth_clear_mib_counters(unsigned int eth_port_num)
2285{
2286 int i;
2287
2288 /* Perform dummy reads from MIB counters */
2289 for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
2290 i += 4)
2291 mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(eth_port_num) + i);
2292}
2293
2294static inline u32 read_mib(struct mv643xx_private *mp, int offset)
2295{
2296 return mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(mp->port_num) + offset);
2297}
2298
2299static void eth_update_mib_counters(struct mv643xx_private *mp)
2300{
2301 struct mv643xx_mib_counters *p = &mp->mib_counters;
2302 int offset;
2303
2304 p->good_octets_received +=
2305 read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
2306 p->good_octets_received +=
2307 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32;
2308
2309 for (offset = ETH_MIB_BAD_OCTETS_RECEIVED;
2310 offset <= ETH_MIB_FRAMES_1024_TO_MAX_OCTETS;
2311 offset += 4)
2312 *(u32 *)((char *)p + offset) = read_mib(mp, offset);
2313
2314 p->good_octets_sent += read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_LOW);
2315 p->good_octets_sent +=
2316 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_HIGH) << 32;
2317
2318 for (offset = ETH_MIB_GOOD_FRAMES_SENT;
2319 offset <= ETH_MIB_LATE_COLLISION;
2320 offset += 4)
2321 *(u32 *)((char *)p + offset) = read_mib(mp, offset);
2322}
2323
2324/*
2325 * ethernet_phy_detect - Detect whether a phy is present
2326 *
2327 * DESCRIPTION:
2328 * This function tests whether there is a PHY present on
2329 * the specified port.
2330 *
2331 * INPUT:
2332 * unsigned int eth_port_num Ethernet Port number.
2333 *
2334 * OUTPUT:
2335 * None
2336 *
2337 * RETURN:
2338 * 0 on success
2339 * -ENODEV on failure
2340 *
2341 */
2342static int ethernet_phy_detect(unsigned int port_num)
2343{
2344 unsigned int phy_reg_data0;
2345 int auto_neg;
2346
2347 eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
2348 auto_neg = phy_reg_data0 & 0x1000;
2349 phy_reg_data0 ^= 0x1000; /* invert auto_neg */
2350 eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
2351
2352 eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
2353 if ((phy_reg_data0 & 0x1000) == auto_neg)
2354 return -ENODEV; /* change didn't take */
2355
2356 phy_reg_data0 ^= 0x1000;
2357 eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
2358 return 0;
2359}
2360
2361/*
2362 * ethernet_phy_get - Get the ethernet port PHY address.
2363 *
2364 * DESCRIPTION:
2365 * This routine returns the given ethernet port PHY address.
2366 *
2367 * INPUT:
2368 * unsigned int eth_port_num Ethernet Port number.
2369 *
2370 * OUTPUT:
2371 * None.
2372 *
2373 * RETURN:
2374 * PHY address.
2375 *
2376 */
2377static int ethernet_phy_get(unsigned int eth_port_num)
2378{
2379 unsigned int reg_data;
2380
2381 reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG);
2382
2383 return ((reg_data >> (5 * eth_port_num)) & 0x1f);
2384}
2385
2386/*
2387 * ethernet_phy_set - Set the ethernet port PHY address.
2388 *
2389 * DESCRIPTION:
2390 * This routine sets the given ethernet port PHY address.
2391 *
2392 * INPUT:
2393 * unsigned int eth_port_num Ethernet Port number.
2394 * int phy_addr PHY address.
2395 *
2396 * OUTPUT:
2397 * None.
2398 *
2399 * RETURN:
2400 * None.
2401 *
2402 */
2403static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr)
2404{
2405 u32 reg_data;
2406 int addr_shift = 5 * eth_port_num;
2407
2408 reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG);
2409 reg_data &= ~(0x1f << addr_shift);
2410 reg_data |= (phy_addr & 0x1f) << addr_shift;
2411 mv_write(MV643XX_ETH_PHY_ADDR_REG, reg_data);
2412}
2413
2414/*
2415 * ethernet_phy_reset - Reset Ethernet port PHY.
2416 *
2417 * DESCRIPTION:
2418 * This routine utilizes the SMI interface to reset the ethernet port PHY.
2419 *
2420 * INPUT:
2421 * unsigned int eth_port_num Ethernet Port number.
2422 *
2423 * OUTPUT:
2424 * The PHY is reset.
2425 *
2426 * RETURN:
2427 * None.
2428 *
2429 */
2430static void ethernet_phy_reset(unsigned int eth_port_num)
2431{
2432 unsigned int phy_reg_data;
2433
2434 /* Reset the PHY */
2435 eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data);
2436 phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
2437 eth_port_write_smi_reg(eth_port_num, 0, phy_reg_data);
2438}
2439
2440/*
2441 * eth_port_reset - Reset Ethernet port
2442 *
2443 * DESCRIPTION:
2444 * This routine resets the chip by aborting any SDMA engine activity and
2445 * clearing the MIB counters. The Receiver and the Transmit unit are in
2446 * idle state after this command is performed and the port is disabled.
2447 *
2448 * INPUT:
2449 * unsigned int eth_port_num Ethernet Port number.
2450 *
2451 * OUTPUT:
2452 * Channel activity is halted.
2453 *
2454 * RETURN:
2455 * None.
2456 *
2457 */
2458static void eth_port_reset(unsigned int port_num)
2459{
2460 unsigned int reg_data;
2461
2462 /* Stop Tx port activity. Check port Tx activity. */
2463 reg_data = mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num));
2464
2465 if (reg_data & 0xFF) {
2466 /* Issue stop command for active channels only */
2467 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num),
2468 (reg_data << 8));
2469
2470 /* Wait for all Tx activity to terminate. */
2471 /* Check port cause register that all Tx queues are stopped */
2472 while (mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num))
2473 & 0xFF)
2474 udelay(10);
2475 }
2476
2477 /* Stop Rx port activity. Check port Rx activity. */
2478 reg_data = mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num));
2479
2480 if (reg_data & 0xFF) {
2481 /* Issue stop command for active channels only */
2482 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num),
2483 (reg_data << 8));
2484
2485 /* Wait for all Rx activity to terminate. */
2486 /* Check port cause register that all Rx queues are stopped */
2487 while (mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num))
2488 & 0xFF)
2489 udelay(10);
2490 }
2491
2492 /* Clear all MIB counters */
2493 eth_clear_mib_counters(port_num);
2494
2495 /* Reset the Enable bit in the Configuration Register */
2496 reg_data = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
2497 reg_data &= ~MV643XX_ETH_SERIAL_PORT_ENABLE;
2498 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), reg_data);
2499}
2500
1da177e4
LT		 2501
2502static int eth_port_autoneg_supported(unsigned int eth_port_num)
2503{
2504 unsigned int phy_reg_data0;
2505
2506 eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data0);
2507
2508 return phy_reg_data0 & 0x1000;
2509}
2510
2511static int eth_port_link_is_up(unsigned int eth_port_num)
2512{
2513 unsigned int phy_reg_data1;
2514
2515 eth_port_read_smi_reg(eth_port_num, 1, &phy_reg_data1);
2516
2517 if (eth_port_autoneg_supported(eth_port_num)) {
2518 if (phy_reg_data1 & 0x20) /* auto-neg complete */
2519 return 1;
2520 } else if (phy_reg_data1 & 0x4) /* link up */
2521 return 1;
2522
2523 return 0;
2524}
2525
1da177e4
LT		 2526/*
2527 * eth_port_read_smi_reg - Read PHY registers
2528 *
2529 * DESCRIPTION:
2530 * This routine utilize the SMI interface to interact with the PHY in
2531 * order to perform PHY register read.
2532 *
2533 * INPUT:
2534 * unsigned int port_num Ethernet Port number.
2535 * unsigned int phy_reg PHY register address offset.
2536 * unsigned int *value Register value buffer.
2537 *
2538 * OUTPUT:
2539 * Write the value of a specified PHY register into given buffer.
2540 *
2541 * RETURN:
2542 * false if the PHY is busy or read data is not in valid state.
2543 * true otherwise.
2544 *
2545 */
2546static void eth_port_read_smi_reg(unsigned int port_num,
2547 unsigned int phy_reg, unsigned int *value)
2548{
2549 int phy_addr = ethernet_phy_get(port_num);
2550 unsigned long flags;
2551 int i;
2552
2553 /* the SMI register is a shared resource */
2554 spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
2555
2556 /* wait for the SMI register to become available */
2557 for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) {
2558 if (i == PHY_WAIT_ITERATIONS) {
2559 printk("mv643xx PHY busy timeout, port %d\n", port_num);
2560 goto out;
2561 }
2562 udelay(PHY_WAIT_MICRO_SECONDS);
2563 }
2564
2565 mv_write(MV643XX_ETH_SMI_REG,
2566 (phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ);
2567
2568 /* now wait for the data to be valid */
2569 for (i = 0; !(mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_READ_VALID); i++) {
2570 if (i == PHY_WAIT_ITERATIONS) {
2571 printk("mv643xx PHY read timeout, port %d\n", port_num);
2572 goto out;
2573 }
2574 udelay(PHY_WAIT_MICRO_SECONDS);
2575 }
2576
2577 *value = mv_read(MV643XX_ETH_SMI_REG) & 0xffff;
2578out:
2579 spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
2580}
2581
2582/*
2583 * eth_port_write_smi_reg - Write to PHY registers
2584 *
2585 * DESCRIPTION:
2586 * This routine utilize the SMI interface to interact with the PHY in
2587 * order to perform writes to PHY registers.
2588 *
2589 * INPUT:
2590 * unsigned int eth_port_num Ethernet Port number.
2591 * unsigned int phy_reg PHY register address offset.
2592 * unsigned int value Register value.
2593 *
2594 * OUTPUT:
2595 * Write the given value to the specified PHY register.
2596 *
2597 * RETURN:
2598 * false if the PHY is busy.
2599 * true otherwise.
2600 *
2601 */
2602static void eth_port_write_smi_reg(unsigned int eth_port_num,
2603 unsigned int phy_reg, unsigned int value)
2604{
2605 int phy_addr;
2606 int i;
2607 unsigned long flags;
2608
2609 phy_addr = ethernet_phy_get(eth_port_num);
2610
2611 /* the SMI register is a shared resource */
2612 spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
2613
2614 /* wait for the SMI register to become available */
2615 for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) {
2616 if (i == PHY_WAIT_ITERATIONS) {
2617 printk("mv643xx PHY busy timeout, port %d\n",
2618 eth_port_num);
2619 goto out;
2620 }
2621 udelay(PHY_WAIT_MICRO_SECONDS);
2622 }
2623
2624 mv_write(MV643XX_ETH_SMI_REG, (phy_addr << 16) | (phy_reg << 21) |
2625 ETH_SMI_OPCODE_WRITE | (value & 0xffff));
2626out:
2627 spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
2628}
2629
2630/*
2631 * eth_port_send - Send an Ethernet packet
2632 *
2633 * DESCRIPTION:
2634 * This routine send a given packet described by p_pktinfo parameter. It
2635 * supports transmitting of a packet spaned over multiple buffers. The
2636 * routine updates 'curr' and 'first' indexes according to the packet
2637 * segment passed to the routine. In case the packet segment is first,
2638 * the 'first' index is update. In any case, the 'curr' index is updated.
2639 * If the routine get into Tx resource error it assigns 'curr' index as
2640 * 'first'. This way the function can abort Tx process of multiple
2641 * descriptors per packet.
2642 *
2643 * INPUT:
2644 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2645 * struct pkt_info *p_pkt_info User packet buffer.
2646 *
2647 * OUTPUT:
2648 * Tx ring 'curr' and 'first' indexes are updated.
2649 *
2650 * RETURN:
2651 * ETH_QUEUE_FULL in case of Tx resource error.
2652 * ETH_ERROR in case the routine can not access Tx desc ring.
2653 * ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource.
2654 * ETH_OK otherwise.
2655 *
2656 */
2657#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
2658/*
2659 * Modified to include the first descriptor pointer in case of SG
2660 */
2661static ETH_FUNC_RET_STATUS eth_port_send(struct mv643xx_private *mp,
2662 struct pkt_info *p_pkt_info)
2663{
2664 int tx_desc_curr, tx_desc_used, tx_first_desc, tx_next_desc;
2665 struct eth_tx_desc *current_descriptor;
2666 struct eth_tx_desc *first_descriptor;
2667 u32 command;
8f518703 2668 unsigned long flags;
1da177e4
LT		 2669
2670 /* Do not process Tx ring in case of Tx ring resource error */
2671 if (mp->tx_resource_err)
2672 return ETH_QUEUE_FULL;
2673
2674 /*
2675 * The hardware requires that each buffer that is <= 8 bytes
2676 * in length must be aligned on an 8 byte boundary.
2677 */
2678 if (p_pkt_info->byte_cnt <= 8 && p_pkt_info->buf_ptr & 0x7) {
2679 printk(KERN_ERR
2680 "mv643xx_eth port %d: packet size <= 8 problem\n",
2681 mp->port_num);
2682 return ETH_ERROR;
2683 }
2684
8f518703
DF		 2685 spin_lock_irqsave(&mp->lock, flags);
2686
b111ceb6
DF		 2687 mp->tx_ring_skbs++;
2688 BUG_ON(mp->tx_ring_skbs > mp->tx_ring_size);
2689
1da177e4
LT		 2690 /* Get the Tx Desc ring indexes */
2691 tx_desc_curr = mp->tx_curr_desc_q;
2692 tx_desc_used = mp->tx_used_desc_q;
2693
2694 current_descriptor = &mp->p_tx_desc_area[tx_desc_curr];
2695
2696 tx_next_desc = (tx_desc_curr + 1) % mp->tx_ring_size;
2697
2698 current_descriptor->buf_ptr = p_pkt_info->buf_ptr;
2699 current_descriptor->byte_cnt = p_pkt_info->byte_cnt;
2700 current_descriptor->l4i_chk = p_pkt_info->l4i_chk;
2701 mp->tx_skb[tx_desc_curr] = p_pkt_info->return_info;
2702
2703 command = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC |
2704 ETH_BUFFER_OWNED_BY_DMA;
2705 if (command & ETH_TX_FIRST_DESC) {
2706 tx_first_desc = tx_desc_curr;
2707 mp->tx_first_desc_q = tx_first_desc;
2708 first_descriptor = current_descriptor;
2709 mp->tx_first_command = command;
2710 } else {
2711 tx_first_desc = mp->tx_first_desc_q;
2712 first_descriptor = &mp->p_tx_desc_area[tx_first_desc];
2713 BUG_ON(first_descriptor == NULL);
2714 current_descriptor->cmd_sts = command;
2715 }
2716
2717 if (command & ETH_TX_LAST_DESC) {
2718 wmb();
2719 first_descriptor->cmd_sts = mp->tx_first_command;
2720
2721 wmb();
2722 ETH_ENABLE_TX_QUEUE(mp->port_num);
2723
2724 /*
2725 * Finish Tx packet. Update first desc in case of Tx resource
2726 * error */
2727 tx_first_desc = tx_next_desc;
2728 mp->tx_first_desc_q = tx_first_desc;
2729 }
2730
2731 /* Check for ring index overlap in the Tx desc ring */
2732 if (tx_next_desc == tx_desc_used) {
2733 mp->tx_resource_err = 1;
2734 mp->tx_curr_desc_q = tx_first_desc;
2735
8f518703
DF		 2736 spin_unlock_irqrestore(&mp->lock, flags);
2737
1da177e4
LT		 2738 return ETH_QUEUE_LAST_RESOURCE;
2739 }
2740
2741 mp->tx_curr_desc_q = tx_next_desc;
2742
8f518703
DF		 2743 spin_unlock_irqrestore(&mp->lock, flags);
2744
1da177e4
LT		 2745 return ETH_OK;
2746}
2747#else
2748static ETH_FUNC_RET_STATUS eth_port_send(struct mv643xx_private *mp,
2749 struct pkt_info *p_pkt_info)
2750{
2751 int tx_desc_curr;
2752 int tx_desc_used;
2753 struct eth_tx_desc *current_descriptor;
2754 unsigned int command_status;
8f518703 2755 unsigned long flags;
1da177e4
LT		 2756
2757 /* Do not process Tx ring in case of Tx ring resource error */
2758 if (mp->tx_resource_err)
2759 return ETH_QUEUE_FULL;
2760
8f518703
DF		 2761 spin_lock_irqsave(&mp->lock, flags);
2762
b111ceb6
DF		 2763 mp->tx_ring_skbs++;
2764 BUG_ON(mp->tx_ring_skbs > mp->tx_ring_size);
2765
1da177e4
LT		 2766 /* Get the Tx Desc ring indexes */
2767 tx_desc_curr = mp->tx_curr_desc_q;
2768 tx_desc_used = mp->tx_used_desc_q;
2769 current_descriptor = &mp->p_tx_desc_area[tx_desc_curr];
2770
2771 command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC;
2772 current_descriptor->buf_ptr = p_pkt_info->buf_ptr;
2773 current_descriptor->byte_cnt = p_pkt_info->byte_cnt;
2774 mp->tx_skb[tx_desc_curr] = p_pkt_info->return_info;
2775
2776 /* Set last desc with DMA ownership and interrupt enable. */
2777 wmb();
2778 current_descriptor->cmd_sts = command_status |
2779 ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT;
2780
2781 wmb();
2782 ETH_ENABLE_TX_QUEUE(mp->port_num);
2783
2784 /* Finish Tx packet. Update first desc in case of Tx resource error */
2785 tx_desc_curr = (tx_desc_curr + 1) % mp->tx_ring_size;
2786
2787 /* Update the current descriptor */
2788 mp->tx_curr_desc_q = tx_desc_curr;
2789
2790 /* Check for ring index overlap in the Tx desc ring */
2791 if (tx_desc_curr == tx_desc_used) {
2792 mp->tx_resource_err = 1;
8f518703
DF		 2793
2794 spin_unlock_irqrestore(&mp->lock, flags);
1da177e4
LT		 2795 return ETH_QUEUE_LAST_RESOURCE;
2796 }
2797
8f518703 2798 spin_unlock_irqrestore(&mp->lock, flags);
1da177e4
LT		 2799 return ETH_OK;
2800}
2801#endif
2802
2803/*
2804 * eth_tx_return_desc - Free all used Tx descriptors
2805 *
2806 * DESCRIPTION:
2807 * This routine returns the transmitted packet information to the caller.
2808 * It uses the 'first' index to support Tx desc return in case a transmit
2809 * of a packet spanned over multiple buffer still in process.
2810 * In case the Tx queue was in "resource error" condition, where there are
2811 * no available Tx resources, the function resets the resource error flag.
2812 *
2813 * INPUT:
2814 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2815 * struct pkt_info *p_pkt_info User packet buffer.
2816 *
2817 * OUTPUT:
2818 * Tx ring 'first' and 'used' indexes are updated.
2819 *
2820 * RETURN:
8f518703
DF		 2821 * ETH_OK on success
2822 * ETH_ERROR otherwise.
1da177e4
LT		 2823 *
2824 */
2825static ETH_FUNC_RET_STATUS eth_tx_return_desc(struct mv643xx_private *mp,
2826 struct pkt_info *p_pkt_info)
2827{
2828 int tx_desc_used;
8f518703
DF		 2829 int tx_busy_desc;
2830 struct eth_tx_desc *p_tx_desc_used;
2831 unsigned int command_status;
2832 unsigned long flags;
2833 int err = ETH_OK;
2834
2835 spin_lock_irqsave(&mp->lock, flags);
2836
1da177e4 2837#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
8f518703 2838 tx_busy_desc = mp->tx_first_desc_q;
1da177e4 2839#else
8f518703 2840 tx_busy_desc = mp->tx_curr_desc_q;
1da177e4 2841#endif
1da177e4
LT		 2842
2843 /* Get the Tx Desc ring indexes */
2844 tx_desc_used = mp->tx_used_desc_q;
2845
2846 p_tx_desc_used = &mp->p_tx_desc_area[tx_desc_used];
2847
2848 /* Sanity check */
8f518703
DF		 2849 if (p_tx_desc_used == NULL) {
2850 err = ETH_ERROR;
2851 goto out;
2852 }
1da177e4
LT		 2853
2854 /* Stop release. About to overlap the current available Tx descriptor */
8f518703
DF		 2855 if (tx_desc_used == tx_busy_desc && !mp->tx_resource_err) {
2856 err = ETH_ERROR;
2857 goto out;
2858 }
1da177e4
LT		 2859
2860 command_status = p_tx_desc_used->cmd_sts;
2861
2862 /* Still transmitting... */
8f518703
DF		 2863 if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
2864 err = ETH_ERROR;
2865 goto out;
2866 }
1da177e4
LT		 2867
2868 /* Pass the packet information to the caller */
2869 p_pkt_info->cmd_sts = command_status;
2870 p_pkt_info->return_info = mp->tx_skb[tx_desc_used];
4eaa3cb3
PG		 2871 p_pkt_info->buf_ptr = p_tx_desc_used->buf_ptr;
2872 p_pkt_info->byte_cnt = p_tx_desc_used->byte_cnt;
1da177e4
LT		 2873 mp->tx_skb[tx_desc_used] = NULL;
2874
2875 /* Update the next descriptor to release. */
2876 mp->tx_used_desc_q = (tx_desc_used + 1) % mp->tx_ring_size;
2877
2878 /* Any Tx return cancels the Tx resource error status */
2879 mp->tx_resource_err = 0;
2880
b111ceb6
DF		 2881 BUG_ON(mp->tx_ring_skbs == 0);
2882 mp->tx_ring_skbs--;
2883
8f518703
DF		 2884out:
2885 spin_unlock_irqrestore(&mp->lock, flags);
2886
2887 return err;
1da177e4
LT		 2888}
2889
2890/*
2891 * eth_port_receive - Get received information from Rx ring.
2892 *
2893 * DESCRIPTION:
2894 * This routine returns the received data to the caller. There is no
2895 * data copying during routine operation. All information is returned
2896 * using pointer to packet information struct passed from the caller.
2897 * If the routine exhausts Rx ring resources then the resource error flag
2898 * is set.
2899 *
2900 * INPUT:
2901 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2902 * struct pkt_info *p_pkt_info User packet buffer.
2903 *
2904 * OUTPUT:
2905 * Rx ring current and used indexes are updated.
2906 *
2907 * RETURN:
2908 * ETH_ERROR in case the routine can not access Rx desc ring.
2909 * ETH_QUEUE_FULL if Rx ring resources are exhausted.
2910 * ETH_END_OF_JOB if there is no received data.
2911 * ETH_OK otherwise.
2912 */
2913static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
2914 struct pkt_info *p_pkt_info)
2915{
2916 int rx_next_curr_desc, rx_curr_desc, rx_used_desc;
2917 volatile struct eth_rx_desc *p_rx_desc;
2918 unsigned int command_status;
8f518703 2919 unsigned long flags;
1da177e4
LT		 2920
2921 /* Do not process Rx ring in case of Rx ring resource error */
2922 if (mp->rx_resource_err)
2923 return ETH_QUEUE_FULL;
2924
8f518703
DF		 2925 spin_lock_irqsave(&mp->lock, flags);
2926
1da177e4
LT		 2927 /* Get the Rx Desc ring 'curr and 'used' indexes */
2928 rx_curr_desc = mp->rx_curr_desc_q;
2929 rx_used_desc = mp->rx_used_desc_q;
2930
2931 p_rx_desc = &mp->p_rx_desc_area[rx_curr_desc];
2932
2933 /* The following parameters are used to save readings from memory */
2934 command_status = p_rx_desc->cmd_sts;
2935 rmb();
2936
2937 /* Nothing to receive... */
8f518703
DF		 2938 if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
2939 spin_unlock_irqrestore(&mp->lock, flags);
1da177e4 2940 return ETH_END_OF_JOB;
8f518703 2941 }
1da177e4
LT		 2942
2943 p_pkt_info->byte_cnt = (p_rx_desc->byte_cnt) - RX_BUF_OFFSET;
2944 p_pkt_info->cmd_sts = command_status;
2945 p_pkt_info->buf_ptr = (p_rx_desc->buf_ptr) + RX_BUF_OFFSET;
2946 p_pkt_info->return_info = mp->rx_skb[rx_curr_desc];
2947 p_pkt_info->l4i_chk = p_rx_desc->buf_size;
2948
2949 /* Clean the return info field to indicate that the packet has been */
2950 /* moved to the upper layers */
2951 mp->rx_skb[rx_curr_desc] = NULL;
2952
2953 /* Update current index in data structure */
2954 rx_next_curr_desc = (rx_curr_desc + 1) % mp->rx_ring_size;
2955 mp->rx_curr_desc_q = rx_next_curr_desc;
2956
2957 /* Rx descriptors exhausted. Set the Rx ring resource error flag */
2958 if (rx_next_curr_desc == rx_used_desc)
2959 mp->rx_resource_err = 1;
2960
8f518703
DF		 2961 spin_unlock_irqrestore(&mp->lock, flags);
2962
1da177e4
LT		 2963 return ETH_OK;
2964}
2965
2966/*
2967 * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
2968 *
2969 * DESCRIPTION:
2970 * This routine returns a Rx buffer back to the Rx ring. It retrieves the
2971 * next 'used' descriptor and attached the returned buffer to it.
2972 * In case the Rx ring was in "resource error" condition, where there are
2973 * no available Rx resources, the function resets the resource error flag.
2974 *
2975 * INPUT:
2976 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2977 * struct pkt_info *p_pkt_info Information on returned buffer.
2978 *
2979 * OUTPUT:
2980 * New available Rx resource in Rx descriptor ring.
2981 *
2982 * RETURN:
2983 * ETH_ERROR in case the routine can not access Rx desc ring.
2984 * ETH_OK otherwise.
2985 */
2986static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
2987 struct pkt_info *p_pkt_info)
2988{
2989 int used_rx_desc; /* Where to return Rx resource */
2990 volatile struct eth_rx_desc *p_used_rx_desc;
8f518703
DF		 2991 unsigned long flags;
2992
2993 spin_lock_irqsave(&mp->lock, flags);
1da177e4
LT		 2994
2995 /* Get 'used' Rx descriptor */
2996 used_rx_desc = mp->rx_used_desc_q;
2997 p_used_rx_desc = &mp->p_rx_desc_area[used_rx_desc];
2998
2999 p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
3000 p_used_rx_desc->buf_size = p_pkt_info->byte_cnt;
3001 mp->rx_skb[used_rx_desc] = p_pkt_info->return_info;
3002
3003 /* Flush the write pipe */
3004
3005 /* Return the descriptor to DMA ownership */
3006 wmb();
3007 p_used_rx_desc->cmd_sts =
3008 ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
3009 wmb();
3010
3011 /* Move the used descriptor pointer to the next descriptor */
3012 mp->rx_used_desc_q = (used_rx_desc + 1) % mp->rx_ring_size;
3013
3014 /* Any Rx return cancels the Rx resource error status */
3015 mp->rx_resource_err = 0;
3016
8f518703
DF		 3017 spin_unlock_irqrestore(&mp->lock, flags);
3018
1da177e4
LT		 3019 return ETH_OK;
3020}
3021
3022/************* Begin ethtool support *************************/
3023
3024struct mv643xx_stats {
3025 char stat_string[ETH_GSTRING_LEN];
3026 int sizeof_stat;
3027 int stat_offset;
3028};
3029
3030#define MV643XX_STAT(m) sizeof(((struct mv643xx_private *)0)->m), \
3031 offsetof(struct mv643xx_private, m)
3032
3033static const struct mv643xx_stats mv643xx_gstrings_stats[] = {
3034 { "rx_packets", MV643XX_STAT(stats.rx_packets) },
3035 { "tx_packets", MV643XX_STAT(stats.tx_packets) },
3036 { "rx_bytes", MV643XX_STAT(stats.rx_bytes) },
3037 { "tx_bytes", MV643XX_STAT(stats.tx_bytes) },
3038 { "rx_errors", MV643XX_STAT(stats.rx_errors) },
3039 { "tx_errors", MV643XX_STAT(stats.tx_errors) },
3040 { "rx_dropped", MV643XX_STAT(stats.rx_dropped) },
3041 { "tx_dropped", MV643XX_STAT(stats.tx_dropped) },
3042 { "good_octets_received", MV643XX_STAT(mib_counters.good_octets_received) },
3043 { "bad_octets_received", MV643XX_STAT(mib_counters.bad_octets_received) },
3044 { "internal_mac_transmit_err", MV643XX_STAT(mib_counters.internal_mac_transmit_err) },
3045 { "good_frames_received", MV643XX_STAT(mib_counters.good_frames_received) },
3046 { "bad_frames_received", MV643XX_STAT(mib_counters.bad_frames_received) },
3047 { "broadcast_frames_received", MV643XX_STAT(mib_counters.broadcast_frames_received) },
3048 { "multicast_frames_received", MV643XX_STAT(mib_counters.multicast_frames_received) },
3049 { "frames_64_octets", MV643XX_STAT(mib_counters.frames_64_octets) },
3050 { "frames_65_to_127_octets", MV643XX_STAT(mib_counters.frames_65_to_127_octets) },
3051 { "frames_128_to_255_octets", MV643XX_STAT(mib_counters.frames_128_to_255_octets) },
3052 { "frames_256_to_511_octets", MV643XX_STAT(mib_counters.frames_256_to_511_octets) },
3053 { "frames_512_to_1023_octets", MV643XX_STAT(mib_counters.frames_512_to_1023_octets) },
3054 { "frames_1024_to_max_octets", MV643XX_STAT(mib_counters.frames_1024_to_max_octets) },
3055 { "good_octets_sent", MV643XX_STAT(mib_counters.good_octets_sent) },
3056 { "good_frames_sent", MV643XX_STAT(mib_counters.good_frames_sent) },
3057 { "excessive_collision", MV643XX_STAT(mib_counters.excessive_collision) },
3058 { "multicast_frames_sent", MV643XX_STAT(mib_counters.multicast_frames_sent) },
3059 { "broadcast_frames_sent", MV643XX_STAT(mib_counters.broadcast_frames_sent) },
3060 { "unrec_mac_control_received", MV643XX_STAT(mib_counters.unrec_mac_control_received) },
3061 { "fc_sent", MV643XX_STAT(mib_counters.fc_sent) },
3062 { "good_fc_received", MV643XX_STAT(mib_counters.good_fc_received) },
3063 { "bad_fc_received", MV643XX_STAT(mib_counters.bad_fc_received) },
3064 { "undersize_received", MV643XX_STAT(mib_counters.undersize_received) },
3065 { "fragments_received", MV643XX_STAT(mib_counters.fragments_received) },
3066 { "oversize_received", MV643XX_STAT(mib_counters.oversize_received) },
3067 { "jabber_received", MV643XX_STAT(mib_counters.jabber_received) },
3068 { "mac_receive_error", MV643XX_STAT(mib_counters.mac_receive_error) },
3069 { "bad_crc_event", MV643XX_STAT(mib_counters.bad_crc_event) },
3070 { "collision", MV643XX_STAT(mib_counters.collision) },
3071 { "late_collision", MV643XX_STAT(mib_counters.late_collision) },
3072};
3073
3074#define MV643XX_STATS_LEN \
3075 sizeof(mv643xx_gstrings_stats) / sizeof(struct mv643xx_stats)
3076
3077static int
3078mv643xx_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
3079{
3080 struct mv643xx_private *mp = netdev->priv;
3081 int port_num = mp->port_num;
3082 int autoneg = eth_port_autoneg_supported(port_num);
3083 int mode_10_bit;
3084 int auto_duplex;
3085 int half_duplex = 0;
3086 int full_duplex = 0;
3087 int auto_speed;
3088 int speed_10 = 0;
3089 int speed_100 = 0;
3090 int speed_1000 = 0;
3091
3092 u32 pcs = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
3093 u32 psr = mv_read(MV643XX_ETH_PORT_STATUS_REG(port_num));
3094
3095 mode_10_bit = psr & MV643XX_ETH_PORT_STATUS_MODE_10_BIT;
3096
3097 if (mode_10_bit) {
3098 ecmd->supported = SUPPORTED_10baseT_Half;
3099 } else {
3100 ecmd->supported = (SUPPORTED_10baseT_Half |
3101 SUPPORTED_10baseT_Full |
3102 SUPPORTED_100baseT_Half |
3103 SUPPORTED_100baseT_Full |
3104 SUPPORTED_1000baseT_Full |
3105 (autoneg ? SUPPORTED_Autoneg : 0) |
3106 SUPPORTED_TP);
3107
3108 auto_duplex = !(pcs & MV643XX_ETH_DISABLE_AUTO_NEG_FOR_DUPLX);
3109 auto_speed = !(pcs & MV643XX_ETH_DISABLE_AUTO_NEG_SPEED_GMII);
3110
3111 ecmd->advertising = ADVERTISED_TP;
3112
3113 if (autoneg) {
3114 ecmd->advertising |= ADVERTISED_Autoneg;
3115
3116 if (auto_duplex) {
3117 half_duplex = 1;
3118 full_duplex = 1;
3119 } else {
3120 if (pcs & MV643XX_ETH_SET_FULL_DUPLEX_MODE)
3121 full_duplex = 1;
3122 else
3123 half_duplex = 1;
3124 }
3125
3126 if (auto_speed) {
3127 speed_10 = 1;
3128 speed_100 = 1;
3129 speed_1000 = 1;
3130 } else {
3131 if (pcs & MV643XX_ETH_SET_GMII_SPEED_TO_1000)
3132 speed_1000 = 1;
3133 else if (pcs & MV643XX_ETH_SET_MII_SPEED_TO_100)
3134 speed_100 = 1;
3135 else
3136 speed_10 = 1;
3137 }
3138
3139 if (speed_10 & half_duplex)
3140 ecmd->advertising |= ADVERTISED_10baseT_Half;
3141 if (speed_10 & full_duplex)
3142 ecmd->advertising |= ADVERTISED_10baseT_Full;
3143 if (speed_100 & half_duplex)
3144 ecmd->advertising |= ADVERTISED_100baseT_Half;
3145 if (speed_100 & full_duplex)
3146 ecmd->advertising |= ADVERTISED_100baseT_Full;
3147 if (speed_1000)
3148 ecmd->advertising |= ADVERTISED_1000baseT_Full;
3149 }
3150 }
3151
3152 ecmd->port = PORT_TP;
3153 ecmd->phy_address = ethernet_phy_get(port_num);
3154
3155 ecmd->transceiver = XCVR_EXTERNAL;
3156
3157 if (netif_carrier_ok(netdev)) {
3158 if (mode_10_bit)
3159 ecmd->speed = SPEED_10;
3160 else {
3161 if (psr & MV643XX_ETH_PORT_STATUS_GMII_1000)
3162 ecmd->speed = SPEED_1000;
3163 else if (psr & MV643XX_ETH_PORT_STATUS_MII_100)
3164 ecmd->speed = SPEED_100;
3165 else
3166 ecmd->speed = SPEED_10;
3167 }
3168
3169 if (psr & MV643XX_ETH_PORT_STATUS_FULL_DUPLEX)
3170 ecmd->duplex = DUPLEX_FULL;
3171 else
3172 ecmd->duplex = DUPLEX_HALF;
3173 } else {
3174 ecmd->speed = -1;
3175 ecmd->duplex = -1;
3176 }
3177
3178 ecmd->autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3179 return 0;
3180}
3181
3182static void
3183mv643xx_get_drvinfo(struct net_device *netdev,
3184 struct ethtool_drvinfo *drvinfo)
3185{
3186 strncpy(drvinfo->driver, mv643xx_driver_name, 32);
3187 strncpy(drvinfo->version, mv643xx_driver_version, 32);
3188 strncpy(drvinfo->fw_version, "N/A", 32);
3189 strncpy(drvinfo->bus_info, "mv643xx", 32);
3190 drvinfo->n_stats = MV643XX_STATS_LEN;
3191}
3192
3193static int
3194mv643xx_get_stats_count(struct net_device *netdev)
3195{
3196 return MV643XX_STATS_LEN;
3197}
3198
3199static void
3200mv643xx_get_ethtool_stats(struct net_device *netdev,
3201 struct ethtool_stats *stats, uint64_t *data)
3202{
3203 struct mv643xx_private *mp = netdev->priv;
3204 int i;
3205
3206 eth_update_mib_counters(mp);
3207
3208 for(i = 0; i < MV643XX_STATS_LEN; i++) {
3209 char *p = (char *)mp+mv643xx_gstrings_stats[i].stat_offset;
3210 data[i] = (mv643xx_gstrings_stats[i].sizeof_stat ==
3211 sizeof(uint64_t)) ? *(uint64_t *)p : *(uint32_t *)p;
3212 }
3213}
3214
3215static void
3216mv643xx_get_strings(struct net_device *netdev, uint32_t stringset, uint8_t *data)
3217{
3218 int i;
3219
3220 switch(stringset) {
3221 case ETH_SS_STATS:
3222 for (i=0; i < MV643XX_STATS_LEN; i++) {
3223 memcpy(data + i * ETH_GSTRING_LEN,
3224 mv643xx_gstrings_stats[i].stat_string,
3225 ETH_GSTRING_LEN);
3226 }
3227 break;
3228 }
3229}
3230
3231static struct ethtool_ops mv643xx_ethtool_ops = {
3232 .get_settings = mv643xx_get_settings,
3233 .get_drvinfo = mv643xx_get_drvinfo,
3234 .get_link = ethtool_op_get_link,
3235 .get_sg = ethtool_op_get_sg,
3236 .set_sg = ethtool_op_set_sg,
3237 .get_strings = mv643xx_get_strings,
3238 .get_stats_count = mv643xx_get_stats_count,
3239 .get_ethtool_stats = mv643xx_get_ethtool_stats,
3240};
3241
3242/************* End ethtool support *************************/
Linux 6.x block layer and io_uring tree(s)