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mv643xx_eth: work around TX hang hardware issue
[linux-2.6-block.git] / drivers / net / mv643xx_eth.c
CommitLineData
1da177e4 1/*
9c1bbdfe 2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
1da177e4
LT		 3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
4547fa61
LB		 6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
1da177e4
LT		 8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
3bb8a18a 10 * written by Manish Lachwani
1da177e4
LT		 11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
c8aaea25 14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
1da177e4
LT		 15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
4547fa61
LB		 20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
1da177e4
LT		 23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36 */
a779d38c 37
1da177e4
LT		 38#include <linux/init.h>
39#include <linux/dma-mapping.h>
b6298c22 40#include <linux/in.h>
1da177e4
LT		 41#include <linux/tcp.h>
42#include <linux/udp.h>
43#include <linux/etherdevice.h>
1da177e4
LT		 44#include <linux/delay.h>
45#include <linux/ethtool.h>
d052d1be 46#include <linux/platform_device.h>
fbd6a754
LB		 47#include <linux/module.h>
48#include <linux/kernel.h>
49#include <linux/spinlock.h>
50#include <linux/workqueue.h>
51#include <linux/mii.h>
fbd6a754 52#include <linux/mv643xx_eth.h>
1da177e4
LT		 53#include <asm/io.h>
54#include <asm/types.h>
1da177e4 55#include <asm/system.h>
fbd6a754 56
e5371493
LB		 57static char mv643xx_eth_driver_name[] = "mv643xx_eth";
58static char mv643xx_eth_driver_version[] = "1.0";
c9df406f 59
e5371493
LB		 60#define MV643XX_ETH_CHECKSUM_OFFLOAD_TX
61#define MV643XX_ETH_NAPI
62#define MV643XX_ETH_TX_FAST_REFILL
fbd6a754 63
e5371493 64#ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
fbd6a754
LB		 65#define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
66#else
67#define MAX_DESCS_PER_SKB 1
68#endif
69
fbd6a754
LB		 70/*
71 * Registers shared between all ports.
72 */
3cb4667c
LB		 73#define PHY_ADDR 0x0000
74#define SMI_REG 0x0004
75#define WINDOW_BASE(w) (0x0200 + ((w) << 3))
76#define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
77#define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
78#define WINDOW_BAR_ENABLE 0x0290
79#define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
fbd6a754
LB		 80
81/*
82 * Per-port registers.
83 */
3cb4667c 84#define PORT_CONFIG(p) (0x0400 + ((p) << 10))
d9a073ea 85#define UNICAST_PROMISCUOUS_MODE 0x00000001
3cb4667c
LB		 86#define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
87#define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
88#define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
89#define SDMA_CONFIG(p) (0x041c + ((p) << 10))
90#define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
91#define PORT_STATUS(p) (0x0444 + ((p) << 10))
a2a41689 92#define TX_FIFO_EMPTY 0x00000400
3cb4667c 93#define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
89df5fdc
LB		 94#define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10))
95#define TX_BW_RATE(p) (0x0450 + ((p) << 10))
3cb4667c 96#define TX_BW_MTU(p) (0x0458 + ((p) << 10))
89df5fdc 97#define TX_BW_BURST(p) (0x045c + ((p) << 10))
3cb4667c 98#define INT_CAUSE(p) (0x0460 + ((p) << 10))
226bb6b7 99#define INT_TX_END 0x07f80000
64da80a2 100#define INT_RX 0x0007fbfc
073a345c 101#define INT_EXT 0x00000002
3cb4667c 102#define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
073a345c
LB		 103#define INT_EXT_LINK 0x00100000
104#define INT_EXT_PHY 0x00010000
105#define INT_EXT_TX_ERROR_0 0x00000100
106#define INT_EXT_TX_0 0x00000001
3d6b35bc 107#define INT_EXT_TX 0x0000ffff
3cb4667c
LB		 108#define INT_MASK(p) (0x0468 + ((p) << 10))
109#define INT_MASK_EXT(p) (0x046c + ((p) << 10))
110#define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
64da80a2 111#define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4))
3cb4667c 112#define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
3d6b35bc
LB		 113#define TXQ_CURRENT_DESC_PTR(p, q) (0x06c0 + ((p) << 10) + ((q) << 2))
114#define TXQ_BW_TOKENS(p, q) (0x0700 + ((p) << 10) + ((q) << 4))
115#define TXQ_BW_CONF(p, q) (0x0704 + ((p) << 10) + ((q) << 4))
116#define TXQ_BW_WRR_CONF(p, q) (0x0708 + ((p) << 10) + ((q) << 4))
3cb4667c
LB		 117#define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
118#define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
119#define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
120#define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
fbd6a754 121
2679a550
LB		 122
123/*
124 * SDMA configuration register.
125 */
fbd6a754 126#define RX_BURST_SIZE_4_64BIT (2 << 1)
fbd6a754 127#define BLM_RX_NO_SWAP (1 << 4)
fbd6a754 128#define BLM_TX_NO_SWAP (1 << 5)
fbd6a754 129#define TX_BURST_SIZE_4_64BIT (2 << 22)
fbd6a754
LB		 130
131#if defined(__BIG_ENDIAN)
132#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
133 RX_BURST_SIZE_4_64BIT | \
fbd6a754
LB		 134 TX_BURST_SIZE_4_64BIT
135#elif defined(__LITTLE_ENDIAN)
136#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
137 RX_BURST_SIZE_4_64BIT | \
138 BLM_RX_NO_SWAP | \
139 BLM_TX_NO_SWAP | \
fbd6a754
LB		 140 TX_BURST_SIZE_4_64BIT
141#else
142#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
143#endif
144
2beff77b
LB		 145
146/*
147 * Port serial control register.
148 */
149#define SET_MII_SPEED_TO_100 (1 << 24)
150#define SET_GMII_SPEED_TO_1000 (1 << 23)
151#define SET_FULL_DUPLEX_MODE (1 << 21)
fbd6a754 152#define MAX_RX_PACKET_1522BYTE (1 << 17)
fbd6a754
LB		 153#define MAX_RX_PACKET_9700BYTE (5 << 17)
154#define MAX_RX_PACKET_MASK (7 << 17)
2beff77b
LB		 155#define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
156#define DO_NOT_FORCE_LINK_FAIL (1 << 10)
157#define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
158#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
159#define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
160#define FORCE_LINK_PASS (1 << 1)
161#define SERIAL_PORT_ENABLE (1 << 0)
fbd6a754 162
cc9754b3
LB		 163#define DEFAULT_RX_QUEUE_SIZE 400
164#define DEFAULT_TX_QUEUE_SIZE 800
fbd6a754 165
fbd6a754 166
7ca72a3b
LB		 167/*
168 * RX/TX descriptors.
fbd6a754
LB		 169 */
170#if defined(__BIG_ENDIAN)
cc9754b3 171struct rx_desc {
fbd6a754
LB		 172 u16 byte_cnt; /* Descriptor buffer byte count */
173 u16 buf_size; /* Buffer size */
174 u32 cmd_sts; /* Descriptor command status */
175 u32 next_desc_ptr; /* Next descriptor pointer */
176 u32 buf_ptr; /* Descriptor buffer pointer */
177};
178
cc9754b3 179struct tx_desc {
fbd6a754
LB		 180 u16 byte_cnt; /* buffer byte count */
181 u16 l4i_chk; /* CPU provided TCP checksum */
182 u32 cmd_sts; /* Command/status field */
183 u32 next_desc_ptr; /* Pointer to next descriptor */
184 u32 buf_ptr; /* pointer to buffer for this descriptor*/
185};
186#elif defined(__LITTLE_ENDIAN)
cc9754b3 187struct rx_desc {
fbd6a754
LB		 188 u32 cmd_sts; /* Descriptor command status */
189 u16 buf_size; /* Buffer size */
190 u16 byte_cnt; /* Descriptor buffer byte count */
191 u32 buf_ptr; /* Descriptor buffer pointer */
192 u32 next_desc_ptr; /* Next descriptor pointer */
193};
194
cc9754b3 195struct tx_desc {
fbd6a754
LB		 196 u32 cmd_sts; /* Command/status field */
197 u16 l4i_chk; /* CPU provided TCP checksum */
198 u16 byte_cnt; /* buffer byte count */
199 u32 buf_ptr; /* pointer to buffer for this descriptor*/
200 u32 next_desc_ptr; /* Pointer to next descriptor */
201};
202#else
203#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
204#endif
205
7ca72a3b 206/* RX & TX descriptor command */
cc9754b3 207#define BUFFER_OWNED_BY_DMA 0x80000000
7ca72a3b
LB		 208
209/* RX & TX descriptor status */
cc9754b3 210#define ERROR_SUMMARY 0x00000001
7ca72a3b
LB		 211
212/* RX descriptor status */
cc9754b3
LB		 213#define LAYER_4_CHECKSUM_OK 0x40000000
214#define RX_ENABLE_INTERRUPT 0x20000000
215#define RX_FIRST_DESC 0x08000000
216#define RX_LAST_DESC 0x04000000
7ca72a3b
LB		 217
218/* TX descriptor command */
cc9754b3
LB		 219#define TX_ENABLE_INTERRUPT 0x00800000
220#define GEN_CRC 0x00400000
221#define TX_FIRST_DESC 0x00200000
222#define TX_LAST_DESC 0x00100000
223#define ZERO_PADDING 0x00080000
224#define GEN_IP_V4_CHECKSUM 0x00040000
225#define GEN_TCP_UDP_CHECKSUM 0x00020000
226#define UDP_FRAME 0x00010000
7ca72a3b 227
cc9754b3 228#define TX_IHL_SHIFT 11
7ca72a3b
LB		 229
230
c9df406f 231/* global *******************************************************************/
e5371493 232struct mv643xx_eth_shared_private {
fc32b0e2
LB		 233 /*
234 * Ethernet controller base address.
235 */
cc9754b3 236 void __iomem *base;
c9df406f 237
fc32b0e2
LB		 238 /*
239 * Protects access to SMI_REG, which is shared between ports.
240 */
c9df406f
LB		 241 spinlock_t phy_lock;
242
fc32b0e2
LB		 243 /*
244 * Per-port MBUS window access register value.
245 */
c9df406f
LB		 246 u32 win_protect;
247
fc32b0e2
LB		 248 /*
249 * Hardware-specific parameters.
250 */
c9df406f
LB		 251 unsigned int t_clk;
252};
253
254
255/* per-port *****************************************************************/
e5371493 256struct mib_counters {
fbd6a754
LB		 257 u64 good_octets_received;
258 u32 bad_octets_received;
259 u32 internal_mac_transmit_err;
260 u32 good_frames_received;
261 u32 bad_frames_received;
262 u32 broadcast_frames_received;
263 u32 multicast_frames_received;
264 u32 frames_64_octets;
265 u32 frames_65_to_127_octets;
266 u32 frames_128_to_255_octets;
267 u32 frames_256_to_511_octets;
268 u32 frames_512_to_1023_octets;
269 u32 frames_1024_to_max_octets;
270 u64 good_octets_sent;
271 u32 good_frames_sent;
272 u32 excessive_collision;
273 u32 multicast_frames_sent;
274 u32 broadcast_frames_sent;
275 u32 unrec_mac_control_received;
276 u32 fc_sent;
277 u32 good_fc_received;
278 u32 bad_fc_received;
279 u32 undersize_received;
280 u32 fragments_received;
281 u32 oversize_received;
282 u32 jabber_received;
283 u32 mac_receive_error;
284 u32 bad_crc_event;
285 u32 collision;
286 u32 late_collision;
287};
288
8a578111 289struct rx_queue {
64da80a2
LB		 290 int index;
291
8a578111
LB		 292 int rx_ring_size;
293
294 int rx_desc_count;
295 int rx_curr_desc;
296 int rx_used_desc;
297
298 struct rx_desc *rx_desc_area;
299 dma_addr_t rx_desc_dma;
300 int rx_desc_area_size;
301 struct sk_buff **rx_skb;
302
303 struct timer_list rx_oom;
304};
305
13d64285 306struct tx_queue {
3d6b35bc
LB		 307 int index;
308
13d64285 309 int tx_ring_size;
fbd6a754 310
13d64285
LB		 311 int tx_desc_count;
312 int tx_curr_desc;
313 int tx_used_desc;
fbd6a754 314
5daffe94 315 struct tx_desc *tx_desc_area;
fbd6a754
LB		 316 dma_addr_t tx_desc_dma;
317 int tx_desc_area_size;
318 struct sk_buff **tx_skb;
13d64285
LB		 319};
320
321struct mv643xx_eth_private {
322 struct mv643xx_eth_shared_private *shared;
fc32b0e2 323 int port_num;
13d64285 324
fc32b0e2 325 struct net_device *dev;
fbd6a754 326
fc32b0e2
LB		 327 struct mv643xx_eth_shared_private *shared_smi;
328 int phy_addr;
fbd6a754 329
fbd6a754 330 spinlock_t lock;
fbd6a754 331
fc32b0e2
LB		 332 struct mib_counters mib_counters;
333 struct work_struct tx_timeout_task;
fbd6a754 334 struct mii_if_info mii;
8a578111
LB		 335
336 /*
337 * RX state.
338 */
339 int default_rx_ring_size;
340 unsigned long rx_desc_sram_addr;
341 int rx_desc_sram_size;
64da80a2
LB		 342 u8 rxq_mask;
343 int rxq_primary;
8a578111 344 struct napi_struct napi;
64da80a2 345 struct rx_queue rxq[8];
13d64285
LB		 346
347 /*
348 * TX state.
349 */
350 int default_tx_ring_size;
351 unsigned long tx_desc_sram_addr;
352 int tx_desc_sram_size;
3d6b35bc
LB		 353 u8 txq_mask;
354 int txq_primary;
355 struct tx_queue txq[8];
13d64285
LB		 356#ifdef MV643XX_ETH_TX_FAST_REFILL
357 int tx_clean_threshold;
358#endif
fbd6a754 359};
1da177e4 360
fbd6a754 361
c9df406f 362/* port register accessors **************************************************/
e5371493 363static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
c9df406f 364{
cc9754b3 365 return readl(mp->shared->base + offset);
c9df406f 366}
fbd6a754 367
e5371493 368static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
c9df406f 369{
cc9754b3 370 writel(data, mp->shared->base + offset);
c9df406f 371}
fbd6a754 372
fbd6a754 373
c9df406f 374/* rxq/txq helper functions *************************************************/
8a578111 375static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
c9df406f 376{
64da80a2 377 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
c9df406f 378}
fbd6a754 379
13d64285
LB		 380static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
381{
3d6b35bc 382 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
13d64285
LB		 383}
384
8a578111 385static void rxq_enable(struct rx_queue *rxq)
c9df406f 386{
8a578111 387 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
64da80a2 388 wrl(mp, RXQ_COMMAND(mp->port_num), 1 << rxq->index);
8a578111 389}
1da177e4 390
8a578111
LB		 391static void rxq_disable(struct rx_queue *rxq)
392{
393 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
64da80a2 394 u8 mask = 1 << rxq->index;
1da177e4 395
8a578111
LB		 396 wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8);
397 while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask)
398 udelay(10);
c9df406f
LB		 399}
400
13d64285 401static void txq_enable(struct tx_queue *txq)
1da177e4 402{
13d64285 403 struct mv643xx_eth_private *mp = txq_to_mp(txq);
3d6b35bc 404 wrl(mp, TXQ_COMMAND(mp->port_num), 1 << txq->index);
1da177e4
LT		 405}
406
13d64285 407static void txq_disable(struct tx_queue *txq)
1da177e4 408{
13d64285 409 struct mv643xx_eth_private *mp = txq_to_mp(txq);
3d6b35bc 410 u8 mask = 1 << txq->index;
c9df406f 411
13d64285
LB		 412 wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8);
413 while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask)
414 udelay(10);
415}
416
417static void __txq_maybe_wake(struct tx_queue *txq)
418{
419 struct mv643xx_eth_private *mp = txq_to_mp(txq);
420
3d6b35bc
LB		 421 /*
422 * netif_{stop,wake}_queue() flow control only applies to
423 * the primary queue.
424 */
425 BUG_ON(txq->index != mp->txq_primary);
426
13d64285
LB		 427 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_DESCS_PER_SKB)
428 netif_wake_queue(mp->dev);
1da177e4
LT		 429}
430
c9df406f
LB		 431
432/* rx ***********************************************************************/
13d64285 433static void txq_reclaim(struct tx_queue *txq, int force);
c9df406f 434
8a578111 435static void rxq_refill(struct rx_queue *rxq)
1da177e4 436{
8a578111 437 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
c9df406f 438 unsigned long flags;
1da177e4 439
c9df406f 440 spin_lock_irqsave(&mp->lock, flags);
c0d0f2ca 441
8a578111
LB		 442 while (rxq->rx_desc_count < rxq->rx_ring_size) {
443 int skb_size;
de34f225
LB		 444 struct sk_buff *skb;
445 int unaligned;
446 int rx;
447
8a578111
LB		 448 /*
449 * Reserve 2+14 bytes for an ethernet header (the
450 * hardware automatically prepends 2 bytes of dummy
451 * data to each received packet), 4 bytes for a VLAN
452 * header, and 4 bytes for the trailing FCS -- 24
453 * bytes total.
454 */
455 skb_size = mp->dev->mtu + 24;
456
457 skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1);
de34f225 458 if (skb == NULL)
1da177e4 459 break;
de34f225 460
908b637f 461 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
b44cd572 462 if (unaligned)
908b637f 463 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
de34f225 464
8a578111
LB		 465 rxq->rx_desc_count++;
466 rx = rxq->rx_used_desc;
467 rxq->rx_used_desc = (rx + 1) % rxq->rx_ring_size;
de34f225 468
8a578111
LB		 469 rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
470 skb_size, DMA_FROM_DEVICE);
471 rxq->rx_desc_area[rx].buf_size = skb_size;
472 rxq->rx_skb[rx] = skb;
de34f225 473 wmb();
8a578111 474 rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
de34f225
LB		 475 RX_ENABLE_INTERRUPT;
476 wmb();
477
fc32b0e2
LB		 478 /*
479 * The hardware automatically prepends 2 bytes of
480 * dummy data to each received packet, so that the
481 * IP header ends up 16-byte aligned.
482 */
483 skb_reserve(skb, 2);
1da177e4 484 }
de34f225 485
8a578111
LB		 486 if (rxq->rx_desc_count == 0) {
487 rxq->rx_oom.expires = jiffies + (HZ / 10);
488 add_timer(&rxq->rx_oom);
1da177e4 489 }
de34f225
LB		 490
491 spin_unlock_irqrestore(&mp->lock, flags);
1da177e4
LT		 492}
493
8a578111 494static inline void rxq_refill_timer_wrapper(unsigned long data)
1da177e4 495{
8a578111 496 rxq_refill((struct rx_queue *)data);
1da177e4
LT		 497}
498
8a578111 499static int rxq_process(struct rx_queue *rxq, int budget)
1da177e4 500{
8a578111
LB		 501 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
502 struct net_device_stats *stats = &mp->dev->stats;
503 int rx;
1da177e4 504
8a578111
LB		 505 rx = 0;
506 while (rx < budget) {
fc32b0e2 507 struct rx_desc *rx_desc;
96587661 508 unsigned int cmd_sts;
fc32b0e2 509 struct sk_buff *skb;
96587661 510 unsigned long flags;
d344bff9 511
96587661 512 spin_lock_irqsave(&mp->lock, flags);
ff561eef 513
8a578111 514 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
1da177e4 515
96587661
LB		 516 cmd_sts = rx_desc->cmd_sts;
517 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
518 spin_unlock_irqrestore(&mp->lock, flags);
519 break;
520 }
521 rmb();
1da177e4 522
8a578111
LB		 523 skb = rxq->rx_skb[rxq->rx_curr_desc];
524 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
ff561eef 525
8a578111 526 rxq->rx_curr_desc = (rxq->rx_curr_desc + 1) % rxq->rx_ring_size;
ff561eef 527
96587661 528 spin_unlock_irqrestore(&mp->lock, flags);
1da177e4 529
fc32b0e2
LB		 530 dma_unmap_single(NULL, rx_desc->buf_ptr + 2,
531 mp->dev->mtu + 24, DMA_FROM_DEVICE);
8a578111
LB		 532 rxq->rx_desc_count--;
533 rx++;
b1dd9ca1 534
468d09f8
DF		 535 /*
536 * Update statistics.
fc32b0e2
LB		 537 *
538 * Note that the descriptor byte count includes 2 dummy
539 * bytes automatically inserted by the hardware at the
540 * start of the packet (which we don't count), and a 4
541 * byte CRC at the end of the packet (which we do count).
468d09f8 542 */
1da177e4 543 stats->rx_packets++;
fc32b0e2 544 stats->rx_bytes += rx_desc->byte_cnt - 2;
96587661 545
1da177e4 546 /*
fc32b0e2
LB		 547 * In case we received a packet without first / last bits
548 * on, or the error summary bit is set, the packet needs
549 * to be dropped.
1da177e4 550 */
96587661 551 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
cc9754b3 552 (RX_FIRST_DESC | RX_LAST_DESC))
96587661 553 || (cmd_sts & ERROR_SUMMARY)) {
1da177e4 554 stats->rx_dropped++;
fc32b0e2 555
96587661 556 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
cc9754b3 557 (RX_FIRST_DESC | RX_LAST_DESC)) {
1da177e4 558 if (net_ratelimit())
fc32b0e2
LB		 559 dev_printk(KERN_ERR, &mp->dev->dev,
560 "received packet spanning "
561 "multiple descriptors\n");
1da177e4 562 }
fc32b0e2 563
96587661 564 if (cmd_sts & ERROR_SUMMARY)
1da177e4
LT		 565 stats->rx_errors++;
566
567 dev_kfree_skb_irq(skb);
568 } else {
569 /*
570 * The -4 is for the CRC in the trailer of the
571 * received packet
572 */
fc32b0e2 573 skb_put(skb, rx_desc->byte_cnt - 2 - 4);
1da177e4 574
96587661 575 if (cmd_sts & LAYER_4_CHECKSUM_OK) {
1da177e4
LT		 576 skb->ip_summed = CHECKSUM_UNNECESSARY;
577 skb->csum = htons(
96587661 578 (cmd_sts & 0x0007fff8) >> 3);
1da177e4 579 }
8a578111 580 skb->protocol = eth_type_trans(skb, mp->dev);
e5371493 581#ifdef MV643XX_ETH_NAPI
1da177e4
LT		 582 netif_receive_skb(skb);
583#else
584 netif_rx(skb);
585#endif
586 }
fc32b0e2 587
8a578111 588 mp->dev->last_rx = jiffies;
1da177e4 589 }
fc32b0e2 590
8a578111 591 rxq_refill(rxq);
1da177e4 592
8a578111 593 return rx;
1da177e4
LT		 594}
595
e5371493 596#ifdef MV643XX_ETH_NAPI
e5371493 597static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
d0412d96 598{
8a578111
LB		 599 struct mv643xx_eth_private *mp;
600 int rx;
64da80a2 601 int i;
8a578111
LB		 602
603 mp = container_of(napi, struct mv643xx_eth_private, napi);
d0412d96 604
e5371493 605#ifdef MV643XX_ETH_TX_FAST_REFILL
c9df406f 606 if (++mp->tx_clean_threshold > 5) {
c9df406f 607 mp->tx_clean_threshold = 0;
3d6b35bc
LB		 608 for (i = 0; i < 8; i++)
609 if (mp->txq_mask & (1 << i))
610 txq_reclaim(mp->txq + i, 0);
d0412d96 611 }
c9df406f 612#endif
d0412d96 613
64da80a2
LB		 614 rx = 0;
615 for (i = 7; rx < budget && i >= 0; i--)
616 if (mp->rxq_mask & (1 << i))
617 rx += rxq_process(mp->rxq + i, budget - rx);
d0412d96 618
8a578111
LB		 619 if (rx < budget) {
620 netif_rx_complete(mp->dev, napi);
621 wrl(mp, INT_CAUSE(mp->port_num), 0);
622 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
226bb6b7 623 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
d0412d96 624 }
c9df406f 625
8a578111 626 return rx;
d0412d96 627}
c9df406f 628#endif
d0412d96 629
c9df406f
LB		 630
631/* tx ***********************************************************************/
c9df406f 632static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1da177e4 633{
13d64285 634 int frag;
1da177e4 635
c9df406f 636 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
13d64285
LB		 637 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
638 if (fragp->size <= 8 && fragp->page_offset & 7)
c9df406f 639 return 1;
1da177e4 640 }
13d64285 641
c9df406f
LB		 642 return 0;
643}
7303fde8 644
13d64285 645static int txq_alloc_desc_index(struct tx_queue *txq)
c9df406f
LB		 646{
647 int tx_desc_curr;
d0412d96 648
13d64285 649 BUG_ON(txq->tx_desc_count >= txq->tx_ring_size);
1da177e4 650
13d64285
LB		 651 tx_desc_curr = txq->tx_curr_desc;
652 txq->tx_curr_desc = (tx_desc_curr + 1) % txq->tx_ring_size;
e4d00fa9 653
13d64285 654 BUG_ON(txq->tx_curr_desc == txq->tx_used_desc);
468d09f8 655
c9df406f
LB		 656 return tx_desc_curr;
657}
468d09f8 658
13d64285 659static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
c9df406f 660{
13d64285 661 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 662 int frag;
1da177e4 663
13d64285
LB		 664 for (frag = 0; frag < nr_frags; frag++) {
665 skb_frag_t *this_frag;
666 int tx_index;
667 struct tx_desc *desc;
668
669 this_frag = &skb_shinfo(skb)->frags[frag];
670 tx_index = txq_alloc_desc_index(txq);
671 desc = &txq->tx_desc_area[tx_index];
672
673 /*
674 * The last fragment will generate an interrupt
675 * which will free the skb on TX completion.
676 */
677 if (frag == nr_frags - 1) {
678 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
679 ZERO_PADDING | TX_LAST_DESC |
680 TX_ENABLE_INTERRUPT;
681 txq->tx_skb[tx_index] = skb;
682 } else {
683 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
684 txq->tx_skb[tx_index] = NULL;
685 }
686
c9df406f
LB		 687 desc->l4i_chk = 0;
688 desc->byte_cnt = this_frag->size;
689 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
690 this_frag->page_offset,
691 this_frag->size,
692 DMA_TO_DEVICE);
693 }
1da177e4
LT		 694}
695
c9df406f
LB		 696static inline __be16 sum16_as_be(__sum16 sum)
697{
698 return (__force __be16)sum;
699}
1da177e4 700
13d64285 701static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
1da177e4 702{
13d64285 703 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 704 int tx_index;
cc9754b3 705 struct tx_desc *desc;
c9df406f
LB		 706 u32 cmd_sts;
707 int length;
1da177e4 708
cc9754b3 709 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
1da177e4 710
13d64285
LB		 711 tx_index = txq_alloc_desc_index(txq);
712 desc = &txq->tx_desc_area[tx_index];
c9df406f
LB		 713
714 if (nr_frags) {
13d64285 715 txq_submit_frag_skb(txq, skb);
c9df406f
LB		 716
717 length = skb_headlen(skb);
13d64285 718 txq->tx_skb[tx_index] = NULL;
c9df406f 719 } else {
cc9754b3 720 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
c9df406f 721 length = skb->len;
13d64285 722 txq->tx_skb[tx_index] = skb;
c9df406f
LB		 723 }
724
725 desc->byte_cnt = length;
726 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
727
728 if (skb->ip_summed == CHECKSUM_PARTIAL) {
729 BUG_ON(skb->protocol != htons(ETH_P_IP));
730
cc9754b3
LB		 731 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
732 GEN_IP_V4_CHECKSUM |
733 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
c9df406f
LB		 734
735 switch (ip_hdr(skb)->protocol) {
736 case IPPROTO_UDP:
cc9754b3 737 cmd_sts |= UDP_FRAME;
c9df406f
LB		 738 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
739 break;
740 case IPPROTO_TCP:
741 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
742 break;
743 default:
744 BUG();
745 }
746 } else {
747 /* Errata BTS #50, IHL must be 5 if no HW checksum */
cc9754b3 748 cmd_sts |= 5 << TX_IHL_SHIFT;
c9df406f
LB		 749 desc->l4i_chk = 0;
750 }
751
752 /* ensure all other descriptors are written before first cmd_sts */
753 wmb();
754 desc->cmd_sts = cmd_sts;
755
756 /* ensure all descriptors are written before poking hardware */
757 wmb();
13d64285 758 txq_enable(txq);
c9df406f 759
13d64285 760 txq->tx_desc_count += nr_frags + 1;
1da177e4 761}
1da177e4 762
fc32b0e2 763static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 764{
e5371493 765 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 766 struct net_device_stats *stats = &dev->stats;
13d64285 767 struct tx_queue *txq;
c9df406f 768 unsigned long flags;
afdb57a2 769
c9df406f
LB		 770 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
771 stats->tx_dropped++;
fc32b0e2
LB		 772 dev_printk(KERN_DEBUG, &dev->dev,
773 "failed to linearize skb with tiny "
774 "unaligned fragment\n");
c9df406f
LB		 775 return NETDEV_TX_BUSY;
776 }
777
778 spin_lock_irqsave(&mp->lock, flags);
779
3d6b35bc 780 txq = mp->txq + mp->txq_primary;
13d64285
LB		 781
782 if (txq->tx_ring_size - txq->tx_desc_count < MAX_DESCS_PER_SKB) {
c9df406f 783 spin_unlock_irqrestore(&mp->lock, flags);
3d6b35bc
LB		 784 if (txq->index == mp->txq_primary && net_ratelimit())
785 dev_printk(KERN_ERR, &dev->dev,
786 "primary tx queue full?!\n");
787 kfree_skb(skb);
788 return NETDEV_TX_OK;
c9df406f
LB		 789 }
790
13d64285 791 txq_submit_skb(txq, skb);
c9df406f
LB		 792 stats->tx_bytes += skb->len;
793 stats->tx_packets++;
794 dev->trans_start = jiffies;
795
3d6b35bc
LB		 796 if (txq->index == mp->txq_primary) {
797 int entries_left;
798
799 entries_left = txq->tx_ring_size - txq->tx_desc_count;
800 if (entries_left < MAX_DESCS_PER_SKB)
801 netif_stop_queue(dev);
802 }
c9df406f
LB		 803
804 spin_unlock_irqrestore(&mp->lock, flags);
805
806 return NETDEV_TX_OK;
1da177e4
LT		 807}
808
c9df406f 809
89df5fdc
LB		 810/* tx rate control **********************************************************/
811/*
812 * Set total maximum TX rate (shared by all TX queues for this port)
813 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
814 */
815static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
816{
817 int token_rate;
818 int mtu;
819 int bucket_size;
820
821 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
822 if (token_rate > 1023)
823 token_rate = 1023;
824
825 mtu = (mp->dev->mtu + 255) >> 8;
826 if (mtu > 63)
827 mtu = 63;
828
829 bucket_size = (burst + 255) >> 8;
830 if (bucket_size > 65535)
831 bucket_size = 65535;
832
833 wrl(mp, TX_BW_RATE(mp->port_num), token_rate);
834 wrl(mp, TX_BW_MTU(mp->port_num), mtu);
835 wrl(mp, TX_BW_BURST(mp->port_num), bucket_size);
836}
837
838static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
839{
840 struct mv643xx_eth_private *mp = txq_to_mp(txq);
841 int token_rate;
842 int bucket_size;
843
844 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
845 if (token_rate > 1023)
846 token_rate = 1023;
847
848 bucket_size = (burst + 255) >> 8;
849 if (bucket_size > 65535)
850 bucket_size = 65535;
851
3d6b35bc
LB		 852 wrl(mp, TXQ_BW_TOKENS(mp->port_num, txq->index), token_rate << 14);
853 wrl(mp, TXQ_BW_CONF(mp->port_num, txq->index),
89df5fdc
LB		 854 (bucket_size << 10) | token_rate);
855}
856
857static void txq_set_fixed_prio_mode(struct tx_queue *txq)
858{
859 struct mv643xx_eth_private *mp = txq_to_mp(txq);
860 int off;
861 u32 val;
862
863 /*
864 * Turn on fixed priority mode.
865 */
866 off = TXQ_FIX_PRIO_CONF(mp->port_num);
867
868 val = rdl(mp, off);
3d6b35bc 869 val |= 1 << txq->index;
89df5fdc
LB		 870 wrl(mp, off, val);
871}
872
873static void txq_set_wrr(struct tx_queue *txq, int weight)
874{
875 struct mv643xx_eth_private *mp = txq_to_mp(txq);
876 int off;
877 u32 val;
878
879 /*
880 * Turn off fixed priority mode.
881 */
882 off = TXQ_FIX_PRIO_CONF(mp->port_num);
883
884 val = rdl(mp, off);
3d6b35bc 885 val &= ~(1 << txq->index);
89df5fdc
LB		 886 wrl(mp, off, val);
887
888 /*
889 * Configure WRR weight for this queue.
890 */
3d6b35bc 891 off = TXQ_BW_WRR_CONF(mp->port_num, txq->index);
89df5fdc
LB		 892
893 val = rdl(mp, off);
894 val = (val & ~0xff) | (weight & 0xff);
895 wrl(mp, off, val);
896}
897
898
c9df406f 899/* mii management interface *************************************************/
fc32b0e2
LB		 900#define SMI_BUSY 0x10000000
901#define SMI_READ_VALID 0x08000000
902#define SMI_OPCODE_READ 0x04000000
903#define SMI_OPCODE_WRITE 0x00000000
c9df406f 904
fc32b0e2
LB		 905static void smi_reg_read(struct mv643xx_eth_private *mp, unsigned int addr,
906 unsigned int reg, unsigned int *value)
1da177e4 907{
cc9754b3 908 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
c9df406f 909 unsigned long flags;
1da177e4
LT		 910 int i;
911
c9df406f
LB		 912 /* the SMI register is a shared resource */
913 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
914
915 /* wait for the SMI register to become available */
cc9754b3 916 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
e1bea50a 917 if (i == 1000) {
c9df406f
LB		 918 printk("%s: PHY busy timeout\n", mp->dev->name);
919 goto out;
920 }
e1bea50a 921 udelay(10);
1da177e4
LT		 922 }
923
fc32b0e2 924 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1da177e4 925
c9df406f 926 /* now wait for the data to be valid */
cc9754b3 927 for (i = 0; !(readl(smi_reg) & SMI_READ_VALID); i++) {
e1bea50a 928 if (i == 1000) {
c9df406f
LB		 929 printk("%s: PHY read timeout\n", mp->dev->name);
930 goto out;
931 }
e1bea50a 932 udelay(10);
c9df406f
LB		 933 }
934
935 *value = readl(smi_reg) & 0xffff;
936out:
937 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
1da177e4
LT		 938}
939
fc32b0e2
LB		 940static void smi_reg_write(struct mv643xx_eth_private *mp,
941 unsigned int addr,
942 unsigned int reg, unsigned int value)
1da177e4 943{
cc9754b3 944 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
c9df406f 945 unsigned long flags;
1da177e4
LT		 946 int i;
947
c9df406f
LB		 948 /* the SMI register is a shared resource */
949 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
950
951 /* wait for the SMI register to become available */
cc9754b3 952 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
e1bea50a 953 if (i == 1000) {
c9df406f
LB		 954 printk("%s: PHY busy timeout\n", mp->dev->name);
955 goto out;
956 }
e1bea50a 957 udelay(10);
1da177e4
LT		 958 }
959
fc32b0e2
LB		 960 writel(SMI_OPCODE_WRITE | (reg << 21) |
961 (addr << 16) | (value & 0xffff), smi_reg);
c9df406f
LB		 962out:
963 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
964}
1da177e4 965
c9df406f
LB		 966
967/* mib counters *************************************************************/
fc32b0e2 968static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
c9df406f 969{
fc32b0e2 970 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1da177e4
LT		 971}
972
fc32b0e2 973static void mib_counters_clear(struct mv643xx_eth_private *mp)
d0412d96 974{
fc32b0e2
LB		 975 int i;
976
977 for (i = 0; i < 0x80; i += 4)
978 mib_read(mp, i);
c9df406f 979}
d0412d96 980
fc32b0e2 981static void mib_counters_update(struct mv643xx_eth_private *mp)
c9df406f 982{
e5371493 983 struct mib_counters *p = &mp->mib_counters;
4b8e3655 984
fc32b0e2
LB		 985 p->good_octets_received += mib_read(mp, 0x00);
986 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
987 p->bad_octets_received += mib_read(mp, 0x08);
988 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
989 p->good_frames_received += mib_read(mp, 0x10);
990 p->bad_frames_received += mib_read(mp, 0x14);
991 p->broadcast_frames_received += mib_read(mp, 0x18);
992 p->multicast_frames_received += mib_read(mp, 0x1c);
993 p->frames_64_octets += mib_read(mp, 0x20);
994 p->frames_65_to_127_octets += mib_read(mp, 0x24);
995 p->frames_128_to_255_octets += mib_read(mp, 0x28);
996 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
997 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
998 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
999 p->good_octets_sent += mib_read(mp, 0x38);
1000 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1001 p->good_frames_sent += mib_read(mp, 0x40);
1002 p->excessive_collision += mib_read(mp, 0x44);
1003 p->multicast_frames_sent += mib_read(mp, 0x48);
1004 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1005 p->unrec_mac_control_received += mib_read(mp, 0x50);
1006 p->fc_sent += mib_read(mp, 0x54);
1007 p->good_fc_received += mib_read(mp, 0x58);
1008 p->bad_fc_received += mib_read(mp, 0x5c);
1009 p->undersize_received += mib_read(mp, 0x60);
1010 p->fragments_received += mib_read(mp, 0x64);
1011 p->oversize_received += mib_read(mp, 0x68);
1012 p->jabber_received += mib_read(mp, 0x6c);
1013 p->mac_receive_error += mib_read(mp, 0x70);
1014 p->bad_crc_event += mib_read(mp, 0x74);
1015 p->collision += mib_read(mp, 0x78);
1016 p->late_collision += mib_read(mp, 0x7c);
d0412d96
JC		 1017}
1018
c9df406f
LB		 1019
1020/* ethtool ******************************************************************/
e5371493 1021struct mv643xx_eth_stats {
c9df406f
LB		 1022 char stat_string[ETH_GSTRING_LEN];
1023 int sizeof_stat;
16820054
LB		 1024 int netdev_off;
1025 int mp_off;
c9df406f
LB		 1026};
1027
16820054
LB		 1028#define SSTAT(m) \
1029 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1030 offsetof(struct net_device, stats.m), -1 }
1031
1032#define MIBSTAT(m) \
1033 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1034 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1035
1036static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1037 SSTAT(rx_packets),
1038 SSTAT(tx_packets),
1039 SSTAT(rx_bytes),
1040 SSTAT(tx_bytes),
1041 SSTAT(rx_errors),
1042 SSTAT(tx_errors),
1043 SSTAT(rx_dropped),
1044 SSTAT(tx_dropped),
1045 MIBSTAT(good_octets_received),
1046 MIBSTAT(bad_octets_received),
1047 MIBSTAT(internal_mac_transmit_err),
1048 MIBSTAT(good_frames_received),
1049 MIBSTAT(bad_frames_received),
1050 MIBSTAT(broadcast_frames_received),
1051 MIBSTAT(multicast_frames_received),
1052 MIBSTAT(frames_64_octets),
1053 MIBSTAT(frames_65_to_127_octets),
1054 MIBSTAT(frames_128_to_255_octets),
1055 MIBSTAT(frames_256_to_511_octets),
1056 MIBSTAT(frames_512_to_1023_octets),
1057 MIBSTAT(frames_1024_to_max_octets),
1058 MIBSTAT(good_octets_sent),
1059 MIBSTAT(good_frames_sent),
1060 MIBSTAT(excessive_collision),
1061 MIBSTAT(multicast_frames_sent),
1062 MIBSTAT(broadcast_frames_sent),
1063 MIBSTAT(unrec_mac_control_received),
1064 MIBSTAT(fc_sent),
1065 MIBSTAT(good_fc_received),
1066 MIBSTAT(bad_fc_received),
1067 MIBSTAT(undersize_received),
1068 MIBSTAT(fragments_received),
1069 MIBSTAT(oversize_received),
1070 MIBSTAT(jabber_received),
1071 MIBSTAT(mac_receive_error),
1072 MIBSTAT(bad_crc_event),
1073 MIBSTAT(collision),
1074 MIBSTAT(late_collision),
c9df406f
LB		 1075};
1076
e5371493 1077static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
d0412d96 1078{
e5371493 1079 struct mv643xx_eth_private *mp = netdev_priv(dev);
d0412d96
JC		 1080 int err;
1081
1082 spin_lock_irq(&mp->lock);
1083 err = mii_ethtool_gset(&mp->mii, cmd);
1084 spin_unlock_irq(&mp->lock);
1085
fc32b0e2
LB		 1086 /*
1087 * The MAC does not support 1000baseT_Half.
1088 */
d0412d96
JC		 1089 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1090 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1091
1092 return err;
1093}
1094
e5371493 1095static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4 1096{
e5371493 1097 struct mv643xx_eth_private *mp = netdev_priv(dev);
ab4384a6
DF		 1098 int err;
1099
fc32b0e2
LB		 1100 /*
1101 * The MAC does not support 1000baseT_Half.
1102 */
1103 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1104
c9df406f
LB		 1105 spin_lock_irq(&mp->lock);
1106 err = mii_ethtool_sset(&mp->mii, cmd);
1107 spin_unlock_irq(&mp->lock);
85cf572c 1108
c9df406f
LB		 1109 return err;
1110}
1da177e4 1111
fc32b0e2
LB		 1112static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1113 struct ethtool_drvinfo *drvinfo)
c9df406f 1114{
e5371493
LB		 1115 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1116 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
c9df406f 1117 strncpy(drvinfo->fw_version, "N/A", 32);
fc32b0e2 1118 strncpy(drvinfo->bus_info, "platform", 32);
16820054 1119 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
c9df406f 1120}
1da177e4 1121
fc32b0e2 1122static int mv643xx_eth_nway_reset(struct net_device *dev)
c9df406f 1123{
e5371493 1124 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1125
c9df406f
LB		 1126 return mii_nway_restart(&mp->mii);
1127}
1da177e4 1128
c9df406f
LB		 1129static u32 mv643xx_eth_get_link(struct net_device *dev)
1130{
e5371493 1131 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1132
c9df406f
LB		 1133 return mii_link_ok(&mp->mii);
1134}
1da177e4 1135
fc32b0e2
LB		 1136static void mv643xx_eth_get_strings(struct net_device *dev,
1137 uint32_t stringset, uint8_t *data)
c9df406f
LB		 1138{
1139 int i;
1da177e4 1140
fc32b0e2
LB		 1141 if (stringset == ETH_SS_STATS) {
1142 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
c9df406f 1143 memcpy(data + i * ETH_GSTRING_LEN,
16820054 1144 mv643xx_eth_stats[i].stat_string,
e5371493 1145 ETH_GSTRING_LEN);
c9df406f 1146 }
c9df406f
LB		 1147 }
1148}
1da177e4 1149
fc32b0e2
LB		 1150static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1151 struct ethtool_stats *stats,
1152 uint64_t *data)
c9df406f 1153{
fc32b0e2 1154 struct mv643xx_eth_private *mp = dev->priv;
c9df406f 1155 int i;
1da177e4 1156
fc32b0e2 1157 mib_counters_update(mp);
1da177e4 1158
16820054
LB		 1159 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1160 const struct mv643xx_eth_stats *stat;
1161 void *p;
1162
1163 stat = mv643xx_eth_stats + i;
1164
1165 if (stat->netdev_off >= 0)
1166 p = ((void *)mp->dev) + stat->netdev_off;
1167 else
1168 p = ((void *)mp) + stat->mp_off;
1169
1170 data[i] = (stat->sizeof_stat == 8) ?
1171 *(uint64_t *)p : *(uint32_t *)p;
1da177e4 1172 }
c9df406f 1173}
1da177e4 1174
fc32b0e2 1175static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
c9df406f 1176{
fc32b0e2 1177 if (sset == ETH_SS_STATS)
16820054 1178 return ARRAY_SIZE(mv643xx_eth_stats);
fc32b0e2
LB		 1179
1180 return -EOPNOTSUPP;
c9df406f 1181}
1da177e4 1182
e5371493 1183static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
fc32b0e2
LB		 1184 .get_settings = mv643xx_eth_get_settings,
1185 .set_settings = mv643xx_eth_set_settings,
1186 .get_drvinfo = mv643xx_eth_get_drvinfo,
1187 .nway_reset = mv643xx_eth_nway_reset,
1188 .get_link = mv643xx_eth_get_link,
c9df406f 1189 .set_sg = ethtool_op_set_sg,
fc32b0e2
LB		 1190 .get_strings = mv643xx_eth_get_strings,
1191 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
e5371493 1192 .get_sset_count = mv643xx_eth_get_sset_count,
c9df406f 1193};
1da177e4 1194
bea3348e 1195
c9df406f 1196/* address handling *********************************************************/
5daffe94 1197static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
c9df406f 1198{
c9df406f
LB		 1199 unsigned int mac_h;
1200 unsigned int mac_l;
1da177e4 1201
fc32b0e2
LB		 1202 mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num));
1203 mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num));
1da177e4 1204
5daffe94
LB		 1205 addr[0] = (mac_h >> 24) & 0xff;
1206 addr[1] = (mac_h >> 16) & 0xff;
1207 addr[2] = (mac_h >> 8) & 0xff;
1208 addr[3] = mac_h & 0xff;
1209 addr[4] = (mac_l >> 8) & 0xff;
1210 addr[5] = mac_l & 0xff;
c9df406f 1211}
1da177e4 1212
e5371493 1213static void init_mac_tables(struct mv643xx_eth_private *mp)
c9df406f 1214{
fc32b0e2 1215 int i;
1da177e4 1216
fc32b0e2
LB		 1217 for (i = 0; i < 0x100; i += 4) {
1218 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1219 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
c9df406f 1220 }
fc32b0e2
LB		 1221
1222 for (i = 0; i < 0x10; i += 4)
1223 wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
c9df406f 1224}
d0412d96 1225
e5371493 1226static void set_filter_table_entry(struct mv643xx_eth_private *mp,
fc32b0e2 1227 int table, unsigned char entry)
c9df406f
LB		 1228{
1229 unsigned int table_reg;
ab4384a6 1230
c9df406f 1231 /* Set "accepts frame bit" at specified table entry */
fc32b0e2
LB		 1232 table_reg = rdl(mp, table + (entry & 0xfc));
1233 table_reg |= 0x01 << (8 * (entry & 3));
1234 wrl(mp, table + (entry & 0xfc), table_reg);
1da177e4
LT		 1235}
1236
5daffe94 1237static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1da177e4 1238{
c9df406f
LB		 1239 unsigned int mac_h;
1240 unsigned int mac_l;
1241 int table;
1da177e4 1242
fc32b0e2
LB		 1243 mac_l = (addr[4] << 8) | addr[5];
1244 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
ff561eef 1245
fc32b0e2
LB		 1246 wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l);
1247 wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h);
1da177e4 1248
fc32b0e2 1249 table = UNICAST_TABLE(mp->port_num);
5daffe94 1250 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1da177e4
LT		 1251}
1252
fc32b0e2 1253static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1da177e4 1254{
e5371493 1255 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1256
fc32b0e2
LB		 1257 /* +2 is for the offset of the HW addr type */
1258 memcpy(dev->dev_addr, addr + 2, 6);
1259
cc9754b3
LB		 1260 init_mac_tables(mp);
1261 uc_addr_set(mp, dev->dev_addr);
1da177e4
LT		 1262
1263 return 0;
1264}
1265
69876569
LB		 1266static int addr_crc(unsigned char *addr)
1267{
1268 int crc = 0;
1269 int i;
1270
1271 for (i = 0; i < 6; i++) {
1272 int j;
1273
1274 crc = (crc ^ addr[i]) << 8;
1275 for (j = 7; j >= 0; j--) {
1276 if (crc & (0x100 << j))
1277 crc ^= 0x107 << j;
1278 }
1279 }
1280
1281 return crc;
1282}
1283
fc32b0e2 1284static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1da177e4 1285{
fc32b0e2
LB		 1286 struct mv643xx_eth_private *mp = netdev_priv(dev);
1287 u32 port_config;
1288 struct dev_addr_list *addr;
1289 int i;
c8aaea25 1290
fc32b0e2
LB		 1291 port_config = rdl(mp, PORT_CONFIG(mp->port_num));
1292 if (dev->flags & IFF_PROMISC)
1293 port_config |= UNICAST_PROMISCUOUS_MODE;
1294 else
1295 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1296 wrl(mp, PORT_CONFIG(mp->port_num), port_config);
1da177e4 1297
fc32b0e2
LB		 1298 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1299 int port_num = mp->port_num;
1300 u32 accept = 0x01010101;
c8aaea25 1301
fc32b0e2
LB		 1302 for (i = 0; i < 0x100; i += 4) {
1303 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1304 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
c9df406f
LB		 1305 }
1306 return;
1307 }
c8aaea25 1308
fc32b0e2
LB		 1309 for (i = 0; i < 0x100; i += 4) {
1310 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1311 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1da177e4
LT		 1312 }
1313
fc32b0e2
LB		 1314 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1315 u8 *a = addr->da_addr;
1316 int table;
324ff2c1 1317
fc32b0e2
LB		 1318 if (addr->da_addrlen != 6)
1319 continue;
1da177e4 1320
fc32b0e2
LB		 1321 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1322 table = SPECIAL_MCAST_TABLE(mp->port_num);
1323 set_filter_table_entry(mp, table, a[5]);
1324 } else {
1325 int crc = addr_crc(a);
1da177e4 1326
fc32b0e2
LB		 1327 table = OTHER_MCAST_TABLE(mp->port_num);
1328 set_filter_table_entry(mp, table, crc);
1329 }
1330 }
c9df406f 1331}
c8aaea25 1332
c8aaea25 1333
c9df406f 1334/* rx/tx queue initialisation ***********************************************/
64da80a2 1335static int rxq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1336{
64da80a2 1337 struct rx_queue *rxq = mp->rxq + index;
8a578111
LB		 1338 struct rx_desc *rx_desc;
1339 int size;
c9df406f
LB		 1340 int i;
1341
64da80a2
LB		 1342 rxq->index = index;
1343
8a578111
LB		 1344 rxq->rx_ring_size = mp->default_rx_ring_size;
1345
1346 rxq->rx_desc_count = 0;
1347 rxq->rx_curr_desc = 0;
1348 rxq->rx_used_desc = 0;
1349
1350 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1351
64da80a2 1352 if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size) {
8a578111
LB		 1353 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1354 mp->rx_desc_sram_size);
1355 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1356 } else {
1357 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1358 &rxq->rx_desc_dma,
1359 GFP_KERNEL);
f7ea3337
PJ		 1360 }
1361
8a578111
LB		 1362 if (rxq->rx_desc_area == NULL) {
1363 dev_printk(KERN_ERR, &mp->dev->dev,
1364 "can't allocate rx ring (%d bytes)\n", size);
1365 goto out;
1366 }
1367 memset(rxq->rx_desc_area, 0, size);
1da177e4 1368
8a578111
LB		 1369 rxq->rx_desc_area_size = size;
1370 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1371 GFP_KERNEL);
1372 if (rxq->rx_skb == NULL) {
1373 dev_printk(KERN_ERR, &mp->dev->dev,
1374 "can't allocate rx skb ring\n");
1375 goto out_free;
1376 }
1377
1378 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1379 for (i = 0; i < rxq->rx_ring_size; i++) {
1380 int nexti = (i + 1) % rxq->rx_ring_size;
1381 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1382 nexti * sizeof(struct rx_desc);
1383 }
1384
1385 init_timer(&rxq->rx_oom);
1386 rxq->rx_oom.data = (unsigned long)rxq;
1387 rxq->rx_oom.function = rxq_refill_timer_wrapper;
1388
1389 return 0;
1390
1391
1392out_free:
64da80a2 1393 if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size)
8a578111
LB		 1394 iounmap(rxq->rx_desc_area);
1395 else
1396 dma_free_coherent(NULL, size,
1397 rxq->rx_desc_area,
1398 rxq->rx_desc_dma);
1399
1400out:
1401 return -ENOMEM;
c9df406f 1402}
c8aaea25 1403
8a578111 1404static void rxq_deinit(struct rx_queue *rxq)
c9df406f 1405{
8a578111
LB		 1406 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1407 int i;
1408
1409 rxq_disable(rxq);
c8aaea25 1410
8a578111 1411 del_timer_sync(&rxq->rx_oom);
c9df406f 1412
8a578111
LB		 1413 for (i = 0; i < rxq->rx_ring_size; i++) {
1414 if (rxq->rx_skb[i]) {
1415 dev_kfree_skb(rxq->rx_skb[i]);
1416 rxq->rx_desc_count--;
1da177e4 1417 }
c8aaea25 1418 }
1da177e4 1419
8a578111
LB		 1420 if (rxq->rx_desc_count) {
1421 dev_printk(KERN_ERR, &mp->dev->dev,
1422 "error freeing rx ring -- %d skbs stuck\n",
1423 rxq->rx_desc_count);
1424 }
1425
64da80a2
LB		 1426 if (rxq->index == mp->rxq_primary &&
1427 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
8a578111 1428 iounmap(rxq->rx_desc_area);
c9df406f 1429 else
8a578111
LB		 1430 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1431 rxq->rx_desc_area, rxq->rx_desc_dma);
1432
1433 kfree(rxq->rx_skb);
c9df406f 1434}
1da177e4 1435
3d6b35bc 1436static int txq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1437{
3d6b35bc 1438 struct tx_queue *txq = mp->txq + index;
13d64285
LB		 1439 struct tx_desc *tx_desc;
1440 int size;
c9df406f 1441 int i;
1da177e4 1442
3d6b35bc
LB		 1443 txq->index = index;
1444
13d64285
LB		 1445 txq->tx_ring_size = mp->default_tx_ring_size;
1446
1447 txq->tx_desc_count = 0;
1448 txq->tx_curr_desc = 0;
1449 txq->tx_used_desc = 0;
1450
1451 size = txq->tx_ring_size * sizeof(struct tx_desc);
1452
3d6b35bc 1453 if (index == mp->txq_primary && size <= mp->tx_desc_sram_size) {
13d64285
LB		 1454 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1455 mp->tx_desc_sram_size);
1456 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1457 } else {
1458 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1459 &txq->tx_desc_dma,
1460 GFP_KERNEL);
1461 }
1462
1463 if (txq->tx_desc_area == NULL) {
1464 dev_printk(KERN_ERR, &mp->dev->dev,
1465 "can't allocate tx ring (%d bytes)\n", size);
1466 goto out;
c9df406f 1467 }
13d64285
LB		 1468 memset(txq->tx_desc_area, 0, size);
1469
1470 txq->tx_desc_area_size = size;
1471 txq->tx_skb = kmalloc(txq->tx_ring_size * sizeof(*txq->tx_skb),
1472 GFP_KERNEL);
1473 if (txq->tx_skb == NULL) {
1474 dev_printk(KERN_ERR, &mp->dev->dev,
1475 "can't allocate tx skb ring\n");
1476 goto out_free;
1477 }
1478
1479 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1480 for (i = 0; i < txq->tx_ring_size; i++) {
1481 int nexti = (i + 1) % txq->tx_ring_size;
1482 tx_desc[i].next_desc_ptr = txq->tx_desc_dma +
1483 nexti * sizeof(struct tx_desc);
1484 }
1485
1486 return 0;
1487
c9df406f 1488
13d64285 1489out_free:
3d6b35bc 1490 if (index == mp->txq_primary && size <= mp->tx_desc_sram_size)
13d64285
LB		 1491 iounmap(txq->tx_desc_area);
1492 else
1493 dma_free_coherent(NULL, size,
1494 txq->tx_desc_area,
1495 txq->tx_desc_dma);
c9df406f 1496
13d64285
LB		 1497out:
1498 return -ENOMEM;
c8aaea25 1499}
1da177e4 1500
13d64285 1501static void txq_reclaim(struct tx_queue *txq, int force)
c8aaea25 1502{
13d64285 1503 struct mv643xx_eth_private *mp = txq_to_mp(txq);
c8aaea25 1504 unsigned long flags;
1da177e4 1505
13d64285
LB		 1506 spin_lock_irqsave(&mp->lock, flags);
1507 while (txq->tx_desc_count > 0) {
1508 int tx_index;
1509 struct tx_desc *desc;
1510 u32 cmd_sts;
1511 struct sk_buff *skb;
1512 dma_addr_t addr;
1513 int count;
4d64e718 1514
13d64285
LB		 1515 tx_index = txq->tx_used_desc;
1516 desc = &txq->tx_desc_area[tx_index];
c9df406f 1517 cmd_sts = desc->cmd_sts;
4d64e718 1518
13d64285
LB		 1519 if (!force && (cmd_sts & BUFFER_OWNED_BY_DMA))
1520 break;
1da177e4 1521
13d64285
LB		 1522 txq->tx_used_desc = (tx_index + 1) % txq->tx_ring_size;
1523 txq->tx_desc_count--;
1da177e4 1524
c9df406f
LB		 1525 addr = desc->buf_ptr;
1526 count = desc->byte_cnt;
13d64285
LB		 1527 skb = txq->tx_skb[tx_index];
1528 txq->tx_skb[tx_index] = NULL;
c8aaea25 1529
cc9754b3 1530 if (cmd_sts & ERROR_SUMMARY) {
13d64285
LB		 1531 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
1532 mp->dev->stats.tx_errors++;
c9df406f 1533 }
1da177e4 1534
13d64285
LB		 1535 /*
1536 * Drop mp->lock while we free the skb.
1537 */
c9df406f 1538 spin_unlock_irqrestore(&mp->lock, flags);
1da177e4 1539
cc9754b3 1540 if (cmd_sts & TX_FIRST_DESC)
c9df406f
LB		 1541 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
1542 else
1543 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
c2e5b352 1544
c9df406f
LB		 1545 if (skb)
1546 dev_kfree_skb_irq(skb);
63c9e549 1547
13d64285 1548 spin_lock_irqsave(&mp->lock, flags);
c9df406f 1549 }
13d64285 1550 spin_unlock_irqrestore(&mp->lock, flags);
c9df406f 1551}
1da177e4 1552
13d64285 1553static void txq_deinit(struct tx_queue *txq)
c9df406f 1554{
13d64285 1555 struct mv643xx_eth_private *mp = txq_to_mp(txq);
fa3959f4 1556
13d64285
LB		 1557 txq_disable(txq);
1558 txq_reclaim(txq, 1);
1da177e4 1559
13d64285 1560 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1da177e4 1561
3d6b35bc
LB		 1562 if (txq->index == mp->txq_primary &&
1563 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
13d64285 1564 iounmap(txq->tx_desc_area);
c9df406f 1565 else
13d64285
LB		 1566 dma_free_coherent(NULL, txq->tx_desc_area_size,
1567 txq->tx_desc_area, txq->tx_desc_dma);
1568
1569 kfree(txq->tx_skb);
c9df406f 1570}
1da177e4 1571
1da177e4 1572
c9df406f 1573/* netdev ops and related ***************************************************/
fc32b0e2 1574static void update_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
c9df406f 1575{
13d64285
LB		 1576 u32 pscr_o;
1577 u32 pscr_n;
1da177e4 1578
13d64285 1579 pscr_o = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
63c9e549 1580
c9df406f 1581 /* clear speed, duplex and rx buffer size fields */
13d64285
LB		 1582 pscr_n = pscr_o & ~(SET_MII_SPEED_TO_100 |
1583 SET_GMII_SPEED_TO_1000 |
1584 SET_FULL_DUPLEX_MODE |
1585 MAX_RX_PACKET_MASK);
1da177e4 1586
fc32b0e2 1587 if (speed == SPEED_1000) {
13d64285
LB		 1588 pscr_n |= SET_GMII_SPEED_TO_1000 | MAX_RX_PACKET_9700BYTE;
1589 } else {
fc32b0e2 1590 if (speed == SPEED_100)
13d64285
LB		 1591 pscr_n |= SET_MII_SPEED_TO_100;
1592 pscr_n |= MAX_RX_PACKET_1522BYTE;
c9df406f 1593 }
1da177e4 1594
fc32b0e2 1595 if (duplex == DUPLEX_FULL)
13d64285
LB		 1596 pscr_n |= SET_FULL_DUPLEX_MODE;
1597
1598 if (pscr_n != pscr_o) {
1599 if ((pscr_o & SERIAL_PORT_ENABLE) == 0)
1600 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
c9df406f 1601 else {
3d6b35bc
LB		 1602 int i;
1603
1604 for (i = 0; i < 8; i++)
1605 if (mp->txq_mask & (1 << i))
1606 txq_disable(mp->txq + i);
1607
13d64285
LB		 1608 pscr_o &= ~SERIAL_PORT_ENABLE;
1609 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_o);
1610 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
1611 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
3d6b35bc
LB		 1612
1613 for (i = 0; i < 8; i++)
1614 if (mp->txq_mask & (1 << i))
1615 txq_enable(mp->txq + i);
c9df406f
LB		 1616 }
1617 }
1618}
84dd619e 1619
fc32b0e2 1620static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
c9df406f
LB		 1621{
1622 struct net_device *dev = (struct net_device *)dev_id;
e5371493 1623 struct mv643xx_eth_private *mp = netdev_priv(dev);
fc32b0e2
LB		 1624 u32 int_cause;
1625 u32 int_cause_ext;
226bb6b7 1626 u32 txq_active;
ce4e2e45 1627
226bb6b7
LB		 1628 int_cause = rdl(mp, INT_CAUSE(mp->port_num)) &
1629 (INT_TX_END | INT_RX | INT_EXT);
fc32b0e2
LB		 1630 if (int_cause == 0)
1631 return IRQ_NONE;
1632
1633 int_cause_ext = 0;
cc9754b3 1634 if (int_cause & INT_EXT) {
13d64285 1635 int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num))
073a345c 1636 & (INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
13d64285 1637 wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext);
c9df406f 1638 }
1da177e4 1639
fc32b0e2 1640 if (int_cause_ext & (INT_EXT_PHY | INT_EXT_LINK)) {
c9df406f 1641 if (mii_link_ok(&mp->mii)) {
13d64285 1642 struct ethtool_cmd cmd;
3d6b35bc 1643 int i;
13d64285 1644
c9df406f 1645 mii_ethtool_gset(&mp->mii, &cmd);
fc32b0e2 1646 update_pscr(mp, cmd.speed, cmd.duplex);
3d6b35bc
LB		 1647 for (i = 0; i < 8; i++)
1648 if (mp->txq_mask & (1 << i))
1649 txq_enable(mp->txq + i);
1650
c9df406f
LB		 1651 if (!netif_carrier_ok(dev)) {
1652 netif_carrier_on(dev);
3d6b35bc 1653 __txq_maybe_wake(mp->txq + mp->txq_primary);
c9df406f
LB		 1654 }
1655 } else if (netif_carrier_ok(dev)) {
1656 netif_stop_queue(dev);
1657 netif_carrier_off(dev);
1658 }
1659 }
1da177e4 1660
64da80a2
LB		 1661 /*
1662 * RxBuffer or RxError set for any of the 8 queues?
1663 */
e5371493 1664#ifdef MV643XX_ETH_NAPI
cc9754b3 1665 if (int_cause & INT_RX) {
13d64285 1666 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
13d64285 1667 rdl(mp, INT_MASK(mp->port_num));
1da177e4 1668
c9df406f 1669 netif_rx_schedule(dev, &mp->napi);
84dd619e 1670 }
c9df406f 1671#else
64da80a2
LB		 1672 if (int_cause & INT_RX) {
1673 int i;
1674
1675 for (i = 7; i >= 0; i--)
1676 if (mp->rxq_mask & (1 << i))
1677 rxq_process(mp->rxq + i, INT_MAX);
1678 }
c9df406f 1679#endif
fc32b0e2 1680
226bb6b7
LB		 1681 txq_active = rdl(mp, TXQ_COMMAND(mp->port_num));
1682
3d6b35bc
LB		 1683 /*
1684 * TxBuffer or TxError set for any of the 8 queues?
1685 */
13d64285 1686 if (int_cause_ext & INT_EXT_TX) {
3d6b35bc
LB		 1687 int i;
1688
1689 for (i = 0; i < 8; i++)
1690 if (mp->txq_mask & (1 << i))
1691 txq_reclaim(mp->txq + i, 0);
226bb6b7 1692 }
3d6b35bc 1693
226bb6b7
LB		 1694 /*
1695 * Any TxEnd interrupts?
1696 */
1697 if (int_cause & INT_TX_END) {
1698 int i;
1699
1700 wrl(mp, INT_CAUSE(mp->port_num), ~(int_cause & INT_TX_END));
1701 for (i = 0; i < 8; i++) {
1702 struct tx_queue *txq = mp->txq + i;
1703 if (txq->tx_desc_count && !((txq_active >> i) & 1))
1704 txq_enable(txq);
1705 }
1706 }
1707
1708 /*
1709 * Enough space again in the primary TX queue for a full packet?
1710 */
1711 if (int_cause_ext & INT_EXT_TX) {
1712 struct tx_queue *txq = mp->txq + mp->txq_primary;
1713 __txq_maybe_wake(txq);
13d64285 1714 }
1da177e4 1715
c9df406f 1716 return IRQ_HANDLED;
1da177e4
LT		 1717}
1718
e5371493 1719static void phy_reset(struct mv643xx_eth_private *mp)
1da177e4 1720{
fc32b0e2 1721 unsigned int data;
1da177e4 1722
fc32b0e2
LB		 1723 smi_reg_read(mp, mp->phy_addr, 0, &data);
1724 data |= 0x8000;
1725 smi_reg_write(mp, mp->phy_addr, 0, data);
1da177e4 1726
c9df406f
LB		 1727 do {
1728 udelay(1);
fc32b0e2
LB		 1729 smi_reg_read(mp, mp->phy_addr, 0, &data);
1730 } while (data & 0x8000);
1da177e4
LT		 1731}
1732
fc32b0e2 1733static void port_start(struct mv643xx_eth_private *mp)
1da177e4 1734{
d0412d96
JC		 1735 u32 pscr;
1736 struct ethtool_cmd ethtool_cmd;
8a578111 1737 int i;
1da177e4 1738
8a578111
LB		 1739 /*
1740 * Configure basic link parameters.
1741 */
1742 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1743 pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS);
1744 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1745 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1746 DISABLE_AUTO_NEG_SPEED_GMII |
1747 DISABLE_AUTO_NEG_FOR_DUPLEX |
1748 DO_NOT_FORCE_LINK_FAIL |
1749 SERIAL_PORT_CONTROL_RESERVED;
1750 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1751 pscr |= SERIAL_PORT_ENABLE;
1752 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1da177e4 1753
8a578111
LB		 1754 wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1755
fc32b0e2 1756 mv643xx_eth_get_settings(mp->dev, &ethtool_cmd);
8a578111 1757 phy_reset(mp);
fc32b0e2 1758 mv643xx_eth_set_settings(mp->dev, &ethtool_cmd);
1da177e4 1759
13d64285
LB		 1760 /*
1761 * Configure TX path and queues.
1762 */
89df5fdc 1763 tx_set_rate(mp, 1000000000, 16777216);
3d6b35bc
LB		 1764 for (i = 0; i < 8; i++) {
1765 struct tx_queue *txq = mp->txq + i;
1766 int off = TXQ_CURRENT_DESC_PTR(mp->port_num, i);
13d64285
LB		 1767 u32 addr;
1768
3d6b35bc
LB		 1769 if ((mp->txq_mask & (1 << i)) == 0)
1770 continue;
1771
13d64285
LB		 1772 addr = (u32)txq->tx_desc_dma;
1773 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
1774 wrl(mp, off, addr);
89df5fdc
LB		 1775
1776 txq_set_rate(txq, 1000000000, 16777216);
1777 txq_set_fixed_prio_mode(txq);
13d64285
LB		 1778 }
1779
fc32b0e2
LB		 1780 /*
1781 * Add configured unicast address to address filter table.
1782 */
1783 uc_addr_set(mp, mp->dev->dev_addr);
1da177e4 1784
d9a073ea
LB		 1785 /*
1786 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
1787 * frames to RX queue #0.
1788 */
8a578111 1789 wrl(mp, PORT_CONFIG(mp->port_num), 0x00000000);
01999873 1790
376489a2
LB		 1791 /*
1792 * Treat BPDUs as normal multicasts, and disable partition mode.
1793 */
8a578111 1794 wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000);
01999873 1795
8a578111 1796 /*
64da80a2 1797 * Enable the receive queues.
8a578111 1798 */
64da80a2
LB		 1799 for (i = 0; i < 8; i++) {
1800 struct rx_queue *rxq = mp->rxq + i;
1801 int off = RXQ_CURRENT_DESC_PTR(mp->port_num, i);
8a578111 1802 u32 addr;
1da177e4 1803
64da80a2
LB		 1804 if ((mp->rxq_mask & (1 << i)) == 0)
1805 continue;
1806
8a578111
LB		 1807 addr = (u32)rxq->rx_desc_dma;
1808 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
1809 wrl(mp, off, addr);
1da177e4 1810
8a578111
LB		 1811 rxq_enable(rxq);
1812 }
1da177e4
LT		 1813}
1814
ffd86bbe 1815static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1da177e4 1816{
c9df406f 1817 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1da177e4 1818
fc32b0e2
LB		 1819 if (coal > 0x3fff)
1820 coal = 0x3fff;
1821
1822 wrl(mp, SDMA_CONFIG(mp->port_num),
c9df406f 1823 ((coal & 0x3fff) << 8) |
fc32b0e2 1824 (rdl(mp, SDMA_CONFIG(mp->port_num))
c9df406f 1825 & 0xffc000ff));
1da177e4
LT		 1826}
1827
ffd86bbe 1828static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1da177e4 1829{
c9df406f 1830 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1da177e4 1831
fc32b0e2
LB		 1832 if (coal > 0x3fff)
1833 coal = 0x3fff;
1834 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4);
16e03018
DF		 1835}
1836
c9df406f 1837static int mv643xx_eth_open(struct net_device *dev)
16e03018 1838{
e5371493 1839 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 1840 int err;
64da80a2 1841 int i;
16e03018 1842
fc32b0e2
LB		 1843 wrl(mp, INT_CAUSE(mp->port_num), 0);
1844 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
1845 rdl(mp, INT_CAUSE_EXT(mp->port_num));
c9df406f 1846
fc32b0e2
LB		 1847 err = request_irq(dev->irq, mv643xx_eth_irq,
1848 IRQF_SHARED | IRQF_SAMPLE_RANDOM,
1849 dev->name, dev);
c9df406f 1850 if (err) {
fc32b0e2 1851 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
c9df406f 1852 return -EAGAIN;
16e03018
DF		 1853 }
1854
fc32b0e2 1855 init_mac_tables(mp);
16e03018 1856
64da80a2
LB		 1857 for (i = 0; i < 8; i++) {
1858 if ((mp->rxq_mask & (1 << i)) == 0)
1859 continue;
1860
1861 err = rxq_init(mp, i);
1862 if (err) {
1863 while (--i >= 0)
1864 if (mp->rxq_mask & (1 << i))
1865 rxq_deinit(mp->rxq + i);
1866 goto out;
1867 }
1868
1869 rxq_refill(mp->rxq + i);
1870 }
8a578111 1871
3d6b35bc
LB		 1872 for (i = 0; i < 8; i++) {
1873 if ((mp->txq_mask & (1 << i)) == 0)
1874 continue;
1875
1876 err = txq_init(mp, i);
1877 if (err) {
1878 while (--i >= 0)
1879 if (mp->txq_mask & (1 << i))
1880 txq_deinit(mp->txq + i);
1881 goto out_free;
1882 }
1883 }
16e03018 1884
e5371493 1885#ifdef MV643XX_ETH_NAPI
c9df406f
LB		 1886 napi_enable(&mp->napi);
1887#endif
16e03018 1888
fc32b0e2 1889 port_start(mp);
16e03018 1890
ffd86bbe
LB		 1891 set_rx_coal(mp, 0);
1892 set_tx_coal(mp, 0);
16e03018 1893
fc32b0e2
LB		 1894 wrl(mp, INT_MASK_EXT(mp->port_num),
1895 INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
16e03018 1896
226bb6b7 1897 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
16e03018 1898
c9df406f
LB		 1899 return 0;
1900
13d64285 1901
fc32b0e2 1902out_free:
64da80a2
LB		 1903 for (i = 0; i < 8; i++)
1904 if (mp->rxq_mask & (1 << i))
1905 rxq_deinit(mp->rxq + i);
fc32b0e2 1906out:
c9df406f
LB		 1907 free_irq(dev->irq, dev);
1908
1909 return err;
16e03018
DF		 1910}
1911
e5371493 1912static void port_reset(struct mv643xx_eth_private *mp)
1da177e4 1913{
fc32b0e2 1914 unsigned int data;
64da80a2 1915 int i;
1da177e4 1916
64da80a2
LB		 1917 for (i = 0; i < 8; i++) {
1918 if (mp->rxq_mask & (1 << i))
1919 rxq_disable(mp->rxq + i);
3d6b35bc
LB		 1920 if (mp->txq_mask & (1 << i))
1921 txq_disable(mp->txq + i);
64da80a2 1922 }
13d64285
LB		 1923 while (!(rdl(mp, PORT_STATUS(mp->port_num)) & TX_FIFO_EMPTY))
1924 udelay(10);
1da177e4 1925
c9df406f 1926 /* Reset the Enable bit in the Configuration Register */
fc32b0e2
LB		 1927 data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1928 data &= ~(SERIAL_PORT_ENABLE |
1929 DO_NOT_FORCE_LINK_FAIL |
1930 FORCE_LINK_PASS);
1931 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data);
1da177e4
LT		 1932}
1933
c9df406f 1934static int mv643xx_eth_stop(struct net_device *dev)
1da177e4 1935{
e5371493 1936 struct mv643xx_eth_private *mp = netdev_priv(dev);
64da80a2 1937 int i;
1da177e4 1938
fc32b0e2
LB		 1939 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
1940 rdl(mp, INT_MASK(mp->port_num));
1da177e4 1941
e5371493 1942#ifdef MV643XX_ETH_NAPI
c9df406f
LB		 1943 napi_disable(&mp->napi);
1944#endif
1945 netif_carrier_off(dev);
1946 netif_stop_queue(dev);
1da177e4 1947
fc32b0e2
LB		 1948 free_irq(dev->irq, dev);
1949
cc9754b3 1950 port_reset(mp);
fc32b0e2 1951 mib_counters_update(mp);
1da177e4 1952
64da80a2
LB		 1953 for (i = 0; i < 8; i++) {
1954 if (mp->rxq_mask & (1 << i))
1955 rxq_deinit(mp->rxq + i);
3d6b35bc
LB		 1956 if (mp->txq_mask & (1 << i))
1957 txq_deinit(mp->txq + i);
64da80a2 1958 }
1da177e4 1959
c9df406f 1960 return 0;
1da177e4
LT		 1961}
1962
fc32b0e2 1963static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1da177e4 1964{
e5371493 1965 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1966
c9df406f 1967 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
1da177e4
LT		 1968}
1969
c9df406f 1970static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 1971{
89df5fdc
LB		 1972 struct mv643xx_eth_private *mp = netdev_priv(dev);
1973
fc32b0e2 1974 if (new_mtu < 64 || new_mtu > 9500)
c9df406f 1975 return -EINVAL;
1da177e4 1976
c9df406f 1977 dev->mtu = new_mtu;
89df5fdc
LB		 1978 tx_set_rate(mp, 1000000000, 16777216);
1979
c9df406f
LB		 1980 if (!netif_running(dev))
1981 return 0;
1da177e4 1982
c9df406f
LB		 1983 /*
1984 * Stop and then re-open the interface. This will allocate RX
1985 * skbs of the new MTU.
1986 * There is a possible danger that the open will not succeed,
fc32b0e2 1987 * due to memory being full.
c9df406f
LB		 1988 */
1989 mv643xx_eth_stop(dev);
1990 if (mv643xx_eth_open(dev)) {
fc32b0e2
LB		 1991 dev_printk(KERN_ERR, &dev->dev,
1992 "fatal error on re-opening device after "
1993 "MTU change\n");
c9df406f
LB		 1994 }
1995
1996 return 0;
1da177e4
LT		 1997}
1998
fc32b0e2 1999static void tx_timeout_task(struct work_struct *ugly)
1da177e4 2000{
fc32b0e2 2001 struct mv643xx_eth_private *mp;
1da177e4 2002
fc32b0e2
LB		 2003 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2004 if (netif_running(mp->dev)) {
2005 netif_stop_queue(mp->dev);
c9df406f 2006
fc32b0e2
LB		 2007 port_reset(mp);
2008 port_start(mp);
c9df406f 2009
3d6b35bc 2010 __txq_maybe_wake(mp->txq + mp->txq_primary);
fc32b0e2 2011 }
c9df406f
LB		 2012}
2013
c9df406f 2014static void mv643xx_eth_tx_timeout(struct net_device *dev)
1da177e4 2015{
e5371493 2016 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2017
fc32b0e2 2018 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
d0412d96 2019
c9df406f 2020 schedule_work(&mp->tx_timeout_task);
1da177e4
LT		 2021}
2022
c9df406f 2023#ifdef CONFIG_NET_POLL_CONTROLLER
fc32b0e2 2024static void mv643xx_eth_netpoll(struct net_device *dev)
9f8dd319 2025{
fc32b0e2 2026 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2027
fc32b0e2
LB		 2028 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2029 rdl(mp, INT_MASK(mp->port_num));
c9df406f 2030
fc32b0e2 2031 mv643xx_eth_irq(dev->irq, dev);
c9df406f 2032
226bb6b7 2033 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_CAUSE_EXT);
9f8dd319 2034}
c9df406f 2035#endif
9f8dd319 2036
fc32b0e2 2037static int mv643xx_eth_mdio_read(struct net_device *dev, int addr, int reg)
9f8dd319 2038{
e5371493 2039 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f
LB		 2040 int val;
2041
fc32b0e2
LB		 2042 smi_reg_read(mp, addr, reg, &val);
2043
c9df406f 2044 return val;
9f8dd319
DF		 2045}
2046
fc32b0e2 2047static void mv643xx_eth_mdio_write(struct net_device *dev, int addr, int reg, int val)
9f8dd319 2048{
e5371493 2049 struct mv643xx_eth_private *mp = netdev_priv(dev);
fc32b0e2 2050 smi_reg_write(mp, addr, reg, val);
c9df406f 2051}
9f8dd319 2052
9f8dd319 2053
c9df406f 2054/* platform glue ************************************************************/
e5371493
LB		 2055static void
2056mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2057 struct mbus_dram_target_info *dram)
c9df406f 2058{
cc9754b3 2059 void __iomem *base = msp->base;
c9df406f
LB		 2060 u32 win_enable;
2061 u32 win_protect;
2062 int i;
9f8dd319 2063
c9df406f
LB		 2064 for (i = 0; i < 6; i++) {
2065 writel(0, base + WINDOW_BASE(i));
2066 writel(0, base + WINDOW_SIZE(i));
2067 if (i < 4)
2068 writel(0, base + WINDOW_REMAP_HIGH(i));
9f8dd319
DF		 2069 }
2070
c9df406f
LB		 2071 win_enable = 0x3f;
2072 win_protect = 0;
2073
2074 for (i = 0; i < dram->num_cs; i++) {
2075 struct mbus_dram_window *cs = dram->cs + i;
2076
2077 writel((cs->base & 0xffff0000) |
2078 (cs->mbus_attr << 8) |
2079 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2080 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2081
2082 win_enable &= ~(1 << i);
2083 win_protect |= 3 << (2 * i);
2084 }
2085
2086 writel(win_enable, base + WINDOW_BAR_ENABLE);
2087 msp->win_protect = win_protect;
9f8dd319
DF		 2088}
2089
c9df406f 2090static int mv643xx_eth_shared_probe(struct platform_device *pdev)
9f8dd319 2091{
e5371493 2092 static int mv643xx_eth_version_printed = 0;
c9df406f 2093 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
e5371493 2094 struct mv643xx_eth_shared_private *msp;
c9df406f
LB		 2095 struct resource *res;
2096 int ret;
9f8dd319 2097
e5371493 2098 if (!mv643xx_eth_version_printed++)
c9df406f 2099 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
9f8dd319 2100
c9df406f
LB		 2101 ret = -EINVAL;
2102 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2103 if (res == NULL)
2104 goto out;
9f8dd319 2105
c9df406f
LB		 2106 ret = -ENOMEM;
2107 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2108 if (msp == NULL)
2109 goto out;
2110 memset(msp, 0, sizeof(*msp));
2111
cc9754b3
LB		 2112 msp->base = ioremap(res->start, res->end - res->start + 1);
2113 if (msp->base == NULL)
c9df406f
LB		 2114 goto out_free;
2115
2116 spin_lock_init(&msp->phy_lock);
c9df406f
LB		 2117
2118 /*
2119 * (Re-)program MBUS remapping windows if we are asked to.
2120 */
2121 if (pd != NULL && pd->dram != NULL)
2122 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2123
fc32b0e2
LB		 2124 /*
2125 * Detect hardware parameters.
2126 */
2127 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
2128
2129 platform_set_drvdata(pdev, msp);
2130
c9df406f
LB		 2131 return 0;
2132
2133out_free:
2134 kfree(msp);
2135out:
2136 return ret;
2137}
2138
2139static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2140{
e5371493 2141 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
c9df406f 2142
cc9754b3 2143 iounmap(msp->base);
c9df406f
LB		 2144 kfree(msp);
2145
2146 return 0;
9f8dd319
DF		 2147}
2148
c9df406f 2149static struct platform_driver mv643xx_eth_shared_driver = {
fc32b0e2
LB		 2150 .probe = mv643xx_eth_shared_probe,
2151 .remove = mv643xx_eth_shared_remove,
c9df406f 2152 .driver = {
fc32b0e2 2153 .name = MV643XX_ETH_SHARED_NAME,
c9df406f
LB		 2154 .owner = THIS_MODULE,
2155 },
2156};
2157
e5371493 2158static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
1da177e4 2159{
c9df406f 2160 int addr_shift = 5 * mp->port_num;
fc32b0e2 2161 u32 data;
1da177e4 2162
fc32b0e2
LB		 2163 data = rdl(mp, PHY_ADDR);
2164 data &= ~(0x1f << addr_shift);
2165 data |= (phy_addr & 0x1f) << addr_shift;
2166 wrl(mp, PHY_ADDR, data);
1da177e4
LT		 2167}
2168
e5371493 2169static int phy_addr_get(struct mv643xx_eth_private *mp)
1da177e4 2170{
fc32b0e2
LB		 2171 unsigned int data;
2172
2173 data = rdl(mp, PHY_ADDR);
2174
2175 return (data >> (5 * mp->port_num)) & 0x1f;
2176}
2177
2178static void set_params(struct mv643xx_eth_private *mp,
2179 struct mv643xx_eth_platform_data *pd)
2180{
2181 struct net_device *dev = mp->dev;
2182
2183 if (is_valid_ether_addr(pd->mac_addr))
2184 memcpy(dev->dev_addr, pd->mac_addr, 6);
2185 else
2186 uc_addr_get(mp, dev->dev_addr);
2187
2188 if (pd->phy_addr == -1) {
2189 mp->shared_smi = NULL;
2190 mp->phy_addr = -1;
2191 } else {
2192 mp->shared_smi = mp->shared;
2193 if (pd->shared_smi != NULL)
2194 mp->shared_smi = platform_get_drvdata(pd->shared_smi);
2195
2196 if (pd->force_phy_addr || pd->phy_addr) {
2197 mp->phy_addr = pd->phy_addr & 0x3f;
2198 phy_addr_set(mp, mp->phy_addr);
2199 } else {
2200 mp->phy_addr = phy_addr_get(mp);
2201 }
2202 }
1da177e4 2203
fc32b0e2
LB		 2204 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2205 if (pd->rx_queue_size)
2206 mp->default_rx_ring_size = pd->rx_queue_size;
2207 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2208 mp->rx_desc_sram_size = pd->rx_sram_size;
1da177e4 2209
64da80a2
LB		 2210 if (pd->rx_queue_mask)
2211 mp->rxq_mask = pd->rx_queue_mask;
2212 else
2213 mp->rxq_mask = 0x01;
2214 mp->rxq_primary = fls(mp->rxq_mask) - 1;
2215
fc32b0e2
LB		 2216 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2217 if (pd->tx_queue_size)
2218 mp->default_tx_ring_size = pd->tx_queue_size;
2219 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2220 mp->tx_desc_sram_size = pd->tx_sram_size;
3d6b35bc
LB		 2221
2222 if (pd->tx_queue_mask)
2223 mp->txq_mask = pd->tx_queue_mask;
2224 else
2225 mp->txq_mask = 0x01;
2226 mp->txq_primary = fls(mp->txq_mask) - 1;
1da177e4
LT		 2227}
2228
e5371493 2229static int phy_detect(struct mv643xx_eth_private *mp)
1da177e4 2230{
fc32b0e2
LB		 2231 unsigned int data;
2232 unsigned int data2;
2233
2234 smi_reg_read(mp, mp->phy_addr, 0, &data);
2235 smi_reg_write(mp, mp->phy_addr, 0, data ^ 0x1000);
1da177e4 2236
fc32b0e2
LB		 2237 smi_reg_read(mp, mp->phy_addr, 0, &data2);
2238 if (((data ^ data2) & 0x1000) == 0)
2239 return -ENODEV;
1da177e4 2240
fc32b0e2 2241 smi_reg_write(mp, mp->phy_addr, 0, data);
1da177e4 2242
c9df406f 2243 return 0;
1da177e4
LT		 2244}
2245
fc32b0e2
LB		 2246static int phy_init(struct mv643xx_eth_private *mp,
2247 struct mv643xx_eth_platform_data *pd)
c28a4f89 2248{
fc32b0e2
LB		 2249 struct ethtool_cmd cmd;
2250 int err;
c28a4f89 2251
fc32b0e2
LB		 2252 err = phy_detect(mp);
2253 if (err) {
2254 dev_printk(KERN_INFO, &mp->dev->dev,
2255 "no PHY detected at addr %d\n", mp->phy_addr);
2256 return err;
2257 }
2258 phy_reset(mp);
2259
2260 mp->mii.phy_id = mp->phy_addr;
2261 mp->mii.phy_id_mask = 0x3f;
2262 mp->mii.reg_num_mask = 0x1f;
2263 mp->mii.dev = mp->dev;
2264 mp->mii.mdio_read = mv643xx_eth_mdio_read;
2265 mp->mii.mdio_write = mv643xx_eth_mdio_write;
c28a4f89 2266
fc32b0e2 2267 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
c9df406f 2268
fc32b0e2
LB		 2269 memset(&cmd, 0, sizeof(cmd));
2270
2271 cmd.port = PORT_MII;
2272 cmd.transceiver = XCVR_INTERNAL;
2273 cmd.phy_address = mp->phy_addr;
2274 if (pd->speed == 0) {
2275 cmd.autoneg = AUTONEG_ENABLE;
2276 cmd.speed = SPEED_100;
2277 cmd.advertising = ADVERTISED_10baseT_Half |
2278 ADVERTISED_10baseT_Full |
2279 ADVERTISED_100baseT_Half |
2280 ADVERTISED_100baseT_Full;
c9df406f 2281 if (mp->mii.supports_gmii)
fc32b0e2 2282 cmd.advertising |= ADVERTISED_1000baseT_Full;
c9df406f 2283 } else {
fc32b0e2
LB		 2284 cmd.autoneg = AUTONEG_DISABLE;
2285 cmd.speed = pd->speed;
2286 cmd.duplex = pd->duplex;
c9df406f 2287 }
fc32b0e2
LB		 2288
2289 update_pscr(mp, cmd.speed, cmd.duplex);
2290 mv643xx_eth_set_settings(mp->dev, &cmd);
2291
2292 return 0;
c28a4f89
JC		 2293}
2294
c9df406f 2295static int mv643xx_eth_probe(struct platform_device *pdev)
1da177e4 2296{
c9df406f 2297 struct mv643xx_eth_platform_data *pd;
e5371493 2298 struct mv643xx_eth_private *mp;
c9df406f 2299 struct net_device *dev;
c9df406f 2300 struct resource *res;
c9df406f 2301 DECLARE_MAC_BUF(mac);
fc32b0e2 2302 int err;
1da177e4 2303
c9df406f
LB		 2304 pd = pdev->dev.platform_data;
2305 if (pd == NULL) {
fc32b0e2
LB		 2306 dev_printk(KERN_ERR, &pdev->dev,
2307 "no mv643xx_eth_platform_data\n");
c9df406f
LB		 2308 return -ENODEV;
2309 }
1da177e4 2310
c9df406f 2311 if (pd->shared == NULL) {
fc32b0e2
LB		 2312 dev_printk(KERN_ERR, &pdev->dev,
2313 "no mv643xx_eth_platform_data->shared\n");
c9df406f
LB		 2314 return -ENODEV;
2315 }
8f518703 2316
e5371493 2317 dev = alloc_etherdev(sizeof(struct mv643xx_eth_private));
c9df406f
LB		 2318 if (!dev)
2319 return -ENOMEM;
1da177e4 2320
c9df406f 2321 mp = netdev_priv(dev);
fc32b0e2
LB		 2322 platform_set_drvdata(pdev, mp);
2323
2324 mp->shared = platform_get_drvdata(pd->shared);
2325 mp->port_num = pd->port_number;
2326
c9df406f 2327 mp->dev = dev;
e5371493
LB		 2328#ifdef MV643XX_ETH_NAPI
2329 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 64);
c9df406f 2330#endif
1da177e4 2331
fc32b0e2
LB		 2332 set_params(mp, pd);
2333
2334 spin_lock_init(&mp->lock);
2335
2336 mib_counters_clear(mp);
2337 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2338
2339 err = phy_init(mp, pd);
2340 if (err)
2341 goto out;
2342 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2343
2344
c9df406f
LB		 2345 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2346 BUG_ON(!res);
2347 dev->irq = res->start;
1da177e4 2348
fc32b0e2 2349 dev->hard_start_xmit = mv643xx_eth_xmit;
c9df406f
LB		 2350 dev->open = mv643xx_eth_open;
2351 dev->stop = mv643xx_eth_stop;
c9df406f 2352 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
fc32b0e2
LB		 2353 dev->set_mac_address = mv643xx_eth_set_mac_address;
2354 dev->do_ioctl = mv643xx_eth_ioctl;
2355 dev->change_mtu = mv643xx_eth_change_mtu;
c9df406f 2356 dev->tx_timeout = mv643xx_eth_tx_timeout;
c9df406f 2357#ifdef CONFIG_NET_POLL_CONTROLLER
e5371493 2358 dev->poll_controller = mv643xx_eth_netpoll;
c9df406f 2359#endif
c9df406f
LB		 2360 dev->watchdog_timeo = 2 * HZ;
2361 dev->base_addr = 0;
1da177e4 2362
e5371493 2363#ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
b4de9051 2364 /*
c9df406f
LB		 2365 * Zero copy can only work if we use Discovery II memory. Else, we will
2366 * have to map the buffers to ISA memory which is only 16 MB
b4de9051 2367 */
c9df406f 2368 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
c9df406f 2369#endif
1da177e4 2370
fc32b0e2 2371 SET_NETDEV_DEV(dev, &pdev->dev);
8f518703 2372
c9df406f 2373 if (mp->shared->win_protect)
fc32b0e2 2374 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
1da177e4 2375
c9df406f
LB		 2376 err = register_netdev(dev);
2377 if (err)
2378 goto out;
1da177e4 2379
fc32b0e2
LB		 2380 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %s\n",
2381 mp->port_num, print_mac(mac, dev->dev_addr));
1da177e4 2382
c9df406f 2383 if (dev->features & NETIF_F_SG)
fc32b0e2 2384 dev_printk(KERN_NOTICE, &dev->dev, "scatter/gather enabled\n");
1da177e4 2385
c9df406f 2386 if (dev->features & NETIF_F_IP_CSUM)
fc32b0e2 2387 dev_printk(KERN_NOTICE, &dev->dev, "tx checksum offload\n");
1da177e4 2388
e5371493 2389#ifdef MV643XX_ETH_NAPI
fc32b0e2 2390 dev_printk(KERN_NOTICE, &dev->dev, "napi enabled\n");
c9df406f 2391#endif
1da177e4 2392
13d64285 2393 if (mp->tx_desc_sram_size > 0)
fc32b0e2 2394 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
1da177e4 2395
c9df406f 2396 return 0;
1da177e4 2397
c9df406f
LB		 2398out:
2399 free_netdev(dev);
1da177e4 2400
c9df406f 2401 return err;
1da177e4
LT		 2402}
2403
c9df406f 2404static int mv643xx_eth_remove(struct platform_device *pdev)
1da177e4 2405{
fc32b0e2 2406 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
1da177e4 2407
fc32b0e2 2408 unregister_netdev(mp->dev);
c9df406f 2409 flush_scheduled_work();
fc32b0e2 2410 free_netdev(mp->dev);
c9df406f 2411
c9df406f 2412 platform_set_drvdata(pdev, NULL);
fc32b0e2 2413
c9df406f 2414 return 0;
1da177e4
LT		 2415}
2416
c9df406f 2417static void mv643xx_eth_shutdown(struct platform_device *pdev)
d0412d96 2418{
fc32b0e2 2419 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
d0412d96 2420
c9df406f 2421 /* Mask all interrupts on ethernet port */
fc32b0e2
LB		 2422 wrl(mp, INT_MASK(mp->port_num), 0);
2423 rdl(mp, INT_MASK(mp->port_num));
c9df406f 2424
fc32b0e2
LB		 2425 if (netif_running(mp->dev))
2426 port_reset(mp);
d0412d96
JC		 2427}
2428
c9df406f 2429static struct platform_driver mv643xx_eth_driver = {
fc32b0e2
LB		 2430 .probe = mv643xx_eth_probe,
2431 .remove = mv643xx_eth_remove,
2432 .shutdown = mv643xx_eth_shutdown,
c9df406f 2433 .driver = {
fc32b0e2 2434 .name = MV643XX_ETH_NAME,
c9df406f
LB		 2435 .owner = THIS_MODULE,
2436 },
2437};
2438
e5371493 2439static int __init mv643xx_eth_init_module(void)
d0412d96 2440{
c9df406f 2441 int rc;
d0412d96 2442
c9df406f
LB		 2443 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2444 if (!rc) {
2445 rc = platform_driver_register(&mv643xx_eth_driver);
2446 if (rc)
2447 platform_driver_unregister(&mv643xx_eth_shared_driver);
2448 }
fc32b0e2 2449
c9df406f 2450 return rc;
d0412d96 2451}
fc32b0e2 2452module_init(mv643xx_eth_init_module);
d0412d96 2453
e5371493 2454static void __exit mv643xx_eth_cleanup_module(void)
d0412d96 2455{
c9df406f
LB		 2456 platform_driver_unregister(&mv643xx_eth_driver);
2457 platform_driver_unregister(&mv643xx_eth_shared_driver);
d0412d96 2458}
e5371493 2459module_exit(mv643xx_eth_cleanup_module);
1da177e4 2460
fc32b0e2
LB		 2461MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani "
2462 "and Dale Farnsworth");
c9df406f 2463MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
fc32b0e2 2464MODULE_LICENSE("GPL");
c9df406f 2465MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
fc32b0e2 2466MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
Linux 6.x block layer and io_uring tree(s)