Commit | Line | Data |
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1da177e4 | 1 | /* |
9c1bbdfe | 2 | * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports |
1da177e4 LT |
3 | * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com> |
4 | * | |
5 | * Based on the 64360 driver from: | |
4547fa61 LB |
6 | * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il> |
7 | * Rabeeh Khoury <rabeeh@marvell.com> | |
1da177e4 LT |
8 | * |
9 | * Copyright (C) 2003 PMC-Sierra, Inc., | |
3bb8a18a | 10 | * written by Manish Lachwani |
1da177e4 LT |
11 | * |
12 | * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org> | |
13 | * | |
c8aaea25 | 14 | * Copyright (C) 2004-2006 MontaVista Software, Inc. |
1da177e4 LT |
15 | * Dale Farnsworth <dale@farnsworth.org> |
16 | * | |
17 | * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com> | |
18 | * <sjhill@realitydiluted.com> | |
19 | * | |
4547fa61 LB |
20 | * Copyright (C) 2007-2008 Marvell Semiconductor |
21 | * Lennert Buytenhek <buytenh@marvell.com> | |
22 | * | |
1da177e4 LT |
23 | * This program is free software; you can redistribute it and/or |
24 | * modify it under the terms of the GNU General Public License | |
25 | * as published by the Free Software Foundation; either version 2 | |
26 | * of the License, or (at your option) any later version. | |
27 | * | |
28 | * This program is distributed in the hope that it will be useful, | |
29 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
30 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
31 | * GNU General Public License for more details. | |
32 | * | |
33 | * You should have received a copy of the GNU General Public License | |
34 | * along with this program; if not, write to the Free Software | |
35 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
36 | */ | |
a779d38c | 37 | |
1da177e4 LT |
38 | #include <linux/init.h> |
39 | #include <linux/dma-mapping.h> | |
b6298c22 | 40 | #include <linux/in.h> |
1da177e4 LT |
41 | #include <linux/tcp.h> |
42 | #include <linux/udp.h> | |
43 | #include <linux/etherdevice.h> | |
1da177e4 LT |
44 | #include <linux/delay.h> |
45 | #include <linux/ethtool.h> | |
d052d1be | 46 | #include <linux/platform_device.h> |
fbd6a754 LB |
47 | #include <linux/module.h> |
48 | #include <linux/kernel.h> | |
49 | #include <linux/spinlock.h> | |
50 | #include <linux/workqueue.h> | |
51 | #include <linux/mii.h> | |
fbd6a754 | 52 | #include <linux/mv643xx_eth.h> |
1da177e4 LT |
53 | #include <asm/io.h> |
54 | #include <asm/types.h> | |
1da177e4 | 55 | #include <asm/system.h> |
fbd6a754 | 56 | |
c9df406f LB |
57 | static char mv643xx_driver_name[] = "mv643xx_eth"; |
58 | static char mv643xx_driver_version[] = "1.0"; | |
59 | ||
fbd6a754 LB |
60 | #define MV643XX_CHECKSUM_OFFLOAD_TX |
61 | #define MV643XX_NAPI | |
62 | #define MV643XX_TX_FAST_REFILL | |
63 | #undef MV643XX_COAL | |
64 | ||
fbd6a754 LB |
65 | #define MV643XX_TX_COAL 100 |
66 | #ifdef MV643XX_COAL | |
67 | #define MV643XX_RX_COAL 100 | |
68 | #endif | |
69 | ||
70 | #ifdef MV643XX_CHECKSUM_OFFLOAD_TX | |
71 | #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1) | |
72 | #else | |
73 | #define MAX_DESCS_PER_SKB 1 | |
74 | #endif | |
75 | ||
76 | #define ETH_VLAN_HLEN 4 | |
77 | #define ETH_FCS_LEN 4 | |
78 | #define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */ | |
79 | #define ETH_WRAPPER_LEN (ETH_HW_IP_ALIGN + ETH_HLEN + \ | |
80 | ETH_VLAN_HLEN + ETH_FCS_LEN) | |
81 | #define ETH_RX_SKB_SIZE (dev->mtu + ETH_WRAPPER_LEN + \ | |
82 | dma_get_cache_alignment()) | |
83 | ||
84 | /* | |
85 | * Registers shared between all ports. | |
86 | */ | |
3cb4667c LB |
87 | #define PHY_ADDR 0x0000 |
88 | #define SMI_REG 0x0004 | |
89 | #define WINDOW_BASE(w) (0x0200 + ((w) << 3)) | |
90 | #define WINDOW_SIZE(w) (0x0204 + ((w) << 3)) | |
91 | #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2)) | |
92 | #define WINDOW_BAR_ENABLE 0x0290 | |
93 | #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4)) | |
fbd6a754 LB |
94 | |
95 | /* | |
96 | * Per-port registers. | |
97 | */ | |
3cb4667c | 98 | #define PORT_CONFIG(p) (0x0400 + ((p) << 10)) |
d9a073ea | 99 | #define UNICAST_PROMISCUOUS_MODE 0x00000001 |
3cb4667c LB |
100 | #define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10)) |
101 | #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10)) | |
102 | #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10)) | |
103 | #define SDMA_CONFIG(p) (0x041c + ((p) << 10)) | |
104 | #define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10)) | |
105 | #define PORT_STATUS(p) (0x0444 + ((p) << 10)) | |
106 | #define TXQ_COMMAND(p) (0x0448 + ((p) << 10)) | |
107 | #define TX_BW_MTU(p) (0x0458 + ((p) << 10)) | |
108 | #define INT_CAUSE(p) (0x0460 + ((p) << 10)) | |
073a345c LB |
109 | #define INT_RX 0x00000804 |
110 | #define INT_EXT 0x00000002 | |
3cb4667c | 111 | #define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10)) |
073a345c LB |
112 | #define INT_EXT_LINK 0x00100000 |
113 | #define INT_EXT_PHY 0x00010000 | |
114 | #define INT_EXT_TX_ERROR_0 0x00000100 | |
115 | #define INT_EXT_TX_0 0x00000001 | |
116 | #define INT_EXT_TX 0x00000101 | |
3cb4667c LB |
117 | #define INT_MASK(p) (0x0468 + ((p) << 10)) |
118 | #define INT_MASK_EXT(p) (0x046c + ((p) << 10)) | |
119 | #define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10)) | |
120 | #define RXQ_CURRENT_DESC_PTR(p) (0x060c + ((p) << 10)) | |
121 | #define RXQ_COMMAND(p) (0x0680 + ((p) << 10)) | |
122 | #define TXQ_CURRENT_DESC_PTR(p) (0x06c0 + ((p) << 10)) | |
123 | #define MIB_COUNTERS(p) (0x1000 + ((p) << 7)) | |
124 | #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10)) | |
125 | #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10)) | |
126 | #define UNICAST_TABLE(p) (0x1600 + ((p) << 10)) | |
fbd6a754 | 127 | |
2679a550 LB |
128 | |
129 | /* | |
130 | * SDMA configuration register. | |
131 | */ | |
fbd6a754 | 132 | #define RX_BURST_SIZE_4_64BIT (2 << 1) |
fbd6a754 | 133 | #define BLM_RX_NO_SWAP (1 << 4) |
fbd6a754 | 134 | #define BLM_TX_NO_SWAP (1 << 5) |
fbd6a754 | 135 | #define TX_BURST_SIZE_4_64BIT (2 << 22) |
fbd6a754 LB |
136 | |
137 | #if defined(__BIG_ENDIAN) | |
138 | #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ | |
139 | RX_BURST_SIZE_4_64BIT | \ | |
fbd6a754 LB |
140 | TX_BURST_SIZE_4_64BIT |
141 | #elif defined(__LITTLE_ENDIAN) | |
142 | #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ | |
143 | RX_BURST_SIZE_4_64BIT | \ | |
144 | BLM_RX_NO_SWAP | \ | |
145 | BLM_TX_NO_SWAP | \ | |
fbd6a754 LB |
146 | TX_BURST_SIZE_4_64BIT |
147 | #else | |
148 | #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined | |
149 | #endif | |
150 | ||
2beff77b LB |
151 | |
152 | /* | |
153 | * Port serial control register. | |
154 | */ | |
155 | #define SET_MII_SPEED_TO_100 (1 << 24) | |
156 | #define SET_GMII_SPEED_TO_1000 (1 << 23) | |
157 | #define SET_FULL_DUPLEX_MODE (1 << 21) | |
fbd6a754 | 158 | #define MAX_RX_PACKET_1522BYTE (1 << 17) |
fbd6a754 LB |
159 | #define MAX_RX_PACKET_9700BYTE (5 << 17) |
160 | #define MAX_RX_PACKET_MASK (7 << 17) | |
2beff77b LB |
161 | #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13) |
162 | #define DO_NOT_FORCE_LINK_FAIL (1 << 10) | |
163 | #define SERIAL_PORT_CONTROL_RESERVED (1 << 9) | |
164 | #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3) | |
165 | #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2) | |
166 | #define FORCE_LINK_PASS (1 << 1) | |
167 | #define SERIAL_PORT_ENABLE (1 << 0) | |
fbd6a754 | 168 | |
fbd6a754 LB |
169 | #define PORT_DEFAULT_TRANSMIT_QUEUE_SIZE 800 |
170 | #define PORT_DEFAULT_RECEIVE_QUEUE_SIZE 400 | |
171 | ||
fbd6a754 LB |
172 | /* Gigabit Ethernet Unit Global Registers */ |
173 | ||
174 | /* MIB Counters register definitions */ | |
175 | #define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0 | |
176 | #define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4 | |
177 | #define ETH_MIB_BAD_OCTETS_RECEIVED 0x8 | |
178 | #define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc | |
179 | #define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10 | |
180 | #define ETH_MIB_BAD_FRAMES_RECEIVED 0x14 | |
181 | #define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18 | |
182 | #define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c | |
183 | #define ETH_MIB_FRAMES_64_OCTETS 0x20 | |
184 | #define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24 | |
185 | #define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28 | |
186 | #define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c | |
187 | #define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30 | |
188 | #define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34 | |
189 | #define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38 | |
190 | #define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c | |
191 | #define ETH_MIB_GOOD_FRAMES_SENT 0x40 | |
192 | #define ETH_MIB_EXCESSIVE_COLLISION 0x44 | |
193 | #define ETH_MIB_MULTICAST_FRAMES_SENT 0x48 | |
194 | #define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c | |
195 | #define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50 | |
196 | #define ETH_MIB_FC_SENT 0x54 | |
197 | #define ETH_MIB_GOOD_FC_RECEIVED 0x58 | |
198 | #define ETH_MIB_BAD_FC_RECEIVED 0x5c | |
199 | #define ETH_MIB_UNDERSIZE_RECEIVED 0x60 | |
200 | #define ETH_MIB_FRAGMENTS_RECEIVED 0x64 | |
201 | #define ETH_MIB_OVERSIZE_RECEIVED 0x68 | |
202 | #define ETH_MIB_JABBER_RECEIVED 0x6c | |
203 | #define ETH_MIB_MAC_RECEIVE_ERROR 0x70 | |
204 | #define ETH_MIB_BAD_CRC_EVENT 0x74 | |
205 | #define ETH_MIB_COLLISION 0x78 | |
206 | #define ETH_MIB_LATE_COLLISION 0x7c | |
207 | ||
208 | /* Port serial status reg (PSR) */ | |
209 | #define ETH_INTERFACE_PCM 0x00000001 | |
210 | #define ETH_LINK_IS_UP 0x00000002 | |
211 | #define ETH_PORT_AT_FULL_DUPLEX 0x00000004 | |
212 | #define ETH_RX_FLOW_CTRL_ENABLED 0x00000008 | |
213 | #define ETH_GMII_SPEED_1000 0x00000010 | |
214 | #define ETH_MII_SPEED_100 0x00000020 | |
215 | #define ETH_TX_IN_PROGRESS 0x00000080 | |
216 | #define ETH_BYPASS_ACTIVE 0x00000100 | |
217 | #define ETH_PORT_AT_PARTITION_STATE 0x00000200 | |
218 | #define ETH_PORT_TX_FIFO_EMPTY 0x00000400 | |
219 | ||
220 | /* SMI reg */ | |
221 | #define ETH_SMI_BUSY 0x10000000 /* 0 - Write, 1 - Read */ | |
222 | #define ETH_SMI_READ_VALID 0x08000000 /* 0 - Write, 1 - Read */ | |
223 | #define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read */ | |
224 | #define ETH_SMI_OPCODE_READ 0x04000000 /* Operation is in progress */ | |
225 | ||
226 | /* Interrupt Cause Register Bit Definitions */ | |
227 | ||
228 | /* SDMA command status fields macros */ | |
229 | ||
230 | /* Tx & Rx descriptors status */ | |
231 | #define ETH_ERROR_SUMMARY 0x00000001 | |
232 | ||
233 | /* Tx & Rx descriptors command */ | |
234 | #define ETH_BUFFER_OWNED_BY_DMA 0x80000000 | |
235 | ||
236 | /* Tx descriptors status */ | |
237 | #define ETH_LC_ERROR 0 | |
238 | #define ETH_UR_ERROR 0x00000002 | |
239 | #define ETH_RL_ERROR 0x00000004 | |
240 | #define ETH_LLC_SNAP_FORMAT 0x00000200 | |
241 | ||
242 | /* Rx descriptors status */ | |
243 | #define ETH_OVERRUN_ERROR 0x00000002 | |
244 | #define ETH_MAX_FRAME_LENGTH_ERROR 0x00000004 | |
245 | #define ETH_RESOURCE_ERROR 0x00000006 | |
246 | #define ETH_VLAN_TAGGED 0x00080000 | |
247 | #define ETH_BPDU_FRAME 0x00100000 | |
248 | #define ETH_UDP_FRAME_OVER_IP_V_4 0x00200000 | |
249 | #define ETH_OTHER_FRAME_TYPE 0x00400000 | |
250 | #define ETH_LAYER_2_IS_ETH_V_2 0x00800000 | |
251 | #define ETH_FRAME_TYPE_IP_V_4 0x01000000 | |
252 | #define ETH_FRAME_HEADER_OK 0x02000000 | |
253 | #define ETH_RX_LAST_DESC 0x04000000 | |
254 | #define ETH_RX_FIRST_DESC 0x08000000 | |
255 | #define ETH_UNKNOWN_DESTINATION_ADDR 0x10000000 | |
256 | #define ETH_RX_ENABLE_INTERRUPT 0x20000000 | |
257 | #define ETH_LAYER_4_CHECKSUM_OK 0x40000000 | |
258 | ||
259 | /* Rx descriptors byte count */ | |
260 | #define ETH_FRAME_FRAGMENTED 0x00000004 | |
261 | ||
262 | /* Tx descriptors command */ | |
263 | #define ETH_LAYER_4_CHECKSUM_FIRST_DESC 0x00000400 | |
264 | #define ETH_FRAME_SET_TO_VLAN 0x00008000 | |
265 | #define ETH_UDP_FRAME 0x00010000 | |
266 | #define ETH_GEN_TCP_UDP_CHECKSUM 0x00020000 | |
267 | #define ETH_GEN_IP_V_4_CHECKSUM 0x00040000 | |
268 | #define ETH_ZERO_PADDING 0x00080000 | |
269 | #define ETH_TX_LAST_DESC 0x00100000 | |
270 | #define ETH_TX_FIRST_DESC 0x00200000 | |
271 | #define ETH_GEN_CRC 0x00400000 | |
272 | #define ETH_TX_ENABLE_INTERRUPT 0x00800000 | |
273 | #define ETH_AUTO_MODE 0x40000000 | |
274 | ||
275 | #define ETH_TX_IHL_SHIFT 11 | |
276 | ||
277 | /* typedefs */ | |
278 | ||
279 | typedef enum _eth_func_ret_status { | |
280 | ETH_OK, /* Returned as expected. */ | |
281 | ETH_ERROR, /* Fundamental error. */ | |
282 | ETH_RETRY, /* Could not process request. Try later.*/ | |
283 | ETH_END_OF_JOB, /* Ring has nothing to process. */ | |
284 | ETH_QUEUE_FULL, /* Ring resource error. */ | |
285 | ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */ | |
286 | } ETH_FUNC_RET_STATUS; | |
287 | ||
fbd6a754 LB |
288 | /* These are for big-endian machines. Little endian needs different |
289 | * definitions. | |
290 | */ | |
291 | #if defined(__BIG_ENDIAN) | |
292 | struct eth_rx_desc { | |
293 | u16 byte_cnt; /* Descriptor buffer byte count */ | |
294 | u16 buf_size; /* Buffer size */ | |
295 | u32 cmd_sts; /* Descriptor command status */ | |
296 | u32 next_desc_ptr; /* Next descriptor pointer */ | |
297 | u32 buf_ptr; /* Descriptor buffer pointer */ | |
298 | }; | |
299 | ||
300 | struct eth_tx_desc { | |
301 | u16 byte_cnt; /* buffer byte count */ | |
302 | u16 l4i_chk; /* CPU provided TCP checksum */ | |
303 | u32 cmd_sts; /* Command/status field */ | |
304 | u32 next_desc_ptr; /* Pointer to next descriptor */ | |
305 | u32 buf_ptr; /* pointer to buffer for this descriptor*/ | |
306 | }; | |
307 | #elif defined(__LITTLE_ENDIAN) | |
308 | struct eth_rx_desc { | |
309 | u32 cmd_sts; /* Descriptor command status */ | |
310 | u16 buf_size; /* Buffer size */ | |
311 | u16 byte_cnt; /* Descriptor buffer byte count */ | |
312 | u32 buf_ptr; /* Descriptor buffer pointer */ | |
313 | u32 next_desc_ptr; /* Next descriptor pointer */ | |
314 | }; | |
315 | ||
316 | struct eth_tx_desc { | |
317 | u32 cmd_sts; /* Command/status field */ | |
318 | u16 l4i_chk; /* CPU provided TCP checksum */ | |
319 | u16 byte_cnt; /* buffer byte count */ | |
320 | u32 buf_ptr; /* pointer to buffer for this descriptor*/ | |
321 | u32 next_desc_ptr; /* Pointer to next descriptor */ | |
322 | }; | |
323 | #else | |
324 | #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined | |
325 | #endif | |
326 | ||
327 | /* Unified struct for Rx and Tx operations. The user is not required to */ | |
328 | /* be familier with neither Tx nor Rx descriptors. */ | |
329 | struct pkt_info { | |
330 | unsigned short byte_cnt; /* Descriptor buffer byte count */ | |
331 | unsigned short l4i_chk; /* Tx CPU provided TCP Checksum */ | |
332 | unsigned int cmd_sts; /* Descriptor command status */ | |
333 | dma_addr_t buf_ptr; /* Descriptor buffer pointer */ | |
334 | struct sk_buff *return_info; /* User resource return information */ | |
335 | }; | |
336 | ||
c9df406f LB |
337 | |
338 | /* global *******************************************************************/ | |
339 | struct mv643xx_shared_private { | |
340 | void __iomem *eth_base; | |
341 | ||
342 | /* used to protect SMI_REG, which is shared across ports */ | |
343 | spinlock_t phy_lock; | |
344 | ||
345 | u32 win_protect; | |
346 | ||
347 | unsigned int t_clk; | |
348 | }; | |
349 | ||
350 | ||
351 | /* per-port *****************************************************************/ | |
fbd6a754 LB |
352 | struct mv643xx_mib_counters { |
353 | u64 good_octets_received; | |
354 | u32 bad_octets_received; | |
355 | u32 internal_mac_transmit_err; | |
356 | u32 good_frames_received; | |
357 | u32 bad_frames_received; | |
358 | u32 broadcast_frames_received; | |
359 | u32 multicast_frames_received; | |
360 | u32 frames_64_octets; | |
361 | u32 frames_65_to_127_octets; | |
362 | u32 frames_128_to_255_octets; | |
363 | u32 frames_256_to_511_octets; | |
364 | u32 frames_512_to_1023_octets; | |
365 | u32 frames_1024_to_max_octets; | |
366 | u64 good_octets_sent; | |
367 | u32 good_frames_sent; | |
368 | u32 excessive_collision; | |
369 | u32 multicast_frames_sent; | |
370 | u32 broadcast_frames_sent; | |
371 | u32 unrec_mac_control_received; | |
372 | u32 fc_sent; | |
373 | u32 good_fc_received; | |
374 | u32 bad_fc_received; | |
375 | u32 undersize_received; | |
376 | u32 fragments_received; | |
377 | u32 oversize_received; | |
378 | u32 jabber_received; | |
379 | u32 mac_receive_error; | |
380 | u32 bad_crc_event; | |
381 | u32 collision; | |
382 | u32 late_collision; | |
383 | }; | |
384 | ||
385 | struct mv643xx_private { | |
fa3959f4 | 386 | struct mv643xx_shared_private *shared; |
fbd6a754 LB |
387 | int port_num; /* User Ethernet port number */ |
388 | ||
ce4e2e45 LB |
389 | struct mv643xx_shared_private *shared_smi; |
390 | ||
fbd6a754 LB |
391 | u32 rx_sram_addr; /* Base address of rx sram area */ |
392 | u32 rx_sram_size; /* Size of rx sram area */ | |
393 | u32 tx_sram_addr; /* Base address of tx sram area */ | |
394 | u32 tx_sram_size; /* Size of tx sram area */ | |
395 | ||
396 | int rx_resource_err; /* Rx ring resource error flag */ | |
397 | ||
398 | /* Tx/Rx rings managment indexes fields. For driver use */ | |
399 | ||
400 | /* Next available and first returning Rx resource */ | |
401 | int rx_curr_desc_q, rx_used_desc_q; | |
402 | ||
403 | /* Next available and first returning Tx resource */ | |
404 | int tx_curr_desc_q, tx_used_desc_q; | |
405 | ||
406 | #ifdef MV643XX_TX_FAST_REFILL | |
407 | u32 tx_clean_threshold; | |
408 | #endif | |
409 | ||
410 | struct eth_rx_desc *p_rx_desc_area; | |
411 | dma_addr_t rx_desc_dma; | |
412 | int rx_desc_area_size; | |
413 | struct sk_buff **rx_skb; | |
414 | ||
415 | struct eth_tx_desc *p_tx_desc_area; | |
416 | dma_addr_t tx_desc_dma; | |
417 | int tx_desc_area_size; | |
418 | struct sk_buff **tx_skb; | |
419 | ||
420 | struct work_struct tx_timeout_task; | |
421 | ||
422 | struct net_device *dev; | |
423 | struct napi_struct napi; | |
424 | struct net_device_stats stats; | |
425 | struct mv643xx_mib_counters mib_counters; | |
426 | spinlock_t lock; | |
427 | /* Size of Tx Ring per queue */ | |
428 | int tx_ring_size; | |
429 | /* Number of tx descriptors in use */ | |
430 | int tx_desc_count; | |
431 | /* Size of Rx Ring per queue */ | |
432 | int rx_ring_size; | |
433 | /* Number of rx descriptors in use */ | |
434 | int rx_desc_count; | |
435 | ||
436 | /* | |
437 | * Used in case RX Ring is empty, which can be caused when | |
438 | * system does not have resources (skb's) | |
439 | */ | |
440 | struct timer_list timeout; | |
441 | ||
442 | u32 rx_int_coal; | |
443 | u32 tx_int_coal; | |
444 | struct mii_if_info mii; | |
445 | }; | |
1da177e4 | 446 | |
fbd6a754 | 447 | |
c9df406f LB |
448 | /* port register accessors **************************************************/ |
449 | static inline u32 rdl(struct mv643xx_private *mp, int offset) | |
450 | { | |
451 | return readl(mp->shared->eth_base + offset); | |
452 | } | |
fbd6a754 | 453 | |
c9df406f LB |
454 | static inline void wrl(struct mv643xx_private *mp, int offset, u32 data) |
455 | { | |
456 | writel(data, mp->shared->eth_base + offset); | |
457 | } | |
fbd6a754 | 458 | |
fbd6a754 | 459 | |
c9df406f LB |
460 | /* rxq/txq helper functions *************************************************/ |
461 | static void mv643xx_eth_port_enable_rx(struct mv643xx_private *mp, | |
462 | unsigned int queues) | |
463 | { | |
3cb4667c | 464 | wrl(mp, RXQ_COMMAND(mp->port_num), queues); |
c9df406f | 465 | } |
fbd6a754 | 466 | |
c9df406f LB |
467 | static unsigned int mv643xx_eth_port_disable_rx(struct mv643xx_private *mp) |
468 | { | |
469 | unsigned int port_num = mp->port_num; | |
470 | u32 queues; | |
fbd6a754 | 471 | |
c9df406f | 472 | /* Stop Rx port activity. Check port Rx activity. */ |
3cb4667c | 473 | queues = rdl(mp, RXQ_COMMAND(port_num)) & 0xFF; |
c9df406f LB |
474 | if (queues) { |
475 | /* Issue stop command for active queues only */ | |
3cb4667c | 476 | wrl(mp, RXQ_COMMAND(port_num), (queues << 8)); |
1da177e4 | 477 | |
c9df406f LB |
478 | /* Wait for all Rx activity to terminate. */ |
479 | /* Check port cause register that all Rx queues are stopped */ | |
3cb4667c | 480 | while (rdl(mp, RXQ_COMMAND(port_num)) & 0xFF) |
e1bea50a | 481 | udelay(10); |
c9df406f | 482 | } |
1da177e4 | 483 | |
c9df406f LB |
484 | return queues; |
485 | } | |
486 | ||
487 | static void mv643xx_eth_port_enable_tx(struct mv643xx_private *mp, | |
488 | unsigned int queues) | |
1da177e4 | 489 | { |
3cb4667c | 490 | wrl(mp, TXQ_COMMAND(mp->port_num), queues); |
1da177e4 LT |
491 | } |
492 | ||
c9df406f | 493 | static unsigned int mv643xx_eth_port_disable_tx(struct mv643xx_private *mp) |
1da177e4 | 494 | { |
c9df406f LB |
495 | unsigned int port_num = mp->port_num; |
496 | u32 queues; | |
497 | ||
498 | /* Stop Tx port activity. Check port Tx activity. */ | |
3cb4667c | 499 | queues = rdl(mp, TXQ_COMMAND(port_num)) & 0xFF; |
c9df406f LB |
500 | if (queues) { |
501 | /* Issue stop command for active queues only */ | |
3cb4667c | 502 | wrl(mp, TXQ_COMMAND(port_num), (queues << 8)); |
c9df406f LB |
503 | |
504 | /* Wait for all Tx activity to terminate. */ | |
505 | /* Check port cause register that all Tx queues are stopped */ | |
3cb4667c | 506 | while (rdl(mp, TXQ_COMMAND(port_num)) & 0xFF) |
e1bea50a | 507 | udelay(10); |
c9df406f LB |
508 | |
509 | /* Wait for Tx FIFO to empty */ | |
3cb4667c | 510 | while (rdl(mp, PORT_STATUS(port_num)) & ETH_PORT_TX_FIFO_EMPTY) |
e1bea50a | 511 | udelay(10); |
c9df406f LB |
512 | } |
513 | ||
514 | return queues; | |
1da177e4 LT |
515 | } |
516 | ||
c9df406f LB |
517 | |
518 | /* rx ***********************************************************************/ | |
519 | static void mv643xx_eth_free_completed_tx_descs(struct net_device *dev); | |
520 | ||
1da177e4 | 521 | /* |
c9df406f | 522 | * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring. |
1da177e4 | 523 | * |
c9df406f LB |
524 | * DESCRIPTION: |
525 | * This routine returns a Rx buffer back to the Rx ring. It retrieves the | |
526 | * next 'used' descriptor and attached the returned buffer to it. | |
527 | * In case the Rx ring was in "resource error" condition, where there are | |
528 | * no available Rx resources, the function resets the resource error flag. | |
529 | * | |
530 | * INPUT: | |
531 | * struct mv643xx_private *mp Ethernet Port Control srtuct. | |
532 | * struct pkt_info *p_pkt_info Information on returned buffer. | |
533 | * | |
534 | * OUTPUT: | |
535 | * New available Rx resource in Rx descriptor ring. | |
536 | * | |
537 | * RETURN: | |
538 | * ETH_ERROR in case the routine can not access Rx desc ring. | |
539 | * ETH_OK otherwise. | |
1da177e4 | 540 | */ |
c9df406f LB |
541 | static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp, |
542 | struct pkt_info *p_pkt_info) | |
1da177e4 | 543 | { |
c9df406f LB |
544 | int used_rx_desc; /* Where to return Rx resource */ |
545 | volatile struct eth_rx_desc *p_used_rx_desc; | |
546 | unsigned long flags; | |
1da177e4 | 547 | |
c9df406f | 548 | spin_lock_irqsave(&mp->lock, flags); |
c0d0f2ca | 549 | |
c9df406f LB |
550 | /* Get 'used' Rx descriptor */ |
551 | used_rx_desc = mp->rx_used_desc_q; | |
552 | p_used_rx_desc = &mp->p_rx_desc_area[used_rx_desc]; | |
1da177e4 | 553 | |
c9df406f LB |
554 | p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr; |
555 | p_used_rx_desc->buf_size = p_pkt_info->byte_cnt; | |
556 | mp->rx_skb[used_rx_desc] = p_pkt_info->return_info; | |
557 | ||
558 | /* Flush the write pipe */ | |
559 | ||
560 | /* Return the descriptor to DMA ownership */ | |
561 | wmb(); | |
562 | p_used_rx_desc->cmd_sts = | |
563 | ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT; | |
564 | wmb(); | |
565 | ||
566 | /* Move the used descriptor pointer to the next descriptor */ | |
567 | mp->rx_used_desc_q = (used_rx_desc + 1) % mp->rx_ring_size; | |
568 | ||
569 | /* Any Rx return cancels the Rx resource error status */ | |
570 | mp->rx_resource_err = 0; | |
571 | ||
572 | spin_unlock_irqrestore(&mp->lock, flags); | |
573 | ||
574 | return ETH_OK; | |
1da177e4 LT |
575 | } |
576 | ||
577 | /* | |
f78fb474 | 578 | * mv643xx_eth_rx_refill_descs |
1da177e4 LT |
579 | * |
580 | * Fills / refills RX queue on a certain gigabit ethernet port | |
581 | * | |
582 | * Input : pointer to ethernet interface network device structure | |
583 | * Output : N/A | |
584 | */ | |
f78fb474 | 585 | static void mv643xx_eth_rx_refill_descs(struct net_device *dev) |
1da177e4 | 586 | { |
1da177e4 LT |
587 | struct mv643xx_private *mp = netdev_priv(dev); |
588 | struct pkt_info pkt_info; | |
589 | struct sk_buff *skb; | |
b44cd572 | 590 | int unaligned; |
1da177e4 | 591 | |
f78fb474 | 592 | while (mp->rx_desc_count < mp->rx_ring_size) { |
908b637f | 593 | skb = dev_alloc_skb(ETH_RX_SKB_SIZE + dma_get_cache_alignment()); |
1da177e4 LT |
594 | if (!skb) |
595 | break; | |
f98e36f1 | 596 | mp->rx_desc_count++; |
908b637f | 597 | unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1); |
b44cd572 | 598 | if (unaligned) |
908b637f | 599 | skb_reserve(skb, dma_get_cache_alignment() - unaligned); |
1da177e4 | 600 | pkt_info.cmd_sts = ETH_RX_ENABLE_INTERRUPT; |
7303fde8 DF |
601 | pkt_info.byte_cnt = ETH_RX_SKB_SIZE; |
602 | pkt_info.buf_ptr = dma_map_single(NULL, skb->data, | |
603 | ETH_RX_SKB_SIZE, DMA_FROM_DEVICE); | |
1da177e4 LT |
604 | pkt_info.return_info = skb; |
605 | if (eth_rx_return_buff(mp, &pkt_info) != ETH_OK) { | |
606 | printk(KERN_ERR | |
607 | "%s: Error allocating RX Ring\n", dev->name); | |
608 | break; | |
609 | } | |
7303fde8 | 610 | skb_reserve(skb, ETH_HW_IP_ALIGN); |
1da177e4 | 611 | } |
1da177e4 LT |
612 | /* |
613 | * If RX ring is empty of SKB, set a timer to try allocating | |
f78fb474 | 614 | * again at a later time. |
1da177e4 | 615 | */ |
f78fb474 | 616 | if (mp->rx_desc_count == 0) { |
1da177e4 | 617 | printk(KERN_INFO "%s: Rx ring is empty\n", dev->name); |
f78fb474 | 618 | mp->timeout.expires = jiffies + (HZ / 10); /* 100 mSec */ |
1da177e4 | 619 | add_timer(&mp->timeout); |
1da177e4 | 620 | } |
1da177e4 LT |
621 | } |
622 | ||
623 | /* | |
f78fb474 | 624 | * mv643xx_eth_rx_refill_descs_timer_wrapper |
1da177e4 LT |
625 | * |
626 | * Timer routine to wake up RX queue filling task. This function is | |
627 | * used only in case the RX queue is empty, and all alloc_skb has | |
628 | * failed (due to out of memory event). | |
629 | * | |
630 | * Input : pointer to ethernet interface network device structure | |
631 | * Output : N/A | |
632 | */ | |
f78fb474 | 633 | static inline void mv643xx_eth_rx_refill_descs_timer_wrapper(unsigned long data) |
1da177e4 | 634 | { |
f78fb474 | 635 | mv643xx_eth_rx_refill_descs((struct net_device *)data); |
1da177e4 LT |
636 | } |
637 | ||
638 | /* | |
c9df406f | 639 | * eth_port_receive - Get received information from Rx ring. |
1da177e4 | 640 | * |
c9df406f LB |
641 | * DESCRIPTION: |
642 | * This routine returns the received data to the caller. There is no | |
643 | * data copying during routine operation. All information is returned | |
644 | * using pointer to packet information struct passed from the caller. | |
645 | * If the routine exhausts Rx ring resources then the resource error flag | |
646 | * is set. | |
1da177e4 | 647 | * |
c9df406f LB |
648 | * INPUT: |
649 | * struct mv643xx_private *mp Ethernet Port Control srtuct. | |
650 | * struct pkt_info *p_pkt_info User packet buffer. | |
1da177e4 | 651 | * |
c9df406f LB |
652 | * OUTPUT: |
653 | * Rx ring current and used indexes are updated. | |
1da177e4 | 654 | * |
c9df406f LB |
655 | * RETURN: |
656 | * ETH_ERROR in case the routine can not access Rx desc ring. | |
657 | * ETH_QUEUE_FULL if Rx ring resources are exhausted. | |
658 | * ETH_END_OF_JOB if there is no received data. | |
659 | * ETH_OK otherwise. | |
1da177e4 | 660 | */ |
c9df406f LB |
661 | static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp, |
662 | struct pkt_info *p_pkt_info) | |
1da177e4 | 663 | { |
c9df406f LB |
664 | int rx_next_curr_desc, rx_curr_desc, rx_used_desc; |
665 | volatile struct eth_rx_desc *p_rx_desc; | |
666 | unsigned int command_status; | |
667 | unsigned long flags; | |
1da177e4 | 668 | |
c9df406f LB |
669 | /* Do not process Rx ring in case of Rx ring resource error */ |
670 | if (mp->rx_resource_err) | |
671 | return ETH_QUEUE_FULL; | |
16e03018 | 672 | |
c9df406f | 673 | spin_lock_irqsave(&mp->lock, flags); |
1da177e4 | 674 | |
c9df406f LB |
675 | /* Get the Rx Desc ring 'curr and 'used' indexes */ |
676 | rx_curr_desc = mp->rx_curr_desc_q; | |
677 | rx_used_desc = mp->rx_used_desc_q; | |
1da177e4 | 678 | |
c9df406f | 679 | p_rx_desc = &mp->p_rx_desc_area[rx_curr_desc]; |
1da177e4 | 680 | |
c9df406f LB |
681 | /* The following parameters are used to save readings from memory */ |
682 | command_status = p_rx_desc->cmd_sts; | |
683 | rmb(); | |
1da177e4 | 684 | |
c9df406f LB |
685 | /* Nothing to receive... */ |
686 | if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { | |
d344bff9 | 687 | spin_unlock_irqrestore(&mp->lock, flags); |
c9df406f LB |
688 | return ETH_END_OF_JOB; |
689 | } | |
d344bff9 | 690 | |
0a6cf74d | 691 | p_pkt_info->byte_cnt = p_rx_desc->byte_cnt - ETH_HW_IP_ALIGN; |
c9df406f | 692 | p_pkt_info->cmd_sts = command_status; |
0a6cf74d | 693 | p_pkt_info->buf_ptr = p_rx_desc->buf_ptr + ETH_HW_IP_ALIGN; |
c9df406f LB |
694 | p_pkt_info->return_info = mp->rx_skb[rx_curr_desc]; |
695 | p_pkt_info->l4i_chk = p_rx_desc->buf_size; | |
ff561eef | 696 | |
c9df406f LB |
697 | /* |
698 | * Clean the return info field to indicate that the | |
699 | * packet has been moved to the upper layers | |
700 | */ | |
701 | mp->rx_skb[rx_curr_desc] = NULL; | |
1da177e4 | 702 | |
c9df406f LB |
703 | /* Update current index in data structure */ |
704 | rx_next_curr_desc = (rx_curr_desc + 1) % mp->rx_ring_size; | |
705 | mp->rx_curr_desc_q = rx_next_curr_desc; | |
1da177e4 | 706 | |
c9df406f LB |
707 | /* Rx descriptors exhausted. Set the Rx ring resource error flag */ |
708 | if (rx_next_curr_desc == rx_used_desc) | |
709 | mp->rx_resource_err = 1; | |
ff561eef | 710 | |
c9df406f | 711 | spin_unlock_irqrestore(&mp->lock, flags); |
ff561eef | 712 | |
c9df406f | 713 | return ETH_OK; |
ff561eef DF |
714 | } |
715 | ||
1da177e4 LT |
716 | /* |
717 | * mv643xx_eth_receive | |
718 | * | |
719 | * This function is forward packets that are received from the port's | |
720 | * queues toward kernel core or FastRoute them to another interface. | |
721 | * | |
722 | * Input : dev - a pointer to the required interface | |
723 | * max - maximum number to receive (0 means unlimted) | |
724 | * | |
725 | * Output : number of served packets | |
726 | */ | |
1da177e4 | 727 | static int mv643xx_eth_receive_queue(struct net_device *dev, int budget) |
1da177e4 LT |
728 | { |
729 | struct mv643xx_private *mp = netdev_priv(dev); | |
09f75cd7 | 730 | struct net_device_stats *stats = &dev->stats; |
1da177e4 LT |
731 | unsigned int received_packets = 0; |
732 | struct sk_buff *skb; | |
733 | struct pkt_info pkt_info; | |
734 | ||
b1dd9ca1 | 735 | while (budget-- > 0 && eth_port_receive(mp, &pkt_info) == ETH_OK) { |
54caf44d | 736 | dma_unmap_single(NULL, pkt_info.buf_ptr, ETH_RX_SKB_SIZE, |
71d28725 | 737 | DMA_FROM_DEVICE); |
f98e36f1 | 738 | mp->rx_desc_count--; |
1da177e4 | 739 | received_packets++; |
b1dd9ca1 | 740 | |
468d09f8 DF |
741 | /* |
742 | * Update statistics. | |
743 | * Note byte count includes 4 byte CRC count | |
744 | */ | |
1da177e4 LT |
745 | stats->rx_packets++; |
746 | stats->rx_bytes += pkt_info.byte_cnt; | |
747 | skb = pkt_info.return_info; | |
748 | /* | |
749 | * In case received a packet without first / last bits on OR | |
750 | * the error summary bit is on, the packets needs to be dropeed. | |
751 | */ | |
752 | if (((pkt_info.cmd_sts | |
753 | & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) != | |
754 | (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) | |
755 | || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) { | |
756 | stats->rx_dropped++; | |
757 | if ((pkt_info.cmd_sts & (ETH_RX_FIRST_DESC | | |
758 | ETH_RX_LAST_DESC)) != | |
759 | (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) { | |
760 | if (net_ratelimit()) | |
761 | printk(KERN_ERR | |
762 | "%s: Received packet spread " | |
763 | "on multiple descriptors\n", | |
764 | dev->name); | |
765 | } | |
766 | if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) | |
767 | stats->rx_errors++; | |
768 | ||
769 | dev_kfree_skb_irq(skb); | |
770 | } else { | |
771 | /* | |
772 | * The -4 is for the CRC in the trailer of the | |
773 | * received packet | |
774 | */ | |
775 | skb_put(skb, pkt_info.byte_cnt - 4); | |
1da177e4 LT |
776 | |
777 | if (pkt_info.cmd_sts & ETH_LAYER_4_CHECKSUM_OK) { | |
778 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
779 | skb->csum = htons( | |
780 | (pkt_info.cmd_sts & 0x0007fff8) >> 3); | |
781 | } | |
782 | skb->protocol = eth_type_trans(skb, dev); | |
783 | #ifdef MV643XX_NAPI | |
784 | netif_receive_skb(skb); | |
785 | #else | |
786 | netif_rx(skb); | |
787 | #endif | |
788 | } | |
12ad74f8 | 789 | dev->last_rx = jiffies; |
1da177e4 | 790 | } |
f78fb474 | 791 | mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */ |
1da177e4 LT |
792 | |
793 | return received_packets; | |
794 | } | |
795 | ||
c9df406f LB |
796 | #ifdef MV643XX_NAPI |
797 | /* | |
798 | * mv643xx_poll | |
799 | * | |
800 | * This function is used in case of NAPI | |
801 | */ | |
802 | static int mv643xx_poll(struct napi_struct *napi, int budget) | |
d0412d96 | 803 | { |
c9df406f LB |
804 | struct mv643xx_private *mp = container_of(napi, struct mv643xx_private, napi); |
805 | struct net_device *dev = mp->dev; | |
806 | unsigned int port_num = mp->port_num; | |
807 | int work_done; | |
d0412d96 | 808 | |
c9df406f LB |
809 | #ifdef MV643XX_TX_FAST_REFILL |
810 | if (++mp->tx_clean_threshold > 5) { | |
811 | mv643xx_eth_free_completed_tx_descs(dev); | |
812 | mp->tx_clean_threshold = 0; | |
d0412d96 | 813 | } |
c9df406f | 814 | #endif |
d0412d96 | 815 | |
c9df406f | 816 | work_done = 0; |
3cb4667c | 817 | if ((rdl(mp, RXQ_CURRENT_DESC_PTR(port_num))) |
c9df406f LB |
818 | != (u32) mp->rx_used_desc_q) |
819 | work_done = mv643xx_eth_receive_queue(dev, budget); | |
d0412d96 | 820 | |
c9df406f LB |
821 | if (work_done < budget) { |
822 | netif_rx_complete(dev, napi); | |
3cb4667c LB |
823 | wrl(mp, INT_CAUSE(port_num), 0); |
824 | wrl(mp, INT_CAUSE_EXT(port_num), 0); | |
073a345c | 825 | wrl(mp, INT_MASK(port_num), INT_RX | INT_EXT); |
d0412d96 | 826 | } |
c9df406f LB |
827 | |
828 | return work_done; | |
d0412d96 | 829 | } |
c9df406f | 830 | #endif |
d0412d96 | 831 | |
c9df406f LB |
832 | |
833 | /* tx ***********************************************************************/ | |
834 | /** | |
835 | * has_tiny_unaligned_frags - check if skb has any small, unaligned fragments | |
1da177e4 | 836 | * |
c9df406f LB |
837 | * Hardware can't handle unaligned fragments smaller than 9 bytes. |
838 | * This helper function detects that case. | |
1da177e4 LT |
839 | */ |
840 | ||
c9df406f | 841 | static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb) |
1da177e4 | 842 | { |
c9df406f LB |
843 | unsigned int frag; |
844 | skb_frag_t *fragp; | |
1da177e4 | 845 | |
c9df406f LB |
846 | for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { |
847 | fragp = &skb_shinfo(skb)->frags[frag]; | |
848 | if (fragp->size <= 8 && fragp->page_offset & 0x7) | |
849 | return 1; | |
1da177e4 | 850 | } |
c9df406f LB |
851 | return 0; |
852 | } | |
7303fde8 | 853 | |
c9df406f LB |
854 | /** |
855 | * eth_alloc_tx_desc_index - return the index of the next available tx desc | |
856 | */ | |
857 | static int eth_alloc_tx_desc_index(struct mv643xx_private *mp) | |
858 | { | |
859 | int tx_desc_curr; | |
d0412d96 | 860 | |
c9df406f | 861 | BUG_ON(mp->tx_desc_count >= mp->tx_ring_size); |
1da177e4 | 862 | |
c9df406f LB |
863 | tx_desc_curr = mp->tx_curr_desc_q; |
864 | mp->tx_curr_desc_q = (tx_desc_curr + 1) % mp->tx_ring_size; | |
e4d00fa9 | 865 | |
c9df406f | 866 | BUG_ON(mp->tx_curr_desc_q == mp->tx_used_desc_q); |
468d09f8 | 867 | |
c9df406f LB |
868 | return tx_desc_curr; |
869 | } | |
468d09f8 | 870 | |
c9df406f LB |
871 | /** |
872 | * eth_tx_fill_frag_descs - fill tx hw descriptors for an skb's fragments. | |
873 | * | |
874 | * Ensure the data for each fragment to be transmitted is mapped properly, | |
875 | * then fill in descriptors in the tx hw queue. | |
876 | */ | |
877 | static void eth_tx_fill_frag_descs(struct mv643xx_private *mp, | |
878 | struct sk_buff *skb) | |
879 | { | |
880 | int frag; | |
881 | int tx_index; | |
882 | struct eth_tx_desc *desc; | |
1da177e4 | 883 | |
c9df406f LB |
884 | for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { |
885 | skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag]; | |
886 | ||
887 | tx_index = eth_alloc_tx_desc_index(mp); | |
888 | desc = &mp->p_tx_desc_area[tx_index]; | |
889 | ||
890 | desc->cmd_sts = ETH_BUFFER_OWNED_BY_DMA; | |
891 | /* Last Frag enables interrupt and frees the skb */ | |
892 | if (frag == (skb_shinfo(skb)->nr_frags - 1)) { | |
893 | desc->cmd_sts |= ETH_ZERO_PADDING | | |
894 | ETH_TX_LAST_DESC | | |
895 | ETH_TX_ENABLE_INTERRUPT; | |
896 | mp->tx_skb[tx_index] = skb; | |
897 | } else | |
898 | mp->tx_skb[tx_index] = NULL; | |
899 | ||
900 | desc = &mp->p_tx_desc_area[tx_index]; | |
901 | desc->l4i_chk = 0; | |
902 | desc->byte_cnt = this_frag->size; | |
903 | desc->buf_ptr = dma_map_page(NULL, this_frag->page, | |
904 | this_frag->page_offset, | |
905 | this_frag->size, | |
906 | DMA_TO_DEVICE); | |
907 | } | |
1da177e4 LT |
908 | } |
909 | ||
c9df406f LB |
910 | static inline __be16 sum16_as_be(__sum16 sum) |
911 | { | |
912 | return (__force __be16)sum; | |
913 | } | |
1da177e4 | 914 | |
c9df406f LB |
915 | /** |
916 | * eth_tx_submit_descs_for_skb - submit data from an skb to the tx hw | |
1da177e4 | 917 | * |
c9df406f LB |
918 | * Ensure the data for an skb to be transmitted is mapped properly, |
919 | * then fill in descriptors in the tx hw queue and start the hardware. | |
1da177e4 | 920 | */ |
c9df406f LB |
921 | static void eth_tx_submit_descs_for_skb(struct mv643xx_private *mp, |
922 | struct sk_buff *skb) | |
1da177e4 | 923 | { |
c9df406f LB |
924 | int tx_index; |
925 | struct eth_tx_desc *desc; | |
926 | u32 cmd_sts; | |
927 | int length; | |
928 | int nr_frags = skb_shinfo(skb)->nr_frags; | |
1da177e4 | 929 | |
c9df406f | 930 | cmd_sts = ETH_TX_FIRST_DESC | ETH_GEN_CRC | ETH_BUFFER_OWNED_BY_DMA; |
1da177e4 | 931 | |
c9df406f LB |
932 | tx_index = eth_alloc_tx_desc_index(mp); |
933 | desc = &mp->p_tx_desc_area[tx_index]; | |
934 | ||
935 | if (nr_frags) { | |
936 | eth_tx_fill_frag_descs(mp, skb); | |
937 | ||
938 | length = skb_headlen(skb); | |
939 | mp->tx_skb[tx_index] = NULL; | |
940 | } else { | |
941 | cmd_sts |= ETH_ZERO_PADDING | | |
942 | ETH_TX_LAST_DESC | | |
943 | ETH_TX_ENABLE_INTERRUPT; | |
944 | length = skb->len; | |
945 | mp->tx_skb[tx_index] = skb; | |
946 | } | |
947 | ||
948 | desc->byte_cnt = length; | |
949 | desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE); | |
950 | ||
951 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
952 | BUG_ON(skb->protocol != htons(ETH_P_IP)); | |
953 | ||
954 | cmd_sts |= ETH_GEN_TCP_UDP_CHECKSUM | | |
955 | ETH_GEN_IP_V_4_CHECKSUM | | |
956 | ip_hdr(skb)->ihl << ETH_TX_IHL_SHIFT; | |
957 | ||
958 | switch (ip_hdr(skb)->protocol) { | |
959 | case IPPROTO_UDP: | |
960 | cmd_sts |= ETH_UDP_FRAME; | |
961 | desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check)); | |
962 | break; | |
963 | case IPPROTO_TCP: | |
964 | desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check)); | |
965 | break; | |
966 | default: | |
967 | BUG(); | |
968 | } | |
969 | } else { | |
970 | /* Errata BTS #50, IHL must be 5 if no HW checksum */ | |
971 | cmd_sts |= 5 << ETH_TX_IHL_SHIFT; | |
972 | desc->l4i_chk = 0; | |
973 | } | |
974 | ||
975 | /* ensure all other descriptors are written before first cmd_sts */ | |
976 | wmb(); | |
977 | desc->cmd_sts = cmd_sts; | |
978 | ||
979 | /* ensure all descriptors are written before poking hardware */ | |
980 | wmb(); | |
073a345c | 981 | mv643xx_eth_port_enable_tx(mp, 1); |
c9df406f LB |
982 | |
983 | mp->tx_desc_count += nr_frags + 1; | |
1da177e4 | 984 | } |
1da177e4 | 985 | |
c9df406f LB |
986 | /** |
987 | * mv643xx_eth_start_xmit - queue an skb to the hardware for transmission | |
1da177e4 LT |
988 | * |
989 | */ | |
c9df406f | 990 | static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev) |
1da177e4 | 991 | { |
c9df406f LB |
992 | struct mv643xx_private *mp = netdev_priv(dev); |
993 | struct net_device_stats *stats = &dev->stats; | |
994 | unsigned long flags; | |
afdb57a2 | 995 | |
c9df406f | 996 | BUG_ON(netif_queue_stopped(dev)); |
afdb57a2 | 997 | |
c9df406f LB |
998 | if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) { |
999 | stats->tx_dropped++; | |
1000 | printk(KERN_DEBUG "%s: failed to linearize tiny " | |
1001 | "unaligned fragment\n", dev->name); | |
1002 | return NETDEV_TX_BUSY; | |
1003 | } | |
1004 | ||
1005 | spin_lock_irqsave(&mp->lock, flags); | |
1006 | ||
1007 | if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB) { | |
1008 | printk(KERN_ERR "%s: transmit with queue full\n", dev->name); | |
1009 | netif_stop_queue(dev); | |
1010 | spin_unlock_irqrestore(&mp->lock, flags); | |
1011 | return NETDEV_TX_BUSY; | |
1012 | } | |
1013 | ||
1014 | eth_tx_submit_descs_for_skb(mp, skb); | |
1015 | stats->tx_bytes += skb->len; | |
1016 | stats->tx_packets++; | |
1017 | dev->trans_start = jiffies; | |
1018 | ||
1019 | if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB) | |
1020 | netif_stop_queue(dev); | |
1021 | ||
1022 | spin_unlock_irqrestore(&mp->lock, flags); | |
1023 | ||
1024 | return NETDEV_TX_OK; | |
1da177e4 LT |
1025 | } |
1026 | ||
c9df406f LB |
1027 | |
1028 | /* mii management interface *************************************************/ | |
1029 | static int ethernet_phy_get(struct mv643xx_private *mp); | |
1030 | ||
1da177e4 | 1031 | /* |
c9df406f | 1032 | * eth_port_read_smi_reg - Read PHY registers |
1da177e4 LT |
1033 | * |
1034 | * DESCRIPTION: | |
c9df406f LB |
1035 | * This routine utilize the SMI interface to interact with the PHY in |
1036 | * order to perform PHY register read. | |
1da177e4 LT |
1037 | * |
1038 | * INPUT: | |
c9df406f LB |
1039 | * struct mv643xx_private *mp Ethernet Port. |
1040 | * unsigned int phy_reg PHY register address offset. | |
1041 | * unsigned int *value Register value buffer. | |
1da177e4 LT |
1042 | * |
1043 | * OUTPUT: | |
c9df406f | 1044 | * Write the value of a specified PHY register into given buffer. |
1da177e4 LT |
1045 | * |
1046 | * RETURN: | |
c9df406f LB |
1047 | * false if the PHY is busy or read data is not in valid state. |
1048 | * true otherwise. | |
1049 | * | |
1da177e4 | 1050 | */ |
c9df406f LB |
1051 | static void eth_port_read_smi_reg(struct mv643xx_private *mp, |
1052 | unsigned int phy_reg, unsigned int *value) | |
1da177e4 | 1053 | { |
c9df406f LB |
1054 | void __iomem *smi_reg = mp->shared_smi->eth_base + SMI_REG; |
1055 | int phy_addr = ethernet_phy_get(mp); | |
1056 | unsigned long flags; | |
1da177e4 LT |
1057 | int i; |
1058 | ||
c9df406f LB |
1059 | /* the SMI register is a shared resource */ |
1060 | spin_lock_irqsave(&mp->shared_smi->phy_lock, flags); | |
1061 | ||
1062 | /* wait for the SMI register to become available */ | |
1063 | for (i = 0; readl(smi_reg) & ETH_SMI_BUSY; i++) { | |
e1bea50a | 1064 | if (i == 1000) { |
c9df406f LB |
1065 | printk("%s: PHY busy timeout\n", mp->dev->name); |
1066 | goto out; | |
1067 | } | |
e1bea50a | 1068 | udelay(10); |
1da177e4 LT |
1069 | } |
1070 | ||
c9df406f LB |
1071 | writel((phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ, |
1072 | smi_reg); | |
1da177e4 | 1073 | |
c9df406f LB |
1074 | /* now wait for the data to be valid */ |
1075 | for (i = 0; !(readl(smi_reg) & ETH_SMI_READ_VALID); i++) { | |
e1bea50a | 1076 | if (i == 1000) { |
c9df406f LB |
1077 | printk("%s: PHY read timeout\n", mp->dev->name); |
1078 | goto out; | |
1079 | } | |
e1bea50a | 1080 | udelay(10); |
c9df406f LB |
1081 | } |
1082 | ||
1083 | *value = readl(smi_reg) & 0xffff; | |
1084 | out: | |
1085 | spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags); | |
1da177e4 LT |
1086 | } |
1087 | ||
1088 | /* | |
c9df406f | 1089 | * eth_port_write_smi_reg - Write to PHY registers |
1da177e4 LT |
1090 | * |
1091 | * DESCRIPTION: | |
c9df406f LB |
1092 | * This routine utilize the SMI interface to interact with the PHY in |
1093 | * order to perform writes to PHY registers. | |
1da177e4 LT |
1094 | * |
1095 | * INPUT: | |
c9df406f LB |
1096 | * struct mv643xx_private *mp Ethernet Port. |
1097 | * unsigned int phy_reg PHY register address offset. | |
1098 | * unsigned int value Register value. | |
1da177e4 LT |
1099 | * |
1100 | * OUTPUT: | |
c9df406f | 1101 | * Write the given value to the specified PHY register. |
1da177e4 LT |
1102 | * |
1103 | * RETURN: | |
c9df406f LB |
1104 | * false if the PHY is busy. |
1105 | * true otherwise. | |
1106 | * | |
1da177e4 | 1107 | */ |
c9df406f LB |
1108 | static void eth_port_write_smi_reg(struct mv643xx_private *mp, |
1109 | unsigned int phy_reg, unsigned int value) | |
1da177e4 | 1110 | { |
c9df406f LB |
1111 | void __iomem *smi_reg = mp->shared_smi->eth_base + SMI_REG; |
1112 | int phy_addr = ethernet_phy_get(mp); | |
1113 | unsigned long flags; | |
1da177e4 LT |
1114 | int i; |
1115 | ||
c9df406f LB |
1116 | /* the SMI register is a shared resource */ |
1117 | spin_lock_irqsave(&mp->shared_smi->phy_lock, flags); | |
1118 | ||
1119 | /* wait for the SMI register to become available */ | |
1120 | for (i = 0; readl(smi_reg) & ETH_SMI_BUSY; i++) { | |
e1bea50a | 1121 | if (i == 1000) { |
c9df406f LB |
1122 | printk("%s: PHY busy timeout\n", mp->dev->name); |
1123 | goto out; | |
1124 | } | |
e1bea50a | 1125 | udelay(10); |
1da177e4 LT |
1126 | } |
1127 | ||
c9df406f LB |
1128 | writel((phy_addr << 16) | (phy_reg << 21) | |
1129 | ETH_SMI_OPCODE_WRITE | (value & 0xffff), smi_reg); | |
1130 | out: | |
1131 | spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags); | |
1132 | } | |
1da177e4 | 1133 | |
c9df406f LB |
1134 | |
1135 | /* mib counters *************************************************************/ | |
1136 | /* | |
1137 | * eth_clear_mib_counters - Clear all MIB counters | |
1138 | * | |
1139 | * DESCRIPTION: | |
1140 | * This function clears all MIB counters of a specific ethernet port. | |
1141 | * A read from the MIB counter will reset the counter. | |
1142 | * | |
1143 | * INPUT: | |
1144 | * struct mv643xx_private *mp Ethernet Port. | |
1145 | * | |
1146 | * OUTPUT: | |
1147 | * After reading all MIB counters, the counters resets. | |
1148 | * | |
1149 | * RETURN: | |
1150 | * MIB counter value. | |
1151 | * | |
1152 | */ | |
1153 | static void eth_clear_mib_counters(struct mv643xx_private *mp) | |
1154 | { | |
1155 | unsigned int port_num = mp->port_num; | |
1156 | int i; | |
1157 | ||
1158 | /* Perform dummy reads from MIB counters */ | |
1159 | for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION; | |
1160 | i += 4) | |
3cb4667c | 1161 | rdl(mp, MIB_COUNTERS(port_num) + i); |
1da177e4 LT |
1162 | } |
1163 | ||
c9df406f | 1164 | static inline u32 read_mib(struct mv643xx_private *mp, int offset) |
d0412d96 | 1165 | { |
3cb4667c | 1166 | return rdl(mp, MIB_COUNTERS(mp->port_num) + offset); |
c9df406f | 1167 | } |
d0412d96 | 1168 | |
c9df406f LB |
1169 | static void eth_update_mib_counters(struct mv643xx_private *mp) |
1170 | { | |
1171 | struct mv643xx_mib_counters *p = &mp->mib_counters; | |
1172 | int offset; | |
d0412d96 | 1173 | |
c9df406f LB |
1174 | p->good_octets_received += |
1175 | read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW); | |
1176 | p->good_octets_received += | |
1177 | (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32; | |
1178 | ||
1179 | for (offset = ETH_MIB_BAD_OCTETS_RECEIVED; | |
1180 | offset <= ETH_MIB_FRAMES_1024_TO_MAX_OCTETS; | |
1181 | offset += 4) | |
1182 | *(u32 *)((char *)p + offset) += read_mib(mp, offset); | |
1183 | ||
1184 | p->good_octets_sent += read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_LOW); | |
1185 | p->good_octets_sent += | |
1186 | (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_HIGH) << 32; | |
1187 | ||
1188 | for (offset = ETH_MIB_GOOD_FRAMES_SENT; | |
1189 | offset <= ETH_MIB_LATE_COLLISION; | |
1190 | offset += 4) | |
1191 | *(u32 *)((char *)p + offset) += read_mib(mp, offset); | |
d0412d96 JC |
1192 | } |
1193 | ||
c9df406f LB |
1194 | |
1195 | /* ethtool ******************************************************************/ | |
1196 | struct mv643xx_stats { | |
1197 | char stat_string[ETH_GSTRING_LEN]; | |
1198 | int sizeof_stat; | |
1199 | int stat_offset; | |
1200 | }; | |
1201 | ||
1202 | #define MV643XX_STAT(m) FIELD_SIZEOF(struct mv643xx_private, m), \ | |
1203 | offsetof(struct mv643xx_private, m) | |
1204 | ||
1205 | static const struct mv643xx_stats mv643xx_gstrings_stats[] = { | |
1206 | { "rx_packets", MV643XX_STAT(stats.rx_packets) }, | |
1207 | { "tx_packets", MV643XX_STAT(stats.tx_packets) }, | |
1208 | { "rx_bytes", MV643XX_STAT(stats.rx_bytes) }, | |
1209 | { "tx_bytes", MV643XX_STAT(stats.tx_bytes) }, | |
1210 | { "rx_errors", MV643XX_STAT(stats.rx_errors) }, | |
1211 | { "tx_errors", MV643XX_STAT(stats.tx_errors) }, | |
1212 | { "rx_dropped", MV643XX_STAT(stats.rx_dropped) }, | |
1213 | { "tx_dropped", MV643XX_STAT(stats.tx_dropped) }, | |
1214 | { "good_octets_received", MV643XX_STAT(mib_counters.good_octets_received) }, | |
1215 | { "bad_octets_received", MV643XX_STAT(mib_counters.bad_octets_received) }, | |
1216 | { "internal_mac_transmit_err", MV643XX_STAT(mib_counters.internal_mac_transmit_err) }, | |
1217 | { "good_frames_received", MV643XX_STAT(mib_counters.good_frames_received) }, | |
1218 | { "bad_frames_received", MV643XX_STAT(mib_counters.bad_frames_received) }, | |
1219 | { "broadcast_frames_received", MV643XX_STAT(mib_counters.broadcast_frames_received) }, | |
1220 | { "multicast_frames_received", MV643XX_STAT(mib_counters.multicast_frames_received) }, | |
1221 | { "frames_64_octets", MV643XX_STAT(mib_counters.frames_64_octets) }, | |
1222 | { "frames_65_to_127_octets", MV643XX_STAT(mib_counters.frames_65_to_127_octets) }, | |
1223 | { "frames_128_to_255_octets", MV643XX_STAT(mib_counters.frames_128_to_255_octets) }, | |
1224 | { "frames_256_to_511_octets", MV643XX_STAT(mib_counters.frames_256_to_511_octets) }, | |
1225 | { "frames_512_to_1023_octets", MV643XX_STAT(mib_counters.frames_512_to_1023_octets) }, | |
1226 | { "frames_1024_to_max_octets", MV643XX_STAT(mib_counters.frames_1024_to_max_octets) }, | |
1227 | { "good_octets_sent", MV643XX_STAT(mib_counters.good_octets_sent) }, | |
1228 | { "good_frames_sent", MV643XX_STAT(mib_counters.good_frames_sent) }, | |
1229 | { "excessive_collision", MV643XX_STAT(mib_counters.excessive_collision) }, | |
1230 | { "multicast_frames_sent", MV643XX_STAT(mib_counters.multicast_frames_sent) }, | |
1231 | { "broadcast_frames_sent", MV643XX_STAT(mib_counters.broadcast_frames_sent) }, | |
1232 | { "unrec_mac_control_received", MV643XX_STAT(mib_counters.unrec_mac_control_received) }, | |
1233 | { "fc_sent", MV643XX_STAT(mib_counters.fc_sent) }, | |
1234 | { "good_fc_received", MV643XX_STAT(mib_counters.good_fc_received) }, | |
1235 | { "bad_fc_received", MV643XX_STAT(mib_counters.bad_fc_received) }, | |
1236 | { "undersize_received", MV643XX_STAT(mib_counters.undersize_received) }, | |
1237 | { "fragments_received", MV643XX_STAT(mib_counters.fragments_received) }, | |
1238 | { "oversize_received", MV643XX_STAT(mib_counters.oversize_received) }, | |
1239 | { "jabber_received", MV643XX_STAT(mib_counters.jabber_received) }, | |
1240 | { "mac_receive_error", MV643XX_STAT(mib_counters.mac_receive_error) }, | |
1241 | { "bad_crc_event", MV643XX_STAT(mib_counters.bad_crc_event) }, | |
1242 | { "collision", MV643XX_STAT(mib_counters.collision) }, | |
1243 | { "late_collision", MV643XX_STAT(mib_counters.late_collision) }, | |
1244 | }; | |
1245 | ||
1246 | #define MV643XX_STATS_LEN ARRAY_SIZE(mv643xx_gstrings_stats) | |
1247 | ||
d0412d96 JC |
1248 | static int mv643xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
1249 | { | |
1250 | struct mv643xx_private *mp = netdev_priv(dev); | |
1251 | int err; | |
1252 | ||
1253 | spin_lock_irq(&mp->lock); | |
1254 | err = mii_ethtool_gset(&mp->mii, cmd); | |
1255 | spin_unlock_irq(&mp->lock); | |
1256 | ||
1257 | /* The PHY may support 1000baseT_Half, but the mv643xx does not */ | |
1258 | cmd->supported &= ~SUPPORTED_1000baseT_Half; | |
1259 | cmd->advertising &= ~ADVERTISED_1000baseT_Half; | |
1260 | ||
1261 | return err; | |
1262 | } | |
1263 | ||
c9df406f | 1264 | static int mv643xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
1da177e4 LT |
1265 | { |
1266 | struct mv643xx_private *mp = netdev_priv(dev); | |
ab4384a6 DF |
1267 | int err; |
1268 | ||
c9df406f LB |
1269 | spin_lock_irq(&mp->lock); |
1270 | err = mii_ethtool_sset(&mp->mii, cmd); | |
1271 | spin_unlock_irq(&mp->lock); | |
85cf572c | 1272 | |
c9df406f LB |
1273 | return err; |
1274 | } | |
1da177e4 | 1275 | |
c9df406f LB |
1276 | static void mv643xx_get_drvinfo(struct net_device *netdev, |
1277 | struct ethtool_drvinfo *drvinfo) | |
1278 | { | |
1279 | strncpy(drvinfo->driver, mv643xx_driver_name, 32); | |
1280 | strncpy(drvinfo->version, mv643xx_driver_version, 32); | |
1281 | strncpy(drvinfo->fw_version, "N/A", 32); | |
1282 | strncpy(drvinfo->bus_info, "mv643xx", 32); | |
1283 | drvinfo->n_stats = MV643XX_STATS_LEN; | |
1284 | } | |
1da177e4 | 1285 | |
c9df406f LB |
1286 | static int mv643xx_eth_nway_restart(struct net_device *dev) |
1287 | { | |
1288 | struct mv643xx_private *mp = netdev_priv(dev); | |
1da177e4 | 1289 | |
c9df406f LB |
1290 | return mii_nway_restart(&mp->mii); |
1291 | } | |
1da177e4 | 1292 | |
c9df406f LB |
1293 | static u32 mv643xx_eth_get_link(struct net_device *dev) |
1294 | { | |
1295 | struct mv643xx_private *mp = netdev_priv(dev); | |
1da177e4 | 1296 | |
c9df406f LB |
1297 | return mii_link_ok(&mp->mii); |
1298 | } | |
1da177e4 | 1299 | |
c9df406f LB |
1300 | static void mv643xx_get_strings(struct net_device *netdev, uint32_t stringset, |
1301 | uint8_t *data) | |
1302 | { | |
1303 | int i; | |
1da177e4 | 1304 | |
c9df406f LB |
1305 | switch(stringset) { |
1306 | case ETH_SS_STATS: | |
1307 | for (i=0; i < MV643XX_STATS_LEN; i++) { | |
1308 | memcpy(data + i * ETH_GSTRING_LEN, | |
1309 | mv643xx_gstrings_stats[i].stat_string, | |
1310 | ETH_GSTRING_LEN); | |
1311 | } | |
1312 | break; | |
1313 | } | |
1314 | } | |
1da177e4 | 1315 | |
c9df406f LB |
1316 | static void mv643xx_get_ethtool_stats(struct net_device *netdev, |
1317 | struct ethtool_stats *stats, uint64_t *data) | |
1318 | { | |
1319 | struct mv643xx_private *mp = netdev->priv; | |
1320 | int i; | |
1da177e4 | 1321 | |
c9df406f | 1322 | eth_update_mib_counters(mp); |
1da177e4 | 1323 | |
c9df406f LB |
1324 | for (i = 0; i < MV643XX_STATS_LEN; i++) { |
1325 | char *p = (char *)mp+mv643xx_gstrings_stats[i].stat_offset; | |
1326 | data[i] = (mv643xx_gstrings_stats[i].sizeof_stat == | |
1327 | sizeof(uint64_t)) ? *(uint64_t *)p : *(uint32_t *)p; | |
1da177e4 | 1328 | } |
c9df406f | 1329 | } |
1da177e4 | 1330 | |
c9df406f LB |
1331 | static int mv643xx_get_sset_count(struct net_device *netdev, int sset) |
1332 | { | |
1333 | switch (sset) { | |
1334 | case ETH_SS_STATS: | |
1335 | return MV643XX_STATS_LEN; | |
1336 | default: | |
1337 | return -EOPNOTSUPP; | |
1338 | } | |
1339 | } | |
1da177e4 | 1340 | |
c9df406f LB |
1341 | static const struct ethtool_ops mv643xx_ethtool_ops = { |
1342 | .get_settings = mv643xx_get_settings, | |
1343 | .set_settings = mv643xx_set_settings, | |
1344 | .get_drvinfo = mv643xx_get_drvinfo, | |
1345 | .get_link = mv643xx_eth_get_link, | |
1346 | .set_sg = ethtool_op_set_sg, | |
1347 | .get_sset_count = mv643xx_get_sset_count, | |
1348 | .get_ethtool_stats = mv643xx_get_ethtool_stats, | |
1349 | .get_strings = mv643xx_get_strings, | |
1350 | .nway_reset = mv643xx_eth_nway_restart, | |
1351 | }; | |
1da177e4 | 1352 | |
bea3348e | 1353 | |
c9df406f LB |
1354 | /* address handling *********************************************************/ |
1355 | /* | |
1356 | * eth_port_uc_addr_get - Read the MAC address from the port's hw registers | |
1357 | */ | |
1358 | static void eth_port_uc_addr_get(struct mv643xx_private *mp, | |
1359 | unsigned char *p_addr) | |
1360 | { | |
1361 | unsigned int port_num = mp->port_num; | |
1362 | unsigned int mac_h; | |
1363 | unsigned int mac_l; | |
1da177e4 | 1364 | |
c9df406f LB |
1365 | mac_h = rdl(mp, MAC_ADDR_HIGH(port_num)); |
1366 | mac_l = rdl(mp, MAC_ADDR_LOW(port_num)); | |
1da177e4 | 1367 | |
c9df406f LB |
1368 | p_addr[0] = (mac_h >> 24) & 0xff; |
1369 | p_addr[1] = (mac_h >> 16) & 0xff; | |
1370 | p_addr[2] = (mac_h >> 8) & 0xff; | |
1371 | p_addr[3] = mac_h & 0xff; | |
1372 | p_addr[4] = (mac_l >> 8) & 0xff; | |
1373 | p_addr[5] = mac_l & 0xff; | |
1374 | } | |
1da177e4 | 1375 | |
c9df406f LB |
1376 | /* |
1377 | * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables | |
1378 | * | |
1379 | * DESCRIPTION: | |
1380 | * Go through all the DA filter tables (Unicast, Special Multicast & | |
1381 | * Other Multicast) and set each entry to 0. | |
1382 | * | |
1383 | * INPUT: | |
1384 | * struct mv643xx_private *mp Ethernet Port. | |
1385 | * | |
1386 | * OUTPUT: | |
1387 | * Multicast and Unicast packets are rejected. | |
1388 | * | |
1389 | * RETURN: | |
1390 | * None. | |
1391 | */ | |
1392 | static void eth_port_init_mac_tables(struct mv643xx_private *mp) | |
1393 | { | |
1394 | unsigned int port_num = mp->port_num; | |
1395 | int table_index; | |
1da177e4 | 1396 | |
c9df406f LB |
1397 | /* Clear DA filter unicast table (Ex_dFUT) */ |
1398 | for (table_index = 0; table_index <= 0xC; table_index += 4) | |
3cb4667c | 1399 | wrl(mp, UNICAST_TABLE(port_num) + table_index, 0); |
1da177e4 | 1400 | |
c9df406f LB |
1401 | for (table_index = 0; table_index <= 0xFC; table_index += 4) { |
1402 | /* Clear DA filter special multicast table (Ex_dFSMT) */ | |
3cb4667c | 1403 | wrl(mp, SPECIAL_MCAST_TABLE(port_num) + table_index, 0); |
c9df406f | 1404 | /* Clear DA filter other multicast table (Ex_dFOMT) */ |
3cb4667c | 1405 | wrl(mp, OTHER_MCAST_TABLE(port_num) + table_index, 0); |
c9df406f LB |
1406 | } |
1407 | } | |
d0412d96 | 1408 | |
c9df406f LB |
1409 | /* |
1410 | * The entries in each table are indexed by a hash of a packet's MAC | |
1411 | * address. One bit in each entry determines whether the packet is | |
1412 | * accepted. There are 4 entries (each 8 bits wide) in each register | |
1413 | * of the table. The bits in each entry are defined as follows: | |
1414 | * 0 Accept=1, Drop=0 | |
1415 | * 3-1 Queue (ETH_Q0=0) | |
1416 | * 7-4 Reserved = 0; | |
1417 | */ | |
1418 | static void eth_port_set_filter_table_entry(struct mv643xx_private *mp, | |
1419 | int table, unsigned char entry) | |
1420 | { | |
1421 | unsigned int table_reg; | |
1422 | unsigned int tbl_offset; | |
1423 | unsigned int reg_offset; | |
ab4384a6 | 1424 | |
c9df406f LB |
1425 | tbl_offset = (entry / 4) * 4; /* Register offset of DA table entry */ |
1426 | reg_offset = entry % 4; /* Entry offset within the register */ | |
ab4384a6 | 1427 | |
c9df406f LB |
1428 | /* Set "accepts frame bit" at specified table entry */ |
1429 | table_reg = rdl(mp, table + tbl_offset); | |
1430 | table_reg |= 0x01 << (8 * reg_offset); | |
1431 | wrl(mp, table + tbl_offset, table_reg); | |
1da177e4 LT |
1432 | } |
1433 | ||
c9df406f LB |
1434 | /* |
1435 | * eth_port_uc_addr_set - Write a MAC address into the port's hw registers | |
1436 | */ | |
1437 | static void eth_port_uc_addr_set(struct mv643xx_private *mp, | |
1438 | unsigned char *p_addr) | |
1da177e4 | 1439 | { |
c9df406f LB |
1440 | unsigned int port_num = mp->port_num; |
1441 | unsigned int mac_h; | |
1442 | unsigned int mac_l; | |
1443 | int table; | |
1da177e4 | 1444 | |
c9df406f LB |
1445 | mac_l = (p_addr[4] << 8) | (p_addr[5]); |
1446 | mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) | | |
1447 | (p_addr[3] << 0); | |
ff561eef | 1448 | |
c9df406f LB |
1449 | wrl(mp, MAC_ADDR_LOW(port_num), mac_l); |
1450 | wrl(mp, MAC_ADDR_HIGH(port_num), mac_h); | |
1da177e4 | 1451 | |
c9df406f | 1452 | /* Accept frames with this address */ |
3cb4667c | 1453 | table = UNICAST_TABLE(port_num); |
c9df406f | 1454 | eth_port_set_filter_table_entry(mp, table, p_addr[5] & 0x0f); |
1da177e4 LT |
1455 | } |
1456 | ||
c9df406f LB |
1457 | /* |
1458 | * mv643xx_eth_update_mac_address | |
1459 | * | |
1460 | * Update the MAC address of the port in the address table | |
1461 | * | |
1462 | * Input : pointer to ethernet interface network device structure | |
1463 | * Output : N/A | |
1464 | */ | |
1465 | static void mv643xx_eth_update_mac_address(struct net_device *dev) | |
1da177e4 LT |
1466 | { |
1467 | struct mv643xx_private *mp = netdev_priv(dev); | |
1da177e4 | 1468 | |
c9df406f LB |
1469 | eth_port_init_mac_tables(mp); |
1470 | eth_port_uc_addr_set(mp, dev->dev_addr); | |
1471 | } | |
1da177e4 LT |
1472 | |
1473 | /* | |
c9df406f | 1474 | * mv643xx_eth_set_mac_address |
1da177e4 | 1475 | * |
c9df406f LB |
1476 | * Change the interface's mac address. |
1477 | * No special hardware thing should be done because interface is always | |
1478 | * put in promiscuous mode. | |
1479 | * | |
1480 | * Input : pointer to ethernet interface network device structure and | |
1481 | * a pointer to the designated entry to be added to the cache. | |
1482 | * Output : zero upon success, negative upon failure | |
1da177e4 | 1483 | */ |
c9df406f | 1484 | static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr) |
1da177e4 | 1485 | { |
c9df406f | 1486 | int i; |
1da177e4 | 1487 | |
c9df406f LB |
1488 | for (i = 0; i < 6; i++) |
1489 | /* +2 is for the offset of the HW addr type */ | |
1490 | dev->dev_addr[i] = ((unsigned char *)addr)[i + 2]; | |
1491 | mv643xx_eth_update_mac_address(dev); | |
1da177e4 LT |
1492 | return 0; |
1493 | } | |
1494 | ||
1da177e4 | 1495 | /* |
c9df406f | 1496 | * eth_port_mc_addr - Multicast address settings. |
1da177e4 | 1497 | * |
c9df406f LB |
1498 | * The MV device supports multicast using two tables: |
1499 | * 1) Special Multicast Table for MAC addresses of the form | |
1500 | * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_FF). | |
1501 | * The MAC DA[7:0] bits are used as a pointer to the Special Multicast | |
1502 | * Table entries in the DA-Filter table. | |
1503 | * 2) Other Multicast Table for multicast of another type. A CRC-8bit | |
1504 | * is used as an index to the Other Multicast Table entries in the | |
1505 | * DA-Filter table. This function calculates the CRC-8bit value. | |
1506 | * In either case, eth_port_set_filter_table_entry() is then called | |
1507 | * to set to set the actual table entry. | |
1da177e4 | 1508 | */ |
c9df406f | 1509 | static void eth_port_mc_addr(struct mv643xx_private *mp, unsigned char *p_addr) |
1da177e4 | 1510 | { |
1da177e4 | 1511 | unsigned int port_num = mp->port_num; |
c9df406f LB |
1512 | unsigned int mac_h; |
1513 | unsigned int mac_l; | |
1514 | unsigned char crc_result = 0; | |
1515 | int table; | |
1516 | int mac_array[48]; | |
1517 | int crc[8]; | |
1518 | int i; | |
1da177e4 | 1519 | |
c9df406f LB |
1520 | if ((p_addr[0] == 0x01) && (p_addr[1] == 0x00) && |
1521 | (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) { | |
3cb4667c | 1522 | table = SPECIAL_MCAST_TABLE(port_num); |
c9df406f LB |
1523 | eth_port_set_filter_table_entry(mp, table, p_addr[5]); |
1524 | return; | |
1da177e4 | 1525 | } |
1da177e4 | 1526 | |
c9df406f LB |
1527 | /* Calculate CRC-8 out of the given address */ |
1528 | mac_h = (p_addr[0] << 8) | (p_addr[1]); | |
1529 | mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) | | |
1530 | (p_addr[4] << 8) | (p_addr[5] << 0); | |
1da177e4 | 1531 | |
c9df406f LB |
1532 | for (i = 0; i < 32; i++) |
1533 | mac_array[i] = (mac_l >> i) & 0x1; | |
1534 | for (i = 32; i < 48; i++) | |
1535 | mac_array[i] = (mac_h >> (i - 32)) & 0x1; | |
1da177e4 | 1536 | |
c9df406f LB |
1537 | crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ mac_array[39] ^ |
1538 | mac_array[35] ^ mac_array[34] ^ mac_array[31] ^ mac_array[30] ^ | |
1539 | mac_array[28] ^ mac_array[23] ^ mac_array[21] ^ mac_array[19] ^ | |
1540 | mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ mac_array[12] ^ | |
1541 | mac_array[8] ^ mac_array[7] ^ mac_array[6] ^ mac_array[0]; | |
1da177e4 | 1542 | |
c9df406f LB |
1543 | crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^ |
1544 | mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ mac_array[34] ^ | |
1545 | mac_array[32] ^ mac_array[30] ^ mac_array[29] ^ mac_array[28] ^ | |
1546 | mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ mac_array[21] ^ | |
1547 | mac_array[20] ^ mac_array[18] ^ mac_array[17] ^ mac_array[16] ^ | |
1548 | mac_array[15] ^ mac_array[14] ^ mac_array[13] ^ mac_array[12] ^ | |
1549 | mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ mac_array[0]; | |
f7ea3337 | 1550 | |
c9df406f LB |
1551 | crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ mac_array[43] ^ |
1552 | mac_array[42] ^ mac_array[39] ^ mac_array[37] ^ mac_array[34] ^ | |
1553 | mac_array[33] ^ mac_array[29] ^ mac_array[28] ^ mac_array[25] ^ | |
1554 | mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ mac_array[15] ^ | |
1555 | mac_array[13] ^ mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ | |
1556 | mac_array[6] ^ mac_array[2] ^ mac_array[1] ^ mac_array[0]; | |
f7ea3337 | 1557 | |
c9df406f LB |
1558 | crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^ |
1559 | mac_array[40] ^ mac_array[38] ^ mac_array[35] ^ mac_array[34] ^ | |
1560 | mac_array[30] ^ mac_array[29] ^ mac_array[26] ^ mac_array[25] ^ | |
1561 | mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ | |
1562 | mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[7] ^ | |
1563 | mac_array[3] ^ mac_array[2] ^ mac_array[1]; | |
f7ea3337 | 1564 | |
c9df406f LB |
1565 | crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[41] ^ |
1566 | mac_array[39] ^ mac_array[36] ^ mac_array[35] ^ mac_array[31] ^ | |
1567 | mac_array[30] ^ mac_array[27] ^ mac_array[26] ^ mac_array[24] ^ | |
1568 | mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ mac_array[14] ^ | |
1569 | mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ mac_array[4] ^ | |
1570 | mac_array[3] ^ mac_array[2]; | |
c8aaea25 | 1571 | |
c9df406f LB |
1572 | crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ mac_array[42] ^ |
1573 | mac_array[40] ^ mac_array[37] ^ mac_array[36] ^ mac_array[32] ^ | |
1574 | mac_array[31] ^ mac_array[28] ^ mac_array[27] ^ mac_array[25] ^ | |
1575 | mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ mac_array[15] ^ | |
1576 | mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[5] ^ | |
1577 | mac_array[4] ^ mac_array[3]; | |
c8aaea25 | 1578 | |
c9df406f LB |
1579 | crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ mac_array[41] ^ |
1580 | mac_array[38] ^ mac_array[37] ^ mac_array[33] ^ mac_array[32] ^ | |
1581 | mac_array[29] ^ mac_array[28] ^ mac_array[26] ^ mac_array[21] ^ | |
1582 | mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ mac_array[14] ^ | |
1583 | mac_array[12] ^ mac_array[10] ^ mac_array[6] ^ mac_array[5] ^ | |
1584 | mac_array[4]; | |
c8aaea25 | 1585 | |
c9df406f LB |
1586 | crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ mac_array[39] ^ |
1587 | mac_array[38] ^ mac_array[34] ^ mac_array[33] ^ mac_array[30] ^ | |
1588 | mac_array[29] ^ mac_array[27] ^ mac_array[22] ^ mac_array[20] ^ | |
1589 | mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ mac_array[13] ^ | |
1590 | mac_array[11] ^ mac_array[7] ^ mac_array[6] ^ mac_array[5]; | |
c8aaea25 | 1591 | |
c9df406f LB |
1592 | for (i = 0; i < 8; i++) |
1593 | crc_result = crc_result | (crc[i] << i); | |
1594 | ||
3cb4667c | 1595 | table = OTHER_MCAST_TABLE(port_num); |
c9df406f | 1596 | eth_port_set_filter_table_entry(mp, table, crc_result); |
c8aaea25 DF |
1597 | } |
1598 | ||
c9df406f LB |
1599 | /* |
1600 | * Set the entire multicast list based on dev->mc_list. | |
1da177e4 | 1601 | */ |
c9df406f | 1602 | static void eth_port_set_multicast_list(struct net_device *dev) |
1da177e4 | 1603 | { |
1da177e4 | 1604 | |
c9df406f LB |
1605 | struct dev_mc_list *mc_list; |
1606 | int i; | |
1607 | int table_index; | |
1608 | struct mv643xx_private *mp = netdev_priv(dev); | |
1609 | unsigned int eth_port_num = mp->port_num; | |
c8aaea25 | 1610 | |
c9df406f LB |
1611 | /* If the device is in promiscuous mode or in all multicast mode, |
1612 | * we will fully populate both multicast tables with accept. | |
1613 | * This is guaranteed to yield a match on all multicast addresses... | |
1614 | */ | |
1615 | if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) { | |
1616 | for (table_index = 0; table_index <= 0xFC; table_index += 4) { | |
1617 | /* Set all entries in DA filter special multicast | |
1618 | * table (Ex_dFSMT) | |
1619 | * Set for ETH_Q0 for now | |
1620 | * Bits | |
1621 | * 0 Accept=1, Drop=0 | |
1622 | * 3-1 Queue ETH_Q0=0 | |
1623 | * 7-4 Reserved = 0; | |
1624 | */ | |
3cb4667c | 1625 | wrl(mp, SPECIAL_MCAST_TABLE(eth_port_num) + table_index, 0x01010101); |
c8aaea25 | 1626 | |
c9df406f LB |
1627 | /* Set all entries in DA filter other multicast |
1628 | * table (Ex_dFOMT) | |
1629 | * Set for ETH_Q0 for now | |
1630 | * Bits | |
1631 | * 0 Accept=1, Drop=0 | |
1632 | * 3-1 Queue ETH_Q0=0 | |
1633 | * 7-4 Reserved = 0; | |
1634 | */ | |
3cb4667c | 1635 | wrl(mp, OTHER_MCAST_TABLE(eth_port_num) + table_index, 0x01010101); |
c9df406f LB |
1636 | } |
1637 | return; | |
1638 | } | |
c8aaea25 | 1639 | |
c9df406f LB |
1640 | /* We will clear out multicast tables every time we get the list. |
1641 | * Then add the entire new list... | |
1642 | */ | |
1643 | for (table_index = 0; table_index <= 0xFC; table_index += 4) { | |
1644 | /* Clear DA filter special multicast table (Ex_dFSMT) */ | |
3cb4667c | 1645 | wrl(mp, SPECIAL_MCAST_TABLE(eth_port_num) + table_index, 0); |
c9df406f LB |
1646 | |
1647 | /* Clear DA filter other multicast table (Ex_dFOMT) */ | |
3cb4667c | 1648 | wrl(mp, OTHER_MCAST_TABLE(eth_port_num) + table_index, 0); |
1da177e4 LT |
1649 | } |
1650 | ||
c9df406f LB |
1651 | /* Get pointer to net_device multicast list and add each one... */ |
1652 | for (i = 0, mc_list = dev->mc_list; | |
1653 | (i < 256) && (mc_list != NULL) && (i < dev->mc_count); | |
1654 | i++, mc_list = mc_list->next) | |
1655 | if (mc_list->dmi_addrlen == 6) | |
1656 | eth_port_mc_addr(mp, mc_list->dmi_addr); | |
324ff2c1 BB |
1657 | } |
1658 | ||
c9df406f LB |
1659 | /* |
1660 | * mv643xx_eth_set_rx_mode | |
c8aaea25 | 1661 | * |
c9df406f LB |
1662 | * Change from promiscuos to regular rx mode |
1663 | * | |
1664 | * Input : pointer to ethernet interface network device structure | |
1665 | * Output : N/A | |
c8aaea25 | 1666 | */ |
c9df406f | 1667 | static void mv643xx_eth_set_rx_mode(struct net_device *dev) |
c8aaea25 | 1668 | { |
c9df406f LB |
1669 | struct mv643xx_private *mp = netdev_priv(dev); |
1670 | u32 config_reg; | |
1da177e4 | 1671 | |
3cb4667c | 1672 | config_reg = rdl(mp, PORT_CONFIG(mp->port_num)); |
c9df406f | 1673 | if (dev->flags & IFF_PROMISC) |
d9a073ea | 1674 | config_reg |= UNICAST_PROMISCUOUS_MODE; |
c9df406f | 1675 | else |
d9a073ea | 1676 | config_reg &= ~UNICAST_PROMISCUOUS_MODE; |
3cb4667c | 1677 | wrl(mp, PORT_CONFIG(mp->port_num), config_reg); |
1da177e4 | 1678 | |
c9df406f LB |
1679 | eth_port_set_multicast_list(dev); |
1680 | } | |
c8aaea25 | 1681 | |
c8aaea25 | 1682 | |
c9df406f LB |
1683 | /* rx/tx queue initialisation ***********************************************/ |
1684 | /* | |
1685 | * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory. | |
1686 | * | |
1687 | * DESCRIPTION: | |
1688 | * This function prepares a Rx chained list of descriptors and packet | |
1689 | * buffers in a form of a ring. The routine must be called after port | |
1690 | * initialization routine and before port start routine. | |
1691 | * The Ethernet SDMA engine uses CPU bus addresses to access the various | |
1692 | * devices in the system (i.e. DRAM). This function uses the ethernet | |
1693 | * struct 'virtual to physical' routine (set by the user) to set the ring | |
1694 | * with physical addresses. | |
1695 | * | |
1696 | * INPUT: | |
1697 | * struct mv643xx_private *mp Ethernet Port Control srtuct. | |
1698 | * | |
1699 | * OUTPUT: | |
1700 | * The routine updates the Ethernet port control struct with information | |
1701 | * regarding the Rx descriptors and buffers. | |
1702 | * | |
1703 | * RETURN: | |
1704 | * None. | |
1705 | */ | |
1706 | static void ether_init_rx_desc_ring(struct mv643xx_private *mp) | |
1707 | { | |
1708 | volatile struct eth_rx_desc *p_rx_desc; | |
1709 | int rx_desc_num = mp->rx_ring_size; | |
1710 | int i; | |
1711 | ||
1712 | /* initialize the next_desc_ptr links in the Rx descriptors ring */ | |
1713 | p_rx_desc = (struct eth_rx_desc *)mp->p_rx_desc_area; | |
1714 | for (i = 0; i < rx_desc_num; i++) { | |
1715 | p_rx_desc[i].next_desc_ptr = mp->rx_desc_dma + | |
1716 | ((i + 1) % rx_desc_num) * sizeof(struct eth_rx_desc); | |
f7ea3337 PJ |
1717 | } |
1718 | ||
c9df406f LB |
1719 | /* Save Rx desc pointer to driver struct. */ |
1720 | mp->rx_curr_desc_q = 0; | |
1721 | mp->rx_used_desc_q = 0; | |
1da177e4 | 1722 | |
c9df406f LB |
1723 | mp->rx_desc_area_size = rx_desc_num * sizeof(struct eth_rx_desc); |
1724 | } | |
c8aaea25 | 1725 | |
c9df406f LB |
1726 | static void mv643xx_eth_free_rx_rings(struct net_device *dev) |
1727 | { | |
1728 | struct mv643xx_private *mp = netdev_priv(dev); | |
1729 | int curr; | |
c8aaea25 | 1730 | |
c9df406f LB |
1731 | /* Stop RX Queues */ |
1732 | mv643xx_eth_port_disable_rx(mp); | |
1733 | ||
1734 | /* Free preallocated skb's on RX rings */ | |
1735 | for (curr = 0; mp->rx_desc_count && curr < mp->rx_ring_size; curr++) { | |
1736 | if (mp->rx_skb[curr]) { | |
1737 | dev_kfree_skb(mp->rx_skb[curr]); | |
1738 | mp->rx_desc_count--; | |
1da177e4 | 1739 | } |
c8aaea25 | 1740 | } |
1da177e4 | 1741 | |
c9df406f LB |
1742 | if (mp->rx_desc_count) |
1743 | printk(KERN_ERR | |
1744 | "%s: Error in freeing Rx Ring. %d skb's still" | |
1745 | " stuck in RX Ring - ignoring them\n", dev->name, | |
1746 | mp->rx_desc_count); | |
1747 | /* Free RX ring */ | |
1748 | if (mp->rx_sram_size) | |
1749 | iounmap(mp->p_rx_desc_area); | |
1750 | else | |
1751 | dma_free_coherent(NULL, mp->rx_desc_area_size, | |
1752 | mp->p_rx_desc_area, mp->rx_desc_dma); | |
1753 | } | |
1da177e4 | 1754 | |
c9df406f LB |
1755 | /* |
1756 | * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory. | |
1757 | * | |
1758 | * DESCRIPTION: | |
1759 | * This function prepares a Tx chained list of descriptors and packet | |
1760 | * buffers in a form of a ring. The routine must be called after port | |
1761 | * initialization routine and before port start routine. | |
1762 | * The Ethernet SDMA engine uses CPU bus addresses to access the various | |
1763 | * devices in the system (i.e. DRAM). This function uses the ethernet | |
1764 | * struct 'virtual to physical' routine (set by the user) to set the ring | |
1765 | * with physical addresses. | |
1766 | * | |
1767 | * INPUT: | |
1768 | * struct mv643xx_private *mp Ethernet Port Control srtuct. | |
1769 | * | |
1770 | * OUTPUT: | |
1771 | * The routine updates the Ethernet port control struct with information | |
1772 | * regarding the Tx descriptors and buffers. | |
1773 | * | |
1774 | * RETURN: | |
1775 | * None. | |
1776 | */ | |
1777 | static void ether_init_tx_desc_ring(struct mv643xx_private *mp) | |
1778 | { | |
1779 | int tx_desc_num = mp->tx_ring_size; | |
1780 | struct eth_tx_desc *p_tx_desc; | |
1781 | int i; | |
1da177e4 | 1782 | |
c9df406f LB |
1783 | /* Initialize the next_desc_ptr links in the Tx descriptors ring */ |
1784 | p_tx_desc = (struct eth_tx_desc *)mp->p_tx_desc_area; | |
1785 | for (i = 0; i < tx_desc_num; i++) { | |
1786 | p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma + | |
1787 | ((i + 1) % tx_desc_num) * sizeof(struct eth_tx_desc); | |
1788 | } | |
1789 | ||
1790 | mp->tx_curr_desc_q = 0; | |
1791 | mp->tx_used_desc_q = 0; | |
1792 | ||
1793 | mp->tx_desc_area_size = tx_desc_num * sizeof(struct eth_tx_desc); | |
c8aaea25 | 1794 | } |
1da177e4 | 1795 | |
c8aaea25 | 1796 | /** |
c9df406f | 1797 | * mv643xx_eth_free_tx_descs - Free the tx desc data for completed descriptors |
c8aaea25 | 1798 | * |
c9df406f | 1799 | * If force is non-zero, frees uncompleted descriptors as well |
c8aaea25 | 1800 | */ |
c9df406f | 1801 | static int mv643xx_eth_free_tx_descs(struct net_device *dev, int force) |
c8aaea25 DF |
1802 | { |
1803 | struct mv643xx_private *mp = netdev_priv(dev); | |
c9df406f LB |
1804 | struct eth_tx_desc *desc; |
1805 | u32 cmd_sts; | |
1806 | struct sk_buff *skb; | |
c8aaea25 | 1807 | unsigned long flags; |
c9df406f LB |
1808 | int tx_index; |
1809 | dma_addr_t addr; | |
1810 | int count; | |
1811 | int released = 0; | |
1da177e4 | 1812 | |
c9df406f LB |
1813 | while (mp->tx_desc_count > 0) { |
1814 | spin_lock_irqsave(&mp->lock, flags); | |
94843566 | 1815 | |
c9df406f LB |
1816 | /* tx_desc_count might have changed before acquiring the lock */ |
1817 | if (mp->tx_desc_count <= 0) { | |
1818 | spin_unlock_irqrestore(&mp->lock, flags); | |
1819 | return released; | |
1820 | } | |
4d64e718 | 1821 | |
c9df406f LB |
1822 | tx_index = mp->tx_used_desc_q; |
1823 | desc = &mp->p_tx_desc_area[tx_index]; | |
1824 | cmd_sts = desc->cmd_sts; | |
4d64e718 | 1825 | |
c9df406f LB |
1826 | if (!force && (cmd_sts & ETH_BUFFER_OWNED_BY_DMA)) { |
1827 | spin_unlock_irqrestore(&mp->lock, flags); | |
1828 | return released; | |
1829 | } | |
1da177e4 | 1830 | |
c9df406f LB |
1831 | mp->tx_used_desc_q = (tx_index + 1) % mp->tx_ring_size; |
1832 | mp->tx_desc_count--; | |
1da177e4 | 1833 | |
c9df406f LB |
1834 | addr = desc->buf_ptr; |
1835 | count = desc->byte_cnt; | |
1836 | skb = mp->tx_skb[tx_index]; | |
1837 | if (skb) | |
1838 | mp->tx_skb[tx_index] = NULL; | |
c8aaea25 | 1839 | |
c9df406f LB |
1840 | if (cmd_sts & ETH_ERROR_SUMMARY) { |
1841 | printk("%s: Error in TX\n", dev->name); | |
1842 | dev->stats.tx_errors++; | |
1843 | } | |
1da177e4 | 1844 | |
c9df406f | 1845 | spin_unlock_irqrestore(&mp->lock, flags); |
1da177e4 | 1846 | |
c9df406f LB |
1847 | if (cmd_sts & ETH_TX_FIRST_DESC) |
1848 | dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE); | |
1849 | else | |
1850 | dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE); | |
c2e5b352 | 1851 | |
c9df406f LB |
1852 | if (skb) |
1853 | dev_kfree_skb_irq(skb); | |
63c9e549 | 1854 | |
c9df406f LB |
1855 | released = 1; |
1856 | } | |
c2e5b352 | 1857 | |
c9df406f | 1858 | return released; |
63c9e549 | 1859 | } |
63c9e549 | 1860 | |
c9df406f | 1861 | static void mv643xx_eth_free_completed_tx_descs(struct net_device *dev) |
d0412d96 JC |
1862 | { |
1863 | struct mv643xx_private *mp = netdev_priv(dev); | |
1864 | ||
c9df406f LB |
1865 | if (mv643xx_eth_free_tx_descs(dev, 0) && |
1866 | mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB) | |
1867 | netif_wake_queue(dev); | |
d0412d96 JC |
1868 | } |
1869 | ||
c9df406f | 1870 | static void mv643xx_eth_free_all_tx_descs(struct net_device *dev) |
1da177e4 | 1871 | { |
c9df406f LB |
1872 | mv643xx_eth_free_tx_descs(dev, 1); |
1873 | } | |
1da177e4 | 1874 | |
c9df406f LB |
1875 | static void mv643xx_eth_free_tx_rings(struct net_device *dev) |
1876 | { | |
1877 | struct mv643xx_private *mp = netdev_priv(dev); | |
84dd619e | 1878 | |
c9df406f LB |
1879 | /* Stop Tx Queues */ |
1880 | mv643xx_eth_port_disable_tx(mp); | |
fa3959f4 | 1881 | |
c9df406f LB |
1882 | /* Free outstanding skb's on TX ring */ |
1883 | mv643xx_eth_free_all_tx_descs(dev); | |
1da177e4 | 1884 | |
c9df406f | 1885 | BUG_ON(mp->tx_used_desc_q != mp->tx_curr_desc_q); |
1da177e4 | 1886 | |
c9df406f LB |
1887 | /* Free TX ring */ |
1888 | if (mp->tx_sram_size) | |
1889 | iounmap(mp->p_tx_desc_area); | |
1890 | else | |
1891 | dma_free_coherent(NULL, mp->tx_desc_area_size, | |
1892 | mp->p_tx_desc_area, mp->tx_desc_dma); | |
1893 | } | |
1da177e4 | 1894 | |
1da177e4 | 1895 | |
c9df406f LB |
1896 | /* netdev ops and related ***************************************************/ |
1897 | static void eth_port_reset(struct mv643xx_private *mp); | |
1da177e4 | 1898 | |
c9df406f LB |
1899 | /* Set the mv643xx port configuration register for the speed/duplex mode. */ |
1900 | static void mv643xx_eth_update_pscr(struct net_device *dev, | |
1901 | struct ethtool_cmd *ecmd) | |
1902 | { | |
1903 | struct mv643xx_private *mp = netdev_priv(dev); | |
1904 | int port_num = mp->port_num; | |
1905 | u32 o_pscr, n_pscr; | |
1906 | unsigned int queues; | |
1da177e4 | 1907 | |
3cb4667c | 1908 | o_pscr = rdl(mp, PORT_SERIAL_CONTROL(port_num)); |
c9df406f | 1909 | n_pscr = o_pscr; |
63c9e549 | 1910 | |
c9df406f LB |
1911 | /* clear speed, duplex and rx buffer size fields */ |
1912 | n_pscr &= ~(SET_MII_SPEED_TO_100 | | |
1913 | SET_GMII_SPEED_TO_1000 | | |
1914 | SET_FULL_DUPLEX_MODE | | |
1915 | MAX_RX_PACKET_MASK); | |
1da177e4 | 1916 | |
c9df406f LB |
1917 | if (ecmd->duplex == DUPLEX_FULL) |
1918 | n_pscr |= SET_FULL_DUPLEX_MODE; | |
1da177e4 | 1919 | |
c9df406f LB |
1920 | if (ecmd->speed == SPEED_1000) |
1921 | n_pscr |= SET_GMII_SPEED_TO_1000 | | |
1922 | MAX_RX_PACKET_9700BYTE; | |
1923 | else { | |
1924 | if (ecmd->speed == SPEED_100) | |
1925 | n_pscr |= SET_MII_SPEED_TO_100; | |
1926 | n_pscr |= MAX_RX_PACKET_1522BYTE; | |
1927 | } | |
1da177e4 | 1928 | |
c9df406f LB |
1929 | if (n_pscr != o_pscr) { |
1930 | if ((o_pscr & SERIAL_PORT_ENABLE) == 0) | |
3cb4667c | 1931 | wrl(mp, PORT_SERIAL_CONTROL(port_num), n_pscr); |
c9df406f LB |
1932 | else { |
1933 | queues = mv643xx_eth_port_disable_tx(mp); | |
1da177e4 | 1934 | |
c9df406f | 1935 | o_pscr &= ~SERIAL_PORT_ENABLE; |
3cb4667c LB |
1936 | wrl(mp, PORT_SERIAL_CONTROL(port_num), o_pscr); |
1937 | wrl(mp, PORT_SERIAL_CONTROL(port_num), n_pscr); | |
1938 | wrl(mp, PORT_SERIAL_CONTROL(port_num), n_pscr); | |
c9df406f LB |
1939 | if (queues) |
1940 | mv643xx_eth_port_enable_tx(mp, queues); | |
1941 | } | |
1942 | } | |
1943 | } | |
84dd619e | 1944 | |
c9df406f LB |
1945 | /* |
1946 | * mv643xx_eth_int_handler | |
1947 | * | |
1948 | * Main interrupt handler for the gigbit ethernet ports | |
1949 | * | |
1950 | * Input : irq - irq number (not used) | |
1951 | * dev_id - a pointer to the required interface's data structure | |
1952 | * regs - not used | |
1953 | * Output : N/A | |
1954 | */ | |
f2ce825d | 1955 | |
c9df406f LB |
1956 | static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id) |
1957 | { | |
1958 | struct net_device *dev = (struct net_device *)dev_id; | |
1959 | struct mv643xx_private *mp = netdev_priv(dev); | |
1960 | u32 eth_int_cause, eth_int_cause_ext = 0; | |
1961 | unsigned int port_num = mp->port_num; | |
ce4e2e45 | 1962 | |
c9df406f | 1963 | /* Read interrupt cause registers */ |
073a345c LB |
1964 | eth_int_cause = rdl(mp, INT_CAUSE(port_num)) & (INT_RX | INT_EXT); |
1965 | if (eth_int_cause & INT_EXT) { | |
3cb4667c | 1966 | eth_int_cause_ext = rdl(mp, INT_CAUSE_EXT(port_num)) |
073a345c | 1967 | & (INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX); |
3cb4667c | 1968 | wrl(mp, INT_CAUSE_EXT(port_num), ~eth_int_cause_ext); |
c9df406f | 1969 | } |
1da177e4 | 1970 | |
c9df406f | 1971 | /* PHY status changed */ |
073a345c | 1972 | if (eth_int_cause_ext & (INT_EXT_LINK | INT_EXT_PHY)) { |
c9df406f | 1973 | struct ethtool_cmd cmd; |
1da177e4 | 1974 | |
c9df406f LB |
1975 | if (mii_link_ok(&mp->mii)) { |
1976 | mii_ethtool_gset(&mp->mii, &cmd); | |
1977 | mv643xx_eth_update_pscr(dev, &cmd); | |
073a345c | 1978 | mv643xx_eth_port_enable_tx(mp, 1); |
c9df406f LB |
1979 | if (!netif_carrier_ok(dev)) { |
1980 | netif_carrier_on(dev); | |
1981 | if (mp->tx_ring_size - mp->tx_desc_count >= | |
1982 | MAX_DESCS_PER_SKB) | |
1983 | netif_wake_queue(dev); | |
1984 | } | |
1985 | } else if (netif_carrier_ok(dev)) { | |
1986 | netif_stop_queue(dev); | |
1987 | netif_carrier_off(dev); | |
1988 | } | |
1989 | } | |
1da177e4 | 1990 | |
c9df406f | 1991 | #ifdef MV643XX_NAPI |
073a345c | 1992 | if (eth_int_cause & INT_RX) { |
c9df406f | 1993 | /* schedule the NAPI poll routine to maintain port */ |
073a345c | 1994 | wrl(mp, INT_MASK(port_num), 0x00000000); |
1da177e4 | 1995 | |
c9df406f | 1996 | /* wait for previous write to complete */ |
3cb4667c | 1997 | rdl(mp, INT_MASK(port_num)); |
1da177e4 | 1998 | |
c9df406f | 1999 | netif_rx_schedule(dev, &mp->napi); |
84dd619e | 2000 | } |
c9df406f | 2001 | #else |
073a345c | 2002 | if (eth_int_cause & INT_RX) |
c9df406f LB |
2003 | mv643xx_eth_receive_queue(dev, INT_MAX); |
2004 | #endif | |
073a345c | 2005 | if (eth_int_cause_ext & INT_EXT_TX) |
c9df406f | 2006 | mv643xx_eth_free_completed_tx_descs(dev); |
1da177e4 | 2007 | |
f2ce825d | 2008 | /* |
c9df406f LB |
2009 | * If no real interrupt occured, exit. |
2010 | * This can happen when using gigE interrupt coalescing mechanism. | |
f2ce825d | 2011 | */ |
c9df406f LB |
2012 | if ((eth_int_cause == 0x0) && (eth_int_cause_ext == 0x0)) |
2013 | return IRQ_NONE; | |
1da177e4 | 2014 | |
c9df406f | 2015 | return IRQ_HANDLED; |
1da177e4 LT |
2016 | } |
2017 | ||
1da177e4 | 2018 | /* |
c9df406f | 2019 | * ethernet_phy_reset - Reset Ethernet port PHY. |
1da177e4 LT |
2020 | * |
2021 | * DESCRIPTION: | |
c9df406f | 2022 | * This routine utilizes the SMI interface to reset the ethernet port PHY. |
1da177e4 LT |
2023 | * |
2024 | * INPUT: | |
c9df406f | 2025 | * struct mv643xx_private *mp Ethernet Port. |
1da177e4 LT |
2026 | * |
2027 | * OUTPUT: | |
c9df406f | 2028 | * The PHY is reset. |
1da177e4 LT |
2029 | * |
2030 | * RETURN: | |
2031 | * None. | |
c9df406f | 2032 | * |
1da177e4 | 2033 | */ |
c9df406f | 2034 | static void ethernet_phy_reset(struct mv643xx_private *mp) |
1da177e4 | 2035 | { |
c9df406f | 2036 | unsigned int phy_reg_data; |
1da177e4 | 2037 | |
c9df406f LB |
2038 | /* Reset the PHY */ |
2039 | eth_port_read_smi_reg(mp, 0, &phy_reg_data); | |
2040 | phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */ | |
2041 | eth_port_write_smi_reg(mp, 0, phy_reg_data); | |
1da177e4 | 2042 | |
c9df406f LB |
2043 | /* wait for PHY to come out of reset */ |
2044 | do { | |
2045 | udelay(1); | |
2046 | eth_port_read_smi_reg(mp, 0, &phy_reg_data); | |
2047 | } while (phy_reg_data & 0x8000); | |
1da177e4 LT |
2048 | } |
2049 | ||
2050 | /* | |
2051 | * eth_port_start - Start the Ethernet port activity. | |
2052 | * | |
2053 | * DESCRIPTION: | |
2054 | * This routine prepares the Ethernet port for Rx and Tx activity: | |
2055 | * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that | |
2056 | * has been initialized a descriptor's ring (using | |
2057 | * ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx) | |
2058 | * 2. Initialize and enable the Ethernet configuration port by writing to | |
2059 | * the port's configuration and command registers. | |
2060 | * 3. Initialize and enable the SDMA by writing to the SDMA's | |
2061 | * configuration and command registers. After completing these steps, | |
2062 | * the ethernet port SDMA can starts to perform Rx and Tx activities. | |
2063 | * | |
2064 | * Note: Each Rx and Tx queue descriptor's list must be initialized prior | |
2065 | * to calling this function (use ether_init_tx_desc_ring for Tx queues | |
2066 | * and ether_init_rx_desc_ring for Rx queues). | |
2067 | * | |
2068 | * INPUT: | |
ed9b5d45 | 2069 | * dev - a pointer to the required interface |
1da177e4 LT |
2070 | * |
2071 | * OUTPUT: | |
2072 | * Ethernet port is ready to receive and transmit. | |
2073 | * | |
2074 | * RETURN: | |
2075 | * None. | |
2076 | */ | |
ed9b5d45 | 2077 | static void eth_port_start(struct net_device *dev) |
1da177e4 | 2078 | { |
ed9b5d45 | 2079 | struct mv643xx_private *mp = netdev_priv(dev); |
1da177e4 LT |
2080 | unsigned int port_num = mp->port_num; |
2081 | int tx_curr_desc, rx_curr_desc; | |
d0412d96 JC |
2082 | u32 pscr; |
2083 | struct ethtool_cmd ethtool_cmd; | |
1da177e4 LT |
2084 | |
2085 | /* Assignment of Tx CTRP of given queue */ | |
2086 | tx_curr_desc = mp->tx_curr_desc_q; | |
3cb4667c | 2087 | wrl(mp, TXQ_CURRENT_DESC_PTR(port_num), |
1da177e4 LT |
2088 | (u32)((struct eth_tx_desc *)mp->tx_desc_dma + tx_curr_desc)); |
2089 | ||
2090 | /* Assignment of Rx CRDP of given queue */ | |
2091 | rx_curr_desc = mp->rx_curr_desc_q; | |
3cb4667c | 2092 | wrl(mp, RXQ_CURRENT_DESC_PTR(port_num), |
1da177e4 LT |
2093 | (u32)((struct eth_rx_desc *)mp->rx_desc_dma + rx_curr_desc)); |
2094 | ||
2095 | /* Add the assigned Ethernet address to the port's address table */ | |
afdb57a2 | 2096 | eth_port_uc_addr_set(mp, dev->dev_addr); |
1da177e4 | 2097 | |
d9a073ea LB |
2098 | /* |
2099 | * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast | |
2100 | * frames to RX queue #0. | |
2101 | */ | |
2102 | wrl(mp, PORT_CONFIG(port_num), 0x00000000); | |
01999873 | 2103 | |
376489a2 LB |
2104 | /* |
2105 | * Treat BPDUs as normal multicasts, and disable partition mode. | |
2106 | */ | |
2107 | wrl(mp, PORT_CONFIG_EXT(port_num), 0x00000000); | |
1da177e4 | 2108 | |
3cb4667c | 2109 | pscr = rdl(mp, PORT_SERIAL_CONTROL(port_num)); |
01999873 | 2110 | |
e4d00fa9 | 2111 | pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS); |
3cb4667c | 2112 | wrl(mp, PORT_SERIAL_CONTROL(port_num), pscr); |
1da177e4 | 2113 | |
e4d00fa9 LB |
2114 | pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL | |
2115 | DISABLE_AUTO_NEG_SPEED_GMII | | |
2beff77b | 2116 | DISABLE_AUTO_NEG_FOR_DUPLEX | |
e4d00fa9 LB |
2117 | DO_NOT_FORCE_LINK_FAIL | |
2118 | SERIAL_PORT_CONTROL_RESERVED; | |
1da177e4 | 2119 | |
3cb4667c | 2120 | wrl(mp, PORT_SERIAL_CONTROL(port_num), pscr); |
1da177e4 | 2121 | |
e4d00fa9 | 2122 | pscr |= SERIAL_PORT_ENABLE; |
3cb4667c | 2123 | wrl(mp, PORT_SERIAL_CONTROL(port_num), pscr); |
1da177e4 LT |
2124 | |
2125 | /* Assign port SDMA configuration */ | |
3cb4667c | 2126 | wrl(mp, SDMA_CONFIG(port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE); |
1da177e4 LT |
2127 | |
2128 | /* Enable port Rx. */ | |
073a345c | 2129 | mv643xx_eth_port_enable_rx(mp, 1); |
8f543718 DF |
2130 | |
2131 | /* Disable port bandwidth limits by clearing MTU register */ | |
3cb4667c | 2132 | wrl(mp, TX_BW_MTU(port_num), 0); |
d0412d96 JC |
2133 | |
2134 | /* save phy settings across reset */ | |
2135 | mv643xx_get_settings(dev, ðtool_cmd); | |
afdb57a2 | 2136 | ethernet_phy_reset(mp); |
d0412d96 | 2137 | mv643xx_set_settings(dev, ðtool_cmd); |
1da177e4 LT |
2138 | } |
2139 | ||
c9df406f LB |
2140 | #ifdef MV643XX_COAL |
2141 | ||
1da177e4 | 2142 | /* |
c9df406f LB |
2143 | * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path |
2144 | * | |
2145 | * DESCRIPTION: | |
2146 | * This routine sets the RX coalescing interrupt mechanism parameter. | |
2147 | * This parameter is a timeout counter, that counts in 64 t_clk | |
2148 | * chunks ; that when timeout event occurs a maskable interrupt | |
2149 | * occurs. | |
2150 | * The parameter is calculated using the tClk of the MV-643xx chip | |
2151 | * , and the required delay of the interrupt in usec. | |
2152 | * | |
2153 | * INPUT: | |
2154 | * struct mv643xx_private *mp Ethernet port | |
2155 | * unsigned int delay Delay in usec | |
2156 | * | |
2157 | * OUTPUT: | |
2158 | * Interrupt coalescing mechanism value is set in MV-643xx chip. | |
2159 | * | |
2160 | * RETURN: | |
2161 | * The interrupt coalescing value set in the gigE port. | |
2162 | * | |
1da177e4 | 2163 | */ |
c9df406f LB |
2164 | static unsigned int eth_port_set_rx_coal(struct mv643xx_private *mp, |
2165 | unsigned int delay) | |
1da177e4 | 2166 | { |
afdb57a2 | 2167 | unsigned int port_num = mp->port_num; |
c9df406f | 2168 | unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64; |
1da177e4 | 2169 | |
c9df406f | 2170 | /* Set RX Coalescing mechanism */ |
3cb4667c | 2171 | wrl(mp, SDMA_CONFIG(port_num), |
c9df406f | 2172 | ((coal & 0x3fff) << 8) | |
3cb4667c | 2173 | (rdl(mp, SDMA_CONFIG(port_num)) |
c9df406f | 2174 | & 0xffc000ff)); |
1da177e4 | 2175 | |
c9df406f | 2176 | return coal; |
1da177e4 | 2177 | } |
c9df406f | 2178 | #endif |
1da177e4 LT |
2179 | |
2180 | /* | |
c9df406f LB |
2181 | * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path |
2182 | * | |
2183 | * DESCRIPTION: | |
2184 | * This routine sets the TX coalescing interrupt mechanism parameter. | |
2185 | * This parameter is a timeout counter, that counts in 64 t_clk | |
2186 | * chunks ; that when timeout event occurs a maskable interrupt | |
2187 | * occurs. | |
2188 | * The parameter is calculated using the t_cLK frequency of the | |
2189 | * MV-643xx chip and the required delay in the interrupt in uSec | |
2190 | * | |
2191 | * INPUT: | |
2192 | * struct mv643xx_private *mp Ethernet port | |
2193 | * unsigned int delay Delay in uSeconds | |
2194 | * | |
2195 | * OUTPUT: | |
2196 | * Interrupt coalescing mechanism value is set in MV-643xx chip. | |
2197 | * | |
2198 | * RETURN: | |
2199 | * The interrupt coalescing value set in the gigE port. | |
2200 | * | |
1da177e4 | 2201 | */ |
c9df406f LB |
2202 | static unsigned int eth_port_set_tx_coal(struct mv643xx_private *mp, |
2203 | unsigned int delay) | |
1da177e4 | 2204 | { |
c9df406f | 2205 | unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64; |
1da177e4 | 2206 | |
c9df406f | 2207 | /* Set TX Coalescing mechanism */ |
3cb4667c | 2208 | wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), coal << 4); |
1da177e4 | 2209 | |
c9df406f | 2210 | return coal; |
1da177e4 LT |
2211 | } |
2212 | ||
16e03018 | 2213 | /* |
c9df406f LB |
2214 | * eth_port_init - Initialize the Ethernet port driver |
2215 | * | |
2216 | * DESCRIPTION: | |
2217 | * This function prepares the ethernet port to start its activity: | |
2218 | * 1) Completes the ethernet port driver struct initialization toward port | |
2219 | * start routine. | |
2220 | * 2) Resets the device to a quiescent state in case of warm reboot. | |
2221 | * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM. | |
2222 | * 4) Clean MAC tables. The reset status of those tables is unknown. | |
2223 | * 5) Set PHY address. | |
2224 | * Note: Call this routine prior to eth_port_start routine and after | |
2225 | * setting user values in the user fields of Ethernet port control | |
2226 | * struct. | |
2227 | * | |
2228 | * INPUT: | |
2229 | * struct mv643xx_private *mp Ethernet port control struct | |
2230 | * | |
2231 | * OUTPUT: | |
2232 | * See description. | |
2233 | * | |
2234 | * RETURN: | |
2235 | * None. | |
16e03018 | 2236 | */ |
c9df406f | 2237 | static void eth_port_init(struct mv643xx_private *mp) |
16e03018 | 2238 | { |
c9df406f | 2239 | mp->rx_resource_err = 0; |
16e03018 | 2240 | |
c9df406f | 2241 | eth_port_reset(mp); |
16e03018 | 2242 | |
c9df406f | 2243 | eth_port_init_mac_tables(mp); |
16e03018 DF |
2244 | } |
2245 | ||
2246 | /* | |
c9df406f | 2247 | * mv643xx_eth_open |
16e03018 | 2248 | * |
c9df406f LB |
2249 | * This function is called when openning the network device. The function |
2250 | * should initialize all the hardware, initialize cyclic Rx/Tx | |
2251 | * descriptors chain and buffers and allocate an IRQ to the network | |
2252 | * device. | |
2253 | * | |
2254 | * Input : a pointer to the network device structure | |
2255 | * | |
2256 | * Output : zero of success , nonzero if fails. | |
16e03018 | 2257 | */ |
c9df406f LB |
2258 | |
2259 | static int mv643xx_eth_open(struct net_device *dev) | |
16e03018 | 2260 | { |
c9df406f | 2261 | struct mv643xx_private *mp = netdev_priv(dev); |
afdb57a2 | 2262 | unsigned int port_num = mp->port_num; |
c9df406f LB |
2263 | unsigned int size; |
2264 | int err; | |
16e03018 | 2265 | |
c9df406f | 2266 | /* Clear any pending ethernet port interrupts */ |
3cb4667c LB |
2267 | wrl(mp, INT_CAUSE(port_num), 0); |
2268 | wrl(mp, INT_CAUSE_EXT(port_num), 0); | |
c9df406f | 2269 | /* wait for previous write to complete */ |
3cb4667c | 2270 | rdl(mp, INT_CAUSE_EXT(port_num)); |
c9df406f LB |
2271 | |
2272 | err = request_irq(dev->irq, mv643xx_eth_int_handler, | |
2273 | IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev); | |
2274 | if (err) { | |
2275 | printk(KERN_ERR "%s: Can not assign IRQ\n", dev->name); | |
2276 | return -EAGAIN; | |
16e03018 DF |
2277 | } |
2278 | ||
c9df406f | 2279 | eth_port_init(mp); |
16e03018 | 2280 | |
c9df406f LB |
2281 | memset(&mp->timeout, 0, sizeof(struct timer_list)); |
2282 | mp->timeout.function = mv643xx_eth_rx_refill_descs_timer_wrapper; | |
2283 | mp->timeout.data = (unsigned long)dev; | |
16e03018 | 2284 | |
c9df406f LB |
2285 | /* Allocate RX and TX skb rings */ |
2286 | mp->rx_skb = kmalloc(sizeof(*mp->rx_skb) * mp->rx_ring_size, | |
2287 | GFP_KERNEL); | |
2288 | if (!mp->rx_skb) { | |
2289 | printk(KERN_ERR "%s: Cannot allocate Rx skb ring\n", dev->name); | |
2290 | err = -ENOMEM; | |
2291 | goto out_free_irq; | |
2292 | } | |
2293 | mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size, | |
2294 | GFP_KERNEL); | |
2295 | if (!mp->tx_skb) { | |
2296 | printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name); | |
2297 | err = -ENOMEM; | |
2298 | goto out_free_rx_skb; | |
2299 | } | |
16e03018 | 2300 | |
c9df406f LB |
2301 | /* Allocate TX ring */ |
2302 | mp->tx_desc_count = 0; | |
2303 | size = mp->tx_ring_size * sizeof(struct eth_tx_desc); | |
2304 | mp->tx_desc_area_size = size; | |
16e03018 | 2305 | |
c9df406f LB |
2306 | if (mp->tx_sram_size) { |
2307 | mp->p_tx_desc_area = ioremap(mp->tx_sram_addr, | |
2308 | mp->tx_sram_size); | |
2309 | mp->tx_desc_dma = mp->tx_sram_addr; | |
2310 | } else | |
2311 | mp->p_tx_desc_area = dma_alloc_coherent(NULL, size, | |
2312 | &mp->tx_desc_dma, | |
2313 | GFP_KERNEL); | |
16e03018 | 2314 | |
c9df406f LB |
2315 | if (!mp->p_tx_desc_area) { |
2316 | printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n", | |
2317 | dev->name, size); | |
2318 | err = -ENOMEM; | |
2319 | goto out_free_tx_skb; | |
2320 | } | |
2321 | BUG_ON((u32) mp->p_tx_desc_area & 0xf); /* check 16-byte alignment */ | |
2322 | memset((void *)mp->p_tx_desc_area, 0, mp->tx_desc_area_size); | |
16e03018 | 2323 | |
c9df406f | 2324 | ether_init_tx_desc_ring(mp); |
16e03018 | 2325 | |
c9df406f LB |
2326 | /* Allocate RX ring */ |
2327 | mp->rx_desc_count = 0; | |
2328 | size = mp->rx_ring_size * sizeof(struct eth_rx_desc); | |
2329 | mp->rx_desc_area_size = size; | |
16e03018 | 2330 | |
c9df406f LB |
2331 | if (mp->rx_sram_size) { |
2332 | mp->p_rx_desc_area = ioremap(mp->rx_sram_addr, | |
2333 | mp->rx_sram_size); | |
2334 | mp->rx_desc_dma = mp->rx_sram_addr; | |
2335 | } else | |
2336 | mp->p_rx_desc_area = dma_alloc_coherent(NULL, size, | |
2337 | &mp->rx_desc_dma, | |
2338 | GFP_KERNEL); | |
16e03018 | 2339 | |
c9df406f LB |
2340 | if (!mp->p_rx_desc_area) { |
2341 | printk(KERN_ERR "%s: Cannot allocate Rx ring (size %d bytes)\n", | |
2342 | dev->name, size); | |
2343 | printk(KERN_ERR "%s: Freeing previously allocated TX queues...", | |
2344 | dev->name); | |
2345 | if (mp->rx_sram_size) | |
2346 | iounmap(mp->p_tx_desc_area); | |
2347 | else | |
2348 | dma_free_coherent(NULL, mp->tx_desc_area_size, | |
2349 | mp->p_tx_desc_area, mp->tx_desc_dma); | |
2350 | err = -ENOMEM; | |
2351 | goto out_free_tx_skb; | |
2352 | } | |
2353 | memset((void *)mp->p_rx_desc_area, 0, size); | |
16e03018 | 2354 | |
c9df406f | 2355 | ether_init_rx_desc_ring(mp); |
16e03018 | 2356 | |
c9df406f | 2357 | mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */ |
16e03018 | 2358 | |
c9df406f LB |
2359 | #ifdef MV643XX_NAPI |
2360 | napi_enable(&mp->napi); | |
2361 | #endif | |
16e03018 | 2362 | |
c9df406f | 2363 | eth_port_start(dev); |
16e03018 | 2364 | |
c9df406f | 2365 | /* Interrupt Coalescing */ |
b4de9051 | 2366 | |
c9df406f LB |
2367 | #ifdef MV643XX_COAL |
2368 | mp->rx_int_coal = | |
2369 | eth_port_set_rx_coal(mp, MV643XX_RX_COAL); | |
2370 | #endif | |
2371 | ||
2372 | mp->tx_int_coal = | |
2373 | eth_port_set_tx_coal(mp, MV643XX_TX_COAL); | |
16e03018 | 2374 | |
c9df406f | 2375 | /* Unmask phy and link status changes interrupts */ |
073a345c | 2376 | wrl(mp, INT_MASK_EXT(port_num), INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX); |
16e03018 | 2377 | |
c9df406f | 2378 | /* Unmask RX buffer and TX end interrupt */ |
073a345c | 2379 | wrl(mp, INT_MASK(port_num), INT_RX | INT_EXT); |
16e03018 | 2380 | |
c9df406f LB |
2381 | return 0; |
2382 | ||
2383 | out_free_tx_skb: | |
2384 | kfree(mp->tx_skb); | |
2385 | out_free_rx_skb: | |
2386 | kfree(mp->rx_skb); | |
2387 | out_free_irq: | |
2388 | free_irq(dev->irq, dev); | |
2389 | ||
2390 | return err; | |
16e03018 DF |
2391 | } |
2392 | ||
1da177e4 | 2393 | /* |
c9df406f | 2394 | * eth_port_reset - Reset Ethernet port |
1da177e4 LT |
2395 | * |
2396 | * DESCRIPTION: | |
c9df406f LB |
2397 | * This routine resets the chip by aborting any SDMA engine activity and |
2398 | * clearing the MIB counters. The Receiver and the Transmit unit are in | |
2399 | * idle state after this command is performed and the port is disabled. | |
1da177e4 LT |
2400 | * |
2401 | * INPUT: | |
afdb57a2 | 2402 | * struct mv643xx_private *mp Ethernet Port. |
1da177e4 LT |
2403 | * |
2404 | * OUTPUT: | |
c9df406f | 2405 | * Channel activity is halted. |
1da177e4 LT |
2406 | * |
2407 | * RETURN: | |
2408 | * None. | |
c9df406f | 2409 | * |
1da177e4 | 2410 | */ |
c9df406f | 2411 | static void eth_port_reset(struct mv643xx_private *mp) |
1da177e4 | 2412 | { |
afdb57a2 | 2413 | unsigned int port_num = mp->port_num; |
c9df406f | 2414 | unsigned int reg_data; |
1da177e4 | 2415 | |
c9df406f LB |
2416 | mv643xx_eth_port_disable_tx(mp); |
2417 | mv643xx_eth_port_disable_rx(mp); | |
1da177e4 | 2418 | |
c9df406f LB |
2419 | /* Clear all MIB counters */ |
2420 | eth_clear_mib_counters(mp); | |
2421 | ||
2422 | /* Reset the Enable bit in the Configuration Register */ | |
3cb4667c | 2423 | reg_data = rdl(mp, PORT_SERIAL_CONTROL(port_num)); |
c9df406f LB |
2424 | reg_data &= ~(SERIAL_PORT_ENABLE | |
2425 | DO_NOT_FORCE_LINK_FAIL | | |
2426 | FORCE_LINK_PASS); | |
3cb4667c | 2427 | wrl(mp, PORT_SERIAL_CONTROL(port_num), reg_data); |
1da177e4 LT |
2428 | } |
2429 | ||
2430 | /* | |
c9df406f | 2431 | * mv643xx_eth_stop |
1da177e4 | 2432 | * |
c9df406f LB |
2433 | * This function is used when closing the network device. |
2434 | * It updates the hardware, | |
2435 | * release all memory that holds buffers and descriptors and release the IRQ. | |
2436 | * Input : a pointer to the device structure | |
2437 | * Output : zero if success , nonzero if fails | |
1da177e4 | 2438 | */ |
c9df406f LB |
2439 | |
2440 | static int mv643xx_eth_stop(struct net_device *dev) | |
1da177e4 | 2441 | { |
c9df406f | 2442 | struct mv643xx_private *mp = netdev_priv(dev); |
afdb57a2 | 2443 | unsigned int port_num = mp->port_num; |
1da177e4 | 2444 | |
c9df406f | 2445 | /* Mask all interrupts on ethernet port */ |
073a345c | 2446 | wrl(mp, INT_MASK(port_num), 0x00000000); |
c9df406f | 2447 | /* wait for previous write to complete */ |
3cb4667c | 2448 | rdl(mp, INT_MASK(port_num)); |
1da177e4 | 2449 | |
c9df406f LB |
2450 | #ifdef MV643XX_NAPI |
2451 | napi_disable(&mp->napi); | |
2452 | #endif | |
2453 | netif_carrier_off(dev); | |
2454 | netif_stop_queue(dev); | |
1da177e4 | 2455 | |
c9df406f | 2456 | eth_port_reset(mp); |
1da177e4 | 2457 | |
c9df406f LB |
2458 | mv643xx_eth_free_tx_rings(dev); |
2459 | mv643xx_eth_free_rx_rings(dev); | |
1da177e4 | 2460 | |
c9df406f | 2461 | free_irq(dev->irq, dev); |
1da177e4 | 2462 | |
c9df406f | 2463 | return 0; |
1da177e4 LT |
2464 | } |
2465 | ||
c9df406f | 2466 | static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
1da177e4 | 2467 | { |
c9df406f | 2468 | struct mv643xx_private *mp = netdev_priv(dev); |
1da177e4 | 2469 | |
c9df406f | 2470 | return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL); |
1da177e4 LT |
2471 | } |
2472 | ||
2473 | /* | |
c9df406f | 2474 | * Changes MTU (maximum transfer unit) of the gigabit ethenret port |
1da177e4 | 2475 | * |
c9df406f LB |
2476 | * Input : pointer to ethernet interface network device structure |
2477 | * new mtu size | |
2478 | * Output : 0 upon success, -EINVAL upon failure | |
1da177e4 | 2479 | */ |
c9df406f | 2480 | static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu) |
1da177e4 | 2481 | { |
c9df406f LB |
2482 | if ((new_mtu > 9500) || (new_mtu < 64)) |
2483 | return -EINVAL; | |
1da177e4 | 2484 | |
c9df406f LB |
2485 | dev->mtu = new_mtu; |
2486 | if (!netif_running(dev)) | |
2487 | return 0; | |
1da177e4 | 2488 | |
c9df406f LB |
2489 | /* |
2490 | * Stop and then re-open the interface. This will allocate RX | |
2491 | * skbs of the new MTU. | |
2492 | * There is a possible danger that the open will not succeed, | |
2493 | * due to memory being full, which might fail the open function. | |
2494 | */ | |
2495 | mv643xx_eth_stop(dev); | |
2496 | if (mv643xx_eth_open(dev)) { | |
2497 | printk(KERN_ERR "%s: Fatal error on opening device\n", | |
2498 | dev->name); | |
2499 | } | |
2500 | ||
2501 | return 0; | |
1da177e4 LT |
2502 | } |
2503 | ||
2504 | /* | |
c9df406f | 2505 | * mv643xx_eth_tx_timeout_task |
1da177e4 | 2506 | * |
c9df406f | 2507 | * Actual routine to reset the adapter when a timeout on Tx has occurred |
1da177e4 | 2508 | */ |
c9df406f | 2509 | static void mv643xx_eth_tx_timeout_task(struct work_struct *ugly) |
1da177e4 | 2510 | { |
c9df406f LB |
2511 | struct mv643xx_private *mp = container_of(ugly, struct mv643xx_private, |
2512 | tx_timeout_task); | |
2513 | struct net_device *dev = mp->dev; | |
1da177e4 | 2514 | |
c9df406f LB |
2515 | if (!netif_running(dev)) |
2516 | return; | |
1da177e4 | 2517 | |
c9df406f LB |
2518 | netif_stop_queue(dev); |
2519 | ||
2520 | eth_port_reset(mp); | |
2521 | eth_port_start(dev); | |
2522 | ||
2523 | if (mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB) | |
2524 | netif_wake_queue(dev); | |
2525 | } | |
2526 | ||
2527 | /* | |
2528 | * mv643xx_eth_tx_timeout | |
1da177e4 | 2529 | * |
c9df406f | 2530 | * Called upon a timeout on transmitting a packet |
1da177e4 | 2531 | * |
c9df406f LB |
2532 | * Input : pointer to ethernet interface network device structure. |
2533 | * Output : N/A | |
1da177e4 | 2534 | */ |
c9df406f | 2535 | static void mv643xx_eth_tx_timeout(struct net_device *dev) |
1da177e4 | 2536 | { |
c9df406f | 2537 | struct mv643xx_private *mp = netdev_priv(dev); |
1da177e4 | 2538 | |
c9df406f | 2539 | printk(KERN_INFO "%s: TX timeout ", dev->name); |
d0412d96 | 2540 | |
c9df406f LB |
2541 | /* Do the reset outside of interrupt context */ |
2542 | schedule_work(&mp->tx_timeout_task); | |
1da177e4 LT |
2543 | } |
2544 | ||
c9df406f LB |
2545 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2546 | static void mv643xx_netpoll(struct net_device *netdev) | |
9f8dd319 | 2547 | { |
c9df406f LB |
2548 | struct mv643xx_private *mp = netdev_priv(netdev); |
2549 | int port_num = mp->port_num; | |
2550 | ||
073a345c | 2551 | wrl(mp, INT_MASK(port_num), 0x00000000); |
c9df406f | 2552 | /* wait for previous write to complete */ |
3cb4667c | 2553 | rdl(mp, INT_MASK(port_num)); |
c9df406f LB |
2554 | |
2555 | mv643xx_eth_int_handler(netdev->irq, netdev); | |
2556 | ||
073a345c | 2557 | wrl(mp, INT_MASK(port_num), INT_RX | INT_CAUSE_EXT); |
9f8dd319 | 2558 | } |
c9df406f | 2559 | #endif |
9f8dd319 | 2560 | |
c9df406f LB |
2561 | /* |
2562 | * Wrappers for MII support library. | |
2563 | */ | |
2564 | static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location) | |
9f8dd319 | 2565 | { |
c9df406f LB |
2566 | struct mv643xx_private *mp = netdev_priv(dev); |
2567 | int val; | |
2568 | ||
2569 | eth_port_read_smi_reg(mp, location, &val); | |
2570 | return val; | |
9f8dd319 DF |
2571 | } |
2572 | ||
c9df406f | 2573 | static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val) |
9f8dd319 | 2574 | { |
c9df406f LB |
2575 | struct mv643xx_private *mp = netdev_priv(dev); |
2576 | eth_port_write_smi_reg(mp, location, val); | |
2577 | } | |
9f8dd319 | 2578 | |
9f8dd319 | 2579 | |
c9df406f LB |
2580 | /* platform glue ************************************************************/ |
2581 | static void mv643xx_eth_conf_mbus_windows(struct mv643xx_shared_private *msp, | |
2582 | struct mbus_dram_target_info *dram) | |
2583 | { | |
2584 | void __iomem *base = msp->eth_base; | |
2585 | u32 win_enable; | |
2586 | u32 win_protect; | |
2587 | int i; | |
9f8dd319 | 2588 | |
c9df406f LB |
2589 | for (i = 0; i < 6; i++) { |
2590 | writel(0, base + WINDOW_BASE(i)); | |
2591 | writel(0, base + WINDOW_SIZE(i)); | |
2592 | if (i < 4) | |
2593 | writel(0, base + WINDOW_REMAP_HIGH(i)); | |
9f8dd319 DF |
2594 | } |
2595 | ||
c9df406f LB |
2596 | win_enable = 0x3f; |
2597 | win_protect = 0; | |
2598 | ||
2599 | for (i = 0; i < dram->num_cs; i++) { | |
2600 | struct mbus_dram_window *cs = dram->cs + i; | |
2601 | ||
2602 | writel((cs->base & 0xffff0000) | | |
2603 | (cs->mbus_attr << 8) | | |
2604 | dram->mbus_dram_target_id, base + WINDOW_BASE(i)); | |
2605 | writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i)); | |
2606 | ||
2607 | win_enable &= ~(1 << i); | |
2608 | win_protect |= 3 << (2 * i); | |
2609 | } | |
2610 | ||
2611 | writel(win_enable, base + WINDOW_BAR_ENABLE); | |
2612 | msp->win_protect = win_protect; | |
9f8dd319 DF |
2613 | } |
2614 | ||
c9df406f | 2615 | static int mv643xx_eth_shared_probe(struct platform_device *pdev) |
9f8dd319 | 2616 | { |
c9df406f LB |
2617 | static int mv643xx_version_printed = 0; |
2618 | struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data; | |
2619 | struct mv643xx_shared_private *msp; | |
2620 | struct resource *res; | |
2621 | int ret; | |
9f8dd319 | 2622 | |
c9df406f LB |
2623 | if (!mv643xx_version_printed++) |
2624 | printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n"); | |
9f8dd319 | 2625 | |
c9df406f LB |
2626 | ret = -EINVAL; |
2627 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2628 | if (res == NULL) | |
2629 | goto out; | |
9f8dd319 | 2630 | |
c9df406f LB |
2631 | ret = -ENOMEM; |
2632 | msp = kmalloc(sizeof(*msp), GFP_KERNEL); | |
2633 | if (msp == NULL) | |
2634 | goto out; | |
2635 | memset(msp, 0, sizeof(*msp)); | |
2636 | ||
2637 | msp->eth_base = ioremap(res->start, res->end - res->start + 1); | |
2638 | if (msp->eth_base == NULL) | |
2639 | goto out_free; | |
2640 | ||
2641 | spin_lock_init(&msp->phy_lock); | |
2642 | msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000; | |
2643 | ||
2644 | platform_set_drvdata(pdev, msp); | |
2645 | ||
2646 | /* | |
2647 | * (Re-)program MBUS remapping windows if we are asked to. | |
2648 | */ | |
2649 | if (pd != NULL && pd->dram != NULL) | |
2650 | mv643xx_eth_conf_mbus_windows(msp, pd->dram); | |
2651 | ||
2652 | return 0; | |
2653 | ||
2654 | out_free: | |
2655 | kfree(msp); | |
2656 | out: | |
2657 | return ret; | |
2658 | } | |
2659 | ||
2660 | static int mv643xx_eth_shared_remove(struct platform_device *pdev) | |
2661 | { | |
2662 | struct mv643xx_shared_private *msp = platform_get_drvdata(pdev); | |
2663 | ||
2664 | iounmap(msp->eth_base); | |
2665 | kfree(msp); | |
2666 | ||
2667 | return 0; | |
9f8dd319 DF |
2668 | } |
2669 | ||
c9df406f LB |
2670 | static struct platform_driver mv643xx_eth_shared_driver = { |
2671 | .probe = mv643xx_eth_shared_probe, | |
2672 | .remove = mv643xx_eth_shared_remove, | |
2673 | .driver = { | |
2674 | .name = MV643XX_ETH_SHARED_NAME, | |
2675 | .owner = THIS_MODULE, | |
2676 | }, | |
2677 | }; | |
2678 | ||
1da177e4 | 2679 | /* |
c9df406f | 2680 | * ethernet_phy_set - Set the ethernet port PHY address. |
1da177e4 LT |
2681 | * |
2682 | * DESCRIPTION: | |
c9df406f | 2683 | * This routine sets the given ethernet port PHY address. |
1da177e4 LT |
2684 | * |
2685 | * INPUT: | |
afdb57a2 | 2686 | * struct mv643xx_private *mp Ethernet Port. |
c9df406f | 2687 | * int phy_addr PHY address. |
1da177e4 LT |
2688 | * |
2689 | * OUTPUT: | |
c9df406f | 2690 | * None. |
1da177e4 LT |
2691 | * |
2692 | * RETURN: | |
2693 | * None. | |
2694 | * | |
2695 | */ | |
c9df406f | 2696 | static void ethernet_phy_set(struct mv643xx_private *mp, int phy_addr) |
1da177e4 | 2697 | { |
c9df406f LB |
2698 | u32 reg_data; |
2699 | int addr_shift = 5 * mp->port_num; | |
1da177e4 | 2700 | |
3cb4667c | 2701 | reg_data = rdl(mp, PHY_ADDR); |
c9df406f LB |
2702 | reg_data &= ~(0x1f << addr_shift); |
2703 | reg_data |= (phy_addr & 0x1f) << addr_shift; | |
3cb4667c | 2704 | wrl(mp, PHY_ADDR, reg_data); |
1da177e4 LT |
2705 | } |
2706 | ||
1da177e4 | 2707 | /* |
c9df406f | 2708 | * ethernet_phy_get - Get the ethernet port PHY address. |
1da177e4 LT |
2709 | * |
2710 | * DESCRIPTION: | |
c9df406f | 2711 | * This routine returns the given ethernet port PHY address. |
1da177e4 LT |
2712 | * |
2713 | * INPUT: | |
afdb57a2 | 2714 | * struct mv643xx_private *mp Ethernet Port. |
1da177e4 LT |
2715 | * |
2716 | * OUTPUT: | |
c9df406f | 2717 | * None. |
1da177e4 LT |
2718 | * |
2719 | * RETURN: | |
c9df406f | 2720 | * PHY address. |
1da177e4 LT |
2721 | * |
2722 | */ | |
c9df406f | 2723 | static int ethernet_phy_get(struct mv643xx_private *mp) |
1da177e4 | 2724 | { |
c9df406f | 2725 | unsigned int reg_data; |
1da177e4 | 2726 | |
3cb4667c | 2727 | reg_data = rdl(mp, PHY_ADDR); |
1da177e4 | 2728 | |
c9df406f | 2729 | return ((reg_data >> (5 * mp->port_num)) & 0x1f); |
1da177e4 LT |
2730 | } |
2731 | ||
2732 | /* | |
c9df406f | 2733 | * ethernet_phy_detect - Detect whether a phy is present |
1da177e4 LT |
2734 | * |
2735 | * DESCRIPTION: | |
c9df406f LB |
2736 | * This function tests whether there is a PHY present on |
2737 | * the specified port. | |
1da177e4 LT |
2738 | * |
2739 | * INPUT: | |
afdb57a2 | 2740 | * struct mv643xx_private *mp Ethernet Port. |
1da177e4 LT |
2741 | * |
2742 | * OUTPUT: | |
c9df406f | 2743 | * None |
1da177e4 LT |
2744 | * |
2745 | * RETURN: | |
c9df406f LB |
2746 | * 0 on success |
2747 | * -ENODEV on failure | |
1da177e4 LT |
2748 | * |
2749 | */ | |
c9df406f | 2750 | static int ethernet_phy_detect(struct mv643xx_private *mp) |
1da177e4 | 2751 | { |
c9df406f LB |
2752 | unsigned int phy_reg_data0; |
2753 | int auto_neg; | |
1da177e4 | 2754 | |
c9df406f LB |
2755 | eth_port_read_smi_reg(mp, 0, &phy_reg_data0); |
2756 | auto_neg = phy_reg_data0 & 0x1000; | |
2757 | phy_reg_data0 ^= 0x1000; /* invert auto_neg */ | |
2758 | eth_port_write_smi_reg(mp, 0, phy_reg_data0); | |
1da177e4 | 2759 | |
c9df406f LB |
2760 | eth_port_read_smi_reg(mp, 0, &phy_reg_data0); |
2761 | if ((phy_reg_data0 & 0x1000) == auto_neg) | |
2762 | return -ENODEV; /* change didn't take */ | |
1da177e4 | 2763 | |
c9df406f LB |
2764 | phy_reg_data0 ^= 0x1000; |
2765 | eth_port_write_smi_reg(mp, 0, phy_reg_data0); | |
2766 | return 0; | |
1da177e4 LT |
2767 | } |
2768 | ||
c9df406f LB |
2769 | static void mv643xx_init_ethtool_cmd(struct net_device *dev, int phy_address, |
2770 | int speed, int duplex, | |
2771 | struct ethtool_cmd *cmd) | |
c28a4f89 | 2772 | { |
c28a4f89 JC |
2773 | struct mv643xx_private *mp = netdev_priv(dev); |
2774 | ||
c9df406f | 2775 | memset(cmd, 0, sizeof(*cmd)); |
c28a4f89 | 2776 | |
c9df406f LB |
2777 | cmd->port = PORT_MII; |
2778 | cmd->transceiver = XCVR_INTERNAL; | |
2779 | cmd->phy_address = phy_address; | |
2780 | ||
2781 | if (speed == 0) { | |
2782 | cmd->autoneg = AUTONEG_ENABLE; | |
2783 | /* mii lib checks, but doesn't use speed on AUTONEG_ENABLE */ | |
2784 | cmd->speed = SPEED_100; | |
2785 | cmd->advertising = ADVERTISED_10baseT_Half | | |
2786 | ADVERTISED_10baseT_Full | | |
2787 | ADVERTISED_100baseT_Half | | |
2788 | ADVERTISED_100baseT_Full; | |
2789 | if (mp->mii.supports_gmii) | |
2790 | cmd->advertising |= ADVERTISED_1000baseT_Full; | |
2791 | } else { | |
2792 | cmd->autoneg = AUTONEG_DISABLE; | |
2793 | cmd->speed = speed; | |
2794 | cmd->duplex = duplex; | |
2795 | } | |
c28a4f89 JC |
2796 | } |
2797 | ||
c9df406f LB |
2798 | /*/ |
2799 | * mv643xx_eth_probe | |
1da177e4 | 2800 | * |
c9df406f LB |
2801 | * First function called after registering the network device. |
2802 | * It's purpose is to initialize the device as an ethernet device, | |
2803 | * fill the ethernet device structure with pointers * to functions, | |
2804 | * and set the MAC address of the interface | |
1da177e4 | 2805 | * |
c9df406f LB |
2806 | * Input : struct device * |
2807 | * Output : -ENOMEM if failed , 0 if success | |
1da177e4 | 2808 | */ |
c9df406f | 2809 | static int mv643xx_eth_probe(struct platform_device *pdev) |
1da177e4 | 2810 | { |
c9df406f LB |
2811 | struct mv643xx_eth_platform_data *pd; |
2812 | int port_num; | |
2813 | struct mv643xx_private *mp; | |
2814 | struct net_device *dev; | |
2815 | u8 *p; | |
2816 | struct resource *res; | |
2817 | int err; | |
2818 | struct ethtool_cmd cmd; | |
2819 | int duplex = DUPLEX_HALF; | |
2820 | int speed = 0; /* default to auto-negotiation */ | |
2821 | DECLARE_MAC_BUF(mac); | |
1da177e4 | 2822 | |
c9df406f LB |
2823 | pd = pdev->dev.platform_data; |
2824 | if (pd == NULL) { | |
2825 | printk(KERN_ERR "No mv643xx_eth_platform_data\n"); | |
2826 | return -ENODEV; | |
2827 | } | |
1da177e4 | 2828 | |
c9df406f LB |
2829 | if (pd->shared == NULL) { |
2830 | printk(KERN_ERR "No mv643xx_eth_platform_data->shared\n"); | |
2831 | return -ENODEV; | |
2832 | } | |
8f518703 | 2833 | |
c9df406f LB |
2834 | dev = alloc_etherdev(sizeof(struct mv643xx_private)); |
2835 | if (!dev) | |
2836 | return -ENOMEM; | |
1da177e4 | 2837 | |
c9df406f | 2838 | platform_set_drvdata(pdev, dev); |
1da177e4 | 2839 | |
c9df406f LB |
2840 | mp = netdev_priv(dev); |
2841 | mp->dev = dev; | |
2842 | #ifdef MV643XX_NAPI | |
2843 | netif_napi_add(dev, &mp->napi, mv643xx_poll, 64); | |
2844 | #endif | |
1da177e4 | 2845 | |
c9df406f LB |
2846 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
2847 | BUG_ON(!res); | |
2848 | dev->irq = res->start; | |
1da177e4 | 2849 | |
c9df406f LB |
2850 | dev->open = mv643xx_eth_open; |
2851 | dev->stop = mv643xx_eth_stop; | |
2852 | dev->hard_start_xmit = mv643xx_eth_start_xmit; | |
2853 | dev->set_mac_address = mv643xx_eth_set_mac_address; | |
2854 | dev->set_multicast_list = mv643xx_eth_set_rx_mode; | |
2855 | ||
2856 | /* No need to Tx Timeout */ | |
2857 | dev->tx_timeout = mv643xx_eth_tx_timeout; | |
2858 | ||
2859 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2860 | dev->poll_controller = mv643xx_netpoll; | |
2861 | #endif | |
2862 | ||
2863 | dev->watchdog_timeo = 2 * HZ; | |
2864 | dev->base_addr = 0; | |
2865 | dev->change_mtu = mv643xx_eth_change_mtu; | |
2866 | dev->do_ioctl = mv643xx_eth_do_ioctl; | |
2867 | SET_ETHTOOL_OPS(dev, &mv643xx_ethtool_ops); | |
1da177e4 | 2868 | |
c9df406f LB |
2869 | #ifdef MV643XX_CHECKSUM_OFFLOAD_TX |
2870 | #ifdef MAX_SKB_FRAGS | |
b4de9051 | 2871 | /* |
c9df406f LB |
2872 | * Zero copy can only work if we use Discovery II memory. Else, we will |
2873 | * have to map the buffers to ISA memory which is only 16 MB | |
b4de9051 | 2874 | */ |
c9df406f LB |
2875 | dev->features = NETIF_F_SG | NETIF_F_IP_CSUM; |
2876 | #endif | |
2877 | #endif | |
1da177e4 | 2878 | |
c9df406f LB |
2879 | /* Configure the timeout task */ |
2880 | INIT_WORK(&mp->tx_timeout_task, mv643xx_eth_tx_timeout_task); | |
1da177e4 | 2881 | |
c9df406f | 2882 | spin_lock_init(&mp->lock); |
1da177e4 | 2883 | |
c9df406f LB |
2884 | mp->shared = platform_get_drvdata(pd->shared); |
2885 | port_num = mp->port_num = pd->port_number; | |
8f518703 | 2886 | |
c9df406f LB |
2887 | if (mp->shared->win_protect) |
2888 | wrl(mp, WINDOW_PROTECT(port_num), mp->shared->win_protect); | |
1da177e4 | 2889 | |
c9df406f LB |
2890 | mp->shared_smi = mp->shared; |
2891 | if (pd->shared_smi != NULL) | |
2892 | mp->shared_smi = platform_get_drvdata(pd->shared_smi); | |
2893 | ||
2894 | /* set default config values */ | |
2895 | eth_port_uc_addr_get(mp, dev->dev_addr); | |
2896 | mp->rx_ring_size = PORT_DEFAULT_RECEIVE_QUEUE_SIZE; | |
2897 | mp->tx_ring_size = PORT_DEFAULT_TRANSMIT_QUEUE_SIZE; | |
2898 | ||
2899 | if (is_valid_ether_addr(pd->mac_addr)) | |
2900 | memcpy(dev->dev_addr, pd->mac_addr, 6); | |
2901 | ||
2902 | if (pd->phy_addr || pd->force_phy_addr) | |
2903 | ethernet_phy_set(mp, pd->phy_addr); | |
8f518703 | 2904 | |
c9df406f LB |
2905 | if (pd->rx_queue_size) |
2906 | mp->rx_ring_size = pd->rx_queue_size; | |
1da177e4 | 2907 | |
c9df406f LB |
2908 | if (pd->tx_queue_size) |
2909 | mp->tx_ring_size = pd->tx_queue_size; | |
1da177e4 | 2910 | |
c9df406f LB |
2911 | if (pd->tx_sram_size) { |
2912 | mp->tx_sram_size = pd->tx_sram_size; | |
2913 | mp->tx_sram_addr = pd->tx_sram_addr; | |
2914 | } | |
1da177e4 | 2915 | |
c9df406f LB |
2916 | if (pd->rx_sram_size) { |
2917 | mp->rx_sram_size = pd->rx_sram_size; | |
2918 | mp->rx_sram_addr = pd->rx_sram_addr; | |
2919 | } | |
1da177e4 | 2920 | |
c9df406f LB |
2921 | duplex = pd->duplex; |
2922 | speed = pd->speed; | |
1da177e4 | 2923 | |
c9df406f LB |
2924 | /* Hook up MII support for ethtool */ |
2925 | mp->mii.dev = dev; | |
2926 | mp->mii.mdio_read = mv643xx_mdio_read; | |
2927 | mp->mii.mdio_write = mv643xx_mdio_write; | |
2928 | mp->mii.phy_id = ethernet_phy_get(mp); | |
2929 | mp->mii.phy_id_mask = 0x3f; | |
2930 | mp->mii.reg_num_mask = 0x1f; | |
1da177e4 | 2931 | |
c9df406f LB |
2932 | err = ethernet_phy_detect(mp); |
2933 | if (err) { | |
2934 | pr_debug("%s: No PHY detected at addr %d\n", | |
2935 | dev->name, ethernet_phy_get(mp)); | |
2936 | goto out; | |
2937 | } | |
1da177e4 | 2938 | |
c9df406f LB |
2939 | ethernet_phy_reset(mp); |
2940 | mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii); | |
2941 | mv643xx_init_ethtool_cmd(dev, mp->mii.phy_id, speed, duplex, &cmd); | |
2942 | mv643xx_eth_update_pscr(dev, &cmd); | |
2943 | mv643xx_set_settings(dev, &cmd); | |
8f518703 | 2944 | |
c9df406f LB |
2945 | SET_NETDEV_DEV(dev, &pdev->dev); |
2946 | err = register_netdev(dev); | |
2947 | if (err) | |
2948 | goto out; | |
1da177e4 | 2949 | |
c9df406f LB |
2950 | p = dev->dev_addr; |
2951 | printk(KERN_NOTICE | |
2952 | "%s: port %d with MAC address %s\n", | |
2953 | dev->name, port_num, print_mac(mac, p)); | |
1da177e4 | 2954 | |
c9df406f LB |
2955 | if (dev->features & NETIF_F_SG) |
2956 | printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name); | |
1da177e4 | 2957 | |
c9df406f LB |
2958 | if (dev->features & NETIF_F_IP_CSUM) |
2959 | printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n", | |
2960 | dev->name); | |
1da177e4 | 2961 | |
c9df406f LB |
2962 | #ifdef MV643XX_CHECKSUM_OFFLOAD_TX |
2963 | printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name); | |
2964 | #endif | |
1da177e4 | 2965 | |
c9df406f LB |
2966 | #ifdef MV643XX_COAL |
2967 | printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n", | |
2968 | dev->name); | |
2969 | #endif | |
1da177e4 | 2970 | |
c9df406f LB |
2971 | #ifdef MV643XX_NAPI |
2972 | printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name); | |
2973 | #endif | |
1da177e4 | 2974 | |
c9df406f LB |
2975 | if (mp->tx_sram_size > 0) |
2976 | printk(KERN_NOTICE "%s: Using SRAM\n", dev->name); | |
1da177e4 | 2977 | |
c9df406f | 2978 | return 0; |
1da177e4 | 2979 | |
c9df406f LB |
2980 | out: |
2981 | free_netdev(dev); | |
1da177e4 | 2982 | |
c9df406f | 2983 | return err; |
1da177e4 LT |
2984 | } |
2985 | ||
c9df406f | 2986 | static int mv643xx_eth_remove(struct platform_device *pdev) |
1da177e4 | 2987 | { |
c9df406f | 2988 | struct net_device *dev = platform_get_drvdata(pdev); |
1da177e4 | 2989 | |
c9df406f LB |
2990 | unregister_netdev(dev); |
2991 | flush_scheduled_work(); | |
2992 | ||
2993 | free_netdev(dev); | |
2994 | platform_set_drvdata(pdev, NULL); | |
2995 | return 0; | |
1da177e4 LT |
2996 | } |
2997 | ||
c9df406f | 2998 | static void mv643xx_eth_shutdown(struct platform_device *pdev) |
d0412d96 | 2999 | { |
c9df406f | 3000 | struct net_device *dev = platform_get_drvdata(pdev); |
d0412d96 | 3001 | struct mv643xx_private *mp = netdev_priv(dev); |
c9df406f | 3002 | unsigned int port_num = mp->port_num; |
d0412d96 | 3003 | |
c9df406f | 3004 | /* Mask all interrupts on ethernet port */ |
3cb4667c LB |
3005 | wrl(mp, INT_MASK(port_num), 0); |
3006 | rdl(mp, INT_MASK(port_num)); | |
c9df406f LB |
3007 | |
3008 | eth_port_reset(mp); | |
d0412d96 JC |
3009 | } |
3010 | ||
c9df406f LB |
3011 | static struct platform_driver mv643xx_eth_driver = { |
3012 | .probe = mv643xx_eth_probe, | |
3013 | .remove = mv643xx_eth_remove, | |
3014 | .shutdown = mv643xx_eth_shutdown, | |
3015 | .driver = { | |
3016 | .name = MV643XX_ETH_NAME, | |
3017 | .owner = THIS_MODULE, | |
3018 | }, | |
3019 | }; | |
3020 | ||
3021 | /* | |
3022 | * mv643xx_init_module | |
3023 | * | |
3024 | * Registers the network drivers into the Linux kernel | |
3025 | * | |
3026 | * Input : N/A | |
3027 | * | |
3028 | * Output : N/A | |
3029 | */ | |
3030 | static int __init mv643xx_init_module(void) | |
d0412d96 | 3031 | { |
c9df406f | 3032 | int rc; |
d0412d96 | 3033 | |
c9df406f LB |
3034 | rc = platform_driver_register(&mv643xx_eth_shared_driver); |
3035 | if (!rc) { | |
3036 | rc = platform_driver_register(&mv643xx_eth_driver); | |
3037 | if (rc) | |
3038 | platform_driver_unregister(&mv643xx_eth_shared_driver); | |
3039 | } | |
3040 | return rc; | |
d0412d96 JC |
3041 | } |
3042 | ||
c9df406f LB |
3043 | /* |
3044 | * mv643xx_cleanup_module | |
3045 | * | |
3046 | * Registers the network drivers into the Linux kernel | |
3047 | * | |
3048 | * Input : N/A | |
3049 | * | |
3050 | * Output : N/A | |
3051 | */ | |
3052 | static void __exit mv643xx_cleanup_module(void) | |
d0412d96 | 3053 | { |
c9df406f LB |
3054 | platform_driver_unregister(&mv643xx_eth_driver); |
3055 | platform_driver_unregister(&mv643xx_eth_shared_driver); | |
d0412d96 JC |
3056 | } |
3057 | ||
c9df406f LB |
3058 | module_init(mv643xx_init_module); |
3059 | module_exit(mv643xx_cleanup_module); | |
1da177e4 | 3060 | |
c9df406f LB |
3061 | MODULE_LICENSE("GPL"); |
3062 | MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani" | |
3063 | " and Dale Farnsworth"); | |
3064 | MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX"); | |
3065 | MODULE_ALIAS("platform:" MV643XX_ETH_NAME); | |
3066 | MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME); |