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mv643xx_eth: kill FUNC_RET_STATUS/pkt_info
[linux-2.6-block.git] / drivers / net / mv643xx_eth.c
CommitLineData
1da177e4 1/*
9c1bbdfe 2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
1da177e4
LT		 3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
4547fa61
LB		 6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
1da177e4
LT		 8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
3bb8a18a 10 * written by Manish Lachwani
1da177e4
LT		 11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
c8aaea25 14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
1da177e4
LT		 15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
4547fa61
LB		 20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
1da177e4
LT		 23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36 */
a779d38c 37
1da177e4
LT		 38#include <linux/init.h>
39#include <linux/dma-mapping.h>
b6298c22 40#include <linux/in.h>
1da177e4
LT		 41#include <linux/tcp.h>
42#include <linux/udp.h>
43#include <linux/etherdevice.h>
1da177e4
LT		 44#include <linux/delay.h>
45#include <linux/ethtool.h>
d052d1be 46#include <linux/platform_device.h>
fbd6a754
LB		 47#include <linux/module.h>
48#include <linux/kernel.h>
49#include <linux/spinlock.h>
50#include <linux/workqueue.h>
51#include <linux/mii.h>
fbd6a754 52#include <linux/mv643xx_eth.h>
1da177e4
LT		 53#include <asm/io.h>
54#include <asm/types.h>
1da177e4 55#include <asm/system.h>
fbd6a754 56
e5371493
LB		 57static char mv643xx_eth_driver_name[] = "mv643xx_eth";
58static char mv643xx_eth_driver_version[] = "1.0";
c9df406f 59
e5371493
LB		 60#define MV643XX_ETH_CHECKSUM_OFFLOAD_TX
61#define MV643XX_ETH_NAPI
62#define MV643XX_ETH_TX_FAST_REFILL
63#undef MV643XX_ETH_COAL
fbd6a754 64
e5371493
LB		 65#define MV643XX_ETH_TX_COAL 100
66#ifdef MV643XX_ETH_COAL
67#define MV643XX_ETH_RX_COAL 100
fbd6a754
LB		 68#endif
69
e5371493 70#ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
fbd6a754
LB		 71#define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
72#else
73#define MAX_DESCS_PER_SKB 1
74#endif
75
76#define ETH_VLAN_HLEN 4
77#define ETH_FCS_LEN 4
78#define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */
79#define ETH_WRAPPER_LEN (ETH_HW_IP_ALIGN + ETH_HLEN + \
80 ETH_VLAN_HLEN + ETH_FCS_LEN)
81#define ETH_RX_SKB_SIZE (dev->mtu + ETH_WRAPPER_LEN + \
82 dma_get_cache_alignment())
83
84/*
85 * Registers shared between all ports.
86 */
3cb4667c
LB		 87#define PHY_ADDR 0x0000
88#define SMI_REG 0x0004
89#define WINDOW_BASE(w) (0x0200 + ((w) << 3))
90#define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
91#define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
92#define WINDOW_BAR_ENABLE 0x0290
93#define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
fbd6a754
LB		 94
95/*
96 * Per-port registers.
97 */
3cb4667c 98#define PORT_CONFIG(p) (0x0400 + ((p) << 10))
d9a073ea 99#define UNICAST_PROMISCUOUS_MODE 0x00000001
3cb4667c
LB		 100#define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
101#define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
102#define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
103#define SDMA_CONFIG(p) (0x041c + ((p) << 10))
104#define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
105#define PORT_STATUS(p) (0x0444 + ((p) << 10))
a2a41689 106#define TX_FIFO_EMPTY 0x00000400
3cb4667c
LB		 107#define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
108#define TX_BW_MTU(p) (0x0458 + ((p) << 10))
109#define INT_CAUSE(p) (0x0460 + ((p) << 10))
073a345c
LB		 110#define INT_RX 0x00000804
111#define INT_EXT 0x00000002
3cb4667c 112#define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
073a345c
LB		 113#define INT_EXT_LINK 0x00100000
114#define INT_EXT_PHY 0x00010000
115#define INT_EXT_TX_ERROR_0 0x00000100
116#define INT_EXT_TX_0 0x00000001
117#define INT_EXT_TX 0x00000101
3cb4667c
LB		 118#define INT_MASK(p) (0x0468 + ((p) << 10))
119#define INT_MASK_EXT(p) (0x046c + ((p) << 10))
120#define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
121#define RXQ_CURRENT_DESC_PTR(p) (0x060c + ((p) << 10))
122#define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
123#define TXQ_CURRENT_DESC_PTR(p) (0x06c0 + ((p) << 10))
124#define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
125#define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
126#define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
127#define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
fbd6a754 128
2679a550
LB		 129
130/*
131 * SDMA configuration register.
132 */
fbd6a754 133#define RX_BURST_SIZE_4_64BIT (2 << 1)
fbd6a754 134#define BLM_RX_NO_SWAP (1 << 4)
fbd6a754 135#define BLM_TX_NO_SWAP (1 << 5)
fbd6a754 136#define TX_BURST_SIZE_4_64BIT (2 << 22)
fbd6a754
LB		 137
138#if defined(__BIG_ENDIAN)
139#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
140 RX_BURST_SIZE_4_64BIT | \
fbd6a754
LB		 141 TX_BURST_SIZE_4_64BIT
142#elif defined(__LITTLE_ENDIAN)
143#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
144 RX_BURST_SIZE_4_64BIT | \
145 BLM_RX_NO_SWAP | \
146 BLM_TX_NO_SWAP | \
fbd6a754
LB		 147 TX_BURST_SIZE_4_64BIT
148#else
149#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
150#endif
151
2beff77b
LB		 152
153/*
154 * Port serial control register.
155 */
156#define SET_MII_SPEED_TO_100 (1 << 24)
157#define SET_GMII_SPEED_TO_1000 (1 << 23)
158#define SET_FULL_DUPLEX_MODE (1 << 21)
fbd6a754 159#define MAX_RX_PACKET_1522BYTE (1 << 17)
fbd6a754
LB		 160#define MAX_RX_PACKET_9700BYTE (5 << 17)
161#define MAX_RX_PACKET_MASK (7 << 17)
2beff77b
LB		 162#define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
163#define DO_NOT_FORCE_LINK_FAIL (1 << 10)
164#define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
165#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
166#define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
167#define FORCE_LINK_PASS (1 << 1)
168#define SERIAL_PORT_ENABLE (1 << 0)
fbd6a754 169
cc9754b3
LB		 170#define DEFAULT_RX_QUEUE_SIZE 400
171#define DEFAULT_TX_QUEUE_SIZE 800
fbd6a754 172
fbd6a754 173/* SMI reg */
cc9754b3
LB		 174#define SMI_BUSY 0x10000000 /* 0 - Write, 1 - Read */
175#define SMI_READ_VALID 0x08000000 /* 0 - Write, 1 - Read */
176#define SMI_OPCODE_WRITE 0 /* Completion of Read */
177#define SMI_OPCODE_READ 0x04000000 /* Operation is in progress */
fbd6a754 178
fbd6a754 179
7ca72a3b
LB		 180/*
181 * RX/TX descriptors.
fbd6a754
LB		 182 */
183#if defined(__BIG_ENDIAN)
cc9754b3 184struct rx_desc {
fbd6a754
LB		 185 u16 byte_cnt; /* Descriptor buffer byte count */
186 u16 buf_size; /* Buffer size */
187 u32 cmd_sts; /* Descriptor command status */
188 u32 next_desc_ptr; /* Next descriptor pointer */
189 u32 buf_ptr; /* Descriptor buffer pointer */
190};
191
cc9754b3 192struct tx_desc {
fbd6a754
LB		 193 u16 byte_cnt; /* buffer byte count */
194 u16 l4i_chk; /* CPU provided TCP checksum */
195 u32 cmd_sts; /* Command/status field */
196 u32 next_desc_ptr; /* Pointer to next descriptor */
197 u32 buf_ptr; /* pointer to buffer for this descriptor*/
198};
199#elif defined(__LITTLE_ENDIAN)
cc9754b3 200struct rx_desc {
fbd6a754
LB		 201 u32 cmd_sts; /* Descriptor command status */
202 u16 buf_size; /* Buffer size */
203 u16 byte_cnt; /* Descriptor buffer byte count */
204 u32 buf_ptr; /* Descriptor buffer pointer */
205 u32 next_desc_ptr; /* Next descriptor pointer */
206};
207
cc9754b3 208struct tx_desc {
fbd6a754
LB		 209 u32 cmd_sts; /* Command/status field */
210 u16 l4i_chk; /* CPU provided TCP checksum */
211 u16 byte_cnt; /* buffer byte count */
212 u32 buf_ptr; /* pointer to buffer for this descriptor*/
213 u32 next_desc_ptr; /* Pointer to next descriptor */
214};
215#else
216#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
217#endif
218
7ca72a3b 219/* RX & TX descriptor command */
cc9754b3 220#define BUFFER_OWNED_BY_DMA 0x80000000
7ca72a3b
LB		 221
222/* RX & TX descriptor status */
cc9754b3 223#define ERROR_SUMMARY 0x00000001
7ca72a3b
LB		 224
225/* RX descriptor status */
cc9754b3
LB		 226#define LAYER_4_CHECKSUM_OK 0x40000000
227#define RX_ENABLE_INTERRUPT 0x20000000
228#define RX_FIRST_DESC 0x08000000
229#define RX_LAST_DESC 0x04000000
7ca72a3b
LB		 230
231/* TX descriptor command */
cc9754b3
LB		 232#define TX_ENABLE_INTERRUPT 0x00800000
233#define GEN_CRC 0x00400000
234#define TX_FIRST_DESC 0x00200000
235#define TX_LAST_DESC 0x00100000
236#define ZERO_PADDING 0x00080000
237#define GEN_IP_V4_CHECKSUM 0x00040000
238#define GEN_TCP_UDP_CHECKSUM 0x00020000
239#define UDP_FRAME 0x00010000
7ca72a3b 240
cc9754b3 241#define TX_IHL_SHIFT 11
7ca72a3b
LB		 242
243
c9df406f 244/* global *******************************************************************/
e5371493 245struct mv643xx_eth_shared_private {
cc9754b3 246 void __iomem *base;
c9df406f
LB		 247
248 /* used to protect SMI_REG, which is shared across ports */
249 spinlock_t phy_lock;
250
251 u32 win_protect;
252
253 unsigned int t_clk;
254};
255
256
257/* per-port *****************************************************************/
e5371493 258struct mib_counters {
fbd6a754
LB		 259 u64 good_octets_received;
260 u32 bad_octets_received;
261 u32 internal_mac_transmit_err;
262 u32 good_frames_received;
263 u32 bad_frames_received;
264 u32 broadcast_frames_received;
265 u32 multicast_frames_received;
266 u32 frames_64_octets;
267 u32 frames_65_to_127_octets;
268 u32 frames_128_to_255_octets;
269 u32 frames_256_to_511_octets;
270 u32 frames_512_to_1023_octets;
271 u32 frames_1024_to_max_octets;
272 u64 good_octets_sent;
273 u32 good_frames_sent;
274 u32 excessive_collision;
275 u32 multicast_frames_sent;
276 u32 broadcast_frames_sent;
277 u32 unrec_mac_control_received;
278 u32 fc_sent;
279 u32 good_fc_received;
280 u32 bad_fc_received;
281 u32 undersize_received;
282 u32 fragments_received;
283 u32 oversize_received;
284 u32 jabber_received;
285 u32 mac_receive_error;
286 u32 bad_crc_event;
287 u32 collision;
288 u32 late_collision;
289};
290
e5371493
LB		 291struct mv643xx_eth_private {
292 struct mv643xx_eth_shared_private *shared;
fbd6a754
LB		 293 int port_num; /* User Ethernet port number */
294
e5371493 295 struct mv643xx_eth_shared_private *shared_smi;
ce4e2e45 296
fbd6a754
LB		 297 u32 rx_sram_addr; /* Base address of rx sram area */
298 u32 rx_sram_size; /* Size of rx sram area */
299 u32 tx_sram_addr; /* Base address of tx sram area */
300 u32 tx_sram_size; /* Size of tx sram area */
301
fbd6a754
LB		 302 /* Tx/Rx rings managment indexes fields. For driver use */
303
304 /* Next available and first returning Rx resource */
5daffe94 305 int rx_curr_desc, rx_used_desc;
fbd6a754
LB		 306
307 /* Next available and first returning Tx resource */
5daffe94 308 int tx_curr_desc, tx_used_desc;
fbd6a754 309
e5371493 310#ifdef MV643XX_ETH_TX_FAST_REFILL
fbd6a754
LB		 311 u32 tx_clean_threshold;
312#endif
313
5daffe94 314 struct rx_desc *rx_desc_area;
fbd6a754
LB		 315 dma_addr_t rx_desc_dma;
316 int rx_desc_area_size;
317 struct sk_buff **rx_skb;
318
5daffe94 319 struct tx_desc *tx_desc_area;
fbd6a754
LB		 320 dma_addr_t tx_desc_dma;
321 int tx_desc_area_size;
322 struct sk_buff **tx_skb;
323
324 struct work_struct tx_timeout_task;
325
326 struct net_device *dev;
327 struct napi_struct napi;
328 struct net_device_stats stats;
e5371493 329 struct mib_counters mib_counters;
fbd6a754
LB		 330 spinlock_t lock;
331 /* Size of Tx Ring per queue */
332 int tx_ring_size;
333 /* Number of tx descriptors in use */
334 int tx_desc_count;
335 /* Size of Rx Ring per queue */
336 int rx_ring_size;
337 /* Number of rx descriptors in use */
338 int rx_desc_count;
339
340 /*
341 * Used in case RX Ring is empty, which can be caused when
342 * system does not have resources (skb's)
343 */
344 struct timer_list timeout;
345
346 u32 rx_int_coal;
347 u32 tx_int_coal;
348 struct mii_if_info mii;
349};
1da177e4 350
fbd6a754 351
c9df406f 352/* port register accessors **************************************************/
e5371493 353static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
c9df406f 354{
cc9754b3 355 return readl(mp->shared->base + offset);
c9df406f 356}
fbd6a754 357
e5371493 358static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
c9df406f 359{
cc9754b3 360 writel(data, mp->shared->base + offset);
c9df406f 361}
fbd6a754 362
fbd6a754 363
c9df406f 364/* rxq/txq helper functions *************************************************/
e5371493 365static void mv643xx_eth_port_enable_rx(struct mv643xx_eth_private *mp,
c9df406f
LB		 366 unsigned int queues)
367{
3cb4667c 368 wrl(mp, RXQ_COMMAND(mp->port_num), queues);
c9df406f 369}
fbd6a754 370
e5371493 371static unsigned int mv643xx_eth_port_disable_rx(struct mv643xx_eth_private *mp)
c9df406f
LB		 372{
373 unsigned int port_num = mp->port_num;
374 u32 queues;
fbd6a754 375
c9df406f 376 /* Stop Rx port activity. Check port Rx activity. */
3cb4667c 377 queues = rdl(mp, RXQ_COMMAND(port_num)) & 0xFF;
c9df406f
LB		 378 if (queues) {
379 /* Issue stop command for active queues only */
3cb4667c 380 wrl(mp, RXQ_COMMAND(port_num), (queues << 8));
1da177e4 381
c9df406f
LB		 382 /* Wait for all Rx activity to terminate. */
383 /* Check port cause register that all Rx queues are stopped */
3cb4667c 384 while (rdl(mp, RXQ_COMMAND(port_num)) & 0xFF)
e1bea50a 385 udelay(10);
c9df406f 386 }
1da177e4 387
c9df406f
LB		 388 return queues;
389}
390
e5371493 391static void mv643xx_eth_port_enable_tx(struct mv643xx_eth_private *mp,
c9df406f 392 unsigned int queues)
1da177e4 393{
3cb4667c 394 wrl(mp, TXQ_COMMAND(mp->port_num), queues);
1da177e4
LT		 395}
396
e5371493 397static unsigned int mv643xx_eth_port_disable_tx(struct mv643xx_eth_private *mp)
1da177e4 398{
c9df406f
LB		 399 unsigned int port_num = mp->port_num;
400 u32 queues;
401
402 /* Stop Tx port activity. Check port Tx activity. */
3cb4667c 403 queues = rdl(mp, TXQ_COMMAND(port_num)) & 0xFF;
c9df406f
LB		 404 if (queues) {
405 /* Issue stop command for active queues only */
3cb4667c 406 wrl(mp, TXQ_COMMAND(port_num), (queues << 8));
c9df406f
LB		 407
408 /* Wait for all Tx activity to terminate. */
409 /* Check port cause register that all Tx queues are stopped */
3cb4667c 410 while (rdl(mp, TXQ_COMMAND(port_num)) & 0xFF)
e1bea50a 411 udelay(10);
c9df406f
LB		 412
413 /* Wait for Tx FIFO to empty */
a2a41689 414 while (rdl(mp, PORT_STATUS(port_num)) & TX_FIFO_EMPTY)
e1bea50a 415 udelay(10);
c9df406f
LB		 416 }
417
418 return queues;
1da177e4
LT		 419}
420
c9df406f
LB		 421
422/* rx ***********************************************************************/
423static void mv643xx_eth_free_completed_tx_descs(struct net_device *dev);
424
de34f225 425static void mv643xx_eth_rx_refill_descs(struct net_device *dev)
1da177e4 426{
de34f225 427 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 428 unsigned long flags;
1da177e4 429
c9df406f 430 spin_lock_irqsave(&mp->lock, flags);
c0d0f2ca 431
f78fb474 432 while (mp->rx_desc_count < mp->rx_ring_size) {
de34f225
LB		 433 struct sk_buff *skb;
434 int unaligned;
435 int rx;
436
908b637f 437 skb = dev_alloc_skb(ETH_RX_SKB_SIZE + dma_get_cache_alignment());
de34f225 438 if (skb == NULL)
1da177e4 439 break;
de34f225 440
908b637f 441 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
b44cd572 442 if (unaligned)
908b637f 443 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
de34f225
LB		 444
445 mp->rx_desc_count++;
446 rx = mp->rx_used_desc;
447 mp->rx_used_desc = (rx + 1) % mp->rx_ring_size;
448
449 mp->rx_desc_area[rx].buf_ptr = dma_map_single(NULL,
450 skb->data,
451 ETH_RX_SKB_SIZE,
452 DMA_FROM_DEVICE);
453 mp->rx_desc_area[rx].buf_size = ETH_RX_SKB_SIZE;
454 mp->rx_skb[rx] = skb;
455 wmb();
456 mp->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
457 RX_ENABLE_INTERRUPT;
458 wmb();
459
7303fde8 460 skb_reserve(skb, ETH_HW_IP_ALIGN);
1da177e4 461 }
de34f225 462
f78fb474 463 if (mp->rx_desc_count == 0) {
de34f225 464 mp->timeout.expires = jiffies + (HZ / 10);
1da177e4 465 add_timer(&mp->timeout);
1da177e4 466 }
de34f225
LB		 467
468 spin_unlock_irqrestore(&mp->lock, flags);
1da177e4
LT		 469}
470
f78fb474 471static inline void mv643xx_eth_rx_refill_descs_timer_wrapper(unsigned long data)
1da177e4 472{
f78fb474 473 mv643xx_eth_rx_refill_descs((struct net_device *)data);
1da177e4
LT		 474}
475
96587661 476static int mv643xx_eth_receive_queue(struct net_device *dev, int budget)
1da177e4 477{
96587661
LB		 478 struct mv643xx_eth_private *mp = netdev_priv(dev);
479 struct net_device_stats *stats = &dev->stats;
480 unsigned int received_packets = 0;
1da177e4 481
96587661
LB		 482 while (budget-- > 0) {
483 struct sk_buff *skb;
484 volatile struct rx_desc *rx_desc;
485 unsigned int cmd_sts;
486 unsigned long flags;
d344bff9 487
96587661 488 spin_lock_irqsave(&mp->lock, flags);
ff561eef 489
96587661 490 rx_desc = &mp->rx_desc_area[mp->rx_curr_desc];
1da177e4 491
96587661
LB		 492 cmd_sts = rx_desc->cmd_sts;
493 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
494 spin_unlock_irqrestore(&mp->lock, flags);
495 break;
496 }
497 rmb();
1da177e4 498
96587661
LB		 499 skb = mp->rx_skb[mp->rx_curr_desc];
500 mp->rx_skb[mp->rx_curr_desc] = NULL;
ff561eef 501
96587661 502 mp->rx_curr_desc = (mp->rx_curr_desc + 1) % mp->rx_ring_size;
ff561eef 503
96587661 504 spin_unlock_irqrestore(&mp->lock, flags);
1da177e4 505
96587661
LB		 506 dma_unmap_single(NULL, rx_desc->buf_ptr + ETH_HW_IP_ALIGN,
507 ETH_RX_SKB_SIZE, DMA_FROM_DEVICE);
f98e36f1 508 mp->rx_desc_count--;
1da177e4 509 received_packets++;
b1dd9ca1 510
468d09f8
DF		 511 /*
512 * Update statistics.
513 * Note byte count includes 4 byte CRC count
514 */
1da177e4 515 stats->rx_packets++;
96587661
LB		 516 stats->rx_bytes += rx_desc->byte_cnt - ETH_HW_IP_ALIGN;
517
1da177e4
LT		 518 /*
519 * In case received a packet without first / last bits on OR
520 * the error summary bit is on, the packets needs to be dropeed.
521 */
96587661 522 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
cc9754b3 523 (RX_FIRST_DESC | RX_LAST_DESC))
96587661 524 || (cmd_sts & ERROR_SUMMARY)) {
1da177e4 525 stats->rx_dropped++;
96587661 526 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
cc9754b3 527 (RX_FIRST_DESC | RX_LAST_DESC)) {
1da177e4
LT		 528 if (net_ratelimit())
529 printk(KERN_ERR
530 "%s: Received packet spread "
531 "on multiple descriptors\n",
532 dev->name);
533 }
96587661 534 if (cmd_sts & ERROR_SUMMARY)
1da177e4
LT		 535 stats->rx_errors++;
536
537 dev_kfree_skb_irq(skb);
538 } else {
539 /*
540 * The -4 is for the CRC in the trailer of the
541 * received packet
542 */
96587661 543 skb_put(skb, rx_desc->byte_cnt - ETH_HW_IP_ALIGN - 4);
1da177e4 544
96587661 545 if (cmd_sts & LAYER_4_CHECKSUM_OK) {
1da177e4
LT		 546 skb->ip_summed = CHECKSUM_UNNECESSARY;
547 skb->csum = htons(
96587661 548 (cmd_sts & 0x0007fff8) >> 3);
1da177e4
LT		 549 }
550 skb->protocol = eth_type_trans(skb, dev);
e5371493 551#ifdef MV643XX_ETH_NAPI
1da177e4
LT		 552 netif_receive_skb(skb);
553#else
554 netif_rx(skb);
555#endif
556 }
12ad74f8 557 dev->last_rx = jiffies;
1da177e4 558 }
f78fb474 559 mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */
1da177e4
LT		 560
561 return received_packets;
562}
563
e5371493 564#ifdef MV643XX_ETH_NAPI
e5371493 565static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
d0412d96 566{
e5371493 567 struct mv643xx_eth_private *mp = container_of(napi, struct mv643xx_eth_private, napi);
c9df406f
LB		 568 struct net_device *dev = mp->dev;
569 unsigned int port_num = mp->port_num;
570 int work_done;
d0412d96 571
e5371493 572#ifdef MV643XX_ETH_TX_FAST_REFILL
c9df406f
LB		 573 if (++mp->tx_clean_threshold > 5) {
574 mv643xx_eth_free_completed_tx_descs(dev);
575 mp->tx_clean_threshold = 0;
d0412d96 576 }
c9df406f 577#endif
d0412d96 578
c9df406f 579 work_done = 0;
3cb4667c 580 if ((rdl(mp, RXQ_CURRENT_DESC_PTR(port_num)))
5daffe94 581 != (u32) mp->rx_used_desc)
c9df406f 582 work_done = mv643xx_eth_receive_queue(dev, budget);
d0412d96 583
c9df406f
LB		 584 if (work_done < budget) {
585 netif_rx_complete(dev, napi);
3cb4667c
LB		 586 wrl(mp, INT_CAUSE(port_num), 0);
587 wrl(mp, INT_CAUSE_EXT(port_num), 0);
073a345c 588 wrl(mp, INT_MASK(port_num), INT_RX | INT_EXT);
d0412d96 589 }
c9df406f
LB		 590
591 return work_done;
d0412d96 592}
c9df406f 593#endif
d0412d96 594
c9df406f
LB		 595
596/* tx ***********************************************************************/
c9df406f 597static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1da177e4 598{
c9df406f
LB		 599 unsigned int frag;
600 skb_frag_t *fragp;
1da177e4 601
c9df406f
LB		 602 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
603 fragp = &skb_shinfo(skb)->frags[frag];
604 if (fragp->size <= 8 && fragp->page_offset & 0x7)
605 return 1;
1da177e4 606 }
c9df406f
LB		 607 return 0;
608}
7303fde8 609
e5371493 610static int alloc_tx_desc_index(struct mv643xx_eth_private *mp)
c9df406f
LB		 611{
612 int tx_desc_curr;
d0412d96 613
c9df406f 614 BUG_ON(mp->tx_desc_count >= mp->tx_ring_size);
1da177e4 615
5daffe94
LB		 616 tx_desc_curr = mp->tx_curr_desc;
617 mp->tx_curr_desc = (tx_desc_curr + 1) % mp->tx_ring_size;
e4d00fa9 618
5daffe94 619 BUG_ON(mp->tx_curr_desc == mp->tx_used_desc);
468d09f8 620
c9df406f
LB		 621 return tx_desc_curr;
622}
468d09f8 623
e5371493 624static void tx_fill_frag_descs(struct mv643xx_eth_private *mp,
c9df406f
LB		 625 struct sk_buff *skb)
626{
627 int frag;
628 int tx_index;
cc9754b3 629 struct tx_desc *desc;
1da177e4 630
c9df406f
LB		 631 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
632 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
633
cc9754b3 634 tx_index = alloc_tx_desc_index(mp);
5daffe94 635 desc = &mp->tx_desc_area[tx_index];
c9df406f 636
cc9754b3 637 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
c9df406f
LB		 638 /* Last Frag enables interrupt and frees the skb */
639 if (frag == (skb_shinfo(skb)->nr_frags - 1)) {
cc9754b3
LB		 640 desc->cmd_sts |= ZERO_PADDING |
641 TX_LAST_DESC |
642 TX_ENABLE_INTERRUPT;
c9df406f
LB		 643 mp->tx_skb[tx_index] = skb;
644 } else
645 mp->tx_skb[tx_index] = NULL;
646
5daffe94 647 desc = &mp->tx_desc_area[tx_index];
c9df406f
LB		 648 desc->l4i_chk = 0;
649 desc->byte_cnt = this_frag->size;
650 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
651 this_frag->page_offset,
652 this_frag->size,
653 DMA_TO_DEVICE);
654 }
1da177e4
LT		 655}
656
c9df406f
LB		 657static inline __be16 sum16_as_be(__sum16 sum)
658{
659 return (__force __be16)sum;
660}
1da177e4 661
e5371493 662static void tx_submit_descs_for_skb(struct mv643xx_eth_private *mp,
c9df406f 663 struct sk_buff *skb)
1da177e4 664{
c9df406f 665 int tx_index;
cc9754b3 666 struct tx_desc *desc;
c9df406f
LB		 667 u32 cmd_sts;
668 int length;
669 int nr_frags = skb_shinfo(skb)->nr_frags;
1da177e4 670
cc9754b3 671 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
1da177e4 672
cc9754b3 673 tx_index = alloc_tx_desc_index(mp);
5daffe94 674 desc = &mp->tx_desc_area[tx_index];
c9df406f
LB		 675
676 if (nr_frags) {
cc9754b3 677 tx_fill_frag_descs(mp, skb);
c9df406f
LB		 678
679 length = skb_headlen(skb);
680 mp->tx_skb[tx_index] = NULL;
681 } else {
cc9754b3 682 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
c9df406f
LB		 683 length = skb->len;
684 mp->tx_skb[tx_index] = skb;
685 }
686
687 desc->byte_cnt = length;
688 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
689
690 if (skb->ip_summed == CHECKSUM_PARTIAL) {
691 BUG_ON(skb->protocol != htons(ETH_P_IP));
692
cc9754b3
LB		 693 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
694 GEN_IP_V4_CHECKSUM |
695 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
c9df406f
LB		 696
697 switch (ip_hdr(skb)->protocol) {
698 case IPPROTO_UDP:
cc9754b3 699 cmd_sts |= UDP_FRAME;
c9df406f
LB		 700 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
701 break;
702 case IPPROTO_TCP:
703 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
704 break;
705 default:
706 BUG();
707 }
708 } else {
709 /* Errata BTS #50, IHL must be 5 if no HW checksum */
cc9754b3 710 cmd_sts |= 5 << TX_IHL_SHIFT;
c9df406f
LB		 711 desc->l4i_chk = 0;
712 }
713
714 /* ensure all other descriptors are written before first cmd_sts */
715 wmb();
716 desc->cmd_sts = cmd_sts;
717
718 /* ensure all descriptors are written before poking hardware */
719 wmb();
073a345c 720 mv643xx_eth_port_enable_tx(mp, 1);
c9df406f
LB		 721
722 mp->tx_desc_count += nr_frags + 1;
1da177e4 723}
1da177e4 724
c9df406f 725static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 726{
e5371493 727 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f
LB		 728 struct net_device_stats *stats = &dev->stats;
729 unsigned long flags;
afdb57a2 730
c9df406f 731 BUG_ON(netif_queue_stopped(dev));
afdb57a2 732
c9df406f
LB		 733 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
734 stats->tx_dropped++;
735 printk(KERN_DEBUG "%s: failed to linearize tiny "
736 "unaligned fragment\n", dev->name);
737 return NETDEV_TX_BUSY;
738 }
739
740 spin_lock_irqsave(&mp->lock, flags);
741
742 if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB) {
743 printk(KERN_ERR "%s: transmit with queue full\n", dev->name);
744 netif_stop_queue(dev);
745 spin_unlock_irqrestore(&mp->lock, flags);
746 return NETDEV_TX_BUSY;
747 }
748
cc9754b3 749 tx_submit_descs_for_skb(mp, skb);
c9df406f
LB		 750 stats->tx_bytes += skb->len;
751 stats->tx_packets++;
752 dev->trans_start = jiffies;
753
754 if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB)
755 netif_stop_queue(dev);
756
757 spin_unlock_irqrestore(&mp->lock, flags);
758
759 return NETDEV_TX_OK;
1da177e4
LT		 760}
761
c9df406f
LB		 762
763/* mii management interface *************************************************/
e5371493 764static int phy_addr_get(struct mv643xx_eth_private *mp);
c9df406f 765
e5371493 766static void read_smi_reg(struct mv643xx_eth_private *mp,
c9df406f 767 unsigned int phy_reg, unsigned int *value)
1da177e4 768{
cc9754b3
LB		 769 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
770 int phy_addr = phy_addr_get(mp);
c9df406f 771 unsigned long flags;
1da177e4
LT		 772 int i;
773
c9df406f
LB		 774 /* the SMI register is a shared resource */
775 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
776
777 /* wait for the SMI register to become available */
cc9754b3 778 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
e1bea50a 779 if (i == 1000) {
c9df406f
LB		 780 printk("%s: PHY busy timeout\n", mp->dev->name);
781 goto out;
782 }
e1bea50a 783 udelay(10);
1da177e4
LT		 784 }
785
cc9754b3 786 writel((phy_addr << 16) | (phy_reg << 21) | SMI_OPCODE_READ, smi_reg);
1da177e4 787
c9df406f 788 /* now wait for the data to be valid */
cc9754b3 789 for (i = 0; !(readl(smi_reg) & SMI_READ_VALID); i++) {
e1bea50a 790 if (i == 1000) {
c9df406f
LB		 791 printk("%s: PHY read timeout\n", mp->dev->name);
792 goto out;
793 }
e1bea50a 794 udelay(10);
c9df406f
LB		 795 }
796
797 *value = readl(smi_reg) & 0xffff;
798out:
799 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
1da177e4
LT		 800}
801
e5371493 802static void write_smi_reg(struct mv643xx_eth_private *mp,
c9df406f 803 unsigned int phy_reg, unsigned int value)
1da177e4 804{
cc9754b3
LB		 805 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
806 int phy_addr = phy_addr_get(mp);
c9df406f 807 unsigned long flags;
1da177e4
LT		 808 int i;
809
c9df406f
LB		 810 /* the SMI register is a shared resource */
811 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
812
813 /* wait for the SMI register to become available */
cc9754b3 814 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
e1bea50a 815 if (i == 1000) {
c9df406f
LB		 816 printk("%s: PHY busy timeout\n", mp->dev->name);
817 goto out;
818 }
e1bea50a 819 udelay(10);
1da177e4
LT		 820 }
821
c9df406f 822 writel((phy_addr << 16) | (phy_reg << 21) |
cc9754b3 823 SMI_OPCODE_WRITE | (value & 0xffff), smi_reg);
c9df406f
LB		 824out:
825 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
826}
1da177e4 827
c9df406f
LB		 828
829/* mib counters *************************************************************/
e5371493 830static void clear_mib_counters(struct mv643xx_eth_private *mp)
c9df406f
LB		 831{
832 unsigned int port_num = mp->port_num;
833 int i;
834
835 /* Perform dummy reads from MIB counters */
4b8e3655 836 for (i = 0; i < 0x80; i += 4)
3cb4667c 837 rdl(mp, MIB_COUNTERS(port_num) + i);
1da177e4
LT		 838}
839
e5371493 840static inline u32 read_mib(struct mv643xx_eth_private *mp, int offset)
d0412d96 841{
3cb4667c 842 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
c9df406f 843}
d0412d96 844
e5371493 845static void update_mib_counters(struct mv643xx_eth_private *mp)
c9df406f 846{
e5371493 847 struct mib_counters *p = &mp->mib_counters;
4b8e3655
LB		 848
849 p->good_octets_received += read_mib(mp, 0x00);
850 p->good_octets_received += (u64)read_mib(mp, 0x04) << 32;
851 p->bad_octets_received += read_mib(mp, 0x08);
852 p->internal_mac_transmit_err += read_mib(mp, 0x0c);
853 p->good_frames_received += read_mib(mp, 0x10);
854 p->bad_frames_received += read_mib(mp, 0x14);
855 p->broadcast_frames_received += read_mib(mp, 0x18);
856 p->multicast_frames_received += read_mib(mp, 0x1c);
857 p->frames_64_octets += read_mib(mp, 0x20);
858 p->frames_65_to_127_octets += read_mib(mp, 0x24);
859 p->frames_128_to_255_octets += read_mib(mp, 0x28);
860 p->frames_256_to_511_octets += read_mib(mp, 0x2c);
861 p->frames_512_to_1023_octets += read_mib(mp, 0x30);
862 p->frames_1024_to_max_octets += read_mib(mp, 0x34);
863 p->good_octets_sent += read_mib(mp, 0x38);
864 p->good_octets_sent += (u64)read_mib(mp, 0x3c) << 32;
865 p->good_frames_sent += read_mib(mp, 0x40);
866 p->excessive_collision += read_mib(mp, 0x44);
867 p->multicast_frames_sent += read_mib(mp, 0x48);
868 p->broadcast_frames_sent += read_mib(mp, 0x4c);
869 p->unrec_mac_control_received += read_mib(mp, 0x50);
870 p->fc_sent += read_mib(mp, 0x54);
871 p->good_fc_received += read_mib(mp, 0x58);
872 p->bad_fc_received += read_mib(mp, 0x5c);
873 p->undersize_received += read_mib(mp, 0x60);
874 p->fragments_received += read_mib(mp, 0x64);
875 p->oversize_received += read_mib(mp, 0x68);
876 p->jabber_received += read_mib(mp, 0x6c);
877 p->mac_receive_error += read_mib(mp, 0x70);
878 p->bad_crc_event += read_mib(mp, 0x74);
879 p->collision += read_mib(mp, 0x78);
880 p->late_collision += read_mib(mp, 0x7c);
d0412d96
JC		 881}
882
c9df406f
LB		 883
884/* ethtool ******************************************************************/
e5371493 885struct mv643xx_eth_stats {
c9df406f
LB		 886 char stat_string[ETH_GSTRING_LEN];
887 int sizeof_stat;
888 int stat_offset;
889};
890
e5371493
LB		 891#define MV643XX_ETH_STAT(m) FIELD_SIZEOF(struct mv643xx_eth_private, m), \
892 offsetof(struct mv643xx_eth_private, m)
893
894static const struct mv643xx_eth_stats mv643xx_eth_gstrings_stats[] = {
895 { "rx_packets", MV643XX_ETH_STAT(stats.rx_packets) },
896 { "tx_packets", MV643XX_ETH_STAT(stats.tx_packets) },
897 { "rx_bytes", MV643XX_ETH_STAT(stats.rx_bytes) },
898 { "tx_bytes", MV643XX_ETH_STAT(stats.tx_bytes) },
899 { "rx_errors", MV643XX_ETH_STAT(stats.rx_errors) },
900 { "tx_errors", MV643XX_ETH_STAT(stats.tx_errors) },
901 { "rx_dropped", MV643XX_ETH_STAT(stats.rx_dropped) },
902 { "tx_dropped", MV643XX_ETH_STAT(stats.tx_dropped) },
903 { "good_octets_received", MV643XX_ETH_STAT(mib_counters.good_octets_received) },
904 { "bad_octets_received", MV643XX_ETH_STAT(mib_counters.bad_octets_received) },
905 { "internal_mac_transmit_err", MV643XX_ETH_STAT(mib_counters.internal_mac_transmit_err) },
906 { "good_frames_received", MV643XX_ETH_STAT(mib_counters.good_frames_received) },
907 { "bad_frames_received", MV643XX_ETH_STAT(mib_counters.bad_frames_received) },
908 { "broadcast_frames_received", MV643XX_ETH_STAT(mib_counters.broadcast_frames_received) },
909 { "multicast_frames_received", MV643XX_ETH_STAT(mib_counters.multicast_frames_received) },
910 { "frames_64_octets", MV643XX_ETH_STAT(mib_counters.frames_64_octets) },
911 { "frames_65_to_127_octets", MV643XX_ETH_STAT(mib_counters.frames_65_to_127_octets) },
912 { "frames_128_to_255_octets", MV643XX_ETH_STAT(mib_counters.frames_128_to_255_octets) },
913 { "frames_256_to_511_octets", MV643XX_ETH_STAT(mib_counters.frames_256_to_511_octets) },
914 { "frames_512_to_1023_octets", MV643XX_ETH_STAT(mib_counters.frames_512_to_1023_octets) },
915 { "frames_1024_to_max_octets", MV643XX_ETH_STAT(mib_counters.frames_1024_to_max_octets) },
916 { "good_octets_sent", MV643XX_ETH_STAT(mib_counters.good_octets_sent) },
917 { "good_frames_sent", MV643XX_ETH_STAT(mib_counters.good_frames_sent) },
918 { "excessive_collision", MV643XX_ETH_STAT(mib_counters.excessive_collision) },
919 { "multicast_frames_sent", MV643XX_ETH_STAT(mib_counters.multicast_frames_sent) },
920 { "broadcast_frames_sent", MV643XX_ETH_STAT(mib_counters.broadcast_frames_sent) },
921 { "unrec_mac_control_received", MV643XX_ETH_STAT(mib_counters.unrec_mac_control_received) },
922 { "fc_sent", MV643XX_ETH_STAT(mib_counters.fc_sent) },
923 { "good_fc_received", MV643XX_ETH_STAT(mib_counters.good_fc_received) },
924 { "bad_fc_received", MV643XX_ETH_STAT(mib_counters.bad_fc_received) },
925 { "undersize_received", MV643XX_ETH_STAT(mib_counters.undersize_received) },
926 { "fragments_received", MV643XX_ETH_STAT(mib_counters.fragments_received) },
927 { "oversize_received", MV643XX_ETH_STAT(mib_counters.oversize_received) },
928 { "jabber_received", MV643XX_ETH_STAT(mib_counters.jabber_received) },
929 { "mac_receive_error", MV643XX_ETH_STAT(mib_counters.mac_receive_error) },
930 { "bad_crc_event", MV643XX_ETH_STAT(mib_counters.bad_crc_event) },
931 { "collision", MV643XX_ETH_STAT(mib_counters.collision) },
932 { "late_collision", MV643XX_ETH_STAT(mib_counters.late_collision) },
c9df406f
LB		 933};
934
e5371493 935#define MV643XX_ETH_STATS_LEN ARRAY_SIZE(mv643xx_eth_gstrings_stats)
c9df406f 936
e5371493 937static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
d0412d96 938{
e5371493 939 struct mv643xx_eth_private *mp = netdev_priv(dev);
d0412d96
JC		 940 int err;
941
942 spin_lock_irq(&mp->lock);
943 err = mii_ethtool_gset(&mp->mii, cmd);
944 spin_unlock_irq(&mp->lock);
945
946 /* The PHY may support 1000baseT_Half, but the mv643xx does not */
947 cmd->supported &= ~SUPPORTED_1000baseT_Half;
948 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
949
950 return err;
951}
952
e5371493 953static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4 954{
e5371493 955 struct mv643xx_eth_private *mp = netdev_priv(dev);
ab4384a6
DF		 956 int err;
957
c9df406f
LB		 958 spin_lock_irq(&mp->lock);
959 err = mii_ethtool_sset(&mp->mii, cmd);
960 spin_unlock_irq(&mp->lock);
85cf572c 961
c9df406f
LB		 962 return err;
963}
1da177e4 964
e5371493 965static void mv643xx_eth_get_drvinfo(struct net_device *netdev,
c9df406f
LB		 966 struct ethtool_drvinfo *drvinfo)
967{
e5371493
LB		 968 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
969 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
c9df406f
LB		 970 strncpy(drvinfo->fw_version, "N/A", 32);
971 strncpy(drvinfo->bus_info, "mv643xx", 32);
e5371493 972 drvinfo->n_stats = MV643XX_ETH_STATS_LEN;
c9df406f 973}
1da177e4 974
c9df406f
LB		 975static int mv643xx_eth_nway_restart(struct net_device *dev)
976{
e5371493 977 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 978
c9df406f
LB		 979 return mii_nway_restart(&mp->mii);
980}
1da177e4 981
c9df406f
LB		 982static u32 mv643xx_eth_get_link(struct net_device *dev)
983{
e5371493 984 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 985
c9df406f
LB		 986 return mii_link_ok(&mp->mii);
987}
1da177e4 988
e5371493 989static void mv643xx_eth_get_strings(struct net_device *netdev, uint32_t stringset,
c9df406f
LB		 990 uint8_t *data)
991{
992 int i;
1da177e4 993
c9df406f
LB		 994 switch(stringset) {
995 case ETH_SS_STATS:
e5371493 996 for (i=0; i < MV643XX_ETH_STATS_LEN; i++) {
c9df406f 997 memcpy(data + i * ETH_GSTRING_LEN,
e5371493
LB		 998 mv643xx_eth_gstrings_stats[i].stat_string,
999 ETH_GSTRING_LEN);
c9df406f
LB		 1000 }
1001 break;
1002 }
1003}
1da177e4 1004
e5371493 1005static void mv643xx_eth_get_ethtool_stats(struct net_device *netdev,
c9df406f
LB		 1006 struct ethtool_stats *stats, uint64_t *data)
1007{
e5371493 1008 struct mv643xx_eth_private *mp = netdev->priv;
c9df406f 1009 int i;
1da177e4 1010
cc9754b3 1011 update_mib_counters(mp);
1da177e4 1012
e5371493
LB		 1013 for (i = 0; i < MV643XX_ETH_STATS_LEN; i++) {
1014 char *p = (char *)mp+mv643xx_eth_gstrings_stats[i].stat_offset;
1015 data[i] = (mv643xx_eth_gstrings_stats[i].sizeof_stat ==
c9df406f 1016 sizeof(uint64_t)) ? *(uint64_t *)p : *(uint32_t *)p;
1da177e4 1017 }
c9df406f 1018}
1da177e4 1019
e5371493 1020static int mv643xx_eth_get_sset_count(struct net_device *netdev, int sset)
c9df406f
LB		 1021{
1022 switch (sset) {
1023 case ETH_SS_STATS:
e5371493 1024 return MV643XX_ETH_STATS_LEN;
c9df406f
LB		 1025 default:
1026 return -EOPNOTSUPP;
1027 }
1028}
1da177e4 1029
e5371493
LB		 1030static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1031 .get_settings = mv643xx_eth_get_settings,
1032 .set_settings = mv643xx_eth_set_settings,
1033 .get_drvinfo = mv643xx_eth_get_drvinfo,
c9df406f
LB		 1034 .get_link = mv643xx_eth_get_link,
1035 .set_sg = ethtool_op_set_sg,
e5371493
LB		 1036 .get_sset_count = mv643xx_eth_get_sset_count,
1037 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1038 .get_strings = mv643xx_eth_get_strings,
c9df406f
LB		 1039 .nway_reset = mv643xx_eth_nway_restart,
1040};
1da177e4 1041
bea3348e 1042
c9df406f 1043/* address handling *********************************************************/
5daffe94 1044static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
c9df406f
LB		 1045{
1046 unsigned int port_num = mp->port_num;
1047 unsigned int mac_h;
1048 unsigned int mac_l;
1da177e4 1049
c9df406f
LB		 1050 mac_h = rdl(mp, MAC_ADDR_HIGH(port_num));
1051 mac_l = rdl(mp, MAC_ADDR_LOW(port_num));
1da177e4 1052
5daffe94
LB		 1053 addr[0] = (mac_h >> 24) & 0xff;
1054 addr[1] = (mac_h >> 16) & 0xff;
1055 addr[2] = (mac_h >> 8) & 0xff;
1056 addr[3] = mac_h & 0xff;
1057 addr[4] = (mac_l >> 8) & 0xff;
1058 addr[5] = mac_l & 0xff;
c9df406f 1059}
1da177e4 1060
e5371493 1061static void init_mac_tables(struct mv643xx_eth_private *mp)
c9df406f
LB		 1062{
1063 unsigned int port_num = mp->port_num;
1064 int table_index;
1da177e4 1065
c9df406f
LB		 1066 /* Clear DA filter unicast table (Ex_dFUT) */
1067 for (table_index = 0; table_index <= 0xC; table_index += 4)
3cb4667c 1068 wrl(mp, UNICAST_TABLE(port_num) + table_index, 0);
1da177e4 1069
c9df406f
LB		 1070 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
1071 /* Clear DA filter special multicast table (Ex_dFSMT) */
3cb4667c 1072 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + table_index, 0);
c9df406f 1073 /* Clear DA filter other multicast table (Ex_dFOMT) */
3cb4667c 1074 wrl(mp, OTHER_MCAST_TABLE(port_num) + table_index, 0);
c9df406f
LB		 1075 }
1076}
d0412d96 1077
e5371493 1078static void set_filter_table_entry(struct mv643xx_eth_private *mp,
c9df406f
LB		 1079 int table, unsigned char entry)
1080{
1081 unsigned int table_reg;
1082 unsigned int tbl_offset;
1083 unsigned int reg_offset;
ab4384a6 1084
c9df406f
LB		 1085 tbl_offset = (entry / 4) * 4; /* Register offset of DA table entry */
1086 reg_offset = entry % 4; /* Entry offset within the register */
ab4384a6 1087
c9df406f
LB		 1088 /* Set "accepts frame bit" at specified table entry */
1089 table_reg = rdl(mp, table + tbl_offset);
1090 table_reg |= 0x01 << (8 * reg_offset);
1091 wrl(mp, table + tbl_offset, table_reg);
1da177e4
LT		 1092}
1093
5daffe94 1094static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1da177e4 1095{
c9df406f
LB		 1096 unsigned int port_num = mp->port_num;
1097 unsigned int mac_h;
1098 unsigned int mac_l;
1099 int table;
1da177e4 1100
5daffe94
LB		 1101 mac_l = (addr[4] << 8) | (addr[5]);
1102 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) |
1103 (addr[3] << 0);
ff561eef 1104
c9df406f
LB		 1105 wrl(mp, MAC_ADDR_LOW(port_num), mac_l);
1106 wrl(mp, MAC_ADDR_HIGH(port_num), mac_h);
1da177e4 1107
c9df406f 1108 /* Accept frames with this address */
3cb4667c 1109 table = UNICAST_TABLE(port_num);
5daffe94 1110 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1da177e4
LT		 1111}
1112
c9df406f 1113static void mv643xx_eth_update_mac_address(struct net_device *dev)
1da177e4 1114{
e5371493 1115 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1116
cc9754b3
LB		 1117 init_mac_tables(mp);
1118 uc_addr_set(mp, dev->dev_addr);
c9df406f 1119}
1da177e4 1120
c9df406f 1121static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1da177e4 1122{
c9df406f 1123 int i;
1da177e4 1124
c9df406f
LB		 1125 for (i = 0; i < 6; i++)
1126 /* +2 is for the offset of the HW addr type */
1127 dev->dev_addr[i] = ((unsigned char *)addr)[i + 2];
1128 mv643xx_eth_update_mac_address(dev);
1da177e4
LT		 1129 return 0;
1130}
1131
5daffe94 1132static void mc_addr(struct mv643xx_eth_private *mp, unsigned char *addr)
1da177e4 1133{
1da177e4 1134 unsigned int port_num = mp->port_num;
c9df406f
LB		 1135 unsigned int mac_h;
1136 unsigned int mac_l;
1137 unsigned char crc_result = 0;
1138 int table;
1139 int mac_array[48];
1140 int crc[8];
1141 int i;
1da177e4 1142
5daffe94
LB		 1143 if ((addr[0] == 0x01) && (addr[1] == 0x00) &&
1144 (addr[2] == 0x5E) && (addr[3] == 0x00) && (addr[4] == 0x00)) {
3cb4667c 1145 table = SPECIAL_MCAST_TABLE(port_num);
5daffe94 1146 set_filter_table_entry(mp, table, addr[5]);
c9df406f 1147 return;
1da177e4 1148 }
1da177e4 1149
c9df406f 1150 /* Calculate CRC-8 out of the given address */
5daffe94
LB		 1151 mac_h = (addr[0] << 8) | (addr[1]);
1152 mac_l = (addr[2] << 24) | (addr[3] << 16) |
1153 (addr[4] << 8) | (addr[5] << 0);
1da177e4 1154
c9df406f
LB		 1155 for (i = 0; i < 32; i++)
1156 mac_array[i] = (mac_l >> i) & 0x1;
1157 for (i = 32; i < 48; i++)
1158 mac_array[i] = (mac_h >> (i - 32)) & 0x1;
1da177e4 1159
c9df406f
LB		 1160 crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ mac_array[39] ^
1161 mac_array[35] ^ mac_array[34] ^ mac_array[31] ^ mac_array[30] ^
1162 mac_array[28] ^ mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
1163 mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ mac_array[12] ^
1164 mac_array[8] ^ mac_array[7] ^ mac_array[6] ^ mac_array[0];
1da177e4 1165
c9df406f
LB		 1166 crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
1167 mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ mac_array[34] ^
1168 mac_array[32] ^ mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
1169 mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ mac_array[21] ^
1170 mac_array[20] ^ mac_array[18] ^ mac_array[17] ^ mac_array[16] ^
1171 mac_array[15] ^ mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
1172 mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ mac_array[0];
f7ea3337 1173
c9df406f
LB		 1174 crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ mac_array[43] ^
1175 mac_array[42] ^ mac_array[39] ^ mac_array[37] ^ mac_array[34] ^
1176 mac_array[33] ^ mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
1177 mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ mac_array[15] ^
1178 mac_array[13] ^ mac_array[12] ^ mac_array[10] ^ mac_array[8] ^
1179 mac_array[6] ^ mac_array[2] ^ mac_array[1] ^ mac_array[0];
f7ea3337 1180
c9df406f
LB		 1181 crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
1182 mac_array[40] ^ mac_array[38] ^ mac_array[35] ^ mac_array[34] ^
1183 mac_array[30] ^ mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
1184 mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
1185 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[7] ^
1186 mac_array[3] ^ mac_array[2] ^ mac_array[1];
f7ea3337 1187
c9df406f
LB		 1188 crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[41] ^
1189 mac_array[39] ^ mac_array[36] ^ mac_array[35] ^ mac_array[31] ^
1190 mac_array[30] ^ mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
1191 mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ mac_array[14] ^
1192 mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ mac_array[4] ^
1193 mac_array[3] ^ mac_array[2];
c8aaea25 1194
c9df406f
LB		 1195 crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ mac_array[42] ^
1196 mac_array[40] ^ mac_array[37] ^ mac_array[36] ^ mac_array[32] ^
1197 mac_array[31] ^ mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
1198 mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ mac_array[15] ^
1199 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[5] ^
1200 mac_array[4] ^ mac_array[3];
c8aaea25 1201
c9df406f
LB		 1202 crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ mac_array[41] ^
1203 mac_array[38] ^ mac_array[37] ^ mac_array[33] ^ mac_array[32] ^
1204 mac_array[29] ^ mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
1205 mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ mac_array[14] ^
1206 mac_array[12] ^ mac_array[10] ^ mac_array[6] ^ mac_array[5] ^
1207 mac_array[4];
c8aaea25 1208
c9df406f
LB		 1209 crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ mac_array[39] ^
1210 mac_array[38] ^ mac_array[34] ^ mac_array[33] ^ mac_array[30] ^
1211 mac_array[29] ^ mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
1212 mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ mac_array[13] ^
1213 mac_array[11] ^ mac_array[7] ^ mac_array[6] ^ mac_array[5];
c8aaea25 1214
c9df406f
LB		 1215 for (i = 0; i < 8; i++)
1216 crc_result = crc_result | (crc[i] << i);
1217
3cb4667c 1218 table = OTHER_MCAST_TABLE(port_num);
cc9754b3 1219 set_filter_table_entry(mp, table, crc_result);
c8aaea25
DF		 1220}
1221
cc9754b3 1222static void set_multicast_list(struct net_device *dev)
1da177e4 1223{
1da177e4 1224
c9df406f
LB		 1225 struct dev_mc_list *mc_list;
1226 int i;
1227 int table_index;
e5371493 1228 struct mv643xx_eth_private *mp = netdev_priv(dev);
cc9754b3 1229 unsigned int port_num = mp->port_num;
c8aaea25 1230
c9df406f
LB		 1231 /* If the device is in promiscuous mode or in all multicast mode,
1232 * we will fully populate both multicast tables with accept.
1233 * This is guaranteed to yield a match on all multicast addresses...
1234 */
1235 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) {
1236 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
1237 /* Set all entries in DA filter special multicast
1238 * table (Ex_dFSMT)
1239 * Set for ETH_Q0 for now
1240 * Bits
1241 * 0 Accept=1, Drop=0
1242 * 3-1 Queue ETH_Q0=0
1243 * 7-4 Reserved = 0;
1244 */
cc9754b3 1245 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + table_index, 0x01010101);
c8aaea25 1246
c9df406f
LB		 1247 /* Set all entries in DA filter other multicast
1248 * table (Ex_dFOMT)
1249 * Set for ETH_Q0 for now
1250 * Bits
1251 * 0 Accept=1, Drop=0
1252 * 3-1 Queue ETH_Q0=0
1253 * 7-4 Reserved = 0;
1254 */
cc9754b3 1255 wrl(mp, OTHER_MCAST_TABLE(port_num) + table_index, 0x01010101);
c9df406f
LB		 1256 }
1257 return;
1258 }
c8aaea25 1259
c9df406f
LB		 1260 /* We will clear out multicast tables every time we get the list.
1261 * Then add the entire new list...
1262 */
1263 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
1264 /* Clear DA filter special multicast table (Ex_dFSMT) */
cc9754b3 1265 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + table_index, 0);
c9df406f
LB		 1266
1267 /* Clear DA filter other multicast table (Ex_dFOMT) */
cc9754b3 1268 wrl(mp, OTHER_MCAST_TABLE(port_num) + table_index, 0);
1da177e4
LT		 1269 }
1270
c9df406f
LB		 1271 /* Get pointer to net_device multicast list and add each one... */
1272 for (i = 0, mc_list = dev->mc_list;
1273 (i < 256) && (mc_list != NULL) && (i < dev->mc_count);
1274 i++, mc_list = mc_list->next)
1275 if (mc_list->dmi_addrlen == 6)
cc9754b3 1276 mc_addr(mp, mc_list->dmi_addr);
324ff2c1
BB		 1277}
1278
c9df406f 1279static void mv643xx_eth_set_rx_mode(struct net_device *dev)
c8aaea25 1280{
e5371493 1281 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 1282 u32 config_reg;
1da177e4 1283
3cb4667c 1284 config_reg = rdl(mp, PORT_CONFIG(mp->port_num));
c9df406f 1285 if (dev->flags & IFF_PROMISC)
d9a073ea 1286 config_reg |= UNICAST_PROMISCUOUS_MODE;
c9df406f 1287 else
d9a073ea 1288 config_reg &= ~UNICAST_PROMISCUOUS_MODE;
3cb4667c 1289 wrl(mp, PORT_CONFIG(mp->port_num), config_reg);
1da177e4 1290
cc9754b3 1291 set_multicast_list(dev);
c9df406f 1292}
c8aaea25 1293
c8aaea25 1294
c9df406f 1295/* rx/tx queue initialisation ***********************************************/
e5371493 1296static void ether_init_rx_desc_ring(struct mv643xx_eth_private *mp)
c9df406f 1297{
cc9754b3 1298 volatile struct rx_desc *p_rx_desc;
c9df406f
LB		 1299 int rx_desc_num = mp->rx_ring_size;
1300 int i;
1301
1302 /* initialize the next_desc_ptr links in the Rx descriptors ring */
5daffe94 1303 p_rx_desc = (struct rx_desc *)mp->rx_desc_area;
c9df406f
LB		 1304 for (i = 0; i < rx_desc_num; i++) {
1305 p_rx_desc[i].next_desc_ptr = mp->rx_desc_dma +
cc9754b3 1306 ((i + 1) % rx_desc_num) * sizeof(struct rx_desc);
f7ea3337
PJ		 1307 }
1308
c9df406f 1309 /* Save Rx desc pointer to driver struct. */
5daffe94
LB		 1310 mp->rx_curr_desc = 0;
1311 mp->rx_used_desc = 0;
1da177e4 1312
cc9754b3 1313 mp->rx_desc_area_size = rx_desc_num * sizeof(struct rx_desc);
c9df406f 1314}
c8aaea25 1315
c9df406f
LB		 1316static void mv643xx_eth_free_rx_rings(struct net_device *dev)
1317{
e5371493 1318 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 1319 int curr;
c8aaea25 1320
c9df406f
LB		 1321 /* Stop RX Queues */
1322 mv643xx_eth_port_disable_rx(mp);
1323
1324 /* Free preallocated skb's on RX rings */
1325 for (curr = 0; mp->rx_desc_count && curr < mp->rx_ring_size; curr++) {
1326 if (mp->rx_skb[curr]) {
1327 dev_kfree_skb(mp->rx_skb[curr]);
1328 mp->rx_desc_count--;
1da177e4 1329 }
c8aaea25 1330 }
1da177e4 1331
c9df406f
LB		 1332 if (mp->rx_desc_count)
1333 printk(KERN_ERR
1334 "%s: Error in freeing Rx Ring. %d skb's still"
1335 " stuck in RX Ring - ignoring them\n", dev->name,
1336 mp->rx_desc_count);
1337 /* Free RX ring */
1338 if (mp->rx_sram_size)
5daffe94 1339 iounmap(mp->rx_desc_area);
c9df406f
LB		 1340 else
1341 dma_free_coherent(NULL, mp->rx_desc_area_size,
5daffe94 1342 mp->rx_desc_area, mp->rx_desc_dma);
c9df406f 1343}
1da177e4 1344
e5371493 1345static void ether_init_tx_desc_ring(struct mv643xx_eth_private *mp)
c9df406f
LB		 1346{
1347 int tx_desc_num = mp->tx_ring_size;
cc9754b3 1348 struct tx_desc *p_tx_desc;
c9df406f 1349 int i;
1da177e4 1350
c9df406f 1351 /* Initialize the next_desc_ptr links in the Tx descriptors ring */
5daffe94 1352 p_tx_desc = (struct tx_desc *)mp->tx_desc_area;
c9df406f
LB		 1353 for (i = 0; i < tx_desc_num; i++) {
1354 p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma +
cc9754b3 1355 ((i + 1) % tx_desc_num) * sizeof(struct tx_desc);
c9df406f
LB		 1356 }
1357
5daffe94
LB		 1358 mp->tx_curr_desc = 0;
1359 mp->tx_used_desc = 0;
c9df406f 1360
cc9754b3 1361 mp->tx_desc_area_size = tx_desc_num * sizeof(struct tx_desc);
c8aaea25 1362}
1da177e4 1363
c9df406f 1364static int mv643xx_eth_free_tx_descs(struct net_device *dev, int force)
c8aaea25 1365{
e5371493 1366 struct mv643xx_eth_private *mp = netdev_priv(dev);
cc9754b3 1367 struct tx_desc *desc;
c9df406f
LB		 1368 u32 cmd_sts;
1369 struct sk_buff *skb;
c8aaea25 1370 unsigned long flags;
c9df406f
LB		 1371 int tx_index;
1372 dma_addr_t addr;
1373 int count;
1374 int released = 0;
1da177e4 1375
c9df406f
LB		 1376 while (mp->tx_desc_count > 0) {
1377 spin_lock_irqsave(&mp->lock, flags);
94843566 1378
c9df406f
LB		 1379 /* tx_desc_count might have changed before acquiring the lock */
1380 if (mp->tx_desc_count <= 0) {
1381 spin_unlock_irqrestore(&mp->lock, flags);
1382 return released;
1383 }
4d64e718 1384
5daffe94
LB		 1385 tx_index = mp->tx_used_desc;
1386 desc = &mp->tx_desc_area[tx_index];
c9df406f 1387 cmd_sts = desc->cmd_sts;
4d64e718 1388
cc9754b3 1389 if (!force && (cmd_sts & BUFFER_OWNED_BY_DMA)) {
c9df406f
LB		 1390 spin_unlock_irqrestore(&mp->lock, flags);
1391 return released;
1392 }
1da177e4 1393
5daffe94 1394 mp->tx_used_desc = (tx_index + 1) % mp->tx_ring_size;
c9df406f 1395 mp->tx_desc_count--;
1da177e4 1396
c9df406f
LB		 1397 addr = desc->buf_ptr;
1398 count = desc->byte_cnt;
1399 skb = mp->tx_skb[tx_index];
1400 if (skb)
1401 mp->tx_skb[tx_index] = NULL;
c8aaea25 1402
cc9754b3 1403 if (cmd_sts & ERROR_SUMMARY) {
c9df406f
LB		 1404 printk("%s: Error in TX\n", dev->name);
1405 dev->stats.tx_errors++;
1406 }
1da177e4 1407
c9df406f 1408 spin_unlock_irqrestore(&mp->lock, flags);
1da177e4 1409
cc9754b3 1410 if (cmd_sts & TX_FIRST_DESC)
c9df406f
LB		 1411 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
1412 else
1413 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
c2e5b352 1414
c9df406f
LB		 1415 if (skb)
1416 dev_kfree_skb_irq(skb);
63c9e549 1417
c9df406f
LB		 1418 released = 1;
1419 }
c2e5b352 1420
c9df406f 1421 return released;
63c9e549 1422}
63c9e549 1423
c9df406f 1424static void mv643xx_eth_free_completed_tx_descs(struct net_device *dev)
d0412d96 1425{
e5371493 1426 struct mv643xx_eth_private *mp = netdev_priv(dev);
d0412d96 1427
c9df406f
LB		 1428 if (mv643xx_eth_free_tx_descs(dev, 0) &&
1429 mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB)
1430 netif_wake_queue(dev);
d0412d96
JC		 1431}
1432
c9df406f 1433static void mv643xx_eth_free_all_tx_descs(struct net_device *dev)
1da177e4 1434{
c9df406f
LB		 1435 mv643xx_eth_free_tx_descs(dev, 1);
1436}
1da177e4 1437
c9df406f
LB		 1438static void mv643xx_eth_free_tx_rings(struct net_device *dev)
1439{
e5371493 1440 struct mv643xx_eth_private *mp = netdev_priv(dev);
84dd619e 1441
c9df406f
LB		 1442 /* Stop Tx Queues */
1443 mv643xx_eth_port_disable_tx(mp);
fa3959f4 1444
c9df406f
LB		 1445 /* Free outstanding skb's on TX ring */
1446 mv643xx_eth_free_all_tx_descs(dev);
1da177e4 1447
5daffe94 1448 BUG_ON(mp->tx_used_desc != mp->tx_curr_desc);
1da177e4 1449
c9df406f
LB		 1450 /* Free TX ring */
1451 if (mp->tx_sram_size)
5daffe94 1452 iounmap(mp->tx_desc_area);
c9df406f
LB		 1453 else
1454 dma_free_coherent(NULL, mp->tx_desc_area_size,
5daffe94 1455 mp->tx_desc_area, mp->tx_desc_dma);
c9df406f 1456}
1da177e4 1457
1da177e4 1458
c9df406f 1459/* netdev ops and related ***************************************************/
e5371493 1460static void port_reset(struct mv643xx_eth_private *mp);
1da177e4 1461
c9df406f
LB		 1462static void mv643xx_eth_update_pscr(struct net_device *dev,
1463 struct ethtool_cmd *ecmd)
1464{
e5371493 1465 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f
LB		 1466 int port_num = mp->port_num;
1467 u32 o_pscr, n_pscr;
1468 unsigned int queues;
1da177e4 1469
3cb4667c 1470 o_pscr = rdl(mp, PORT_SERIAL_CONTROL(port_num));
c9df406f 1471 n_pscr = o_pscr;
63c9e549 1472
c9df406f
LB		 1473 /* clear speed, duplex and rx buffer size fields */
1474 n_pscr &= ~(SET_MII_SPEED_TO_100 |
1475 SET_GMII_SPEED_TO_1000 |
1476 SET_FULL_DUPLEX_MODE |
1477 MAX_RX_PACKET_MASK);
1da177e4 1478
c9df406f
LB		 1479 if (ecmd->duplex == DUPLEX_FULL)
1480 n_pscr |= SET_FULL_DUPLEX_MODE;
1da177e4 1481
c9df406f
LB		 1482 if (ecmd->speed == SPEED_1000)
1483 n_pscr |= SET_GMII_SPEED_TO_1000 |
1484 MAX_RX_PACKET_9700BYTE;
1485 else {
1486 if (ecmd->speed == SPEED_100)
1487 n_pscr |= SET_MII_SPEED_TO_100;
1488 n_pscr |= MAX_RX_PACKET_1522BYTE;
1489 }
1da177e4 1490
c9df406f
LB		 1491 if (n_pscr != o_pscr) {
1492 if ((o_pscr & SERIAL_PORT_ENABLE) == 0)
3cb4667c 1493 wrl(mp, PORT_SERIAL_CONTROL(port_num), n_pscr);
c9df406f
LB		 1494 else {
1495 queues = mv643xx_eth_port_disable_tx(mp);
1da177e4 1496
c9df406f 1497 o_pscr &= ~SERIAL_PORT_ENABLE;
3cb4667c
LB		 1498 wrl(mp, PORT_SERIAL_CONTROL(port_num), o_pscr);
1499 wrl(mp, PORT_SERIAL_CONTROL(port_num), n_pscr);
1500 wrl(mp, PORT_SERIAL_CONTROL(port_num), n_pscr);
c9df406f
LB		 1501 if (queues)
1502 mv643xx_eth_port_enable_tx(mp, queues);
1503 }
1504 }
1505}
84dd619e 1506
c9df406f
LB		 1507static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id)
1508{
1509 struct net_device *dev = (struct net_device *)dev_id;
e5371493 1510 struct mv643xx_eth_private *mp = netdev_priv(dev);
cc9754b3 1511 u32 int_cause, int_cause_ext = 0;
c9df406f 1512 unsigned int port_num = mp->port_num;
ce4e2e45 1513
c9df406f 1514 /* Read interrupt cause registers */
cc9754b3
LB		 1515 int_cause = rdl(mp, INT_CAUSE(port_num)) & (INT_RX | INT_EXT);
1516 if (int_cause & INT_EXT) {
1517 int_cause_ext = rdl(mp, INT_CAUSE_EXT(port_num))
073a345c 1518 & (INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
cc9754b3 1519 wrl(mp, INT_CAUSE_EXT(port_num), ~int_cause_ext);
c9df406f 1520 }
1da177e4 1521
c9df406f 1522 /* PHY status changed */
cc9754b3 1523 if (int_cause_ext & (INT_EXT_LINK | INT_EXT_PHY)) {
c9df406f 1524 struct ethtool_cmd cmd;
1da177e4 1525
c9df406f
LB		 1526 if (mii_link_ok(&mp->mii)) {
1527 mii_ethtool_gset(&mp->mii, &cmd);
1528 mv643xx_eth_update_pscr(dev, &cmd);
073a345c 1529 mv643xx_eth_port_enable_tx(mp, 1);
c9df406f
LB		 1530 if (!netif_carrier_ok(dev)) {
1531 netif_carrier_on(dev);
1532 if (mp->tx_ring_size - mp->tx_desc_count >=
1533 MAX_DESCS_PER_SKB)
1534 netif_wake_queue(dev);
1535 }
1536 } else if (netif_carrier_ok(dev)) {
1537 netif_stop_queue(dev);
1538 netif_carrier_off(dev);
1539 }
1540 }
1da177e4 1541
e5371493 1542#ifdef MV643XX_ETH_NAPI
cc9754b3 1543 if (int_cause & INT_RX) {
c9df406f 1544 /* schedule the NAPI poll routine to maintain port */
073a345c 1545 wrl(mp, INT_MASK(port_num), 0x00000000);
1da177e4 1546
c9df406f 1547 /* wait for previous write to complete */
3cb4667c 1548 rdl(mp, INT_MASK(port_num));
1da177e4 1549
c9df406f 1550 netif_rx_schedule(dev, &mp->napi);
84dd619e 1551 }
c9df406f 1552#else
cc9754b3 1553 if (int_cause & INT_RX)
c9df406f
LB		 1554 mv643xx_eth_receive_queue(dev, INT_MAX);
1555#endif
cc9754b3 1556 if (int_cause_ext & INT_EXT_TX)
c9df406f 1557 mv643xx_eth_free_completed_tx_descs(dev);
1da177e4 1558
f2ce825d 1559 /*
c9df406f
LB		 1560 * If no real interrupt occured, exit.
1561 * This can happen when using gigE interrupt coalescing mechanism.
f2ce825d 1562 */
cc9754b3 1563 if ((int_cause == 0x0) && (int_cause_ext == 0x0))
c9df406f 1564 return IRQ_NONE;
1da177e4 1565
c9df406f 1566 return IRQ_HANDLED;
1da177e4
LT		 1567}
1568
e5371493 1569static void phy_reset(struct mv643xx_eth_private *mp)
1da177e4 1570{
c9df406f 1571 unsigned int phy_reg_data;
1da177e4 1572
c9df406f 1573 /* Reset the PHY */
cc9754b3 1574 read_smi_reg(mp, 0, &phy_reg_data);
c9df406f 1575 phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
cc9754b3 1576 write_smi_reg(mp, 0, phy_reg_data);
1da177e4 1577
c9df406f
LB		 1578 /* wait for PHY to come out of reset */
1579 do {
1580 udelay(1);
cc9754b3 1581 read_smi_reg(mp, 0, &phy_reg_data);
c9df406f 1582 } while (phy_reg_data & 0x8000);
1da177e4
LT		 1583}
1584
cc9754b3 1585static void port_start(struct net_device *dev)
1da177e4 1586{
e5371493 1587 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4
LT		 1588 unsigned int port_num = mp->port_num;
1589 int tx_curr_desc, rx_curr_desc;
d0412d96
JC		 1590 u32 pscr;
1591 struct ethtool_cmd ethtool_cmd;
1da177e4
LT		 1592
1593 /* Assignment of Tx CTRP of given queue */
5daffe94 1594 tx_curr_desc = mp->tx_curr_desc;
3cb4667c 1595 wrl(mp, TXQ_CURRENT_DESC_PTR(port_num),
cc9754b3 1596 (u32)((struct tx_desc *)mp->tx_desc_dma + tx_curr_desc));
1da177e4
LT		 1597
1598 /* Assignment of Rx CRDP of given queue */
5daffe94 1599 rx_curr_desc = mp->rx_curr_desc;
3cb4667c 1600 wrl(mp, RXQ_CURRENT_DESC_PTR(port_num),
cc9754b3 1601 (u32)((struct rx_desc *)mp->rx_desc_dma + rx_curr_desc));
1da177e4
LT		 1602
1603 /* Add the assigned Ethernet address to the port's address table */
cc9754b3 1604 uc_addr_set(mp, dev->dev_addr);
1da177e4 1605
d9a073ea
LB		 1606 /*
1607 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
1608 * frames to RX queue #0.
1609 */
1610 wrl(mp, PORT_CONFIG(port_num), 0x00000000);
01999873 1611
376489a2
LB		 1612 /*
1613 * Treat BPDUs as normal multicasts, and disable partition mode.
1614 */
1615 wrl(mp, PORT_CONFIG_EXT(port_num), 0x00000000);
1da177e4 1616
3cb4667c 1617 pscr = rdl(mp, PORT_SERIAL_CONTROL(port_num));
01999873 1618
e4d00fa9 1619 pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS);
3cb4667c 1620 wrl(mp, PORT_SERIAL_CONTROL(port_num), pscr);
1da177e4 1621
e4d00fa9
LB		 1622 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1623 DISABLE_AUTO_NEG_SPEED_GMII |
2beff77b 1624 DISABLE_AUTO_NEG_FOR_DUPLEX |
e4d00fa9
LB		 1625 DO_NOT_FORCE_LINK_FAIL |
1626 SERIAL_PORT_CONTROL_RESERVED;
1da177e4 1627
3cb4667c 1628 wrl(mp, PORT_SERIAL_CONTROL(port_num), pscr);
1da177e4 1629
e4d00fa9 1630 pscr |= SERIAL_PORT_ENABLE;
3cb4667c 1631 wrl(mp, PORT_SERIAL_CONTROL(port_num), pscr);
1da177e4
LT		 1632
1633 /* Assign port SDMA configuration */
3cb4667c 1634 wrl(mp, SDMA_CONFIG(port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1da177e4
LT		 1635
1636 /* Enable port Rx. */
073a345c 1637 mv643xx_eth_port_enable_rx(mp, 1);
8f543718
DF		 1638
1639 /* Disable port bandwidth limits by clearing MTU register */
3cb4667c 1640 wrl(mp, TX_BW_MTU(port_num), 0);
d0412d96
JC		 1641
1642 /* save phy settings across reset */
e5371493 1643 mv643xx_eth_get_settings(dev, &ethtool_cmd);
cc9754b3 1644 phy_reset(mp);
e5371493 1645 mv643xx_eth_set_settings(dev, &ethtool_cmd);
1da177e4
LT		 1646}
1647
e5371493 1648#ifdef MV643XX_ETH_COAL
e5371493 1649static unsigned int set_rx_coal(struct mv643xx_eth_private *mp,
c9df406f 1650 unsigned int delay)
1da177e4 1651{
afdb57a2 1652 unsigned int port_num = mp->port_num;
c9df406f 1653 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1da177e4 1654
c9df406f 1655 /* Set RX Coalescing mechanism */
3cb4667c 1656 wrl(mp, SDMA_CONFIG(port_num),
c9df406f 1657 ((coal & 0x3fff) << 8) |
3cb4667c 1658 (rdl(mp, SDMA_CONFIG(port_num))
c9df406f 1659 & 0xffc000ff));
1da177e4 1660
c9df406f 1661 return coal;
1da177e4 1662}
c9df406f 1663#endif
1da177e4 1664
e5371493 1665static unsigned int set_tx_coal(struct mv643xx_eth_private *mp,
c9df406f 1666 unsigned int delay)
1da177e4 1667{
c9df406f 1668 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1da177e4 1669
c9df406f 1670 /* Set TX Coalescing mechanism */
3cb4667c 1671 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), coal << 4);
1da177e4 1672
c9df406f 1673 return coal;
1da177e4
LT		 1674}
1675
e5371493 1676static void port_init(struct mv643xx_eth_private *mp)
16e03018 1677{
cc9754b3 1678 port_reset(mp);
16e03018 1679
cc9754b3 1680 init_mac_tables(mp);
16e03018
DF		 1681}
1682
c9df406f 1683static int mv643xx_eth_open(struct net_device *dev)
16e03018 1684{
e5371493 1685 struct mv643xx_eth_private *mp = netdev_priv(dev);
afdb57a2 1686 unsigned int port_num = mp->port_num;
c9df406f
LB		 1687 unsigned int size;
1688 int err;
16e03018 1689
c9df406f 1690 /* Clear any pending ethernet port interrupts */
3cb4667c
LB		 1691 wrl(mp, INT_CAUSE(port_num), 0);
1692 wrl(mp, INT_CAUSE_EXT(port_num), 0);
c9df406f 1693 /* wait for previous write to complete */
3cb4667c 1694 rdl(mp, INT_CAUSE_EXT(port_num));
c9df406f
LB		 1695
1696 err = request_irq(dev->irq, mv643xx_eth_int_handler,
1697 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
1698 if (err) {
1699 printk(KERN_ERR "%s: Can not assign IRQ\n", dev->name);
1700 return -EAGAIN;
16e03018
DF		 1701 }
1702
cc9754b3 1703 port_init(mp);
16e03018 1704
c9df406f
LB		 1705 memset(&mp->timeout, 0, sizeof(struct timer_list));
1706 mp->timeout.function = mv643xx_eth_rx_refill_descs_timer_wrapper;
1707 mp->timeout.data = (unsigned long)dev;
16e03018 1708
c9df406f
LB		 1709 /* Allocate RX and TX skb rings */
1710 mp->rx_skb = kmalloc(sizeof(*mp->rx_skb) * mp->rx_ring_size,
1711 GFP_KERNEL);
1712 if (!mp->rx_skb) {
1713 printk(KERN_ERR "%s: Cannot allocate Rx skb ring\n", dev->name);
1714 err = -ENOMEM;
1715 goto out_free_irq;
1716 }
1717 mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size,
1718 GFP_KERNEL);
1719 if (!mp->tx_skb) {
1720 printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name);
1721 err = -ENOMEM;
1722 goto out_free_rx_skb;
1723 }
16e03018 1724
c9df406f
LB		 1725 /* Allocate TX ring */
1726 mp->tx_desc_count = 0;
cc9754b3 1727 size = mp->tx_ring_size * sizeof(struct tx_desc);
c9df406f 1728 mp->tx_desc_area_size = size;
16e03018 1729
c9df406f 1730 if (mp->tx_sram_size) {
5daffe94 1731 mp->tx_desc_area = ioremap(mp->tx_sram_addr,
c9df406f
LB		 1732 mp->tx_sram_size);
1733 mp->tx_desc_dma = mp->tx_sram_addr;
1734 } else
5daffe94 1735 mp->tx_desc_area = dma_alloc_coherent(NULL, size,
c9df406f
LB		 1736 &mp->tx_desc_dma,
1737 GFP_KERNEL);
16e03018 1738
5daffe94 1739 if (!mp->tx_desc_area) {
c9df406f
LB		 1740 printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n",
1741 dev->name, size);
1742 err = -ENOMEM;
1743 goto out_free_tx_skb;
1744 }
5daffe94
LB		 1745 BUG_ON((u32) mp->tx_desc_area & 0xf); /* check 16-byte alignment */
1746 memset((void *)mp->tx_desc_area, 0, mp->tx_desc_area_size);
16e03018 1747
c9df406f 1748 ether_init_tx_desc_ring(mp);
16e03018 1749
c9df406f
LB		 1750 /* Allocate RX ring */
1751 mp->rx_desc_count = 0;
cc9754b3 1752 size = mp->rx_ring_size * sizeof(struct rx_desc);
c9df406f 1753 mp->rx_desc_area_size = size;
16e03018 1754
c9df406f 1755 if (mp->rx_sram_size) {
5daffe94 1756 mp->rx_desc_area = ioremap(mp->rx_sram_addr,
c9df406f
LB		 1757 mp->rx_sram_size);
1758 mp->rx_desc_dma = mp->rx_sram_addr;
1759 } else
5daffe94 1760 mp->rx_desc_area = dma_alloc_coherent(NULL, size,
c9df406f
LB		 1761 &mp->rx_desc_dma,
1762 GFP_KERNEL);
16e03018 1763
5daffe94 1764 if (!mp->rx_desc_area) {
c9df406f
LB		 1765 printk(KERN_ERR "%s: Cannot allocate Rx ring (size %d bytes)\n",
1766 dev->name, size);
1767 printk(KERN_ERR "%s: Freeing previously allocated TX queues...",
1768 dev->name);
1769 if (mp->rx_sram_size)
5daffe94 1770 iounmap(mp->tx_desc_area);
c9df406f
LB		 1771 else
1772 dma_free_coherent(NULL, mp->tx_desc_area_size,
5daffe94 1773 mp->tx_desc_area, mp->tx_desc_dma);
c9df406f
LB		 1774 err = -ENOMEM;
1775 goto out_free_tx_skb;
1776 }
5daffe94 1777 memset((void *)mp->rx_desc_area, 0, size);
16e03018 1778
c9df406f 1779 ether_init_rx_desc_ring(mp);
16e03018 1780
c9df406f 1781 mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */
16e03018 1782
e5371493 1783#ifdef MV643XX_ETH_NAPI
c9df406f
LB		 1784 napi_enable(&mp->napi);
1785#endif
16e03018 1786
cc9754b3 1787 port_start(dev);
16e03018 1788
c9df406f 1789 /* Interrupt Coalescing */
b4de9051 1790
e5371493
LB		 1791#ifdef MV643XX_ETH_COAL
1792 mp->rx_int_coal = set_rx_coal(mp, MV643XX_ETH_RX_COAL);
c9df406f
LB		 1793#endif
1794
e5371493 1795 mp->tx_int_coal = set_tx_coal(mp, MV643XX_ETH_TX_COAL);
16e03018 1796
c9df406f 1797 /* Unmask phy and link status changes interrupts */
073a345c 1798 wrl(mp, INT_MASK_EXT(port_num), INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
16e03018 1799
c9df406f 1800 /* Unmask RX buffer and TX end interrupt */
073a345c 1801 wrl(mp, INT_MASK(port_num), INT_RX | INT_EXT);
16e03018 1802
c9df406f
LB		 1803 return 0;
1804
1805out_free_tx_skb:
1806 kfree(mp->tx_skb);
1807out_free_rx_skb:
1808 kfree(mp->rx_skb);
1809out_free_irq:
1810 free_irq(dev->irq, dev);
1811
1812 return err;
16e03018
DF		 1813}
1814
e5371493 1815static void port_reset(struct mv643xx_eth_private *mp)
1da177e4 1816{
afdb57a2 1817 unsigned int port_num = mp->port_num;
c9df406f 1818 unsigned int reg_data;
1da177e4 1819
c9df406f
LB		 1820 mv643xx_eth_port_disable_tx(mp);
1821 mv643xx_eth_port_disable_rx(mp);
1da177e4 1822
c9df406f 1823 /* Clear all MIB counters */
cc9754b3 1824 clear_mib_counters(mp);
c9df406f
LB		 1825
1826 /* Reset the Enable bit in the Configuration Register */
3cb4667c 1827 reg_data = rdl(mp, PORT_SERIAL_CONTROL(port_num));
c9df406f
LB		 1828 reg_data &= ~(SERIAL_PORT_ENABLE |
1829 DO_NOT_FORCE_LINK_FAIL |
1830 FORCE_LINK_PASS);
3cb4667c 1831 wrl(mp, PORT_SERIAL_CONTROL(port_num), reg_data);
1da177e4
LT		 1832}
1833
c9df406f 1834static int mv643xx_eth_stop(struct net_device *dev)
1da177e4 1835{
e5371493 1836 struct mv643xx_eth_private *mp = netdev_priv(dev);
afdb57a2 1837 unsigned int port_num = mp->port_num;
1da177e4 1838
c9df406f 1839 /* Mask all interrupts on ethernet port */
073a345c 1840 wrl(mp, INT_MASK(port_num), 0x00000000);
c9df406f 1841 /* wait for previous write to complete */
3cb4667c 1842 rdl(mp, INT_MASK(port_num));
1da177e4 1843
e5371493 1844#ifdef MV643XX_ETH_NAPI
c9df406f
LB		 1845 napi_disable(&mp->napi);
1846#endif
1847 netif_carrier_off(dev);
1848 netif_stop_queue(dev);
1da177e4 1849
cc9754b3 1850 port_reset(mp);
1da177e4 1851
c9df406f
LB		 1852 mv643xx_eth_free_tx_rings(dev);
1853 mv643xx_eth_free_rx_rings(dev);
1da177e4 1854
c9df406f 1855 free_irq(dev->irq, dev);
1da177e4 1856
c9df406f 1857 return 0;
1da177e4
LT		 1858}
1859
c9df406f 1860static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1da177e4 1861{
e5371493 1862 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1863
c9df406f 1864 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
1da177e4
LT		 1865}
1866
c9df406f 1867static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 1868{
c9df406f
LB		 1869 if ((new_mtu > 9500) || (new_mtu < 64))
1870 return -EINVAL;
1da177e4 1871
c9df406f
LB		 1872 dev->mtu = new_mtu;
1873 if (!netif_running(dev))
1874 return 0;
1da177e4 1875
c9df406f
LB		 1876 /*
1877 * Stop and then re-open the interface. This will allocate RX
1878 * skbs of the new MTU.
1879 * There is a possible danger that the open will not succeed,
1880 * due to memory being full, which might fail the open function.
1881 */
1882 mv643xx_eth_stop(dev);
1883 if (mv643xx_eth_open(dev)) {
1884 printk(KERN_ERR "%s: Fatal error on opening device\n",
1885 dev->name);
1886 }
1887
1888 return 0;
1da177e4
LT		 1889}
1890
c9df406f 1891static void mv643xx_eth_tx_timeout_task(struct work_struct *ugly)
1da177e4 1892{
e5371493 1893 struct mv643xx_eth_private *mp = container_of(ugly, struct mv643xx_eth_private,
c9df406f
LB		 1894 tx_timeout_task);
1895 struct net_device *dev = mp->dev;
1da177e4 1896
c9df406f
LB		 1897 if (!netif_running(dev))
1898 return;
1da177e4 1899
c9df406f
LB		 1900 netif_stop_queue(dev);
1901
cc9754b3
LB		 1902 port_reset(mp);
1903 port_start(dev);
c9df406f
LB		 1904
1905 if (mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB)
1906 netif_wake_queue(dev);
1907}
1908
c9df406f 1909static void mv643xx_eth_tx_timeout(struct net_device *dev)
1da177e4 1910{
e5371493 1911 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1912
c9df406f 1913 printk(KERN_INFO "%s: TX timeout ", dev->name);
d0412d96 1914
c9df406f
LB		 1915 /* Do the reset outside of interrupt context */
1916 schedule_work(&mp->tx_timeout_task);
1da177e4
LT		 1917}
1918
c9df406f 1919#ifdef CONFIG_NET_POLL_CONTROLLER
e5371493 1920static void mv643xx_eth_netpoll(struct net_device *netdev)
9f8dd319 1921{
e5371493 1922 struct mv643xx_eth_private *mp = netdev_priv(netdev);
c9df406f
LB		 1923 int port_num = mp->port_num;
1924
073a345c 1925 wrl(mp, INT_MASK(port_num), 0x00000000);
c9df406f 1926 /* wait for previous write to complete */
3cb4667c 1927 rdl(mp, INT_MASK(port_num));
c9df406f
LB		 1928
1929 mv643xx_eth_int_handler(netdev->irq, netdev);
1930
073a345c 1931 wrl(mp, INT_MASK(port_num), INT_RX | INT_CAUSE_EXT);
9f8dd319 1932}
c9df406f 1933#endif
9f8dd319 1934
e5371493 1935static int mv643xx_eth_mdio_read(struct net_device *dev, int phy_id, int location)
9f8dd319 1936{
e5371493 1937 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f
LB		 1938 int val;
1939
cc9754b3 1940 read_smi_reg(mp, location, &val);
c9df406f 1941 return val;
9f8dd319
DF		 1942}
1943
e5371493 1944static void mv643xx_eth_mdio_write(struct net_device *dev, int phy_id, int location, int val)
9f8dd319 1945{
e5371493 1946 struct mv643xx_eth_private *mp = netdev_priv(dev);
cc9754b3 1947 write_smi_reg(mp, location, val);
c9df406f 1948}
9f8dd319 1949
9f8dd319 1950
c9df406f 1951/* platform glue ************************************************************/
e5371493
LB		 1952static void
1953mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
1954 struct mbus_dram_target_info *dram)
c9df406f 1955{
cc9754b3 1956 void __iomem *base = msp->base;
c9df406f
LB		 1957 u32 win_enable;
1958 u32 win_protect;
1959 int i;
9f8dd319 1960
c9df406f
LB		 1961 for (i = 0; i < 6; i++) {
1962 writel(0, base + WINDOW_BASE(i));
1963 writel(0, base + WINDOW_SIZE(i));
1964 if (i < 4)
1965 writel(0, base + WINDOW_REMAP_HIGH(i));
9f8dd319
DF		 1966 }
1967
c9df406f
LB		 1968 win_enable = 0x3f;
1969 win_protect = 0;
1970
1971 for (i = 0; i < dram->num_cs; i++) {
1972 struct mbus_dram_window *cs = dram->cs + i;
1973
1974 writel((cs->base & 0xffff0000) |
1975 (cs->mbus_attr << 8) |
1976 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
1977 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
1978
1979 win_enable &= ~(1 << i);
1980 win_protect |= 3 << (2 * i);
1981 }
1982
1983 writel(win_enable, base + WINDOW_BAR_ENABLE);
1984 msp->win_protect = win_protect;
9f8dd319
DF		 1985}
1986
c9df406f 1987static int mv643xx_eth_shared_probe(struct platform_device *pdev)
9f8dd319 1988{
e5371493 1989 static int mv643xx_eth_version_printed = 0;
c9df406f 1990 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
e5371493 1991 struct mv643xx_eth_shared_private *msp;
c9df406f
LB		 1992 struct resource *res;
1993 int ret;
9f8dd319 1994
e5371493 1995 if (!mv643xx_eth_version_printed++)
c9df406f 1996 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
9f8dd319 1997
c9df406f
LB		 1998 ret = -EINVAL;
1999 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2000 if (res == NULL)
2001 goto out;
9f8dd319 2002
c9df406f
LB		 2003 ret = -ENOMEM;
2004 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2005 if (msp == NULL)
2006 goto out;
2007 memset(msp, 0, sizeof(*msp));
2008
cc9754b3
LB		 2009 msp->base = ioremap(res->start, res->end - res->start + 1);
2010 if (msp->base == NULL)
c9df406f
LB		 2011 goto out_free;
2012
2013 spin_lock_init(&msp->phy_lock);
2014 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
2015
2016 platform_set_drvdata(pdev, msp);
2017
2018 /*
2019 * (Re-)program MBUS remapping windows if we are asked to.
2020 */
2021 if (pd != NULL && pd->dram != NULL)
2022 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2023
2024 return 0;
2025
2026out_free:
2027 kfree(msp);
2028out:
2029 return ret;
2030}
2031
2032static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2033{
e5371493 2034 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
c9df406f 2035
cc9754b3 2036 iounmap(msp->base);
c9df406f
LB		 2037 kfree(msp);
2038
2039 return 0;
9f8dd319
DF		 2040}
2041
c9df406f
LB		 2042static struct platform_driver mv643xx_eth_shared_driver = {
2043 .probe = mv643xx_eth_shared_probe,
2044 .remove = mv643xx_eth_shared_remove,
2045 .driver = {
2046 .name = MV643XX_ETH_SHARED_NAME,
2047 .owner = THIS_MODULE,
2048 },
2049};
2050
e5371493 2051static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
1da177e4 2052{
c9df406f
LB		 2053 u32 reg_data;
2054 int addr_shift = 5 * mp->port_num;
1da177e4 2055
3cb4667c 2056 reg_data = rdl(mp, PHY_ADDR);
c9df406f
LB		 2057 reg_data &= ~(0x1f << addr_shift);
2058 reg_data |= (phy_addr & 0x1f) << addr_shift;
3cb4667c 2059 wrl(mp, PHY_ADDR, reg_data);
1da177e4
LT		 2060}
2061
e5371493 2062static int phy_addr_get(struct mv643xx_eth_private *mp)
1da177e4 2063{
c9df406f 2064 unsigned int reg_data;
1da177e4 2065
3cb4667c 2066 reg_data = rdl(mp, PHY_ADDR);
1da177e4 2067
c9df406f 2068 return ((reg_data >> (5 * mp->port_num)) & 0x1f);
1da177e4
LT		 2069}
2070
e5371493 2071static int phy_detect(struct mv643xx_eth_private *mp)
1da177e4 2072{
c9df406f
LB		 2073 unsigned int phy_reg_data0;
2074 int auto_neg;
1da177e4 2075
cc9754b3 2076 read_smi_reg(mp, 0, &phy_reg_data0);
c9df406f
LB		 2077 auto_neg = phy_reg_data0 & 0x1000;
2078 phy_reg_data0 ^= 0x1000; /* invert auto_neg */
cc9754b3 2079 write_smi_reg(mp, 0, phy_reg_data0);
1da177e4 2080
cc9754b3 2081 read_smi_reg(mp, 0, &phy_reg_data0);
c9df406f
LB		 2082 if ((phy_reg_data0 & 0x1000) == auto_neg)
2083 return -ENODEV; /* change didn't take */
1da177e4 2084
c9df406f 2085 phy_reg_data0 ^= 0x1000;
cc9754b3 2086 write_smi_reg(mp, 0, phy_reg_data0);
c9df406f 2087 return 0;
1da177e4
LT		 2088}
2089
c9df406f
LB		 2090static void mv643xx_init_ethtool_cmd(struct net_device *dev, int phy_address,
2091 int speed, int duplex,
2092 struct ethtool_cmd *cmd)
c28a4f89 2093{
e5371493 2094 struct mv643xx_eth_private *mp = netdev_priv(dev);
c28a4f89 2095
c9df406f 2096 memset(cmd, 0, sizeof(*cmd));
c28a4f89 2097
c9df406f
LB		 2098 cmd->port = PORT_MII;
2099 cmd->transceiver = XCVR_INTERNAL;
2100 cmd->phy_address = phy_address;
2101
2102 if (speed == 0) {
2103 cmd->autoneg = AUTONEG_ENABLE;
2104 /* mii lib checks, but doesn't use speed on AUTONEG_ENABLE */
2105 cmd->speed = SPEED_100;
2106 cmd->advertising = ADVERTISED_10baseT_Half |
2107 ADVERTISED_10baseT_Full |
2108 ADVERTISED_100baseT_Half |
2109 ADVERTISED_100baseT_Full;
2110 if (mp->mii.supports_gmii)
2111 cmd->advertising |= ADVERTISED_1000baseT_Full;
2112 } else {
2113 cmd->autoneg = AUTONEG_DISABLE;
2114 cmd->speed = speed;
2115 cmd->duplex = duplex;
2116 }
c28a4f89
JC		 2117}
2118
c9df406f 2119static int mv643xx_eth_probe(struct platform_device *pdev)
1da177e4 2120{
c9df406f
LB		 2121 struct mv643xx_eth_platform_data *pd;
2122 int port_num;
e5371493 2123 struct mv643xx_eth_private *mp;
c9df406f
LB		 2124 struct net_device *dev;
2125 u8 *p;
2126 struct resource *res;
2127 int err;
2128 struct ethtool_cmd cmd;
2129 int duplex = DUPLEX_HALF;
2130 int speed = 0; /* default to auto-negotiation */
2131 DECLARE_MAC_BUF(mac);
1da177e4 2132
c9df406f
LB		 2133 pd = pdev->dev.platform_data;
2134 if (pd == NULL) {
2135 printk(KERN_ERR "No mv643xx_eth_platform_data\n");
2136 return -ENODEV;
2137 }
1da177e4 2138
c9df406f
LB		 2139 if (pd->shared == NULL) {
2140 printk(KERN_ERR "No mv643xx_eth_platform_data->shared\n");
2141 return -ENODEV;
2142 }
8f518703 2143
e5371493 2144 dev = alloc_etherdev(sizeof(struct mv643xx_eth_private));
c9df406f
LB		 2145 if (!dev)
2146 return -ENOMEM;
1da177e4 2147
c9df406f 2148 platform_set_drvdata(pdev, dev);
1da177e4 2149
c9df406f
LB		 2150 mp = netdev_priv(dev);
2151 mp->dev = dev;
e5371493
LB		 2152#ifdef MV643XX_ETH_NAPI
2153 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 64);
c9df406f 2154#endif
1da177e4 2155
c9df406f
LB		 2156 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2157 BUG_ON(!res);
2158 dev->irq = res->start;
1da177e4 2159
c9df406f
LB		 2160 dev->open = mv643xx_eth_open;
2161 dev->stop = mv643xx_eth_stop;
2162 dev->hard_start_xmit = mv643xx_eth_start_xmit;
2163 dev->set_mac_address = mv643xx_eth_set_mac_address;
2164 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
2165
2166 /* No need to Tx Timeout */
2167 dev->tx_timeout = mv643xx_eth_tx_timeout;
2168
2169#ifdef CONFIG_NET_POLL_CONTROLLER
e5371493 2170 dev->poll_controller = mv643xx_eth_netpoll;
c9df406f
LB		 2171#endif
2172
2173 dev->watchdog_timeo = 2 * HZ;
2174 dev->base_addr = 0;
2175 dev->change_mtu = mv643xx_eth_change_mtu;
2176 dev->do_ioctl = mv643xx_eth_do_ioctl;
e5371493 2177 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
1da177e4 2178
e5371493 2179#ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
c9df406f 2180#ifdef MAX_SKB_FRAGS
b4de9051 2181 /*
c9df406f
LB		 2182 * Zero copy can only work if we use Discovery II memory. Else, we will
2183 * have to map the buffers to ISA memory which is only 16 MB
b4de9051 2184 */
c9df406f
LB		 2185 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2186#endif
2187#endif
1da177e4 2188
c9df406f
LB		 2189 /* Configure the timeout task */
2190 INIT_WORK(&mp->tx_timeout_task, mv643xx_eth_tx_timeout_task);
1da177e4 2191
c9df406f 2192 spin_lock_init(&mp->lock);
1da177e4 2193
c9df406f
LB		 2194 mp->shared = platform_get_drvdata(pd->shared);
2195 port_num = mp->port_num = pd->port_number;
8f518703 2196
c9df406f
LB		 2197 if (mp->shared->win_protect)
2198 wrl(mp, WINDOW_PROTECT(port_num), mp->shared->win_protect);
1da177e4 2199
c9df406f
LB		 2200 mp->shared_smi = mp->shared;
2201 if (pd->shared_smi != NULL)
2202 mp->shared_smi = platform_get_drvdata(pd->shared_smi);
2203
2204 /* set default config values */
cc9754b3
LB		 2205 uc_addr_get(mp, dev->dev_addr);
2206 mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2207 mp->tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
c9df406f
LB		 2208
2209 if (is_valid_ether_addr(pd->mac_addr))
2210 memcpy(dev->dev_addr, pd->mac_addr, 6);
2211
2212 if (pd->phy_addr || pd->force_phy_addr)
cc9754b3 2213 phy_addr_set(mp, pd->phy_addr);
8f518703 2214
c9df406f
LB		 2215 if (pd->rx_queue_size)
2216 mp->rx_ring_size = pd->rx_queue_size;
1da177e4 2217
c9df406f
LB		 2218 if (pd->tx_queue_size)
2219 mp->tx_ring_size = pd->tx_queue_size;
1da177e4 2220
c9df406f
LB		 2221 if (pd->tx_sram_size) {
2222 mp->tx_sram_size = pd->tx_sram_size;
2223 mp->tx_sram_addr = pd->tx_sram_addr;
2224 }
1da177e4 2225
c9df406f
LB		 2226 if (pd->rx_sram_size) {
2227 mp->rx_sram_size = pd->rx_sram_size;
2228 mp->rx_sram_addr = pd->rx_sram_addr;
2229 }
1da177e4 2230
c9df406f
LB		 2231 duplex = pd->duplex;
2232 speed = pd->speed;
1da177e4 2233
c9df406f
LB		 2234 /* Hook up MII support for ethtool */
2235 mp->mii.dev = dev;
e5371493
LB		 2236 mp->mii.mdio_read = mv643xx_eth_mdio_read;
2237 mp->mii.mdio_write = mv643xx_eth_mdio_write;
cc9754b3 2238 mp->mii.phy_id = phy_addr_get(mp);
c9df406f
LB		 2239 mp->mii.phy_id_mask = 0x3f;
2240 mp->mii.reg_num_mask = 0x1f;
1da177e4 2241
cc9754b3 2242 err = phy_detect(mp);
c9df406f
LB		 2243 if (err) {
2244 pr_debug("%s: No PHY detected at addr %d\n",
cc9754b3 2245 dev->name, phy_addr_get(mp));
c9df406f
LB		 2246 goto out;
2247 }
1da177e4 2248
cc9754b3 2249 phy_reset(mp);
c9df406f
LB		 2250 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
2251 mv643xx_init_ethtool_cmd(dev, mp->mii.phy_id, speed, duplex, &cmd);
2252 mv643xx_eth_update_pscr(dev, &cmd);
e5371493 2253 mv643xx_eth_set_settings(dev, &cmd);
8f518703 2254
c9df406f
LB		 2255 SET_NETDEV_DEV(dev, &pdev->dev);
2256 err = register_netdev(dev);
2257 if (err)
2258 goto out;
1da177e4 2259
c9df406f
LB		 2260 p = dev->dev_addr;
2261 printk(KERN_NOTICE
2262 "%s: port %d with MAC address %s\n",
2263 dev->name, port_num, print_mac(mac, p));
1da177e4 2264
c9df406f
LB		 2265 if (dev->features & NETIF_F_SG)
2266 printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name);
1da177e4 2267
c9df406f
LB		 2268 if (dev->features & NETIF_F_IP_CSUM)
2269 printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n",
2270 dev->name);
1da177e4 2271
e5371493 2272#ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
c9df406f
LB		 2273 printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name);
2274#endif
1da177e4 2275
e5371493 2276#ifdef MV643XX_ETH_COAL
c9df406f
LB		 2277 printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n",
2278 dev->name);
2279#endif
1da177e4 2280
e5371493 2281#ifdef MV643XX_ETH_NAPI
c9df406f
LB		 2282 printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name);
2283#endif
1da177e4 2284
c9df406f
LB		 2285 if (mp->tx_sram_size > 0)
2286 printk(KERN_NOTICE "%s: Using SRAM\n", dev->name);
1da177e4 2287
c9df406f 2288 return 0;
1da177e4 2289
c9df406f
LB		 2290out:
2291 free_netdev(dev);
1da177e4 2292
c9df406f 2293 return err;
1da177e4
LT		 2294}
2295
c9df406f 2296static int mv643xx_eth_remove(struct platform_device *pdev)
1da177e4 2297{
c9df406f 2298 struct net_device *dev = platform_get_drvdata(pdev);
1da177e4 2299
c9df406f
LB		 2300 unregister_netdev(dev);
2301 flush_scheduled_work();
2302
2303 free_netdev(dev);
2304 platform_set_drvdata(pdev, NULL);
2305 return 0;
1da177e4
LT		 2306}
2307
c9df406f 2308static void mv643xx_eth_shutdown(struct platform_device *pdev)
d0412d96 2309{
c9df406f 2310 struct net_device *dev = platform_get_drvdata(pdev);
e5371493 2311 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2312 unsigned int port_num = mp->port_num;
d0412d96 2313
c9df406f 2314 /* Mask all interrupts on ethernet port */
3cb4667c
LB		 2315 wrl(mp, INT_MASK(port_num), 0);
2316 rdl(mp, INT_MASK(port_num));
c9df406f 2317
cc9754b3 2318 port_reset(mp);
d0412d96
JC		 2319}
2320
c9df406f
LB		 2321static struct platform_driver mv643xx_eth_driver = {
2322 .probe = mv643xx_eth_probe,
2323 .remove = mv643xx_eth_remove,
2324 .shutdown = mv643xx_eth_shutdown,
2325 .driver = {
2326 .name = MV643XX_ETH_NAME,
2327 .owner = THIS_MODULE,
2328 },
2329};
2330
e5371493 2331static int __init mv643xx_eth_init_module(void)
d0412d96 2332{
c9df406f 2333 int rc;
d0412d96 2334
c9df406f
LB		 2335 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2336 if (!rc) {
2337 rc = platform_driver_register(&mv643xx_eth_driver);
2338 if (rc)
2339 platform_driver_unregister(&mv643xx_eth_shared_driver);
2340 }
2341 return rc;
d0412d96
JC		 2342}
2343
e5371493 2344static void __exit mv643xx_eth_cleanup_module(void)
d0412d96 2345{
c9df406f
LB		 2346 platform_driver_unregister(&mv643xx_eth_driver);
2347 platform_driver_unregister(&mv643xx_eth_shared_driver);
d0412d96
JC		 2348}
2349
e5371493
LB		 2350module_init(mv643xx_eth_init_module);
2351module_exit(mv643xx_eth_cleanup_module);
1da177e4 2352
c9df406f
LB		 2353MODULE_LICENSE("GPL");
2354MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani"
2355 " and Dale Farnsworth");
2356MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
2357MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
2358MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
Linux 6.x block layer and io_uring tree(s)