[linux-block.git] / drivers / net / mlx4 / mr.c

/*
 * Copyright (c) 2004 Topspin Communications.  All rights reserved.
 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
 * Copyright (c) 2006, 2007 Cisco Systems, Inc.  All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#include <linux/init.h>
#include <linux/errno.h>

#include <linux/mlx4/cmd.h>

#include "mlx4.h"
#include "icm.h"

/*
 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
 */
struct mlx4_mpt_entry {
	__be32 flags;
	__be32 qpn;
	__be32 key;
	__be32 pd;
	__be64 start;
	__be64 length;
	__be32 lkey;
	__be32 win_cnt;
	u8	reserved1[3];
	u8	mtt_rep;
	__be64 mtt_seg;
	__be32 mtt_sz;
	__be32 entity_size;
	__be32 first_byte_offset;
} __attribute__((packed));

#define MLX4_MPT_FLAG_SW_OWNS	    (0xfUL << 28)
#define MLX4_MPT_FLAG_MIO	    (1 << 17)
#define MLX4_MPT_FLAG_BIND_ENABLE   (1 << 15)
#define MLX4_MPT_FLAG_PHYSICAL	    (1 <<  9)
#define MLX4_MPT_FLAG_REGION	    (1 <<  8)

#define MLX4_MTT_FLAG_PRESENT		1

static u32 mlx4_buddy_alloc(struct mlx4_buddy *buddy, int order)
{
	int o;
	int m;
	u32 seg;

	spin_lock(&buddy->lock);

	for (o = order; o <= buddy->max_order; ++o) {
		m = 1 << (buddy->max_order - o);
		seg = find_first_bit(buddy->bits[o], m);
		if (seg < m)
			goto found;
	}

	spin_unlock(&buddy->lock);
	return -1;

 found:
	clear_bit(seg, buddy->bits[o]);

	while (o > order) {
		--o;
		seg <<= 1;
		set_bit(seg ^ 1, buddy->bits[o]);
	}

	spin_unlock(&buddy->lock);

	seg <<= order;

	return seg;
}

static void mlx4_buddy_free(struct mlx4_buddy *buddy, u32 seg, int order)
{
	seg >>= order;

	spin_lock(&buddy->lock);

	while (test_bit(seg ^ 1, buddy->bits[order])) {
		clear_bit(seg ^ 1, buddy->bits[order]);
		seg >>= 1;
		++order;
	}

	set_bit(seg, buddy->bits[order]);

	spin_unlock(&buddy->lock);
}

static int __devinit mlx4_buddy_init(struct mlx4_buddy *buddy, int max_order)
{
	int i, s;

	buddy->max_order = max_order;
	spin_lock_init(&buddy->lock);

	buddy->bits = kzalloc((buddy->max_order + 1) * sizeof (long *),
			      GFP_KERNEL);
	if (!buddy->bits)
		goto err_out;

	for (i = 0; i <= buddy->max_order; ++i) {
		s = BITS_TO_LONGS(1 << (buddy->max_order - i));
		buddy->bits[i] = kmalloc(s * sizeof (long), GFP_KERNEL);
		if (!buddy->bits[i])
			goto err_out_free;
		bitmap_zero(buddy->bits[i], 1 << (buddy->max_order - i));
	}

	set_bit(0, buddy->bits[buddy->max_order]);

	return 0;

err_out_free:
	for (i = 0; i <= buddy->max_order; ++i)
		kfree(buddy->bits[i]);

	kfree(buddy->bits);

err_out:
	return -ENOMEM;
}

static void mlx4_buddy_cleanup(struct mlx4_buddy *buddy)
{
	int i;

	for (i = 0; i <= buddy->max_order; ++i)
		kfree(buddy->bits[i]);

	kfree(buddy->bits);
}

static u32 mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order)
{
	struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
	u32 seg;

	seg = mlx4_buddy_alloc(&mr_table->mtt_buddy, order);
	if (seg == -1)
		return -1;

	if (mlx4_table_get_range(dev, &mr_table->mtt_table, seg,
				 seg + (1 << order) - 1)) {
		mlx4_buddy_free(&mr_table->mtt_buddy, seg, order);
		return -1;
	}

	return seg;
}

int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
		  struct mlx4_mtt *mtt)
{
	int i;

	if (!npages) {
		mtt->order      = -1;
		mtt->page_shift = MLX4_ICM_PAGE_SHIFT;
		return 0;
	} else
		mtt->page_shift = page_shift;

	for (mtt->order = 0, i = MLX4_MTT_ENTRY_PER_SEG; i < npages; i <<= 1)
		++mtt->order;

	mtt->first_seg = mlx4_alloc_mtt_range(dev, mtt->order);
	if (mtt->first_seg == -1)
		return -ENOMEM;

	return 0;
}
EXPORT_SYMBOL_GPL(mlx4_mtt_init);

void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt)
{
	struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;

	if (mtt->order < 0)
		return;

	mlx4_buddy_free(&mr_table->mtt_buddy, mtt->first_seg, mtt->order);
	mlx4_table_put_range(dev, &mr_table->mtt_table, mtt->first_seg,
			     mtt->first_seg + (1 << mtt->order) - 1);
}
EXPORT_SYMBOL_GPL(mlx4_mtt_cleanup);

u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt)
{
	return (u64) mtt->first_seg * dev->caps.mtt_entry_sz;
}
EXPORT_SYMBOL_GPL(mlx4_mtt_addr);

static u32 hw_index_to_key(u32 ind)
{
	return (ind >> 24) | (ind << 8);
}

static u32 key_to_hw_index(u32 key)
{
	return (key << 24) | (key >> 8);
}

static int mlx4_SW2HW_MPT(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
			  int mpt_index)
{
	return mlx4_cmd(dev, mailbox->dma, mpt_index, 0, MLX4_CMD_SW2HW_MPT,
			MLX4_CMD_TIME_CLASS_B);
}

static int mlx4_HW2SW_MPT(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
			  int mpt_index)
{
	return mlx4_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, mpt_index,
			    !mailbox, MLX4_CMD_HW2SW_MPT, MLX4_CMD_TIME_CLASS_B);
}

int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
		  int npages, int page_shift, struct mlx4_mr *mr)
{
	struct mlx4_priv *priv = mlx4_priv(dev);
	u32 index;
	int err;

	index = mlx4_bitmap_alloc(&priv->mr_table.mpt_bitmap);
	if (index == -1)
		return -ENOMEM;

	mr->iova       = iova;
	mr->size       = size;
	mr->pd	       = pd;
	mr->access     = access;
	mr->enabled    = 0;
	mr->key	       = hw_index_to_key(index);

	err = mlx4_mtt_init(dev, npages, page_shift, &mr->mtt);
	if (err)
		mlx4_bitmap_free(&priv->mr_table.mpt_bitmap, index);

	return err;
}
EXPORT_SYMBOL_GPL(mlx4_mr_alloc);

void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr)
{
	struct mlx4_priv *priv = mlx4_priv(dev);
	int err;

	if (mr->enabled) {
		err = mlx4_HW2SW_MPT(dev, NULL,
				     key_to_hw_index(mr->key) &
				     (dev->caps.num_mpts - 1));
		if (err)
			mlx4_warn(dev, "HW2SW_MPT failed (%d)\n", err);
	}

	mlx4_mtt_cleanup(dev, &mr->mtt);
	mlx4_bitmap_free(&priv->mr_table.mpt_bitmap, key_to_hw_index(mr->key));
}
EXPORT_SYMBOL_GPL(mlx4_mr_free);

int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr)
{
	struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
	struct mlx4_cmd_mailbox *mailbox;
	struct mlx4_mpt_entry *mpt_entry;
	int err;

	err = mlx4_table_get(dev, &mr_table->dmpt_table, key_to_hw_index(mr->key));
	if (err)
		return err;

	mailbox = mlx4_alloc_cmd_mailbox(dev);
	if (IS_ERR(mailbox)) {
		err = PTR_ERR(mailbox);
		goto err_table;
	}
	mpt_entry = mailbox->buf;

	memset(mpt_entry, 0, sizeof *mpt_entry);

	mpt_entry->flags = cpu_to_be32(MLX4_MPT_FLAG_SW_OWNS	 |
				       MLX4_MPT_FLAG_MIO	 |
				       MLX4_MPT_FLAG_REGION	 |
				       mr->access);

	mpt_entry->key	       = cpu_to_be32(key_to_hw_index(mr->key));
	mpt_entry->pd	       = cpu_to_be32(mr->pd);
	mpt_entry->start       = cpu_to_be64(mr->iova);
	mpt_entry->length      = cpu_to_be64(mr->size);
	mpt_entry->entity_size = cpu_to_be32(mr->mtt.page_shift);
	if (mr->mtt.order < 0) {
		mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_PHYSICAL);
		mpt_entry->mtt_seg = 0;
	} else
		mpt_entry->mtt_seg = cpu_to_be64(mlx4_mtt_addr(dev, &mr->mtt));

	err = mlx4_SW2HW_MPT(dev, mailbox,
			     key_to_hw_index(mr->key) & (dev->caps.num_mpts - 1));
	if (err) {
		mlx4_warn(dev, "SW2HW_MPT failed (%d)\n", err);
		goto err_cmd;
	}

	mr->enabled = 1;

	mlx4_free_cmd_mailbox(dev, mailbox);

	return 0;

err_cmd:
	mlx4_free_cmd_mailbox(dev, mailbox);

err_table:
	mlx4_table_put(dev, &mr_table->dmpt_table, key_to_hw_index(mr->key));
	return err;
}
EXPORT_SYMBOL_GPL(mlx4_mr_enable);

static int mlx4_WRITE_MTT(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
			  int num_mtt)
{
	return mlx4_cmd(dev, mailbox->dma, num_mtt, 0, MLX4_CMD_WRITE_MTT,
			MLX4_CMD_TIME_CLASS_B);
}

int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
		   int start_index, int npages, u64 *page_list)
{
	struct mlx4_cmd_mailbox *mailbox;
	__be64 *mtt_entry;
	int i;
	int err = 0;

	if (mtt->order < 0)
		return -EINVAL;

	mailbox = mlx4_alloc_cmd_mailbox(dev);
	if (IS_ERR(mailbox))
		return PTR_ERR(mailbox);

	mtt_entry = mailbox->buf;

	while (npages > 0) {
		mtt_entry[0] = cpu_to_be64(mlx4_mtt_addr(dev, mtt) + start_index * 8);
		mtt_entry[1] = 0;

		for (i = 0; i < npages && i < MLX4_MAILBOX_SIZE / 8 - 2; ++i)
			mtt_entry[i + 2] = cpu_to_be64(page_list[i] |
						       MLX4_MTT_FLAG_PRESENT);

		/*
		 * If we have an odd number of entries to write, add
		 * one more dummy entry for firmware efficiency.
		 */
		if (i & 1)
			mtt_entry[i + 2] = 0;

		err = mlx4_WRITE_MTT(dev, mailbox, (i + 1) & ~1);
		if (err)
			goto out;

		npages      -= i;
		start_index += i;
		page_list   += i;
	}

out:
	mlx4_free_cmd_mailbox(dev, mailbox);

	return err;
}
EXPORT_SYMBOL_GPL(mlx4_write_mtt);

int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
		       struct mlx4_buf *buf)
{
	u64 *page_list;
	int err;
	int i;

	page_list = kmalloc(buf->npages * sizeof *page_list, GFP_KERNEL);
	if (!page_list)
		return -ENOMEM;

	for (i = 0; i < buf->npages; ++i)
		if (buf->nbufs == 1)
			page_list[i] = buf->u.direct.map + (i << buf->page_shift);
		else
			page_list[i] = buf->u.page_list[i].map;

	err = mlx4_write_mtt(dev, mtt, 0, buf->npages, page_list);

	kfree(page_list);
	return err;
}
EXPORT_SYMBOL_GPL(mlx4_buf_write_mtt);

int __devinit mlx4_init_mr_table(struct mlx4_dev *dev)
{
	struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
	int err;

	err = mlx4_bitmap_init(&mr_table->mpt_bitmap, dev->caps.num_mpts,
			       ~0, dev->caps.reserved_mrws);
	if (err)
		return err;

	err = mlx4_buddy_init(&mr_table->mtt_buddy,
			      ilog2(dev->caps.num_mtt_segs));
	if (err)
		goto err_buddy;

	if (dev->caps.reserved_mtts) {
		if (mlx4_alloc_mtt_range(dev, fls(dev->caps.reserved_mtts - 1)) == -1) {
			mlx4_warn(dev, "MTT table of order %d is too small.\n",
				  mr_table->mtt_buddy.max_order);
			err = -ENOMEM;
			goto err_reserve_mtts;
		}
	}

	return 0;

err_reserve_mtts:
	mlx4_buddy_cleanup(&mr_table->mtt_buddy);

err_buddy:
	mlx4_bitmap_cleanup(&mr_table->mpt_bitmap);

	return err;
}

void mlx4_cleanup_mr_table(struct mlx4_dev *dev)
{
	struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;

	mlx4_buddy_cleanup(&mr_table->mtt_buddy);
	mlx4_bitmap_cleanup(&mr_table->mpt_bitmap);
}
Commit	Line	Data
225c7b1f RD	1	/*
	2	* Copyright (c) 2004 Topspin Communications. All rights reserved.
	3	* Copyright (c) 2005 Mellanox Technologies. All rights reserved.
	4	* Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
	5	*
	6	* This software is available to you under a choice of one of two
	7	* licenses. You may choose to be licensed under the terms of the GNU
	8	* General Public License (GPL) Version 2, available from the file
	9	* COPYING in the main directory of this source tree, or the
	10	* OpenIB.org BSD license below:
	11	*
	12	* Redistribution and use in source and binary forms, with or
	13	* without modification, are permitted provided that the following
	14	* conditions are met:
	15	*
	16	* - Redistributions of source code must retain the above
	17	* copyright notice, this list of conditions and the following
	18	* disclaimer.
	19	*
	20	* - Redistributions in binary form must reproduce the above
	21	* copyright notice, this list of conditions and the following
	22	* disclaimer in the documentation and/or other materials
	23	* provided with the distribution.
	24	*
	25	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	26	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	27	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	28	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	29	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	30	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	31	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	32	* SOFTWARE.
	33	*/
	34
	35	#include <linux/init.h>
	36	#include <linux/errno.h>
	37
	38	#include <linux/mlx4/cmd.h>
	39
	40	#include "mlx4.h"
	41	#include "icm.h"
	42
	43	/*
	44	* Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
	45	*/
	46	struct mlx4_mpt_entry {
	47	__be32 flags;
	48	__be32 qpn;
	49	__be32 key;
	50	__be32 pd;
	51	__be64 start;
	52	__be64 length;
	53	__be32 lkey;
	54	__be32 win_cnt;
	55	u8 reserved1[3];
	56	u8 mtt_rep;
	57	__be64 mtt_seg;
	58	__be32 mtt_sz;
	59	__be32 entity_size;
	60	__be32 first_byte_offset;
	61	} __attribute__((packed));
	62
	63	#define MLX4_MPT_FLAG_SW_OWNS (0xfUL << 28)
	64	#define MLX4_MPT_FLAG_MIO (1 << 17)
65	#define MLX4_MPT_FLAG_BIND_ENABLE (1 << 15)
66	#define MLX4_MPT_FLAG_PHYSICAL (1 << 9)
67	#define MLX4_MPT_FLAG_REGION (1 << 8)
68
69	#define MLX4_MTT_FLAG_PRESENT 1
70
71	static u32 mlx4_buddy_alloc(struct mlx4_buddy *buddy, int order)
72	{
73	int o;
74	int m;
75	u32 seg;
76
77	spin_lock(&buddy->lock);
78
79	for (o = order; o <= buddy->max_order; ++o) {
80	m = 1 << (buddy->max_order - o);
81	seg = find_first_bit(buddy->bits[o], m);
82	if (seg < m)
83	goto found;
84	}
85
86	spin_unlock(&buddy->lock);
87	return -1;
88
89	found:
90	clear_bit(seg, buddy->bits[o]);
91
92	while (o > order) {
93	--o;
94	seg <<= 1;
95	set_bit(seg ^ 1, buddy->bits[o]);
96	}
97
98	spin_unlock(&buddy->lock);
99
100	seg <<= order;
101
102	return seg;
103	}
104
105	static void mlx4_buddy_free(struct mlx4_buddy *buddy, u32 seg, int order)
106	{
107	seg >>= order;
108
109	spin_lock(&buddy->lock);
110
111	while (test_bit(seg ^ 1, buddy->bits[order])) {
112	clear_bit(seg ^ 1, buddy->bits[order]);
113	seg >>= 1;
114	++order;
115	}
116
117	set_bit(seg, buddy->bits[order]);
118
119	spin_unlock(&buddy->lock);
120	}
121
122	static int __devinit mlx4_buddy_init(struct mlx4_buddy *buddy, int max_order)
123	{
124	int i, s;
125
126	buddy->max_order = max_order;
127	spin_lock_init(&buddy->lock);
128
129	buddy->bits = kzalloc((buddy->max_order + 1) * sizeof (long *),
130	GFP_KERNEL);
131	if (!buddy->bits)
132	goto err_out;
133
134	for (i = 0; i <= buddy->max_order; ++i) {
135	s = BITS_TO_LONGS(1 << (buddy->max_order - i));
136	buddy->bits[i] = kmalloc(s * sizeof (long), GFP_KERNEL);
137	if (!buddy->bits[i])
138	goto err_out_free;
139	bitmap_zero(buddy->bits[i], 1 << (buddy->max_order - i));
140	}
141
142	set_bit(0, buddy->bits[buddy->max_order]);
143
144	return 0;
145
146	err_out_free:
147	for (i = 0; i <= buddy->max_order; ++i)
148	kfree(buddy->bits[i]);
149
150	kfree(buddy->bits);
151
152	err_out:
153	return -ENOMEM;
154	}
155
156	static void mlx4_buddy_cleanup(struct mlx4_buddy *buddy)
157	{
158	int i;
159
160	for (i = 0; i <= buddy->max_order; ++i)
161	kfree(buddy->bits[i]);
162
163	kfree(buddy->bits);
164	}
165
166	static u32 mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order)
167	{
168	struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
169	u32 seg;
170
171	seg = mlx4_buddy_alloc(&mr_table->mtt_buddy, order);
172	if (seg == -1)
173	return -1;
174
175	if (mlx4_table_get_range(dev, &mr_table->mtt_table, seg,
176	seg + (1 << order) - 1)) {
177	mlx4_buddy_free(&mr_table->mtt_buddy, seg, order);
178	return -1;
179	}
180
181	return seg;
182	}
183
184	int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
185	struct mlx4_mtt *mtt)
186	{
187	int i;
188
189	if (!npages) {
190	mtt->order = -1;
191	mtt->page_shift = MLX4_ICM_PAGE_SHIFT;
192	return 0;
193	} else
194	mtt->page_shift = page_shift;
195
196	for (mtt->order = 0, i = MLX4_MTT_ENTRY_PER_SEG; i < npages; i <<= 1)
197	++mtt->order;
198
199	mtt->first_seg = mlx4_alloc_mtt_range(dev, mtt->order);
200	if (mtt->first_seg == -1)
201	return -ENOMEM;
202
203	return 0;
204	}
205	EXPORT_SYMBOL_GPL(mlx4_mtt_init);
206
207	void mlx4_mtt_cleanup(struct mlx4_dev dev, struct mlx4_mtt mtt)
208	{
209	struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
210
211	if (mtt->order < 0)
212	return;
213
214	mlx4_buddy_free(&mr_table->mtt_buddy, mtt->first_seg, mtt->order);
215	mlx4_table_put_range(dev, &mr_table->mtt_table, mtt->first_seg,
216	mtt->first_seg + (1 << mtt->order) - 1);
217	}
218	EXPORT_SYMBOL_GPL(mlx4_mtt_cleanup);
219
220	u64 mlx4_mtt_addr(struct mlx4_dev dev, struct mlx4_mtt mtt)
221	{
222	return (u64) mtt->first_seg * dev->caps.mtt_entry_sz;
223	}
224	EXPORT_SYMBOL_GPL(mlx4_mtt_addr);
225
226	static u32 hw_index_to_key(u32 ind)
227	{
228	return (ind >> 24) \| (ind << 8);
229	}
230
231	static u32 key_to_hw_index(u32 key)
232	{
233	return (key << 24) \| (key >> 8);
234	}
235
236	static int mlx4_SW2HW_MPT(struct mlx4_dev dev, struct mlx4_cmd_mailbox mailbox,
237	int mpt_index)
238	{
239	return mlx4_cmd(dev, mailbox->dma, mpt_index, 0, MLX4_CMD_SW2HW_MPT,
240	MLX4_CMD_TIME_CLASS_B);
241	}
242
243	static int mlx4_HW2SW_MPT(struct mlx4_dev dev, struct mlx4_cmd_mailbox mailbox,
244	int mpt_index)
245	{
246	return mlx4_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, mpt_index,
247	!mailbox, MLX4_CMD_HW2SW_MPT, MLX4_CMD_TIME_CLASS_B);
248	}
249
250	int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
251	int npages, int page_shift, struct mlx4_mr *mr)
252	{
253	struct mlx4_priv *priv = mlx4_priv(dev);
254	u32 index;
255	int err;
256
257	index = mlx4_bitmap_alloc(&priv->mr_table.mpt_bitmap);
0172e2e1 JM	258	if (index == -1)
0172e2e1 JM	259	return -ENOMEM;
225c7b1f RD	260
	261	mr->iova = iova;
	262	mr->size = size;
	263	mr->pd = pd;
	264	mr->access = access;
	265	mr->enabled = 0;
	266	mr->key = hw_index_to_key(index);
	267
	268	err = mlx4_mtt_init(dev, npages, page_shift, &mr->mtt);
	269	if (err)
0172e2e1	270	mlx4_bitmap_free(&priv->mr_table.mpt_bitmap, index);
225c7b1f	271
225c7b1f RD	272	return err;
	273	}
	274	EXPORT_SYMBOL_GPL(mlx4_mr_alloc);
	275
	276	void mlx4_mr_free(struct mlx4_dev dev, struct mlx4_mr mr)
	277	{
	278	struct mlx4_priv *priv = mlx4_priv(dev);
	279	int err;
	280
	281	if (mr->enabled) {
	282	err = mlx4_HW2SW_MPT(dev, NULL,
	283	key_to_hw_index(mr->key) &
	284	(dev->caps.num_mpts - 1));
	285	if (err)
	286	mlx4_warn(dev, "HW2SW_MPT failed (%d)\n", err);
	287	}
	288
	289	mlx4_mtt_cleanup(dev, &mr->mtt);
	290	mlx4_bitmap_free(&priv->mr_table.mpt_bitmap, key_to_hw_index(mr->key));
	291	}
	292	EXPORT_SYMBOL_GPL(mlx4_mr_free);
	293
	294	int mlx4_mr_enable(struct mlx4_dev dev, struct mlx4_mr mr)
	295	{
	296	struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
	297	struct mlx4_cmd_mailbox *mailbox;
	298	struct mlx4_mpt_entry *mpt_entry;
	299	int err;
	300
	301	err = mlx4_table_get(dev, &mr_table->dmpt_table, key_to_hw_index(mr->key));
	302	if (err)
	303	return err;
	304
	305	mailbox = mlx4_alloc_cmd_mailbox(dev);
	306	if (IS_ERR(mailbox)) {
	307	err = PTR_ERR(mailbox);
	308	goto err_table;
	309	}
	310	mpt_entry = mailbox->buf;
	311
	312	memset(mpt_entry, 0, sizeof *mpt_entry);
	313
	314	mpt_entry->flags = cpu_to_be32(MLX4_MPT_FLAG_SW_OWNS \|
	315	MLX4_MPT_FLAG_MIO \|
	316	MLX4_MPT_FLAG_REGION \|
	317	mr->access);
225c7b1f RD	318
	319	mpt_entry->key = cpu_to_be32(key_to_hw_index(mr->key));
	320	mpt_entry->pd = cpu_to_be32(mr->pd);
	321	mpt_entry->start = cpu_to_be64(mr->iova);
	322	mpt_entry->length = cpu_to_be64(mr->size);
	323	mpt_entry->entity_size = cpu_to_be32(mr->mtt.page_shift);
b2d9308a JM	324	if (mr->mtt.order < 0) {
	325	mpt_entry->flags \|= cpu_to_be32(MLX4_MPT_FLAG_PHYSICAL);
	326	mpt_entry->mtt_seg = 0;
	327	} else
	328	mpt_entry->mtt_seg = cpu_to_be64(mlx4_mtt_addr(dev, &mr->mtt));
225c7b1f RD	329
	330	err = mlx4_SW2HW_MPT(dev, mailbox,
	331	key_to_hw_index(mr->key) & (dev->caps.num_mpts - 1));
	332	if (err) {
	333	mlx4_warn(dev, "SW2HW_MPT failed (%d)\n", err);
	334	goto err_cmd;
	335	}
	336
	337	mr->enabled = 1;
	338
	339	mlx4_free_cmd_mailbox(dev, mailbox);
	340
	341	return 0;
	342
	343	err_cmd:
	344	mlx4_free_cmd_mailbox(dev, mailbox);
	345
	346	err_table:
	347	mlx4_table_put(dev, &mr_table->dmpt_table, key_to_hw_index(mr->key));
	348	return err;
	349	}
	350	EXPORT_SYMBOL_GPL(mlx4_mr_enable);
	351
	352	static int mlx4_WRITE_MTT(struct mlx4_dev dev, struct mlx4_cmd_mailbox mailbox,
	353	int num_mtt)
	354	{
	355	return mlx4_cmd(dev, mailbox->dma, num_mtt, 0, MLX4_CMD_WRITE_MTT,
	356	MLX4_CMD_TIME_CLASS_B);
	357	}
	358
	359	int mlx4_write_mtt(struct mlx4_dev dev, struct mlx4_mtt mtt,
	360	int start_index, int npages, u64 *page_list)
	361	{
	362	struct mlx4_cmd_mailbox *mailbox;
	363	__be64 *mtt_entry;
	364	int i;
	365	int err = 0;
	366
	367	if (mtt->order < 0)
	368	return -EINVAL;
	369
	370	mailbox = mlx4_alloc_cmd_mailbox(dev);
	371	if (IS_ERR(mailbox))
	372	return PTR_ERR(mailbox);
	373
	374	mtt_entry = mailbox->buf;
	375
	376	while (npages > 0) {
	377	mtt_entry[0] = cpu_to_be64(mlx4_mtt_addr(dev, mtt) + start_index * 8);
	378	mtt_entry[1] = 0;
	379
	380	for (i = 0; i < npages && i < MLX4_MAILBOX_SIZE / 8 - 2; ++i)
	381	mtt_entry[i + 2] = cpu_to_be64(page_list[i] \|
	382	MLX4_MTT_FLAG_PRESENT);
	383
	384	/*
	385	* If we have an odd number of entries to write, add
	386	* one more dummy entry for firmware efficiency.
	387	*/
	388	if (i & 1)
	389	mtt_entry[i + 2] = 0;
	390
	391	err = mlx4_WRITE_MTT(dev, mailbox, (i + 1) & ~1);
	392	if (err)
393	goto out;
394
395	npages -= i;
396	start_index += i;
397	page_list += i;
398	}
399
400	out:
401	mlx4_free_cmd_mailbox(dev, mailbox);
402
403	return err;
404	}
405	EXPORT_SYMBOL_GPL(mlx4_write_mtt);
406
407	int mlx4_buf_write_mtt(struct mlx4_dev dev, struct mlx4_mtt mtt,
408	struct mlx4_buf *buf)
409	{
410	u64 *page_list;
411	int err;
412	int i;
413
414	page_list = kmalloc(buf->npages * sizeof *page_list, GFP_KERNEL);
415	if (!page_list)
416	return -ENOMEM;
417
418	for (i = 0; i < buf->npages; ++i)
419	if (buf->nbufs == 1)
420	page_list[i] = buf->u.direct.map + (i << buf->page_shift);
421	else
422	page_list[i] = buf->u.page_list[i].map;
423
424	err = mlx4_write_mtt(dev, mtt, 0, buf->npages, page_list);
425
426	kfree(page_list);
427	return err;
428	}
429	EXPORT_SYMBOL_GPL(mlx4_buf_write_mtt);
430
431	int __devinit mlx4_init_mr_table(struct mlx4_dev *dev)
432	{
433	struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
434	int err;
435
436	err = mlx4_bitmap_init(&mr_table->mpt_bitmap, dev->caps.num_mpts,
437	~0, dev->caps.reserved_mrws);
438	if (err)
439	return err;
440
441	err = mlx4_buddy_init(&mr_table->mtt_buddy,
442	ilog2(dev->caps.num_mtt_segs));
443	if (err)
444	goto err_buddy;
445
446	if (dev->caps.reserved_mtts) {
cf78237d	447	if (mlx4_alloc_mtt_range(dev, fls(dev->caps.reserved_mtts - 1)) == -1) {
225c7b1f RD	448	mlx4_warn(dev, "MTT table of order %d is too small.\n",
	449	mr_table->mtt_buddy.max_order);
	450	err = -ENOMEM;
	451	goto err_reserve_mtts;
	452	}
	453	}
	454
	455	return 0;
	456
	457	err_reserve_mtts:
	458	mlx4_buddy_cleanup(&mr_table->mtt_buddy);
	459
	460	err_buddy:
	461	mlx4_bitmap_cleanup(&mr_table->mpt_bitmap);
	462
	463	return err;
	464	}
	465
	466	void mlx4_cleanup_mr_table(struct mlx4_dev *dev)
	467	{
	468	struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
	469
	470	mlx4_buddy_cleanup(&mr_table->mtt_buddy);
	471	mlx4_bitmap_cleanup(&mr_table->mpt_bitmap);
	472	}