[linux-block.git] / drivers / net / mlx4 / mlx4.h

/*
 * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
 * Copyright (c) 2005, 2006, 2007 Cisco Systems.  All rights reserved.
 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#ifndef MLX4_H
#define MLX4_H

#include <linux/radix-tree.h>

#include <linux/mlx4/device.h>
#include <linux/mlx4/doorbell.h>

#define DRV_NAME	"mlx4_core"
#define PFX		DRV_NAME ": "
#define DRV_VERSION	"0.01"
#define DRV_RELDATE	"May 1, 2007"

enum {
	MLX4_HCR_BASE		= 0x80680,
	MLX4_HCR_SIZE		= 0x0001c,
	MLX4_CLR_INT_SIZE	= 0x00008
};

enum {
	MLX4_BOARD_ID_LEN	= 64
};

enum {
	MLX4_MGM_ENTRY_SIZE	=  0x40,
	MLX4_QP_PER_MGM		= 4 * (MLX4_MGM_ENTRY_SIZE / 16 - 2),
	MLX4_MTT_ENTRY_PER_SEG	= 8
};

enum {
	MLX4_EQ_ASYNC,
	MLX4_EQ_COMP,
	MLX4_EQ_CATAS,
	MLX4_NUM_EQ
};

enum {
	MLX4_NUM_PDS		= 1 << 15
};

enum {
	MLX4_CMPT_TYPE_QP	= 0,
	MLX4_CMPT_TYPE_SRQ	= 1,
	MLX4_CMPT_TYPE_CQ	= 2,
	MLX4_CMPT_TYPE_EQ	= 3,
	MLX4_CMPT_NUM_TYPE
};

enum {
	MLX4_CMPT_SHIFT		= 24,
	MLX4_NUM_CMPTS		= MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
};

#ifdef CONFIG_MLX4_DEBUG
extern int mlx4_debug_level;

#define mlx4_dbg(mdev, format, arg...)					\
	do {								\
		if (mlx4_debug_level)					\
			dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ## arg); \
	} while (0)

#else /* CONFIG_MLX4_DEBUG */

#define mlx4_dbg(mdev, format, arg...) do { (void) mdev; } while (0)

#endif /* CONFIG_MLX4_DEBUG */

#define mlx4_err(mdev, format, arg...) \
	dev_err(&mdev->pdev->dev, format, ## arg)
#define mlx4_info(mdev, format, arg...) \
	dev_info(&mdev->pdev->dev, format, ## arg)
#define mlx4_warn(mdev, format, arg...) \
	dev_warn(&mdev->pdev->dev, format, ## arg)

struct mlx4_bitmap {
	u32			last;
	u32			top;
	u32			max;
	u32			mask;
	spinlock_t		lock;
	unsigned long	       *table;
};

struct mlx4_buddy {
	unsigned long	      **bits;
	int			max_order;
	spinlock_t		lock;
};

struct mlx4_icm;

struct mlx4_icm_table {
	u64			virt;
	int			num_icm;
	int			num_obj;
	int			obj_size;
	int			lowmem;
	struct mutex		mutex;
	struct mlx4_icm	      **icm;
};

struct mlx4_eq {
	struct mlx4_dev	       *dev;
	void __iomem	       *doorbell;
	int			eqn;
	u32			cons_index;
	u16			irq;
	u16			have_irq;
	int			nent;
	struct mlx4_buf_list   *page_list;
	struct mlx4_mtt		mtt;
};

struct mlx4_profile {
	int			num_qp;
	int			rdmarc_per_qp;
	int			num_srq;
	int			num_cq;
	int			num_mcg;
	int			num_mpt;
	int			num_mtt;
};

struct mlx4_fw {
	u64			clr_int_base;
	u64			catas_offset;
	struct mlx4_icm	       *fw_icm;
	struct mlx4_icm	       *aux_icm;
	u32			catas_size;
	u16			fw_pages;
	u8			clr_int_bar;
	u8			catas_bar;
};

struct mlx4_cmd {
	struct pci_pool	       *pool;
	void __iomem	       *hcr;
	struct mutex		hcr_mutex;
	struct semaphore	poll_sem;
	struct semaphore	event_sem;
	int			max_cmds;
	spinlock_t		context_lock;
	int			free_head;
	struct mlx4_cmd_context *context;
	u16			token_mask;
	u8			use_events;
	u8			toggle;
};

struct mlx4_uar_table {
	struct mlx4_bitmap	bitmap;
};

struct mlx4_mr_table {
	struct mlx4_bitmap	mpt_bitmap;
	struct mlx4_buddy	mtt_buddy;
	u64			mtt_base;
	u64			mpt_base;
	struct mlx4_icm_table	mtt_table;
	struct mlx4_icm_table	dmpt_table;
};

struct mlx4_cq_table {
	struct mlx4_bitmap	bitmap;
	spinlock_t		lock;
	struct radix_tree_root	tree;
	struct mlx4_icm_table	table;
	struct mlx4_icm_table	cmpt_table;
};

struct mlx4_eq_table {
	struct mlx4_bitmap	bitmap;
	void __iomem	       *clr_int;
	void __iomem	       *uar_map[(MLX4_NUM_EQ + 6) / 4];
	u32			clr_mask;
	struct mlx4_eq		eq[MLX4_NUM_EQ];
	u64			icm_virt;
	struct page	       *icm_page;
	dma_addr_t		icm_dma;
	struct mlx4_icm_table	cmpt_table;
	int			have_irq;
	u8			inta_pin;
};

struct mlx4_srq_table {
	struct mlx4_bitmap	bitmap;
	spinlock_t		lock;
	struct radix_tree_root	tree;
	struct mlx4_icm_table	table;
	struct mlx4_icm_table	cmpt_table;
};

struct mlx4_qp_table {
	struct mlx4_bitmap	bitmap;
	u32			rdmarc_base;
	int			rdmarc_shift;
	spinlock_t		lock;
	struct mlx4_icm_table	qp_table;
	struct mlx4_icm_table	auxc_table;
	struct mlx4_icm_table	altc_table;
	struct mlx4_icm_table	rdmarc_table;
	struct mlx4_icm_table	cmpt_table;
};

struct mlx4_mcg_table {
	struct mutex		mutex;
	struct mlx4_bitmap	bitmap;
	struct mlx4_icm_table	table;
};

struct mlx4_catas_err {
	u32 __iomem	       *map;
	int			size;
};

struct mlx4_priv {
	struct mlx4_dev		dev;

	struct list_head	dev_list;
	struct list_head	ctx_list;
	spinlock_t		ctx_lock;

	struct mlx4_fw		fw;
	struct mlx4_cmd		cmd;

	struct mlx4_bitmap	pd_bitmap;
	struct mlx4_uar_table	uar_table;
	struct mlx4_mr_table	mr_table;
	struct mlx4_cq_table	cq_table;
	struct mlx4_eq_table	eq_table;
	struct mlx4_srq_table	srq_table;
	struct mlx4_qp_table	qp_table;
	struct mlx4_mcg_table	mcg_table;

	struct mlx4_catas_err	catas_err;

	void __iomem	       *clr_base;

	struct mlx4_uar		driver_uar;
	void __iomem	       *kar;

	u32			rev_id;
	char			board_id[MLX4_BOARD_ID_LEN];
};

static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
{
	return container_of(dev, struct mlx4_priv, dev);
}

u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj);
int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask, u32 reserved);
void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);

int mlx4_reset(struct mlx4_dev *dev);

int mlx4_init_pd_table(struct mlx4_dev *dev);
int mlx4_init_uar_table(struct mlx4_dev *dev);
int mlx4_init_mr_table(struct mlx4_dev *dev);
int mlx4_init_eq_table(struct mlx4_dev *dev);
int mlx4_init_cq_table(struct mlx4_dev *dev);
int mlx4_init_qp_table(struct mlx4_dev *dev);
int mlx4_init_srq_table(struct mlx4_dev *dev);
int mlx4_init_mcg_table(struct mlx4_dev *dev);

void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);

void mlx4_map_catas_buf(struct mlx4_dev *dev);
void mlx4_unmap_catas_buf(struct mlx4_dev *dev);

int mlx4_register_device(struct mlx4_dev *dev);
void mlx4_unregister_device(struct mlx4_dev *dev);
void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_event type,
			 int subtype, int port);

struct mlx4_dev_cap;
struct mlx4_init_hca_param;

u64 mlx4_make_profile(struct mlx4_dev *dev,
		      struct mlx4_profile *request,
		      struct mlx4_dev_cap *dev_cap,
		      struct mlx4_init_hca_param *init_hca);

int mlx4_map_eq_icm(struct mlx4_dev *dev, u64 icm_virt);
void mlx4_unmap_eq_icm(struct mlx4_dev *dev);

int mlx4_cmd_init(struct mlx4_dev *dev);
void mlx4_cmd_cleanup(struct mlx4_dev *dev);
void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
int mlx4_cmd_use_events(struct mlx4_dev *dev);
void mlx4_cmd_use_polling(struct mlx4_dev *dev);

void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);

void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);

void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);

void mlx4_handle_catas_err(struct mlx4_dev *dev);

#endif /* MLX4_H */
Commit	Line	Data
225c7b1f RD	1	/*
	2	* Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
	3	* Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
	4	* Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved.
	5	* Copyright (c) 2005 Mellanox Technologies. All rights reserved.
	6	* Copyright (c) 2004 Voltaire, Inc. All rights reserved.
	7	*
	8	* This software is available to you under a choice of one of two
	9	* licenses. You may choose to be licensed under the terms of the GNU
	10	* General Public License (GPL) Version 2, available from the file
	11	* COPYING in the main directory of this source tree, or the
	12	* OpenIB.org BSD license below:
	13	*
	14	* Redistribution and use in source and binary forms, with or
	15	* without modification, are permitted provided that the following
	16	* conditions are met:
	17	*
	18	* - Redistributions of source code must retain the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer.
	21	*
	22	* - Redistributions in binary form must reproduce the above
	23	* copyright notice, this list of conditions and the following
	24	* disclaimer in the documentation and/or other materials
	25	* provided with the distribution.
	26	*
	27	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	28	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	29	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	30	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	31	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	32	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	33	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	34	* SOFTWARE.
	35	*/
	36
	37	#ifndef MLX4_H
	38	#define MLX4_H
	39
	40	#include <linux/radix-tree.h>
	41
	42	#include <linux/mlx4/device.h>
	43	#include <linux/mlx4/doorbell.h>
	44
	45	#define DRV_NAME "mlx4_core"
	46	#define PFX DRV_NAME ": "
	47	#define DRV_VERSION "0.01"
	48	#define DRV_RELDATE "May 1, 2007"
	49
	50	enum {
	51	MLX4_HCR_BASE = 0x80680,
	52	MLX4_HCR_SIZE = 0x0001c,
	53	MLX4_CLR_INT_SIZE = 0x00008
	54	};
	55
	56	enum {
	57	MLX4_BOARD_ID_LEN = 64
	58	};
	59
	60	enum {
	61	MLX4_MGM_ENTRY_SIZE = 0x40,
	62	MLX4_QP_PER_MGM = 4 * (MLX4_MGM_ENTRY_SIZE / 16 - 2),
	63	MLX4_MTT_ENTRY_PER_SEG = 8
	64	};
65
66	enum {
67	MLX4_EQ_ASYNC,
68	MLX4_EQ_COMP,
69	MLX4_EQ_CATAS,
70	MLX4_NUM_EQ
71	};
72
73	enum {
74	MLX4_NUM_PDS = 1 << 15
75	};
76
77	enum {
78	MLX4_CMPT_TYPE_QP = 0,
79	MLX4_CMPT_TYPE_SRQ = 1,
80	MLX4_CMPT_TYPE_CQ = 2,
81	MLX4_CMPT_TYPE_EQ = 3,
82	MLX4_CMPT_NUM_TYPE
83	};
84
85	enum {
86	MLX4_CMPT_SHIFT = 24,
87	MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
88	};
89
90	#ifdef CONFIG_MLX4_DEBUG
91	extern int mlx4_debug_level;
92
93	#define mlx4_dbg(mdev, format, arg...) \
94	do { \
95	if (mlx4_debug_level) \
96	dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ## arg); \
97	} while (0)
98
99	#else /* CONFIG_MLX4_DEBUG */
100
101	#define mlx4_dbg(mdev, format, arg...) do { (void) mdev; } while (0)
102
103	#endif /* CONFIG_MLX4_DEBUG */
104
105	#define mlx4_err(mdev, format, arg...) \
106	dev_err(&mdev->pdev->dev, format, ## arg)
107	#define mlx4_info(mdev, format, arg...) \
108	dev_info(&mdev->pdev->dev, format, ## arg)
109	#define mlx4_warn(mdev, format, arg...) \
110	dev_warn(&mdev->pdev->dev, format, ## arg)
111
112	struct mlx4_bitmap {
113	u32 last;
114	u32 top;
115	u32 max;
116	u32 mask;
117	spinlock_t lock;
118	unsigned long *table;
119	};
120
121	struct mlx4_buddy {
122	unsigned long **bits;
123	int max_order;
124	spinlock_t lock;
125	};
126
127	struct mlx4_icm;
128
129	struct mlx4_icm_table {
130	u64 virt;
131	int num_icm;
132	int num_obj;
133	int obj_size;
134	int lowmem;
135	struct mutex mutex;
136	struct mlx4_icm **icm;
137	};
138
139	struct mlx4_eq {
140	struct mlx4_dev *dev;
141	void __iomem *doorbell;
142	int eqn;
143	u32 cons_index;
144	u16 irq;
145	u16 have_irq;
146	int nent;
147	struct mlx4_buf_list *page_list;
148	struct mlx4_mtt mtt;
149	};
150
151	struct mlx4_profile {
152	int num_qp;
153	int rdmarc_per_qp;
154	int num_srq;
155	int num_cq;
156	int num_mcg;
157	int num_mpt;
158	int num_mtt;
159	};
160
161	struct mlx4_fw {
162	u64 clr_int_base;
163	u64 catas_offset;
164	struct mlx4_icm *fw_icm;
165	struct mlx4_icm *aux_icm;
166	u32 catas_size;
167	u16 fw_pages;
168	u8 clr_int_bar;
169	u8 catas_bar;
170	};
171
172	struct mlx4_cmd {
173	struct pci_pool *pool;
174	void __iomem *hcr;
175	struct mutex hcr_mutex;
176	struct semaphore poll_sem;
177	struct semaphore event_sem;
178	int max_cmds;
179	spinlock_t context_lock;
180	int free_head;
181	struct mlx4_cmd_context *context;
182	u16 token_mask;
183	u8 use_events;
184	u8 toggle;
185	};
186
187	struct mlx4_uar_table {
188	struct mlx4_bitmap bitmap;
189	};
190
191	struct mlx4_mr_table {
192	struct mlx4_bitmap mpt_bitmap;
193	struct mlx4_buddy mtt_buddy;
194	u64 mtt_base;
195	u64 mpt_base;
196	struct mlx4_icm_table mtt_table;
197	struct mlx4_icm_table dmpt_table;
198	};
199
200	struct mlx4_cq_table {
201	struct mlx4_bitmap bitmap;
202	spinlock_t lock;
203	struct radix_tree_root tree;
204	struct mlx4_icm_table table;
205	struct mlx4_icm_table cmpt_table;
206	};
207
208	struct mlx4_eq_table {
209	struct mlx4_bitmap bitmap;
210	void __iomem *clr_int;
211	void __iomem *uar_map[(MLX4_NUM_EQ + 6) / 4];
212	u32 clr_mask;
213	struct mlx4_eq eq[MLX4_NUM_EQ];
214	u64 icm_virt;
215	struct page *icm_page;
216	dma_addr_t icm_dma;
217	struct mlx4_icm_table cmpt_table;
218	int have_irq;
219	u8 inta_pin;
220	};
221
222	struct mlx4_srq_table {
223	struct mlx4_bitmap bitmap;
224	spinlock_t lock;
225	struct radix_tree_root tree;
226	struct mlx4_icm_table table;
227	struct mlx4_icm_table cmpt_table;
228	};
229
230	struct mlx4_qp_table {
231	struct mlx4_bitmap bitmap;
232	u32 rdmarc_base;
233	int rdmarc_shift;
234	spinlock_t lock;
235	struct mlx4_icm_table qp_table;
236	struct mlx4_icm_table auxc_table;
237	struct mlx4_icm_table altc_table;
238	struct mlx4_icm_table rdmarc_table;
239	struct mlx4_icm_table cmpt_table;
240	};
241
242	struct mlx4_mcg_table {
243	struct mutex mutex;
244	struct mlx4_bitmap bitmap;
245	struct mlx4_icm_table table;
246	};
247
248	struct mlx4_catas_err {
249	u32 __iomem *map;
250	int size;
251	};
252
253	struct mlx4_priv {
254	struct mlx4_dev dev;
255
256	struct list_head dev_list;
257	struct list_head ctx_list;
258	spinlock_t ctx_lock;
259
260	struct mlx4_fw fw;
261	struct mlx4_cmd cmd;
262
263	struct mlx4_bitmap pd_bitmap;
264	struct mlx4_uar_table uar_table;
265	struct mlx4_mr_table mr_table;
266	struct mlx4_cq_table cq_table;
267	struct mlx4_eq_table eq_table;
268	struct mlx4_srq_table srq_table;
269	struct mlx4_qp_table qp_table;
270	struct mlx4_mcg_table mcg_table;
271
272	struct mlx4_catas_err catas_err;
273
274	void __iomem *clr_base;
275
276	struct mlx4_uar driver_uar;
277	void __iomem *kar;
225c7b1f RD	278
	279	u32 rev_id;
	280	char board_id[MLX4_BOARD_ID_LEN];
	281	};
	282
	283	static inline struct mlx4_priv mlx4_priv(struct mlx4_dev dev)
	284	{
	285	return container_of(dev, struct mlx4_priv, dev);
	286	}
	287
	288	u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
	289	void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj);
	290	int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask, u32 reserved);
	291	void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
	292
	293	int mlx4_reset(struct mlx4_dev *dev);
	294
	295	int mlx4_init_pd_table(struct mlx4_dev *dev);
	296	int mlx4_init_uar_table(struct mlx4_dev *dev);
	297	int mlx4_init_mr_table(struct mlx4_dev *dev);
	298	int mlx4_init_eq_table(struct mlx4_dev *dev);
	299	int mlx4_init_cq_table(struct mlx4_dev *dev);
	300	int mlx4_init_qp_table(struct mlx4_dev *dev);
	301	int mlx4_init_srq_table(struct mlx4_dev *dev);
	302	int mlx4_init_mcg_table(struct mlx4_dev *dev);
	303
	304	void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
	305	void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
	306	void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
	307	void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
	308	void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
	309	void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
	310	void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
	311	void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
	312
	313	void mlx4_map_catas_buf(struct mlx4_dev *dev);
	314	void mlx4_unmap_catas_buf(struct mlx4_dev *dev);
	315
	316	int mlx4_register_device(struct mlx4_dev *dev);
	317	void mlx4_unregister_device(struct mlx4_dev *dev);
	318	void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_event type,
	319	int subtype, int port);
	320
	321	struct mlx4_dev_cap;
	322	struct mlx4_init_hca_param;
	323
	324	u64 mlx4_make_profile(struct mlx4_dev *dev,
	325	struct mlx4_profile *request,
	326	struct mlx4_dev_cap *dev_cap,
	327	struct mlx4_init_hca_param *init_hca);
	328
	329	int mlx4_map_eq_icm(struct mlx4_dev *dev, u64 icm_virt);
	330	void mlx4_unmap_eq_icm(struct mlx4_dev *dev);
	331
	332	int mlx4_cmd_init(struct mlx4_dev *dev);
	333	void mlx4_cmd_cleanup(struct mlx4_dev *dev);
	334	void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
	335	int mlx4_cmd_use_events(struct mlx4_dev *dev);
	336	void mlx4_cmd_use_polling(struct mlx4_dev *dev);
	337
	338	void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
	339	void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
	340
	341	void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
342
343	void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
344
345	void mlx4_handle_catas_err(struct mlx4_dev *dev);
346
347	#endif /* MLX4_H */