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Linux 2.6.31-rc9
[linux-2.6-block.git] / drivers / net / mlx4 / main.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
51a379d0 4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 */
35
36#include <linux/module.h>
37#include <linux/init.h>
38#include <linux/errno.h>
39#include <linux/pci.h>
40#include <linux/dma-mapping.h>
41
42#include <linux/mlx4/device.h>
43#include <linux/mlx4/doorbell.h>
44
45#include "mlx4.h"
46#include "fw.h"
47#include "icm.h"
48
49MODULE_AUTHOR("Roland Dreier");
50MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
51MODULE_LICENSE("Dual BSD/GPL");
52MODULE_VERSION(DRV_VERSION);
53
27bf91d6
YP		 54struct workqueue_struct *mlx4_wq;
55
225c7b1f
RD		 56#ifdef CONFIG_MLX4_DEBUG
57
58int mlx4_debug_level = 0;
59module_param_named(debug_level, mlx4_debug_level, int, 0644);
60MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
61
62#endif /* CONFIG_MLX4_DEBUG */
63
64#ifdef CONFIG_PCI_MSI
65
08fb1055 66static int msi_x = 1;
225c7b1f
RD		 67module_param(msi_x, int, 0444);
68MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
69
70#else /* CONFIG_PCI_MSI */
71
72#define msi_x (0)
73
74#endif /* CONFIG_PCI_MSI */
75
f33afc26 76static char mlx4_version[] __devinitdata =
225c7b1f
RD		 77 DRV_NAME ": Mellanox ConnectX core driver v"
78 DRV_VERSION " (" DRV_RELDATE ")\n";
79
80static struct mlx4_profile default_profile = {
9b1f3851 81 .num_qp = 1 << 17,
225c7b1f 82 .num_srq = 1 << 16,
c9f2ba5e 83 .rdmarc_per_qp = 1 << 4,
225c7b1f
RD		 84 .num_cq = 1 << 16,
85 .num_mcg = 1 << 13,
86 .num_mpt = 1 << 17,
87 .num_mtt = 1 << 20,
88};
89
93fc9e1b
YP		 90static int log_num_mac = 2;
91module_param_named(log_num_mac, log_num_mac, int, 0444);
92MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
93
94static int log_num_vlan;
95module_param_named(log_num_vlan, log_num_vlan, int, 0444);
96MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
97
98static int use_prio;
99module_param_named(use_prio, use_prio, bool, 0444);
100MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports "
101 "(0/1, default 0)");
102
ab6bf42e
EC		 103static int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
104module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
105MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-5)");
106
27bf91d6
YP		 107int mlx4_check_port_params(struct mlx4_dev *dev,
108 enum mlx4_port_type *port_type)
7ff93f8b
YP		 109{
110 int i;
111
112 for (i = 0; i < dev->caps.num_ports - 1; i++) {
27bf91d6
YP		 113 if (port_type[i] != port_type[i + 1]) {
114 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
115 mlx4_err(dev, "Only same port types supported "
116 "on this HCA, aborting.\n");
117 return -EINVAL;
118 }
119 if (port_type[i] == MLX4_PORT_TYPE_ETH &&
120 port_type[i + 1] == MLX4_PORT_TYPE_IB)
121 return -EINVAL;
7ff93f8b
YP		 122 }
123 }
7ff93f8b
YP		 124
125 for (i = 0; i < dev->caps.num_ports; i++) {
126 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
127 mlx4_err(dev, "Requested port type for port %d is not "
128 "supported on this HCA\n", i + 1);
129 return -EINVAL;
130 }
131 }
132 return 0;
133}
134
135static void mlx4_set_port_mask(struct mlx4_dev *dev)
136{
137 int i;
138
139 dev->caps.port_mask = 0;
140 for (i = 1; i <= dev->caps.num_ports; ++i)
141 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_IB)
142 dev->caps.port_mask |= 1 << (i - 1);
143}
3d73c288 144static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
225c7b1f
RD		 145{
146 int err;
5ae2a7a8 147 int i;
225c7b1f
RD		 148
149 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
150 if (err) {
151 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
152 return err;
153 }
154
155 if (dev_cap->min_page_sz > PAGE_SIZE) {
156 mlx4_err(dev, "HCA minimum page size of %d bigger than "
157 "kernel PAGE_SIZE of %ld, aborting.\n",
158 dev_cap->min_page_sz, PAGE_SIZE);
159 return -ENODEV;
160 }
161 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
162 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
163 "aborting.\n",
164 dev_cap->num_ports, MLX4_MAX_PORTS);
165 return -ENODEV;
166 }
167
168 if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) {
169 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than "
170 "PCI resource 2 size of 0x%llx, aborting.\n",
171 dev_cap->uar_size,
172 (unsigned long long) pci_resource_len(dev->pdev, 2));
173 return -ENODEV;
174 }
175
176 dev->caps.num_ports = dev_cap->num_ports;
5ae2a7a8
RD		 177 for (i = 1; i <= dev->caps.num_ports; ++i) {
178 dev->caps.vl_cap[i] = dev_cap->max_vl[i];
b79acb49 179 dev->caps.ib_mtu_cap[i] = dev_cap->ib_mtu[i];
5ae2a7a8
RD		 180 dev->caps.gid_table_len[i] = dev_cap->max_gids[i];
181 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
182 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i];
b79acb49
YP		 183 dev->caps.eth_mtu_cap[i] = dev_cap->eth_mtu[i];
184 dev->caps.def_mac[i] = dev_cap->def_mac[i];
7ff93f8b 185 dev->caps.supported_type[i] = dev_cap->supported_port_types[i];
5ae2a7a8
RD		 186 }
187
225c7b1f 188 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
225c7b1f
RD		 189 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
190 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
191 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
192 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
193 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
194 dev->caps.max_wqes = dev_cap->max_qp_sz;
195 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
225c7b1f
RD		 196 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
197 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
198 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
199 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
200 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
201 dev->caps.num_qp_per_mgm = MLX4_QP_PER_MGM;
202 /*
203 * Subtract 1 from the limit because we need to allocate a
204 * spare CQE so the HCA HW can tell the difference between an
205 * empty CQ and a full CQ.
206 */
207 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
208 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
209 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
ab6bf42e 210 dev->caps.mtts_per_seg = 1 << log_mtts_per_seg;
121964ec 211 dev->caps.reserved_mtts = DIV_ROUND_UP(dev_cap->reserved_mtts,
ab6bf42e 212 dev->caps.mtts_per_seg);
225c7b1f
RD		 213 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
214 dev->caps.reserved_uars = dev_cap->reserved_uars;
215 dev->caps.reserved_pds = dev_cap->reserved_pds;
ab6bf42e 216 dev->caps.mtt_entry_sz = dev->caps.mtts_per_seg * dev_cap->mtt_entry_sz;
149983af 217 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
225c7b1f
RD		 218 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
219 dev->caps.flags = dev_cap->flags;
95d04f07
RD		 220 dev->caps.bmme_flags = dev_cap->bmme_flags;
221 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
225c7b1f 222 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
b832be1e 223 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
225c7b1f 224
93fc9e1b
YP		 225 dev->caps.log_num_macs = log_num_mac;
226 dev->caps.log_num_vlans = log_num_vlan;
227 dev->caps.log_num_prios = use_prio ? 3 : 0;
228
229 for (i = 1; i <= dev->caps.num_ports; ++i) {
7ff93f8b
YP		 230 if (dev->caps.supported_type[i] != MLX4_PORT_TYPE_ETH)
231 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
232 else
233 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
27bf91d6
YP		 234 dev->caps.possible_type[i] = dev->caps.port_type[i];
235 mlx4_priv(dev)->sense.sense_allowed[i] =
236 dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO;
7ff93f8b 237
93fc9e1b
YP		 238 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) {
239 dev->caps.log_num_macs = dev_cap->log_max_macs[i];
240 mlx4_warn(dev, "Requested number of MACs is too much "
241 "for port %d, reducing to %d.\n",
242 i, 1 << dev->caps.log_num_macs);
243 }
244 if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) {
245 dev->caps.log_num_vlans = dev_cap->log_max_vlans[i];
246 mlx4_warn(dev, "Requested number of VLANs is too much "
247 "for port %d, reducing to %d.\n",
248 i, 1 << dev->caps.log_num_vlans);
249 }
250 }
251
7ff93f8b
YP		 252 mlx4_set_port_mask(dev);
253
93fc9e1b
YP		 254 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
255 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
256 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
257 (1 << dev->caps.log_num_macs) *
258 (1 << dev->caps.log_num_vlans) *
259 (1 << dev->caps.log_num_prios) *
260 dev->caps.num_ports;
261 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
262
263 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
264 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
265 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
266 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
267
225c7b1f
RD		 268 return 0;
269}
270
7ff93f8b
YP		 271/*
272 * Change the port configuration of the device.
273 * Every user of this function must hold the port mutex.
274 */
27bf91d6
YP		 275int mlx4_change_port_types(struct mlx4_dev *dev,
276 enum mlx4_port_type *port_types)
7ff93f8b
YP		 277{
278 int err = 0;
279 int change = 0;
280 int port;
281
282 for (port = 0; port < dev->caps.num_ports; port++) {
27bf91d6
YP		 283 /* Change the port type only if the new type is different
284 * from the current, and not set to Auto */
7ff93f8b
YP		 285 if (port_types[port] != dev->caps.port_type[port + 1]) {
286 change = 1;
287 dev->caps.port_type[port + 1] = port_types[port];
288 }
289 }
290 if (change) {
291 mlx4_unregister_device(dev);
292 for (port = 1; port <= dev->caps.num_ports; port++) {
293 mlx4_CLOSE_PORT(dev, port);
294 err = mlx4_SET_PORT(dev, port);
295 if (err) {
296 mlx4_err(dev, "Failed to set port %d, "
297 "aborting\n", port);
298 goto out;
299 }
300 }
301 mlx4_set_port_mask(dev);
302 err = mlx4_register_device(dev);
303 }
304
305out:
306 return err;
307}
308
309static ssize_t show_port_type(struct device *dev,
310 struct device_attribute *attr,
311 char *buf)
312{
313 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
314 port_attr);
315 struct mlx4_dev *mdev = info->dev;
27bf91d6
YP		 316 char type[8];
317
318 sprintf(type, "%s",
319 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
320 "ib" : "eth");
321 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
322 sprintf(buf, "auto (%s)\n", type);
323 else
324 sprintf(buf, "%s\n", type);
7ff93f8b 325
27bf91d6 326 return strlen(buf);
7ff93f8b
YP		 327}
328
329static ssize_t set_port_type(struct device *dev,
330 struct device_attribute *attr,
331 const char *buf, size_t count)
332{
333 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
334 port_attr);
335 struct mlx4_dev *mdev = info->dev;
336 struct mlx4_priv *priv = mlx4_priv(mdev);
337 enum mlx4_port_type types[MLX4_MAX_PORTS];
27bf91d6 338 enum mlx4_port_type new_types[MLX4_MAX_PORTS];
7ff93f8b
YP		 339 int i;
340 int err = 0;
341
342 if (!strcmp(buf, "ib\n"))
343 info->tmp_type = MLX4_PORT_TYPE_IB;
344 else if (!strcmp(buf, "eth\n"))
345 info->tmp_type = MLX4_PORT_TYPE_ETH;
27bf91d6
YP		 346 else if (!strcmp(buf, "auto\n"))
347 info->tmp_type = MLX4_PORT_TYPE_AUTO;
7ff93f8b
YP		 348 else {
349 mlx4_err(mdev, "%s is not supported port type\n", buf);
350 return -EINVAL;
351 }
352
27bf91d6 353 mlx4_stop_sense(mdev);
7ff93f8b 354 mutex_lock(&priv->port_mutex);
27bf91d6
YP		 355 /* Possible type is always the one that was delivered */
356 mdev->caps.possible_type[info->port] = info->tmp_type;
357
358 for (i = 0; i < mdev->caps.num_ports; i++) {
7ff93f8b 359 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
27bf91d6
YP		 360 mdev->caps.possible_type[i+1];
361 if (types[i] == MLX4_PORT_TYPE_AUTO)
362 types[i] = mdev->caps.port_type[i+1];
363 }
7ff93f8b 364
27bf91d6
YP		 365 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
366 for (i = 1; i <= mdev->caps.num_ports; i++) {
367 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
368 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
369 err = -EINVAL;
370 }
371 }
372 }
373 if (err) {
374 mlx4_err(mdev, "Auto sensing is not supported on this HCA. "
375 "Set only 'eth' or 'ib' for both ports "
376 "(should be the same)\n");
377 goto out;
378 }
379
380 mlx4_do_sense_ports(mdev, new_types, types);
381
382 err = mlx4_check_port_params(mdev, new_types);
7ff93f8b
YP		 383 if (err)
384 goto out;
385
27bf91d6
YP		 386 /* We are about to apply the changes after the configuration
387 * was verified, no need to remember the temporary types
388 * any more */
389 for (i = 0; i < mdev->caps.num_ports; i++)
390 priv->port[i + 1].tmp_type = 0;
7ff93f8b 391
27bf91d6 392 err = mlx4_change_port_types(mdev, new_types);
7ff93f8b
YP		 393
394out:
27bf91d6 395 mlx4_start_sense(mdev);
7ff93f8b
YP		 396 mutex_unlock(&priv->port_mutex);
397 return err ? err : count;
398}
399
e8f9b2ed 400static int mlx4_load_fw(struct mlx4_dev *dev)
225c7b1f
RD		 401{
402 struct mlx4_priv *priv = mlx4_priv(dev);
403 int err;
404
405 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
5b0bf5e2 406 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f
RD		 407 if (!priv->fw.fw_icm) {
408 mlx4_err(dev, "Couldn't allocate FW area, aborting.\n");
409 return -ENOMEM;
410 }
411
412 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
413 if (err) {
414 mlx4_err(dev, "MAP_FA command failed, aborting.\n");
415 goto err_free;
416 }
417
418 err = mlx4_RUN_FW(dev);
419 if (err) {
420 mlx4_err(dev, "RUN_FW command failed, aborting.\n");
421 goto err_unmap_fa;
422 }
423
424 return 0;
425
426err_unmap_fa:
427 mlx4_UNMAP_FA(dev);
428
429err_free:
5b0bf5e2 430 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
225c7b1f
RD		 431 return err;
432}
433
e8f9b2ed
RD		 434static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
435 int cmpt_entry_sz)
225c7b1f
RD		 436{
437 struct mlx4_priv *priv = mlx4_priv(dev);
438 int err;
439
440 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
441 cmpt_base +
442 ((u64) (MLX4_CMPT_TYPE_QP *
443 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
444 cmpt_entry_sz, dev->caps.num_qps,
93fc9e1b
YP		 445 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
446 0, 0);
225c7b1f
RD		 447 if (err)
448 goto err;
449
450 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
451 cmpt_base +
452 ((u64) (MLX4_CMPT_TYPE_SRQ *
453 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
454 cmpt_entry_sz, dev->caps.num_srqs,
5b0bf5e2 455 dev->caps.reserved_srqs, 0, 0);
225c7b1f
RD		 456 if (err)
457 goto err_qp;
458
459 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
460 cmpt_base +
461 ((u64) (MLX4_CMPT_TYPE_CQ *
462 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
463 cmpt_entry_sz, dev->caps.num_cqs,
5b0bf5e2 464 dev->caps.reserved_cqs, 0, 0);
225c7b1f
RD		 465 if (err)
466 goto err_srq;
467
468 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
469 cmpt_base +
470 ((u64) (MLX4_CMPT_TYPE_EQ *
471 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
472 cmpt_entry_sz,
b8dd786f 473 dev->caps.num_eqs, dev->caps.num_eqs, 0, 0);
225c7b1f
RD		 474 if (err)
475 goto err_cq;
476
477 return 0;
478
479err_cq:
480 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
481
482err_srq:
483 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
484
485err_qp:
486 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
487
488err:
489 return err;
490}
491
3d73c288
RD		 492static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
493 struct mlx4_init_hca_param *init_hca, u64 icm_size)
225c7b1f
RD		 494{
495 struct mlx4_priv *priv = mlx4_priv(dev);
496 u64 aux_pages;
497 int err;
498
499 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
500 if (err) {
501 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n");
502 return err;
503 }
504
505 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n",
506 (unsigned long long) icm_size >> 10,
507 (unsigned long long) aux_pages << 2);
508
509 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
5b0bf5e2 510 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f
RD		 511 if (!priv->fw.aux_icm) {
512 mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n");
513 return -ENOMEM;
514 }
515
516 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
517 if (err) {
518 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n");
519 goto err_free_aux;
520 }
521
522 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
523 if (err) {
524 mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n");
525 goto err_unmap_aux;
526 }
527
528 err = mlx4_map_eq_icm(dev, init_hca->eqc_base);
529 if (err) {
530 mlx4_err(dev, "Failed to map EQ context memory, aborting.\n");
531 goto err_unmap_cmpt;
532 }
533
d7bb58fb
JM		 534 /*
535 * Reserved MTT entries must be aligned up to a cacheline
536 * boundary, since the FW will write to them, while the driver
537 * writes to all other MTT entries. (The variable
538 * dev->caps.mtt_entry_sz below is really the MTT segment
539 * size, not the raw entry size)
540 */
541 dev->caps.reserved_mtts =
542 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
543 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
544
225c7b1f
RD		 545 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
546 init_hca->mtt_base,
547 dev->caps.mtt_entry_sz,
548 dev->caps.num_mtt_segs,
5b0bf5e2 549 dev->caps.reserved_mtts, 1, 0);
225c7b1f
RD		 550 if (err) {
551 mlx4_err(dev, "Failed to map MTT context memory, aborting.\n");
552 goto err_unmap_eq;
553 }
554
555 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
556 init_hca->dmpt_base,
557 dev_cap->dmpt_entry_sz,
558 dev->caps.num_mpts,
5b0bf5e2 559 dev->caps.reserved_mrws, 1, 1);
225c7b1f
RD		 560 if (err) {
561 mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n");
562 goto err_unmap_mtt;
563 }
564
565 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
566 init_hca->qpc_base,
567 dev_cap->qpc_entry_sz,
568 dev->caps.num_qps,
93fc9e1b
YP		 569 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
570 0, 0);
225c7b1f
RD		 571 if (err) {
572 mlx4_err(dev, "Failed to map QP context memory, aborting.\n");
573 goto err_unmap_dmpt;
574 }
575
576 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
577 init_hca->auxc_base,
578 dev_cap->aux_entry_sz,
579 dev->caps.num_qps,
93fc9e1b
YP		 580 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
581 0, 0);
225c7b1f
RD		 582 if (err) {
583 mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n");
584 goto err_unmap_qp;
585 }
586
587 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
588 init_hca->altc_base,
589 dev_cap->altc_entry_sz,
590 dev->caps.num_qps,
93fc9e1b
YP		 591 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
592 0, 0);
225c7b1f
RD		 593 if (err) {
594 mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n");
595 goto err_unmap_auxc;
596 }
597
598 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
599 init_hca->rdmarc_base,
600 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
601 dev->caps.num_qps,
93fc9e1b
YP		 602 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
603 0, 0);
225c7b1f
RD		 604 if (err) {
605 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
606 goto err_unmap_altc;
607 }
608
609 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
610 init_hca->cqc_base,
611 dev_cap->cqc_entry_sz,
612 dev->caps.num_cqs,
5b0bf5e2 613 dev->caps.reserved_cqs, 0, 0);
225c7b1f
RD		 614 if (err) {
615 mlx4_err(dev, "Failed to map CQ context memory, aborting.\n");
616 goto err_unmap_rdmarc;
617 }
618
619 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
620 init_hca->srqc_base,
621 dev_cap->srq_entry_sz,
622 dev->caps.num_srqs,
5b0bf5e2 623 dev->caps.reserved_srqs, 0, 0);
225c7b1f
RD		 624 if (err) {
625 mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n");
626 goto err_unmap_cq;
627 }
628
629 /*
630 * It's not strictly required, but for simplicity just map the
631 * whole multicast group table now. The table isn't very big
632 * and it's a lot easier than trying to track ref counts.
633 */
634 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
635 init_hca->mc_base, MLX4_MGM_ENTRY_SIZE,
636 dev->caps.num_mgms + dev->caps.num_amgms,
637 dev->caps.num_mgms + dev->caps.num_amgms,
5b0bf5e2 638 0, 0);
225c7b1f
RD		 639 if (err) {
640 mlx4_err(dev, "Failed to map MCG context memory, aborting.\n");
641 goto err_unmap_srq;
642 }
643
644 return 0;
645
646err_unmap_srq:
647 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
648
649err_unmap_cq:
650 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
651
652err_unmap_rdmarc:
653 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
654
655err_unmap_altc:
656 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
657
658err_unmap_auxc:
659 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
660
661err_unmap_qp:
662 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
663
664err_unmap_dmpt:
665 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
666
667err_unmap_mtt:
668 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
669
670err_unmap_eq:
671 mlx4_unmap_eq_icm(dev);
672
673err_unmap_cmpt:
674 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
675 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
676 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
677 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
678
679err_unmap_aux:
680 mlx4_UNMAP_ICM_AUX(dev);
681
682err_free_aux:
5b0bf5e2 683 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 684
685 return err;
686}
687
688static void mlx4_free_icms(struct mlx4_dev *dev)
689{
690 struct mlx4_priv *priv = mlx4_priv(dev);
691
692 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
693 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
694 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
695 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
696 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
697 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
698 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
699 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
700 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
701 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
702 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
703 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
704 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
705 mlx4_unmap_eq_icm(dev);
706
707 mlx4_UNMAP_ICM_AUX(dev);
5b0bf5e2 708 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 709}
710
711static void mlx4_close_hca(struct mlx4_dev *dev)
712{
713 mlx4_CLOSE_HCA(dev, 0);
714 mlx4_free_icms(dev);
715 mlx4_UNMAP_FA(dev);
5b0bf5e2 716 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
225c7b1f
RD		 717}
718
3d73c288 719static int mlx4_init_hca(struct mlx4_dev *dev)
225c7b1f
RD		 720{
721 struct mlx4_priv *priv = mlx4_priv(dev);
722 struct mlx4_adapter adapter;
723 struct mlx4_dev_cap dev_cap;
2d928651 724 struct mlx4_mod_stat_cfg mlx4_cfg;
225c7b1f
RD		 725 struct mlx4_profile profile;
726 struct mlx4_init_hca_param init_hca;
727 u64 icm_size;
728 int err;
729
730 err = mlx4_QUERY_FW(dev);
731 if (err) {
cc4ac2e7
YP		 732 if (err == -EACCES)
733 mlx4_info(dev, "non-primary physical function, skipping.\n");
734 else
735 mlx4_err(dev, "QUERY_FW command failed, aborting.\n");
225c7b1f
RD		 736 return err;
737 }
738
739 err = mlx4_load_fw(dev);
740 if (err) {
741 mlx4_err(dev, "Failed to start FW, aborting.\n");
742 return err;
743 }
744
2d928651
VS		 745 mlx4_cfg.log_pg_sz_m = 1;
746 mlx4_cfg.log_pg_sz = 0;
747 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
748 if (err)
749 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
750
225c7b1f
RD		 751 err = mlx4_dev_cap(dev, &dev_cap);
752 if (err) {
753 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
754 goto err_stop_fw;
755 }
756
757 profile = default_profile;
758
759 icm_size = mlx4_make_profile(dev, &profile, &dev_cap, &init_hca);
760 if ((long long) icm_size < 0) {
761 err = icm_size;
762 goto err_stop_fw;
763 }
764
765 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
766
767 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
768 if (err)
769 goto err_stop_fw;
770
771 err = mlx4_INIT_HCA(dev, &init_hca);
772 if (err) {
773 mlx4_err(dev, "INIT_HCA command failed, aborting.\n");
774 goto err_free_icm;
775 }
776
777 err = mlx4_QUERY_ADAPTER(dev, &adapter);
778 if (err) {
779 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n");
780 goto err_close;
781 }
782
783 priv->eq_table.inta_pin = adapter.inta_pin;
cd9281d8 784 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
225c7b1f
RD		 785
786 return 0;
787
788err_close:
789 mlx4_close_hca(dev);
790
791err_free_icm:
792 mlx4_free_icms(dev);
793
794err_stop_fw:
795 mlx4_UNMAP_FA(dev);
5b0bf5e2 796 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
225c7b1f
RD		 797
798 return err;
799}
800
3d73c288 801static int mlx4_setup_hca(struct mlx4_dev *dev)
225c7b1f
RD		 802{
803 struct mlx4_priv *priv = mlx4_priv(dev);
804 int err;
7ff93f8b 805 int port;
9a5aa622 806 __be32 ib_port_default_caps;
225c7b1f 807
225c7b1f
RD		 808 err = mlx4_init_uar_table(dev);
809 if (err) {
810 mlx4_err(dev, "Failed to initialize "
811 "user access region table, aborting.\n");
812 return err;
813 }
814
815 err = mlx4_uar_alloc(dev, &priv->driver_uar);
816 if (err) {
817 mlx4_err(dev, "Failed to allocate driver access region, "
818 "aborting.\n");
819 goto err_uar_table_free;
820 }
821
822 priv->kar = ioremap(priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
823 if (!priv->kar) {
824 mlx4_err(dev, "Couldn't map kernel access region, "
825 "aborting.\n");
826 err = -ENOMEM;
827 goto err_uar_free;
828 }
829
830 err = mlx4_init_pd_table(dev);
831 if (err) {
832 mlx4_err(dev, "Failed to initialize "
833 "protection domain table, aborting.\n");
834 goto err_kar_unmap;
835 }
836
837 err = mlx4_init_mr_table(dev);
838 if (err) {
839 mlx4_err(dev, "Failed to initialize "
840 "memory region table, aborting.\n");
841 goto err_pd_table_free;
842 }
843
225c7b1f
RD		 844 err = mlx4_init_eq_table(dev);
845 if (err) {
846 mlx4_err(dev, "Failed to initialize "
847 "event queue table, aborting.\n");
ee49bd93 848 goto err_mr_table_free;
225c7b1f
RD		 849 }
850
851 err = mlx4_cmd_use_events(dev);
852 if (err) {
853 mlx4_err(dev, "Failed to switch to event-driven "
854 "firmware commands, aborting.\n");
855 goto err_eq_table_free;
856 }
857
858 err = mlx4_NOP(dev);
859 if (err) {
08fb1055
MT		 860 if (dev->flags & MLX4_FLAG_MSI_X) {
861 mlx4_warn(dev, "NOP command failed to generate MSI-X "
862 "interrupt IRQ %d).\n",
b8dd786f 863 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
08fb1055
MT		 864 mlx4_warn(dev, "Trying again without MSI-X.\n");
865 } else {
866 mlx4_err(dev, "NOP command failed to generate interrupt "
867 "(IRQ %d), aborting.\n",
b8dd786f 868 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
225c7b1f 869 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
08fb1055 870 }
225c7b1f
RD		 871
872 goto err_cmd_poll;
873 }
874
875 mlx4_dbg(dev, "NOP command IRQ test passed\n");
876
877 err = mlx4_init_cq_table(dev);
878 if (err) {
879 mlx4_err(dev, "Failed to initialize "
880 "completion queue table, aborting.\n");
881 goto err_cmd_poll;
882 }
883
884 err = mlx4_init_srq_table(dev);
885 if (err) {
886 mlx4_err(dev, "Failed to initialize "
887 "shared receive queue table, aborting.\n");
888 goto err_cq_table_free;
889 }
890
891 err = mlx4_init_qp_table(dev);
892 if (err) {
893 mlx4_err(dev, "Failed to initialize "
894 "queue pair table, aborting.\n");
895 goto err_srq_table_free;
896 }
897
898 err = mlx4_init_mcg_table(dev);
899 if (err) {
900 mlx4_err(dev, "Failed to initialize "
901 "multicast group table, aborting.\n");
902 goto err_qp_table_free;
903 }
904
7ff93f8b 905 for (port = 1; port <= dev->caps.num_ports; port++) {
9a5aa622
JM		 906 ib_port_default_caps = 0;
907 err = mlx4_get_port_ib_caps(dev, port, &ib_port_default_caps);
908 if (err)
909 mlx4_warn(dev, "failed to get port %d default "
910 "ib capabilities (%d). Continuing with "
911 "caps = 0\n", port, err);
912 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
7ff93f8b
YP		 913 err = mlx4_SET_PORT(dev, port);
914 if (err) {
915 mlx4_err(dev, "Failed to set port %d, aborting\n",
916 port);
917 goto err_mcg_table_free;
918 }
919 }
920
225c7b1f
RD		 921 return 0;
922
7ff93f8b
YP		 923err_mcg_table_free:
924 mlx4_cleanup_mcg_table(dev);
925
225c7b1f
RD		 926err_qp_table_free:
927 mlx4_cleanup_qp_table(dev);
928
929err_srq_table_free:
930 mlx4_cleanup_srq_table(dev);
931
932err_cq_table_free:
933 mlx4_cleanup_cq_table(dev);
934
935err_cmd_poll:
936 mlx4_cmd_use_polling(dev);
937
938err_eq_table_free:
939 mlx4_cleanup_eq_table(dev);
940
ee49bd93 941err_mr_table_free:
225c7b1f
RD		 942 mlx4_cleanup_mr_table(dev);
943
944err_pd_table_free:
945 mlx4_cleanup_pd_table(dev);
946
947err_kar_unmap:
948 iounmap(priv->kar);
949
950err_uar_free:
951 mlx4_uar_free(dev, &priv->driver_uar);
952
953err_uar_table_free:
954 mlx4_cleanup_uar_table(dev);
955 return err;
956}
957
e8f9b2ed 958static void mlx4_enable_msi_x(struct mlx4_dev *dev)
225c7b1f
RD		 959{
960 struct mlx4_priv *priv = mlx4_priv(dev);
b8dd786f
YP		 961 struct msix_entry *entries;
962 int nreq;
225c7b1f
RD		 963 int err;
964 int i;
965
966 if (msi_x) {
70cb9253
RD		 967 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs,
968 num_possible_cpus() + 1);
b8dd786f
YP		 969 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
970 if (!entries)
971 goto no_msi;
972
973 for (i = 0; i < nreq; ++i)
225c7b1f
RD		 974 entries[i].entry = i;
975
b8dd786f
YP		 976 retry:
977 err = pci_enable_msix(dev->pdev, entries, nreq);
225c7b1f 978 if (err) {
b8dd786f
YP		 979 /* Try again if at least 2 vectors are available */
980 if (err > 1) {
981 mlx4_info(dev, "Requested %d vectors, "
982 "but only %d MSI-X vectors available, "
983 "trying again\n", nreq, err);
984 nreq = err;
985 goto retry;
986 }
5bf0da7d 987 kfree(entries);
225c7b1f
RD		 988 goto no_msi;
989 }
990
b8dd786f
YP		 991 dev->caps.num_comp_vectors = nreq - 1;
992 for (i = 0; i < nreq; ++i)
225c7b1f
RD		 993 priv->eq_table.eq[i].irq = entries[i].vector;
994
995 dev->flags |= MLX4_FLAG_MSI_X;
b8dd786f
YP		 996
997 kfree(entries);
225c7b1f
RD		 998 return;
999 }
1000
1001no_msi:
b8dd786f
YP		 1002 dev->caps.num_comp_vectors = 1;
1003
1004 for (i = 0; i < 2; ++i)
225c7b1f
RD		 1005 priv->eq_table.eq[i].irq = dev->pdev->irq;
1006}
1007
7ff93f8b 1008static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
2a2336f8
YP		 1009{
1010 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
7ff93f8b 1011 int err = 0;
2a2336f8
YP		 1012
1013 info->dev = dev;
1014 info->port = port;
1015 mlx4_init_mac_table(dev, &info->mac_table);
1016 mlx4_init_vlan_table(dev, &info->vlan_table);
7ff93f8b
YP		 1017
1018 sprintf(info->dev_name, "mlx4_port%d", port);
1019 info->port_attr.attr.name = info->dev_name;
1020 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
1021 info->port_attr.show = show_port_type;
1022 info->port_attr.store = set_port_type;
1023
1024 err = device_create_file(&dev->pdev->dev, &info->port_attr);
1025 if (err) {
1026 mlx4_err(dev, "Failed to create file for port %d\n", port);
1027 info->port = -1;
1028 }
1029
1030 return err;
1031}
1032
1033static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
1034{
1035 if (info->port < 0)
1036 return;
1037
1038 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
2a2336f8
YP		 1039}
1040
3d73c288 1041static int __mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
225c7b1f 1042{
225c7b1f
RD		 1043 struct mlx4_priv *priv;
1044 struct mlx4_dev *dev;
1045 int err;
2a2336f8 1046 int port;
225c7b1f 1047
225c7b1f
RD		 1048 printk(KERN_INFO PFX "Initializing %s\n",
1049 pci_name(pdev));
1050
1051 err = pci_enable_device(pdev);
1052 if (err) {
1053 dev_err(&pdev->dev, "Cannot enable PCI device, "
1054 "aborting.\n");
1055 return err;
1056 }
1057
1058 /*
4ff08a76 1059 * Check for BARs. We expect 0: 1MB
225c7b1f
RD		 1060 */
1061 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
1062 pci_resource_len(pdev, 0) != 1 << 20) {
1063 dev_err(&pdev->dev, "Missing DCS, aborting.\n");
1064 err = -ENODEV;
1065 goto err_disable_pdev;
1066 }
1067 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
1068 dev_err(&pdev->dev, "Missing UAR, aborting.\n");
1069 err = -ENODEV;
1070 goto err_disable_pdev;
1071 }
1072
1073 err = pci_request_region(pdev, 0, DRV_NAME);
1074 if (err) {
1075 dev_err(&pdev->dev, "Cannot request control region, aborting.\n");
1076 goto err_disable_pdev;
1077 }
1078
1079 err = pci_request_region(pdev, 2, DRV_NAME);
1080 if (err) {
1081 dev_err(&pdev->dev, "Cannot request UAR region, aborting.\n");
1082 goto err_release_bar0;
1083 }
1084
1085 pci_set_master(pdev);
1086
6a35528a 1087 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
225c7b1f
RD		 1088 if (err) {
1089 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
284901a9 1090 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
225c7b1f
RD		 1091 if (err) {
1092 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
1093 goto err_release_bar2;
1094 }
1095 }
6a35528a 1096 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
225c7b1f
RD		 1097 if (err) {
1098 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
1099 "consistent PCI DMA mask.\n");
284901a9 1100 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
225c7b1f
RD		 1101 if (err) {
1102 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
1103 "aborting.\n");
1104 goto err_release_bar2;
1105 }
1106 }
1107
1108 priv = kzalloc(sizeof *priv, GFP_KERNEL);
1109 if (!priv) {
1110 dev_err(&pdev->dev, "Device struct alloc failed, "
1111 "aborting.\n");
1112 err = -ENOMEM;
1113 goto err_release_bar2;
1114 }
1115
1116 dev = &priv->dev;
1117 dev->pdev = pdev;
b581401e
RD		 1118 INIT_LIST_HEAD(&priv->ctx_list);
1119 spin_lock_init(&priv->ctx_lock);
225c7b1f 1120
7ff93f8b
YP		 1121 mutex_init(&priv->port_mutex);
1122
6296883c
YP		 1123 INIT_LIST_HEAD(&priv->pgdir_list);
1124 mutex_init(&priv->pgdir_mutex);
1125
225c7b1f
RD		 1126 /*
1127 * Now reset the HCA before we touch the PCI capabilities or
1128 * attempt a firmware command, since a boot ROM may have left
1129 * the HCA in an undefined state.
1130 */
1131 err = mlx4_reset(dev);
1132 if (err) {
1133 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
1134 goto err_free_dev;
1135 }
1136
225c7b1f
RD		 1137 if (mlx4_cmd_init(dev)) {
1138 mlx4_err(dev, "Failed to init command interface, aborting.\n");
1139 goto err_free_dev;
1140 }
1141
1142 err = mlx4_init_hca(dev);
1143 if (err)
1144 goto err_cmd;
1145
b8dd786f
YP		 1146 err = mlx4_alloc_eq_table(dev);
1147 if (err)
1148 goto err_close;
1149
08fb1055
MT		 1150 mlx4_enable_msi_x(dev);
1151
225c7b1f 1152 err = mlx4_setup_hca(dev);
08fb1055
MT		 1153 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X)) {
1154 dev->flags &= ~MLX4_FLAG_MSI_X;
1155 pci_disable_msix(pdev);
1156 err = mlx4_setup_hca(dev);
1157 }
1158
225c7b1f 1159 if (err)
b8dd786f 1160 goto err_free_eq;
225c7b1f 1161
7ff93f8b
YP		 1162 for (port = 1; port <= dev->caps.num_ports; port++) {
1163 err = mlx4_init_port_info(dev, port);
1164 if (err)
1165 goto err_port;
1166 }
2a2336f8 1167
225c7b1f
RD		 1168 err = mlx4_register_device(dev);
1169 if (err)
7ff93f8b 1170 goto err_port;
225c7b1f 1171
27bf91d6
YP		 1172 mlx4_sense_init(dev);
1173 mlx4_start_sense(dev);
1174
225c7b1f
RD		 1175 pci_set_drvdata(pdev, dev);
1176
1177 return 0;
1178
7ff93f8b
YP		 1179err_port:
1180 for (port = 1; port <= dev->caps.num_ports; port++)
1181 mlx4_cleanup_port_info(&priv->port[port]);
1182
225c7b1f
RD		 1183 mlx4_cleanup_mcg_table(dev);
1184 mlx4_cleanup_qp_table(dev);
1185 mlx4_cleanup_srq_table(dev);
1186 mlx4_cleanup_cq_table(dev);
1187 mlx4_cmd_use_polling(dev);
1188 mlx4_cleanup_eq_table(dev);
225c7b1f
RD		 1189 mlx4_cleanup_mr_table(dev);
1190 mlx4_cleanup_pd_table(dev);
1191 mlx4_cleanup_uar_table(dev);
1192
b8dd786f
YP		 1193err_free_eq:
1194 mlx4_free_eq_table(dev);
1195
225c7b1f 1196err_close:
08fb1055
MT		 1197 if (dev->flags & MLX4_FLAG_MSI_X)
1198 pci_disable_msix(pdev);
1199
225c7b1f
RD		 1200 mlx4_close_hca(dev);
1201
1202err_cmd:
1203 mlx4_cmd_cleanup(dev);
1204
1205err_free_dev:
225c7b1f
RD		 1206 kfree(priv);
1207
1208err_release_bar2:
1209 pci_release_region(pdev, 2);
1210
1211err_release_bar0:
1212 pci_release_region(pdev, 0);
1213
1214err_disable_pdev:
1215 pci_disable_device(pdev);
1216 pci_set_drvdata(pdev, NULL);
1217 return err;
1218}
1219
3d73c288
RD		 1220static int __devinit mlx4_init_one(struct pci_dev *pdev,
1221 const struct pci_device_id *id)
1222{
1223 static int mlx4_version_printed;
1224
1225 if (!mlx4_version_printed) {
1226 printk(KERN_INFO "%s", mlx4_version);
1227 ++mlx4_version_printed;
1228 }
1229
b027cacd 1230 return __mlx4_init_one(pdev, id);
3d73c288
RD		 1231}
1232
1233static void mlx4_remove_one(struct pci_dev *pdev)
225c7b1f
RD		 1234{
1235 struct mlx4_dev *dev = pci_get_drvdata(pdev);
1236 struct mlx4_priv *priv = mlx4_priv(dev);
1237 int p;
1238
1239 if (dev) {
27bf91d6 1240 mlx4_stop_sense(dev);
225c7b1f
RD		 1241 mlx4_unregister_device(dev);
1242
7ff93f8b
YP		 1243 for (p = 1; p <= dev->caps.num_ports; p++) {
1244 mlx4_cleanup_port_info(&priv->port[p]);
225c7b1f 1245 mlx4_CLOSE_PORT(dev, p);
7ff93f8b 1246 }
225c7b1f
RD		 1247
1248 mlx4_cleanup_mcg_table(dev);
1249 mlx4_cleanup_qp_table(dev);
1250 mlx4_cleanup_srq_table(dev);
1251 mlx4_cleanup_cq_table(dev);
1252 mlx4_cmd_use_polling(dev);
1253 mlx4_cleanup_eq_table(dev);
225c7b1f
RD		 1254 mlx4_cleanup_mr_table(dev);
1255 mlx4_cleanup_pd_table(dev);
1256
1257 iounmap(priv->kar);
1258 mlx4_uar_free(dev, &priv->driver_uar);
1259 mlx4_cleanup_uar_table(dev);
b8dd786f 1260 mlx4_free_eq_table(dev);
225c7b1f
RD		 1261 mlx4_close_hca(dev);
1262 mlx4_cmd_cleanup(dev);
1263
1264 if (dev->flags & MLX4_FLAG_MSI_X)
1265 pci_disable_msix(pdev);
1266
1267 kfree(priv);
1268 pci_release_region(pdev, 2);
1269 pci_release_region(pdev, 0);
1270 pci_disable_device(pdev);
1271 pci_set_drvdata(pdev, NULL);
1272 }
1273}
1274
ee49bd93
JM		 1275int mlx4_restart_one(struct pci_dev *pdev)
1276{
1277 mlx4_remove_one(pdev);
3d73c288 1278 return __mlx4_init_one(pdev, NULL);
ee49bd93
JM		 1279}
1280
225c7b1f
RD		 1281static struct pci_device_id mlx4_pci_table[] = {
1282 { PCI_VDEVICE(MELLANOX, 0x6340) }, /* MT25408 "Hermon" SDR */
1283 { PCI_VDEVICE(MELLANOX, 0x634a) }, /* MT25408 "Hermon" DDR */
1284 { PCI_VDEVICE(MELLANOX, 0x6354) }, /* MT25408 "Hermon" QDR */
786f238e
JM		 1285 { PCI_VDEVICE(MELLANOX, 0x6732) }, /* MT25408 "Hermon" DDR PCIe gen2 */
1286 { PCI_VDEVICE(MELLANOX, 0x673c) }, /* MT25408 "Hermon" QDR PCIe gen2 */
57893d1c
YP		 1287 { PCI_VDEVICE(MELLANOX, 0x6368) }, /* MT25408 "Hermon" EN 10GigE */
1288 { PCI_VDEVICE(MELLANOX, 0x6750) }, /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
085343b4
JM		 1289 { PCI_VDEVICE(MELLANOX, 0x6372) }, /* MT25458 ConnectX EN 10GBASE-T 10GigE */
1290 { PCI_VDEVICE(MELLANOX, 0x675a) }, /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
92bd3bbf 1291 { PCI_VDEVICE(MELLANOX, 0x6764) }, /* MT26468 ConnectX EN 10GigE PCIe gen2*/
225c7b1f
RD		 1292 { 0, }
1293};
1294
1295MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
1296
1297static struct pci_driver mlx4_driver = {
1298 .name = DRV_NAME,
1299 .id_table = mlx4_pci_table,
1300 .probe = mlx4_init_one,
1301 .remove = __devexit_p(mlx4_remove_one)
1302};
1303
7ff93f8b
YP		 1304static int __init mlx4_verify_params(void)
1305{
1306 if ((log_num_mac < 0) || (log_num_mac > 7)) {
1307 printk(KERN_WARNING "mlx4_core: bad num_mac: %d\n", log_num_mac);
1308 return -1;
1309 }
1310
1311 if ((log_num_vlan < 0) || (log_num_vlan > 7)) {
1312 printk(KERN_WARNING "mlx4_core: bad num_vlan: %d\n", log_num_vlan);
1313 return -1;
1314 }
1315
ab6bf42e
EC		 1316 if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 5)) {
1317 printk(KERN_WARNING "mlx4_core: bad log_mtts_per_seg: %d\n", log_mtts_per_seg);
1318 return -1;
1319 }
1320
7ff93f8b
YP		 1321 return 0;
1322}
1323
225c7b1f
RD		 1324static int __init mlx4_init(void)
1325{
1326 int ret;
1327
7ff93f8b
YP		 1328 if (mlx4_verify_params())
1329 return -EINVAL;
1330
27bf91d6
YP		 1331 mlx4_catas_init();
1332
1333 mlx4_wq = create_singlethread_workqueue("mlx4");
1334 if (!mlx4_wq)
1335 return -ENOMEM;
ee49bd93 1336
225c7b1f
RD		 1337 ret = pci_register_driver(&mlx4_driver);
1338 return ret < 0 ? ret : 0;
1339}
1340
1341static void __exit mlx4_cleanup(void)
1342{
1343 pci_unregister_driver(&mlx4_driver);
27bf91d6 1344 destroy_workqueue(mlx4_wq);
225c7b1f
RD		 1345}
1346
1347module_init(mlx4_init);
1348module_exit(mlx4_cleanup);
Linux 6.x block layer and io_uring tree(s)