projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
IPoIB: Allow setting policy to ignore multicast groups
[linux-2.6-block.git] / drivers / net / mlx4 / main.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 */
35
36#include <linux/module.h>
37#include <linux/init.h>
38#include <linux/errno.h>
39#include <linux/pci.h>
40#include <linux/dma-mapping.h>
41
42#include <linux/mlx4/device.h>
43#include <linux/mlx4/doorbell.h>
44
45#include "mlx4.h"
46#include "fw.h"
47#include "icm.h"
48
49MODULE_AUTHOR("Roland Dreier");
50MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
51MODULE_LICENSE("Dual BSD/GPL");
52MODULE_VERSION(DRV_VERSION);
53
54#ifdef CONFIG_MLX4_DEBUG
55
56int mlx4_debug_level = 0;
57module_param_named(debug_level, mlx4_debug_level, int, 0644);
58MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
59
60#endif /* CONFIG_MLX4_DEBUG */
61
62#ifdef CONFIG_PCI_MSI
63
08fb1055 64static int msi_x = 1;
225c7b1f
RD		 65module_param(msi_x, int, 0444);
66MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
67
68#else /* CONFIG_PCI_MSI */
69
70#define msi_x (0)
71
72#endif /* CONFIG_PCI_MSI */
73
74static const char mlx4_version[] __devinitdata =
75 DRV_NAME ": Mellanox ConnectX core driver v"
76 DRV_VERSION " (" DRV_RELDATE ")\n";
77
78static struct mlx4_profile default_profile = {
79 .num_qp = 1 << 16,
80 .num_srq = 1 << 16,
c9f2ba5e 81 .rdmarc_per_qp = 1 << 4,
225c7b1f
RD		 82 .num_cq = 1 << 16,
83 .num_mcg = 1 << 13,
84 .num_mpt = 1 << 17,
85 .num_mtt = 1 << 20,
86};
87
88static int __devinit mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
89{
90 int err;
5ae2a7a8 91 int i;
225c7b1f
RD		 92
93 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
94 if (err) {
95 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
96 return err;
97 }
98
99 if (dev_cap->min_page_sz > PAGE_SIZE) {
100 mlx4_err(dev, "HCA minimum page size of %d bigger than "
101 "kernel PAGE_SIZE of %ld, aborting.\n",
102 dev_cap->min_page_sz, PAGE_SIZE);
103 return -ENODEV;
104 }
105 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
106 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
107 "aborting.\n",
108 dev_cap->num_ports, MLX4_MAX_PORTS);
109 return -ENODEV;
110 }
111
112 if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) {
113 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than "
114 "PCI resource 2 size of 0x%llx, aborting.\n",
115 dev_cap->uar_size,
116 (unsigned long long) pci_resource_len(dev->pdev, 2));
117 return -ENODEV;
118 }
119
120 dev->caps.num_ports = dev_cap->num_ports;
5ae2a7a8
RD		 121 for (i = 1; i <= dev->caps.num_ports; ++i) {
122 dev->caps.vl_cap[i] = dev_cap->max_vl[i];
123 dev->caps.mtu_cap[i] = dev_cap->max_mtu[i];
124 dev->caps.gid_table_len[i] = dev_cap->max_gids[i];
125 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
126 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i];
127 }
128
225c7b1f 129 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
225c7b1f
RD		 130 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
131 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
132 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
133 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
134 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
135 dev->caps.max_wqes = dev_cap->max_qp_sz;
136 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
137 dev->caps.reserved_qps = dev_cap->reserved_qps;
138 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
139 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
140 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
141 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
142 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
143 dev->caps.num_qp_per_mgm = MLX4_QP_PER_MGM;
144 /*
145 * Subtract 1 from the limit because we need to allocate a
146 * spare CQE so the HCA HW can tell the difference between an
147 * empty CQ and a full CQ.
148 */
149 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
150 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
151 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
121964ec
RD		 152 dev->caps.reserved_mtts = DIV_ROUND_UP(dev_cap->reserved_mtts,
153 MLX4_MTT_ENTRY_PER_SEG);
225c7b1f
RD		 154 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
155 dev->caps.reserved_uars = dev_cap->reserved_uars;
156 dev->caps.reserved_pds = dev_cap->reserved_pds;
225c7b1f 157 dev->caps.mtt_entry_sz = MLX4_MTT_ENTRY_PER_SEG * dev_cap->mtt_entry_sz;
149983af 158 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
225c7b1f
RD		 159 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
160 dev->caps.flags = dev_cap->flags;
161 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
162
163 return 0;
164}
165
166static int __devinit mlx4_load_fw(struct mlx4_dev *dev)
167{
168 struct mlx4_priv *priv = mlx4_priv(dev);
169 int err;
170
171 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
5b0bf5e2 172 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f
RD		 173 if (!priv->fw.fw_icm) {
174 mlx4_err(dev, "Couldn't allocate FW area, aborting.\n");
175 return -ENOMEM;
176 }
177
178 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
179 if (err) {
180 mlx4_err(dev, "MAP_FA command failed, aborting.\n");
181 goto err_free;
182 }
183
184 err = mlx4_RUN_FW(dev);
185 if (err) {
186 mlx4_err(dev, "RUN_FW command failed, aborting.\n");
187 goto err_unmap_fa;
188 }
189
190 return 0;
191
192err_unmap_fa:
193 mlx4_UNMAP_FA(dev);
194
195err_free:
5b0bf5e2 196 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
225c7b1f
RD		 197 return err;
198}
199
200static int __devinit mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
201 int cmpt_entry_sz)
202{
203 struct mlx4_priv *priv = mlx4_priv(dev);
204 int err;
205
206 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
207 cmpt_base +
208 ((u64) (MLX4_CMPT_TYPE_QP *
209 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
210 cmpt_entry_sz, dev->caps.num_qps,
5b0bf5e2 211 dev->caps.reserved_qps, 0, 0);
225c7b1f
RD		 212 if (err)
213 goto err;
214
215 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
216 cmpt_base +
217 ((u64) (MLX4_CMPT_TYPE_SRQ *
218 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
219 cmpt_entry_sz, dev->caps.num_srqs,
5b0bf5e2 220 dev->caps.reserved_srqs, 0, 0);
225c7b1f
RD		 221 if (err)
222 goto err_qp;
223
224 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
225 cmpt_base +
226 ((u64) (MLX4_CMPT_TYPE_CQ *
227 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
228 cmpt_entry_sz, dev->caps.num_cqs,
5b0bf5e2 229 dev->caps.reserved_cqs, 0, 0);
225c7b1f
RD		 230 if (err)
231 goto err_srq;
232
233 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
234 cmpt_base +
235 ((u64) (MLX4_CMPT_TYPE_EQ *
236 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
237 cmpt_entry_sz,
238 roundup_pow_of_two(MLX4_NUM_EQ +
239 dev->caps.reserved_eqs),
5b0bf5e2 240 MLX4_NUM_EQ + dev->caps.reserved_eqs, 0, 0);
225c7b1f
RD		 241 if (err)
242 goto err_cq;
243
244 return 0;
245
246err_cq:
247 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
248
249err_srq:
250 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
251
252err_qp:
253 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
254
255err:
256 return err;
257}
258
259static int __devinit mlx4_init_icm(struct mlx4_dev *dev,
260 struct mlx4_dev_cap *dev_cap,
261 struct mlx4_init_hca_param *init_hca,
262 u64 icm_size)
263{
264 struct mlx4_priv *priv = mlx4_priv(dev);
265 u64 aux_pages;
266 int err;
267
268 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
269 if (err) {
270 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n");
271 return err;
272 }
273
274 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n",
275 (unsigned long long) icm_size >> 10,
276 (unsigned long long) aux_pages << 2);
277
278 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
5b0bf5e2 279 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f
RD		 280 if (!priv->fw.aux_icm) {
281 mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n");
282 return -ENOMEM;
283 }
284
285 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
286 if (err) {
287 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n");
288 goto err_free_aux;
289 }
290
291 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
292 if (err) {
293 mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n");
294 goto err_unmap_aux;
295 }
296
297 err = mlx4_map_eq_icm(dev, init_hca->eqc_base);
298 if (err) {
299 mlx4_err(dev, "Failed to map EQ context memory, aborting.\n");
300 goto err_unmap_cmpt;
301 }
302
d7bb58fb
JM		 303 /*
304 * Reserved MTT entries must be aligned up to a cacheline
305 * boundary, since the FW will write to them, while the driver
306 * writes to all other MTT entries. (The variable
307 * dev->caps.mtt_entry_sz below is really the MTT segment
308 * size, not the raw entry size)
309 */
310 dev->caps.reserved_mtts =
311 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
312 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
313
225c7b1f
RD		 314 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
315 init_hca->mtt_base,
316 dev->caps.mtt_entry_sz,
317 dev->caps.num_mtt_segs,
5b0bf5e2 318 dev->caps.reserved_mtts, 1, 0);
225c7b1f
RD		 319 if (err) {
320 mlx4_err(dev, "Failed to map MTT context memory, aborting.\n");
321 goto err_unmap_eq;
322 }
323
324 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
325 init_hca->dmpt_base,
326 dev_cap->dmpt_entry_sz,
327 dev->caps.num_mpts,
5b0bf5e2 328 dev->caps.reserved_mrws, 1, 1);
225c7b1f
RD		 329 if (err) {
330 mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n");
331 goto err_unmap_mtt;
332 }
333
334 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
335 init_hca->qpc_base,
336 dev_cap->qpc_entry_sz,
337 dev->caps.num_qps,
5b0bf5e2 338 dev->caps.reserved_qps, 0, 0);
225c7b1f
RD		 339 if (err) {
340 mlx4_err(dev, "Failed to map QP context memory, aborting.\n");
341 goto err_unmap_dmpt;
342 }
343
344 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
345 init_hca->auxc_base,
346 dev_cap->aux_entry_sz,
347 dev->caps.num_qps,
5b0bf5e2 348 dev->caps.reserved_qps, 0, 0);
225c7b1f
RD		 349 if (err) {
350 mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n");
351 goto err_unmap_qp;
352 }
353
354 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
355 init_hca->altc_base,
356 dev_cap->altc_entry_sz,
357 dev->caps.num_qps,
5b0bf5e2 358 dev->caps.reserved_qps, 0, 0);
225c7b1f
RD		 359 if (err) {
360 mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n");
361 goto err_unmap_auxc;
362 }
363
364 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
365 init_hca->rdmarc_base,
366 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
367 dev->caps.num_qps,
5b0bf5e2 368 dev->caps.reserved_qps, 0, 0);
225c7b1f
RD		 369 if (err) {
370 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
371 goto err_unmap_altc;
372 }
373
374 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
375 init_hca->cqc_base,
376 dev_cap->cqc_entry_sz,
377 dev->caps.num_cqs,
5b0bf5e2 378 dev->caps.reserved_cqs, 0, 0);
225c7b1f
RD		 379 if (err) {
380 mlx4_err(dev, "Failed to map CQ context memory, aborting.\n");
381 goto err_unmap_rdmarc;
382 }
383
384 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
385 init_hca->srqc_base,
386 dev_cap->srq_entry_sz,
387 dev->caps.num_srqs,
5b0bf5e2 388 dev->caps.reserved_srqs, 0, 0);
225c7b1f
RD		 389 if (err) {
390 mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n");
391 goto err_unmap_cq;
392 }
393
394 /*
395 * It's not strictly required, but for simplicity just map the
396 * whole multicast group table now. The table isn't very big
397 * and it's a lot easier than trying to track ref counts.
398 */
399 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
400 init_hca->mc_base, MLX4_MGM_ENTRY_SIZE,
401 dev->caps.num_mgms + dev->caps.num_amgms,
402 dev->caps.num_mgms + dev->caps.num_amgms,
5b0bf5e2 403 0, 0);
225c7b1f
RD		 404 if (err) {
405 mlx4_err(dev, "Failed to map MCG context memory, aborting.\n");
406 goto err_unmap_srq;
407 }
408
409 return 0;
410
411err_unmap_srq:
412 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
413
414err_unmap_cq:
415 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
416
417err_unmap_rdmarc:
418 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
419
420err_unmap_altc:
421 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
422
423err_unmap_auxc:
424 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
425
426err_unmap_qp:
427 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
428
429err_unmap_dmpt:
430 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
431
432err_unmap_mtt:
433 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
434
435err_unmap_eq:
436 mlx4_unmap_eq_icm(dev);
437
438err_unmap_cmpt:
439 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
440 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
441 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
442 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
443
444err_unmap_aux:
445 mlx4_UNMAP_ICM_AUX(dev);
446
447err_free_aux:
5b0bf5e2 448 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 449
450 return err;
451}
452
453static void mlx4_free_icms(struct mlx4_dev *dev)
454{
455 struct mlx4_priv *priv = mlx4_priv(dev);
456
457 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
458 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
459 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
460 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
461 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
462 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
463 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
464 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
465 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
466 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
467 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
468 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
469 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
470 mlx4_unmap_eq_icm(dev);
471
472 mlx4_UNMAP_ICM_AUX(dev);
5b0bf5e2 473 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 474}
475
476static void mlx4_close_hca(struct mlx4_dev *dev)
477{
478 mlx4_CLOSE_HCA(dev, 0);
479 mlx4_free_icms(dev);
480 mlx4_UNMAP_FA(dev);
5b0bf5e2 481 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
225c7b1f
RD		 482}
483
484static int __devinit mlx4_init_hca(struct mlx4_dev *dev)
485{
486 struct mlx4_priv *priv = mlx4_priv(dev);
487 struct mlx4_adapter adapter;
488 struct mlx4_dev_cap dev_cap;
489 struct mlx4_profile profile;
490 struct mlx4_init_hca_param init_hca;
491 u64 icm_size;
492 int err;
493
494 err = mlx4_QUERY_FW(dev);
495 if (err) {
496 mlx4_err(dev, "QUERY_FW command failed, aborting.\n");
497 return err;
498 }
499
500 err = mlx4_load_fw(dev);
501 if (err) {
502 mlx4_err(dev, "Failed to start FW, aborting.\n");
503 return err;
504 }
505
506 err = mlx4_dev_cap(dev, &dev_cap);
507 if (err) {
508 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
509 goto err_stop_fw;
510 }
511
512 profile = default_profile;
513
514 icm_size = mlx4_make_profile(dev, &profile, &dev_cap, &init_hca);
515 if ((long long) icm_size < 0) {
516 err = icm_size;
517 goto err_stop_fw;
518 }
519
520 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
521
522 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
523 if (err)
524 goto err_stop_fw;
525
526 err = mlx4_INIT_HCA(dev, &init_hca);
527 if (err) {
528 mlx4_err(dev, "INIT_HCA command failed, aborting.\n");
529 goto err_free_icm;
530 }
531
532 err = mlx4_QUERY_ADAPTER(dev, &adapter);
533 if (err) {
534 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n");
535 goto err_close;
536 }
537
538 priv->eq_table.inta_pin = adapter.inta_pin;
cd9281d8
JM		 539 dev->rev_id = adapter.revision_id;
540 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
225c7b1f
RD		 541
542 return 0;
543
544err_close:
545 mlx4_close_hca(dev);
546
547err_free_icm:
548 mlx4_free_icms(dev);
549
550err_stop_fw:
551 mlx4_UNMAP_FA(dev);
5b0bf5e2 552 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
225c7b1f
RD		 553
554 return err;
555}
556
557static int __devinit mlx4_setup_hca(struct mlx4_dev *dev)
558{
559 struct mlx4_priv *priv = mlx4_priv(dev);
560 int err;
561
225c7b1f
RD		 562 err = mlx4_init_uar_table(dev);
563 if (err) {
564 mlx4_err(dev, "Failed to initialize "
565 "user access region table, aborting.\n");
566 return err;
567 }
568
569 err = mlx4_uar_alloc(dev, &priv->driver_uar);
570 if (err) {
571 mlx4_err(dev, "Failed to allocate driver access region, "
572 "aborting.\n");
573 goto err_uar_table_free;
574 }
575
576 priv->kar = ioremap(priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
577 if (!priv->kar) {
578 mlx4_err(dev, "Couldn't map kernel access region, "
579 "aborting.\n");
580 err = -ENOMEM;
581 goto err_uar_free;
582 }
583
584 err = mlx4_init_pd_table(dev);
585 if (err) {
586 mlx4_err(dev, "Failed to initialize "
587 "protection domain table, aborting.\n");
588 goto err_kar_unmap;
589 }
590
591 err = mlx4_init_mr_table(dev);
592 if (err) {
593 mlx4_err(dev, "Failed to initialize "
594 "memory region table, aborting.\n");
595 goto err_pd_table_free;
596 }
597
225c7b1f
RD		 598 err = mlx4_init_eq_table(dev);
599 if (err) {
600 mlx4_err(dev, "Failed to initialize "
601 "event queue table, aborting.\n");
ee49bd93 602 goto err_mr_table_free;
225c7b1f
RD		 603 }
604
605 err = mlx4_cmd_use_events(dev);
606 if (err) {
607 mlx4_err(dev, "Failed to switch to event-driven "
608 "firmware commands, aborting.\n");
609 goto err_eq_table_free;
610 }
611
612 err = mlx4_NOP(dev);
613 if (err) {
08fb1055
MT		 614 if (dev->flags & MLX4_FLAG_MSI_X) {
615 mlx4_warn(dev, "NOP command failed to generate MSI-X "
616 "interrupt IRQ %d).\n",
617 priv->eq_table.eq[MLX4_EQ_ASYNC].irq);
618 mlx4_warn(dev, "Trying again without MSI-X.\n");
619 } else {
620 mlx4_err(dev, "NOP command failed to generate interrupt "
621 "(IRQ %d), aborting.\n",
622 priv->eq_table.eq[MLX4_EQ_ASYNC].irq);
225c7b1f 623 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
08fb1055 624 }
225c7b1f
RD		 625
626 goto err_cmd_poll;
627 }
628
629 mlx4_dbg(dev, "NOP command IRQ test passed\n");
630
631 err = mlx4_init_cq_table(dev);
632 if (err) {
633 mlx4_err(dev, "Failed to initialize "
634 "completion queue table, aborting.\n");
635 goto err_cmd_poll;
636 }
637
638 err = mlx4_init_srq_table(dev);
639 if (err) {
640 mlx4_err(dev, "Failed to initialize "
641 "shared receive queue table, aborting.\n");
642 goto err_cq_table_free;
643 }
644
645 err = mlx4_init_qp_table(dev);
646 if (err) {
647 mlx4_err(dev, "Failed to initialize "
648 "queue pair table, aborting.\n");
649 goto err_srq_table_free;
650 }
651
652 err = mlx4_init_mcg_table(dev);
653 if (err) {
654 mlx4_err(dev, "Failed to initialize "
655 "multicast group table, aborting.\n");
656 goto err_qp_table_free;
657 }
658
659 return 0;
660
661err_qp_table_free:
662 mlx4_cleanup_qp_table(dev);
663
664err_srq_table_free:
665 mlx4_cleanup_srq_table(dev);
666
667err_cq_table_free:
668 mlx4_cleanup_cq_table(dev);
669
670err_cmd_poll:
671 mlx4_cmd_use_polling(dev);
672
673err_eq_table_free:
674 mlx4_cleanup_eq_table(dev);
675
ee49bd93 676err_mr_table_free:
225c7b1f
RD		 677 mlx4_cleanup_mr_table(dev);
678
679err_pd_table_free:
680 mlx4_cleanup_pd_table(dev);
681
682err_kar_unmap:
683 iounmap(priv->kar);
684
685err_uar_free:
686 mlx4_uar_free(dev, &priv->driver_uar);
687
688err_uar_table_free:
689 mlx4_cleanup_uar_table(dev);
690 return err;
691}
692
693static void __devinit mlx4_enable_msi_x(struct mlx4_dev *dev)
694{
695 struct mlx4_priv *priv = mlx4_priv(dev);
696 struct msix_entry entries[MLX4_NUM_EQ];
697 int err;
698 int i;
699
700 if (msi_x) {
701 for (i = 0; i < MLX4_NUM_EQ; ++i)
702 entries[i].entry = i;
703
704 err = pci_enable_msix(dev->pdev, entries, ARRAY_SIZE(entries));
705 if (err) {
706 if (err > 0)
707 mlx4_info(dev, "Only %d MSI-X vectors available, "
708 "not using MSI-X\n", err);
709 goto no_msi;
710 }
711
712 for (i = 0; i < MLX4_NUM_EQ; ++i)
713 priv->eq_table.eq[i].irq = entries[i].vector;
714
715 dev->flags |= MLX4_FLAG_MSI_X;
716 return;
717 }
718
719no_msi:
720 for (i = 0; i < MLX4_NUM_EQ; ++i)
721 priv->eq_table.eq[i].irq = dev->pdev->irq;
722}
723
724static int __devinit mlx4_init_one(struct pci_dev *pdev,
725 const struct pci_device_id *id)
726{
727 static int mlx4_version_printed;
728 struct mlx4_priv *priv;
729 struct mlx4_dev *dev;
730 int err;
731
732 if (!mlx4_version_printed) {
733 printk(KERN_INFO "%s", mlx4_version);
734 ++mlx4_version_printed;
735 }
736
737 printk(KERN_INFO PFX "Initializing %s\n",
738 pci_name(pdev));
739
740 err = pci_enable_device(pdev);
741 if (err) {
742 dev_err(&pdev->dev, "Cannot enable PCI device, "
743 "aborting.\n");
744 return err;
745 }
746
747 /*
748 * Check for BARs. We expect 0: 1MB, 2: 8MB, 4: DDR (may not
749 * be present)
750 */
751 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
752 pci_resource_len(pdev, 0) != 1 << 20) {
753 dev_err(&pdev->dev, "Missing DCS, aborting.\n");
754 err = -ENODEV;
755 goto err_disable_pdev;
756 }
757 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
758 dev_err(&pdev->dev, "Missing UAR, aborting.\n");
759 err = -ENODEV;
760 goto err_disable_pdev;
761 }
762
763 err = pci_request_region(pdev, 0, DRV_NAME);
764 if (err) {
765 dev_err(&pdev->dev, "Cannot request control region, aborting.\n");
766 goto err_disable_pdev;
767 }
768
769 err = pci_request_region(pdev, 2, DRV_NAME);
770 if (err) {
771 dev_err(&pdev->dev, "Cannot request UAR region, aborting.\n");
772 goto err_release_bar0;
773 }
774
775 pci_set_master(pdev);
776
777 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
778 if (err) {
779 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
780 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
781 if (err) {
782 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
783 goto err_release_bar2;
784 }
785 }
786 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
787 if (err) {
788 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
789 "consistent PCI DMA mask.\n");
790 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
791 if (err) {
792 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
793 "aborting.\n");
794 goto err_release_bar2;
795 }
796 }
797
798 priv = kzalloc(sizeof *priv, GFP_KERNEL);
799 if (!priv) {
800 dev_err(&pdev->dev, "Device struct alloc failed, "
801 "aborting.\n");
802 err = -ENOMEM;
803 goto err_release_bar2;
804 }
805
806 dev = &priv->dev;
807 dev->pdev = pdev;
b581401e
RD		 808 INIT_LIST_HEAD(&priv->ctx_list);
809 spin_lock_init(&priv->ctx_lock);
225c7b1f
RD		 810
811 /*
812 * Now reset the HCA before we touch the PCI capabilities or
813 * attempt a firmware command, since a boot ROM may have left
814 * the HCA in an undefined state.
815 */
816 err = mlx4_reset(dev);
817 if (err) {
818 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
819 goto err_free_dev;
820 }
821
225c7b1f
RD		 822 if (mlx4_cmd_init(dev)) {
823 mlx4_err(dev, "Failed to init command interface, aborting.\n");
824 goto err_free_dev;
825 }
826
827 err = mlx4_init_hca(dev);
828 if (err)
829 goto err_cmd;
830
08fb1055
MT		 831 mlx4_enable_msi_x(dev);
832
225c7b1f 833 err = mlx4_setup_hca(dev);
08fb1055
MT		 834 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X)) {
835 dev->flags &= ~MLX4_FLAG_MSI_X;
836 pci_disable_msix(pdev);
837 err = mlx4_setup_hca(dev);
838 }
839
225c7b1f
RD		 840 if (err)
841 goto err_close;
842
843 err = mlx4_register_device(dev);
844 if (err)
845 goto err_cleanup;
846
847 pci_set_drvdata(pdev, dev);
848
849 return 0;
850
851err_cleanup:
852 mlx4_cleanup_mcg_table(dev);
853 mlx4_cleanup_qp_table(dev);
854 mlx4_cleanup_srq_table(dev);
855 mlx4_cleanup_cq_table(dev);
856 mlx4_cmd_use_polling(dev);
857 mlx4_cleanup_eq_table(dev);
225c7b1f
RD		 858 mlx4_cleanup_mr_table(dev);
859 mlx4_cleanup_pd_table(dev);
860 mlx4_cleanup_uar_table(dev);
861
862err_close:
08fb1055
MT		 863 if (dev->flags & MLX4_FLAG_MSI_X)
864 pci_disable_msix(pdev);
865
225c7b1f
RD		 866 mlx4_close_hca(dev);
867
868err_cmd:
869 mlx4_cmd_cleanup(dev);
870
871err_free_dev:
225c7b1f
RD		 872 kfree(priv);
873
874err_release_bar2:
875 pci_release_region(pdev, 2);
876
877err_release_bar0:
878 pci_release_region(pdev, 0);
879
880err_disable_pdev:
881 pci_disable_device(pdev);
882 pci_set_drvdata(pdev, NULL);
883 return err;
884}
885
886static void __devexit mlx4_remove_one(struct pci_dev *pdev)
887{
888 struct mlx4_dev *dev = pci_get_drvdata(pdev);
889 struct mlx4_priv *priv = mlx4_priv(dev);
890 int p;
891
892 if (dev) {
893 mlx4_unregister_device(dev);
894
895 for (p = 1; p <= dev->caps.num_ports; ++p)
896 mlx4_CLOSE_PORT(dev, p);
897
898 mlx4_cleanup_mcg_table(dev);
899 mlx4_cleanup_qp_table(dev);
900 mlx4_cleanup_srq_table(dev);
901 mlx4_cleanup_cq_table(dev);
902 mlx4_cmd_use_polling(dev);
903 mlx4_cleanup_eq_table(dev);
225c7b1f
RD		 904 mlx4_cleanup_mr_table(dev);
905 mlx4_cleanup_pd_table(dev);
906
907 iounmap(priv->kar);
908 mlx4_uar_free(dev, &priv->driver_uar);
909 mlx4_cleanup_uar_table(dev);
910 mlx4_close_hca(dev);
911 mlx4_cmd_cleanup(dev);
912
913 if (dev->flags & MLX4_FLAG_MSI_X)
914 pci_disable_msix(pdev);
915
916 kfree(priv);
917 pci_release_region(pdev, 2);
918 pci_release_region(pdev, 0);
919 pci_disable_device(pdev);
920 pci_set_drvdata(pdev, NULL);
921 }
922}
923
ee49bd93
JM		 924int mlx4_restart_one(struct pci_dev *pdev)
925{
926 mlx4_remove_one(pdev);
927 return mlx4_init_one(pdev, NULL);
928}
929
225c7b1f
RD		 930static struct pci_device_id mlx4_pci_table[] = {
931 { PCI_VDEVICE(MELLANOX, 0x6340) }, /* MT25408 "Hermon" SDR */
932 { PCI_VDEVICE(MELLANOX, 0x634a) }, /* MT25408 "Hermon" DDR */
933 { PCI_VDEVICE(MELLANOX, 0x6354) }, /* MT25408 "Hermon" QDR */
786f238e
JM		 934 { PCI_VDEVICE(MELLANOX, 0x6732) }, /* MT25408 "Hermon" DDR PCIe gen2 */
935 { PCI_VDEVICE(MELLANOX, 0x673c) }, /* MT25408 "Hermon" QDR PCIe gen2 */
225c7b1f
RD		 936 { 0, }
937};
938
939MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
940
941static struct pci_driver mlx4_driver = {
942 .name = DRV_NAME,
943 .id_table = mlx4_pci_table,
944 .probe = mlx4_init_one,
945 .remove = __devexit_p(mlx4_remove_one)
946};
947
948static int __init mlx4_init(void)
949{
950 int ret;
951
ee49bd93
JM		 952 ret = mlx4_catas_init();
953 if (ret)
954 return ret;
955
225c7b1f
RD		 956 ret = pci_register_driver(&mlx4_driver);
957 return ret < 0 ? ret : 0;
958}
959
960static void __exit mlx4_cleanup(void)
961{
962 pci_unregister_driver(&mlx4_driver);
ee49bd93 963 mlx4_catas_cleanup();
225c7b1f
RD		 964}
965
966module_init(mlx4_init);
967module_exit(mlx4_cleanup);
Linux 6.x block layer and io_uring tree(s)